| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.70 | 99.02 | 92.39 | 96.79 | 92.11 | 98.62 | 99.77 | 98.19 |
| T778 | /workspace/coverage/default/37.edn_intr.3621849438 | Jan 14 12:26:17 PM PST 24 | Jan 14 12:26:19 PM PST 24 | 18647874 ps | ||
| T779 | /workspace/coverage/default/5.edn_regwen.2668658052 | Jan 14 12:25:29 PM PST 24 | Jan 14 12:25:35 PM PST 24 | 29714266 ps | ||
| T169 | /workspace/coverage/default/12.edn_disable.2351892828 | Jan 14 12:25:22 PM PST 24 | Jan 14 12:25:25 PM PST 24 | 71906724 ps | ||
| T780 | /workspace/coverage/default/178.edn_genbits.3676019052 | Jan 14 12:26:47 PM PST 24 | Jan 14 12:26:49 PM PST 24 | 54106533 ps | ||
| T278 | /workspace/coverage/default/25.edn_genbits.56527708 | Jan 14 12:25:44 PM PST 24 | Jan 14 12:25:48 PM PST 24 | 25906870 ps | ||
| T781 | /workspace/coverage/default/223.edn_genbits.1885780556 | Jan 14 12:27:01 PM PST 24 | Jan 14 12:27:03 PM PST 24 | 70807843 ps | ||
| T782 | /workspace/coverage/default/22.edn_alert_test.3365872411 | Jan 14 12:25:54 PM PST 24 | Jan 14 12:25:55 PM PST 24 | 31497426 ps | ||
| T783 | /workspace/coverage/default/60.edn_genbits.12114471 | Jan 14 12:26:40 PM PST 24 | Jan 14 12:26:42 PM PST 24 | 193551688 ps | ||
| T784 | /workspace/coverage/default/274.edn_genbits.408040722 | Jan 14 12:27:00 PM PST 24 | Jan 14 12:27:02 PM PST 24 | 39786750 ps | ||
| T785 | /workspace/coverage/default/220.edn_genbits.1668888973 | Jan 14 12:27:03 PM PST 24 | Jan 14 12:27:05 PM PST 24 | 17322477 ps | ||
| T786 | /workspace/coverage/default/252.edn_genbits.2448525961 | Jan 14 12:27:03 PM PST 24 | Jan 14 12:27:05 PM PST 24 | 47178145 ps | ||
| T335 | /workspace/coverage/default/49.edn_alert.3590104820 | Jan 14 12:26:45 PM PST 24 | Jan 14 12:26:47 PM PST 24 | 19882759 ps | ||
| T787 | /workspace/coverage/default/222.edn_genbits.3330519817 | Jan 14 12:27:12 PM PST 24 | Jan 14 12:27:13 PM PST 24 | 19129677 ps | ||
| T788 | /workspace/coverage/default/28.edn_alert.2578738111 | Jan 14 12:26:19 PM PST 24 | Jan 14 12:26:21 PM PST 24 | 172895585 ps | ||
| T789 | /workspace/coverage/default/2.edn_regwen.223551273 | Jan 14 12:25:17 PM PST 24 | Jan 14 12:25:19 PM PST 24 | 14996691 ps | ||
| T790 | /workspace/coverage/default/49.edn_smoke.2862597017 | Jan 14 12:26:34 PM PST 24 | Jan 14 12:26:36 PM PST 24 | 37273412 ps | ||
| T791 | /workspace/coverage/default/166.edn_genbits.513806356 | Jan 14 12:26:53 PM PST 24 | Jan 14 12:26:55 PM PST 24 | 32475046 ps | ||
| T792 | /workspace/coverage/default/4.edn_stress_all.4056612650 | Jan 14 12:25:35 PM PST 24 | Jan 14 12:25:45 PM PST 24 | 327082996 ps | ||
| T793 | /workspace/coverage/default/108.edn_genbits.1163483661 | Jan 14 12:26:38 PM PST 24 | Jan 14 12:26:40 PM PST 24 | 84452623 ps | ||
| T794 | /workspace/coverage/default/49.edn_genbits.2169675487 | Jan 14 12:26:35 PM PST 24 | Jan 14 12:26:37 PM PST 24 | 119536632 ps | ||
| T795 | /workspace/coverage/default/226.edn_genbits.3815501720 | Jan 14 12:26:56 PM PST 24 | Jan 14 12:26:58 PM PST 24 | 24501941 ps | ||
| T796 | /workspace/coverage/default/76.edn_err.1084570910 | Jan 14 12:26:38 PM PST 24 | Jan 14 12:26:39 PM PST 24 | 31479701 ps | ||
| T797 | /workspace/coverage/default/106.edn_genbits.1849036553 | Jan 14 12:27:08 PM PST 24 | Jan 14 12:27:10 PM PST 24 | 24718978 ps | ||
| T798 | /workspace/coverage/default/136.edn_genbits.3521999284 | Jan 14 12:27:01 PM PST 24 | Jan 14 12:27:03 PM PST 24 | 12597788 ps | ||
| T799 | /workspace/coverage/default/13.edn_disable_auto_req_mode.1226572643 | Jan 14 12:25:49 PM PST 24 | Jan 14 12:25:51 PM PST 24 | 73387955 ps | ||
| T800 | /workspace/coverage/default/237.edn_genbits.3544994218 | Jan 14 12:26:54 PM PST 24 | Jan 14 12:26:56 PM PST 24 | 31703777 ps | ||
| T801 | /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3958583616 | Jan 14 12:26:29 PM PST 24 | Jan 14 12:39:35 PM PST 24 | 52445033683 ps | ||
| T203 | /workspace/coverage/default/33.edn_err.3773848219 | Jan 14 12:26:18 PM PST 24 | Jan 14 12:26:20 PM PST 24 | 24082843 ps | ||
| T802 | /workspace/coverage/default/5.edn_alert.1569612820 | Jan 14 12:25:26 PM PST 24 | Jan 14 12:25:31 PM PST 24 | 21979315 ps | ||
| T803 | /workspace/coverage/default/98.edn_err.2809098058 | Jan 14 12:26:53 PM PST 24 | Jan 14 12:26:55 PM PST 24 | 43274934 ps | ||
| T804 | /workspace/coverage/default/66.edn_err.1820670412 | Jan 14 12:27:01 PM PST 24 | Jan 14 12:27:03 PM PST 24 | 57142071 ps | ||
| T805 | /workspace/coverage/default/2.edn_alert.2249504872 | Jan 14 12:25:26 PM PST 24 | Jan 14 12:25:31 PM PST 24 | 26654095 ps | ||
| T806 | /workspace/coverage/default/40.edn_smoke.3479548703 | Jan 14 12:26:22 PM PST 24 | Jan 14 12:26:24 PM PST 24 | 14137452 ps | ||
| T807 | /workspace/coverage/default/100.edn_genbits.1602612305 | Jan 14 12:27:03 PM PST 24 | Jan 14 12:27:07 PM PST 24 | 109749830 ps | ||
| T207 | /workspace/coverage/default/45.edn_err.2881271325 | Jan 14 12:26:50 PM PST 24 | Jan 14 12:26:52 PM PST 24 | 36893759 ps | ||
| T808 | /workspace/coverage/default/50.edn_genbits.831002102 | Jan 14 12:26:33 PM PST 24 | Jan 14 12:26:35 PM PST 24 | 70681832 ps | ||
| T809 | /workspace/coverage/default/7.edn_alert_test.3985343641 | Jan 14 12:25:20 PM PST 24 | Jan 14 12:25:23 PM PST 24 | 71912808 ps | ||
| T810 | /workspace/coverage/default/140.edn_genbits.2795675740 | Jan 14 12:27:01 PM PST 24 | Jan 14 12:27:03 PM PST 24 | 81467221 ps | ||
| T811 | /workspace/coverage/default/120.edn_genbits.1142973139 | Jan 14 12:27:10 PM PST 24 | Jan 14 12:27:12 PM PST 24 | 23631501 ps | ||
| T812 | /workspace/coverage/default/42.edn_smoke.3322232773 | Jan 14 12:26:48 PM PST 24 | Jan 14 12:26:49 PM PST 24 | 23908504 ps | ||
| T813 | /workspace/coverage/default/7.edn_alert.2517491449 | Jan 14 12:25:15 PM PST 24 | Jan 14 12:25:17 PM PST 24 | 64231340 ps | ||
| T814 | /workspace/coverage/default/134.edn_genbits.1833978255 | Jan 14 12:26:55 PM PST 24 | Jan 14 12:26:57 PM PST 24 | 36350678 ps | ||
| T815 | /workspace/coverage/default/22.edn_err.2354295142 | Jan 14 12:25:59 PM PST 24 | Jan 14 12:26:00 PM PST 24 | 28510648 ps | ||
| T816 | /workspace/coverage/default/41.edn_genbits.92930907 | Jan 14 12:26:25 PM PST 24 | Jan 14 12:26:27 PM PST 24 | 33028819 ps | ||
| T817 | /workspace/coverage/default/28.edn_stress_all.1393529164 | Jan 14 12:26:37 PM PST 24 | Jan 14 12:26:39 PM PST 24 | 50329454 ps | ||
| T818 | /workspace/coverage/default/17.edn_smoke.4255363560 | Jan 14 12:25:47 PM PST 24 | Jan 14 12:25:49 PM PST 24 | 16503557 ps | ||
| T160 | /workspace/coverage/default/7.edn_disable.3205503889 | Jan 14 12:25:16 PM PST 24 | Jan 14 12:25:18 PM PST 24 | 14915318 ps | ||
| T819 | /workspace/coverage/default/63.edn_genbits.1622395211 | Jan 14 12:26:52 PM PST 24 | Jan 14 12:26:53 PM PST 24 | 121083326 ps | ||
| T820 | /workspace/coverage/default/131.edn_genbits.290472474 | Jan 14 12:27:01 PM PST 24 | Jan 14 12:27:04 PM PST 24 | 33201157 ps | ||
| T301 | /workspace/coverage/default/55.edn_genbits.1830910556 | Jan 14 12:26:52 PM PST 24 | Jan 14 12:26:54 PM PST 24 | 18471094 ps | ||
| T821 | /workspace/coverage/default/164.edn_genbits.437833295 | Jan 14 12:26:54 PM PST 24 | Jan 14 12:26:56 PM PST 24 | 53531049 ps | ||
| T822 | /workspace/coverage/default/44.edn_disable_auto_req_mode.2336161591 | Jan 14 12:26:45 PM PST 24 | Jan 14 12:26:56 PM PST 24 | 17904902 ps | ||
| T823 | /workspace/coverage/default/254.edn_genbits.2145274447 | Jan 14 12:27:14 PM PST 24 | Jan 14 12:27:15 PM PST 24 | 38631978 ps | ||
| T824 | /workspace/coverage/default/5.edn_alert_test.2764432993 | Jan 14 12:25:32 PM PST 24 | Jan 14 12:25:38 PM PST 24 | 32907018 ps | ||
| T825 | /workspace/coverage/default/28.edn_alert_test.2269621531 | Jan 14 12:26:13 PM PST 24 | Jan 14 12:26:14 PM PST 24 | 14261780 ps | ||
| T826 | /workspace/coverage/default/23.edn_intr.788592454 | Jan 14 12:25:51 PM PST 24 | Jan 14 12:25:53 PM PST 24 | 22501361 ps | ||
| T139 | /workspace/coverage/default/72.edn_err.3304404435 | Jan 14 12:26:48 PM PST 24 | Jan 14 12:26:49 PM PST 24 | 28556260 ps | ||
| T827 | /workspace/coverage/default/53.edn_genbits.1032889905 | Jan 14 12:26:38 PM PST 24 | Jan 14 12:26:41 PM PST 24 | 193060981 ps | ||
| T828 | /workspace/coverage/default/13.edn_stress_all.823288828 | Jan 14 12:25:57 PM PST 24 | Jan 14 12:26:02 PM PST 24 | 159815410 ps | ||
| T829 | /workspace/coverage/default/45.edn_alert.1698878629 | Jan 14 12:26:47 PM PST 24 | Jan 14 12:26:49 PM PST 24 | 37009501 ps | ||
| T830 | /workspace/coverage/default/24.edn_disable.3511038721 | Jan 14 12:25:48 PM PST 24 | Jan 14 12:25:49 PM PST 24 | 29887577 ps | ||
| T831 | /workspace/coverage/default/283.edn_genbits.1740655047 | Jan 14 12:27:20 PM PST 24 | Jan 14 12:27:29 PM PST 24 | 142994391 ps | ||
| T832 | /workspace/coverage/default/215.edn_genbits.548919306 | Jan 14 12:27:09 PM PST 24 | Jan 14 12:27:10 PM PST 24 | 77215732 ps | ||
| T62 | /workspace/coverage/default/4.edn_sec_cm.1573850303 | Jan 14 12:25:14 PM PST 24 | Jan 14 12:25:20 PM PST 24 | 560267356 ps | ||
| T833 | /workspace/coverage/default/16.edn_genbits.4108315782 | Jan 14 12:26:04 PM PST 24 | Jan 14 12:26:05 PM PST 24 | 45863863 ps | ||
| T834 | /workspace/coverage/default/21.edn_smoke.3816894583 | Jan 14 12:26:00 PM PST 24 | Jan 14 12:26:02 PM PST 24 | 12110039 ps | ||
| T835 | /workspace/coverage/default/148.edn_genbits.3606646054 | Jan 14 12:27:14 PM PST 24 | Jan 14 12:27:16 PM PST 24 | 48269157 ps | ||
| T290 | /workspace/coverage/default/146.edn_genbits.696109577 | Jan 14 12:26:58 PM PST 24 | Jan 14 12:27:00 PM PST 24 | 75769939 ps | ||
| T836 | /workspace/coverage/default/262.edn_genbits.161457691 | Jan 14 12:27:05 PM PST 24 | Jan 14 12:27:07 PM PST 24 | 19373025 ps | ||
| T837 | /workspace/coverage/default/24.edn_alert.3470268701 | Jan 14 12:25:59 PM PST 24 | Jan 14 12:26:02 PM PST 24 | 21699690 ps | ||
| T838 | /workspace/coverage/default/14.edn_alert.1116441135 | Jan 14 12:25:54 PM PST 24 | Jan 14 12:25:56 PM PST 24 | 16260351 ps | ||
| T839 | /workspace/coverage/default/19.edn_smoke.1978440346 | Jan 14 12:26:12 PM PST 24 | Jan 14 12:26:14 PM PST 24 | 43584560 ps | ||
| T840 | /workspace/coverage/default/270.edn_genbits.845873320 | Jan 14 12:27:08 PM PST 24 | Jan 14 12:27:10 PM PST 24 | 21357153 ps | ||
| T841 | /workspace/coverage/default/1.edn_genbits.1122136334 | Jan 14 12:25:20 PM PST 24 | Jan 14 12:25:23 PM PST 24 | 45852544 ps | ||
| T842 | /workspace/coverage/default/4.edn_alert.3055325591 | Jan 14 12:25:31 PM PST 24 | Jan 14 12:25:37 PM PST 24 | 32967484 ps | ||
| T843 | /workspace/coverage/default/31.edn_genbits.3505166818 | Jan 14 12:26:17 PM PST 24 | Jan 14 12:26:18 PM PST 24 | 27859002 ps | ||
| T844 | /workspace/coverage/default/71.edn_err.3694004592 | Jan 14 12:26:50 PM PST 24 | Jan 14 12:26:52 PM PST 24 | 36840347 ps | ||
| T845 | /workspace/coverage/default/160.edn_genbits.52356454 | Jan 14 12:26:44 PM PST 24 | Jan 14 12:26:45 PM PST 24 | 55466970 ps | ||
| T846 | /workspace/coverage/default/45.edn_smoke.2653121989 | Jan 14 12:26:47 PM PST 24 | Jan 14 12:26:48 PM PST 24 | 29171028 ps | ||
| T847 | /workspace/coverage/default/40.edn_alert.4083423655 | Jan 14 12:26:21 PM PST 24 | Jan 14 12:26:23 PM PST 24 | 58688748 ps | ||
| T848 | /workspace/coverage/default/231.edn_genbits.1171345558 | Jan 14 12:26:57 PM PST 24 | Jan 14 12:26:59 PM PST 24 | 42261877 ps | ||
| T849 | /workspace/coverage/default/213.edn_genbits.3320542325 | Jan 14 12:26:51 PM PST 24 | Jan 14 12:26:52 PM PST 24 | 63309913 ps | ||
| T850 | /workspace/coverage/default/43.edn_genbits.2954754496 | Jan 14 12:26:31 PM PST 24 | Jan 14 12:26:33 PM PST 24 | 35598986 ps | ||
| T122 | /workspace/coverage/default/4.edn_disable_auto_req_mode.4127858635 | Jan 14 12:25:30 PM PST 24 | Jan 14 12:25:36 PM PST 24 | 90010304 ps | ||
| T851 | /workspace/coverage/default/22.edn_disable.4206713119 | Jan 14 12:25:54 PM PST 24 | Jan 14 12:25:56 PM PST 24 | 29031950 ps | ||
| T852 | /workspace/coverage/default/31.edn_disable_auto_req_mode.3537330510 | Jan 14 12:26:13 PM PST 24 | Jan 14 12:26:21 PM PST 24 | 30314033 ps | ||
| T853 | /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2673329600 | Jan 14 12:25:19 PM PST 24 | Jan 14 12:45:53 PM PST 24 | 96424205257 ps | ||
| T854 | /workspace/coverage/default/16.edn_stress_all.3538979625 | Jan 14 12:25:58 PM PST 24 | Jan 14 12:26:01 PM PST 24 | 163333232 ps | ||
| T855 | /workspace/coverage/default/9.edn_regwen.2927846620 | Jan 14 12:25:19 PM PST 24 | Jan 14 12:25:21 PM PST 24 | 21837235 ps | ||
| T344 | /workspace/coverage/default/8.edn_alert.214552703 | Jan 14 12:25:36 PM PST 24 | Jan 14 12:25:40 PM PST 24 | 33819071 ps | ||
| T856 | /workspace/coverage/default/30.edn_smoke.4049133703 | Jan 14 12:26:07 PM PST 24 | Jan 14 12:26:09 PM PST 24 | 20136472 ps | ||
| T857 | /workspace/coverage/default/165.edn_genbits.4154969017 | Jan 14 12:26:56 PM PST 24 | Jan 14 12:26:59 PM PST 24 | 19729071 ps | ||
| T858 | /workspace/coverage/default/23.edn_genbits.640290072 | Jan 14 12:25:54 PM PST 24 | Jan 14 12:25:56 PM PST 24 | 27461283 ps | ||
| T859 | /workspace/coverage/default/9.edn_genbits.3044426303 | Jan 14 12:25:22 PM PST 24 | Jan 14 12:25:25 PM PST 24 | 70936269 ps | ||
| T860 | /workspace/coverage/default/175.edn_genbits.1004167095 | Jan 14 12:27:10 PM PST 24 | Jan 14 12:27:12 PM PST 24 | 25139689 ps | ||
| T861 | /workspace/coverage/default/211.edn_genbits.3757516289 | Jan 14 12:26:42 PM PST 24 | Jan 14 12:26:43 PM PST 24 | 14818584 ps | ||
| T862 | /workspace/coverage/default/111.edn_genbits.270089408 | Jan 14 12:26:52 PM PST 24 | Jan 14 12:26:53 PM PST 24 | 58894246 ps | ||
| T863 | /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1673094968 | Jan 14 12:25:52 PM PST 24 | Jan 14 12:52:44 PM PST 24 | 67365025146 ps | ||
| T864 | /workspace/coverage/default/247.edn_genbits.1412320482 | Jan 14 12:27:14 PM PST 24 | Jan 14 12:27:15 PM PST 24 | 23540038 ps | ||
| T865 | /workspace/coverage/default/212.edn_genbits.912513660 | Jan 14 12:27:15 PM PST 24 | Jan 14 12:27:18 PM PST 24 | 114269241 ps | ||
| T866 | /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2094851086 | Jan 14 12:25:21 PM PST 24 | Jan 14 12:31:47 PM PST 24 | 27870908645 ps | ||
| T867 | /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1431027555 | Jan 14 12:26:21 PM PST 24 | Jan 14 12:40:48 PM PST 24 | 34120148290 ps | ||
| T868 | /workspace/coverage/default/8.edn_alert_test.719582610 | Jan 14 12:25:48 PM PST 24 | Jan 14 12:25:49 PM PST 24 | 30459825 ps | ||
| T869 | /workspace/coverage/default/3.edn_genbits.2713240519 | Jan 14 12:25:55 PM PST 24 | Jan 14 12:25:58 PM PST 24 | 79550287 ps | ||
| T870 | /workspace/coverage/default/23.edn_alert.455858227 | Jan 14 12:25:56 PM PST 24 | Jan 14 12:25:58 PM PST 24 | 30154698 ps | ||
| T871 | /workspace/coverage/default/46.edn_genbits.3305268741 | Jan 14 12:26:45 PM PST 24 | Jan 14 12:26:47 PM PST 24 | 32743313 ps | ||
| T872 | /workspace/coverage/default/42.edn_alert.1855662543 | Jan 14 12:26:34 PM PST 24 | Jan 14 12:26:36 PM PST 24 | 75638435 ps | ||
| T873 | /workspace/coverage/default/37.edn_disable.3716464701 | Jan 14 12:26:19 PM PST 24 | Jan 14 12:26:21 PM PST 24 | 56907670 ps | ||
| T874 | /workspace/coverage/default/0.edn_err.2956344384 | Jan 14 12:25:22 PM PST 24 | Jan 14 12:25:29 PM PST 24 | 24821177 ps | ||
| T875 | /workspace/coverage/default/183.edn_genbits.1095889729 | Jan 14 12:26:51 PM PST 24 | Jan 14 12:26:52 PM PST 24 | 44239003 ps | ||
| T876 | /workspace/coverage/default/32.edn_disable_auto_req_mode.3223875228 | Jan 14 12:26:19 PM PST 24 | Jan 14 12:26:21 PM PST 24 | 49357805 ps | ||
| T877 | /workspace/coverage/default/18.edn_intr.2707820376 | Jan 14 12:25:57 PM PST 24 | Jan 14 12:26:04 PM PST 24 | 25891237 ps | ||
| T878 | /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2696596839 | Jan 14 12:26:10 PM PST 24 | Jan 14 12:43:41 PM PST 24 | 83780489566 ps | ||
| T879 | /workspace/coverage/default/39.edn_stress_all.1124517799 | Jan 14 12:26:14 PM PST 24 | Jan 14 12:26:18 PM PST 24 | 148186913 ps | ||
| T880 | /workspace/coverage/default/296.edn_genbits.1475244367 | Jan 14 12:27:10 PM PST 24 | Jan 14 12:27:12 PM PST 24 | 94166041 ps | ||
| T881 | /workspace/coverage/default/29.edn_smoke.1707889507 | Jan 14 12:26:28 PM PST 24 | Jan 14 12:26:29 PM PST 24 | 14223092 ps | ||
| T882 | /workspace/coverage/default/33.edn_intr.3795798493 | Jan 14 12:26:17 PM PST 24 | Jan 14 12:26:19 PM PST 24 | 32184241 ps | ||
| T883 | /workspace/coverage/default/126.edn_genbits.4028171077 | Jan 14 12:27:05 PM PST 24 | Jan 14 12:27:09 PM PST 24 | 68630797 ps | ||
| T884 | /workspace/coverage/default/17.edn_stress_all.1205617477 | Jan 14 12:26:05 PM PST 24 | Jan 14 12:26:09 PM PST 24 | 289362879 ps | ||
| T885 | /workspace/coverage/default/3.edn_intr.3360618604 | Jan 14 12:25:24 PM PST 24 | Jan 14 12:25:31 PM PST 24 | 26070488 ps | ||
| T886 | /workspace/coverage/default/23.edn_stress_all.1069024527 | Jan 14 12:25:54 PM PST 24 | Jan 14 12:25:57 PM PST 24 | 316936875 ps | ||
| T887 | /workspace/coverage/default/46.edn_disable.844483773 | Jan 14 12:26:55 PM PST 24 | Jan 14 12:26:57 PM PST 24 | 14005000 ps | ||
| T339 | /workspace/coverage/default/6.edn_regwen.1361145543 | Jan 14 12:25:32 PM PST 24 | Jan 14 12:25:38 PM PST 24 | 15794295 ps | ||
| T888 | /workspace/coverage/default/248.edn_genbits.67012721 | Jan 14 12:27:06 PM PST 24 | Jan 14 12:27:08 PM PST 24 | 15786766 ps | ||
| T889 | /workspace/coverage/default/38.edn_alert_test.3401166578 | Jan 14 12:26:18 PM PST 24 | Jan 14 12:26:20 PM PST 24 | 27482574 ps | ||
| T890 | /workspace/coverage/default/12.edn_alert_test.542919676 | Jan 14 12:25:27 PM PST 24 | Jan 14 12:25:31 PM PST 24 | 58695777 ps | ||
| T891 | /workspace/coverage/default/97.edn_genbits.480652182 | Jan 14 12:27:06 PM PST 24 | Jan 14 12:27:08 PM PST 24 | 76825690 ps | ||
| T892 | /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1062585311 | Jan 14 12:25:15 PM PST 24 | Jan 14 12:49:52 PM PST 24 | 268864305897 ps | ||
| T893 | /workspace/coverage/default/23.edn_disable_auto_req_mode.3030772158 | Jan 14 12:26:09 PM PST 24 | Jan 14 12:26:11 PM PST 24 | 82769165 ps | ||
| T894 | /workspace/coverage/default/34.edn_alert_test.4147593351 | Jan 14 12:26:16 PM PST 24 | Jan 14 12:26:17 PM PST 24 | 22347328 ps | ||
| T895 | /workspace/coverage/default/49.edn_intr.3454873510 | Jan 14 12:26:46 PM PST 24 | Jan 14 12:26:47 PM PST 24 | 25121894 ps | ||
| T896 | /workspace/coverage/default/286.edn_genbits.195481347 | Jan 14 12:27:20 PM PST 24 | Jan 14 12:27:26 PM PST 24 | 30604435 ps | ||
| T897 | /workspace/coverage/default/34.edn_intr.482441299 | Jan 14 12:26:13 PM PST 24 | Jan 14 12:26:15 PM PST 24 | 22554086 ps | ||
| T898 | /workspace/coverage/default/32.edn_genbits.4277038819 | Jan 14 12:26:24 PM PST 24 | Jan 14 12:26:25 PM PST 24 | 25653978 ps | ||
| T899 | /workspace/coverage/default/263.edn_genbits.252578999 | Jan 14 12:27:17 PM PST 24 | Jan 14 12:27:19 PM PST 24 | 42201528 ps | ||
| T900 | /workspace/coverage/default/30.edn_alert_test.1386143971 | Jan 14 12:26:10 PM PST 24 | Jan 14 12:26:11 PM PST 24 | 22011985 ps | ||
| T901 | /workspace/coverage/default/219.edn_genbits.69094045 | Jan 14 12:26:56 PM PST 24 | Jan 14 12:27:03 PM PST 24 | 41572840 ps | ||
| T902 | /workspace/coverage/default/29.edn_disable_auto_req_mode.3482114660 | Jan 14 12:26:20 PM PST 24 | Jan 14 12:26:23 PM PST 24 | 65090126 ps | ||
| T123 | /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3597567209 | Jan 14 12:25:54 PM PST 24 | Jan 14 12:26:28 PM PST 24 | 5437419173 ps | ||
| T903 | /workspace/coverage/default/1.edn_err.1117915433 | Jan 14 12:25:55 PM PST 24 | Jan 14 12:25:58 PM PST 24 | 29165994 ps | ||
| T904 | /workspace/coverage/default/152.edn_genbits.1999930133 | Jan 14 12:26:44 PM PST 24 | Jan 14 12:26:46 PM PST 24 | 80286255 ps | ||
| T905 | /workspace/coverage/default/150.edn_genbits.1019884900 | Jan 14 12:27:04 PM PST 24 | Jan 14 12:27:06 PM PST 24 | 58795096 ps | ||
| T906 | /workspace/coverage/default/196.edn_genbits.2568138691 | Jan 14 12:26:52 PM PST 24 | Jan 14 12:26:53 PM PST 24 | 33950651 ps | ||
| T907 | /workspace/coverage/default/67.edn_genbits.973019909 | Jan 14 12:26:40 PM PST 24 | Jan 14 12:26:42 PM PST 24 | 17921496 ps | ||
| T908 | /workspace/coverage/default/39.edn_genbits.2565774383 | Jan 14 12:26:43 PM PST 24 | Jan 14 12:26:44 PM PST 24 | 17563505 ps | ||
| T909 | /workspace/coverage/default/66.edn_genbits.3412852106 | Jan 14 12:27:04 PM PST 24 | Jan 14 12:27:11 PM PST 24 | 55933350 ps | ||
| T910 | /workspace/coverage/default/32.edn_smoke.1748326022 | Jan 14 12:26:22 PM PST 24 | Jan 14 12:26:23 PM PST 24 | 13828341 ps | ||
| T911 | /workspace/coverage/default/5.edn_stress_all.1697958197 | Jan 14 12:25:13 PM PST 24 | Jan 14 12:25:16 PM PST 24 | 142703656 ps | ||
| T912 | /workspace/coverage/default/265.edn_genbits.890479511 | Jan 14 12:27:01 PM PST 24 | Jan 14 12:27:03 PM PST 24 | 79207278 ps | ||
| T913 | /workspace/coverage/default/44.edn_intr.3917251804 | Jan 14 12:26:18 PM PST 24 | Jan 14 12:26:20 PM PST 24 | 17583892 ps | ||
| T914 | /workspace/coverage/default/130.edn_genbits.702993068 | Jan 14 12:26:47 PM PST 24 | Jan 14 12:26:49 PM PST 24 | 24878902 ps | ||
| T915 | /workspace/coverage/default/22.edn_alert.90505544 | Jan 14 12:26:12 PM PST 24 | Jan 14 12:26:14 PM PST 24 | 213236368 ps | ||
| T130 | /workspace/coverage/default/64.edn_err.2990042876 | Jan 14 12:26:48 PM PST 24 | Jan 14 12:26:50 PM PST 24 | 22321325 ps | ||
| T916 | /workspace/coverage/default/18.edn_stress_all.1258803447 | Jan 14 12:26:02 PM PST 24 | Jan 14 12:26:06 PM PST 24 | 97598267 ps | ||
| T97 | /workspace/coverage/default/21.edn_intr.4040316640 | Jan 14 12:26:01 PM PST 24 | Jan 14 12:26:03 PM PST 24 | 19855119 ps | ||
| T917 | /workspace/coverage/default/14.edn_intr.574558249 | Jan 14 12:25:25 PM PST 24 | Jan 14 12:25:31 PM PST 24 | 44714211 ps | ||
| T918 | /workspace/coverage/default/24.edn_disable_auto_req_mode.548433021 | Jan 14 12:25:50 PM PST 24 | Jan 14 12:25:52 PM PST 24 | 20569867 ps | ||
| T153 | /workspace/coverage/default/30.edn_disable.1141746578 | Jan 14 12:26:10 PM PST 24 | Jan 14 12:26:12 PM PST 24 | 24523598 ps | ||
| T919 | /workspace/coverage/default/1.edn_disable_auto_req_mode.3472856146 | Jan 14 12:25:17 PM PST 24 | Jan 14 12:25:20 PM PST 24 | 41332564 ps | ||
| T920 | /workspace/coverage/default/43.edn_alert_test.2336647922 | Jan 14 12:26:22 PM PST 24 | Jan 14 12:26:24 PM PST 24 | 19963440 ps | ||
| T114 | /workspace/coverage/default/38.edn_intr.3255567895 | Jan 14 12:26:12 PM PST 24 | Jan 14 12:26:13 PM PST 24 | 39077327 ps | ||
| T921 | /workspace/coverage/default/240.edn_genbits.3234117439 | Jan 14 12:26:47 PM PST 24 | Jan 14 12:26:49 PM PST 24 | 114817592 ps | ||
| T922 | /workspace/coverage/default/119.edn_genbits.3111576480 | Jan 14 12:26:59 PM PST 24 | Jan 14 12:27:01 PM PST 24 | 205970027 ps | ||
| T313 | /workspace/coverage/default/227.edn_genbits.3545301150 | Jan 14 12:27:14 PM PST 24 | Jan 14 12:27:15 PM PST 24 | 114784901 ps | ||
| T923 | /workspace/coverage/default/53.edn_err.3453680593 | Jan 14 12:26:45 PM PST 24 | Jan 14 12:26:47 PM PST 24 | 18678076 ps | ||
| T924 | /workspace/coverage/default/293.edn_genbits.153217224 | Jan 14 12:27:05 PM PST 24 | Jan 14 12:27:07 PM PST 24 | 53175717 ps | ||
| T925 | /workspace/coverage/default/21.edn_alert.1411136298 | Jan 14 12:25:57 PM PST 24 | Jan 14 12:25:58 PM PST 24 | 58455348 ps | ||
| T926 | /workspace/coverage/default/0.edn_genbits.3546010313 | Jan 14 12:25:36 PM PST 24 | Jan 14 12:25:40 PM PST 24 | 49483789 ps | ||
| T927 | /workspace/coverage/default/233.edn_genbits.2409553216 | Jan 14 12:27:07 PM PST 24 | Jan 14 12:27:10 PM PST 24 | 47253405 ps | ||
| T928 | /workspace/coverage/default/24.edn_genbits.350200471 | Jan 14 12:25:57 PM PST 24 | Jan 14 12:26:00 PM PST 24 | 52332541 ps | ||
| T929 | /workspace/coverage/default/14.edn_alert_test.3383621647 | Jan 14 12:25:43 PM PST 24 | Jan 14 12:25:45 PM PST 24 | 16947356 ps | ||
| T930 | /workspace/coverage/default/40.edn_disable.1283573861 | Jan 14 12:26:30 PM PST 24 | Jan 14 12:26:31 PM PST 24 | 13706109 ps | ||
| T931 | /workspace/coverage/default/170.edn_genbits.1458945626 | Jan 14 12:26:54 PM PST 24 | Jan 14 12:26:56 PM PST 24 | 85499076 ps | ||
| T932 | /workspace/coverage/default/103.edn_genbits.3217268462 | Jan 14 12:26:51 PM PST 24 | Jan 14 12:26:53 PM PST 24 | 41513923 ps | ||
| T208 | /workspace/coverage/default/59.edn_err.167675843 | Jan 14 12:26:54 PM PST 24 | Jan 14 12:26:56 PM PST 24 | 172487136 ps | ||
| T933 | /workspace/coverage/default/25.edn_alert_test.2177526528 | Jan 14 12:25:58 PM PST 24 | Jan 14 12:25:59 PM PST 24 | 18121222 ps | ||
| T934 | /workspace/coverage/default/26.edn_disable.1555168368 | Jan 14 12:25:56 PM PST 24 | Jan 14 12:25:58 PM PST 24 | 73227183 ps | ||
| T935 | /workspace/coverage/default/42.edn_alert_test.2905273626 | Jan 14 12:26:23 PM PST 24 | Jan 14 12:26:25 PM PST 24 | 14794698 ps | ||
| T936 | /workspace/coverage/default/32.edn_alert_test.3122096386 | Jan 14 12:26:18 PM PST 24 | Jan 14 12:26:21 PM PST 24 | 89429084 ps | ||
| T937 | /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2720388846 | Jan 14 12:25:43 PM PST 24 | Jan 14 12:34:33 PM PST 24 | 23157249259 ps | ||
| T938 | /workspace/coverage/default/298.edn_genbits.1592225637 | Jan 14 12:26:59 PM PST 24 | Jan 14 12:27:01 PM PST 24 | 177033559 ps | ||
| T115 | /workspace/coverage/default/24.edn_intr.3173726017 | Jan 14 12:26:00 PM PST 24 | Jan 14 12:26:02 PM PST 24 | 38441631 ps | ||
| T939 | /workspace/coverage/default/57.edn_err.3168676885 | Jan 14 12:26:53 PM PST 24 | Jan 14 12:26:54 PM PST 24 | 61334056 ps | ||
| T940 | /workspace/coverage/default/28.edn_genbits.2824602941 | Jan 14 12:26:20 PM PST 24 | Jan 14 12:26:21 PM PST 24 | 17462989 ps | ||
| T941 | /workspace/coverage/default/257.edn_genbits.2567007595 | Jan 14 12:26:57 PM PST 24 | Jan 14 12:26:59 PM PST 24 | 20410122 ps | ||
| T942 | /workspace/coverage/default/193.edn_genbits.826785835 | Jan 14 12:26:57 PM PST 24 | Jan 14 12:26:59 PM PST 24 | 19555234 ps | ||
| T943 | /workspace/coverage/default/264.edn_genbits.221137283 | Jan 14 12:27:05 PM PST 24 | Jan 14 12:27:07 PM PST 24 | 25065219 ps | ||
| T944 | /workspace/coverage/default/18.edn_disable.1609827262 | Jan 14 12:26:05 PM PST 24 | Jan 14 12:26:06 PM PST 24 | 40883569 ps | ||
| T945 | /workspace/coverage/default/6.edn_stress_all.4288692400 | Jan 14 12:25:26 PM PST 24 | Jan 14 12:25:32 PM PST 24 | 145834510 ps | ||
| T946 | /workspace/coverage/default/26.edn_intr.1294256727 | Jan 14 12:26:05 PM PST 24 | Jan 14 12:26:07 PM PST 24 | 36163314 ps | ||
| T947 | /workspace/coverage/default/291.edn_genbits.4044281481 | Jan 14 12:27:09 PM PST 24 | Jan 14 12:27:10 PM PST 24 | 15027863 ps | ||
| T161 | /workspace/coverage/default/16.edn_disable.1958101279 | Jan 14 12:25:57 PM PST 24 | Jan 14 12:25:59 PM PST 24 | 26799844 ps | ||
| T948 | /workspace/coverage/default/115.edn_genbits.1082320101 | Jan 14 12:26:44 PM PST 24 | Jan 14 12:26:46 PM PST 24 | 28901651 ps | ||
| T949 | /workspace/coverage/default/20.edn_alert_test.2504373262 | Jan 14 12:25:52 PM PST 24 | Jan 14 12:25:54 PM PST 24 | 49871708 ps | ||
| T950 | /workspace/coverage/default/54.edn_genbits.4067164442 | Jan 14 12:26:47 PM PST 24 | Jan 14 12:26:49 PM PST 24 | 41091529 ps | ||
| T951 | /workspace/coverage/default/74.edn_genbits.2016952139 | Jan 14 12:26:34 PM PST 24 | Jan 14 12:26:36 PM PST 24 | 31681020 ps | ||
| T952 | /workspace/coverage/default/3.edn_smoke.3501935619 | Jan 14 12:25:19 PM PST 24 | Jan 14 12:25:21 PM PST 24 | 15891809 ps | ||
| T165 | /workspace/coverage/default/20.edn_disable.1624644027 | Jan 14 12:26:09 PM PST 24 | Jan 14 12:26:10 PM PST 24 | 12601406 ps | ||
| T953 | /workspace/coverage/default/191.edn_genbits.2850640249 | Jan 14 12:26:53 PM PST 24 | Jan 14 12:26:55 PM PST 24 | 15136377 ps | ||
| T340 | /workspace/coverage/default/12.edn_alert.3602139526 | Jan 14 12:25:35 PM PST 24 | Jan 14 12:25:40 PM PST 24 | 17447177 ps | ||
| T954 | /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1376776199 | Jan 14 12:25:22 PM PST 24 | Jan 14 12:34:58 PM PST 24 | 44380153812 ps | ||
| T955 | /workspace/coverage/default/21.edn_err.2145463609 | Jan 14 12:25:55 PM PST 24 | Jan 14 12:25:57 PM PST 24 | 40836275 ps | ||
| T956 | /workspace/coverage/default/250.edn_genbits.1178269085 | Jan 14 12:26:57 PM PST 24 | Jan 14 12:27:00 PM PST 24 | 24699628 ps | ||
| T957 | /workspace/coverage/default/133.edn_genbits.1045829912 | Jan 14 12:26:59 PM PST 24 | Jan 14 12:27:01 PM PST 24 | 23650495 ps | ||
| T958 | /workspace/coverage/default/69.edn_genbits.2585072938 | Jan 14 12:26:48 PM PST 24 | Jan 14 12:26:50 PM PST 24 | 38375127 ps | ||
| T959 | /workspace/coverage/default/197.edn_genbits.387689648 | Jan 14 12:27:05 PM PST 24 | Jan 14 12:27:06 PM PST 24 | 22324713 ps | ||
| T960 | /workspace/coverage/default/210.edn_genbits.760789010 | Jan 14 12:27:09 PM PST 24 | Jan 14 12:27:11 PM PST 24 | 33110264 ps | ||
| T961 | /workspace/coverage/default/78.edn_err.970790970 | Jan 14 12:26:56 PM PST 24 | Jan 14 12:26:59 PM PST 24 | 18170056 ps | ||
| T962 | /workspace/coverage/default/26.edn_stress_all.95772788 | Jan 14 12:25:59 PM PST 24 | Jan 14 12:26:02 PM PST 24 | 297875806 ps | ||
| T963 | /workspace/coverage/default/26.edn_genbits.1330712796 | Jan 14 12:26:02 PM PST 24 | Jan 14 12:26:05 PM PST 24 | 15909935 ps | ||
| T218 | /workspace/coverage/default/67.edn_err.2000816296 | Jan 14 12:26:54 PM PST 24 | Jan 14 12:26:55 PM PST 24 | 18903623 ps | ||
| T964 | /workspace/coverage/default/189.edn_genbits.1793735504 | Jan 14 12:27:02 PM PST 24 | Jan 14 12:27:05 PM PST 24 | 25273786 ps | ||
| T965 | /workspace/coverage/default/19.edn_err.209166460 | Jan 14 12:25:57 PM PST 24 | Jan 14 12:25:58 PM PST 24 | 108667310 ps | ||
| T279 | /workspace/coverage/default/181.edn_genbits.2558336236 | Jan 14 12:26:44 PM PST 24 | Jan 14 12:26:46 PM PST 24 | 70262737 ps | ||
| T966 | /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1050342621 | Jan 14 12:26:25 PM PST 24 | Jan 14 12:56:47 PM PST 24 | 121288239052 ps | ||
| T967 | /workspace/coverage/default/10.edn_disable.1320643396 | Jan 14 12:25:37 PM PST 24 | Jan 14 12:25:43 PM PST 24 | 14772793 ps | ||
| T223 | /workspace/coverage/default/13.edn_err.2527835233 | Jan 14 12:25:27 PM PST 24 | Jan 14 12:25:32 PM PST 24 | 33507296 ps | ||
| T968 | /workspace/coverage/default/47.edn_disable_auto_req_mode.1339911741 | Jan 14 12:26:48 PM PST 24 | Jan 14 12:26:50 PM PST 24 | 15417069 ps | ||
| T969 | /workspace/coverage/default/217.edn_genbits.1486036189 | Jan 14 12:26:55 PM PST 24 | Jan 14 12:26:57 PM PST 24 | 27453999 ps | ||
| T970 | /workspace/coverage/default/49.edn_disable_auto_req_mode.656856283 | Jan 14 12:26:28 PM PST 24 | Jan 14 12:26:29 PM PST 24 | 79782920 ps | ||
| T971 | /workspace/coverage/default/154.edn_genbits.335595057 | Jan 14 12:26:48 PM PST 24 | Jan 14 12:26:50 PM PST 24 | 43262410 ps | ||
| T972 | /workspace/coverage/default/179.edn_genbits.1404507488 | Jan 14 12:26:47 PM PST 24 | Jan 14 12:26:49 PM PST 24 | 88123968 ps | ||
| T973 | /workspace/coverage/default/105.edn_genbits.2822200055 | Jan 14 12:26:55 PM PST 24 | Jan 14 12:26:57 PM PST 24 | 24786204 ps | ||
| T974 | /workspace/coverage/default/18.edn_smoke.3941652838 | Jan 14 12:26:07 PM PST 24 | Jan 14 12:26:08 PM PST 24 | 17363157 ps | ||
| T975 | /workspace/coverage/default/89.edn_err.433160641 | Jan 14 12:27:02 PM PST 24 | Jan 14 12:27:05 PM PST 24 | 96600924 ps | ||
| T976 | /workspace/coverage/default/4.edn_alert_test.741089087 | Jan 14 12:25:31 PM PST 24 | Jan 14 12:25:37 PM PST 24 | 15708334 ps |
| Test location | /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3839596129 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 68594670369 ps |
| CPU time | 1355.77 seconds |
| Started | Jan 14 12:26:11 PM PST 24 |
| Finished | Jan 14 12:48:48 PM PST 24 |
| Peak memory | 216068 kb |
| Host | smart-05dbabef-e2c2-4a46-b2e5-cd08b4649a51 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839596129 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3839596129 |
| Directory | /workspace/33.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.edn_genbits.3392077226 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 75160169 ps |
| CPU time | 1.06 seconds |
| Started | Jan 14 12:26:02 PM PST 24 |
| Finished | Jan 14 12:26:05 PM PST 24 |
| Peak memory | 205956 kb |
| Host | smart-9ce54fe0-57be-48ba-b471-1c65e1f4f849 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3392077226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3392077226 |
| Directory | /workspace/20.edn_genbits/latest |
| Test location | /workspace/coverage/default/101.edn_genbits.1321827468 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 161593883 ps |
| CPU time | 3.02 seconds |
| Started | Jan 14 12:27:15 PM PST 24 |
| Finished | Jan 14 12:27:19 PM PST 24 |
| Peak memory | 214076 kb |
| Host | smart-aa3f4c5a-45f8-4070-8ebf-5b387de4c8f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1321827468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1321827468 |
| Directory | /workspace/101.edn_genbits/latest |
| Test location | /workspace/coverage/default/35.edn_err.4003930989 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 30487678 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 12:26:19 PM PST 24 |
| Finished | Jan 14 12:26:21 PM PST 24 |
| Peak memory | 215740 kb |
| Host | smart-86450e4a-df67-4dd3-84a2-8f8cc945dec6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4003930989 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.4003930989 |
| Directory | /workspace/35.edn_err/latest |
| Test location | /workspace/coverage/default/2.edn_sec_cm.2024083399 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1105659414 ps |
| CPU time | 15.53 seconds |
| Started | Jan 14 12:25:34 PM PST 24 |
| Finished | Jan 14 12:25:53 PM PST 24 |
| Peak memory | 235156 kb |
| Host | smart-910eb298-8e99-4f06-8149-9b306bebbbef |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024083399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2024083399 |
| Directory | /workspace/2.edn_sec_cm/latest |
| Test location | /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1795525554 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 49868002 ps |
| CPU time | 1.62 seconds |
| Started | Jan 14 12:24:56 PM PST 24 |
| Finished | Jan 14 12:24:59 PM PST 24 |
| Peak memory | 205964 kb |
| Host | smart-804a7c45-2e01-4474-8339-c332b722fdb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795525554 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1795525554 |
| Directory | /workspace/14.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.edn_disable_auto_req_mode.2116043844 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 25145337 ps |
| CPU time | 1.04 seconds |
| Started | Jan 14 12:25:15 PM PST 24 |
| Finished | Jan 14 12:25:16 PM PST 24 |
| Peak memory | 214360 kb |
| Host | smart-cb5fea2a-5f94-474f-a3a8-4d7c5c100fa3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116043844 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di sable_auto_req_mode.2116043844 |
| Directory | /workspace/0.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/87.edn_err.173746156 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 33920980 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:26:54 PM PST 24 |
| Finished | Jan 14 12:26:56 PM PST 24 |
| Peak memory | 221728 kb |
| Host | smart-14cbe6d5-d50f-4e7e-a290-296902a7a67e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=173746156 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.173746156 |
| Directory | /workspace/87.edn_err/latest |
| Test location | /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1613800314 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 446154702662 ps |
| CPU time | 1928.77 seconds |
| Started | Jan 14 12:25:54 PM PST 24 |
| Finished | Jan 14 12:58:04 PM PST 24 |
| Peak memory | 223196 kb |
| Host | smart-147861af-28a2-4066-80c8-a8ff4662829f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613800314 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1613800314 |
| Directory | /workspace/26.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.edn_alert.3270953315 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 19849481 ps |
| CPU time | 1.06 seconds |
| Started | Jan 14 12:25:18 PM PST 24 |
| Finished | Jan 14 12:25:21 PM PST 24 |
| Peak memory | 205828 kb |
| Host | smart-31e83186-8976-4457-b823-43669c50d113 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3270953315 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3270953315 |
| Directory | /workspace/6.edn_alert/latest |
| Test location | /workspace/coverage/default/14.edn_disable_auto_req_mode.2868828363 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 150350070 ps |
| CPU time | 1.01 seconds |
| Started | Jan 14 12:26:03 PM PST 24 |
| Finished | Jan 14 12:26:05 PM PST 24 |
| Peak memory | 214456 kb |
| Host | smart-90dd438e-6d53-48a8-aa7a-8281c3181d5f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868828363 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d isable_auto_req_mode.2868828363 |
| Directory | /workspace/14.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/11.edn_intr.265581926 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 19021127 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:25:26 PM PST 24 |
| Finished | Jan 14 12:25:31 PM PST 24 |
| Peak memory | 214372 kb |
| Host | smart-22aeb7bb-b52c-4d8f-a12c-e6f18df1194f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=265581926 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.265581926 |
| Directory | /workspace/11.edn_intr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1651931192 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 18805677 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:24:46 PM PST 24 |
| Finished | Jan 14 12:24:47 PM PST 24 |
| Peak memory | 205920 kb |
| Host | smart-51e04241-813b-43eb-b14b-a8d68e8ac2ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651931192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1651931192 |
| Directory | /workspace/1.edn_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/35.edn_disable.3344801762 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 36049487 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:26:25 PM PST 24 |
| Finished | Jan 14 12:26:26 PM PST 24 |
| Peak memory | 214464 kb |
| Host | smart-69df81ee-f3fc-4964-b6a1-3bd852eb4703 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344801762 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3344801762 |
| Directory | /workspace/35.edn_disable/latest |
| Test location | /workspace/coverage/default/15.edn_disable_auto_req_mode.2796223576 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 30135385 ps |
| CPU time | 1 seconds |
| Started | Jan 14 12:25:40 PM PST 24 |
| Finished | Jan 14 12:25:45 PM PST 24 |
| Peak memory | 214284 kb |
| Host | smart-c93c627d-1a0f-42a4-8737-80e4391c8064 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796223576 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d isable_auto_req_mode.2796223576 |
| Directory | /workspace/15.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/35.edn_genbits.3451805398 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 57380188 ps |
| CPU time | 1.15 seconds |
| Started | Jan 14 12:26:47 PM PST 24 |
| Finished | Jan 14 12:26:49 PM PST 24 |
| Peak memory | 214120 kb |
| Host | smart-14c3d9ca-af9d-482f-b7e0-067c65518da6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3451805398 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3451805398 |
| Directory | /workspace/35.edn_genbits/latest |
| Test location | /workspace/coverage/default/0.edn_disable.3817635712 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 12260301 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:25:15 PM PST 24 |
| Finished | Jan 14 12:25:17 PM PST 24 |
| Peak memory | 214156 kb |
| Host | smart-81930538-e017-487b-b08e-9671aad6b370 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817635712 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3817635712 |
| Directory | /workspace/0.edn_disable/latest |
| Test location | /workspace/coverage/default/3.edn_disable.2935767449 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 13125169 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:25:15 PM PST 24 |
| Finished | Jan 14 12:25:21 PM PST 24 |
| Peak memory | 214292 kb |
| Host | smart-f48bc1e0-cc00-4426-9aac-8f7b42dda74b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935767449 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.2935767449 |
| Directory | /workspace/3.edn_disable/latest |
| Test location | /workspace/coverage/default/0.edn_regwen.131598932 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 15837623 ps |
| CPU time | 1 seconds |
| Started | Jan 14 12:25:33 PM PST 24 |
| Finished | Jan 14 12:25:38 PM PST 24 |
| Peak memory | 204764 kb |
| Host | smart-f86e5404-bfcc-42f6-8853-d95de10124a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=131598932 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.131598932 |
| Directory | /workspace/0.edn_regwen/latest |
| Test location | /workspace/coverage/default/18.edn_disable.1609827262 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 40883569 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:26:05 PM PST 24 |
| Finished | Jan 14 12:26:06 PM PST 24 |
| Peak memory | 214180 kb |
| Host | smart-3f15ca1a-15d5-4288-9d1c-09446bac15da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609827262 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1609827262 |
| Directory | /workspace/18.edn_disable/latest |
| Test location | /workspace/coverage/default/9.edn_intr.3406391463 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 23851971 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:25:34 PM PST 24 |
| Finished | Jan 14 12:25:38 PM PST 24 |
| Peak memory | 225412 kb |
| Host | smart-be6db33f-1b95-4bb5-be9e-7ea3b82ca83d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3406391463 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3406391463 |
| Directory | /workspace/9.edn_intr/latest |
| Test location | /workspace/coverage/default/137.edn_genbits.3456476122 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 58918316 ps |
| CPU time | 1.18 seconds |
| Started | Jan 14 12:27:05 PM PST 24 |
| Finished | Jan 14 12:27:07 PM PST 24 |
| Peak memory | 214016 kb |
| Host | smart-2dcaa908-e09d-4b61-a9eb-1c1693325dd2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3456476122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.3456476122 |
| Directory | /workspace/137.edn_genbits/latest |
| Test location | /workspace/coverage/default/143.edn_genbits.2255756342 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 111324223 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:26:57 PM PST 24 |
| Finished | Jan 14 12:26:59 PM PST 24 |
| Peak memory | 205132 kb |
| Host | smart-9b7b933a-1168-4041-8e15-e9b2334ae0ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2255756342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2255756342 |
| Directory | /workspace/143.edn_genbits/latest |
| Test location | /workspace/coverage/default/40.edn_disable_auto_req_mode.2190281723 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 26630559 ps |
| CPU time | 1.01 seconds |
| Started | Jan 14 12:26:22 PM PST 24 |
| Finished | Jan 14 12:26:24 PM PST 24 |
| Peak memory | 214484 kb |
| Host | smart-d2b1cee5-3c54-47cf-b780-4d35635c48b4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190281723 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d isable_auto_req_mode.2190281723 |
| Directory | /workspace/40.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/16.edn_intr.368492699 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 18806268 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:26:09 PM PST 24 |
| Finished | Jan 14 12:26:16 PM PST 24 |
| Peak memory | 214180 kb |
| Host | smart-f3537445-2813-47b6-8cbf-19bf424c15f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=368492699 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.368492699 |
| Directory | /workspace/16.edn_intr/latest |
| Test location | /workspace/coverage/default/7.edn_disable_auto_req_mode.3657332954 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 25632112 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:25:16 PM PST 24 |
| Finished | Jan 14 12:25:19 PM PST 24 |
| Peak memory | 214288 kb |
| Host | smart-1cc62a43-b349-42bf-b079-19c9557b5774 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657332954 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di sable_auto_req_mode.3657332954 |
| Directory | /workspace/7.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/27.edn_genbits.3085185988 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 48936000 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:26:22 PM PST 24 |
| Finished | Jan 14 12:26:24 PM PST 24 |
| Peak memory | 205520 kb |
| Host | smart-d011179b-bc96-46e4-be05-e626528c2834 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3085185988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3085185988 |
| Directory | /workspace/27.edn_genbits/latest |
| Test location | /workspace/coverage/default/1.edn_disable.3672438470 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 18821737 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:25:21 PM PST 24 |
| Finished | Jan 14 12:25:24 PM PST 24 |
| Peak memory | 214208 kb |
| Host | smart-ca58874e-4c8c-49da-93ec-a9801cf12a86 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672438470 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3672438470 |
| Directory | /workspace/1.edn_disable/latest |
| Test location | /workspace/coverage/default/4.edn_disable.160126180 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 18419695 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:25:21 PM PST 24 |
| Finished | Jan 14 12:25:24 PM PST 24 |
| Peak memory | 214172 kb |
| Host | smart-8137ec8c-39dd-46f8-aca1-f4ee9f509168 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160126180 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.160126180 |
| Directory | /workspace/4.edn_disable/latest |
| Test location | /workspace/coverage/default/29.edn_alert.1829595238 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 40720960 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:26:10 PM PST 24 |
| Finished | Jan 14 12:26:12 PM PST 24 |
| Peak memory | 205212 kb |
| Host | smart-8da536cc-4f37-4c2e-9a1f-083141a013e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1829595238 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1829595238 |
| Directory | /workspace/29.edn_alert/latest |
| Test location | /workspace/coverage/default/1.edn_disable_auto_req_mode.3472856146 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 41332564 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:25:17 PM PST 24 |
| Finished | Jan 14 12:25:20 PM PST 24 |
| Peak memory | 214292 kb |
| Host | smart-7def45d6-c7e8-4e4f-a9cc-e25e591990a4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472856146 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di sable_auto_req_mode.3472856146 |
| Directory | /workspace/1.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/10.edn_disable.1320643396 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 14772793 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:25:37 PM PST 24 |
| Finished | Jan 14 12:25:43 PM PST 24 |
| Peak memory | 214248 kb |
| Host | smart-3578d043-f9e9-410e-b523-47b56f83a643 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320643396 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1320643396 |
| Directory | /workspace/10.edn_disable/latest |
| Test location | /workspace/coverage/default/14.edn_err.507392480 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 28878334 ps |
| CPU time | 1.21 seconds |
| Started | Jan 14 12:25:47 PM PST 24 |
| Finished | Jan 14 12:25:50 PM PST 24 |
| Peak memory | 216744 kb |
| Host | smart-6af8e7a3-a658-4d87-bc67-8b4fa51e6b89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=507392480 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.507392480 |
| Directory | /workspace/14.edn_err/latest |
| Test location | /workspace/coverage/default/22.edn_disable_auto_req_mode.2477904788 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 118663018 ps |
| CPU time | 1.08 seconds |
| Started | Jan 14 12:26:34 PM PST 24 |
| Finished | Jan 14 12:26:36 PM PST 24 |
| Peak memory | 214400 kb |
| Host | smart-1f457dae-22c4-4c14-bdf9-c2746592b6d7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477904788 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d isable_auto_req_mode.2477904788 |
| Directory | /workspace/22.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/23.edn_disable.4266052193 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 12569061 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:26:05 PM PST 24 |
| Finished | Jan 14 12:26:06 PM PST 24 |
| Peak memory | 214348 kb |
| Host | smart-9f5e2fdc-1b6b-4abb-9100-a24f926c35e8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266052193 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.4266052193 |
| Directory | /workspace/23.edn_disable/latest |
| Test location | /workspace/coverage/default/9.edn_regwen.2927846620 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 21837235 ps |
| CPU time | 0.84 seconds |
| Started | Jan 14 12:25:19 PM PST 24 |
| Finished | Jan 14 12:25:21 PM PST 24 |
| Peak memory | 204712 kb |
| Host | smart-0be35c95-c136-4806-9d72-92e4dd50ccc3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2927846620 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2927846620 |
| Directory | /workspace/9.edn_regwen/latest |
| Test location | /workspace/coverage/default/17.edn_alert.1061634491 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 18260396 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:25:57 PM PST 24 |
| Finished | Jan 14 12:25:58 PM PST 24 |
| Peak memory | 206012 kb |
| Host | smart-50f1013d-819c-4e8d-b76d-3367e61b90ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1061634491 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1061634491 |
| Directory | /workspace/17.edn_alert/latest |
| Test location | /workspace/coverage/default/31.edn_alert.3607087187 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 59122523 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:26:11 PM PST 24 |
| Finished | Jan 14 12:26:12 PM PST 24 |
| Peak memory | 205824 kb |
| Host | smart-7ab2a2d7-b5d8-4564-9a9a-e861c13d898c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3607087187 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3607087187 |
| Directory | /workspace/31.edn_alert/latest |
| Test location | /workspace/coverage/default/25.edn_genbits.56527708 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 25906870 ps |
| CPU time | 1.14 seconds |
| Started | Jan 14 12:25:44 PM PST 24 |
| Finished | Jan 14 12:25:48 PM PST 24 |
| Peak memory | 214096 kb |
| Host | smart-c7cd4b21-240a-4fbb-a3af-782d6376009d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56527708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.56527708 |
| Directory | /workspace/25.edn_genbits/latest |
| Test location | /workspace/coverage/default/110.edn_genbits.1106285377 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 41561082 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:27:05 PM PST 24 |
| Finished | Jan 14 12:27:07 PM PST 24 |
| Peak memory | 205008 kb |
| Host | smart-fc29eb83-c830-4ad9-9bf7-be430afcd307 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1106285377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1106285377 |
| Directory | /workspace/110.edn_genbits/latest |
| Test location | /workspace/coverage/default/21.edn_genbits.1489076079 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 93660933 ps |
| CPU time | 1.04 seconds |
| Started | Jan 14 12:26:26 PM PST 24 |
| Finished | Jan 14 12:26:27 PM PST 24 |
| Peak memory | 205420 kb |
| Host | smart-1df490f6-7a95-48bf-b277-5115e7e6b220 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1489076079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1489076079 |
| Directory | /workspace/21.edn_genbits/latest |
| Test location | /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1851543977 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 89608810283 ps |
| CPU time | 984.77 seconds |
| Started | Jan 14 12:25:50 PM PST 24 |
| Finished | Jan 14 12:42:15 PM PST 24 |
| Peak memory | 216056 kb |
| Host | smart-3e5387be-8d48-4d66-aeee-dfce61559998 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851543977 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1851543977 |
| Directory | /workspace/14.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.edn_genbits.2482804072 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 56121701 ps |
| CPU time | 2.15 seconds |
| Started | Jan 14 12:25:54 PM PST 24 |
| Finished | Jan 14 12:25:57 PM PST 24 |
| Peak memory | 214072 kb |
| Host | smart-e85b5c49-2191-4e83-bcfb-22748175c2f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2482804072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2482804072 |
| Directory | /workspace/17.edn_genbits/latest |
| Test location | /workspace/coverage/default/221.edn_genbits.1974628550 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 15520612 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:26:50 PM PST 24 |
| Finished | Jan 14 12:26:52 PM PST 24 |
| Peak memory | 205228 kb |
| Host | smart-847becb8-6cbe-4670-b616-c575e601b27f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1974628550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1974628550 |
| Directory | /workspace/221.edn_genbits/latest |
| Test location | /workspace/coverage/default/224.edn_genbits.2259891146 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 24092679 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:26:53 PM PST 24 |
| Finished | Jan 14 12:26:55 PM PST 24 |
| Peak memory | 204724 kb |
| Host | smart-76c98756-6165-40aa-a40f-b28e9a825251 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2259891146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2259891146 |
| Directory | /workspace/224.edn_genbits/latest |
| Test location | /workspace/coverage/default/237.edn_genbits.3544994218 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 31703777 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:54 PM PST 24 |
| Finished | Jan 14 12:26:56 PM PST 24 |
| Peak memory | 205384 kb |
| Host | smart-9715a644-454c-43b7-b6d7-b374cfd9f73c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3544994218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3544994218 |
| Directory | /workspace/237.edn_genbits/latest |
| Test location | /workspace/coverage/default/261.edn_genbits.1594997846 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 35314335 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:26:55 PM PST 24 |
| Finished | Jan 14 12:26:57 PM PST 24 |
| Peak memory | 205156 kb |
| Host | smart-3cbe722e-abb6-4af9-98fb-6ee168ef8b8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1594997846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1594997846 |
| Directory | /workspace/261.edn_genbits/latest |
| Test location | /workspace/coverage/default/10.edn_alert_test.2915026858 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 12095558 ps |
| CPU time | 0.8 seconds |
| Started | Jan 14 12:25:18 PM PST 24 |
| Finished | Jan 14 12:25:20 PM PST 24 |
| Peak memory | 204160 kb |
| Host | smart-dd9a652b-c3da-4e8f-bc49-b71346964c69 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915026858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2915026858 |
| Directory | /workspace/10.edn_alert_test/latest |
| Test location | /workspace/coverage/default/28.edn_intr.2329250989 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 23333696 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:18 PM PST 24 |
| Finished | Jan 14 12:26:19 PM PST 24 |
| Peak memory | 214424 kb |
| Host | smart-c51f7605-6790-4a76-882d-24a48f245dad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2329250989 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2329250989 |
| Directory | /workspace/28.edn_intr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3315261122 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 20325597 ps |
| CPU time | 1.22 seconds |
| Started | Jan 14 12:24:49 PM PST 24 |
| Finished | Jan 14 12:24:51 PM PST 24 |
| Peak memory | 206000 kb |
| Host | smart-80341f17-8cb2-4cfd-998d-fb348e8ef102 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315261122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3315261122 |
| Directory | /workspace/0.edn_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.90525564 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 52178205 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:24:43 PM PST 24 |
| Finished | Jan 14 12:24:45 PM PST 24 |
| Peak memory | 205932 kb |
| Host | smart-bee0f4f2-257c-432d-a379-0a3bedf7fe4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90525564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outs tanding.90525564 |
| Directory | /workspace/0.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/13.edn_intr.2539756143 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 22477622 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:25:53 PM PST 24 |
| Finished | Jan 14 12:25:55 PM PST 24 |
| Peak memory | 214416 kb |
| Host | smart-3e028dc3-9419-4353-aa4d-467c05981330 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2539756143 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2539756143 |
| Directory | /workspace/13.edn_intr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2668476347 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 122298937 ps |
| CPU time | 2.01 seconds |
| Started | Jan 14 12:25:11 PM PST 24 |
| Finished | Jan 14 12:25:14 PM PST 24 |
| Peak memory | 205932 kb |
| Host | smart-569335e3-1e81-4a85-8159-88163b5b62fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668476347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2668476347 |
| Directory | /workspace/15.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/default/1.edn_regwen.2980043281 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 12771623 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:25:45 PM PST 24 |
| Finished | Jan 14 12:25:49 PM PST 24 |
| Peak memory | 205028 kb |
| Host | smart-f62c9417-60ce-4f1c-b348-7c563546a0e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2980043281 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2980043281 |
| Directory | /workspace/1.edn_regwen/latest |
| Test location | /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1694499335 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 51978263360 ps |
| CPU time | 991.89 seconds |
| Started | Jan 14 12:25:34 PM PST 24 |
| Finished | Jan 14 12:42:09 PM PST 24 |
| Peak memory | 215388 kb |
| Host | smart-12ee9cf6-e895-4458-b89e-55cd68c19252 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694499335 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1694499335 |
| Directory | /workspace/1.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/109.edn_genbits.1287812960 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 155971455 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:27:05 PM PST 24 |
| Finished | Jan 14 12:27:07 PM PST 24 |
| Peak memory | 205480 kb |
| Host | smart-c4e29e7e-b88a-49db-af9d-7504b733ada8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1287812960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1287812960 |
| Directory | /workspace/109.edn_genbits/latest |
| Test location | /workspace/coverage/default/118.edn_genbits.1623179819 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 299166016 ps |
| CPU time | 3.9 seconds |
| Started | Jan 14 12:27:05 PM PST 24 |
| Finished | Jan 14 12:27:10 PM PST 24 |
| Peak memory | 214020 kb |
| Host | smart-fb5f707a-772b-4ba2-a794-30db11f8a341 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623179819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1623179819 |
| Directory | /workspace/118.edn_genbits/latest |
| Test location | /workspace/coverage/default/144.edn_genbits.2552810448 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 31606736 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:59 PM PST 24 |
| Finished | Jan 14 12:27:01 PM PST 24 |
| Peak memory | 205104 kb |
| Host | smart-86813c52-1d9a-4275-be8c-f701f244affc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2552810448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2552810448 |
| Directory | /workspace/144.edn_genbits/latest |
| Test location | /workspace/coverage/default/16.edn_genbits.4108315782 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 45863863 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:26:04 PM PST 24 |
| Finished | Jan 14 12:26:05 PM PST 24 |
| Peak memory | 204956 kb |
| Host | smart-0b453160-994e-445f-9b19-6ee58278e914 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4108315782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.4108315782 |
| Directory | /workspace/16.edn_genbits/latest |
| Test location | /workspace/coverage/default/163.edn_genbits.1505602445 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 44302448 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:26:55 PM PST 24 |
| Finished | Jan 14 12:26:57 PM PST 24 |
| Peak memory | 205452 kb |
| Host | smart-9279fbef-bb26-466a-8288-17a74df00121 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1505602445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1505602445 |
| Directory | /workspace/163.edn_genbits/latest |
| Test location | /workspace/coverage/default/168.edn_genbits.2884785792 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 18827228 ps |
| CPU time | 1.04 seconds |
| Started | Jan 14 12:26:56 PM PST 24 |
| Finished | Jan 14 12:26:58 PM PST 24 |
| Peak memory | 205060 kb |
| Host | smart-0681cba0-e702-493d-9e4a-276192366d82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2884785792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2884785792 |
| Directory | /workspace/168.edn_genbits/latest |
| Test location | /workspace/coverage/default/19.edn_alert.3745443042 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 21664864 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:25:52 PM PST 24 |
| Finished | Jan 14 12:25:54 PM PST 24 |
| Peak memory | 205020 kb |
| Host | smart-ebf1109e-04cd-4a57-99b5-71e47933288f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3745443042 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.3745443042 |
| Directory | /workspace/19.edn_alert/latest |
| Test location | /workspace/coverage/default/227.edn_genbits.3545301150 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 114784901 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:27:14 PM PST 24 |
| Finished | Jan 14 12:27:15 PM PST 24 |
| Peak memory | 205188 kb |
| Host | smart-89c07dee-96d0-45c0-9a22-b08b62280e73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3545301150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3545301150 |
| Directory | /workspace/227.edn_genbits/latest |
| Test location | /workspace/coverage/default/3.edn_alert.1150843749 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 22103207 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:25:15 PM PST 24 |
| Finished | Jan 14 12:25:17 PM PST 24 |
| Peak memory | 205020 kb |
| Host | smart-9f10f690-cb6d-40a6-ae7f-24dd89331d70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150843749 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1150843749 |
| Directory | /workspace/3.edn_alert/latest |
| Test location | /workspace/coverage/default/16.edn_disable.1958101279 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 26799844 ps |
| CPU time | 0.78 seconds |
| Started | Jan 14 12:25:57 PM PST 24 |
| Finished | Jan 14 12:25:59 PM PST 24 |
| Peak memory | 214192 kb |
| Host | smart-80923a38-9272-49b1-b533-be1782da403e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958101279 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.1958101279 |
| Directory | /workspace/16.edn_disable/latest |
| Test location | /workspace/coverage/default/20.edn_disable.1624644027 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 12601406 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:26:09 PM PST 24 |
| Finished | Jan 14 12:26:10 PM PST 24 |
| Peak memory | 214332 kb |
| Host | smart-021d1477-ee1c-41bd-9d9c-62a4f02159fe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624644027 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1624644027 |
| Directory | /workspace/20.edn_disable/latest |
| Test location | /workspace/coverage/default/39.edn_disable_auto_req_mode.812033610 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 29063079 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:26:17 PM PST 24 |
| Finished | Jan 14 12:26:18 PM PST 24 |
| Peak memory | 206152 kb |
| Host | smart-76e7fa71-1d21-4e4b-827f-fd2fc233b953 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812033610 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di sable_auto_req_mode.812033610 |
| Directory | /workspace/39.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/113.edn_genbits.1072614261 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 29080234 ps |
| CPU time | 1.26 seconds |
| Started | Jan 14 12:27:04 PM PST 24 |
| Finished | Jan 14 12:27:06 PM PST 24 |
| Peak memory | 214032 kb |
| Host | smart-cbce679a-3ef6-4739-8aab-77c5378e94d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1072614261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1072614261 |
| Directory | /workspace/113.edn_genbits/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.296859436 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 99266593 ps |
| CPU time | 3.07 seconds |
| Started | Jan 14 12:24:59 PM PST 24 |
| Finished | Jan 14 12:25:07 PM PST 24 |
| Peak memory | 205928 kb |
| Host | smart-1792ef7e-aeda-4e80-979e-08495256d498 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296859436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.296859436 |
| Directory | /workspace/0.edn_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.475440879 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 20043695 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:25:02 PM PST 24 |
| Finished | Jan 14 12:25:08 PM PST 24 |
| Peak memory | 205920 kb |
| Host | smart-6ae21895-c73e-431a-81b5-7cd30346e27d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475440879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.475440879 |
| Directory | /workspace/0.edn_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2635877154 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 28261750 ps |
| CPU time | 1.39 seconds |
| Started | Jan 14 12:24:48 PM PST 24 |
| Finished | Jan 14 12:24:50 PM PST 24 |
| Peak memory | 214240 kb |
| Host | smart-4b834c60-3ef1-4529-bc13-ceb0d9576222 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635877154 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2635877154 |
| Directory | /workspace/0.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_csr_rw.2314136458 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 13818716 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:24:53 PM PST 24 |
| Finished | Jan 14 12:24:54 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-3c8dd85e-46e3-49e6-afa7-faa0d51a87de |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314136458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2314136458 |
| Directory | /workspace/0.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_intr_test.3011925839 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 13920856 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:24:55 PM PST 24 |
| Finished | Jan 14 12:24:57 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-5041138a-c7be-446f-b4e9-92e9b37e192e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011925839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3011925839 |
| Directory | /workspace/0.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_tl_errors.2870462614 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 114753280 ps |
| CPU time | 2.03 seconds |
| Started | Jan 14 12:24:50 PM PST 24 |
| Finished | Jan 14 12:24:53 PM PST 24 |
| Peak memory | 222384 kb |
| Host | smart-a00274d5-49ca-4923-8e59-e04bb637ef08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870462614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2870462614 |
| Directory | /workspace/0.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1781233683 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 89306206 ps |
| CPU time | 1.48 seconds |
| Started | Jan 14 12:24:46 PM PST 24 |
| Finished | Jan 14 12:24:48 PM PST 24 |
| Peak memory | 205924 kb |
| Host | smart-5d27f216-8d25-4a48-a5e5-2f1be0bd5a97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781233683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1781233683 |
| Directory | /workspace/0.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.4133226407 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 75487216 ps |
| CPU time | 1.05 seconds |
| Started | Jan 14 12:24:51 PM PST 24 |
| Finished | Jan 14 12:24:52 PM PST 24 |
| Peak memory | 206048 kb |
| Host | smart-a85f1498-9005-4c87-8171-164b350045e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133226407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.4133226407 |
| Directory | /workspace/1.edn_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3757326174 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 997265218 ps |
| CPU time | 6.32 seconds |
| Started | Jan 14 12:24:46 PM PST 24 |
| Finished | Jan 14 12:24:53 PM PST 24 |
| Peak memory | 205932 kb |
| Host | smart-b710a0d9-30fa-4643-9908-9133dfc6e9e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757326174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3757326174 |
| Directory | /workspace/1.edn_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2524038902 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 73780805 ps |
| CPU time | 1.08 seconds |
| Started | Jan 14 12:24:39 PM PST 24 |
| Finished | Jan 14 12:24:41 PM PST 24 |
| Peak memory | 211612 kb |
| Host | smart-6afb2d42-3f0f-4a53-94a5-e245d922060d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524038902 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2524038902 |
| Directory | /workspace/1.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_csr_rw.3969062121 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 44759223 ps |
| CPU time | 0.77 seconds |
| Started | Jan 14 12:24:53 PM PST 24 |
| Finished | Jan 14 12:24:54 PM PST 24 |
| Peak memory | 205744 kb |
| Host | smart-10dff4c8-71ab-4f44-a320-65a46fd9321a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969062121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3969062121 |
| Directory | /workspace/1.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_intr_test.3583203566 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 54998539 ps |
| CPU time | 0.77 seconds |
| Started | Jan 14 12:24:44 PM PST 24 |
| Finished | Jan 14 12:24:45 PM PST 24 |
| Peak memory | 205728 kb |
| Host | smart-19e108be-1206-4248-8529-ea47db33221d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583203566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3583203566 |
| Directory | /workspace/1.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.374792060 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 21453118 ps |
| CPU time | 0.87 seconds |
| Started | Jan 14 12:24:55 PM PST 24 |
| Finished | Jan 14 12:25:05 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-a269a006-f897-40eb-b603-15b50a0fb00f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374792060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out standing.374792060 |
| Directory | /workspace/1.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_tl_errors.2863526481 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 76626648 ps |
| CPU time | 2.54 seconds |
| Started | Jan 14 12:24:59 PM PST 24 |
| Finished | Jan 14 12:25:06 PM PST 24 |
| Peak memory | 214272 kb |
| Host | smart-7169f17d-ad25-4c45-8bd0-f44dca1cdd1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863526481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2863526481 |
| Directory | /workspace/1.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.4073915681 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 153244929 ps |
| CPU time | 1.45 seconds |
| Started | Jan 14 12:24:59 PM PST 24 |
| Finished | Jan 14 12:25:06 PM PST 24 |
| Peak memory | 206020 kb |
| Host | smart-86391460-dafa-4212-8b9a-f95c51cd44d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073915681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.4073915681 |
| Directory | /workspace/1.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3428701585 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 75597802 ps |
| CPU time | 1.21 seconds |
| Started | Jan 14 12:25:00 PM PST 24 |
| Finished | Jan 14 12:25:05 PM PST 24 |
| Peak memory | 222420 kb |
| Host | smart-ea89aaa1-03c8-4dae-a73d-656d02114dfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428701585 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3428701585 |
| Directory | /workspace/10.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.edn_csr_rw.1116926217 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 51072028 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:24:43 PM PST 24 |
| Finished | Jan 14 12:24:44 PM PST 24 |
| Peak memory | 205368 kb |
| Host | smart-6b3b2129-917f-42eb-ba32-d9280e4a9b84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116926217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1116926217 |
| Directory | /workspace/10.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.edn_intr_test.1623352369 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 26914825 ps |
| CPU time | 0.8 seconds |
| Started | Jan 14 12:25:03 PM PST 24 |
| Finished | Jan 14 12:25:08 PM PST 24 |
| Peak memory | 205952 kb |
| Host | smart-af1f2865-6c24-4333-9574-7cda4551eff0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623352369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1623352369 |
| Directory | /workspace/10.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1287620686 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 145290175 ps |
| CPU time | 1.49 seconds |
| Started | Jan 14 12:24:51 PM PST 24 |
| Finished | Jan 14 12:24:53 PM PST 24 |
| Peak memory | 206112 kb |
| Host | smart-4bdd42a9-1c40-4296-b3a3-01754c19fac9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287620686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o utstanding.1287620686 |
| Directory | /workspace/10.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.edn_tl_errors.151763421 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 107092786 ps |
| CPU time | 2.53 seconds |
| Started | Jan 14 12:25:01 PM PST 24 |
| Finished | Jan 14 12:25:07 PM PST 24 |
| Peak memory | 214276 kb |
| Host | smart-0856e96f-2995-445b-886f-0f4f8128fa68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151763421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.151763421 |
| Directory | /workspace/10.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1128270563 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 70936284 ps |
| CPU time | 2.09 seconds |
| Started | Jan 14 12:24:42 PM PST 24 |
| Finished | Jan 14 12:24:44 PM PST 24 |
| Peak memory | 205944 kb |
| Host | smart-25410fae-a043-46a2-9b04-353e34c61268 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128270563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1128270563 |
| Directory | /workspace/10.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.1185474038 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 19093252 ps |
| CPU time | 1.19 seconds |
| Started | Jan 14 12:24:54 PM PST 24 |
| Finished | Jan 14 12:24:56 PM PST 24 |
| Peak memory | 214208 kb |
| Host | smart-2e06c05e-03c6-40f1-8e4b-e771540fa050 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185474038 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.1185474038 |
| Directory | /workspace/11.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.edn_csr_rw.347592553 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 155372620 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:24:54 PM PST 24 |
| Finished | Jan 14 12:24:55 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-6dbcf8df-22d3-4421-b14b-322e8283706b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347592553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.347592553 |
| Directory | /workspace/11.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.edn_intr_test.2887910644 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 187324425 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:25:02 PM PST 24 |
| Finished | Jan 14 12:25:06 PM PST 24 |
| Peak memory | 205728 kb |
| Host | smart-e82e5be0-dc29-4496-bad8-c695b977cdc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887910644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2887910644 |
| Directory | /workspace/11.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.4059468425 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 20026864 ps |
| CPU time | 1.01 seconds |
| Started | Jan 14 12:24:52 PM PST 24 |
| Finished | Jan 14 12:24:53 PM PST 24 |
| Peak memory | 205912 kb |
| Host | smart-2e51dd20-a06b-4c4f-a54f-8327bddd50da |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059468425 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o utstanding.4059468425 |
| Directory | /workspace/11.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.edn_tl_errors.3791231569 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 138919764 ps |
| CPU time | 2.43 seconds |
| Started | Jan 14 12:25:10 PM PST 24 |
| Finished | Jan 14 12:25:14 PM PST 24 |
| Peak memory | 214212 kb |
| Host | smart-2b168e79-62b6-447f-b987-4ee8eb916b81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791231569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3791231569 |
| Directory | /workspace/11.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1553847545 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 47957819 ps |
| CPU time | 1.56 seconds |
| Started | Jan 14 12:25:18 PM PST 24 |
| Finished | Jan 14 12:25:21 PM PST 24 |
| Peak memory | 206036 kb |
| Host | smart-50969c13-f3fb-49fb-bd92-2d1289c74f0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553847545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1553847545 |
| Directory | /workspace/11.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.341106981 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 41199026 ps |
| CPU time | 1.42 seconds |
| Started | Jan 14 12:25:00 PM PST 24 |
| Finished | Jan 14 12:25:06 PM PST 24 |
| Peak memory | 214204 kb |
| Host | smart-5c09f0d7-1850-41e3-a3ab-729d28e80f76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341106981 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.341106981 |
| Directory | /workspace/12.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.edn_csr_rw.31540940 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 22969728 ps |
| CPU time | 0.87 seconds |
| Started | Jan 14 12:25:03 PM PST 24 |
| Finished | Jan 14 12:25:08 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-fb5abd8e-5bd6-47db-9d71-d9789c43493d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31540940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.31540940 |
| Directory | /workspace/12.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.edn_intr_test.702681284 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 12255807 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:25:05 PM PST 24 |
| Finished | Jan 14 12:25:09 PM PST 24 |
| Peak memory | 205908 kb |
| Host | smart-c8919a48-34a8-4c31-87d0-0e538679e20b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702681284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.702681284 |
| Directory | /workspace/12.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1860117603 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 69984796 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:25:10 PM PST 24 |
| Finished | Jan 14 12:25:12 PM PST 24 |
| Peak memory | 205988 kb |
| Host | smart-3f7dbab4-747f-4209-b0d1-78f1120114fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860117603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o utstanding.1860117603 |
| Directory | /workspace/12.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.edn_tl_errors.1081854954 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 152609396 ps |
| CPU time | 2.49 seconds |
| Started | Jan 14 12:25:02 PM PST 24 |
| Finished | Jan 14 12:25:10 PM PST 24 |
| Peak memory | 214264 kb |
| Host | smart-2b905def-1699-4acf-b82d-e1c6faab89e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081854954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1081854954 |
| Directory | /workspace/12.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3387664967 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 249137034 ps |
| CPU time | 1.45 seconds |
| Started | Jan 14 12:25:03 PM PST 24 |
| Finished | Jan 14 12:25:09 PM PST 24 |
| Peak memory | 205980 kb |
| Host | smart-00213208-4dae-4214-a0e5-a2221ed0ad31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387664967 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3387664967 |
| Directory | /workspace/12.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2456634524 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 72434760 ps |
| CPU time | 1.2 seconds |
| Started | Jan 14 12:25:11 PM PST 24 |
| Finished | Jan 14 12:25:13 PM PST 24 |
| Peak memory | 214340 kb |
| Host | smart-00a846fb-b2dd-4391-8d54-0a19ff98104c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456634524 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2456634524 |
| Directory | /workspace/13.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.edn_csr_rw.1457318500 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 37523260 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:25:27 PM PST 24 |
| Finished | Jan 14 12:25:31 PM PST 24 |
| Peak memory | 205980 kb |
| Host | smart-a41962b1-1b6f-4553-8cba-af55061cb8ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457318500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1457318500 |
| Directory | /workspace/13.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.edn_intr_test.1262152095 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 182899132 ps |
| CPU time | 0.87 seconds |
| Started | Jan 14 12:25:14 PM PST 24 |
| Finished | Jan 14 12:25:15 PM PST 24 |
| Peak memory | 205712 kb |
| Host | smart-ebe6a538-d418-4491-ac89-c94d6cc4e913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262152095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1262152095 |
| Directory | /workspace/13.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2278543295 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 14014804 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:24:57 PM PST 24 |
| Finished | Jan 14 12:25:05 PM PST 24 |
| Peak memory | 206120 kb |
| Host | smart-a9c9699c-436d-43ce-8a97-d2a8af4c1621 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278543295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o utstanding.2278543295 |
| Directory | /workspace/13.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.edn_tl_errors.1546522714 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 382749813 ps |
| CPU time | 2.06 seconds |
| Started | Jan 14 12:24:48 PM PST 24 |
| Finished | Jan 14 12:24:51 PM PST 24 |
| Peak memory | 214348 kb |
| Host | smart-4d3e4f81-cc61-492c-aabb-d362f1f959ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546522714 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1546522714 |
| Directory | /workspace/13.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2347696543 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 197345117 ps |
| CPU time | 1.52 seconds |
| Started | Jan 14 12:24:52 PM PST 24 |
| Finished | Jan 14 12:24:54 PM PST 24 |
| Peak memory | 205992 kb |
| Host | smart-d3747bc6-60c3-47e6-9c4a-e942ba79cb00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347696543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2347696543 |
| Directory | /workspace/13.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1134609950 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 88100296 ps |
| CPU time | 1.04 seconds |
| Started | Jan 14 12:25:16 PM PST 24 |
| Finished | Jan 14 12:25:21 PM PST 24 |
| Peak memory | 214240 kb |
| Host | smart-f1b56b3d-9e5c-4ed1-bbec-5e6fe6e58bf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134609950 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1134609950 |
| Directory | /workspace/14.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.edn_csr_rw.794953999 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 29491112 ps |
| CPU time | 0.76 seconds |
| Started | Jan 14 12:25:12 PM PST 24 |
| Finished | Jan 14 12:25:13 PM PST 24 |
| Peak memory | 205668 kb |
| Host | smart-6f73f4e5-fa3f-47d8-ad75-087a70a93407 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794953999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.794953999 |
| Directory | /workspace/14.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.edn_intr_test.826667239 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 42088495 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:24:52 PM PST 24 |
| Finished | Jan 14 12:24:53 PM PST 24 |
| Peak memory | 205956 kb |
| Host | smart-5e9b575d-12bb-4ba6-b9ef-7c5a101b005c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826667239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.826667239 |
| Directory | /workspace/14.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.439088860 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 34890412 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:25:04 PM PST 24 |
| Finished | Jan 14 12:25:09 PM PST 24 |
| Peak memory | 205924 kb |
| Host | smart-9029eeee-4b20-417f-b10d-e8311060fda8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439088860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou tstanding.439088860 |
| Directory | /workspace/14.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.edn_tl_errors.1945716363 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 80444383 ps |
| CPU time | 1.6 seconds |
| Started | Jan 14 12:24:52 PM PST 24 |
| Finished | Jan 14 12:24:54 PM PST 24 |
| Peak memory | 214188 kb |
| Host | smart-cf7fd0e7-7c6a-4f93-bf66-f329896719fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945716363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1945716363 |
| Directory | /workspace/14.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.3161677104 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 59876820 ps |
| CPU time | 1.52 seconds |
| Started | Jan 14 12:25:02 PM PST 24 |
| Finished | Jan 14 12:25:08 PM PST 24 |
| Peak memory | 214220 kb |
| Host | smart-3d201154-846e-4d83-80d3-e55676ff0dc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161677104 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.3161677104 |
| Directory | /workspace/15.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.edn_csr_rw.1361707154 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 20109339 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:24:51 PM PST 24 |
| Finished | Jan 14 12:24:53 PM PST 24 |
| Peak memory | 206084 kb |
| Host | smart-b3308d5d-9454-4241-a4e1-5e1424f20614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361707154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1361707154 |
| Directory | /workspace/15.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.edn_intr_test.1616228079 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 15784859 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:25:05 PM PST 24 |
| Finished | Jan 14 12:25:09 PM PST 24 |
| Peak memory | 205956 kb |
| Host | smart-b584c1a2-7aae-4290-b84c-9d3649479591 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616228079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1616228079 |
| Directory | /workspace/15.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2812818444 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 94720984 ps |
| CPU time | 1.05 seconds |
| Started | Jan 14 12:25:04 PM PST 24 |
| Finished | Jan 14 12:25:09 PM PST 24 |
| Peak memory | 205980 kb |
| Host | smart-50942dcb-4559-45e5-86cd-4e05e2bb9c3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812818444 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o utstanding.2812818444 |
| Directory | /workspace/15.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.edn_tl_errors.2450628221 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 195218951 ps |
| CPU time | 1.9 seconds |
| Started | Jan 14 12:25:00 PM PST 24 |
| Finished | Jan 14 12:25:06 PM PST 24 |
| Peak memory | 214244 kb |
| Host | smart-e58f890b-788d-4364-b97f-91d7b9c5c928 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450628221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2450628221 |
| Directory | /workspace/15.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3313886702 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 28932286 ps |
| CPU time | 1.14 seconds |
| Started | Jan 14 12:24:46 PM PST 24 |
| Finished | Jan 14 12:24:48 PM PST 24 |
| Peak memory | 214284 kb |
| Host | smart-5aca49b8-9501-4763-9e31-74375d693bb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313886702 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3313886702 |
| Directory | /workspace/16.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.edn_csr_rw.627665733 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 31421990 ps |
| CPU time | 0.77 seconds |
| Started | Jan 14 12:25:07 PM PST 24 |
| Finished | Jan 14 12:25:10 PM PST 24 |
| Peak memory | 205736 kb |
| Host | smart-c878d30a-4248-4fe3-a46c-608a7daa6560 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627665733 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.627665733 |
| Directory | /workspace/16.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.edn_intr_test.298374395 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 39406377 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 12:25:03 PM PST 24 |
| Finished | Jan 14 12:25:08 PM PST 24 |
| Peak memory | 205716 kb |
| Host | smart-e63a52e9-d71b-4c24-a5a0-5bd1f3b17bbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298374395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.298374395 |
| Directory | /workspace/16.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2644000867 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 76812182 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:25:06 PM PST 24 |
| Finished | Jan 14 12:25:10 PM PST 24 |
| Peak memory | 205952 kb |
| Host | smart-ffb0f576-3144-4186-868b-760e0b589c7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644000867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o utstanding.2644000867 |
| Directory | /workspace/16.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.edn_tl_errors.3338040411 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 397650313 ps |
| CPU time | 2.74 seconds |
| Started | Jan 14 12:25:01 PM PST 24 |
| Finished | Jan 14 12:25:07 PM PST 24 |
| Peak memory | 214256 kb |
| Host | smart-ef6c4328-533e-4914-9e15-ce2018fa49ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338040411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3338040411 |
| Directory | /workspace/16.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1094366538 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 319987212 ps |
| CPU time | 2.28 seconds |
| Started | Jan 14 12:25:02 PM PST 24 |
| Finished | Jan 14 12:25:10 PM PST 24 |
| Peak memory | 206024 kb |
| Host | smart-a4e88d7b-8875-46d8-83d4-7616aa3d90f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094366538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1094366538 |
| Directory | /workspace/16.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.535727855 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 66347413 ps |
| CPU time | 1.3 seconds |
| Started | Jan 14 12:25:00 PM PST 24 |
| Finished | Jan 14 12:25:05 PM PST 24 |
| Peak memory | 214132 kb |
| Host | smart-f2278c2b-2deb-41be-9816-80874732b03f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535727855 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.535727855 |
| Directory | /workspace/17.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.edn_csr_rw.317916404 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 23079276 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:24:58 PM PST 24 |
| Finished | Jan 14 12:25:05 PM PST 24 |
| Peak memory | 205940 kb |
| Host | smart-d4c84b0e-58aa-4fd7-9590-3d33277d6945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317916404 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.317916404 |
| Directory | /workspace/17.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.edn_intr_test.4084947928 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 38612531 ps |
| CPU time | 0.76 seconds |
| Started | Jan 14 12:25:04 PM PST 24 |
| Finished | Jan 14 12:25:09 PM PST 24 |
| Peak memory | 205756 kb |
| Host | smart-339d055e-6f42-4166-8d83-5cc6dca0d3ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084947928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.4084947928 |
| Directory | /workspace/17.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3767644013 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 17901985 ps |
| CPU time | 1.09 seconds |
| Started | Jan 14 12:25:02 PM PST 24 |
| Finished | Jan 14 12:25:06 PM PST 24 |
| Peak memory | 205964 kb |
| Host | smart-e28e6a4c-e262-49d5-afbe-f7d1c3187b71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767644013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o utstanding.3767644013 |
| Directory | /workspace/17.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.edn_tl_errors.226535691 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 122676286 ps |
| CPU time | 1.48 seconds |
| Started | Jan 14 12:25:04 PM PST 24 |
| Finished | Jan 14 12:25:09 PM PST 24 |
| Peak memory | 214120 kb |
| Host | smart-5240c42f-6023-4fb1-be9b-861d9d4ab48b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226535691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.226535691 |
| Directory | /workspace/17.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2682187685 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 51138614 ps |
| CPU time | 1.61 seconds |
| Started | Jan 14 12:25:09 PM PST 24 |
| Finished | Jan 14 12:25:12 PM PST 24 |
| Peak memory | 206036 kb |
| Host | smart-f6e39057-a6e7-496d-8913-5db87500f2ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682187685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2682187685 |
| Directory | /workspace/17.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1788435493 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 37027257 ps |
| CPU time | 1.33 seconds |
| Started | Jan 14 12:25:09 PM PST 24 |
| Finished | Jan 14 12:25:12 PM PST 24 |
| Peak memory | 214576 kb |
| Host | smart-b17af4d6-f338-4189-b037-05a78463cf05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788435493 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1788435493 |
| Directory | /workspace/18.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.edn_csr_rw.490253039 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 26634858 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:25:21 PM PST 24 |
| Finished | Jan 14 12:25:24 PM PST 24 |
| Peak memory | 206068 kb |
| Host | smart-c81bbcb5-7eb3-4558-a03c-28d79fb5a8ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490253039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.490253039 |
| Directory | /workspace/18.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.edn_intr_test.1051428310 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 50893291 ps |
| CPU time | 0.87 seconds |
| Started | Jan 14 12:25:02 PM PST 24 |
| Finished | Jan 14 12:25:08 PM PST 24 |
| Peak memory | 205984 kb |
| Host | smart-f86c5391-b460-470a-9d41-a97706fd1503 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051428310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1051428310 |
| Directory | /workspace/18.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.948894979 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 20217109 ps |
| CPU time | 1.05 seconds |
| Started | Jan 14 12:25:00 PM PST 24 |
| Finished | Jan 14 12:25:05 PM PST 24 |
| Peak memory | 205984 kb |
| Host | smart-99df0437-2ab8-442f-8df0-310f51a035f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948894979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou tstanding.948894979 |
| Directory | /workspace/18.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.edn_tl_errors.4254291076 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 70147399 ps |
| CPU time | 2.53 seconds |
| Started | Jan 14 12:25:07 PM PST 24 |
| Finished | Jan 14 12:25:12 PM PST 24 |
| Peak memory | 214260 kb |
| Host | smart-3175fff4-0f2a-47cf-8db0-9ec425871e30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254291076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.4254291076 |
| Directory | /workspace/18.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2852096252 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 3475555458 ps |
| CPU time | 12.75 seconds |
| Started | Jan 14 12:24:57 PM PST 24 |
| Finished | Jan 14 12:25:15 PM PST 24 |
| Peak memory | 206008 kb |
| Host | smart-d9352820-a550-47ef-80b9-836c63483fc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852096252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2852096252 |
| Directory | /workspace/18.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3087987149 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 21024479 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:25:09 PM PST 24 |
| Finished | Jan 14 12:25:11 PM PST 24 |
| Peak memory | 206012 kb |
| Host | smart-87e38c2e-125c-4238-bcc7-cff4b3eb6005 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087987149 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3087987149 |
| Directory | /workspace/19.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.edn_csr_rw.4157538921 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 30501292 ps |
| CPU time | 0.87 seconds |
| Started | Jan 14 12:25:09 PM PST 24 |
| Finished | Jan 14 12:25:11 PM PST 24 |
| Peak memory | 205952 kb |
| Host | smart-d189ac18-4817-4f46-9ebd-084b3ee6f723 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157538921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.4157538921 |
| Directory | /workspace/19.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.edn_intr_test.1325359260 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 18501882 ps |
| CPU time | 0.84 seconds |
| Started | Jan 14 12:25:14 PM PST 24 |
| Finished | Jan 14 12:25:16 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-fb923be9-f689-4ead-a3a7-78fefdff8827 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325359260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1325359260 |
| Directory | /workspace/19.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.93496247 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 23120681 ps |
| CPU time | 1.06 seconds |
| Started | Jan 14 12:25:20 PM PST 24 |
| Finished | Jan 14 12:25:23 PM PST 24 |
| Peak memory | 206012 kb |
| Host | smart-b15ba69a-9d4f-49a3-8191-311d525aa54d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93496247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_out standing.93496247 |
| Directory | /workspace/19.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.edn_tl_errors.808411453 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 88643128 ps |
| CPU time | 1.76 seconds |
| Started | Jan 14 12:25:11 PM PST 24 |
| Finished | Jan 14 12:25:13 PM PST 24 |
| Peak memory | 214280 kb |
| Host | smart-c045cee9-5eaa-4957-965c-5ef162c54d11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808411453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.808411453 |
| Directory | /workspace/19.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.76061755 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 176216582 ps |
| CPU time | 3.51 seconds |
| Started | Jan 14 12:24:57 PM PST 24 |
| Finished | Jan 14 12:25:06 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-045273df-f9d7-4b6c-aab1-c59d70cd8d73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76061755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.76061755 |
| Directory | /workspace/19.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1148952180 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 35329365 ps |
| CPU time | 1.16 seconds |
| Started | Jan 14 12:25:02 PM PST 24 |
| Finished | Jan 14 12:25:07 PM PST 24 |
| Peak memory | 205924 kb |
| Host | smart-2ddeb6a8-8ec4-4fa7-b073-9247cd553abd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148952180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1148952180 |
| Directory | /workspace/2.edn_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2105390139 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 265783716 ps |
| CPU time | 3.53 seconds |
| Started | Jan 14 12:25:06 PM PST 24 |
| Finished | Jan 14 12:25:12 PM PST 24 |
| Peak memory | 205920 kb |
| Host | smart-b50fe3a5-2669-4eb7-b0fd-b54ec6c8a118 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105390139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2105390139 |
| Directory | /workspace/2.edn_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.725401903 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 54114387 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:24:55 PM PST 24 |
| Finished | Jan 14 12:24:57 PM PST 24 |
| Peak memory | 206084 kb |
| Host | smart-ec228129-afe5-4090-ae7a-55900f7cccc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725401903 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.725401903 |
| Directory | /workspace/2.edn_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3053784008 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 16563470 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:24:55 PM PST 24 |
| Finished | Jan 14 12:24:57 PM PST 24 |
| Peak memory | 206040 kb |
| Host | smart-4859fe32-107f-4483-a276-e6d1fbb609fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053784008 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3053784008 |
| Directory | /workspace/2.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_csr_rw.373693019 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 16468137 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:24:49 PM PST 24 |
| Finished | Jan 14 12:24:51 PM PST 24 |
| Peak memory | 205944 kb |
| Host | smart-2ec4ca14-6f59-4279-b6d6-ee3b6078c472 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373693019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.373693019 |
| Directory | /workspace/2.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_intr_test.4225661626 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 34533649 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:24:43 PM PST 24 |
| Finished | Jan 14 12:24:44 PM PST 24 |
| Peak memory | 206028 kb |
| Host | smart-81f4c47e-ab7d-4b75-9f90-a6fcfc7806a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225661626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.4225661626 |
| Directory | /workspace/2.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2900994629 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 145385176 ps |
| CPU time | 1.07 seconds |
| Started | Jan 14 12:24:50 PM PST 24 |
| Finished | Jan 14 12:24:51 PM PST 24 |
| Peak memory | 205980 kb |
| Host | smart-cbd018bf-df22-46f4-8e2d-2e73a0cd6a72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900994629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou tstanding.2900994629 |
| Directory | /workspace/2.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_tl_errors.36912421 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 139447048 ps |
| CPU time | 2.51 seconds |
| Started | Jan 14 12:24:43 PM PST 24 |
| Finished | Jan 14 12:24:46 PM PST 24 |
| Peak memory | 214276 kb |
| Host | smart-32a7d645-3d79-47cd-ab91-aae728ea3f4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36912421 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.36912421 |
| Directory | /workspace/2.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.734309171 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 122940141 ps |
| CPU time | 2.63 seconds |
| Started | Jan 14 12:25:04 PM PST 24 |
| Finished | Jan 14 12:25:11 PM PST 24 |
| Peak memory | 206020 kb |
| Host | smart-1e41d06d-b961-47f9-abb1-c2420ac005cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734309171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.734309171 |
| Directory | /workspace/2.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.edn_intr_test.3199066111 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 12679883 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:25:15 PM PST 24 |
| Finished | Jan 14 12:25:17 PM PST 24 |
| Peak memory | 205952 kb |
| Host | smart-070aeab4-371e-4b24-8453-fdd977b22010 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199066111 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3199066111 |
| Directory | /workspace/20.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.edn_intr_test.1765579470 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 57855341 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:25:10 PM PST 24 |
| Finished | Jan 14 12:25:12 PM PST 24 |
| Peak memory | 205908 kb |
| Host | smart-b6b12460-7c53-4722-9f7b-6d53ab2fb7f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765579470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1765579470 |
| Directory | /workspace/21.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.edn_intr_test.3196577278 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 38976854 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:24:58 PM PST 24 |
| Finished | Jan 14 12:25:05 PM PST 24 |
| Peak memory | 205952 kb |
| Host | smart-639245f5-260c-4ed4-b193-37c031cb11f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196577278 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3196577278 |
| Directory | /workspace/22.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.edn_intr_test.4254918768 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 33385186 ps |
| CPU time | 0.75 seconds |
| Started | Jan 14 12:24:56 PM PST 24 |
| Finished | Jan 14 12:24:58 PM PST 24 |
| Peak memory | 205756 kb |
| Host | smart-af453aa8-17ac-419a-87be-54524e852af9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254918768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.4254918768 |
| Directory | /workspace/23.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.edn_intr_test.3215019298 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 75738711 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 12:25:09 PM PST 24 |
| Finished | Jan 14 12:25:11 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-e5c1eaa4-2bdf-4fa3-b1ea-43f2e8ae3bf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215019298 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3215019298 |
| Directory | /workspace/24.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.edn_intr_test.2258318914 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 95563619 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:25:15 PM PST 24 |
| Finished | Jan 14 12:25:23 PM PST 24 |
| Peak memory | 205676 kb |
| Host | smart-401d517f-8e85-421e-82cd-8d23e0c6728d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258318914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2258318914 |
| Directory | /workspace/25.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.edn_intr_test.896148269 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 18789170 ps |
| CPU time | 0.77 seconds |
| Started | Jan 14 12:24:50 PM PST 24 |
| Finished | Jan 14 12:24:51 PM PST 24 |
| Peak memory | 205788 kb |
| Host | smart-fd90c72c-ef94-4951-8977-0dc720ab1fc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896148269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.896148269 |
| Directory | /workspace/26.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.edn_intr_test.2054355453 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 11822248 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:25:00 PM PST 24 |
| Finished | Jan 14 12:25:05 PM PST 24 |
| Peak memory | 205836 kb |
| Host | smart-c62c617b-92fc-4bea-a7cc-3840c4bc48dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054355453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2054355453 |
| Directory | /workspace/27.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.edn_intr_test.3667365197 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 14010400 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 12:25:14 PM PST 24 |
| Finished | Jan 14 12:25:16 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-eb59dd82-846e-4ab1-873e-10a689ed2568 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667365197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3667365197 |
| Directory | /workspace/28.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.edn_intr_test.2501308768 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 16323065 ps |
| CPU time | 0.87 seconds |
| Started | Jan 14 12:25:13 PM PST 24 |
| Finished | Jan 14 12:25:15 PM PST 24 |
| Peak memory | 205836 kb |
| Host | smart-a510688b-d745-4503-8375-6bc2881a8d01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501308768 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2501308768 |
| Directory | /workspace/29.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.927464087 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 31335503 ps |
| CPU time | 1.44 seconds |
| Started | Jan 14 12:24:31 PM PST 24 |
| Finished | Jan 14 12:24:33 PM PST 24 |
| Peak memory | 205932 kb |
| Host | smart-9b17ee05-70dc-494b-8c4e-494e5ee1baf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927464087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.927464087 |
| Directory | /workspace/3.edn_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3749983099 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 258415893 ps |
| CPU time | 3.38 seconds |
| Started | Jan 14 12:24:56 PM PST 24 |
| Finished | Jan 14 12:25:00 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-f1371940-b1f4-4f5c-afa6-f33d834813e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749983099 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3749983099 |
| Directory | /workspace/3.edn_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.523361656 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 18191579 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:24:58 PM PST 24 |
| Finished | Jan 14 12:25:05 PM PST 24 |
| Peak memory | 206084 kb |
| Host | smart-30d3f021-c0ea-4694-8eb8-641c3ce6be46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523361656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.523361656 |
| Directory | /workspace/3.edn_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1957288409 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 44985757 ps |
| CPU time | 1.35 seconds |
| Started | Jan 14 12:24:39 PM PST 24 |
| Finished | Jan 14 12:24:41 PM PST 24 |
| Peak memory | 212348 kb |
| Host | smart-333bc6b7-f4f3-4d90-9b6b-b15dfcc51b3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957288409 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1957288409 |
| Directory | /workspace/3.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_csr_rw.2632747782 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 35701178 ps |
| CPU time | 0.79 seconds |
| Started | Jan 14 12:25:03 PM PST 24 |
| Finished | Jan 14 12:25:08 PM PST 24 |
| Peak memory | 205768 kb |
| Host | smart-835aff8e-5937-4f1c-86d7-9587f1d80ec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632747782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2632747782 |
| Directory | /workspace/3.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_intr_test.425321579 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 57281369 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:24:39 PM PST 24 |
| Finished | Jan 14 12:24:41 PM PST 24 |
| Peak memory | 203452 kb |
| Host | smart-e1b1a52c-e372-4352-a8cb-d93c7a697865 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425321579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.425321579 |
| Directory | /workspace/3.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.4038359417 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 21055817 ps |
| CPU time | 1.08 seconds |
| Started | Jan 14 12:24:31 PM PST 24 |
| Finished | Jan 14 12:24:32 PM PST 24 |
| Peak memory | 205988 kb |
| Host | smart-c82d3969-9907-4ef5-8836-a2b36fed2840 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038359417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou tstanding.4038359417 |
| Directory | /workspace/3.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_tl_errors.4279076719 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 61768841 ps |
| CPU time | 2.3 seconds |
| Started | Jan 14 12:24:32 PM PST 24 |
| Finished | Jan 14 12:24:35 PM PST 24 |
| Peak memory | 214188 kb |
| Host | smart-eccc1484-7217-4bd6-8354-f25323d08c76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279076719 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.4279076719 |
| Directory | /workspace/3.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2811190490 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 102112610 ps |
| CPU time | 1.49 seconds |
| Started | Jan 14 12:24:40 PM PST 24 |
| Finished | Jan 14 12:24:42 PM PST 24 |
| Peak memory | 205992 kb |
| Host | smart-14c7faa6-96f2-49f7-b6b9-466c0daa97da |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811190490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2811190490 |
| Directory | /workspace/3.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.edn_intr_test.1185235388 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 149604682 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:24:59 PM PST 24 |
| Finished | Jan 14 12:25:05 PM PST 24 |
| Peak memory | 205956 kb |
| Host | smart-604f4fd5-5759-4967-9578-ff6b8214320f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185235388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.1185235388 |
| Directory | /workspace/30.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.edn_intr_test.33666504 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 18876278 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:25:14 PM PST 24 |
| Finished | Jan 14 12:25:16 PM PST 24 |
| Peak memory | 205828 kb |
| Host | smart-a61ace27-1858-4f9d-8bae-744e3ce5d8e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33666504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.33666504 |
| Directory | /workspace/31.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.edn_intr_test.691964181 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 47162621 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:24:56 PM PST 24 |
| Finished | Jan 14 12:24:58 PM PST 24 |
| Peak memory | 205832 kb |
| Host | smart-84b4a861-0527-4eac-a6f0-cc5ab0a46342 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691964181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.691964181 |
| Directory | /workspace/32.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.edn_intr_test.4266689164 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 34069204 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:25:00 PM PST 24 |
| Finished | Jan 14 12:25:09 PM PST 24 |
| Peak memory | 205788 kb |
| Host | smart-c84c5a2e-d7db-47e6-b721-bc650a9edf7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266689164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.4266689164 |
| Directory | /workspace/33.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.edn_intr_test.946441150 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 12723282 ps |
| CPU time | 0.84 seconds |
| Started | Jan 14 12:25:04 PM PST 24 |
| Finished | Jan 14 12:25:09 PM PST 24 |
| Peak memory | 206080 kb |
| Host | smart-a2e00fe5-6bf8-4540-8f89-aa89a536b7c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946441150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.946441150 |
| Directory | /workspace/34.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.edn_intr_test.567745885 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 37626847 ps |
| CPU time | 0.84 seconds |
| Started | Jan 14 12:25:14 PM PST 24 |
| Finished | Jan 14 12:25:16 PM PST 24 |
| Peak memory | 205828 kb |
| Host | smart-6355fc4e-02d3-44bf-8eb7-c34e7c0068f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567745885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.567745885 |
| Directory | /workspace/35.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.edn_intr_test.4034606063 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 15533514 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:24:50 PM PST 24 |
| Finished | Jan 14 12:24:51 PM PST 24 |
| Peak memory | 205984 kb |
| Host | smart-2444459a-6670-4292-ac3d-789eb1f718c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034606063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.4034606063 |
| Directory | /workspace/36.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.edn_intr_test.3845008396 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 11360011 ps |
| CPU time | 0.84 seconds |
| Started | Jan 14 12:25:25 PM PST 24 |
| Finished | Jan 14 12:25:31 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-e13fe8c4-f7b3-49b9-aac3-d668dbe847d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845008396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3845008396 |
| Directory | /workspace/37.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.edn_intr_test.3322257201 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 139853641 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:25:05 PM PST 24 |
| Finished | Jan 14 12:25:09 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-f459e7e7-8209-4d17-9694-2f55bb1e1799 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322257201 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.3322257201 |
| Directory | /workspace/38.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.edn_intr_test.3387099024 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 21522120 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:25:14 PM PST 24 |
| Finished | Jan 14 12:25:15 PM PST 24 |
| Peak memory | 205836 kb |
| Host | smart-0c8e0b2a-d59c-410f-97d9-069926c515e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387099024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3387099024 |
| Directory | /workspace/39.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.552401225 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 38162229 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:25:00 PM PST 24 |
| Finished | Jan 14 12:25:09 PM PST 24 |
| Peak memory | 205916 kb |
| Host | smart-e71464b3-d0bb-4435-8278-d0685090129f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552401225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.552401225 |
| Directory | /workspace/4.edn_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.586205383 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 136556621 ps |
| CPU time | 3.42 seconds |
| Started | Jan 14 12:24:59 PM PST 24 |
| Finished | Jan 14 12:25:07 PM PST 24 |
| Peak memory | 205916 kb |
| Host | smart-c18b26d9-f5fe-4499-9840-a824dcb93b7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586205383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.586205383 |
| Directory | /workspace/4.edn_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3831235468 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 55191424 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:24:30 PM PST 24 |
| Finished | Jan 14 12:24:31 PM PST 24 |
| Peak memory | 205916 kb |
| Host | smart-8d3729ae-f257-40e4-a42a-b90d527c78bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831235468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3831235468 |
| Directory | /workspace/4.edn_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1646924191 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 40371439 ps |
| CPU time | 1.17 seconds |
| Started | Jan 14 12:24:39 PM PST 24 |
| Finished | Jan 14 12:24:41 PM PST 24 |
| Peak memory | 211916 kb |
| Host | smart-69ee8f58-c2af-4996-b4e1-c0fc012e1e9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646924191 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1646924191 |
| Directory | /workspace/4.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_csr_rw.2166520607 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 20810910 ps |
| CPU time | 0.78 seconds |
| Started | Jan 14 12:24:45 PM PST 24 |
| Finished | Jan 14 12:24:46 PM PST 24 |
| Peak memory | 205764 kb |
| Host | smart-fdecd233-297e-4fd8-84da-377aec367422 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166520607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2166520607 |
| Directory | /workspace/4.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_intr_test.2243228508 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 43355918 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:24:39 PM PST 24 |
| Finished | Jan 14 12:24:41 PM PST 24 |
| Peak memory | 203720 kb |
| Host | smart-25c21c36-8685-4335-bf22-3f944f44c866 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243228508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2243228508 |
| Directory | /workspace/4.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2899300345 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 26532721 ps |
| CPU time | 1.05 seconds |
| Started | Jan 14 12:25:06 PM PST 24 |
| Finished | Jan 14 12:25:10 PM PST 24 |
| Peak memory | 205980 kb |
| Host | smart-c66cae1e-44fe-4568-a51f-4b2010e252bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899300345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou tstanding.2899300345 |
| Directory | /workspace/4.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_tl_errors.2909167136 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 28062925 ps |
| CPU time | 1.97 seconds |
| Started | Jan 14 12:24:38 PM PST 24 |
| Finished | Jan 14 12:24:40 PM PST 24 |
| Peak memory | 214344 kb |
| Host | smart-221edb6a-ce89-46cf-8e23-6bd211c25cda |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909167136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2909167136 |
| Directory | /workspace/4.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1480832970 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 325435570 ps |
| CPU time | 1.54 seconds |
| Started | Jan 14 12:24:47 PM PST 24 |
| Finished | Jan 14 12:24:49 PM PST 24 |
| Peak memory | 205896 kb |
| Host | smart-db6b9540-4120-44f6-9db3-d6014dce83e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480832970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1480832970 |
| Directory | /workspace/4.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.edn_intr_test.4217283438 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 14685276 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:25:11 PM PST 24 |
| Finished | Jan 14 12:25:13 PM PST 24 |
| Peak memory | 205836 kb |
| Host | smart-6cf0993d-f342-4020-8387-f26fc5f3255a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217283438 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.4217283438 |
| Directory | /workspace/40.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.edn_intr_test.1671707079 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 110187178 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:25:14 PM PST 24 |
| Finished | Jan 14 12:25:16 PM PST 24 |
| Peak memory | 205836 kb |
| Host | smart-c4acb201-8e4c-45b1-817a-6493bd88c612 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671707079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1671707079 |
| Directory | /workspace/41.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.edn_intr_test.3141698082 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 46892804 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:25:15 PM PST 24 |
| Finished | Jan 14 12:25:20 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-7dad7c9b-48d7-41de-9e4e-643f74bbb944 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141698082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3141698082 |
| Directory | /workspace/42.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.edn_intr_test.3200896901 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 18170011 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:25:13 PM PST 24 |
| Finished | Jan 14 12:25:15 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-393f0a51-33b5-46f6-b4f2-b54cb3f6e623 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200896901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3200896901 |
| Directory | /workspace/43.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.edn_intr_test.3614997368 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 45583846 ps |
| CPU time | 0.78 seconds |
| Started | Jan 14 12:25:07 PM PST 24 |
| Finished | Jan 14 12:25:10 PM PST 24 |
| Peak memory | 205576 kb |
| Host | smart-47fbaa18-77f6-4078-b1ec-9c838c7ff3bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614997368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3614997368 |
| Directory | /workspace/44.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.edn_intr_test.2865059681 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 26724762 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:25:12 PM PST 24 |
| Finished | Jan 14 12:25:13 PM PST 24 |
| Peak memory | 205936 kb |
| Host | smart-2bb552c1-7126-4c95-bd1d-2439b608260c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865059681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2865059681 |
| Directory | /workspace/45.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.edn_intr_test.2367519341 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 94952413 ps |
| CPU time | 0.84 seconds |
| Started | Jan 14 12:25:05 PM PST 24 |
| Finished | Jan 14 12:25:09 PM PST 24 |
| Peak memory | 204704 kb |
| Host | smart-6b0bc35a-7e4a-4753-bc45-bba2b860578f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367519341 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2367519341 |
| Directory | /workspace/46.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.edn_intr_test.1571773862 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 53452386 ps |
| CPU time | 0.8 seconds |
| Started | Jan 14 12:25:13 PM PST 24 |
| Finished | Jan 14 12:25:14 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-4ab5b8e9-88ad-46eb-8da9-4765ad4715d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571773862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1571773862 |
| Directory | /workspace/47.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.edn_intr_test.986236108 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 13832167 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:24:42 PM PST 24 |
| Finished | Jan 14 12:24:43 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-58036efe-5ab2-416a-9f6b-c9a3c8208598 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986236108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.986236108 |
| Directory | /workspace/48.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.edn_intr_test.2179825186 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 14902367 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:25:15 PM PST 24 |
| Finished | Jan 14 12:25:16 PM PST 24 |
| Peak memory | 205648 kb |
| Host | smart-eceaf080-447a-4a09-a9ba-a4a0ea5317a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179825186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2179825186 |
| Directory | /workspace/49.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1305093630 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 24702849 ps |
| CPU time | 1.05 seconds |
| Started | Jan 14 12:24:35 PM PST 24 |
| Finished | Jan 14 12:24:37 PM PST 24 |
| Peak memory | 214276 kb |
| Host | smart-f261e602-4d4b-4e5a-b09f-b638df01a9ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305093630 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1305093630 |
| Directory | /workspace/5.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.edn_csr_rw.3115130547 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 11288696 ps |
| CPU time | 0.78 seconds |
| Started | Jan 14 12:25:04 PM PST 24 |
| Finished | Jan 14 12:25:09 PM PST 24 |
| Peak memory | 205960 kb |
| Host | smart-2b5f7af9-6403-4364-8d50-70778bb0c1d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115130547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3115130547 |
| Directory | /workspace/5.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.edn_intr_test.2577292607 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 13008643 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:25:01 PM PST 24 |
| Finished | Jan 14 12:25:05 PM PST 24 |
| Peak memory | 205912 kb |
| Host | smart-b5d3b3d2-fcbd-4560-a45f-caeeffd128b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577292607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2577292607 |
| Directory | /workspace/5.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2667452806 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 64987781 ps |
| CPU time | 1.25 seconds |
| Started | Jan 14 12:24:29 PM PST 24 |
| Finished | Jan 14 12:24:30 PM PST 24 |
| Peak memory | 205964 kb |
| Host | smart-0f4ba658-9dd5-46a2-8f78-6dfd73bb0b62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667452806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou tstanding.2667452806 |
| Directory | /workspace/5.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.edn_tl_errors.2853501319 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 48012200 ps |
| CPU time | 1.72 seconds |
| Started | Jan 14 12:24:55 PM PST 24 |
| Finished | Jan 14 12:24:58 PM PST 24 |
| Peak memory | 214172 kb |
| Host | smart-da0d54d7-2b64-4de3-a37d-cf1e034d6899 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853501319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2853501319 |
| Directory | /workspace/5.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3067792321 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 76725299 ps |
| CPU time | 2.25 seconds |
| Started | Jan 14 12:25:00 PM PST 24 |
| Finished | Jan 14 12:25:06 PM PST 24 |
| Peak memory | 205984 kb |
| Host | smart-f70dda4c-970e-460b-9f86-d5c2544256d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067792321 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3067792321 |
| Directory | /workspace/5.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3404595181 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 54987336 ps |
| CPU time | 1.19 seconds |
| Started | Jan 14 12:24:47 PM PST 24 |
| Finished | Jan 14 12:24:49 PM PST 24 |
| Peak memory | 214236 kb |
| Host | smart-ecf05479-c7cd-42ba-9117-f3ecf7dae0a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404595181 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3404595181 |
| Directory | /workspace/6.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.edn_csr_rw.934477467 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 15492153 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:24:47 PM PST 24 |
| Finished | Jan 14 12:24:49 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-f602b972-6172-412d-a0f2-aa9e226a78ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934477467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.934477467 |
| Directory | /workspace/6.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.edn_intr_test.479243095 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 15473648 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:25:00 PM PST 24 |
| Finished | Jan 14 12:25:05 PM PST 24 |
| Peak memory | 205956 kb |
| Host | smart-7d624482-7e20-4526-824e-3e9fcdb68060 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479243095 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.479243095 |
| Directory | /workspace/6.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2200935656 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 24993895 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:25:00 PM PST 24 |
| Finished | Jan 14 12:25:05 PM PST 24 |
| Peak memory | 205944 kb |
| Host | smart-eef0c5b8-b24c-4845-a717-7a4a704b5529 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200935656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou tstanding.2200935656 |
| Directory | /workspace/6.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.edn_tl_errors.224562061 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 326462519 ps |
| CPU time | 2.41 seconds |
| Started | Jan 14 12:24:56 PM PST 24 |
| Finished | Jan 14 12:24:59 PM PST 24 |
| Peak memory | 214288 kb |
| Host | smart-09ac1016-532b-4a68-8123-1b2095ebec7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224562061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.224562061 |
| Directory | /workspace/6.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.814359272 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 58089932 ps |
| CPU time | 1.56 seconds |
| Started | Jan 14 12:24:45 PM PST 24 |
| Finished | Jan 14 12:24:47 PM PST 24 |
| Peak memory | 206016 kb |
| Host | smart-d7400471-ed2a-434a-8bab-46bcee37c15e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814359272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.814359272 |
| Directory | /workspace/6.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2763651028 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 21446194 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:25:01 PM PST 24 |
| Finished | Jan 14 12:25:05 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-45c9b2db-0199-434b-b9ee-d61e5708a126 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763651028 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2763651028 |
| Directory | /workspace/7.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.edn_csr_rw.3812985814 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 20065618 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:24:54 PM PST 24 |
| Finished | Jan 14 12:24:55 PM PST 24 |
| Peak memory | 205920 kb |
| Host | smart-1cbf2131-3899-4a7c-8412-46ded6b57006 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812985814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3812985814 |
| Directory | /workspace/7.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.edn_intr_test.1951038803 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 137372647 ps |
| CPU time | 0.75 seconds |
| Started | Jan 14 12:24:54 PM PST 24 |
| Finished | Jan 14 12:24:55 PM PST 24 |
| Peak memory | 205756 kb |
| Host | smart-cedca489-7343-4bda-b1ee-098c0a20b50b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951038803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1951038803 |
| Directory | /workspace/7.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.967986046 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 32571940 ps |
| CPU time | 1.29 seconds |
| Started | Jan 14 12:24:54 PM PST 24 |
| Finished | Jan 14 12:24:56 PM PST 24 |
| Peak memory | 205960 kb |
| Host | smart-973a4654-83d7-4c12-bf7e-21fb377429bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967986046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out standing.967986046 |
| Directory | /workspace/7.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.edn_tl_errors.701825745 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 70335338 ps |
| CPU time | 2.6 seconds |
| Started | Jan 14 12:25:05 PM PST 24 |
| Finished | Jan 14 12:25:11 PM PST 24 |
| Peak memory | 214176 kb |
| Host | smart-6a9d6c9d-38cf-4c5e-afb6-2f100e84a1a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701825745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.701825745 |
| Directory | /workspace/7.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.409687812 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 117076077 ps |
| CPU time | 1.6 seconds |
| Started | Jan 14 12:25:02 PM PST 24 |
| Finished | Jan 14 12:25:11 PM PST 24 |
| Peak memory | 206016 kb |
| Host | smart-765e2014-3f98-4d66-a772-9ed877443e14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409687812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.409687812 |
| Directory | /workspace/7.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3860792148 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 35209453 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:24:59 PM PST 24 |
| Finished | Jan 14 12:25:05 PM PST 24 |
| Peak memory | 205908 kb |
| Host | smart-3aac9b6c-f754-4cda-a882-b25f3f887aed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860792148 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3860792148 |
| Directory | /workspace/8.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.edn_csr_rw.2786794651 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 50179378 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:24:39 PM PST 24 |
| Finished | Jan 14 12:24:40 PM PST 24 |
| Peak memory | 205864 kb |
| Host | smart-5e81c869-2e4c-409f-ad9f-942b0f0a8282 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786794651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2786794651 |
| Directory | /workspace/8.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.edn_intr_test.653829475 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 18690726 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:25:04 PM PST 24 |
| Finished | Jan 14 12:25:09 PM PST 24 |
| Peak memory | 205728 kb |
| Host | smart-c4953862-7fc1-4d34-9819-5dc1636b9d27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653829475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.653829475 |
| Directory | /workspace/8.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1834815717 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 20065058 ps |
| CPU time | 1.04 seconds |
| Started | Jan 14 12:24:55 PM PST 24 |
| Finished | Jan 14 12:24:57 PM PST 24 |
| Peak memory | 205856 kb |
| Host | smart-9c5db747-0c0f-4ab0-bc5b-05eab7f4fae7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834815717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou tstanding.1834815717 |
| Directory | /workspace/8.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.edn_tl_errors.3304451939 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 568688120 ps |
| CPU time | 4.28 seconds |
| Started | Jan 14 12:24:55 PM PST 24 |
| Finished | Jan 14 12:25:00 PM PST 24 |
| Peak memory | 214192 kb |
| Host | smart-cf01faf1-2f7a-40d8-ad9a-98377f64c422 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304451939 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3304451939 |
| Directory | /workspace/8.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1317999338 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 230371999 ps |
| CPU time | 1.9 seconds |
| Started | Jan 14 12:24:54 PM PST 24 |
| Finished | Jan 14 12:24:56 PM PST 24 |
| Peak memory | 206028 kb |
| Host | smart-1be87ab0-8fb4-4fbe-b35a-3a7bc0cbd947 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317999338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1317999338 |
| Directory | /workspace/8.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.2168517973 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 82665895 ps |
| CPU time | 1.44 seconds |
| Started | Jan 14 12:24:57 PM PST 24 |
| Finished | Jan 14 12:24:59 PM PST 24 |
| Peak memory | 216644 kb |
| Host | smart-dfaad505-86b0-4e9c-b8c7-0f5801efac5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168517973 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.2168517973 |
| Directory | /workspace/9.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.edn_csr_rw.3505789683 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 23341292 ps |
| CPU time | 0.77 seconds |
| Started | Jan 14 12:25:06 PM PST 24 |
| Finished | Jan 14 12:25:09 PM PST 24 |
| Peak memory | 205764 kb |
| Host | smart-9e4dd86b-922b-41c9-8ddd-c111f5218654 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505789683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3505789683 |
| Directory | /workspace/9.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.edn_intr_test.3015485360 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 46114008 ps |
| CPU time | 0.84 seconds |
| Started | Jan 14 12:24:43 PM PST 24 |
| Finished | Jan 14 12:24:44 PM PST 24 |
| Peak memory | 206028 kb |
| Host | smart-6d9a8c41-c38b-44a7-b331-c62bd8652a40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015485360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3015485360 |
| Directory | /workspace/9.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2212235517 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 60833756 ps |
| CPU time | 1.32 seconds |
| Started | Jan 14 12:24:43 PM PST 24 |
| Finished | Jan 14 12:24:45 PM PST 24 |
| Peak memory | 205464 kb |
| Host | smart-712bda5a-62d9-4a3b-ba3b-cf4da0fe4025 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212235517 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou tstanding.2212235517 |
| Directory | /workspace/9.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.edn_tl_errors.1481227076 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 203440761 ps |
| CPU time | 3.16 seconds |
| Started | Jan 14 12:24:59 PM PST 24 |
| Finished | Jan 14 12:25:07 PM PST 24 |
| Peak memory | 214080 kb |
| Host | smart-84e6a951-9067-40d4-8ae8-6bcd0edf81c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481227076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1481227076 |
| Directory | /workspace/9.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.4047758218 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 337281803 ps |
| CPU time | 2.21 seconds |
| Started | Jan 14 12:24:29 PM PST 24 |
| Finished | Jan 14 12:24:32 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-291c18ec-a42f-4e3e-a826-f0d02f89b682 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047758218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.4047758218 |
| Directory | /workspace/9.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.edn_alert.2128544944 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 20530728 ps |
| CPU time | 1.05 seconds |
| Started | Jan 14 12:25:33 PM PST 24 |
| Finished | Jan 14 12:25:38 PM PST 24 |
| Peak memory | 205284 kb |
| Host | smart-181b55ae-2d0d-46e4-bfde-7318e399fffe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2128544944 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2128544944 |
| Directory | /workspace/0.edn_alert/latest |
| Test location | /workspace/coverage/default/0.edn_alert_test.215585943 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 39217789 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:25:19 PM PST 24 |
| Finished | Jan 14 12:25:21 PM PST 24 |
| Peak memory | 205072 kb |
| Host | smart-90115888-0efe-4bf6-af79-e92130b7cc6c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215585943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.215585943 |
| Directory | /workspace/0.edn_alert_test/latest |
| Test location | /workspace/coverage/default/0.edn_err.2956344384 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 24821177 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:25:22 PM PST 24 |
| Finished | Jan 14 12:25:29 PM PST 24 |
| Peak memory | 216060 kb |
| Host | smart-9de0c608-962f-4b16-9b49-9d3c465005c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2956344384 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2956344384 |
| Directory | /workspace/0.edn_err/latest |
| Test location | /workspace/coverage/default/0.edn_genbits.3546010313 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 49483789 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:25:36 PM PST 24 |
| Finished | Jan 14 12:25:40 PM PST 24 |
| Peak memory | 204752 kb |
| Host | smart-79f0f74f-a038-4a8b-8c63-bdd3a2c84844 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3546010313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3546010313 |
| Directory | /workspace/0.edn_genbits/latest |
| Test location | /workspace/coverage/default/0.edn_intr.2382912384 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 20002383 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:25:18 PM PST 24 |
| Finished | Jan 14 12:25:20 PM PST 24 |
| Peak memory | 214248 kb |
| Host | smart-1b819f8d-e1a2-4a95-8b53-4e0e4f50957a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2382912384 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2382912384 |
| Directory | /workspace/0.edn_intr/latest |
| Test location | /workspace/coverage/default/0.edn_sec_cm.210097749 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 177113262 ps |
| CPU time | 3.22 seconds |
| Started | Jan 14 12:25:45 PM PST 24 |
| Finished | Jan 14 12:25:51 PM PST 24 |
| Peak memory | 232856 kb |
| Host | smart-441cf96a-ea3c-4933-a70a-ba4a7f6c4756 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210097749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.210097749 |
| Directory | /workspace/0.edn_sec_cm/latest |
| Test location | /workspace/coverage/default/0.edn_smoke.442472664 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 48048424 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 12:25:18 PM PST 24 |
| Finished | Jan 14 12:25:21 PM PST 24 |
| Peak memory | 204728 kb |
| Host | smart-96dc243b-9c1f-43cd-9fa6-3b73fe362b77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=442472664 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.442472664 |
| Directory | /workspace/0.edn_smoke/latest |
| Test location | /workspace/coverage/default/0.edn_stress_all.1945760294 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 209012147 ps |
| CPU time | 2.79 seconds |
| Started | Jan 14 12:25:59 PM PST 24 |
| Finished | Jan 14 12:26:03 PM PST 24 |
| Peak memory | 205872 kb |
| Host | smart-f0b09ecf-6db6-4afb-b22a-a09d064f87e9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945760294 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1945760294 |
| Directory | /workspace/0.edn_stress_all/latest |
| Test location | /workspace/coverage/default/0.edn_stress_all_with_rand_reset.31638784 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 53018823409 ps |
| CPU time | 281.86 seconds |
| Started | Jan 14 12:25:43 PM PST 24 |
| Finished | Jan 14 12:30:26 PM PST 24 |
| Peak memory | 214436 kb |
| Host | smart-ccfcefc2-ce56-4455-be26-e40d801f7037 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31638784 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.31638784 |
| Directory | /workspace/0.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.edn_alert.4006730275 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 21623693 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:25:25 PM PST 24 |
| Finished | Jan 14 12:25:31 PM PST 24 |
| Peak memory | 205876 kb |
| Host | smart-50e938a4-b0c8-4508-a4d2-7f4d98a9d987 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4006730275 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.4006730275 |
| Directory | /workspace/1.edn_alert/latest |
| Test location | /workspace/coverage/default/1.edn_alert_test.1068153031 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 75665336 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:25:54 PM PST 24 |
| Finished | Jan 14 12:25:55 PM PST 24 |
| Peak memory | 205280 kb |
| Host | smart-3d023097-98d6-4d2e-a704-5e0bc90df9f4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068153031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1068153031 |
| Directory | /workspace/1.edn_alert_test/latest |
| Test location | /workspace/coverage/default/1.edn_err.1117915433 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 29165994 ps |
| CPU time | 1.28 seconds |
| Started | Jan 14 12:25:55 PM PST 24 |
| Finished | Jan 14 12:25:58 PM PST 24 |
| Peak memory | 221832 kb |
| Host | smart-35eb3d76-eb03-497d-96cb-f47dd3e617ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1117915433 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1117915433 |
| Directory | /workspace/1.edn_err/latest |
| Test location | /workspace/coverage/default/1.edn_genbits.1122136334 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 45852544 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:25:20 PM PST 24 |
| Finished | Jan 14 12:25:23 PM PST 24 |
| Peak memory | 205256 kb |
| Host | smart-60e84fd4-8cd7-4a18-8492-1a92583b76f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1122136334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1122136334 |
| Directory | /workspace/1.edn_genbits/latest |
| Test location | /workspace/coverage/default/1.edn_intr.2287222983 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 23605460 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:25:19 PM PST 24 |
| Finished | Jan 14 12:25:22 PM PST 24 |
| Peak memory | 214324 kb |
| Host | smart-4e545c22-a351-4289-b517-6eb708f69a5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2287222983 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2287222983 |
| Directory | /workspace/1.edn_intr/latest |
| Test location | /workspace/coverage/default/1.edn_sec_cm.3008524957 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 314230550 ps |
| CPU time | 2.97 seconds |
| Started | Jan 14 12:25:16 PM PST 24 |
| Finished | Jan 14 12:25:20 PM PST 24 |
| Peak memory | 232748 kb |
| Host | smart-ce0ff9e1-3559-4d1a-b76a-f6ed7f2e0bca |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008524957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3008524957 |
| Directory | /workspace/1.edn_sec_cm/latest |
| Test location | /workspace/coverage/default/1.edn_smoke.4266649436 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 48713505 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:25:33 PM PST 24 |
| Finished | Jan 14 12:25:38 PM PST 24 |
| Peak memory | 203844 kb |
| Host | smart-e75e5d32-76fe-484f-89be-368c239ced5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4266649436 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.4266649436 |
| Directory | /workspace/1.edn_smoke/latest |
| Test location | /workspace/coverage/default/1.edn_stress_all.2149484282 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 537678404 ps |
| CPU time | 3.71 seconds |
| Started | Jan 14 12:25:28 PM PST 24 |
| Finished | Jan 14 12:25:34 PM PST 24 |
| Peak memory | 205924 kb |
| Host | smart-8708ec52-8b5d-4f7b-a9a6-d280da3481af |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149484282 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2149484282 |
| Directory | /workspace/1.edn_stress_all/latest |
| Test location | /workspace/coverage/default/10.edn_alert.667350692 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 33822179 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:25:25 PM PST 24 |
| Finished | Jan 14 12:25:31 PM PST 24 |
| Peak memory | 205840 kb |
| Host | smart-1e39c2d4-3ec6-4227-a8d9-a19033faf2f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=667350692 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.667350692 |
| Directory | /workspace/10.edn_alert/latest |
| Test location | /workspace/coverage/default/10.edn_disable_auto_req_mode.4012801113 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 31462690 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:25:23 PM PST 24 |
| Finished | Jan 14 12:25:29 PM PST 24 |
| Peak memory | 214404 kb |
| Host | smart-f16be87d-164d-4048-a7fc-a7a0a62121c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012801113 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d isable_auto_req_mode.4012801113 |
| Directory | /workspace/10.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/10.edn_err.264783062 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 23730990 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:25:26 PM PST 24 |
| Finished | Jan 14 12:25:31 PM PST 24 |
| Peak memory | 215704 kb |
| Host | smart-aa7eeaa7-31d8-4e7f-935b-840971bc64d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=264783062 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.264783062 |
| Directory | /workspace/10.edn_err/latest |
| Test location | /workspace/coverage/default/10.edn_genbits.227118507 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 61005636 ps |
| CPU time | 1.26 seconds |
| Started | Jan 14 12:25:44 PM PST 24 |
| Finished | Jan 14 12:25:49 PM PST 24 |
| Peak memory | 214016 kb |
| Host | smart-99d29935-af48-49c5-b8b8-a033a08999c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=227118507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.227118507 |
| Directory | /workspace/10.edn_genbits/latest |
| Test location | /workspace/coverage/default/10.edn_intr.321245930 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 27856614 ps |
| CPU time | 1.05 seconds |
| Started | Jan 14 12:25:46 PM PST 24 |
| Finished | Jan 14 12:25:49 PM PST 24 |
| Peak memory | 221820 kb |
| Host | smart-0d530b30-5be0-44f3-8741-c08707c34370 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=321245930 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.321245930 |
| Directory | /workspace/10.edn_intr/latest |
| Test location | /workspace/coverage/default/10.edn_smoke.3737961497 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 12515199 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:25:37 PM PST 24 |
| Finished | Jan 14 12:25:44 PM PST 24 |
| Peak memory | 204748 kb |
| Host | smart-3e2d38a7-cf1e-4ac4-9a56-562bafa889df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3737961497 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3737961497 |
| Directory | /workspace/10.edn_smoke/latest |
| Test location | /workspace/coverage/default/10.edn_stress_all.3929573418 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 97023863 ps |
| CPU time | 1.63 seconds |
| Started | Jan 14 12:25:38 PM PST 24 |
| Finished | Jan 14 12:25:45 PM PST 24 |
| Peak memory | 205656 kb |
| Host | smart-7716f3fa-dd7a-40ee-88f5-8a3c36d1184f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929573418 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3929573418 |
| Directory | /workspace/10.edn_stress_all/latest |
| Test location | /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2094851086 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 27870908645 ps |
| CPU time | 383.19 seconds |
| Started | Jan 14 12:25:21 PM PST 24 |
| Finished | Jan 14 12:31:47 PM PST 24 |
| Peak memory | 215916 kb |
| Host | smart-25aec84d-c4ac-4ae2-9613-6a036a694cfa |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094851086 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2094851086 |
| Directory | /workspace/10.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/100.edn_genbits.1602612305 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 109749830 ps |
| CPU time | 2.46 seconds |
| Started | Jan 14 12:27:03 PM PST 24 |
| Finished | Jan 14 12:27:07 PM PST 24 |
| Peak memory | 214060 kb |
| Host | smart-f8c1f581-8e7f-4956-ae88-27fc42008025 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1602612305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1602612305 |
| Directory | /workspace/100.edn_genbits/latest |
| Test location | /workspace/coverage/default/102.edn_genbits.1581734306 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 151209628 ps |
| CPU time | 1.32 seconds |
| Started | Jan 14 12:26:47 PM PST 24 |
| Finished | Jan 14 12:26:49 PM PST 24 |
| Peak memory | 214128 kb |
| Host | smart-f5789eef-0c1b-48a9-b8b6-567053d56be5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1581734306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1581734306 |
| Directory | /workspace/102.edn_genbits/latest |
| Test location | /workspace/coverage/default/103.edn_genbits.3217268462 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 41513923 ps |
| CPU time | 1.24 seconds |
| Started | Jan 14 12:26:51 PM PST 24 |
| Finished | Jan 14 12:26:53 PM PST 24 |
| Peak memory | 214068 kb |
| Host | smart-b3147317-9c70-4310-9fd6-9419459148fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3217268462 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3217268462 |
| Directory | /workspace/103.edn_genbits/latest |
| Test location | /workspace/coverage/default/104.edn_genbits.252467741 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 41607917 ps |
| CPU time | 0.87 seconds |
| Started | Jan 14 12:26:54 PM PST 24 |
| Finished | Jan 14 12:26:55 PM PST 24 |
| Peak memory | 204952 kb |
| Host | smart-fc9163dd-804a-4eb4-ae70-413f3fbcb19e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=252467741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.252467741 |
| Directory | /workspace/104.edn_genbits/latest |
| Test location | /workspace/coverage/default/105.edn_genbits.2822200055 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 24786204 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:26:55 PM PST 24 |
| Finished | Jan 14 12:26:57 PM PST 24 |
| Peak memory | 205308 kb |
| Host | smart-171c0775-3c1c-4256-b8d4-248aa1ce28aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2822200055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2822200055 |
| Directory | /workspace/105.edn_genbits/latest |
| Test location | /workspace/coverage/default/106.edn_genbits.1849036553 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 24718978 ps |
| CPU time | 1.2 seconds |
| Started | Jan 14 12:27:08 PM PST 24 |
| Finished | Jan 14 12:27:10 PM PST 24 |
| Peak memory | 214068 kb |
| Host | smart-ef8b575e-2281-40f2-94a6-ceaf53ddc1e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1849036553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1849036553 |
| Directory | /workspace/106.edn_genbits/latest |
| Test location | /workspace/coverage/default/107.edn_genbits.2161126441 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 117839350 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:26:52 PM PST 24 |
| Finished | Jan 14 12:26:53 PM PST 24 |
| Peak memory | 205392 kb |
| Host | smart-140fc123-a06c-471c-a788-61d2be60568f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2161126441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2161126441 |
| Directory | /workspace/107.edn_genbits/latest |
| Test location | /workspace/coverage/default/108.edn_genbits.1163483661 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 84452623 ps |
| CPU time | 1.23 seconds |
| Started | Jan 14 12:26:38 PM PST 24 |
| Finished | Jan 14 12:26:40 PM PST 24 |
| Peak memory | 214032 kb |
| Host | smart-f4f627a5-02ad-48b0-9460-627be0eb3d01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1163483661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1163483661 |
| Directory | /workspace/108.edn_genbits/latest |
| Test location | /workspace/coverage/default/11.edn_alert.31476580 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 59060994 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:25:54 PM PST 24 |
| Finished | Jan 14 12:25:56 PM PST 24 |
| Peak memory | 205208 kb |
| Host | smart-82d8ed15-582c-42b7-b800-efb4454bbd54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=31476580 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.31476580 |
| Directory | /workspace/11.edn_alert/latest |
| Test location | /workspace/coverage/default/11.edn_alert_test.4234264428 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 34131992 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 12:25:22 PM PST 24 |
| Finished | Jan 14 12:25:25 PM PST 24 |
| Peak memory | 205000 kb |
| Host | smart-ac17fb21-f1a6-493f-9dc0-fbd219065cdf |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234264428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.4234264428 |
| Directory | /workspace/11.edn_alert_test/latest |
| Test location | /workspace/coverage/default/11.edn_disable.262803243 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 42049912 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 12:25:28 PM PST 24 |
| Finished | Jan 14 12:25:31 PM PST 24 |
| Peak memory | 214336 kb |
| Host | smart-7ca7ae00-e02b-4368-9a6a-73a23062f61c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262803243 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.262803243 |
| Directory | /workspace/11.edn_disable/latest |
| Test location | /workspace/coverage/default/11.edn_disable_auto_req_mode.2942637389 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 92352879 ps |
| CPU time | 1.06 seconds |
| Started | Jan 14 12:25:59 PM PST 24 |
| Finished | Jan 14 12:26:01 PM PST 24 |
| Peak memory | 214432 kb |
| Host | smart-2930409c-0a27-4ce6-ad83-6a024508255e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942637389 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d isable_auto_req_mode.2942637389 |
| Directory | /workspace/11.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/11.edn_err.436663500 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 215926997 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:25:30 PM PST 24 |
| Finished | Jan 14 12:25:36 PM PST 24 |
| Peak memory | 214232 kb |
| Host | smart-771cdd8a-a88d-4ea9-9876-c03b3a8fa3c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=436663500 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.436663500 |
| Directory | /workspace/11.edn_err/latest |
| Test location | /workspace/coverage/default/11.edn_genbits.4273450164 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 92138017 ps |
| CPU time | 1.08 seconds |
| Started | Jan 14 12:25:36 PM PST 24 |
| Finished | Jan 14 12:25:40 PM PST 24 |
| Peak memory | 205132 kb |
| Host | smart-26d95a9b-1922-4663-a8ad-e2fa98779ec2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4273450164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.4273450164 |
| Directory | /workspace/11.edn_genbits/latest |
| Test location | /workspace/coverage/default/11.edn_smoke.4141151094 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 21187203 ps |
| CPU time | 0.87 seconds |
| Started | Jan 14 12:25:15 PM PST 24 |
| Finished | Jan 14 12:25:17 PM PST 24 |
| Peak memory | 204572 kb |
| Host | smart-8772d108-13c1-4d74-8114-b8f6220c1992 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4141151094 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.4141151094 |
| Directory | /workspace/11.edn_smoke/latest |
| Test location | /workspace/coverage/default/11.edn_stress_all.3565620610 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 2016959441 ps |
| CPU time | 3.23 seconds |
| Started | Jan 14 12:25:27 PM PST 24 |
| Finished | Jan 14 12:25:34 PM PST 24 |
| Peak memory | 205756 kb |
| Host | smart-fcaa5def-cdb7-4a75-9c01-0724bcdbdc42 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565620610 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.3565620610 |
| Directory | /workspace/11.edn_stress_all/latest |
| Test location | /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2411142849 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 104840242630 ps |
| CPU time | 268.49 seconds |
| Started | Jan 14 12:25:27 PM PST 24 |
| Finished | Jan 14 12:29:59 PM PST 24 |
| Peak memory | 214352 kb |
| Host | smart-9c4f08d4-9b20-471a-9e50-0b97c05e89af |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411142849 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2411142849 |
| Directory | /workspace/11.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/111.edn_genbits.270089408 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 58894246 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:26:52 PM PST 24 |
| Finished | Jan 14 12:26:53 PM PST 24 |
| Peak memory | 205148 kb |
| Host | smart-f13a074b-9901-45ca-9f24-c80e86568770 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=270089408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.270089408 |
| Directory | /workspace/111.edn_genbits/latest |
| Test location | /workspace/coverage/default/112.edn_genbits.1214003581 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 15674665 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:26:40 PM PST 24 |
| Finished | Jan 14 12:26:41 PM PST 24 |
| Peak memory | 205048 kb |
| Host | smart-3e61620d-b943-4054-9cf5-f4ca6b359389 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1214003581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1214003581 |
| Directory | /workspace/112.edn_genbits/latest |
| Test location | /workspace/coverage/default/114.edn_genbits.1417978171 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 31585332 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:27:03 PM PST 24 |
| Finished | Jan 14 12:27:05 PM PST 24 |
| Peak memory | 205516 kb |
| Host | smart-5bd2f018-81de-4b17-a587-32d27aa09f4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1417978171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1417978171 |
| Directory | /workspace/114.edn_genbits/latest |
| Test location | /workspace/coverage/default/115.edn_genbits.1082320101 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 28901651 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:26:44 PM PST 24 |
| Finished | Jan 14 12:26:46 PM PST 24 |
| Peak memory | 204872 kb |
| Host | smart-2be34638-c153-4d37-b337-f5cc3cb374db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1082320101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1082320101 |
| Directory | /workspace/115.edn_genbits/latest |
| Test location | /workspace/coverage/default/116.edn_genbits.1633827149 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 15675069 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:27:00 PM PST 24 |
| Finished | Jan 14 12:27:02 PM PST 24 |
| Peak memory | 205024 kb |
| Host | smart-532eb3ba-60eb-4b6e-9ea4-7ef5e09a30f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1633827149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1633827149 |
| Directory | /workspace/116.edn_genbits/latest |
| Test location | /workspace/coverage/default/117.edn_genbits.2053485521 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 16707879 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:26:47 PM PST 24 |
| Finished | Jan 14 12:26:49 PM PST 24 |
| Peak memory | 214096 kb |
| Host | smart-aecac6fa-fbc4-4f3f-ac3e-8dd35da81cd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2053485521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2053485521 |
| Directory | /workspace/117.edn_genbits/latest |
| Test location | /workspace/coverage/default/119.edn_genbits.3111576480 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 205970027 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:26:59 PM PST 24 |
| Finished | Jan 14 12:27:01 PM PST 24 |
| Peak memory | 204740 kb |
| Host | smart-aa4c58a6-c46b-47a1-b0c3-1e98b883ff84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3111576480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3111576480 |
| Directory | /workspace/119.edn_genbits/latest |
| Test location | /workspace/coverage/default/12.edn_alert.3602139526 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 17447177 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:25:35 PM PST 24 |
| Finished | Jan 14 12:25:40 PM PST 24 |
| Peak memory | 205716 kb |
| Host | smart-1cdf7488-fdfb-4300-8438-f3694d52e313 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3602139526 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3602139526 |
| Directory | /workspace/12.edn_alert/latest |
| Test location | /workspace/coverage/default/12.edn_alert_test.542919676 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 58695777 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:25:27 PM PST 24 |
| Finished | Jan 14 12:25:31 PM PST 24 |
| Peak memory | 204924 kb |
| Host | smart-9e1ae952-ec04-476e-affe-9b8c36f48a16 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542919676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.542919676 |
| Directory | /workspace/12.edn_alert_test/latest |
| Test location | /workspace/coverage/default/12.edn_disable.2351892828 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 71906724 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:25:22 PM PST 24 |
| Finished | Jan 14 12:25:25 PM PST 24 |
| Peak memory | 206084 kb |
| Host | smart-124f9b55-a184-4557-b657-d581ad68ee0c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351892828 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2351892828 |
| Directory | /workspace/12.edn_disable/latest |
| Test location | /workspace/coverage/default/12.edn_disable_auto_req_mode.147004481 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 41807970 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:25:51 PM PST 24 |
| Finished | Jan 14 12:25:53 PM PST 24 |
| Peak memory | 214376 kb |
| Host | smart-874c5872-d830-4593-8fa3-ba6e16f593eb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147004481 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_di sable_auto_req_mode.147004481 |
| Directory | /workspace/12.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/12.edn_err.1246822136 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 19129674 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:25:42 PM PST 24 |
| Finished | Jan 14 12:25:45 PM PST 24 |
| Peak memory | 215444 kb |
| Host | smart-597dc36c-0878-400c-99d5-e2d91d33f820 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1246822136 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1246822136 |
| Directory | /workspace/12.edn_err/latest |
| Test location | /workspace/coverage/default/12.edn_genbits.29588696 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 99436772 ps |
| CPU time | 1.16 seconds |
| Started | Jan 14 12:25:20 PM PST 24 |
| Finished | Jan 14 12:25:32 PM PST 24 |
| Peak memory | 205332 kb |
| Host | smart-b2b299b2-5f96-418b-87f5-8f3a14cca962 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=29588696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.29588696 |
| Directory | /workspace/12.edn_genbits/latest |
| Test location | /workspace/coverage/default/12.edn_intr.1435056923 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 18966014 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:25:43 PM PST 24 |
| Finished | Jan 14 12:25:45 PM PST 24 |
| Peak memory | 214448 kb |
| Host | smart-ec78e52f-acdd-4718-8229-2fec379a9da1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1435056923 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1435056923 |
| Directory | /workspace/12.edn_intr/latest |
| Test location | /workspace/coverage/default/12.edn_smoke.1221783273 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 47338972 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:25:41 PM PST 24 |
| Finished | Jan 14 12:25:45 PM PST 24 |
| Peak memory | 204760 kb |
| Host | smart-3ef4bb7d-1cfa-477d-8f65-1513a18aa29f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1221783273 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1221783273 |
| Directory | /workspace/12.edn_smoke/latest |
| Test location | /workspace/coverage/default/12.edn_stress_all.988024109 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 84723014 ps |
| CPU time | 2.25 seconds |
| Started | Jan 14 12:25:49 PM PST 24 |
| Finished | Jan 14 12:25:52 PM PST 24 |
| Peak memory | 205292 kb |
| Host | smart-0db499f0-59cb-47ca-86d0-091d6c2e0720 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988024109 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.988024109 |
| Directory | /workspace/12.edn_stress_all/latest |
| Test location | /workspace/coverage/default/12.edn_stress_all_with_rand_reset.392772080 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 19843260377 ps |
| CPU time | 424.89 seconds |
| Started | Jan 14 12:25:53 PM PST 24 |
| Finished | Jan 14 12:32:58 PM PST 24 |
| Peak memory | 214804 kb |
| Host | smart-7ed87ae5-987f-428b-adeb-9f2c15eafb7a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392772080 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.392772080 |
| Directory | /workspace/12.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/120.edn_genbits.1142973139 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 23631501 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:27:10 PM PST 24 |
| Finished | Jan 14 12:27:12 PM PST 24 |
| Peak memory | 205236 kb |
| Host | smart-4521f9f3-0cc8-44ba-957a-96e9017533f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1142973139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1142973139 |
| Directory | /workspace/120.edn_genbits/latest |
| Test location | /workspace/coverage/default/121.edn_genbits.4268869567 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 16950331 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:26:44 PM PST 24 |
| Finished | Jan 14 12:26:45 PM PST 24 |
| Peak memory | 204752 kb |
| Host | smart-0b2148e9-5c4c-46dc-a719-8a8000c9f30c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4268869567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.4268869567 |
| Directory | /workspace/121.edn_genbits/latest |
| Test location | /workspace/coverage/default/122.edn_genbits.3482559501 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 17264139 ps |
| CPU time | 1.09 seconds |
| Started | Jan 14 12:26:53 PM PST 24 |
| Finished | Jan 14 12:26:55 PM PST 24 |
| Peak memory | 205252 kb |
| Host | smart-1ca3171a-6809-43b7-aad1-611a623b9666 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3482559501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3482559501 |
| Directory | /workspace/122.edn_genbits/latest |
| Test location | /workspace/coverage/default/123.edn_genbits.1061868576 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 23832191 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:26:59 PM PST 24 |
| Finished | Jan 14 12:27:01 PM PST 24 |
| Peak memory | 205140 kb |
| Host | smart-523b1499-3191-4a5a-a2fe-c1890eaa5625 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1061868576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1061868576 |
| Directory | /workspace/123.edn_genbits/latest |
| Test location | /workspace/coverage/default/124.edn_genbits.167149645 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 36262711 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:27:06 PM PST 24 |
| Finished | Jan 14 12:27:07 PM PST 24 |
| Peak memory | 204972 kb |
| Host | smart-d7d3a0ee-a3a4-4a15-bdb2-e58fc480913e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=167149645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.167149645 |
| Directory | /workspace/124.edn_genbits/latest |
| Test location | /workspace/coverage/default/125.edn_genbits.199304773 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 97173299 ps |
| CPU time | 1.14 seconds |
| Started | Jan 14 12:26:48 PM PST 24 |
| Finished | Jan 14 12:26:50 PM PST 24 |
| Peak memory | 205456 kb |
| Host | smart-27c09a49-9a0e-493c-b3aa-b4fbc86d614a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=199304773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.199304773 |
| Directory | /workspace/125.edn_genbits/latest |
| Test location | /workspace/coverage/default/126.edn_genbits.4028171077 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 68630797 ps |
| CPU time | 2.64 seconds |
| Started | Jan 14 12:27:05 PM PST 24 |
| Finished | Jan 14 12:27:09 PM PST 24 |
| Peak memory | 214016 kb |
| Host | smart-27dbc733-f549-438f-9aba-3af9a65373cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028171077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.4028171077 |
| Directory | /workspace/126.edn_genbits/latest |
| Test location | /workspace/coverage/default/127.edn_genbits.267306458 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 284878663 ps |
| CPU time | 2.98 seconds |
| Started | Jan 14 12:26:43 PM PST 24 |
| Finished | Jan 14 12:26:47 PM PST 24 |
| Peak memory | 213952 kb |
| Host | smart-37879b7b-9a74-439e-bef3-b873c675a16d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=267306458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.267306458 |
| Directory | /workspace/127.edn_genbits/latest |
| Test location | /workspace/coverage/default/128.edn_genbits.2257184937 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 63270470 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:26:54 PM PST 24 |
| Finished | Jan 14 12:26:56 PM PST 24 |
| Peak memory | 205372 kb |
| Host | smart-f328340f-f750-4dbe-8f49-795dcb4a19e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2257184937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2257184937 |
| Directory | /workspace/128.edn_genbits/latest |
| Test location | /workspace/coverage/default/129.edn_genbits.2247308920 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 16087043 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:27:05 PM PST 24 |
| Finished | Jan 14 12:27:07 PM PST 24 |
| Peak memory | 214024 kb |
| Host | smart-67238cc8-7237-4083-9e74-e8a1de5c8b6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2247308920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2247308920 |
| Directory | /workspace/129.edn_genbits/latest |
| Test location | /workspace/coverage/default/13.edn_alert.4284470865 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 65317020 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:25:30 PM PST 24 |
| Finished | Jan 14 12:25:36 PM PST 24 |
| Peak memory | 204456 kb |
| Host | smart-f2586490-600d-4b00-a861-5387a516d2e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4284470865 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.4284470865 |
| Directory | /workspace/13.edn_alert/latest |
| Test location | /workspace/coverage/default/13.edn_alert_test.2513695640 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 73025951 ps |
| CPU time | 0.74 seconds |
| Started | Jan 14 12:25:28 PM PST 24 |
| Finished | Jan 14 12:25:31 PM PST 24 |
| Peak memory | 204068 kb |
| Host | smart-ea44d662-a1c3-48ac-a706-01c294d9ad4d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513695640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2513695640 |
| Directory | /workspace/13.edn_alert_test/latest |
| Test location | /workspace/coverage/default/13.edn_disable.103793670 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 13204467 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:25:34 PM PST 24 |
| Finished | Jan 14 12:25:38 PM PST 24 |
| Peak memory | 214356 kb |
| Host | smart-a39df5a8-081c-4303-82d4-43f89bbb85cf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103793670 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.103793670 |
| Directory | /workspace/13.edn_disable/latest |
| Test location | /workspace/coverage/default/13.edn_disable_auto_req_mode.1226572643 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 73387955 ps |
| CPU time | 1.11 seconds |
| Started | Jan 14 12:25:49 PM PST 24 |
| Finished | Jan 14 12:25:51 PM PST 24 |
| Peak memory | 214428 kb |
| Host | smart-cf264bf1-bcdb-448f-8730-7505c37925a0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226572643 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d isable_auto_req_mode.1226572643 |
| Directory | /workspace/13.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/13.edn_err.2527835233 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 33507296 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:25:27 PM PST 24 |
| Finished | Jan 14 12:25:32 PM PST 24 |
| Peak memory | 221392 kb |
| Host | smart-bf7d3eef-2efd-48fd-aa3b-69e3cd016ba3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527835233 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2527835233 |
| Directory | /workspace/13.edn_err/latest |
| Test location | /workspace/coverage/default/13.edn_genbits.194646599 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 19532019 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:25:33 PM PST 24 |
| Finished | Jan 14 12:25:38 PM PST 24 |
| Peak memory | 204944 kb |
| Host | smart-d1a6899c-6f7f-40bf-9e8c-6623ed83bccd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=194646599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.194646599 |
| Directory | /workspace/13.edn_genbits/latest |
| Test location | /workspace/coverage/default/13.edn_smoke.1868952817 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 40911960 ps |
| CPU time | 0.87 seconds |
| Started | Jan 14 12:25:56 PM PST 24 |
| Finished | Jan 14 12:25:57 PM PST 24 |
| Peak memory | 204716 kb |
| Host | smart-6aa3cfe0-4f0d-42ca-a7cc-7bbffc92eeec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1868952817 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1868952817 |
| Directory | /workspace/13.edn_smoke/latest |
| Test location | /workspace/coverage/default/13.edn_stress_all.823288828 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 159815410 ps |
| CPU time | 3.27 seconds |
| Started | Jan 14 12:25:57 PM PST 24 |
| Finished | Jan 14 12:26:02 PM PST 24 |
| Peak memory | 205800 kb |
| Host | smart-e0fcc366-23c8-4627-b924-a2f51677da77 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823288828 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.823288828 |
| Directory | /workspace/13.edn_stress_all/latest |
| Test location | /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3623237404 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 400037271961 ps |
| CPU time | 1967.7 seconds |
| Started | Jan 14 12:25:51 PM PST 24 |
| Finished | Jan 14 12:58:39 PM PST 24 |
| Peak memory | 223236 kb |
| Host | smart-90d40c3c-9a5b-47e8-8639-27203493f96d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623237404 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3623237404 |
| Directory | /workspace/13.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/130.edn_genbits.702993068 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 24878902 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:26:47 PM PST 24 |
| Finished | Jan 14 12:26:49 PM PST 24 |
| Peak memory | 205140 kb |
| Host | smart-1c11bc02-78cc-4bf2-8e83-2446b6fa2b19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=702993068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.702993068 |
| Directory | /workspace/130.edn_genbits/latest |
| Test location | /workspace/coverage/default/131.edn_genbits.290472474 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 33201157 ps |
| CPU time | 1.13 seconds |
| Started | Jan 14 12:27:01 PM PST 24 |
| Finished | Jan 14 12:27:04 PM PST 24 |
| Peak memory | 205200 kb |
| Host | smart-0e6f56ad-8698-4f67-abba-522bca833e39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=290472474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.290472474 |
| Directory | /workspace/131.edn_genbits/latest |
| Test location | /workspace/coverage/default/132.edn_genbits.4288385715 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 23885031 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:27:11 PM PST 24 |
| Finished | Jan 14 12:27:12 PM PST 24 |
| Peak memory | 204920 kb |
| Host | smart-381f5794-033a-4cf2-86aa-4007a999777b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4288385715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.4288385715 |
| Directory | /workspace/132.edn_genbits/latest |
| Test location | /workspace/coverage/default/133.edn_genbits.1045829912 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 23650495 ps |
| CPU time | 1.26 seconds |
| Started | Jan 14 12:26:59 PM PST 24 |
| Finished | Jan 14 12:27:01 PM PST 24 |
| Peak memory | 214120 kb |
| Host | smart-d7d91f66-3b23-4e54-9d46-6dc6eed22135 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1045829912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1045829912 |
| Directory | /workspace/133.edn_genbits/latest |
| Test location | /workspace/coverage/default/134.edn_genbits.1833978255 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 36350678 ps |
| CPU time | 1.07 seconds |
| Started | Jan 14 12:26:55 PM PST 24 |
| Finished | Jan 14 12:26:57 PM PST 24 |
| Peak memory | 214128 kb |
| Host | smart-e3bbf80a-1707-4c9b-a8f9-1b3f8c1e07b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1833978255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1833978255 |
| Directory | /workspace/134.edn_genbits/latest |
| Test location | /workspace/coverage/default/135.edn_genbits.4161323560 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 115293123 ps |
| CPU time | 1.82 seconds |
| Started | Jan 14 12:27:03 PM PST 24 |
| Finished | Jan 14 12:27:06 PM PST 24 |
| Peak memory | 214024 kb |
| Host | smart-6634acb4-4e19-43de-b1e9-fa62e17009c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4161323560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.4161323560 |
| Directory | /workspace/135.edn_genbits/latest |
| Test location | /workspace/coverage/default/136.edn_genbits.3521999284 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 12597788 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:27:01 PM PST 24 |
| Finished | Jan 14 12:27:03 PM PST 24 |
| Peak memory | 205076 kb |
| Host | smart-1758ca8f-eff0-41b6-9dad-1b606e9a581d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521999284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3521999284 |
| Directory | /workspace/136.edn_genbits/latest |
| Test location | /workspace/coverage/default/138.edn_genbits.1790787253 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 18154871 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:26:56 PM PST 24 |
| Finished | Jan 14 12:26:59 PM PST 24 |
| Peak memory | 204800 kb |
| Host | smart-8d3e0573-bd3c-4c63-b442-9fcd951e9933 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1790787253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1790787253 |
| Directory | /workspace/138.edn_genbits/latest |
| Test location | /workspace/coverage/default/139.edn_genbits.685011933 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 139902397 ps |
| CPU time | 1.37 seconds |
| Started | Jan 14 12:26:44 PM PST 24 |
| Finished | Jan 14 12:26:46 PM PST 24 |
| Peak memory | 214020 kb |
| Host | smart-559c8142-a3b3-4b2a-8592-46226c67408b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=685011933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.685011933 |
| Directory | /workspace/139.edn_genbits/latest |
| Test location | /workspace/coverage/default/14.edn_alert.1116441135 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 16260351 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:25:54 PM PST 24 |
| Finished | Jan 14 12:25:56 PM PST 24 |
| Peak memory | 205180 kb |
| Host | smart-7a54a3f0-2004-4626-b78f-c187b2c45cd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1116441135 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1116441135 |
| Directory | /workspace/14.edn_alert/latest |
| Test location | /workspace/coverage/default/14.edn_alert_test.3383621647 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 16947356 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:25:43 PM PST 24 |
| Finished | Jan 14 12:25:45 PM PST 24 |
| Peak memory | 204360 kb |
| Host | smart-5bb3b112-2dc8-4bd8-b8e0-10efb306ea94 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383621647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3383621647 |
| Directory | /workspace/14.edn_alert_test/latest |
| Test location | /workspace/coverage/default/14.edn_disable.1586150431 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 43283012 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:25:27 PM PST 24 |
| Finished | Jan 14 12:25:31 PM PST 24 |
| Peak memory | 214208 kb |
| Host | smart-9d739c0b-8656-413f-9d37-32de5e2d0fd2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586150431 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1586150431 |
| Directory | /workspace/14.edn_disable/latest |
| Test location | /workspace/coverage/default/14.edn_genbits.1295452942 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 80975771 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:25:27 PM PST 24 |
| Finished | Jan 14 12:25:32 PM PST 24 |
| Peak memory | 205204 kb |
| Host | smart-4f80bcf8-1b79-4045-9ed9-44d925215092 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1295452942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1295452942 |
| Directory | /workspace/14.edn_genbits/latest |
| Test location | /workspace/coverage/default/14.edn_intr.574558249 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 44714211 ps |
| CPU time | 0.79 seconds |
| Started | Jan 14 12:25:25 PM PST 24 |
| Finished | Jan 14 12:25:31 PM PST 24 |
| Peak memory | 214348 kb |
| Host | smart-068ecfda-8b87-4be1-80ac-a02f743eaa20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=574558249 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.574558249 |
| Directory | /workspace/14.edn_intr/latest |
| Test location | /workspace/coverage/default/14.edn_smoke.2961403900 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 45050385 ps |
| CPU time | 0.84 seconds |
| Started | Jan 14 12:25:23 PM PST 24 |
| Finished | Jan 14 12:25:29 PM PST 24 |
| Peak memory | 204672 kb |
| Host | smart-6fa5ee14-3b7e-4834-9bb4-3f75d3515479 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961403900 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2961403900 |
| Directory | /workspace/14.edn_smoke/latest |
| Test location | /workspace/coverage/default/14.edn_stress_all.812679153 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 866496622 ps |
| CPU time | 4.01 seconds |
| Started | Jan 14 12:25:27 PM PST 24 |
| Finished | Jan 14 12:25:35 PM PST 24 |
| Peak memory | 205812 kb |
| Host | smart-5c09ebdf-a2cb-48b2-bd95-4d400cfcb07f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812679153 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.812679153 |
| Directory | /workspace/14.edn_stress_all/latest |
| Test location | /workspace/coverage/default/140.edn_genbits.2795675740 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 81467221 ps |
| CPU time | 1.16 seconds |
| Started | Jan 14 12:27:01 PM PST 24 |
| Finished | Jan 14 12:27:03 PM PST 24 |
| Peak memory | 205140 kb |
| Host | smart-0c8ebee1-c45f-4187-90da-ff4b5afc30a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2795675740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2795675740 |
| Directory | /workspace/140.edn_genbits/latest |
| Test location | /workspace/coverage/default/141.edn_genbits.4055941568 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 26555024 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:26:47 PM PST 24 |
| Finished | Jan 14 12:26:48 PM PST 24 |
| Peak memory | 205104 kb |
| Host | smart-add26d51-91ae-4048-b3ef-03c8a768850d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4055941568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.4055941568 |
| Directory | /workspace/141.edn_genbits/latest |
| Test location | /workspace/coverage/default/142.edn_genbits.3388591321 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 63526659 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:27:01 PM PST 24 |
| Finished | Jan 14 12:27:04 PM PST 24 |
| Peak memory | 205076 kb |
| Host | smart-2753f768-c19e-4e62-a476-6cce05afc80f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3388591321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3388591321 |
| Directory | /workspace/142.edn_genbits/latest |
| Test location | /workspace/coverage/default/145.edn_genbits.1751650073 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 16139834 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:26:55 PM PST 24 |
| Finished | Jan 14 12:26:57 PM PST 24 |
| Peak memory | 205072 kb |
| Host | smart-82737bad-62a9-45f6-b98b-20a73384b510 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1751650073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1751650073 |
| Directory | /workspace/145.edn_genbits/latest |
| Test location | /workspace/coverage/default/146.edn_genbits.696109577 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 75769939 ps |
| CPU time | 1 seconds |
| Started | Jan 14 12:26:58 PM PST 24 |
| Finished | Jan 14 12:27:00 PM PST 24 |
| Peak memory | 214052 kb |
| Host | smart-dde3107c-d1c4-413b-b9fd-aafcb4cc4968 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=696109577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.696109577 |
| Directory | /workspace/146.edn_genbits/latest |
| Test location | /workspace/coverage/default/147.edn_genbits.1773205983 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 42524800 ps |
| CPU time | 1.18 seconds |
| Started | Jan 14 12:26:43 PM PST 24 |
| Finished | Jan 14 12:26:45 PM PST 24 |
| Peak memory | 214104 kb |
| Host | smart-0850d4ce-3630-40b7-89cd-eeddaf32168d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1773205983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1773205983 |
| Directory | /workspace/147.edn_genbits/latest |
| Test location | /workspace/coverage/default/148.edn_genbits.3606646054 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 48269157 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:27:14 PM PST 24 |
| Finished | Jan 14 12:27:16 PM PST 24 |
| Peak memory | 205060 kb |
| Host | smart-0de7d442-e24a-4575-ac52-bab8f1038751 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3606646054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3606646054 |
| Directory | /workspace/148.edn_genbits/latest |
| Test location | /workspace/coverage/default/149.edn_genbits.3866703700 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 45625317 ps |
| CPU time | 1.13 seconds |
| Started | Jan 14 12:27:02 PM PST 24 |
| Finished | Jan 14 12:27:05 PM PST 24 |
| Peak memory | 205400 kb |
| Host | smart-4e9e52e1-943f-4f25-9c48-3cb860abfb39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3866703700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3866703700 |
| Directory | /workspace/149.edn_genbits/latest |
| Test location | /workspace/coverage/default/15.edn_alert.2654134026 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 66723469 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:25:39 PM PST 24 |
| Finished | Jan 14 12:25:45 PM PST 24 |
| Peak memory | 205916 kb |
| Host | smart-48eb0cdc-cebd-403f-b120-1ed895033315 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2654134026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2654134026 |
| Directory | /workspace/15.edn_alert/latest |
| Test location | /workspace/coverage/default/15.edn_alert_test.1928402485 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 18908052 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:26:00 PM PST 24 |
| Finished | Jan 14 12:26:02 PM PST 24 |
| Peak memory | 204512 kb |
| Host | smart-b0bb79f6-5884-42d4-b5ef-d68d0c83654f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928402485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1928402485 |
| Directory | /workspace/15.edn_alert_test/latest |
| Test location | /workspace/coverage/default/15.edn_disable.1761232299 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 19721649 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:25:58 PM PST 24 |
| Finished | Jan 14 12:26:00 PM PST 24 |
| Peak memory | 214280 kb |
| Host | smart-0d6cb48c-72f6-4f05-82fb-41c1b1eb29fa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761232299 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1761232299 |
| Directory | /workspace/15.edn_disable/latest |
| Test location | /workspace/coverage/default/15.edn_err.440755426 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 72198201 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:25:57 PM PST 24 |
| Finished | Jan 14 12:25:59 PM PST 24 |
| Peak memory | 216084 kb |
| Host | smart-7b583518-9518-4910-bf9e-760efbb74a40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=440755426 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.440755426 |
| Directory | /workspace/15.edn_err/latest |
| Test location | /workspace/coverage/default/15.edn_genbits.1397707655 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 35424610 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:25:53 PM PST 24 |
| Finished | Jan 14 12:25:54 PM PST 24 |
| Peak memory | 205408 kb |
| Host | smart-28545d75-8c65-4c8f-ac5a-e91f0e089af0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1397707655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1397707655 |
| Directory | /workspace/15.edn_genbits/latest |
| Test location | /workspace/coverage/default/15.edn_intr.3115814414 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 34187652 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:26:00 PM PST 24 |
| Finished | Jan 14 12:26:02 PM PST 24 |
| Peak memory | 214228 kb |
| Host | smart-3301546c-eac2-4b17-8674-06766e8a9fff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3115814414 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3115814414 |
| Directory | /workspace/15.edn_intr/latest |
| Test location | /workspace/coverage/default/15.edn_smoke.590239119 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 23307356 ps |
| CPU time | 1.07 seconds |
| Started | Jan 14 12:25:56 PM PST 24 |
| Finished | Jan 14 12:25:58 PM PST 24 |
| Peak memory | 204956 kb |
| Host | smart-1896a7da-b75a-4528-8c20-c151c7359ae4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=590239119 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.590239119 |
| Directory | /workspace/15.edn_smoke/latest |
| Test location | /workspace/coverage/default/15.edn_stress_all.1511420273 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 94294705 ps |
| CPU time | 2.39 seconds |
| Started | Jan 14 12:25:31 PM PST 24 |
| Finished | Jan 14 12:25:38 PM PST 24 |
| Peak memory | 205836 kb |
| Host | smart-1248f821-9e03-43a1-ac6d-493110610e67 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511420273 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1511420273 |
| Directory | /workspace/15.edn_stress_all/latest |
| Test location | /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2018082549 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 243781523860 ps |
| CPU time | 449.34 seconds |
| Started | Jan 14 12:25:31 PM PST 24 |
| Finished | Jan 14 12:33:05 PM PST 24 |
| Peak memory | 221812 kb |
| Host | smart-cdb0d784-bdcc-4ce0-a0cd-69f4086be228 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018082549 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2018082549 |
| Directory | /workspace/15.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/150.edn_genbits.1019884900 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 58795096 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:27:04 PM PST 24 |
| Finished | Jan 14 12:27:06 PM PST 24 |
| Peak memory | 205492 kb |
| Host | smart-b42430ab-cf26-4132-a17f-e6b1cb36ade3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1019884900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1019884900 |
| Directory | /workspace/150.edn_genbits/latest |
| Test location | /workspace/coverage/default/151.edn_genbits.317461198 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 16687612 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:26:38 PM PST 24 |
| Finished | Jan 14 12:26:40 PM PST 24 |
| Peak memory | 204736 kb |
| Host | smart-0767de93-eafd-4a42-9baa-b64592629de7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=317461198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.317461198 |
| Directory | /workspace/151.edn_genbits/latest |
| Test location | /workspace/coverage/default/152.edn_genbits.1999930133 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 80286255 ps |
| CPU time | 1.13 seconds |
| Started | Jan 14 12:26:44 PM PST 24 |
| Finished | Jan 14 12:26:46 PM PST 24 |
| Peak memory | 213652 kb |
| Host | smart-696fd425-0dc7-4dd2-9b5f-0138c4a25f65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1999930133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1999930133 |
| Directory | /workspace/152.edn_genbits/latest |
| Test location | /workspace/coverage/default/153.edn_genbits.336545075 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 20649839 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:26:47 PM PST 24 |
| Finished | Jan 14 12:26:49 PM PST 24 |
| Peak memory | 205408 kb |
| Host | smart-2f28e0ed-c326-4a4c-9915-7011a2befc80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=336545075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.336545075 |
| Directory | /workspace/153.edn_genbits/latest |
| Test location | /workspace/coverage/default/154.edn_genbits.335595057 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 43262410 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:26:48 PM PST 24 |
| Finished | Jan 14 12:26:50 PM PST 24 |
| Peak memory | 205592 kb |
| Host | smart-8233e57e-ca5e-47af-98b6-cc29cb49e950 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=335595057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.335595057 |
| Directory | /workspace/154.edn_genbits/latest |
| Test location | /workspace/coverage/default/155.edn_genbits.3059747979 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 43759796 ps |
| CPU time | 1.14 seconds |
| Started | Jan 14 12:26:55 PM PST 24 |
| Finished | Jan 14 12:26:57 PM PST 24 |
| Peak memory | 205428 kb |
| Host | smart-55498004-f833-4120-93a2-98fb6638162e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3059747979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3059747979 |
| Directory | /workspace/155.edn_genbits/latest |
| Test location | /workspace/coverage/default/156.edn_genbits.3027018871 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 22328100 ps |
| CPU time | 1.09 seconds |
| Started | Jan 14 12:26:50 PM PST 24 |
| Finished | Jan 14 12:26:52 PM PST 24 |
| Peak memory | 205204 kb |
| Host | smart-dc470162-5a77-41c3-a09c-f1ec224b152e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3027018871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3027018871 |
| Directory | /workspace/156.edn_genbits/latest |
| Test location | /workspace/coverage/default/157.edn_genbits.2110865705 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 103278928 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:26:55 PM PST 24 |
| Finished | Jan 14 12:26:57 PM PST 24 |
| Peak memory | 205508 kb |
| Host | smart-82ccd9ad-9ce3-4be8-9810-0e201874d0c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2110865705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2110865705 |
| Directory | /workspace/157.edn_genbits/latest |
| Test location | /workspace/coverage/default/158.edn_genbits.2768243626 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 165080375 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:27:00 PM PST 24 |
| Finished | Jan 14 12:27:02 PM PST 24 |
| Peak memory | 205076 kb |
| Host | smart-f61be30c-5561-4a6a-aa87-a85e76bf8f12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2768243626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2768243626 |
| Directory | /workspace/158.edn_genbits/latest |
| Test location | /workspace/coverage/default/159.edn_genbits.130846692 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 31026822 ps |
| CPU time | 1.53 seconds |
| Started | Jan 14 12:26:55 PM PST 24 |
| Finished | Jan 14 12:26:57 PM PST 24 |
| Peak memory | 214096 kb |
| Host | smart-9d7b3a4b-2b52-453c-8e85-4298c16465e5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=130846692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.130846692 |
| Directory | /workspace/159.edn_genbits/latest |
| Test location | /workspace/coverage/default/16.edn_alert.550187234 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 36274819 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:25:55 PM PST 24 |
| Finished | Jan 14 12:25:57 PM PST 24 |
| Peak memory | 205228 kb |
| Host | smart-0999686d-495c-49b3-bc0f-a5dd7888b376 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=550187234 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.550187234 |
| Directory | /workspace/16.edn_alert/latest |
| Test location | /workspace/coverage/default/16.edn_alert_test.555390753 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 30385953 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:25:50 PM PST 24 |
| Finished | Jan 14 12:25:51 PM PST 24 |
| Peak memory | 204464 kb |
| Host | smart-d6174c59-a0fd-4549-a3c9-072db37e6597 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555390753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.555390753 |
| Directory | /workspace/16.edn_alert_test/latest |
| Test location | /workspace/coverage/default/16.edn_disable_auto_req_mode.4113246245 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 48740974 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:25:35 PM PST 24 |
| Finished | Jan 14 12:25:39 PM PST 24 |
| Peak memory | 214236 kb |
| Host | smart-b5cf499f-b31b-4123-b9bf-8061680008b0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113246245 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d isable_auto_req_mode.4113246245 |
| Directory | /workspace/16.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/16.edn_err.438065667 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 21964439 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:25:51 PM PST 24 |
| Finished | Jan 14 12:25:53 PM PST 24 |
| Peak memory | 215668 kb |
| Host | smart-8574396f-97c4-4209-a546-0bf1387f3072 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=438065667 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.438065667 |
| Directory | /workspace/16.edn_err/latest |
| Test location | /workspace/coverage/default/16.edn_smoke.1613464872 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 33524146 ps |
| CPU time | 0.8 seconds |
| Started | Jan 14 12:26:02 PM PST 24 |
| Finished | Jan 14 12:26:05 PM PST 24 |
| Peak memory | 204576 kb |
| Host | smart-030272b3-fe10-4b7c-9239-3db8f8f866fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1613464872 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1613464872 |
| Directory | /workspace/16.edn_smoke/latest |
| Test location | /workspace/coverage/default/16.edn_stress_all.3538979625 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 163333232 ps |
| CPU time | 2.2 seconds |
| Started | Jan 14 12:25:58 PM PST 24 |
| Finished | Jan 14 12:26:01 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-075c79f8-5ced-4028-b641-6ceae74d17ae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538979625 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3538979625 |
| Directory | /workspace/16.edn_stress_all/latest |
| Test location | /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1673094968 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 67365025146 ps |
| CPU time | 1611.27 seconds |
| Started | Jan 14 12:25:52 PM PST 24 |
| Finished | Jan 14 12:52:44 PM PST 24 |
| Peak memory | 220152 kb |
| Host | smart-5243d7f9-6c9e-4888-8118-b063d4083532 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673094968 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1673094968 |
| Directory | /workspace/16.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/160.edn_genbits.52356454 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 55466970 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:26:44 PM PST 24 |
| Finished | Jan 14 12:26:45 PM PST 24 |
| Peak memory | 204852 kb |
| Host | smart-0335c674-32c1-40a9-81fe-75cec7f9876d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52356454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.52356454 |
| Directory | /workspace/160.edn_genbits/latest |
| Test location | /workspace/coverage/default/161.edn_genbits.1878336392 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 50129890 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:26:56 PM PST 24 |
| Finished | Jan 14 12:26:57 PM PST 24 |
| Peak memory | 204860 kb |
| Host | smart-9ecacf75-07c3-490d-98b6-aa3bcb3d9dfc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1878336392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1878336392 |
| Directory | /workspace/161.edn_genbits/latest |
| Test location | /workspace/coverage/default/162.edn_genbits.1544882593 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 30948257 ps |
| CPU time | 1.01 seconds |
| Started | Jan 14 12:26:54 PM PST 24 |
| Finished | Jan 14 12:26:56 PM PST 24 |
| Peak memory | 205444 kb |
| Host | smart-af0ac822-5ad3-470c-bed7-027dabe8f04d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1544882593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1544882593 |
| Directory | /workspace/162.edn_genbits/latest |
| Test location | /workspace/coverage/default/164.edn_genbits.437833295 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 53531049 ps |
| CPU time | 1.14 seconds |
| Started | Jan 14 12:26:54 PM PST 24 |
| Finished | Jan 14 12:26:56 PM PST 24 |
| Peak memory | 205416 kb |
| Host | smart-bcc542c4-096a-4324-9616-6f11c1623190 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=437833295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.437833295 |
| Directory | /workspace/164.edn_genbits/latest |
| Test location | /workspace/coverage/default/165.edn_genbits.4154969017 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 19729071 ps |
| CPU time | 1.24 seconds |
| Started | Jan 14 12:26:56 PM PST 24 |
| Finished | Jan 14 12:26:59 PM PST 24 |
| Peak memory | 205728 kb |
| Host | smart-99af4c23-8267-4ace-ab49-705b03003ff5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4154969017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.4154969017 |
| Directory | /workspace/165.edn_genbits/latest |
| Test location | /workspace/coverage/default/166.edn_genbits.513806356 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 32475046 ps |
| CPU time | 1.16 seconds |
| Started | Jan 14 12:26:53 PM PST 24 |
| Finished | Jan 14 12:26:55 PM PST 24 |
| Peak memory | 205624 kb |
| Host | smart-ce5f6590-6895-4e2c-be3f-406b5b8b2c19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=513806356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.513806356 |
| Directory | /workspace/166.edn_genbits/latest |
| Test location | /workspace/coverage/default/167.edn_genbits.1681584664 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 22962336 ps |
| CPU time | 1.1 seconds |
| Started | Jan 14 12:26:56 PM PST 24 |
| Finished | Jan 14 12:26:59 PM PST 24 |
| Peak memory | 205196 kb |
| Host | smart-44f51390-f74c-48a7-96b6-77f901e2fbed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1681584664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1681584664 |
| Directory | /workspace/167.edn_genbits/latest |
| Test location | /workspace/coverage/default/169.edn_genbits.2321935061 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 23986632 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:26:52 PM PST 24 |
| Finished | Jan 14 12:26:54 PM PST 24 |
| Peak memory | 205544 kb |
| Host | smart-31445c5b-0c39-47dc-ae97-407f74bd717b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2321935061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2321935061 |
| Directory | /workspace/169.edn_genbits/latest |
| Test location | /workspace/coverage/default/17.edn_alert_test.994460777 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 18137440 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:26:08 PM PST 24 |
| Finished | Jan 14 12:26:10 PM PST 24 |
| Peak memory | 204396 kb |
| Host | smart-d5eb6a86-2692-4021-a221-3a1e158b550b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994460777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.994460777 |
| Directory | /workspace/17.edn_alert_test/latest |
| Test location | /workspace/coverage/default/17.edn_disable.1939595707 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 21398855 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:26:02 PM PST 24 |
| Finished | Jan 14 12:26:05 PM PST 24 |
| Peak memory | 214304 kb |
| Host | smart-1cd91916-32f4-4d37-875a-69cae5d0772a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939595707 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1939595707 |
| Directory | /workspace/17.edn_disable/latest |
| Test location | /workspace/coverage/default/17.edn_disable_auto_req_mode.2838776701 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 82119577 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:25:41 PM PST 24 |
| Finished | Jan 14 12:25:45 PM PST 24 |
| Peak memory | 214276 kb |
| Host | smart-6714dc0e-8483-48a0-8346-ecfd4b863f76 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838776701 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d isable_auto_req_mode.2838776701 |
| Directory | /workspace/17.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/17.edn_err.4244664603 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 26519609 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:25:51 PM PST 24 |
| Finished | Jan 14 12:25:53 PM PST 24 |
| Peak memory | 221116 kb |
| Host | smart-878e05c2-3e7c-421c-9bc3-d43a02a96242 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4244664603 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.4244664603 |
| Directory | /workspace/17.edn_err/latest |
| Test location | /workspace/coverage/default/17.edn_intr.3516262085 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 20506948 ps |
| CPU time | 1 seconds |
| Started | Jan 14 12:25:29 PM PST 24 |
| Finished | Jan 14 12:25:36 PM PST 24 |
| Peak memory | 214380 kb |
| Host | smart-16d3866c-352f-41e2-aee7-fdfbe8284b3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3516262085 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3516262085 |
| Directory | /workspace/17.edn_intr/latest |
| Test location | /workspace/coverage/default/17.edn_smoke.4255363560 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 16503557 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:25:47 PM PST 24 |
| Finished | Jan 14 12:25:49 PM PST 24 |
| Peak memory | 204724 kb |
| Host | smart-bcc13bf6-6629-4da0-80bd-22c04621496d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4255363560 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.4255363560 |
| Directory | /workspace/17.edn_smoke/latest |
| Test location | /workspace/coverage/default/17.edn_stress_all.1205617477 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 289362879 ps |
| CPU time | 3.32 seconds |
| Started | Jan 14 12:26:05 PM PST 24 |
| Finished | Jan 14 12:26:09 PM PST 24 |
| Peak memory | 205556 kb |
| Host | smart-a3e3f287-b492-466d-b775-474e6ab6a138 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205617477 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1205617477 |
| Directory | /workspace/17.edn_stress_all/latest |
| Test location | /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2720388846 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 23157249259 ps |
| CPU time | 528.77 seconds |
| Started | Jan 14 12:25:43 PM PST 24 |
| Finished | Jan 14 12:34:33 PM PST 24 |
| Peak memory | 215480 kb |
| Host | smart-3869ffff-cfd1-4b89-ac63-44eb2cc79dec |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720388846 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2720388846 |
| Directory | /workspace/17.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/170.edn_genbits.1458945626 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 85499076 ps |
| CPU time | 1.11 seconds |
| Started | Jan 14 12:26:54 PM PST 24 |
| Finished | Jan 14 12:26:56 PM PST 24 |
| Peak memory | 205356 kb |
| Host | smart-09059db1-5203-4fba-b42c-c59aeb2b44da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1458945626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1458945626 |
| Directory | /workspace/170.edn_genbits/latest |
| Test location | /workspace/coverage/default/171.edn_genbits.4028229274 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 61373149 ps |
| CPU time | 1.09 seconds |
| Started | Jan 14 12:27:08 PM PST 24 |
| Finished | Jan 14 12:27:09 PM PST 24 |
| Peak memory | 205656 kb |
| Host | smart-93bcddd3-feec-4b37-bdef-96217ccc87ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4028229274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.4028229274 |
| Directory | /workspace/171.edn_genbits/latest |
| Test location | /workspace/coverage/default/172.edn_genbits.3292861851 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 60212496 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:26:56 PM PST 24 |
| Finished | Jan 14 12:26:58 PM PST 24 |
| Peak memory | 205168 kb |
| Host | smart-ca07b7df-cd5b-4a68-89fc-e81214609baa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3292861851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3292861851 |
| Directory | /workspace/172.edn_genbits/latest |
| Test location | /workspace/coverage/default/173.edn_genbits.2058611573 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 20710718 ps |
| CPU time | 1.11 seconds |
| Started | Jan 14 12:26:52 PM PST 24 |
| Finished | Jan 14 12:26:53 PM PST 24 |
| Peak memory | 214084 kb |
| Host | smart-8cd5efc1-22bc-46de-b128-a5e86e762dbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2058611573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2058611573 |
| Directory | /workspace/173.edn_genbits/latest |
| Test location | /workspace/coverage/default/174.edn_genbits.2692566698 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 26839115 ps |
| CPU time | 1.07 seconds |
| Started | Jan 14 12:27:06 PM PST 24 |
| Finished | Jan 14 12:27:08 PM PST 24 |
| Peak memory | 205468 kb |
| Host | smart-5a051eb7-c09d-446d-9c39-29f6106e0fdf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2692566698 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2692566698 |
| Directory | /workspace/174.edn_genbits/latest |
| Test location | /workspace/coverage/default/175.edn_genbits.1004167095 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 25139689 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:27:10 PM PST 24 |
| Finished | Jan 14 12:27:12 PM PST 24 |
| Peak memory | 204928 kb |
| Host | smart-e6890dff-2394-4bfa-a244-d3bc0af0dd74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1004167095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1004167095 |
| Directory | /workspace/175.edn_genbits/latest |
| Test location | /workspace/coverage/default/176.edn_genbits.61134106 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 41942157 ps |
| CPU time | 1.21 seconds |
| Started | Jan 14 12:27:09 PM PST 24 |
| Finished | Jan 14 12:27:10 PM PST 24 |
| Peak memory | 205516 kb |
| Host | smart-bfb4dc5d-11b0-490e-9171-cdcb390fa2b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=61134106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.61134106 |
| Directory | /workspace/176.edn_genbits/latest |
| Test location | /workspace/coverage/default/177.edn_genbits.3493150169 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 41038560 ps |
| CPU time | 1.1 seconds |
| Started | Jan 14 12:26:48 PM PST 24 |
| Finished | Jan 14 12:26:50 PM PST 24 |
| Peak memory | 205136 kb |
| Host | smart-7acc3b30-82a8-4377-a338-8a8ca84514ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493150169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.3493150169 |
| Directory | /workspace/177.edn_genbits/latest |
| Test location | /workspace/coverage/default/178.edn_genbits.3676019052 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 54106533 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:26:47 PM PST 24 |
| Finished | Jan 14 12:26:49 PM PST 24 |
| Peak memory | 205276 kb |
| Host | smart-e625614f-5045-429b-9b35-15b79866c30f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3676019052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3676019052 |
| Directory | /workspace/178.edn_genbits/latest |
| Test location | /workspace/coverage/default/179.edn_genbits.1404507488 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 88123968 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:26:47 PM PST 24 |
| Finished | Jan 14 12:26:49 PM PST 24 |
| Peak memory | 204752 kb |
| Host | smart-81644cf3-8104-413a-8c1b-e522509ece29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1404507488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1404507488 |
| Directory | /workspace/179.edn_genbits/latest |
| Test location | /workspace/coverage/default/18.edn_alert.1668292919 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 30399575 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:07 PM PST 24 |
| Finished | Jan 14 12:26:08 PM PST 24 |
| Peak memory | 205064 kb |
| Host | smart-b8bb1ca0-e18b-4b1a-9943-257f2778ec5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1668292919 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1668292919 |
| Directory | /workspace/18.edn_alert/latest |
| Test location | /workspace/coverage/default/18.edn_alert_test.2701917839 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 18839975 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:26:00 PM PST 24 |
| Finished | Jan 14 12:26:02 PM PST 24 |
| Peak memory | 205064 kb |
| Host | smart-ec14c4e9-b3a5-465d-a86e-d02f7fdf463d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701917839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2701917839 |
| Directory | /workspace/18.edn_alert_test/latest |
| Test location | /workspace/coverage/default/18.edn_disable_auto_req_mode.1695083944 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 23307049 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:25:37 PM PST 24 |
| Finished | Jan 14 12:25:40 PM PST 24 |
| Peak memory | 214452 kb |
| Host | smart-3da2b21b-8b38-48ee-87ad-6c349450b4b0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695083944 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d isable_auto_req_mode.1695083944 |
| Directory | /workspace/18.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/18.edn_err.1350820714 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 39993680 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:25:51 PM PST 24 |
| Finished | Jan 14 12:25:53 PM PST 24 |
| Peak memory | 215684 kb |
| Host | smart-e2c29970-850e-4595-ad1e-c31a14d938d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1350820714 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.1350820714 |
| Directory | /workspace/18.edn_err/latest |
| Test location | /workspace/coverage/default/18.edn_genbits.2110605681 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 48065378 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:25:56 PM PST 24 |
| Finished | Jan 14 12:25:58 PM PST 24 |
| Peak memory | 204748 kb |
| Host | smart-ff3f0c86-3b77-412c-acbf-17624f74cc8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2110605681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.2110605681 |
| Directory | /workspace/18.edn_genbits/latest |
| Test location | /workspace/coverage/default/18.edn_intr.2707820376 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 25891237 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:25:57 PM PST 24 |
| Finished | Jan 14 12:26:04 PM PST 24 |
| Peak memory | 214308 kb |
| Host | smart-3ab4c1d1-5c91-435a-8be9-d84605df7420 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2707820376 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2707820376 |
| Directory | /workspace/18.edn_intr/latest |
| Test location | /workspace/coverage/default/18.edn_smoke.3941652838 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 17363157 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:07 PM PST 24 |
| Finished | Jan 14 12:26:08 PM PST 24 |
| Peak memory | 204636 kb |
| Host | smart-f88ef313-7032-48da-b35d-90f3439a5245 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3941652838 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3941652838 |
| Directory | /workspace/18.edn_smoke/latest |
| Test location | /workspace/coverage/default/18.edn_stress_all.1258803447 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 97598267 ps |
| CPU time | 2.47 seconds |
| Started | Jan 14 12:26:02 PM PST 24 |
| Finished | Jan 14 12:26:06 PM PST 24 |
| Peak memory | 205816 kb |
| Host | smart-ed0c9a78-65c8-44a7-93f2-dea388b223b9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258803447 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1258803447 |
| Directory | /workspace/18.edn_stress_all/latest |
| Test location | /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1460100126 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 19090178450 ps |
| CPU time | 282.71 seconds |
| Started | Jan 14 12:25:50 PM PST 24 |
| Finished | Jan 14 12:30:33 PM PST 24 |
| Peak memory | 215544 kb |
| Host | smart-de0af549-e74e-4266-94df-d071672e455c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460100126 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1460100126 |
| Directory | /workspace/18.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/180.edn_genbits.3992461548 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 73215569 ps |
| CPU time | 1.12 seconds |
| Started | Jan 14 12:27:06 PM PST 24 |
| Finished | Jan 14 12:27:08 PM PST 24 |
| Peak memory | 214088 kb |
| Host | smart-c36d8c20-4c0d-486b-a478-3f8d8633a85c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3992461548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3992461548 |
| Directory | /workspace/180.edn_genbits/latest |
| Test location | /workspace/coverage/default/181.edn_genbits.2558336236 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 70262737 ps |
| CPU time | 1.11 seconds |
| Started | Jan 14 12:26:44 PM PST 24 |
| Finished | Jan 14 12:26:46 PM PST 24 |
| Peak memory | 214076 kb |
| Host | smart-bf42eafe-f4c7-4dc7-ac69-47ff6f19cf64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2558336236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2558336236 |
| Directory | /workspace/181.edn_genbits/latest |
| Test location | /workspace/coverage/default/182.edn_genbits.124775629 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 23622129 ps |
| CPU time | 1.17 seconds |
| Started | Jan 14 12:26:36 PM PST 24 |
| Finished | Jan 14 12:26:38 PM PST 24 |
| Peak memory | 213944 kb |
| Host | smart-ec86182b-d1be-4a1d-93c5-0f058bab7bc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=124775629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.124775629 |
| Directory | /workspace/182.edn_genbits/latest |
| Test location | /workspace/coverage/default/183.edn_genbits.1095889729 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 44239003 ps |
| CPU time | 1.15 seconds |
| Started | Jan 14 12:26:51 PM PST 24 |
| Finished | Jan 14 12:26:52 PM PST 24 |
| Peak memory | 214048 kb |
| Host | smart-98d7c339-7e1b-4687-aa02-b478cee7e94a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1095889729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1095889729 |
| Directory | /workspace/183.edn_genbits/latest |
| Test location | /workspace/coverage/default/184.edn_genbits.375664909 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 4576115969 ps |
| CPU time | 73.78 seconds |
| Started | Jan 14 12:27:03 PM PST 24 |
| Finished | Jan 14 12:28:18 PM PST 24 |
| Peak memory | 214268 kb |
| Host | smart-c17b09a8-392f-4f19-84f8-678769961357 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=375664909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.375664909 |
| Directory | /workspace/184.edn_genbits/latest |
| Test location | /workspace/coverage/default/185.edn_genbits.4253851424 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 34998549 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:26:57 PM PST 24 |
| Finished | Jan 14 12:26:59 PM PST 24 |
| Peak memory | 214060 kb |
| Host | smart-f2e90c7a-b162-4a4e-900b-76943c2a8108 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4253851424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.4253851424 |
| Directory | /workspace/185.edn_genbits/latest |
| Test location | /workspace/coverage/default/186.edn_genbits.2118204134 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 53849446 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:26:53 PM PST 24 |
| Finished | Jan 14 12:26:55 PM PST 24 |
| Peak memory | 214084 kb |
| Host | smart-2fda2917-4f26-4370-b5a4-8490de3c5f3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2118204134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2118204134 |
| Directory | /workspace/186.edn_genbits/latest |
| Test location | /workspace/coverage/default/187.edn_genbits.2336909848 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 15145448 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:26:58 PM PST 24 |
| Finished | Jan 14 12:27:00 PM PST 24 |
| Peak memory | 204928 kb |
| Host | smart-6ca7d227-335d-4c0e-ba9a-5b894c2ceba1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2336909848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2336909848 |
| Directory | /workspace/187.edn_genbits/latest |
| Test location | /workspace/coverage/default/188.edn_genbits.1317399014 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 31361239 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:27:02 PM PST 24 |
| Finished | Jan 14 12:27:05 PM PST 24 |
| Peak memory | 205400 kb |
| Host | smart-f2722fe2-e500-4bc5-a54e-5a8f1673508b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1317399014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1317399014 |
| Directory | /workspace/188.edn_genbits/latest |
| Test location | /workspace/coverage/default/189.edn_genbits.1793735504 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 25273786 ps |
| CPU time | 1.14 seconds |
| Started | Jan 14 12:27:02 PM PST 24 |
| Finished | Jan 14 12:27:05 PM PST 24 |
| Peak memory | 214160 kb |
| Host | smart-2b40b7f8-9ea6-4f8b-955f-b017127e88eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1793735504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1793735504 |
| Directory | /workspace/189.edn_genbits/latest |
| Test location | /workspace/coverage/default/19.edn_alert_test.2230549148 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 80136316 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:25:51 PM PST 24 |
| Finished | Jan 14 12:25:53 PM PST 24 |
| Peak memory | 205100 kb |
| Host | smart-4a037aba-d7e0-4757-93dc-25534d2dc40d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230549148 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2230549148 |
| Directory | /workspace/19.edn_alert_test/latest |
| Test location | /workspace/coverage/default/19.edn_disable.2902769115 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 37239158 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 12:26:01 PM PST 24 |
| Finished | Jan 14 12:26:03 PM PST 24 |
| Peak memory | 214308 kb |
| Host | smart-e3ea164b-4b18-47bf-bbd2-01280e1c1992 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902769115 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2902769115 |
| Directory | /workspace/19.edn_disable/latest |
| Test location | /workspace/coverage/default/19.edn_disable_auto_req_mode.2096504542 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 89059709 ps |
| CPU time | 1.12 seconds |
| Started | Jan 14 12:25:52 PM PST 24 |
| Finished | Jan 14 12:25:54 PM PST 24 |
| Peak memory | 214392 kb |
| Host | smart-0eca4886-ffd2-4655-87b0-77446455fafb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096504542 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d isable_auto_req_mode.2096504542 |
| Directory | /workspace/19.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/19.edn_err.209166460 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 108667310 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:25:57 PM PST 24 |
| Finished | Jan 14 12:25:58 PM PST 24 |
| Peak memory | 217080 kb |
| Host | smart-62f8a41c-93b5-4823-b8fc-c1fc20f85c91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=209166460 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.209166460 |
| Directory | /workspace/19.edn_err/latest |
| Test location | /workspace/coverage/default/19.edn_genbits.3263861558 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 26407143 ps |
| CPU time | 1.33 seconds |
| Started | Jan 14 12:25:55 PM PST 24 |
| Finished | Jan 14 12:25:58 PM PST 24 |
| Peak memory | 214204 kb |
| Host | smart-eec933ce-b4c5-4d50-8cbf-0ba413478f9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263861558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3263861558 |
| Directory | /workspace/19.edn_genbits/latest |
| Test location | /workspace/coverage/default/19.edn_intr.4165199277 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 19599291 ps |
| CPU time | 1.05 seconds |
| Started | Jan 14 12:26:01 PM PST 24 |
| Finished | Jan 14 12:26:03 PM PST 24 |
| Peak memory | 214484 kb |
| Host | smart-9733a430-ba7f-4390-9fa4-534eda4d9cbd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4165199277 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.4165199277 |
| Directory | /workspace/19.edn_intr/latest |
| Test location | /workspace/coverage/default/19.edn_smoke.1978440346 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 43584560 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 12:26:12 PM PST 24 |
| Finished | Jan 14 12:26:14 PM PST 24 |
| Peak memory | 204664 kb |
| Host | smart-6372bdd9-9b14-4343-92b7-b6a93ddcc3d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1978440346 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1978440346 |
| Directory | /workspace/19.edn_smoke/latest |
| Test location | /workspace/coverage/default/19.edn_stress_all.2594942249 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 561182029 ps |
| CPU time | 3.04 seconds |
| Started | Jan 14 12:25:51 PM PST 24 |
| Finished | Jan 14 12:25:55 PM PST 24 |
| Peak memory | 205676 kb |
| Host | smart-67efcd8b-b974-47fb-b4cc-6e8ad34744fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594942249 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2594942249 |
| Directory | /workspace/19.edn_stress_all/latest |
| Test location | /workspace/coverage/default/19.edn_stress_all_with_rand_reset.420930398 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 65370076631 ps |
| CPU time | 1689.99 seconds |
| Started | Jan 14 12:25:57 PM PST 24 |
| Finished | Jan 14 12:54:08 PM PST 24 |
| Peak memory | 219800 kb |
| Host | smart-5257a51a-4b43-4b2b-8c9e-f808e3076726 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420930398 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.420930398 |
| Directory | /workspace/19.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/190.edn_genbits.1242100845 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 18635411 ps |
| CPU time | 1.11 seconds |
| Started | Jan 14 12:26:40 PM PST 24 |
| Finished | Jan 14 12:26:41 PM PST 24 |
| Peak memory | 214052 kb |
| Host | smart-e0b5b0bd-b9ac-4ecb-946d-71f9eec3ef76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1242100845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1242100845 |
| Directory | /workspace/190.edn_genbits/latest |
| Test location | /workspace/coverage/default/191.edn_genbits.2850640249 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 15136377 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:26:53 PM PST 24 |
| Finished | Jan 14 12:26:55 PM PST 24 |
| Peak memory | 205280 kb |
| Host | smart-5eaf3a7a-c90f-431d-8479-4bf6d4f832c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2850640249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2850640249 |
| Directory | /workspace/191.edn_genbits/latest |
| Test location | /workspace/coverage/default/192.edn_genbits.938309961 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 69905587 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:26:54 PM PST 24 |
| Finished | Jan 14 12:26:55 PM PST 24 |
| Peak memory | 205388 kb |
| Host | smart-0df18ba2-26b7-4f4f-bb0a-975386b97fed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=938309961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.938309961 |
| Directory | /workspace/192.edn_genbits/latest |
| Test location | /workspace/coverage/default/193.edn_genbits.826785835 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 19555234 ps |
| CPU time | 1.09 seconds |
| Started | Jan 14 12:26:57 PM PST 24 |
| Finished | Jan 14 12:26:59 PM PST 24 |
| Peak memory | 214072 kb |
| Host | smart-5d5c7c44-7949-43c0-a5f9-3fe993229827 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=826785835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.826785835 |
| Directory | /workspace/193.edn_genbits/latest |
| Test location | /workspace/coverage/default/194.edn_genbits.3897514179 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 53288856 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:27:13 PM PST 24 |
| Finished | Jan 14 12:27:14 PM PST 24 |
| Peak memory | 205024 kb |
| Host | smart-49ee3e7e-5ec8-44ab-b31e-7ba06a62a5cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3897514179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3897514179 |
| Directory | /workspace/194.edn_genbits/latest |
| Test location | /workspace/coverage/default/195.edn_genbits.4275675954 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 39884470 ps |
| CPU time | 1.11 seconds |
| Started | Jan 14 12:26:50 PM PST 24 |
| Finished | Jan 14 12:26:52 PM PST 24 |
| Peak memory | 205404 kb |
| Host | smart-01db08de-8795-4a4f-b808-391c6911a03d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4275675954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.4275675954 |
| Directory | /workspace/195.edn_genbits/latest |
| Test location | /workspace/coverage/default/196.edn_genbits.2568138691 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 33950651 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:26:52 PM PST 24 |
| Finished | Jan 14 12:26:53 PM PST 24 |
| Peak memory | 204972 kb |
| Host | smart-7b7d86a8-1a45-4f91-8f15-483d17fe28d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2568138691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2568138691 |
| Directory | /workspace/196.edn_genbits/latest |
| Test location | /workspace/coverage/default/197.edn_genbits.387689648 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 22324713 ps |
| CPU time | 1.01 seconds |
| Started | Jan 14 12:27:05 PM PST 24 |
| Finished | Jan 14 12:27:06 PM PST 24 |
| Peak memory | 205264 kb |
| Host | smart-df0f5cd2-9f84-4d07-9d37-6e886c01a7e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=387689648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.387689648 |
| Directory | /workspace/197.edn_genbits/latest |
| Test location | /workspace/coverage/default/198.edn_genbits.206717182 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 13632231 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:26:36 PM PST 24 |
| Finished | Jan 14 12:26:38 PM PST 24 |
| Peak memory | 204756 kb |
| Host | smart-8a53d3c1-a4a1-4d60-abe9-b333c0e67b55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=206717182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.206717182 |
| Directory | /workspace/198.edn_genbits/latest |
| Test location | /workspace/coverage/default/199.edn_genbits.2531619350 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 18709292 ps |
| CPU time | 1.21 seconds |
| Started | Jan 14 12:27:12 PM PST 24 |
| Finished | Jan 14 12:27:14 PM PST 24 |
| Peak memory | 205396 kb |
| Host | smart-2e68ab69-9019-4631-8fed-b83efb05f5fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2531619350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2531619350 |
| Directory | /workspace/199.edn_genbits/latest |
| Test location | /workspace/coverage/default/2.edn_alert.2249504872 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 26654095 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:25:26 PM PST 24 |
| Finished | Jan 14 12:25:31 PM PST 24 |
| Peak memory | 205040 kb |
| Host | smart-0bb6db57-9114-4f2c-af5b-efe5250f8418 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2249504872 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2249504872 |
| Directory | /workspace/2.edn_alert/latest |
| Test location | /workspace/coverage/default/2.edn_alert_test.3592573900 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 20977584 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:25:37 PM PST 24 |
| Finished | Jan 14 12:25:40 PM PST 24 |
| Peak memory | 204988 kb |
| Host | smart-46c743b5-910d-4410-bd84-4fd9805aed8a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592573900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3592573900 |
| Directory | /workspace/2.edn_alert_test/latest |
| Test location | /workspace/coverage/default/2.edn_disable.398746814 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 35997431 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 12:25:24 PM PST 24 |
| Finished | Jan 14 12:25:31 PM PST 24 |
| Peak memory | 214312 kb |
| Host | smart-41409252-49d7-4083-9575-eabe01473e3f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398746814 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.398746814 |
| Directory | /workspace/2.edn_disable/latest |
| Test location | /workspace/coverage/default/2.edn_disable_auto_req_mode.2898248419 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 51004321 ps |
| CPU time | 1.01 seconds |
| Started | Jan 14 12:25:52 PM PST 24 |
| Finished | Jan 14 12:25:54 PM PST 24 |
| Peak memory | 214464 kb |
| Host | smart-b4caf36a-7e94-49fa-a32a-ee4ab856358d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898248419 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di sable_auto_req_mode.2898248419 |
| Directory | /workspace/2.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/2.edn_err.877910000 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 30234359 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:25:41 PM PST 24 |
| Finished | Jan 14 12:25:45 PM PST 24 |
| Peak memory | 215864 kb |
| Host | smart-60107b4e-9309-409a-83da-01e8f9818e7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=877910000 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.877910000 |
| Directory | /workspace/2.edn_err/latest |
| Test location | /workspace/coverage/default/2.edn_genbits.3317277730 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 25460927 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:25:51 PM PST 24 |
| Finished | Jan 14 12:25:52 PM PST 24 |
| Peak memory | 205200 kb |
| Host | smart-0fc87b92-0431-4c9a-9f3f-945943c1db77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3317277730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.3317277730 |
| Directory | /workspace/2.edn_genbits/latest |
| Test location | /workspace/coverage/default/2.edn_intr.2958854872 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 60194318 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 12:25:14 PM PST 24 |
| Finished | Jan 14 12:25:15 PM PST 24 |
| Peak memory | 214136 kb |
| Host | smart-75ffd5d8-1e2a-4e11-a322-2f870ff7301a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2958854872 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2958854872 |
| Directory | /workspace/2.edn_intr/latest |
| Test location | /workspace/coverage/default/2.edn_regwen.223551273 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 14996691 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:25:17 PM PST 24 |
| Finished | Jan 14 12:25:19 PM PST 24 |
| Peak memory | 204640 kb |
| Host | smart-969eb03d-80ee-43b9-8cc0-4cfc11a04cb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=223551273 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.223551273 |
| Directory | /workspace/2.edn_regwen/latest |
| Test location | /workspace/coverage/default/2.edn_smoke.2189758075 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 13510769 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:25:12 PM PST 24 |
| Finished | Jan 14 12:25:14 PM PST 24 |
| Peak memory | 204668 kb |
| Host | smart-2d832989-e332-4722-8cda-49a3c148f785 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2189758075 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2189758075 |
| Directory | /workspace/2.edn_smoke/latest |
| Test location | /workspace/coverage/default/2.edn_stress_all.1373779422 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 618196339 ps |
| CPU time | 3.64 seconds |
| Started | Jan 14 12:25:40 PM PST 24 |
| Finished | Jan 14 12:25:48 PM PST 24 |
| Peak memory | 205472 kb |
| Host | smart-47186d72-1f90-4462-81a6-2991e507456a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373779422 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1373779422 |
| Directory | /workspace/2.edn_stress_all/latest |
| Test location | /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3367005993 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 111752886269 ps |
| CPU time | 570.37 seconds |
| Started | Jan 14 12:25:30 PM PST 24 |
| Finished | Jan 14 12:35:06 PM PST 24 |
| Peak memory | 214452 kb |
| Host | smart-336323a6-f2ec-41ae-ac4a-3fee00a92a95 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367005993 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3367005993 |
| Directory | /workspace/2.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.edn_alert.2186663021 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 66221235 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:25:59 PM PST 24 |
| Finished | Jan 14 12:26:00 PM PST 24 |
| Peak memory | 205064 kb |
| Host | smart-60fcf00e-0aaa-48d3-a1df-14000ae9870b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2186663021 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2186663021 |
| Directory | /workspace/20.edn_alert/latest |
| Test location | /workspace/coverage/default/20.edn_alert_test.2504373262 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 49871708 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:25:52 PM PST 24 |
| Finished | Jan 14 12:25:54 PM PST 24 |
| Peak memory | 204348 kb |
| Host | smart-b4ab2cc9-5bfc-499c-92b4-021440e4a3a2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504373262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2504373262 |
| Directory | /workspace/20.edn_alert_test/latest |
| Test location | /workspace/coverage/default/20.edn_disable_auto_req_mode.2525327035 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 28070755 ps |
| CPU time | 1.08 seconds |
| Started | Jan 14 12:26:02 PM PST 24 |
| Finished | Jan 14 12:26:05 PM PST 24 |
| Peak memory | 214432 kb |
| Host | smart-98f18219-0e83-43c0-a783-d7c1db6328bc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525327035 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d isable_auto_req_mode.2525327035 |
| Directory | /workspace/20.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/20.edn_err.2668438035 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 23541460 ps |
| CPU time | 1.01 seconds |
| Started | Jan 14 12:25:48 PM PST 24 |
| Finished | Jan 14 12:25:50 PM PST 24 |
| Peak memory | 221108 kb |
| Host | smart-8378e900-cfaa-46dd-917a-56544bb59329 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2668438035 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2668438035 |
| Directory | /workspace/20.edn_err/latest |
| Test location | /workspace/coverage/default/20.edn_intr.3118884861 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 20785718 ps |
| CPU time | 1 seconds |
| Started | Jan 14 12:26:17 PM PST 24 |
| Finished | Jan 14 12:26:20 PM PST 24 |
| Peak memory | 214256 kb |
| Host | smart-4ad96a45-6fee-4297-b065-c76cefedf6ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3118884861 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3118884861 |
| Directory | /workspace/20.edn_intr/latest |
| Test location | /workspace/coverage/default/20.edn_smoke.1705811201 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 32741667 ps |
| CPU time | 0.79 seconds |
| Started | Jan 14 12:25:53 PM PST 24 |
| Finished | Jan 14 12:25:54 PM PST 24 |
| Peak memory | 204544 kb |
| Host | smart-67b67a55-57ab-4806-a4c4-35b58157664a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1705811201 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1705811201 |
| Directory | /workspace/20.edn_smoke/latest |
| Test location | /workspace/coverage/default/20.edn_stress_all.1915610033 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1116550411 ps |
| CPU time | 3.51 seconds |
| Started | Jan 14 12:25:54 PM PST 24 |
| Finished | Jan 14 12:25:58 PM PST 24 |
| Peak memory | 205792 kb |
| Host | smart-f38fbe05-661e-4aec-bf06-bb8b4171cbae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915610033 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1915610033 |
| Directory | /workspace/20.edn_stress_all/latest |
| Test location | /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3597567209 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 5437419173 ps |
| CPU time | 33.65 seconds |
| Started | Jan 14 12:25:54 PM PST 24 |
| Finished | Jan 14 12:26:28 PM PST 24 |
| Peak memory | 215532 kb |
| Host | smart-d0d18ff3-fcea-4517-8d0b-dcb534671304 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597567209 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3597567209 |
| Directory | /workspace/20.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/200.edn_genbits.2423127966 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 437996416 ps |
| CPU time | 3.19 seconds |
| Started | Jan 14 12:27:11 PM PST 24 |
| Finished | Jan 14 12:27:15 PM PST 24 |
| Peak memory | 214044 kb |
| Host | smart-33a377c1-ad82-4f51-b5e3-108e54794c38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2423127966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2423127966 |
| Directory | /workspace/200.edn_genbits/latest |
| Test location | /workspace/coverage/default/201.edn_genbits.2548859627 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 19963642 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:26:51 PM PST 24 |
| Finished | Jan 14 12:26:53 PM PST 24 |
| Peak memory | 204916 kb |
| Host | smart-68aac6d5-5380-4171-acf6-22d799fbeb27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2548859627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2548859627 |
| Directory | /workspace/201.edn_genbits/latest |
| Test location | /workspace/coverage/default/202.edn_genbits.3323770736 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 54295852 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 12:26:57 PM PST 24 |
| Finished | Jan 14 12:26:59 PM PST 24 |
| Peak memory | 205020 kb |
| Host | smart-3305075d-abff-4bc3-9b5d-514258ba5168 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3323770736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3323770736 |
| Directory | /workspace/202.edn_genbits/latest |
| Test location | /workspace/coverage/default/203.edn_genbits.3650730905 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 44185478 ps |
| CPU time | 0.87 seconds |
| Started | Jan 14 12:26:58 PM PST 24 |
| Finished | Jan 14 12:27:00 PM PST 24 |
| Peak memory | 204980 kb |
| Host | smart-c48c1ee9-eb56-459e-a08d-59cb0940c827 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3650730905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3650730905 |
| Directory | /workspace/203.edn_genbits/latest |
| Test location | /workspace/coverage/default/204.edn_genbits.3411924781 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 58807260 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:26:55 PM PST 24 |
| Finished | Jan 14 12:26:57 PM PST 24 |
| Peak memory | 205292 kb |
| Host | smart-b650655c-b05f-4569-bc4a-d62a53b2e07b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3411924781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3411924781 |
| Directory | /workspace/204.edn_genbits/latest |
| Test location | /workspace/coverage/default/205.edn_genbits.2531219862 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 20012445 ps |
| CPU time | 1.09 seconds |
| Started | Jan 14 12:27:16 PM PST 24 |
| Finished | Jan 14 12:27:22 PM PST 24 |
| Peak memory | 214060 kb |
| Host | smart-4d949059-3e5c-45af-a8d5-1ef6c48a934a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2531219862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.2531219862 |
| Directory | /workspace/205.edn_genbits/latest |
| Test location | /workspace/coverage/default/206.edn_genbits.1897005756 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 66463890 ps |
| CPU time | 1.64 seconds |
| Started | Jan 14 12:27:14 PM PST 24 |
| Finished | Jan 14 12:27:16 PM PST 24 |
| Peak memory | 214116 kb |
| Host | smart-3c55d6ae-390f-4fbc-ac39-7f0724c51f02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1897005756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1897005756 |
| Directory | /workspace/206.edn_genbits/latest |
| Test location | /workspace/coverage/default/207.edn_genbits.940452346 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 26663992 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:26:55 PM PST 24 |
| Finished | Jan 14 12:27:02 PM PST 24 |
| Peak memory | 205440 kb |
| Host | smart-8cd7fa40-46ee-4e48-85b3-35e4f4810de2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=940452346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.940452346 |
| Directory | /workspace/207.edn_genbits/latest |
| Test location | /workspace/coverage/default/208.edn_genbits.3400486042 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 17506601 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:27:15 PM PST 24 |
| Finished | Jan 14 12:27:17 PM PST 24 |
| Peak memory | 204744 kb |
| Host | smart-8548c5ab-4cc4-4734-a062-824690d5762f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3400486042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3400486042 |
| Directory | /workspace/208.edn_genbits/latest |
| Test location | /workspace/coverage/default/209.edn_genbits.3330576037 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 114588875 ps |
| CPU time | 1.07 seconds |
| Started | Jan 14 12:27:03 PM PST 24 |
| Finished | Jan 14 12:27:05 PM PST 24 |
| Peak memory | 205656 kb |
| Host | smart-45369d17-d3e2-4598-85b6-a45326f13604 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3330576037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3330576037 |
| Directory | /workspace/209.edn_genbits/latest |
| Test location | /workspace/coverage/default/21.edn_alert.1411136298 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 58455348 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:25:57 PM PST 24 |
| Finished | Jan 14 12:25:58 PM PST 24 |
| Peak memory | 205132 kb |
| Host | smart-dc9c4d92-95f1-48a4-98fa-3b77120b352c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1411136298 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1411136298 |
| Directory | /workspace/21.edn_alert/latest |
| Test location | /workspace/coverage/default/21.edn_alert_test.347052022 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 53570409 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:25:49 PM PST 24 |
| Finished | Jan 14 12:25:51 PM PST 24 |
| Peak memory | 204444 kb |
| Host | smart-c88ca24b-d697-470d-9108-503e514f5ae2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347052022 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.347052022 |
| Directory | /workspace/21.edn_alert_test/latest |
| Test location | /workspace/coverage/default/21.edn_disable_auto_req_mode.3465398851 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 106253037 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:26:00 PM PST 24 |
| Finished | Jan 14 12:26:02 PM PST 24 |
| Peak memory | 214288 kb |
| Host | smart-a2b2d434-5a4a-4d49-92c4-3e415ab85e19 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465398851 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d isable_auto_req_mode.3465398851 |
| Directory | /workspace/21.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/21.edn_err.2145463609 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 40836275 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:25:55 PM PST 24 |
| Finished | Jan 14 12:25:57 PM PST 24 |
| Peak memory | 221468 kb |
| Host | smart-9edbac5e-04e1-406d-8820-46ad8e43ef8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2145463609 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2145463609 |
| Directory | /workspace/21.edn_err/latest |
| Test location | /workspace/coverage/default/21.edn_intr.4040316640 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 19855119 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:26:01 PM PST 24 |
| Finished | Jan 14 12:26:03 PM PST 24 |
| Peak memory | 214376 kb |
| Host | smart-0bf7a24f-b974-449a-9cff-f6a7758416b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4040316640 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.4040316640 |
| Directory | /workspace/21.edn_intr/latest |
| Test location | /workspace/coverage/default/21.edn_smoke.3816894583 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 12110039 ps |
| CPU time | 0.84 seconds |
| Started | Jan 14 12:26:00 PM PST 24 |
| Finished | Jan 14 12:26:02 PM PST 24 |
| Peak memory | 204624 kb |
| Host | smart-d3bc4b51-d89b-466d-8edb-f86831a02912 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3816894583 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3816894583 |
| Directory | /workspace/21.edn_smoke/latest |
| Test location | /workspace/coverage/default/21.edn_stress_all.2941035441 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 343489838 ps |
| CPU time | 1.94 seconds |
| Started | Jan 14 12:26:01 PM PST 24 |
| Finished | Jan 14 12:26:05 PM PST 24 |
| Peak memory | 205424 kb |
| Host | smart-da579b77-2fe7-41d2-9556-eb6ecfc1e1b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941035441 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2941035441 |
| Directory | /workspace/21.edn_stress_all/latest |
| Test location | /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1299943241 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 155663910788 ps |
| CPU time | 1551.58 seconds |
| Started | Jan 14 12:25:56 PM PST 24 |
| Finished | Jan 14 12:51:48 PM PST 24 |
| Peak memory | 218452 kb |
| Host | smart-5cc4fa21-4238-4199-bcca-116f84416961 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299943241 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1299943241 |
| Directory | /workspace/21.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/210.edn_genbits.760789010 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 33110264 ps |
| CPU time | 1.18 seconds |
| Started | Jan 14 12:27:09 PM PST 24 |
| Finished | Jan 14 12:27:11 PM PST 24 |
| Peak memory | 205620 kb |
| Host | smart-f1854384-9c0a-425b-a602-e7c6521604b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=760789010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.760789010 |
| Directory | /workspace/210.edn_genbits/latest |
| Test location | /workspace/coverage/default/211.edn_genbits.3757516289 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 14818584 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:26:42 PM PST 24 |
| Finished | Jan 14 12:26:43 PM PST 24 |
| Peak memory | 204840 kb |
| Host | smart-45d4bfd1-4653-40a8-843d-70d19b189fd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3757516289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3757516289 |
| Directory | /workspace/211.edn_genbits/latest |
| Test location | /workspace/coverage/default/212.edn_genbits.912513660 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 114269241 ps |
| CPU time | 2.52 seconds |
| Started | Jan 14 12:27:15 PM PST 24 |
| Finished | Jan 14 12:27:18 PM PST 24 |
| Peak memory | 214056 kb |
| Host | smart-5a0f0c9c-3c61-4482-bcb7-bd57105bf87e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=912513660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.912513660 |
| Directory | /workspace/212.edn_genbits/latest |
| Test location | /workspace/coverage/default/213.edn_genbits.3320542325 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 63309913 ps |
| CPU time | 1.09 seconds |
| Started | Jan 14 12:26:51 PM PST 24 |
| Finished | Jan 14 12:26:52 PM PST 24 |
| Peak memory | 205580 kb |
| Host | smart-0c589abd-02f3-4790-8da6-f034ba4c2476 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3320542325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3320542325 |
| Directory | /workspace/213.edn_genbits/latest |
| Test location | /workspace/coverage/default/214.edn_genbits.2658870446 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 98811638 ps |
| CPU time | 1.04 seconds |
| Started | Jan 14 12:27:15 PM PST 24 |
| Finished | Jan 14 12:27:17 PM PST 24 |
| Peak memory | 205084 kb |
| Host | smart-d156c3b9-f36c-4c53-8c2d-0f202262e80d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2658870446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2658870446 |
| Directory | /workspace/214.edn_genbits/latest |
| Test location | /workspace/coverage/default/215.edn_genbits.548919306 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 77215732 ps |
| CPU time | 1.04 seconds |
| Started | Jan 14 12:27:09 PM PST 24 |
| Finished | Jan 14 12:27:10 PM PST 24 |
| Peak memory | 205124 kb |
| Host | smart-09384e4f-0c4e-4025-8c93-0c598415fa67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=548919306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.548919306 |
| Directory | /workspace/215.edn_genbits/latest |
| Test location | /workspace/coverage/default/216.edn_genbits.930481497 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 23924400 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:27:07 PM PST 24 |
| Finished | Jan 14 12:27:08 PM PST 24 |
| Peak memory | 204856 kb |
| Host | smart-9cc0a8ce-8552-4f34-9f83-bef524c6c8cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=930481497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.930481497 |
| Directory | /workspace/216.edn_genbits/latest |
| Test location | /workspace/coverage/default/217.edn_genbits.1486036189 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 27453999 ps |
| CPU time | 1.08 seconds |
| Started | Jan 14 12:26:55 PM PST 24 |
| Finished | Jan 14 12:26:57 PM PST 24 |
| Peak memory | 205500 kb |
| Host | smart-b043ba82-5b11-4fbd-83da-91bda5b386af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1486036189 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1486036189 |
| Directory | /workspace/217.edn_genbits/latest |
| Test location | /workspace/coverage/default/218.edn_genbits.3558936334 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 17330958 ps |
| CPU time | 1.13 seconds |
| Started | Jan 14 12:27:10 PM PST 24 |
| Finished | Jan 14 12:27:12 PM PST 24 |
| Peak memory | 205432 kb |
| Host | smart-63a30b62-4f06-49fd-8ebb-55b4debe2c86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3558936334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3558936334 |
| Directory | /workspace/218.edn_genbits/latest |
| Test location | /workspace/coverage/default/219.edn_genbits.69094045 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 41572840 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:26:56 PM PST 24 |
| Finished | Jan 14 12:27:03 PM PST 24 |
| Peak memory | 205580 kb |
| Host | smart-eb1168bb-f92d-4dec-92eb-f3d45a4412f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=69094045 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.69094045 |
| Directory | /workspace/219.edn_genbits/latest |
| Test location | /workspace/coverage/default/22.edn_alert.90505544 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 213236368 ps |
| CPU time | 1.01 seconds |
| Started | Jan 14 12:26:12 PM PST 24 |
| Finished | Jan 14 12:26:14 PM PST 24 |
| Peak memory | 205908 kb |
| Host | smart-5ac706b8-25a3-4423-a217-b12157533400 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90505544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.90505544 |
| Directory | /workspace/22.edn_alert/latest |
| Test location | /workspace/coverage/default/22.edn_alert_test.3365872411 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 31497426 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:25:54 PM PST 24 |
| Finished | Jan 14 12:25:55 PM PST 24 |
| Peak memory | 204408 kb |
| Host | smart-13123705-72ac-4dac-acef-bcad0ad8e25c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365872411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3365872411 |
| Directory | /workspace/22.edn_alert_test/latest |
| Test location | /workspace/coverage/default/22.edn_disable.4206713119 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 29031950 ps |
| CPU time | 0.8 seconds |
| Started | Jan 14 12:25:54 PM PST 24 |
| Finished | Jan 14 12:25:56 PM PST 24 |
| Peak memory | 214220 kb |
| Host | smart-bd9984d7-69a4-4297-bb7c-a27ee3c18dc4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206713119 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.4206713119 |
| Directory | /workspace/22.edn_disable/latest |
| Test location | /workspace/coverage/default/22.edn_err.2354295142 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 28510648 ps |
| CPU time | 0.78 seconds |
| Started | Jan 14 12:25:59 PM PST 24 |
| Finished | Jan 14 12:26:00 PM PST 24 |
| Peak memory | 215196 kb |
| Host | smart-b09afaf7-1891-4073-a2ed-feb5ab4b398f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2354295142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2354295142 |
| Directory | /workspace/22.edn_err/latest |
| Test location | /workspace/coverage/default/22.edn_genbits.3493114979 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 15696991 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:26:07 PM PST 24 |
| Finished | Jan 14 12:26:08 PM PST 24 |
| Peak memory | 205000 kb |
| Host | smart-5d15d813-b759-4060-997b-866726b6baa7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493114979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3493114979 |
| Directory | /workspace/22.edn_genbits/latest |
| Test location | /workspace/coverage/default/22.edn_intr.1009643182 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 17763716 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:25:59 PM PST 24 |
| Finished | Jan 14 12:26:01 PM PST 24 |
| Peak memory | 214480 kb |
| Host | smart-fcc45412-0442-4a52-9d21-a4fc9926b63c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1009643182 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1009643182 |
| Directory | /workspace/22.edn_intr/latest |
| Test location | /workspace/coverage/default/22.edn_smoke.3714420466 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 25395809 ps |
| CPU time | 0.87 seconds |
| Started | Jan 14 12:26:07 PM PST 24 |
| Finished | Jan 14 12:26:08 PM PST 24 |
| Peak memory | 204668 kb |
| Host | smart-619cef7d-914d-4be1-b56c-24a1540c55c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3714420466 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3714420466 |
| Directory | /workspace/22.edn_smoke/latest |
| Test location | /workspace/coverage/default/22.edn_stress_all.402448953 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 636616079 ps |
| CPU time | 1.91 seconds |
| Started | Jan 14 12:25:44 PM PST 24 |
| Finished | Jan 14 12:25:49 PM PST 24 |
| Peak memory | 205516 kb |
| Host | smart-65bf8b35-a279-4036-9fb5-d3dc6de4aa86 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402448953 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.402448953 |
| Directory | /workspace/22.edn_stress_all/latest |
| Test location | /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3322155826 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 138560719250 ps |
| CPU time | 573.42 seconds |
| Started | Jan 14 12:26:13 PM PST 24 |
| Finished | Jan 14 12:35:47 PM PST 24 |
| Peak memory | 214492 kb |
| Host | smart-359e9f14-305b-4233-8662-641bb9c4b844 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322155826 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3322155826 |
| Directory | /workspace/22.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/220.edn_genbits.1668888973 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 17322477 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:27:03 PM PST 24 |
| Finished | Jan 14 12:27:05 PM PST 24 |
| Peak memory | 204876 kb |
| Host | smart-2dc41e43-e008-43fc-af73-209b606b9c6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1668888973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1668888973 |
| Directory | /workspace/220.edn_genbits/latest |
| Test location | /workspace/coverage/default/222.edn_genbits.3330519817 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 19129677 ps |
| CPU time | 1.05 seconds |
| Started | Jan 14 12:27:12 PM PST 24 |
| Finished | Jan 14 12:27:13 PM PST 24 |
| Peak memory | 205380 kb |
| Host | smart-6f1530af-ee56-4115-909e-c844bdb3d1b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3330519817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3330519817 |
| Directory | /workspace/222.edn_genbits/latest |
| Test location | /workspace/coverage/default/223.edn_genbits.1885780556 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 70807843 ps |
| CPU time | 1.06 seconds |
| Started | Jan 14 12:27:01 PM PST 24 |
| Finished | Jan 14 12:27:03 PM PST 24 |
| Peak memory | 205544 kb |
| Host | smart-ceabe4d3-d44c-4c26-8b33-e7c1ae1f781f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1885780556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1885780556 |
| Directory | /workspace/223.edn_genbits/latest |
| Test location | /workspace/coverage/default/225.edn_genbits.2751643375 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 29068991 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:27:10 PM PST 24 |
| Finished | Jan 14 12:27:12 PM PST 24 |
| Peak memory | 205300 kb |
| Host | smart-cf1c40a0-3049-49d2-b084-b254023e3a2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2751643375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2751643375 |
| Directory | /workspace/225.edn_genbits/latest |
| Test location | /workspace/coverage/default/226.edn_genbits.3815501720 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 24501941 ps |
| CPU time | 1.11 seconds |
| Started | Jan 14 12:26:56 PM PST 24 |
| Finished | Jan 14 12:26:58 PM PST 24 |
| Peak memory | 213376 kb |
| Host | smart-f0de8b19-5580-44fc-a364-aedc11e83069 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3815501720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3815501720 |
| Directory | /workspace/226.edn_genbits/latest |
| Test location | /workspace/coverage/default/228.edn_genbits.1484554409 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 32883551 ps |
| CPU time | 1.06 seconds |
| Started | Jan 14 12:27:04 PM PST 24 |
| Finished | Jan 14 12:27:07 PM PST 24 |
| Peak memory | 205608 kb |
| Host | smart-320159fc-3ccf-4a3c-8491-5021d7a2b20e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1484554409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1484554409 |
| Directory | /workspace/228.edn_genbits/latest |
| Test location | /workspace/coverage/default/229.edn_genbits.488507390 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 17910759 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:26:56 PM PST 24 |
| Finished | Jan 14 12:26:57 PM PST 24 |
| Peak memory | 204412 kb |
| Host | smart-7d5eb712-c822-4c53-afca-1565cf172b40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=488507390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.488507390 |
| Directory | /workspace/229.edn_genbits/latest |
| Test location | /workspace/coverage/default/23.edn_alert.455858227 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 30154698 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:25:56 PM PST 24 |
| Finished | Jan 14 12:25:58 PM PST 24 |
| Peak memory | 205104 kb |
| Host | smart-2da48de4-f043-442c-99c1-ec47c5dd235a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=455858227 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.455858227 |
| Directory | /workspace/23.edn_alert/latest |
| Test location | /workspace/coverage/default/23.edn_alert_test.2083349987 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 25997958 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:26:04 PM PST 24 |
| Finished | Jan 14 12:26:05 PM PST 24 |
| Peak memory | 203808 kb |
| Host | smart-60f0b7a6-86a6-4600-95cf-4f1f897a0858 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083349987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2083349987 |
| Directory | /workspace/23.edn_alert_test/latest |
| Test location | /workspace/coverage/default/23.edn_disable_auto_req_mode.3030772158 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 82769165 ps |
| CPU time | 1.07 seconds |
| Started | Jan 14 12:26:09 PM PST 24 |
| Finished | Jan 14 12:26:11 PM PST 24 |
| Peak memory | 214272 kb |
| Host | smart-53bc2c8f-aca4-4a02-9ecd-199d581fc555 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030772158 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d isable_auto_req_mode.3030772158 |
| Directory | /workspace/23.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/23.edn_err.133499616 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 44936431 ps |
| CPU time | 1.26 seconds |
| Started | Jan 14 12:26:04 PM PST 24 |
| Finished | Jan 14 12:26:06 PM PST 24 |
| Peak memory | 221824 kb |
| Host | smart-d38e17cb-4220-4d74-856e-3acef0f8da65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=133499616 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.133499616 |
| Directory | /workspace/23.edn_err/latest |
| Test location | /workspace/coverage/default/23.edn_genbits.640290072 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 27461283 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:25:54 PM PST 24 |
| Finished | Jan 14 12:25:56 PM PST 24 |
| Peak memory | 204956 kb |
| Host | smart-98fc3099-c3ad-46b1-a68a-933060fd7498 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=640290072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.640290072 |
| Directory | /workspace/23.edn_genbits/latest |
| Test location | /workspace/coverage/default/23.edn_intr.788592454 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 22501361 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:25:51 PM PST 24 |
| Finished | Jan 14 12:25:53 PM PST 24 |
| Peak memory | 214180 kb |
| Host | smart-e3860494-c0c6-4111-b3c1-08441c975ecc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=788592454 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.788592454 |
| Directory | /workspace/23.edn_intr/latest |
| Test location | /workspace/coverage/default/23.edn_smoke.3292351569 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 32968066 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 12:25:54 PM PST 24 |
| Finished | Jan 14 12:25:55 PM PST 24 |
| Peak memory | 204656 kb |
| Host | smart-03f69091-72bc-40f3-833d-738f54b7f02e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3292351569 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3292351569 |
| Directory | /workspace/23.edn_smoke/latest |
| Test location | /workspace/coverage/default/23.edn_stress_all.1069024527 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 316936875 ps |
| CPU time | 2.04 seconds |
| Started | Jan 14 12:25:54 PM PST 24 |
| Finished | Jan 14 12:25:57 PM PST 24 |
| Peak memory | 205796 kb |
| Host | smart-d3f096fc-e8cc-4c87-b9cb-1757f639c95e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069024527 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1069024527 |
| Directory | /workspace/23.edn_stress_all/latest |
| Test location | /workspace/coverage/default/23.edn_stress_all_with_rand_reset.552384218 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 34359969978 ps |
| CPU time | 485.87 seconds |
| Started | Jan 14 12:26:01 PM PST 24 |
| Finished | Jan 14 12:34:08 PM PST 24 |
| Peak memory | 214576 kb |
| Host | smart-4e09f6a9-0186-45c7-82dc-6c67a72bd9f6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552384218 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.552384218 |
| Directory | /workspace/23.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/230.edn_genbits.3725194907 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 53023087 ps |
| CPU time | 2.11 seconds |
| Started | Jan 14 12:27:09 PM PST 24 |
| Finished | Jan 14 12:27:12 PM PST 24 |
| Peak memory | 214124 kb |
| Host | smart-7e647b4e-977f-4c9e-8090-1ef8cb9c1854 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3725194907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.3725194907 |
| Directory | /workspace/230.edn_genbits/latest |
| Test location | /workspace/coverage/default/231.edn_genbits.1171345558 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 42261877 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:26:57 PM PST 24 |
| Finished | Jan 14 12:26:59 PM PST 24 |
| Peak memory | 205276 kb |
| Host | smart-6fe04a59-d334-48c5-946f-b4a239076b4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1171345558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1171345558 |
| Directory | /workspace/231.edn_genbits/latest |
| Test location | /workspace/coverage/default/232.edn_genbits.2560783308 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 29727710 ps |
| CPU time | 1.04 seconds |
| Started | Jan 14 12:26:54 PM PST 24 |
| Finished | Jan 14 12:26:56 PM PST 24 |
| Peak memory | 214024 kb |
| Host | smart-2aeef4c3-287b-4671-b5b2-3762584f31f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2560783308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2560783308 |
| Directory | /workspace/232.edn_genbits/latest |
| Test location | /workspace/coverage/default/233.edn_genbits.2409553216 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 47253405 ps |
| CPU time | 1.91 seconds |
| Started | Jan 14 12:27:07 PM PST 24 |
| Finished | Jan 14 12:27:10 PM PST 24 |
| Peak memory | 214140 kb |
| Host | smart-79f06954-2aa7-47f3-89b6-938ff7941fc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2409553216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2409553216 |
| Directory | /workspace/233.edn_genbits/latest |
| Test location | /workspace/coverage/default/234.edn_genbits.485013859 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 19966231 ps |
| CPU time | 1.25 seconds |
| Started | Jan 14 12:27:10 PM PST 24 |
| Finished | Jan 14 12:27:12 PM PST 24 |
| Peak memory | 205372 kb |
| Host | smart-c9fee6cf-bf68-4111-98b5-63e408506c7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=485013859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.485013859 |
| Directory | /workspace/234.edn_genbits/latest |
| Test location | /workspace/coverage/default/235.edn_genbits.2586394665 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 17978648 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:27:01 PM PST 24 |
| Finished | Jan 14 12:27:02 PM PST 24 |
| Peak memory | 204940 kb |
| Host | smart-d0ed3e89-9e58-4ec1-b06f-7af8570970b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2586394665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2586394665 |
| Directory | /workspace/235.edn_genbits/latest |
| Test location | /workspace/coverage/default/236.edn_genbits.2586887550 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 24775064 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:27:16 PM PST 24 |
| Finished | Jan 14 12:27:17 PM PST 24 |
| Peak memory | 204900 kb |
| Host | smart-00d64ced-9fbc-4e26-b095-640a2d7d0611 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2586887550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2586887550 |
| Directory | /workspace/236.edn_genbits/latest |
| Test location | /workspace/coverage/default/238.edn_genbits.3429229912 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 98899041 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:27:17 PM PST 24 |
| Finished | Jan 14 12:27:18 PM PST 24 |
| Peak memory | 204808 kb |
| Host | smart-8970b207-b71c-45a6-85f5-98619ccad60a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3429229912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3429229912 |
| Directory | /workspace/238.edn_genbits/latest |
| Test location | /workspace/coverage/default/239.edn_genbits.2900559441 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 167673182 ps |
| CPU time | 2.01 seconds |
| Started | Jan 14 12:26:57 PM PST 24 |
| Finished | Jan 14 12:27:00 PM PST 24 |
| Peak memory | 214188 kb |
| Host | smart-03283905-4d04-4b1b-8e95-7f4482d3ae2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2900559441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2900559441 |
| Directory | /workspace/239.edn_genbits/latest |
| Test location | /workspace/coverage/default/24.edn_alert.3470268701 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 21699690 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:25:59 PM PST 24 |
| Finished | Jan 14 12:26:02 PM PST 24 |
| Peak memory | 205820 kb |
| Host | smart-8837bae4-ae35-4a8f-8354-16a2c2a024bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3470268701 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3470268701 |
| Directory | /workspace/24.edn_alert/latest |
| Test location | /workspace/coverage/default/24.edn_alert_test.417741773 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 13775398 ps |
| CPU time | 0.87 seconds |
| Started | Jan 14 12:26:07 PM PST 24 |
| Finished | Jan 14 12:26:08 PM PST 24 |
| Peak memory | 204284 kb |
| Host | smart-4fba1559-582f-4b72-a5d9-6fd59983623f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417741773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.417741773 |
| Directory | /workspace/24.edn_alert_test/latest |
| Test location | /workspace/coverage/default/24.edn_disable.3511038721 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 29887577 ps |
| CPU time | 0.79 seconds |
| Started | Jan 14 12:25:48 PM PST 24 |
| Finished | Jan 14 12:25:49 PM PST 24 |
| Peak memory | 214212 kb |
| Host | smart-0628e8be-de0b-45a7-ad2e-0e4266582389 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511038721 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3511038721 |
| Directory | /workspace/24.edn_disable/latest |
| Test location | /workspace/coverage/default/24.edn_disable_auto_req_mode.548433021 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 20569867 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:25:50 PM PST 24 |
| Finished | Jan 14 12:25:52 PM PST 24 |
| Peak memory | 206172 kb |
| Host | smart-b54a87de-06e0-45d4-add5-602d44e2afb3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548433021 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di sable_auto_req_mode.548433021 |
| Directory | /workspace/24.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/24.edn_err.2795879586 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 20597585 ps |
| CPU time | 1.1 seconds |
| Started | Jan 14 12:25:54 PM PST 24 |
| Finished | Jan 14 12:25:56 PM PST 24 |
| Peak memory | 216092 kb |
| Host | smart-a6119bc8-65ff-4164-ba15-151ee85da72e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2795879586 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2795879586 |
| Directory | /workspace/24.edn_err/latest |
| Test location | /workspace/coverage/default/24.edn_genbits.350200471 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 52332541 ps |
| CPU time | 2.11 seconds |
| Started | Jan 14 12:25:57 PM PST 24 |
| Finished | Jan 14 12:26:00 PM PST 24 |
| Peak memory | 214204 kb |
| Host | smart-799b0e72-60b8-4211-81bf-e7594f8ba5ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=350200471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.350200471 |
| Directory | /workspace/24.edn_genbits/latest |
| Test location | /workspace/coverage/default/24.edn_intr.3173726017 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 38441631 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:26:00 PM PST 24 |
| Finished | Jan 14 12:26:02 PM PST 24 |
| Peak memory | 214368 kb |
| Host | smart-a483540f-cbf4-48f6-9e8a-dc454d11922d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3173726017 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3173726017 |
| Directory | /workspace/24.edn_intr/latest |
| Test location | /workspace/coverage/default/24.edn_smoke.1727306398 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 28468573 ps |
| CPU time | 0.84 seconds |
| Started | Jan 14 12:26:01 PM PST 24 |
| Finished | Jan 14 12:26:03 PM PST 24 |
| Peak memory | 204832 kb |
| Host | smart-7d4c6539-6835-46ca-822e-8e710c570082 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1727306398 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1727306398 |
| Directory | /workspace/24.edn_smoke/latest |
| Test location | /workspace/coverage/default/24.edn_stress_all.2806342749 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 253183952 ps |
| CPU time | 3 seconds |
| Started | Jan 14 12:25:59 PM PST 24 |
| Finished | Jan 14 12:26:03 PM PST 24 |
| Peak memory | 205792 kb |
| Host | smart-1a2dcd7f-f5f9-42df-8cff-fb3c138b5524 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806342749 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2806342749 |
| Directory | /workspace/24.edn_stress_all/latest |
| Test location | /workspace/coverage/default/24.edn_stress_all_with_rand_reset.4024308619 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 147776735310 ps |
| CPU time | 329.63 seconds |
| Started | Jan 14 12:26:04 PM PST 24 |
| Finished | Jan 14 12:31:34 PM PST 24 |
| Peak memory | 214424 kb |
| Host | smart-ca82d8e9-e44d-4059-a467-3a1293740e40 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024308619 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.4024308619 |
| Directory | /workspace/24.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/240.edn_genbits.3234117439 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 114817592 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:26:47 PM PST 24 |
| Finished | Jan 14 12:26:49 PM PST 24 |
| Peak memory | 205448 kb |
| Host | smart-6aad8910-b9b1-4c50-9dca-c9d5d2207489 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3234117439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3234117439 |
| Directory | /workspace/240.edn_genbits/latest |
| Test location | /workspace/coverage/default/241.edn_genbits.3588520741 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 186198692 ps |
| CPU time | 1.25 seconds |
| Started | Jan 14 12:26:42 PM PST 24 |
| Finished | Jan 14 12:26:44 PM PST 24 |
| Peak memory | 214060 kb |
| Host | smart-4a672d70-e336-47f7-a2d1-59e7e62ba806 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3588520741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3588520741 |
| Directory | /workspace/241.edn_genbits/latest |
| Test location | /workspace/coverage/default/242.edn_genbits.1369867273 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 58362792 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:27:01 PM PST 24 |
| Finished | Jan 14 12:27:03 PM PST 24 |
| Peak memory | 205448 kb |
| Host | smart-337263f6-bd86-4a3c-b4dd-7cf2a226fe7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1369867273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1369867273 |
| Directory | /workspace/242.edn_genbits/latest |
| Test location | /workspace/coverage/default/243.edn_genbits.4075862443 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 48095851 ps |
| CPU time | 1 seconds |
| Started | Jan 14 12:27:14 PM PST 24 |
| Finished | Jan 14 12:27:15 PM PST 24 |
| Peak memory | 214076 kb |
| Host | smart-cf6046a2-f1cd-47e7-81b3-eeb715c7a96c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4075862443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.4075862443 |
| Directory | /workspace/243.edn_genbits/latest |
| Test location | /workspace/coverage/default/244.edn_genbits.3375795550 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 25672035 ps |
| CPU time | 1.14 seconds |
| Started | Jan 14 12:26:53 PM PST 24 |
| Finished | Jan 14 12:26:55 PM PST 24 |
| Peak memory | 205352 kb |
| Host | smart-22e7c017-ff66-4d20-8182-7627760c9658 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3375795550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3375795550 |
| Directory | /workspace/244.edn_genbits/latest |
| Test location | /workspace/coverage/default/245.edn_genbits.1706241671 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 13722458 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:27:14 PM PST 24 |
| Finished | Jan 14 12:27:15 PM PST 24 |
| Peak memory | 204932 kb |
| Host | smart-61b6827d-9604-4e5e-bcae-7f0a44cd0d24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1706241671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1706241671 |
| Directory | /workspace/245.edn_genbits/latest |
| Test location | /workspace/coverage/default/246.edn_genbits.965340674 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 20271339 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:27:02 PM PST 24 |
| Finished | Jan 14 12:27:05 PM PST 24 |
| Peak memory | 205048 kb |
| Host | smart-9da9efc6-e5a0-49f9-a910-39fb2be62d82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=965340674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.965340674 |
| Directory | /workspace/246.edn_genbits/latest |
| Test location | /workspace/coverage/default/247.edn_genbits.1412320482 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 23540038 ps |
| CPU time | 1.16 seconds |
| Started | Jan 14 12:27:14 PM PST 24 |
| Finished | Jan 14 12:27:15 PM PST 24 |
| Peak memory | 214064 kb |
| Host | smart-2b6d17f5-8fbd-4ea7-9c0e-6adb5cc42cc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1412320482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1412320482 |
| Directory | /workspace/247.edn_genbits/latest |
| Test location | /workspace/coverage/default/248.edn_genbits.67012721 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 15786766 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:27:06 PM PST 24 |
| Finished | Jan 14 12:27:08 PM PST 24 |
| Peak memory | 205092 kb |
| Host | smart-fa233f2f-eca9-4f7c-85b8-e5a3d356ca8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67012721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.67012721 |
| Directory | /workspace/248.edn_genbits/latest |
| Test location | /workspace/coverage/default/249.edn_genbits.3263261115 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 18915874 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:26:53 PM PST 24 |
| Finished | Jan 14 12:26:55 PM PST 24 |
| Peak memory | 205412 kb |
| Host | smart-19ee0b94-c0a3-4f30-ace7-dd3b1d2a1f80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263261115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3263261115 |
| Directory | /workspace/249.edn_genbits/latest |
| Test location | /workspace/coverage/default/25.edn_alert.3582021327 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 36343541 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:25:57 PM PST 24 |
| Finished | Jan 14 12:25:59 PM PST 24 |
| Peak memory | 205860 kb |
| Host | smart-455aa6a6-5ea7-491b-a51b-8ab1401c3bfa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3582021327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3582021327 |
| Directory | /workspace/25.edn_alert/latest |
| Test location | /workspace/coverage/default/25.edn_alert_test.2177526528 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 18121222 ps |
| CPU time | 0.78 seconds |
| Started | Jan 14 12:25:58 PM PST 24 |
| Finished | Jan 14 12:25:59 PM PST 24 |
| Peak memory | 204268 kb |
| Host | smart-d1092e60-a79e-4f7f-9937-c8ee90b6a54a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177526528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2177526528 |
| Directory | /workspace/25.edn_alert_test/latest |
| Test location | /workspace/coverage/default/25.edn_disable.2073257225 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 40098746 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:26:04 PM PST 24 |
| Finished | Jan 14 12:26:05 PM PST 24 |
| Peak memory | 214200 kb |
| Host | smart-e79c39d4-cb7d-440f-a13e-b6e4a141e961 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073257225 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2073257225 |
| Directory | /workspace/25.edn_disable/latest |
| Test location | /workspace/coverage/default/25.edn_disable_auto_req_mode.2618399489 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 15013574 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:26:04 PM PST 24 |
| Finished | Jan 14 12:26:05 PM PST 24 |
| Peak memory | 213824 kb |
| Host | smart-80a82bed-90f9-4965-8d60-60f7fb45e536 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618399489 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d isable_auto_req_mode.2618399489 |
| Directory | /workspace/25.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/25.edn_err.2990958451 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 32461176 ps |
| CPU time | 0.8 seconds |
| Started | Jan 14 12:26:00 PM PST 24 |
| Finished | Jan 14 12:26:01 PM PST 24 |
| Peak memory | 215352 kb |
| Host | smart-89beddbf-5a4f-4a2d-9b58-fd2157abbc45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2990958451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2990958451 |
| Directory | /workspace/25.edn_err/latest |
| Test location | /workspace/coverage/default/25.edn_intr.1555278181 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 34104489 ps |
| CPU time | 1.01 seconds |
| Started | Jan 14 12:25:57 PM PST 24 |
| Finished | Jan 14 12:25:59 PM PST 24 |
| Peak memory | 221544 kb |
| Host | smart-66da0ed7-c828-4ca3-aca3-493ceb9f13a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1555278181 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1555278181 |
| Directory | /workspace/25.edn_intr/latest |
| Test location | /workspace/coverage/default/25.edn_smoke.497988283 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 23164074 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:25:58 PM PST 24 |
| Finished | Jan 14 12:26:00 PM PST 24 |
| Peak memory | 204528 kb |
| Host | smart-974db944-0caa-45d6-83b0-a53d264dc65c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=497988283 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.497988283 |
| Directory | /workspace/25.edn_smoke/latest |
| Test location | /workspace/coverage/default/25.edn_stress_all.1047115211 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 66159191 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:25:58 PM PST 24 |
| Finished | Jan 14 12:25:59 PM PST 24 |
| Peak memory | 204876 kb |
| Host | smart-5fb66bef-609e-444e-968d-991a47e846d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047115211 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1047115211 |
| Directory | /workspace/25.edn_stress_all/latest |
| Test location | /workspace/coverage/default/25.edn_stress_all_with_rand_reset.3178080631 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 54447400836 ps |
| CPU time | 1303.27 seconds |
| Started | Jan 14 12:26:00 PM PST 24 |
| Finished | Jan 14 12:47:44 PM PST 24 |
| Peak memory | 217324 kb |
| Host | smart-41b21aab-3a50-4493-8f59-48a3b6ba86a9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178080631 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.3178080631 |
| Directory | /workspace/25.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/250.edn_genbits.1178269085 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 24699628 ps |
| CPU time | 1.4 seconds |
| Started | Jan 14 12:26:57 PM PST 24 |
| Finished | Jan 14 12:27:00 PM PST 24 |
| Peak memory | 214032 kb |
| Host | smart-437c6b58-555d-468b-8abe-4a3d87055c6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1178269085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1178269085 |
| Directory | /workspace/250.edn_genbits/latest |
| Test location | /workspace/coverage/default/251.edn_genbits.3079648827 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 33167356 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:27:02 PM PST 24 |
| Finished | Jan 14 12:27:05 PM PST 24 |
| Peak memory | 205376 kb |
| Host | smart-fe463963-3a35-4c59-85a2-c76f43731509 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3079648827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3079648827 |
| Directory | /workspace/251.edn_genbits/latest |
| Test location | /workspace/coverage/default/252.edn_genbits.2448525961 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 47178145 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:27:03 PM PST 24 |
| Finished | Jan 14 12:27:05 PM PST 24 |
| Peak memory | 205308 kb |
| Host | smart-3a31d0f2-5230-4dcc-b894-9d9aa8c0ed28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2448525961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2448525961 |
| Directory | /workspace/252.edn_genbits/latest |
| Test location | /workspace/coverage/default/253.edn_genbits.4037250896 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 36184967 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:26:42 PM PST 24 |
| Finished | Jan 14 12:26:44 PM PST 24 |
| Peak memory | 205340 kb |
| Host | smart-f6f313d9-3453-4dc3-a43b-20693d0e1925 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4037250896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.4037250896 |
| Directory | /workspace/253.edn_genbits/latest |
| Test location | /workspace/coverage/default/254.edn_genbits.2145274447 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 38631978 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:27:14 PM PST 24 |
| Finished | Jan 14 12:27:15 PM PST 24 |
| Peak memory | 204764 kb |
| Host | smart-121020a3-1a27-48e0-8dd6-8ef1c03c07c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2145274447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2145274447 |
| Directory | /workspace/254.edn_genbits/latest |
| Test location | /workspace/coverage/default/255.edn_genbits.1808133913 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 72790137 ps |
| CPU time | 1.07 seconds |
| Started | Jan 14 12:26:59 PM PST 24 |
| Finished | Jan 14 12:27:01 PM PST 24 |
| Peak memory | 214080 kb |
| Host | smart-b53b82d4-a6e6-4a8c-8c85-1554e034aaef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1808133913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1808133913 |
| Directory | /workspace/255.edn_genbits/latest |
| Test location | /workspace/coverage/default/256.edn_genbits.1976713119 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 17997215 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:26:54 PM PST 24 |
| Finished | Jan 14 12:27:01 PM PST 24 |
| Peak memory | 205096 kb |
| Host | smart-e5a3c091-0196-4584-879d-99fa7b0fb6a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1976713119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1976713119 |
| Directory | /workspace/256.edn_genbits/latest |
| Test location | /workspace/coverage/default/257.edn_genbits.2567007595 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 20410122 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:26:57 PM PST 24 |
| Finished | Jan 14 12:26:59 PM PST 24 |
| Peak memory | 205368 kb |
| Host | smart-ccb8a518-ab00-45ca-a0ea-2bb59b3117db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2567007595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2567007595 |
| Directory | /workspace/257.edn_genbits/latest |
| Test location | /workspace/coverage/default/258.edn_genbits.2855870691 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 122108734 ps |
| CPU time | 1.36 seconds |
| Started | Jan 14 12:26:59 PM PST 24 |
| Finished | Jan 14 12:27:02 PM PST 24 |
| Peak memory | 214080 kb |
| Host | smart-e0856a6c-9523-41e8-a67d-2a8e2b41d2dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2855870691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2855870691 |
| Directory | /workspace/258.edn_genbits/latest |
| Test location | /workspace/coverage/default/259.edn_genbits.3098890977 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 25531174 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:26:59 PM PST 24 |
| Finished | Jan 14 12:27:01 PM PST 24 |
| Peak memory | 205356 kb |
| Host | smart-e6a22096-88b1-40e1-aae5-99b4d7184115 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3098890977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3098890977 |
| Directory | /workspace/259.edn_genbits/latest |
| Test location | /workspace/coverage/default/26.edn_alert.3767224389 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 54340939 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:25:59 PM PST 24 |
| Finished | Jan 14 12:26:01 PM PST 24 |
| Peak memory | 205792 kb |
| Host | smart-5c5b8c12-3725-476e-b3bc-948e579129f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3767224389 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3767224389 |
| Directory | /workspace/26.edn_alert/latest |
| Test location | /workspace/coverage/default/26.edn_alert_test.450714843 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 19518242 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:25:55 PM PST 24 |
| Finished | Jan 14 12:25:57 PM PST 24 |
| Peak memory | 205012 kb |
| Host | smart-ff84da1a-420c-4bcb-902a-38b60eb3f254 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450714843 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.450714843 |
| Directory | /workspace/26.edn_alert_test/latest |
| Test location | /workspace/coverage/default/26.edn_disable.1555168368 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 73227183 ps |
| CPU time | 0.8 seconds |
| Started | Jan 14 12:25:56 PM PST 24 |
| Finished | Jan 14 12:25:58 PM PST 24 |
| Peak memory | 214276 kb |
| Host | smart-e4862730-ae23-446c-9dd2-1e575c1c1f5e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555168368 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1555168368 |
| Directory | /workspace/26.edn_disable/latest |
| Test location | /workspace/coverage/default/26.edn_disable_auto_req_mode.1323536866 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 43839475 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:26:05 PM PST 24 |
| Finished | Jan 14 12:26:07 PM PST 24 |
| Peak memory | 214372 kb |
| Host | smart-ce81684f-5341-45fc-9331-1353c1adaf22 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323536866 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d isable_auto_req_mode.1323536866 |
| Directory | /workspace/26.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/26.edn_err.4201306978 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 57887329 ps |
| CPU time | 0.78 seconds |
| Started | Jan 14 12:25:57 PM PST 24 |
| Finished | Jan 14 12:25:59 PM PST 24 |
| Peak memory | 215512 kb |
| Host | smart-2ae08c1f-ac98-48db-8a2a-194e365cd006 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4201306978 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.4201306978 |
| Directory | /workspace/26.edn_err/latest |
| Test location | /workspace/coverage/default/26.edn_genbits.1330712796 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 15909935 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:26:02 PM PST 24 |
| Finished | Jan 14 12:26:05 PM PST 24 |
| Peak memory | 205004 kb |
| Host | smart-f646a52e-c070-4f3c-8cbe-7a855e2dee28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1330712796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1330712796 |
| Directory | /workspace/26.edn_genbits/latest |
| Test location | /workspace/coverage/default/26.edn_intr.1294256727 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 36163314 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:26:05 PM PST 24 |
| Finished | Jan 14 12:26:07 PM PST 24 |
| Peak memory | 221308 kb |
| Host | smart-ad3ff7bb-4720-4d7e-a367-0dd3722ee86b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1294256727 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.1294256727 |
| Directory | /workspace/26.edn_intr/latest |
| Test location | /workspace/coverage/default/26.edn_smoke.2484754659 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 46861357 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:26:05 PM PST 24 |
| Finished | Jan 14 12:26:07 PM PST 24 |
| Peak memory | 204748 kb |
| Host | smart-d4d34e10-9688-4840-94a1-4b0d5f625137 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2484754659 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2484754659 |
| Directory | /workspace/26.edn_smoke/latest |
| Test location | /workspace/coverage/default/26.edn_stress_all.95772788 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 297875806 ps |
| CPU time | 1.68 seconds |
| Started | Jan 14 12:25:59 PM PST 24 |
| Finished | Jan 14 12:26:02 PM PST 24 |
| Peak memory | 205288 kb |
| Host | smart-979d4772-1770-4115-8d9c-0b27e72d4c35 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95772788 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.95772788 |
| Directory | /workspace/26.edn_stress_all/latest |
| Test location | /workspace/coverage/default/260.edn_genbits.3855438442 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 88144070 ps |
| CPU time | 1.18 seconds |
| Started | Jan 14 12:26:57 PM PST 24 |
| Finished | Jan 14 12:26:59 PM PST 24 |
| Peak memory | 214020 kb |
| Host | smart-40dccf26-2629-4a20-b915-f421a5d8a038 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3855438442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.3855438442 |
| Directory | /workspace/260.edn_genbits/latest |
| Test location | /workspace/coverage/default/262.edn_genbits.161457691 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 19373025 ps |
| CPU time | 1 seconds |
| Started | Jan 14 12:27:05 PM PST 24 |
| Finished | Jan 14 12:27:07 PM PST 24 |
| Peak memory | 205252 kb |
| Host | smart-963fe691-1991-4679-9f77-cbfa938492ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=161457691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.161457691 |
| Directory | /workspace/262.edn_genbits/latest |
| Test location | /workspace/coverage/default/263.edn_genbits.252578999 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 42201528 ps |
| CPU time | 1.79 seconds |
| Started | Jan 14 12:27:17 PM PST 24 |
| Finished | Jan 14 12:27:19 PM PST 24 |
| Peak memory | 214032 kb |
| Host | smart-751f5910-b5c6-4eab-855b-afa8ee123824 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=252578999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.252578999 |
| Directory | /workspace/263.edn_genbits/latest |
| Test location | /workspace/coverage/default/264.edn_genbits.221137283 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 25065219 ps |
| CPU time | 1.18 seconds |
| Started | Jan 14 12:27:05 PM PST 24 |
| Finished | Jan 14 12:27:07 PM PST 24 |
| Peak memory | 205660 kb |
| Host | smart-e9dc6216-953b-444d-87b5-d67cac58bfd9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=221137283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.221137283 |
| Directory | /workspace/264.edn_genbits/latest |
| Test location | /workspace/coverage/default/265.edn_genbits.890479511 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 79207278 ps |
| CPU time | 1.06 seconds |
| Started | Jan 14 12:27:01 PM PST 24 |
| Finished | Jan 14 12:27:03 PM PST 24 |
| Peak memory | 205300 kb |
| Host | smart-0818b0c8-b165-48a7-ac40-fc6bb8965b26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=890479511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.890479511 |
| Directory | /workspace/265.edn_genbits/latest |
| Test location | /workspace/coverage/default/266.edn_genbits.3515550660 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 46354158 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:27:03 PM PST 24 |
| Finished | Jan 14 12:27:05 PM PST 24 |
| Peak memory | 204876 kb |
| Host | smart-f0e154bb-d134-479a-9c40-c77b49b95ca9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3515550660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3515550660 |
| Directory | /workspace/266.edn_genbits/latest |
| Test location | /workspace/coverage/default/267.edn_genbits.1649635474 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 22028455 ps |
| CPU time | 1.36 seconds |
| Started | Jan 14 12:26:59 PM PST 24 |
| Finished | Jan 14 12:27:02 PM PST 24 |
| Peak memory | 205776 kb |
| Host | smart-cecdff33-21b5-4f98-90fb-068bdc644efd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1649635474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1649635474 |
| Directory | /workspace/267.edn_genbits/latest |
| Test location | /workspace/coverage/default/268.edn_genbits.4051528692 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 28635914 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:27:07 PM PST 24 |
| Finished | Jan 14 12:27:08 PM PST 24 |
| Peak memory | 205160 kb |
| Host | smart-9c0d4f2e-96d8-408d-9a21-c944f7958763 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4051528692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.4051528692 |
| Directory | /workspace/268.edn_genbits/latest |
| Test location | /workspace/coverage/default/269.edn_genbits.3485373867 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 66254902 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:27:10 PM PST 24 |
| Finished | Jan 14 12:27:11 PM PST 24 |
| Peak memory | 205544 kb |
| Host | smart-49d30797-467d-4487-9c07-2b0a5fa2a2ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3485373867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3485373867 |
| Directory | /workspace/269.edn_genbits/latest |
| Test location | /workspace/coverage/default/27.edn_alert.850058804 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 17436966 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:26:29 PM PST 24 |
| Finished | Jan 14 12:26:30 PM PST 24 |
| Peak memory | 205148 kb |
| Host | smart-ec936789-07c8-4ecf-8d98-418728b1d678 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=850058804 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.850058804 |
| Directory | /workspace/27.edn_alert/latest |
| Test location | /workspace/coverage/default/27.edn_alert_test.2989672256 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 40530839 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:26:18 PM PST 24 |
| Finished | Jan 14 12:26:19 PM PST 24 |
| Peak memory | 204524 kb |
| Host | smart-e7c7bb28-4461-415f-bcba-c257ffe96980 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989672256 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2989672256 |
| Directory | /workspace/27.edn_alert_test/latest |
| Test location | /workspace/coverage/default/27.edn_disable.577486581 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 20060677 ps |
| CPU time | 0.8 seconds |
| Started | Jan 14 12:26:17 PM PST 24 |
| Finished | Jan 14 12:26:19 PM PST 24 |
| Peak memory | 214368 kb |
| Host | smart-8f48a11a-9b57-42c7-891b-ec5b42304f74 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577486581 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.577486581 |
| Directory | /workspace/27.edn_disable/latest |
| Test location | /workspace/coverage/default/27.edn_disable_auto_req_mode.2649990720 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 47922175 ps |
| CPU time | 1.08 seconds |
| Started | Jan 14 12:26:08 PM PST 24 |
| Finished | Jan 14 12:26:10 PM PST 24 |
| Peak memory | 214376 kb |
| Host | smart-e9102056-5a06-48e9-b9f4-c16d2b409b16 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649990720 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d isable_auto_req_mode.2649990720 |
| Directory | /workspace/27.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/27.edn_err.2969041078 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 74620350 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:08 PM PST 24 |
| Finished | Jan 14 12:26:09 PM PST 24 |
| Peak memory | 221264 kb |
| Host | smart-02515740-03dc-450c-bf0a-579c954827a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2969041078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2969041078 |
| Directory | /workspace/27.edn_err/latest |
| Test location | /workspace/coverage/default/27.edn_intr.408670976 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 22810668 ps |
| CPU time | 1.09 seconds |
| Started | Jan 14 12:26:13 PM PST 24 |
| Finished | Jan 14 12:26:15 PM PST 24 |
| Peak memory | 221364 kb |
| Host | smart-aad3cf18-9b78-47a8-8278-9d118617e012 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=408670976 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.408670976 |
| Directory | /workspace/27.edn_intr/latest |
| Test location | /workspace/coverage/default/27.edn_smoke.299593610 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 48886724 ps |
| CPU time | 0.84 seconds |
| Started | Jan 14 12:26:18 PM PST 24 |
| Finished | Jan 14 12:26:20 PM PST 24 |
| Peak memory | 204564 kb |
| Host | smart-4cc1ccb8-d91b-4e52-aae9-48d571b40911 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=299593610 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.299593610 |
| Directory | /workspace/27.edn_smoke/latest |
| Test location | /workspace/coverage/default/27.edn_stress_all.2220984655 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 134890437 ps |
| CPU time | 2.88 seconds |
| Started | Jan 14 12:26:10 PM PST 24 |
| Finished | Jan 14 12:26:14 PM PST 24 |
| Peak memory | 205872 kb |
| Host | smart-70c9105b-36f7-4e3d-9321-399f67974a32 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220984655 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2220984655 |
| Directory | /workspace/27.edn_stress_all/latest |
| Test location | /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1561664377 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 151713868987 ps |
| CPU time | 1710.31 seconds |
| Started | Jan 14 12:26:20 PM PST 24 |
| Finished | Jan 14 12:54:51 PM PST 24 |
| Peak memory | 221772 kb |
| Host | smart-6a2ae231-7d9b-4a05-814f-47cfaa08a50e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561664377 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1561664377 |
| Directory | /workspace/27.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/270.edn_genbits.845873320 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 21357153 ps |
| CPU time | 1.1 seconds |
| Started | Jan 14 12:27:08 PM PST 24 |
| Finished | Jan 14 12:27:10 PM PST 24 |
| Peak memory | 205532 kb |
| Host | smart-8af3efa3-3eaa-45cf-b4d6-e8b0f06b4809 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=845873320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.845873320 |
| Directory | /workspace/270.edn_genbits/latest |
| Test location | /workspace/coverage/default/271.edn_genbits.1650392990 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 262755342 ps |
| CPU time | 3.59 seconds |
| Started | Jan 14 12:26:58 PM PST 24 |
| Finished | Jan 14 12:27:03 PM PST 24 |
| Peak memory | 214036 kb |
| Host | smart-1d52b27a-6532-4d80-aaa7-6baa3ab52557 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1650392990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1650392990 |
| Directory | /workspace/271.edn_genbits/latest |
| Test location | /workspace/coverage/default/272.edn_genbits.790908804 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 63679742 ps |
| CPU time | 1.19 seconds |
| Started | Jan 14 12:26:55 PM PST 24 |
| Finished | Jan 14 12:26:59 PM PST 24 |
| Peak memory | 205564 kb |
| Host | smart-1096a6e0-8ce9-41b3-9d9a-3512b6d7fcee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=790908804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.790908804 |
| Directory | /workspace/272.edn_genbits/latest |
| Test location | /workspace/coverage/default/273.edn_genbits.1108292113 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 186804456 ps |
| CPU time | 1.21 seconds |
| Started | Jan 14 12:27:19 PM PST 24 |
| Finished | Jan 14 12:27:22 PM PST 24 |
| Peak memory | 214064 kb |
| Host | smart-f72da3b6-aec9-48d8-b021-42d557a475f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1108292113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1108292113 |
| Directory | /workspace/273.edn_genbits/latest |
| Test location | /workspace/coverage/default/274.edn_genbits.408040722 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 39786750 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:27:00 PM PST 24 |
| Finished | Jan 14 12:27:02 PM PST 24 |
| Peak memory | 205064 kb |
| Host | smart-641e4b35-b3f9-4e66-8466-bd2a343b263a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=408040722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.408040722 |
| Directory | /workspace/274.edn_genbits/latest |
| Test location | /workspace/coverage/default/275.edn_genbits.3552498884 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 68745200 ps |
| CPU time | 1.05 seconds |
| Started | Jan 14 12:27:12 PM PST 24 |
| Finished | Jan 14 12:27:13 PM PST 24 |
| Peak memory | 205536 kb |
| Host | smart-747ee6a4-852d-481c-b4e9-8a0be02ce6f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3552498884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3552498884 |
| Directory | /workspace/275.edn_genbits/latest |
| Test location | /workspace/coverage/default/276.edn_genbits.1191837204 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 50077882 ps |
| CPU time | 1.13 seconds |
| Started | Jan 14 12:27:04 PM PST 24 |
| Finished | Jan 14 12:27:06 PM PST 24 |
| Peak memory | 205456 kb |
| Host | smart-9451bec2-610e-46dc-b320-87c35e1fe4ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1191837204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1191837204 |
| Directory | /workspace/276.edn_genbits/latest |
| Test location | /workspace/coverage/default/277.edn_genbits.2367328218 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 115366715 ps |
| CPU time | 2.61 seconds |
| Started | Jan 14 12:27:26 PM PST 24 |
| Finished | Jan 14 12:27:30 PM PST 24 |
| Peak memory | 214012 kb |
| Host | smart-c7e763f6-f9a1-4822-b2e1-7913c8f23db8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2367328218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2367328218 |
| Directory | /workspace/277.edn_genbits/latest |
| Test location | /workspace/coverage/default/278.edn_genbits.100544001 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 29130319 ps |
| CPU time | 1.08 seconds |
| Started | Jan 14 12:26:56 PM PST 24 |
| Finished | Jan 14 12:26:58 PM PST 24 |
| Peak memory | 205180 kb |
| Host | smart-03ce6f9d-19f0-4cfe-ad95-d2c361f4a052 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=100544001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.100544001 |
| Directory | /workspace/278.edn_genbits/latest |
| Test location | /workspace/coverage/default/279.edn_genbits.873577993 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 60111095 ps |
| CPU time | 1.28 seconds |
| Started | Jan 14 12:27:03 PM PST 24 |
| Finished | Jan 14 12:27:06 PM PST 24 |
| Peak memory | 214064 kb |
| Host | smart-59be9772-960d-46fd-9051-674b2a658b1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=873577993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.873577993 |
| Directory | /workspace/279.edn_genbits/latest |
| Test location | /workspace/coverage/default/28.edn_alert.2578738111 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 172895585 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:26:19 PM PST 24 |
| Finished | Jan 14 12:26:21 PM PST 24 |
| Peak memory | 205868 kb |
| Host | smart-b83b89aa-7bad-45fd-985d-1662da24c734 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2578738111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2578738111 |
| Directory | /workspace/28.edn_alert/latest |
| Test location | /workspace/coverage/default/28.edn_alert_test.2269621531 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 14261780 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:26:13 PM PST 24 |
| Finished | Jan 14 12:26:14 PM PST 24 |
| Peak memory | 204320 kb |
| Host | smart-6b2538ea-d02a-4933-a5e0-3c07d01ade50 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269621531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2269621531 |
| Directory | /workspace/28.edn_alert_test/latest |
| Test location | /workspace/coverage/default/28.edn_disable.2984395435 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 42622843 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:26:12 PM PST 24 |
| Finished | Jan 14 12:26:13 PM PST 24 |
| Peak memory | 214280 kb |
| Host | smart-98acc9a8-f89e-4d00-b1f2-5fc0b06e9492 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984395435 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2984395435 |
| Directory | /workspace/28.edn_disable/latest |
| Test location | /workspace/coverage/default/28.edn_disable_auto_req_mode.720186823 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 27438978 ps |
| CPU time | 1.13 seconds |
| Started | Jan 14 12:26:23 PM PST 24 |
| Finished | Jan 14 12:26:25 PM PST 24 |
| Peak memory | 214392 kb |
| Host | smart-d37abf46-6a02-4502-8ddf-ce3c46b28cae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720186823 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_di sable_auto_req_mode.720186823 |
| Directory | /workspace/28.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/28.edn_err.2878916546 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 30931951 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:26:41 PM PST 24 |
| Finished | Jan 14 12:26:43 PM PST 24 |
| Peak memory | 215712 kb |
| Host | smart-ecd73fd8-9710-4e39-89d3-41254176960a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2878916546 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2878916546 |
| Directory | /workspace/28.edn_err/latest |
| Test location | /workspace/coverage/default/28.edn_genbits.2824602941 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 17462989 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:26:20 PM PST 24 |
| Finished | Jan 14 12:26:21 PM PST 24 |
| Peak memory | 205264 kb |
| Host | smart-a9f03efa-a81b-44cb-b87b-3e89e28bb484 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2824602941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2824602941 |
| Directory | /workspace/28.edn_genbits/latest |
| Test location | /workspace/coverage/default/28.edn_smoke.1299340610 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 13697309 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:26:11 PM PST 24 |
| Finished | Jan 14 12:26:13 PM PST 24 |
| Peak memory | 204740 kb |
| Host | smart-fda8bb35-57e1-4bc8-a4b9-ea4cbaf8f712 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1299340610 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1299340610 |
| Directory | /workspace/28.edn_smoke/latest |
| Test location | /workspace/coverage/default/28.edn_stress_all.1393529164 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 50329454 ps |
| CPU time | 1.56 seconds |
| Started | Jan 14 12:26:37 PM PST 24 |
| Finished | Jan 14 12:26:39 PM PST 24 |
| Peak memory | 205392 kb |
| Host | smart-481ae8ab-a2a2-4089-a188-9e103fb856e2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393529164 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.1393529164 |
| Directory | /workspace/28.edn_stress_all/latest |
| Test location | /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2696596839 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 83780489566 ps |
| CPU time | 1049.94 seconds |
| Started | Jan 14 12:26:10 PM PST 24 |
| Finished | Jan 14 12:43:41 PM PST 24 |
| Peak memory | 217332 kb |
| Host | smart-3378df2a-3839-439e-8b50-562f887b986f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696596839 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2696596839 |
| Directory | /workspace/28.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/280.edn_genbits.3017966347 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 70291343 ps |
| CPU time | 2.56 seconds |
| Started | Jan 14 12:27:08 PM PST 24 |
| Finished | Jan 14 12:27:11 PM PST 24 |
| Peak memory | 214080 kb |
| Host | smart-385c655c-7a69-4c68-adab-dcf7fb6b608f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3017966347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3017966347 |
| Directory | /workspace/280.edn_genbits/latest |
| Test location | /workspace/coverage/default/281.edn_genbits.1844421910 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 14650962 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:27:20 PM PST 24 |
| Finished | Jan 14 12:27:22 PM PST 24 |
| Peak memory | 204944 kb |
| Host | smart-3d1a2b21-39a7-4794-871f-522c2537626b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1844421910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1844421910 |
| Directory | /workspace/281.edn_genbits/latest |
| Test location | /workspace/coverage/default/282.edn_genbits.3492382691 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 19765919 ps |
| CPU time | 1.05 seconds |
| Started | Jan 14 12:27:16 PM PST 24 |
| Finished | Jan 14 12:27:17 PM PST 24 |
| Peak memory | 205284 kb |
| Host | smart-59eaf6b6-4e7d-4774-ab39-72d903ed0535 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492382691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3492382691 |
| Directory | /workspace/282.edn_genbits/latest |
| Test location | /workspace/coverage/default/283.edn_genbits.1740655047 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 142994391 ps |
| CPU time | 3.3 seconds |
| Started | Jan 14 12:27:20 PM PST 24 |
| Finished | Jan 14 12:27:29 PM PST 24 |
| Peak memory | 214060 kb |
| Host | smart-620f1f12-b944-4b6a-b929-a2697eb13395 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1740655047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1740655047 |
| Directory | /workspace/283.edn_genbits/latest |
| Test location | /workspace/coverage/default/284.edn_genbits.3424413581 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 15238831 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:27:01 PM PST 24 |
| Finished | Jan 14 12:27:03 PM PST 24 |
| Peak memory | 204928 kb |
| Host | smart-58c36247-d6a6-4711-b328-972e9100ca16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3424413581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3424413581 |
| Directory | /workspace/284.edn_genbits/latest |
| Test location | /workspace/coverage/default/285.edn_genbits.2843600556 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 94679957 ps |
| CPU time | 1.15 seconds |
| Started | Jan 14 12:27:03 PM PST 24 |
| Finished | Jan 14 12:27:05 PM PST 24 |
| Peak memory | 214120 kb |
| Host | smart-939801f4-a7ea-42c8-b5f8-f7004c1c016e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2843600556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2843600556 |
| Directory | /workspace/285.edn_genbits/latest |
| Test location | /workspace/coverage/default/286.edn_genbits.195481347 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 30604435 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:27:20 PM PST 24 |
| Finished | Jan 14 12:27:26 PM PST 24 |
| Peak memory | 204656 kb |
| Host | smart-f65b2d80-3b27-4b7f-bdc9-14e361a7305b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=195481347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.195481347 |
| Directory | /workspace/286.edn_genbits/latest |
| Test location | /workspace/coverage/default/287.edn_genbits.1562511960 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 41666762 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:26:58 PM PST 24 |
| Finished | Jan 14 12:27:00 PM PST 24 |
| Peak memory | 204824 kb |
| Host | smart-cf50b7e5-747f-452f-b38f-f4f2b3e741ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1562511960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1562511960 |
| Directory | /workspace/287.edn_genbits/latest |
| Test location | /workspace/coverage/default/288.edn_genbits.1428754324 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 17065622 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:27:03 PM PST 24 |
| Finished | Jan 14 12:27:05 PM PST 24 |
| Peak memory | 205160 kb |
| Host | smart-7f045d09-3b82-4ed7-a3a1-d8a8253f7015 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1428754324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1428754324 |
| Directory | /workspace/288.edn_genbits/latest |
| Test location | /workspace/coverage/default/289.edn_genbits.826255140 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 27382546 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:27:07 PM PST 24 |
| Finished | Jan 14 12:27:08 PM PST 24 |
| Peak memory | 204848 kb |
| Host | smart-00673eb1-3080-4902-9103-1a06bb9ca2e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=826255140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.826255140 |
| Directory | /workspace/289.edn_genbits/latest |
| Test location | /workspace/coverage/default/29.edn_alert_test.3037547837 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 13821418 ps |
| CPU time | 0.84 seconds |
| Started | Jan 14 12:26:04 PM PST 24 |
| Finished | Jan 14 12:26:06 PM PST 24 |
| Peak memory | 204332 kb |
| Host | smart-1abb928e-48c3-4433-a14d-cbca3297b81c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037547837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3037547837 |
| Directory | /workspace/29.edn_alert_test/latest |
| Test location | /workspace/coverage/default/29.edn_disable.3215335603 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 42441401 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:26:10 PM PST 24 |
| Finished | Jan 14 12:26:11 PM PST 24 |
| Peak memory | 214344 kb |
| Host | smart-93f292cb-53d7-40b9-9f26-be16b4e70dba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215335603 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.3215335603 |
| Directory | /workspace/29.edn_disable/latest |
| Test location | /workspace/coverage/default/29.edn_disable_auto_req_mode.3482114660 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 65090126 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:26:20 PM PST 24 |
| Finished | Jan 14 12:26:23 PM PST 24 |
| Peak memory | 214332 kb |
| Host | smart-35dc3273-883b-48f3-9ca1-9d6efc1b4a7d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482114660 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d isable_auto_req_mode.3482114660 |
| Directory | /workspace/29.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/29.edn_err.619097610 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 27101432 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:26:14 PM PST 24 |
| Finished | Jan 14 12:26:16 PM PST 24 |
| Peak memory | 215620 kb |
| Host | smart-14f4271b-102f-43c0-9539-221b6ff5b6ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=619097610 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.619097610 |
| Directory | /workspace/29.edn_err/latest |
| Test location | /workspace/coverage/default/29.edn_genbits.3756775708 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 36622237 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:12 PM PST 24 |
| Finished | Jan 14 12:26:14 PM PST 24 |
| Peak memory | 205380 kb |
| Host | smart-50168288-ccc1-4088-91a1-392b08c7aac8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3756775708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3756775708 |
| Directory | /workspace/29.edn_genbits/latest |
| Test location | /workspace/coverage/default/29.edn_intr.3426936156 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 25006039 ps |
| CPU time | 0.8 seconds |
| Started | Jan 14 12:26:10 PM PST 24 |
| Finished | Jan 14 12:26:11 PM PST 24 |
| Peak memory | 214256 kb |
| Host | smart-ce5e27ef-521a-42e8-92e0-155cc5ee572b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3426936156 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3426936156 |
| Directory | /workspace/29.edn_intr/latest |
| Test location | /workspace/coverage/default/29.edn_smoke.1707889507 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 14223092 ps |
| CPU time | 0.84 seconds |
| Started | Jan 14 12:26:28 PM PST 24 |
| Finished | Jan 14 12:26:29 PM PST 24 |
| Peak memory | 204736 kb |
| Host | smart-393007f1-4cb3-4fd0-930e-3e04d1f9814b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1707889507 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1707889507 |
| Directory | /workspace/29.edn_smoke/latest |
| Test location | /workspace/coverage/default/29.edn_stress_all.2370782216 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 90840755 ps |
| CPU time | 1.39 seconds |
| Started | Jan 14 12:26:10 PM PST 24 |
| Finished | Jan 14 12:26:12 PM PST 24 |
| Peak memory | 204988 kb |
| Host | smart-eac33403-5b08-49ef-b49e-4f4d07b0217b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370782216 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.2370782216 |
| Directory | /workspace/29.edn_stress_all/latest |
| Test location | /workspace/coverage/default/29.edn_stress_all_with_rand_reset.817862783 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 20276609643 ps |
| CPU time | 440.02 seconds |
| Started | Jan 14 12:26:12 PM PST 24 |
| Finished | Jan 14 12:33:33 PM PST 24 |
| Peak memory | 214396 kb |
| Host | smart-009049a1-998f-40d1-a6e0-e21f629f4507 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817862783 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.817862783 |
| Directory | /workspace/29.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/290.edn_genbits.1148137356 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 36501715 ps |
| CPU time | 1.01 seconds |
| Started | Jan 14 12:27:18 PM PST 24 |
| Finished | Jan 14 12:27:21 PM PST 24 |
| Peak memory | 205468 kb |
| Host | smart-7c7aaec0-228d-46b9-bda5-5e401ae19d8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1148137356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1148137356 |
| Directory | /workspace/290.edn_genbits/latest |
| Test location | /workspace/coverage/default/291.edn_genbits.4044281481 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 15027863 ps |
| CPU time | 1 seconds |
| Started | Jan 14 12:27:09 PM PST 24 |
| Finished | Jan 14 12:27:10 PM PST 24 |
| Peak memory | 214132 kb |
| Host | smart-20a0a3ac-8361-4a85-ae23-c5a46d625f29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4044281481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.4044281481 |
| Directory | /workspace/291.edn_genbits/latest |
| Test location | /workspace/coverage/default/292.edn_genbits.555452074 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 33342823 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:27:10 PM PST 24 |
| Finished | Jan 14 12:27:12 PM PST 24 |
| Peak memory | 205500 kb |
| Host | smart-13a5050d-89de-4f37-bedc-a91a178e821a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=555452074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.555452074 |
| Directory | /workspace/292.edn_genbits/latest |
| Test location | /workspace/coverage/default/293.edn_genbits.153217224 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 53175717 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:27:05 PM PST 24 |
| Finished | Jan 14 12:27:07 PM PST 24 |
| Peak memory | 204852 kb |
| Host | smart-d365448c-6af4-421d-a2e9-459440498d67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=153217224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.153217224 |
| Directory | /workspace/293.edn_genbits/latest |
| Test location | /workspace/coverage/default/294.edn_genbits.1227011024 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 19699053 ps |
| CPU time | 1.04 seconds |
| Started | Jan 14 12:27:03 PM PST 24 |
| Finished | Jan 14 12:27:05 PM PST 24 |
| Peak memory | 205468 kb |
| Host | smart-78669b89-03cc-4ccb-be2b-870c407b546f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1227011024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1227011024 |
| Directory | /workspace/294.edn_genbits/latest |
| Test location | /workspace/coverage/default/295.edn_genbits.1990213451 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 24859114 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:27:09 PM PST 24 |
| Finished | Jan 14 12:27:10 PM PST 24 |
| Peak memory | 204912 kb |
| Host | smart-702d5ada-9b1d-48bd-8404-7d896b74757e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1990213451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1990213451 |
| Directory | /workspace/295.edn_genbits/latest |
| Test location | /workspace/coverage/default/296.edn_genbits.1475244367 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 94166041 ps |
| CPU time | 1.22 seconds |
| Started | Jan 14 12:27:10 PM PST 24 |
| Finished | Jan 14 12:27:12 PM PST 24 |
| Peak memory | 205508 kb |
| Host | smart-92a52a4d-8359-4e03-842a-050b122b4bd3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1475244367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1475244367 |
| Directory | /workspace/296.edn_genbits/latest |
| Test location | /workspace/coverage/default/297.edn_genbits.2725232193 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 28416048 ps |
| CPU time | 1 seconds |
| Started | Jan 14 12:27:16 PM PST 24 |
| Finished | Jan 14 12:27:17 PM PST 24 |
| Peak memory | 205540 kb |
| Host | smart-d2d30a80-5f05-4c88-9175-8bba9792cdda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2725232193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2725232193 |
| Directory | /workspace/297.edn_genbits/latest |
| Test location | /workspace/coverage/default/298.edn_genbits.1592225637 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 177033559 ps |
| CPU time | 1.07 seconds |
| Started | Jan 14 12:26:59 PM PST 24 |
| Finished | Jan 14 12:27:01 PM PST 24 |
| Peak memory | 205240 kb |
| Host | smart-5e7b6582-3572-4b33-a737-db98b699407e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1592225637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1592225637 |
| Directory | /workspace/298.edn_genbits/latest |
| Test location | /workspace/coverage/default/299.edn_genbits.3660371299 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 16507049 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:27:03 PM PST 24 |
| Finished | Jan 14 12:27:05 PM PST 24 |
| Peak memory | 205144 kb |
| Host | smart-5ce7ab8a-4b64-4838-81bc-00f6229da151 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3660371299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3660371299 |
| Directory | /workspace/299.edn_genbits/latest |
| Test location | /workspace/coverage/default/3.edn_alert_test.3601271712 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 16927945 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:25:22 PM PST 24 |
| Finished | Jan 14 12:25:25 PM PST 24 |
| Peak memory | 204956 kb |
| Host | smart-5076c2fb-1133-44da-91aa-50ea0f9ff340 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601271712 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3601271712 |
| Directory | /workspace/3.edn_alert_test/latest |
| Test location | /workspace/coverage/default/3.edn_disable_auto_req_mode.2617687333 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 44199219 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:25:15 PM PST 24 |
| Finished | Jan 14 12:25:17 PM PST 24 |
| Peak memory | 214392 kb |
| Host | smart-e7f1fa95-9ae1-4f8b-857a-16c660a532bb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617687333 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di sable_auto_req_mode.2617687333 |
| Directory | /workspace/3.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/3.edn_err.1135341613 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 48592338 ps |
| CPU time | 0.79 seconds |
| Started | Jan 14 12:25:30 PM PST 24 |
| Finished | Jan 14 12:25:36 PM PST 24 |
| Peak memory | 215436 kb |
| Host | smart-e6a157dd-2045-4890-98c5-d85e606a04e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1135341613 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1135341613 |
| Directory | /workspace/3.edn_err/latest |
| Test location | /workspace/coverage/default/3.edn_genbits.2713240519 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 79550287 ps |
| CPU time | 1.13 seconds |
| Started | Jan 14 12:25:55 PM PST 24 |
| Finished | Jan 14 12:25:58 PM PST 24 |
| Peak memory | 214028 kb |
| Host | smart-80f37711-9fc4-4b22-be1f-03a4d02f9201 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2713240519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2713240519 |
| Directory | /workspace/3.edn_genbits/latest |
| Test location | /workspace/coverage/default/3.edn_intr.3360618604 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 26070488 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:25:24 PM PST 24 |
| Finished | Jan 14 12:25:31 PM PST 24 |
| Peak memory | 214296 kb |
| Host | smart-d4622d13-e8ba-4ee6-8992-86ba88f3c090 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3360618604 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3360618604 |
| Directory | /workspace/3.edn_intr/latest |
| Test location | /workspace/coverage/default/3.edn_regwen.1154793965 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 19241068 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 12:25:15 PM PST 24 |
| Finished | Jan 14 12:25:17 PM PST 24 |
| Peak memory | 204676 kb |
| Host | smart-2200e94a-f8f2-4fde-b1ab-6adab4b9c69c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1154793965 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1154793965 |
| Directory | /workspace/3.edn_regwen/latest |
| Test location | /workspace/coverage/default/3.edn_sec_cm.3460274807 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1567796746 ps |
| CPU time | 3.59 seconds |
| Started | Jan 14 12:25:15 PM PST 24 |
| Finished | Jan 14 12:25:19 PM PST 24 |
| Peak memory | 233560 kb |
| Host | smart-be200f88-4c96-4236-8593-822925cc29a7 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460274807 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3460274807 |
| Directory | /workspace/3.edn_sec_cm/latest |
| Test location | /workspace/coverage/default/3.edn_smoke.3501935619 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 15891809 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:25:19 PM PST 24 |
| Finished | Jan 14 12:25:21 PM PST 24 |
| Peak memory | 204764 kb |
| Host | smart-328cc07c-698e-4163-aeab-42c2713f35e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3501935619 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3501935619 |
| Directory | /workspace/3.edn_smoke/latest |
| Test location | /workspace/coverage/default/3.edn_stress_all.330286564 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 189321296 ps |
| CPU time | 2.79 seconds |
| Started | Jan 14 12:25:18 PM PST 24 |
| Finished | Jan 14 12:25:22 PM PST 24 |
| Peak memory | 205900 kb |
| Host | smart-33e26d6e-9ba0-4ed2-8e90-8bd3f5c07db2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330286564 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.330286564 |
| Directory | /workspace/3.edn_stress_all/latest |
| Test location | /workspace/coverage/default/3.edn_stress_all_with_rand_reset.4066761191 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 209691541682 ps |
| CPU time | 1213.38 seconds |
| Started | Jan 14 12:25:15 PM PST 24 |
| Finished | Jan 14 12:45:30 PM PST 24 |
| Peak memory | 215560 kb |
| Host | smart-3d51e092-638e-4550-9836-600c9f9ab798 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066761191 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.4066761191 |
| Directory | /workspace/3.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.edn_alert.478604628 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 82794800 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:26:20 PM PST 24 |
| Finished | Jan 14 12:26:22 PM PST 24 |
| Peak memory | 205788 kb |
| Host | smart-7c5c877b-aaad-49a7-8b8f-3255d193b9ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=478604628 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.478604628 |
| Directory | /workspace/30.edn_alert/latest |
| Test location | /workspace/coverage/default/30.edn_alert_test.1386143971 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 22011985 ps |
| CPU time | 0.8 seconds |
| Started | Jan 14 12:26:10 PM PST 24 |
| Finished | Jan 14 12:26:11 PM PST 24 |
| Peak memory | 204980 kb |
| Host | smart-8d7c16c0-fb63-4519-a18a-87a60a48f8ae |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386143971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1386143971 |
| Directory | /workspace/30.edn_alert_test/latest |
| Test location | /workspace/coverage/default/30.edn_disable.1141746578 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 24523598 ps |
| CPU time | 0.79 seconds |
| Started | Jan 14 12:26:10 PM PST 24 |
| Finished | Jan 14 12:26:12 PM PST 24 |
| Peak memory | 214260 kb |
| Host | smart-d66bd48f-87f4-4c4c-868e-616ea83b3c7a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141746578 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1141746578 |
| Directory | /workspace/30.edn_disable/latest |
| Test location | /workspace/coverage/default/30.edn_disable_auto_req_mode.3410665957 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 71928995 ps |
| CPU time | 1.05 seconds |
| Started | Jan 14 12:26:11 PM PST 24 |
| Finished | Jan 14 12:26:12 PM PST 24 |
| Peak memory | 214344 kb |
| Host | smart-1872f1bb-d276-4496-8326-5e3fb84f5bbc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410665957 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d isable_auto_req_mode.3410665957 |
| Directory | /workspace/30.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/30.edn_err.2661421697 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 35614400 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:26:31 PM PST 24 |
| Finished | Jan 14 12:26:33 PM PST 24 |
| Peak memory | 221396 kb |
| Host | smart-fe2ef1f1-4013-488d-834c-57951ac90cd6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2661421697 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2661421697 |
| Directory | /workspace/30.edn_err/latest |
| Test location | /workspace/coverage/default/30.edn_genbits.3992944827 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 18041383 ps |
| CPU time | 1.06 seconds |
| Started | Jan 14 12:26:27 PM PST 24 |
| Finished | Jan 14 12:26:29 PM PST 24 |
| Peak memory | 205348 kb |
| Host | smart-28123243-497a-4243-b795-c311f48b28e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3992944827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3992944827 |
| Directory | /workspace/30.edn_genbits/latest |
| Test location | /workspace/coverage/default/30.edn_intr.1181775005 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 52986201 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:26:20 PM PST 24 |
| Finished | Jan 14 12:26:23 PM PST 24 |
| Peak memory | 214060 kb |
| Host | smart-c085bd75-9ddf-4a20-ac23-9eceb32c5ec4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1181775005 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1181775005 |
| Directory | /workspace/30.edn_intr/latest |
| Test location | /workspace/coverage/default/30.edn_smoke.4049133703 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 20136472 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:07 PM PST 24 |
| Finished | Jan 14 12:26:09 PM PST 24 |
| Peak memory | 204512 kb |
| Host | smart-2fad4a4b-8633-4e67-9ff8-6bbd637045c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4049133703 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.4049133703 |
| Directory | /workspace/30.edn_smoke/latest |
| Test location | /workspace/coverage/default/30.edn_stress_all.4102211079 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 169581041 ps |
| CPU time | 3.83 seconds |
| Started | Jan 14 12:26:33 PM PST 24 |
| Finished | Jan 14 12:26:37 PM PST 24 |
| Peak memory | 205876 kb |
| Host | smart-a4af14d6-4303-49af-b959-b5d9520c8f92 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102211079 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.4102211079 |
| Directory | /workspace/30.edn_stress_all/latest |
| Test location | /workspace/coverage/default/30.edn_stress_all_with_rand_reset.4268147521 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 58204368076 ps |
| CPU time | 1458.88 seconds |
| Started | Jan 14 12:26:18 PM PST 24 |
| Finished | Jan 14 12:50:37 PM PST 24 |
| Peak memory | 218588 kb |
| Host | smart-66c6666b-a216-40d9-8cdd-3d7734864d20 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268147521 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.4268147521 |
| Directory | /workspace/30.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.edn_alert_test.3094143010 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 16025930 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:32 PM PST 24 |
| Finished | Jan 14 12:26:33 PM PST 24 |
| Peak memory | 205004 kb |
| Host | smart-fa64761b-61e9-4a3d-9e12-2cc51da3c594 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094143010 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3094143010 |
| Directory | /workspace/31.edn_alert_test/latest |
| Test location | /workspace/coverage/default/31.edn_disable.2310822355 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 56937334 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:26:20 PM PST 24 |
| Finished | Jan 14 12:26:22 PM PST 24 |
| Peak memory | 214252 kb |
| Host | smart-88df775a-277b-4e2b-92d1-4e07a737638f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310822355 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2310822355 |
| Directory | /workspace/31.edn_disable/latest |
| Test location | /workspace/coverage/default/31.edn_disable_auto_req_mode.3537330510 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 30314033 ps |
| CPU time | 1.05 seconds |
| Started | Jan 14 12:26:13 PM PST 24 |
| Finished | Jan 14 12:26:21 PM PST 24 |
| Peak memory | 214416 kb |
| Host | smart-fc2e9b07-f59b-4714-842d-4c614c46c6cf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537330510 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d isable_auto_req_mode.3537330510 |
| Directory | /workspace/31.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/31.edn_err.1431408058 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 23431794 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:26:29 PM PST 24 |
| Finished | Jan 14 12:26:30 PM PST 24 |
| Peak memory | 215828 kb |
| Host | smart-275f8cab-645a-4641-8828-57fb7902762e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1431408058 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1431408058 |
| Directory | /workspace/31.edn_err/latest |
| Test location | /workspace/coverage/default/31.edn_genbits.3505166818 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 27859002 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:26:17 PM PST 24 |
| Finished | Jan 14 12:26:18 PM PST 24 |
| Peak memory | 205568 kb |
| Host | smart-9db054ab-fcd1-40cd-a1bd-1e75087d1c62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3505166818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3505166818 |
| Directory | /workspace/31.edn_genbits/latest |
| Test location | /workspace/coverage/default/31.edn_intr.319557321 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 27604208 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:26:11 PM PST 24 |
| Finished | Jan 14 12:26:12 PM PST 24 |
| Peak memory | 214248 kb |
| Host | smart-db8bfa4c-9e40-4204-b548-ec4abaefe94c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=319557321 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.319557321 |
| Directory | /workspace/31.edn_intr/latest |
| Test location | /workspace/coverage/default/31.edn_smoke.84226100 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 41603768 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:26:20 PM PST 24 |
| Finished | Jan 14 12:26:22 PM PST 24 |
| Peak memory | 204692 kb |
| Host | smart-ffec77d5-dd5e-4929-913a-6e3e1f09b3e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=84226100 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.84226100 |
| Directory | /workspace/31.edn_smoke/latest |
| Test location | /workspace/coverage/default/31.edn_stress_all.1137822879 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 279842486 ps |
| CPU time | 3.18 seconds |
| Started | Jan 14 12:26:06 PM PST 24 |
| Finished | Jan 14 12:26:09 PM PST 24 |
| Peak memory | 205844 kb |
| Host | smart-cdaba9de-4abf-49d7-a379-0a3943ca972c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137822879 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1137822879 |
| Directory | /workspace/31.edn_stress_all/latest |
| Test location | /workspace/coverage/default/31.edn_stress_all_with_rand_reset.62529921 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 130389955402 ps |
| CPU time | 1952.67 seconds |
| Started | Jan 14 12:26:20 PM PST 24 |
| Finished | Jan 14 12:58:54 PM PST 24 |
| Peak memory | 220208 kb |
| Host | smart-23436278-c5dd-4c52-9a78-8618da1242f9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62529921 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.62529921 |
| Directory | /workspace/31.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.edn_alert.3631673323 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 20891141 ps |
| CPU time | 1.01 seconds |
| Started | Jan 14 12:26:30 PM PST 24 |
| Finished | Jan 14 12:26:32 PM PST 24 |
| Peak memory | 205276 kb |
| Host | smart-98b07a57-481a-4207-bd2b-2c01fb1dacce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3631673323 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3631673323 |
| Directory | /workspace/32.edn_alert/latest |
| Test location | /workspace/coverage/default/32.edn_alert_test.3122096386 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 89429084 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:26:18 PM PST 24 |
| Finished | Jan 14 12:26:21 PM PST 24 |
| Peak memory | 204544 kb |
| Host | smart-da35cad0-6507-4a9b-9bdf-099e37a472a4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122096386 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3122096386 |
| Directory | /workspace/32.edn_alert_test/latest |
| Test location | /workspace/coverage/default/32.edn_disable.4245782892 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 12664670 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:26:19 PM PST 24 |
| Finished | Jan 14 12:26:21 PM PST 24 |
| Peak memory | 214288 kb |
| Host | smart-d771f257-4683-4239-86d5-0841aed7b2c8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245782892 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.4245782892 |
| Directory | /workspace/32.edn_disable/latest |
| Test location | /workspace/coverage/default/32.edn_disable_auto_req_mode.3223875228 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 49357805 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:19 PM PST 24 |
| Finished | Jan 14 12:26:21 PM PST 24 |
| Peak memory | 214404 kb |
| Host | smart-089414a7-34e8-4d93-80a5-352566839fbe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223875228 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d isable_auto_req_mode.3223875228 |
| Directory | /workspace/32.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/32.edn_err.112977927 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 29256297 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:17 PM PST 24 |
| Finished | Jan 14 12:26:19 PM PST 24 |
| Peak memory | 221364 kb |
| Host | smart-065b9aa7-54aa-451e-b671-0f5afbfff3eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=112977927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.112977927 |
| Directory | /workspace/32.edn_err/latest |
| Test location | /workspace/coverage/default/32.edn_genbits.4277038819 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 25653978 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:26:24 PM PST 24 |
| Finished | Jan 14 12:26:25 PM PST 24 |
| Peak memory | 204944 kb |
| Host | smart-93a9dfbd-7bb2-4bc4-8a9c-43c954252a79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4277038819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.4277038819 |
| Directory | /workspace/32.edn_genbits/latest |
| Test location | /workspace/coverage/default/32.edn_intr.4158228838 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 85807548 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:26:18 PM PST 24 |
| Finished | Jan 14 12:26:19 PM PST 24 |
| Peak memory | 220628 kb |
| Host | smart-7a2cdec4-b803-4665-8153-9c743bc44f25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4158228838 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.4158228838 |
| Directory | /workspace/32.edn_intr/latest |
| Test location | /workspace/coverage/default/32.edn_smoke.1748326022 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 13828341 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:26:22 PM PST 24 |
| Finished | Jan 14 12:26:23 PM PST 24 |
| Peak memory | 204724 kb |
| Host | smart-710c6be8-d782-46d3-83c9-9f3147a113e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1748326022 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1748326022 |
| Directory | /workspace/32.edn_smoke/latest |
| Test location | /workspace/coverage/default/32.edn_stress_all.3940195890 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 213337685 ps |
| CPU time | 2.8 seconds |
| Started | Jan 14 12:26:26 PM PST 24 |
| Finished | Jan 14 12:26:29 PM PST 24 |
| Peak memory | 205908 kb |
| Host | smart-b76ff870-703c-46c4-92f7-361083e153ca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940195890 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3940195890 |
| Directory | /workspace/32.edn_stress_all/latest |
| Test location | /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1233422304 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 169943863997 ps |
| CPU time | 702.05 seconds |
| Started | Jan 14 12:26:18 PM PST 24 |
| Finished | Jan 14 12:38:02 PM PST 24 |
| Peak memory | 214536 kb |
| Host | smart-cd13da84-d123-4ed3-8b29-c3628679f14f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233422304 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1233422304 |
| Directory | /workspace/32.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.edn_alert.1002923216 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 34731686 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:26:18 PM PST 24 |
| Finished | Jan 14 12:26:20 PM PST 24 |
| Peak memory | 205588 kb |
| Host | smart-8ce6725e-de26-4bc0-9d6d-e843d5edc1af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1002923216 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1002923216 |
| Directory | /workspace/33.edn_alert/latest |
| Test location | /workspace/coverage/default/33.edn_alert_test.3821324043 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 14448406 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:26:18 PM PST 24 |
| Finished | Jan 14 12:26:21 PM PST 24 |
| Peak memory | 204380 kb |
| Host | smart-e51f99fc-6af8-4bc0-8968-cf104c6345e5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821324043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3821324043 |
| Directory | /workspace/33.edn_alert_test/latest |
| Test location | /workspace/coverage/default/33.edn_disable_auto_req_mode.1054282607 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 25496036 ps |
| CPU time | 1.09 seconds |
| Started | Jan 14 12:26:20 PM PST 24 |
| Finished | Jan 14 12:26:23 PM PST 24 |
| Peak memory | 213636 kb |
| Host | smart-8acbd3ad-7d6c-4f0f-83e6-447e8a633fe8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054282607 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d isable_auto_req_mode.1054282607 |
| Directory | /workspace/33.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/33.edn_err.3773848219 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 24082843 ps |
| CPU time | 1.14 seconds |
| Started | Jan 14 12:26:18 PM PST 24 |
| Finished | Jan 14 12:26:20 PM PST 24 |
| Peak memory | 215892 kb |
| Host | smart-19f0977d-c4e0-470f-9096-aa6f0bbeb9bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3773848219 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.3773848219 |
| Directory | /workspace/33.edn_err/latest |
| Test location | /workspace/coverage/default/33.edn_genbits.1429232361 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 60101878 ps |
| CPU time | 0.87 seconds |
| Started | Jan 14 12:26:17 PM PST 24 |
| Finished | Jan 14 12:26:19 PM PST 24 |
| Peak memory | 204972 kb |
| Host | smart-e0c10e23-abb4-418a-b0f5-3dbd479e1c5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1429232361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1429232361 |
| Directory | /workspace/33.edn_genbits/latest |
| Test location | /workspace/coverage/default/33.edn_intr.3795798493 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 32184241 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 12:26:17 PM PST 24 |
| Finished | Jan 14 12:26:19 PM PST 24 |
| Peak memory | 213828 kb |
| Host | smart-f16dfe43-f916-4d51-999f-adf075135241 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3795798493 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3795798493 |
| Directory | /workspace/33.edn_intr/latest |
| Test location | /workspace/coverage/default/33.edn_smoke.3081044100 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 29511019 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:26:16 PM PST 24 |
| Finished | Jan 14 12:26:17 PM PST 24 |
| Peak memory | 204592 kb |
| Host | smart-8cb77010-f9bc-42cc-ade5-61037d3ebd6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3081044100 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3081044100 |
| Directory | /workspace/33.edn_smoke/latest |
| Test location | /workspace/coverage/default/33.edn_stress_all.168345091 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 167444912 ps |
| CPU time | 3.6 seconds |
| Started | Jan 14 12:26:17 PM PST 24 |
| Finished | Jan 14 12:26:22 PM PST 24 |
| Peak memory | 205916 kb |
| Host | smart-838f7b62-6a09-4512-a7c7-2c060ae2b436 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168345091 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.168345091 |
| Directory | /workspace/33.edn_stress_all/latest |
| Test location | /workspace/coverage/default/34.edn_alert.2287936857 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 35787989 ps |
| CPU time | 1 seconds |
| Started | Jan 14 12:26:09 PM PST 24 |
| Finished | Jan 14 12:26:11 PM PST 24 |
| Peak memory | 204968 kb |
| Host | smart-24e2cf57-2bf6-452a-af95-7d2dc1070bea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2287936857 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2287936857 |
| Directory | /workspace/34.edn_alert/latest |
| Test location | /workspace/coverage/default/34.edn_alert_test.4147593351 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 22347328 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:26:16 PM PST 24 |
| Finished | Jan 14 12:26:17 PM PST 24 |
| Peak memory | 204960 kb |
| Host | smart-e70d8da7-0d7a-4d63-a0db-3ca75bc889f9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147593351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.4147593351 |
| Directory | /workspace/34.edn_alert_test/latest |
| Test location | /workspace/coverage/default/34.edn_disable.578884433 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 27323608 ps |
| CPU time | 0.79 seconds |
| Started | Jan 14 12:26:37 PM PST 24 |
| Finished | Jan 14 12:26:38 PM PST 24 |
| Peak memory | 214252 kb |
| Host | smart-29ce7153-642b-4d66-87b8-18e3678034fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578884433 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.578884433 |
| Directory | /workspace/34.edn_disable/latest |
| Test location | /workspace/coverage/default/34.edn_disable_auto_req_mode.1821377035 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 41965524 ps |
| CPU time | 1.01 seconds |
| Started | Jan 14 12:26:37 PM PST 24 |
| Finished | Jan 14 12:26:39 PM PST 24 |
| Peak memory | 214436 kb |
| Host | smart-d5f28e21-be68-4dec-8439-c3922a095f82 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821377035 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d isable_auto_req_mode.1821377035 |
| Directory | /workspace/34.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/34.edn_err.2126635442 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 22241533 ps |
| CPU time | 1.07 seconds |
| Started | Jan 14 12:26:19 PM PST 24 |
| Finished | Jan 14 12:26:21 PM PST 24 |
| Peak memory | 216028 kb |
| Host | smart-52387885-cbbc-4f32-a4a4-5e7c454044de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2126635442 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2126635442 |
| Directory | /workspace/34.edn_err/latest |
| Test location | /workspace/coverage/default/34.edn_genbits.1985468415 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 16924259 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:26:21 PM PST 24 |
| Finished | Jan 14 12:26:23 PM PST 24 |
| Peak memory | 204816 kb |
| Host | smart-c6359962-de3c-4e50-b426-f97086dfa558 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1985468415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1985468415 |
| Directory | /workspace/34.edn_genbits/latest |
| Test location | /workspace/coverage/default/34.edn_intr.482441299 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 22554086 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:13 PM PST 24 |
| Finished | Jan 14 12:26:15 PM PST 24 |
| Peak memory | 214392 kb |
| Host | smart-1b9daa2a-5fc8-48a0-9b77-7f83a7ac4555 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=482441299 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.482441299 |
| Directory | /workspace/34.edn_intr/latest |
| Test location | /workspace/coverage/default/34.edn_smoke.2556056148 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 16221938 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:26:44 PM PST 24 |
| Finished | Jan 14 12:26:45 PM PST 24 |
| Peak memory | 204444 kb |
| Host | smart-3ca3d3af-5896-4f7b-a7c4-8e2636d62293 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2556056148 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2556056148 |
| Directory | /workspace/34.edn_smoke/latest |
| Test location | /workspace/coverage/default/34.edn_stress_all.1773908043 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 66507872 ps |
| CPU time | 1.78 seconds |
| Started | Jan 14 12:26:17 PM PST 24 |
| Finished | Jan 14 12:26:20 PM PST 24 |
| Peak memory | 205444 kb |
| Host | smart-67042718-1792-4f96-a75c-6c94f1547124 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773908043 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1773908043 |
| Directory | /workspace/34.edn_stress_all/latest |
| Test location | /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1003977359 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 224309331036 ps |
| CPU time | 628.38 seconds |
| Started | Jan 14 12:26:37 PM PST 24 |
| Finished | Jan 14 12:37:05 PM PST 24 |
| Peak memory | 220452 kb |
| Host | smart-7eae09e9-294e-4705-a676-1afd48df5327 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003977359 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1003977359 |
| Directory | /workspace/34.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.edn_alert.2258265053 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 50245915 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:21 PM PST 24 |
| Finished | Jan 14 12:26:23 PM PST 24 |
| Peak memory | 205852 kb |
| Host | smart-1c306baf-ee2c-4c69-b7cb-5ce419251c82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2258265053 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2258265053 |
| Directory | /workspace/35.edn_alert/latest |
| Test location | /workspace/coverage/default/35.edn_alert_test.4000659270 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 21418638 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:26:20 PM PST 24 |
| Finished | Jan 14 12:26:23 PM PST 24 |
| Peak memory | 205056 kb |
| Host | smart-802e8ba0-c89c-449b-a988-d51d01e22269 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000659270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.4000659270 |
| Directory | /workspace/35.edn_alert_test/latest |
| Test location | /workspace/coverage/default/35.edn_disable_auto_req_mode.595020512 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 41587928 ps |
| CPU time | 1.04 seconds |
| Started | Jan 14 12:26:20 PM PST 24 |
| Finished | Jan 14 12:26:22 PM PST 24 |
| Peak memory | 214404 kb |
| Host | smart-8379f889-bfef-4411-af30-cf649a0ba75d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595020512 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di sable_auto_req_mode.595020512 |
| Directory | /workspace/35.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/35.edn_intr.3229552015 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 25953314 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:26:19 PM PST 24 |
| Finished | Jan 14 12:26:21 PM PST 24 |
| Peak memory | 214380 kb |
| Host | smart-e61bdd9c-c604-4d94-8069-c382a95cbdc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3229552015 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3229552015 |
| Directory | /workspace/35.edn_intr/latest |
| Test location | /workspace/coverage/default/35.edn_smoke.650995842 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 11514044 ps |
| CPU time | 0.84 seconds |
| Started | Jan 14 12:26:11 PM PST 24 |
| Finished | Jan 14 12:26:12 PM PST 24 |
| Peak memory | 204456 kb |
| Host | smart-c7892924-d8aa-469e-9cbd-2000720ebddd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=650995842 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.650995842 |
| Directory | /workspace/35.edn_smoke/latest |
| Test location | /workspace/coverage/default/35.edn_stress_all.2772864398 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 605116528 ps |
| CPU time | 2.07 seconds |
| Started | Jan 14 12:26:19 PM PST 24 |
| Finished | Jan 14 12:26:22 PM PST 24 |
| Peak memory | 205876 kb |
| Host | smart-7b08694d-c1bd-468f-847f-06d7eca66558 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772864398 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2772864398 |
| Directory | /workspace/35.edn_stress_all/latest |
| Test location | /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2306526076 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 37861123501 ps |
| CPU time | 852.01 seconds |
| Started | Jan 14 12:26:25 PM PST 24 |
| Finished | Jan 14 12:40:38 PM PST 24 |
| Peak memory | 217184 kb |
| Host | smart-0cb318cf-0e0b-493d-9be0-50a0e65dbff4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306526076 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2306526076 |
| Directory | /workspace/35.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.edn_alert.2642520882 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 26851640 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:26:27 PM PST 24 |
| Finished | Jan 14 12:26:28 PM PST 24 |
| Peak memory | 205928 kb |
| Host | smart-4adc4025-cf8e-4248-baa3-64c7950d3796 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2642520882 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2642520882 |
| Directory | /workspace/36.edn_alert/latest |
| Test location | /workspace/coverage/default/36.edn_alert_test.2637886637 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 12645349 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:26:26 PM PST 24 |
| Finished | Jan 14 12:26:27 PM PST 24 |
| Peak memory | 204352 kb |
| Host | smart-7ccaabe8-316b-44cf-a340-7818826bc28c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637886637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2637886637 |
| Directory | /workspace/36.edn_alert_test/latest |
| Test location | /workspace/coverage/default/36.edn_disable_auto_req_mode.2600890539 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 38287280 ps |
| CPU time | 1.05 seconds |
| Started | Jan 14 12:26:10 PM PST 24 |
| Finished | Jan 14 12:26:12 PM PST 24 |
| Peak memory | 214456 kb |
| Host | smart-06536e41-bec4-4407-844c-742c62670442 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600890539 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d isable_auto_req_mode.2600890539 |
| Directory | /workspace/36.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/36.edn_err.715580436 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 17895520 ps |
| CPU time | 1.09 seconds |
| Started | Jan 14 12:26:13 PM PST 24 |
| Finished | Jan 14 12:26:15 PM PST 24 |
| Peak memory | 221804 kb |
| Host | smart-3988951c-89ef-438e-aad8-79833fe138ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=715580436 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.715580436 |
| Directory | /workspace/36.edn_err/latest |
| Test location | /workspace/coverage/default/36.edn_genbits.1567234891 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 21194934 ps |
| CPU time | 1.01 seconds |
| Started | Jan 14 12:26:29 PM PST 24 |
| Finished | Jan 14 12:26:30 PM PST 24 |
| Peak memory | 205564 kb |
| Host | smart-68955e2e-4e6a-408a-8ee8-9170b3fbc2c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1567234891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1567234891 |
| Directory | /workspace/36.edn_genbits/latest |
| Test location | /workspace/coverage/default/36.edn_intr.1455808088 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 19708438 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:26:20 PM PST 24 |
| Finished | Jan 14 12:26:22 PM PST 24 |
| Peak memory | 214336 kb |
| Host | smart-fb3488d9-b0d0-4151-a236-694cf4ea8319 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1455808088 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1455808088 |
| Directory | /workspace/36.edn_intr/latest |
| Test location | /workspace/coverage/default/36.edn_smoke.2731441414 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 14624825 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:26:18 PM PST 24 |
| Finished | Jan 14 12:26:20 PM PST 24 |
| Peak memory | 204528 kb |
| Host | smart-e69f2a16-47fa-4fa5-aaf4-96c7e22e48a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2731441414 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2731441414 |
| Directory | /workspace/36.edn_smoke/latest |
| Test location | /workspace/coverage/default/36.edn_stress_all.180588983 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 78562935 ps |
| CPU time | 2.01 seconds |
| Started | Jan 14 12:26:39 PM PST 24 |
| Finished | Jan 14 12:26:41 PM PST 24 |
| Peak memory | 205892 kb |
| Host | smart-8727e13a-6adf-401f-9b1b-4d189eff3ab4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180588983 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.180588983 |
| Directory | /workspace/36.edn_stress_all/latest |
| Test location | /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1050342621 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 121288239052 ps |
| CPU time | 1821.69 seconds |
| Started | Jan 14 12:26:25 PM PST 24 |
| Finished | Jan 14 12:56:47 PM PST 24 |
| Peak memory | 219236 kb |
| Host | smart-2ab27056-37c4-483a-a9f2-c3ba70b427c9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050342621 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1050342621 |
| Directory | /workspace/36.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.edn_alert.403185763 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 20399387 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:26:13 PM PST 24 |
| Finished | Jan 14 12:26:14 PM PST 24 |
| Peak memory | 205808 kb |
| Host | smart-a401a181-387c-4e92-880a-a87961b6aa10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=403185763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.403185763 |
| Directory | /workspace/37.edn_alert/latest |
| Test location | /workspace/coverage/default/37.edn_alert_test.784572545 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 197754769 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:26:26 PM PST 24 |
| Finished | Jan 14 12:26:27 PM PST 24 |
| Peak memory | 205256 kb |
| Host | smart-0fe1be70-928e-4b5a-9d0f-d0a55a1735cb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784572545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.784572545 |
| Directory | /workspace/37.edn_alert_test/latest |
| Test location | /workspace/coverage/default/37.edn_disable.3716464701 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 56907670 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 12:26:19 PM PST 24 |
| Finished | Jan 14 12:26:21 PM PST 24 |
| Peak memory | 214300 kb |
| Host | smart-3b8c6429-e0f6-4cd8-a7ba-fe985d7e8558 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716464701 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3716464701 |
| Directory | /workspace/37.edn_disable/latest |
| Test location | /workspace/coverage/default/37.edn_disable_auto_req_mode.3446295233 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 39280708 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:26:34 PM PST 24 |
| Finished | Jan 14 12:26:35 PM PST 24 |
| Peak memory | 214384 kb |
| Host | smart-6005e3dc-86d0-49f7-bf05-130153987e5b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446295233 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d isable_auto_req_mode.3446295233 |
| Directory | /workspace/37.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/37.edn_err.510937939 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 19638524 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:26:28 PM PST 24 |
| Finished | Jan 14 12:26:29 PM PST 24 |
| Peak memory | 215704 kb |
| Host | smart-50668268-ffd2-4c3f-b8df-dd8078acfd8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=510937939 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.510937939 |
| Directory | /workspace/37.edn_err/latest |
| Test location | /workspace/coverage/default/37.edn_genbits.3420421413 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 23819979 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:18 PM PST 24 |
| Finished | Jan 14 12:26:19 PM PST 24 |
| Peak memory | 204840 kb |
| Host | smart-cae9a216-4ab3-4512-aff1-dc7e05439301 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3420421413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3420421413 |
| Directory | /workspace/37.edn_genbits/latest |
| Test location | /workspace/coverage/default/37.edn_intr.3621849438 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 18647874 ps |
| CPU time | 1.13 seconds |
| Started | Jan 14 12:26:17 PM PST 24 |
| Finished | Jan 14 12:26:19 PM PST 24 |
| Peak memory | 221424 kb |
| Host | smart-c9da1f2d-1a94-4edb-b4ad-f4b350417edf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3621849438 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3621849438 |
| Directory | /workspace/37.edn_intr/latest |
| Test location | /workspace/coverage/default/37.edn_smoke.629002753 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 12558090 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:26:30 PM PST 24 |
| Finished | Jan 14 12:26:42 PM PST 24 |
| Peak memory | 205116 kb |
| Host | smart-32559c47-3027-45a6-bd8b-657b30fd8142 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=629002753 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.629002753 |
| Directory | /workspace/37.edn_smoke/latest |
| Test location | /workspace/coverage/default/37.edn_stress_all.2992322484 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 166853722 ps |
| CPU time | 1.45 seconds |
| Started | Jan 14 12:26:17 PM PST 24 |
| Finished | Jan 14 12:26:19 PM PST 24 |
| Peak memory | 205444 kb |
| Host | smart-721c2454-3267-44d7-ba02-a34c7ed73100 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992322484 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2992322484 |
| Directory | /workspace/37.edn_stress_all/latest |
| Test location | /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1615807589 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 24203970078 ps |
| CPU time | 530.03 seconds |
| Started | Jan 14 12:26:34 PM PST 24 |
| Finished | Jan 14 12:35:25 PM PST 24 |
| Peak memory | 214512 kb |
| Host | smart-e179f6f7-604e-488a-b059-f016d4183a32 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615807589 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1615807589 |
| Directory | /workspace/37.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.edn_alert.2129633414 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 60809085 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:26:14 PM PST 24 |
| Finished | Jan 14 12:26:20 PM PST 24 |
| Peak memory | 205188 kb |
| Host | smart-2878bd54-25f6-43a1-a942-d013134c63aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2129633414 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2129633414 |
| Directory | /workspace/38.edn_alert/latest |
| Test location | /workspace/coverage/default/38.edn_alert_test.3401166578 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 27482574 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:26:18 PM PST 24 |
| Finished | Jan 14 12:26:20 PM PST 24 |
| Peak memory | 205356 kb |
| Host | smart-b8c9a22e-5b87-4ce5-8c55-c4529c8ff792 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401166578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3401166578 |
| Directory | /workspace/38.edn_alert_test/latest |
| Test location | /workspace/coverage/default/38.edn_disable.3018431008 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 13804109 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:22 PM PST 24 |
| Finished | Jan 14 12:26:24 PM PST 24 |
| Peak memory | 214300 kb |
| Host | smart-d827832d-b5c8-4b6a-b0be-a78f3dff9137 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018431008 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3018431008 |
| Directory | /workspace/38.edn_disable/latest |
| Test location | /workspace/coverage/default/38.edn_disable_auto_req_mode.1713352658 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 39568812 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:26:15 PM PST 24 |
| Finished | Jan 14 12:26:17 PM PST 24 |
| Peak memory | 214420 kb |
| Host | smart-f1ad1da2-d145-4075-abc3-a57cec0970be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713352658 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d isable_auto_req_mode.1713352658 |
| Directory | /workspace/38.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/38.edn_err.2724365897 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 29008034 ps |
| CPU time | 1.13 seconds |
| Started | Jan 14 12:26:43 PM PST 24 |
| Finished | Jan 14 12:26:45 PM PST 24 |
| Peak memory | 216108 kb |
| Host | smart-4c607899-ea58-4ea2-935d-140435aced69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2724365897 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2724365897 |
| Directory | /workspace/38.edn_err/latest |
| Test location | /workspace/coverage/default/38.edn_genbits.1694482868 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 74008958 ps |
| CPU time | 1.06 seconds |
| Started | Jan 14 12:26:19 PM PST 24 |
| Finished | Jan 14 12:26:22 PM PST 24 |
| Peak memory | 205408 kb |
| Host | smart-31809057-17ad-4a80-a791-439cace16715 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1694482868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1694482868 |
| Directory | /workspace/38.edn_genbits/latest |
| Test location | /workspace/coverage/default/38.edn_intr.3255567895 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 39077327 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:26:12 PM PST 24 |
| Finished | Jan 14 12:26:13 PM PST 24 |
| Peak memory | 214336 kb |
| Host | smart-c4e777ec-f9d0-48a8-8a62-547a531d89e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3255567895 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3255567895 |
| Directory | /workspace/38.edn_intr/latest |
| Test location | /workspace/coverage/default/38.edn_smoke.3040385629 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 49131267 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:26:19 PM PST 24 |
| Finished | Jan 14 12:26:21 PM PST 24 |
| Peak memory | 204556 kb |
| Host | smart-73a83269-7343-4734-9e1a-97f067dc9d7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3040385629 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3040385629 |
| Directory | /workspace/38.edn_smoke/latest |
| Test location | /workspace/coverage/default/38.edn_stress_all.197910089 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 565998976 ps |
| CPU time | 3.39 seconds |
| Started | Jan 14 12:26:17 PM PST 24 |
| Finished | Jan 14 12:26:21 PM PST 24 |
| Peak memory | 205824 kb |
| Host | smart-b0188bb4-5d4a-4b8c-a4e6-1b1644eaa2fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197910089 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.197910089 |
| Directory | /workspace/38.edn_stress_all/latest |
| Test location | /workspace/coverage/default/38.edn_stress_all_with_rand_reset.4086318858 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 521724192510 ps |
| CPU time | 2505.21 seconds |
| Started | Jan 14 12:26:15 PM PST 24 |
| Finished | Jan 14 01:08:01 PM PST 24 |
| Peak memory | 224620 kb |
| Host | smart-bc2524c3-a74a-49dd-90a7-dc6e29228ca2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086318858 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.4086318858 |
| Directory | /workspace/38.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.edn_alert.3832790800 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 23703724 ps |
| CPU time | 1.06 seconds |
| Started | Jan 14 12:26:40 PM PST 24 |
| Finished | Jan 14 12:26:42 PM PST 24 |
| Peak memory | 205540 kb |
| Host | smart-42551a80-de0a-47ff-931d-bfac537ab60b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3832790800 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3832790800 |
| Directory | /workspace/39.edn_alert/latest |
| Test location | /workspace/coverage/default/39.edn_alert_test.638903056 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 92595940 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:26:26 PM PST 24 |
| Finished | Jan 14 12:26:28 PM PST 24 |
| Peak memory | 204540 kb |
| Host | smart-0b25db57-1b1e-4284-8665-949b427689e3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638903056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.638903056 |
| Directory | /workspace/39.edn_alert_test/latest |
| Test location | /workspace/coverage/default/39.edn_disable.62031495 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 11476029 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:26:13 PM PST 24 |
| Finished | Jan 14 12:26:15 PM PST 24 |
| Peak memory | 214180 kb |
| Host | smart-a1815093-3732-4f0e-a67f-0bb75a426125 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62031495 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.62031495 |
| Directory | /workspace/39.edn_disable/latest |
| Test location | /workspace/coverage/default/39.edn_err.2709135983 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 30319630 ps |
| CPU time | 0.79 seconds |
| Started | Jan 14 12:26:21 PM PST 24 |
| Finished | Jan 14 12:26:23 PM PST 24 |
| Peak memory | 215788 kb |
| Host | smart-87709695-f3ee-4dcb-87ae-127259a18b80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2709135983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2709135983 |
| Directory | /workspace/39.edn_err/latest |
| Test location | /workspace/coverage/default/39.edn_genbits.2565774383 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 17563505 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:26:43 PM PST 24 |
| Finished | Jan 14 12:26:44 PM PST 24 |
| Peak memory | 205336 kb |
| Host | smart-d6677e77-a2fd-44af-8190-ac0ab590e681 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2565774383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2565774383 |
| Directory | /workspace/39.edn_genbits/latest |
| Test location | /workspace/coverage/default/39.edn_intr.1617089076 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 38217242 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:26:34 PM PST 24 |
| Finished | Jan 14 12:26:35 PM PST 24 |
| Peak memory | 221848 kb |
| Host | smart-bcdbb3b0-0193-49c7-95a6-e5d96d53608f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1617089076 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1617089076 |
| Directory | /workspace/39.edn_intr/latest |
| Test location | /workspace/coverage/default/39.edn_smoke.2554043 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 17916866 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:26:15 PM PST 24 |
| Finished | Jan 14 12:26:16 PM PST 24 |
| Peak memory | 204740 kb |
| Host | smart-061a6922-e692-433a-9c47-c34f0cc9805b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2554043 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2554043 |
| Directory | /workspace/39.edn_smoke/latest |
| Test location | /workspace/coverage/default/39.edn_stress_all.1124517799 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 148186913 ps |
| CPU time | 2.86 seconds |
| Started | Jan 14 12:26:14 PM PST 24 |
| Finished | Jan 14 12:26:18 PM PST 24 |
| Peak memory | 205844 kb |
| Host | smart-2aefd577-4f6e-43be-ba16-8ed2d3ceb6ed |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124517799 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1124517799 |
| Directory | /workspace/39.edn_stress_all/latest |
| Test location | /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1223852690 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 77017403393 ps |
| CPU time | 987.94 seconds |
| Started | Jan 14 12:26:44 PM PST 24 |
| Finished | Jan 14 12:43:12 PM PST 24 |
| Peak memory | 216076 kb |
| Host | smart-c19291ea-101f-4fa9-8d60-839385b7f732 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223852690 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1223852690 |
| Directory | /workspace/39.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.edn_alert.3055325591 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 32967484 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:25:31 PM PST 24 |
| Finished | Jan 14 12:25:37 PM PST 24 |
| Peak memory | 205920 kb |
| Host | smart-1b690957-1c9c-4080-8bdc-a5d2d667fc77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3055325591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3055325591 |
| Directory | /workspace/4.edn_alert/latest |
| Test location | /workspace/coverage/default/4.edn_alert_test.741089087 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 15708334 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:25:31 PM PST 24 |
| Finished | Jan 14 12:25:37 PM PST 24 |
| Peak memory | 204420 kb |
| Host | smart-73b90ec5-fd6a-4a74-839c-4e68de4dc32f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741089087 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.741089087 |
| Directory | /workspace/4.edn_alert_test/latest |
| Test location | /workspace/coverage/default/4.edn_disable_auto_req_mode.4127858635 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 90010304 ps |
| CPU time | 1.01 seconds |
| Started | Jan 14 12:25:30 PM PST 24 |
| Finished | Jan 14 12:25:36 PM PST 24 |
| Peak memory | 214348 kb |
| Host | smart-2603ac96-304a-48c3-925e-5c4247077197 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127858635 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di sable_auto_req_mode.4127858635 |
| Directory | /workspace/4.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/4.edn_err.2585747530 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 22472989 ps |
| CPU time | 0.87 seconds |
| Started | Jan 14 12:26:00 PM PST 24 |
| Finished | Jan 14 12:26:02 PM PST 24 |
| Peak memory | 215468 kb |
| Host | smart-c4889530-a259-4745-b7eb-c86cf2e0c2f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2585747530 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2585747530 |
| Directory | /workspace/4.edn_err/latest |
| Test location | /workspace/coverage/default/4.edn_genbits.3956304273 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 64631348 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:25:36 PM PST 24 |
| Finished | Jan 14 12:25:40 PM PST 24 |
| Peak memory | 205340 kb |
| Host | smart-517c18cf-9bd2-4932-9286-4b25f0720c6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3956304273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3956304273 |
| Directory | /workspace/4.edn_genbits/latest |
| Test location | /workspace/coverage/default/4.edn_intr.3029955961 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 28693956 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:25:18 PM PST 24 |
| Finished | Jan 14 12:25:21 PM PST 24 |
| Peak memory | 221852 kb |
| Host | smart-bc99bcf2-b121-45c9-86a0-901db9bd7894 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3029955961 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3029955961 |
| Directory | /workspace/4.edn_intr/latest |
| Test location | /workspace/coverage/default/4.edn_regwen.102501539 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 16574727 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:25:35 PM PST 24 |
| Finished | Jan 14 12:25:39 PM PST 24 |
| Peak memory | 204496 kb |
| Host | smart-f683d86e-29d0-4ea6-926a-b4fe71888aca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=102501539 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.102501539 |
| Directory | /workspace/4.edn_regwen/latest |
| Test location | /workspace/coverage/default/4.edn_sec_cm.1573850303 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 560267356 ps |
| CPU time | 5.18 seconds |
| Started | Jan 14 12:25:14 PM PST 24 |
| Finished | Jan 14 12:25:20 PM PST 24 |
| Peak memory | 233452 kb |
| Host | smart-8c9bb28f-2a04-4187-ae8b-57eb179397a8 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573850303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1573850303 |
| Directory | /workspace/4.edn_sec_cm/latest |
| Test location | /workspace/coverage/default/4.edn_smoke.3748965097 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 13672855 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:25:11 PM PST 24 |
| Finished | Jan 14 12:25:13 PM PST 24 |
| Peak memory | 204460 kb |
| Host | smart-093f1103-e61f-4511-aef4-227be282b77b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748965097 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3748965097 |
| Directory | /workspace/4.edn_smoke/latest |
| Test location | /workspace/coverage/default/4.edn_stress_all.4056612650 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 327082996 ps |
| CPU time | 2.01 seconds |
| Started | Jan 14 12:25:35 PM PST 24 |
| Finished | Jan 14 12:25:45 PM PST 24 |
| Peak memory | 205780 kb |
| Host | smart-6b805a69-e22b-459e-9331-d5f462da5357 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056612650 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.4056612650 |
| Directory | /workspace/4.edn_stress_all/latest |
| Test location | /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1062585311 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 268864305897 ps |
| CPU time | 1475.84 seconds |
| Started | Jan 14 12:25:15 PM PST 24 |
| Finished | Jan 14 12:49:52 PM PST 24 |
| Peak memory | 218584 kb |
| Host | smart-faa1934d-d234-431a-b960-856c3ec02b01 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062585311 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1062585311 |
| Directory | /workspace/4.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.edn_alert.4083423655 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 58688748 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:26:21 PM PST 24 |
| Finished | Jan 14 12:26:23 PM PST 24 |
| Peak memory | 205916 kb |
| Host | smart-3233f3a4-7482-4f57-b4fb-798f07f52b87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4083423655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.4083423655 |
| Directory | /workspace/40.edn_alert/latest |
| Test location | /workspace/coverage/default/40.edn_alert_test.3272160835 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 44306457 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:26:36 PM PST 24 |
| Finished | Jan 14 12:26:38 PM PST 24 |
| Peak memory | 205264 kb |
| Host | smart-d0fe6ef9-dae7-4c54-9395-b496afd3430d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272160835 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3272160835 |
| Directory | /workspace/40.edn_alert_test/latest |
| Test location | /workspace/coverage/default/40.edn_disable.1283573861 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 13706109 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:26:30 PM PST 24 |
| Finished | Jan 14 12:26:31 PM PST 24 |
| Peak memory | 214444 kb |
| Host | smart-f7878872-fccf-43d2-a3ff-86a125447eae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283573861 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1283573861 |
| Directory | /workspace/40.edn_disable/latest |
| Test location | /workspace/coverage/default/40.edn_err.1981756475 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 22398274 ps |
| CPU time | 1 seconds |
| Started | Jan 14 12:26:23 PM PST 24 |
| Finished | Jan 14 12:26:25 PM PST 24 |
| Peak memory | 215880 kb |
| Host | smart-bce20e28-ebbc-4f04-87f0-9b1d4bbdae90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1981756475 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1981756475 |
| Directory | /workspace/40.edn_err/latest |
| Test location | /workspace/coverage/default/40.edn_genbits.3166486205 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 50561452 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:26:52 PM PST 24 |
| Finished | Jan 14 12:26:54 PM PST 24 |
| Peak memory | 205076 kb |
| Host | smart-46e9cf77-537c-407c-a43f-2530c06a4bca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3166486205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3166486205 |
| Directory | /workspace/40.edn_genbits/latest |
| Test location | /workspace/coverage/default/40.edn_intr.10096048 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 25644259 ps |
| CPU time | 0.84 seconds |
| Started | Jan 14 12:26:23 PM PST 24 |
| Finished | Jan 14 12:26:24 PM PST 24 |
| Peak memory | 214272 kb |
| Host | smart-71ccabd7-2faf-4581-b2e2-037227f2a1ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=10096048 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.10096048 |
| Directory | /workspace/40.edn_intr/latest |
| Test location | /workspace/coverage/default/40.edn_smoke.3479548703 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 14137452 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:26:22 PM PST 24 |
| Finished | Jan 14 12:26:24 PM PST 24 |
| Peak memory | 204564 kb |
| Host | smart-026d7e7d-1067-436f-a5c2-acc0a542ebdf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3479548703 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3479548703 |
| Directory | /workspace/40.edn_smoke/latest |
| Test location | /workspace/coverage/default/40.edn_stress_all.839926988 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 237004449 ps |
| CPU time | 1.68 seconds |
| Started | Jan 14 12:26:27 PM PST 24 |
| Finished | Jan 14 12:26:29 PM PST 24 |
| Peak memory | 205880 kb |
| Host | smart-b815b6cc-e408-48b7-9899-6c8f05e36308 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839926988 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.839926988 |
| Directory | /workspace/40.edn_stress_all/latest |
| Test location | /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3482465291 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 103043634607 ps |
| CPU time | 672.04 seconds |
| Started | Jan 14 12:26:44 PM PST 24 |
| Finished | Jan 14 12:37:56 PM PST 24 |
| Peak memory | 215364 kb |
| Host | smart-d7ff9e8e-43c2-48fd-9537-28e9f93e3071 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482465291 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3482465291 |
| Directory | /workspace/40.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.edn_alert.2951298064 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 18692672 ps |
| CPU time | 1 seconds |
| Started | Jan 14 12:26:42 PM PST 24 |
| Finished | Jan 14 12:26:44 PM PST 24 |
| Peak memory | 205844 kb |
| Host | smart-ca4cafaa-2bc9-4cec-a8b9-39e48866c065 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2951298064 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2951298064 |
| Directory | /workspace/41.edn_alert/latest |
| Test location | /workspace/coverage/default/41.edn_alert_test.3714537372 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 17106568 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:26:52 PM PST 24 |
| Finished | Jan 14 12:26:53 PM PST 24 |
| Peak memory | 204448 kb |
| Host | smart-fb0dabbb-798d-41e7-8544-7541bb3fd9dc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714537372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.3714537372 |
| Directory | /workspace/41.edn_alert_test/latest |
| Test location | /workspace/coverage/default/41.edn_disable.2655593462 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 22186194 ps |
| CPU time | 0.76 seconds |
| Started | Jan 14 12:26:22 PM PST 24 |
| Finished | Jan 14 12:26:24 PM PST 24 |
| Peak memory | 214304 kb |
| Host | smart-cef9aaa8-f728-430d-b1f4-a33e37f51332 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655593462 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.2655593462 |
| Directory | /workspace/41.edn_disable/latest |
| Test location | /workspace/coverage/default/41.edn_disable_auto_req_mode.2866358992 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 59031799 ps |
| CPU time | 1 seconds |
| Started | Jan 14 12:26:22 PM PST 24 |
| Finished | Jan 14 12:26:24 PM PST 24 |
| Peak memory | 206292 kb |
| Host | smart-2df567b8-4f88-414e-b9e8-9436f51ca408 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866358992 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d isable_auto_req_mode.2866358992 |
| Directory | /workspace/41.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/41.edn_err.1697890929 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 22427686 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:26:22 PM PST 24 |
| Finished | Jan 14 12:26:24 PM PST 24 |
| Peak memory | 215540 kb |
| Host | smart-f1c2cb52-ff5d-432d-900e-6a3d25d44f3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1697890929 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1697890929 |
| Directory | /workspace/41.edn_err/latest |
| Test location | /workspace/coverage/default/41.edn_genbits.92930907 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 33028819 ps |
| CPU time | 1.58 seconds |
| Started | Jan 14 12:26:25 PM PST 24 |
| Finished | Jan 14 12:26:27 PM PST 24 |
| Peak memory | 214068 kb |
| Host | smart-036f3a78-39e4-4b06-b4bc-34a8e4c89e8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92930907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.92930907 |
| Directory | /workspace/41.edn_genbits/latest |
| Test location | /workspace/coverage/default/41.edn_intr.1788040942 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 20366367 ps |
| CPU time | 1.15 seconds |
| Started | Jan 14 12:26:36 PM PST 24 |
| Finished | Jan 14 12:26:37 PM PST 24 |
| Peak memory | 221404 kb |
| Host | smart-8d33ff2b-c74e-4290-a017-246bb998f31c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1788040942 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1788040942 |
| Directory | /workspace/41.edn_intr/latest |
| Test location | /workspace/coverage/default/41.edn_smoke.154844790 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 170698065 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 12:26:53 PM PST 24 |
| Finished | Jan 14 12:26:54 PM PST 24 |
| Peak memory | 204544 kb |
| Host | smart-a0d297b7-8a3b-431c-a696-a329e3480f12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=154844790 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.154844790 |
| Directory | /workspace/41.edn_smoke/latest |
| Test location | /workspace/coverage/default/41.edn_stress_all.3456440885 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 141926697 ps |
| CPU time | 2.08 seconds |
| Started | Jan 14 12:26:21 PM PST 24 |
| Finished | Jan 14 12:26:25 PM PST 24 |
| Peak memory | 205484 kb |
| Host | smart-ce6c9ab7-4250-447e-80d4-7f289a38866a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456440885 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3456440885 |
| Directory | /workspace/41.edn_stress_all/latest |
| Test location | /workspace/coverage/default/42.edn_alert.1855662543 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 75638435 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:26:34 PM PST 24 |
| Finished | Jan 14 12:26:36 PM PST 24 |
| Peak memory | 206116 kb |
| Host | smart-508af0a4-a22e-45bd-8f54-24b8e0b2e01f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1855662543 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1855662543 |
| Directory | /workspace/42.edn_alert/latest |
| Test location | /workspace/coverage/default/42.edn_alert_test.2905273626 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 14794698 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:26:23 PM PST 24 |
| Finished | Jan 14 12:26:25 PM PST 24 |
| Peak memory | 204400 kb |
| Host | smart-2012c2bb-7212-40b9-8d8f-e19c5e84dd64 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905273626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2905273626 |
| Directory | /workspace/42.edn_alert_test/latest |
| Test location | /workspace/coverage/default/42.edn_disable.4157159885 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 27126599 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:26:53 PM PST 24 |
| Finished | Jan 14 12:26:54 PM PST 24 |
| Peak memory | 214220 kb |
| Host | smart-43904818-e416-477a-ba49-b35516b452f0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157159885 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.4157159885 |
| Directory | /workspace/42.edn_disable/latest |
| Test location | /workspace/coverage/default/42.edn_disable_auto_req_mode.2716438479 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 26767212 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:26:25 PM PST 24 |
| Finished | Jan 14 12:26:27 PM PST 24 |
| Peak memory | 214416 kb |
| Host | smart-a03ec0b8-7ed2-4ac6-a1de-20fe843ae63c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716438479 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d isable_auto_req_mode.2716438479 |
| Directory | /workspace/42.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/42.edn_err.2542989425 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 23069805 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:26:35 PM PST 24 |
| Finished | Jan 14 12:26:36 PM PST 24 |
| Peak memory | 215792 kb |
| Host | smart-0874b733-65b7-4111-b92b-d8c77e8a87bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2542989425 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2542989425 |
| Directory | /workspace/42.edn_err/latest |
| Test location | /workspace/coverage/default/42.edn_genbits.1988892085 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 95413581 ps |
| CPU time | 2.17 seconds |
| Started | Jan 14 12:26:34 PM PST 24 |
| Finished | Jan 14 12:26:37 PM PST 24 |
| Peak memory | 214012 kb |
| Host | smart-d38d2b8f-9a2c-475f-bd2c-b38bcbc68524 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1988892085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1988892085 |
| Directory | /workspace/42.edn_genbits/latest |
| Test location | /workspace/coverage/default/42.edn_intr.671055365 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 19785681 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:26:46 PM PST 24 |
| Finished | Jan 14 12:26:48 PM PST 24 |
| Peak memory | 214332 kb |
| Host | smart-9fdbc9cb-0ff1-4087-afb6-1de7ddf78154 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=671055365 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.671055365 |
| Directory | /workspace/42.edn_intr/latest |
| Test location | /workspace/coverage/default/42.edn_smoke.3322232773 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 23908504 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:26:48 PM PST 24 |
| Finished | Jan 14 12:26:49 PM PST 24 |
| Peak memory | 204920 kb |
| Host | smart-268d0403-f84e-4a43-aadb-21ccffe5e964 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3322232773 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3322232773 |
| Directory | /workspace/42.edn_smoke/latest |
| Test location | /workspace/coverage/default/42.edn_stress_all.1569600354 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 171548647 ps |
| CPU time | 3.67 seconds |
| Started | Jan 14 12:26:31 PM PST 24 |
| Finished | Jan 14 12:26:35 PM PST 24 |
| Peak memory | 205880 kb |
| Host | smart-7e6d1744-797e-4fc6-b05e-16e815fc7c20 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569600354 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1569600354 |
| Directory | /workspace/42.edn_stress_all/latest |
| Test location | /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2028262532 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 259475566348 ps |
| CPU time | 2036.57 seconds |
| Started | Jan 14 12:26:46 PM PST 24 |
| Finished | Jan 14 01:00:43 PM PST 24 |
| Peak memory | 220864 kb |
| Host | smart-df4ecbf5-4d1a-4d60-b0e5-44f528f3af8a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028262532 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2028262532 |
| Directory | /workspace/42.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.edn_alert.2720570752 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 17913975 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:26:50 PM PST 24 |
| Finished | Jan 14 12:26:52 PM PST 24 |
| Peak memory | 204992 kb |
| Host | smart-f20a3aff-e7f2-4c94-ab2b-7b38df691fcf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2720570752 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2720570752 |
| Directory | /workspace/43.edn_alert/latest |
| Test location | /workspace/coverage/default/43.edn_alert_test.2336647922 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 19963440 ps |
| CPU time | 1 seconds |
| Started | Jan 14 12:26:22 PM PST 24 |
| Finished | Jan 14 12:26:24 PM PST 24 |
| Peak memory | 204588 kb |
| Host | smart-f3bcb04c-d259-4505-b20b-82ea0c377031 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336647922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2336647922 |
| Directory | /workspace/43.edn_alert_test/latest |
| Test location | /workspace/coverage/default/43.edn_disable.74301666 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 48921149 ps |
| CPU time | 0.8 seconds |
| Started | Jan 14 12:26:23 PM PST 24 |
| Finished | Jan 14 12:26:24 PM PST 24 |
| Peak memory | 214312 kb |
| Host | smart-85e92f5a-a875-4d03-b384-31d5c372fed2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74301666 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.74301666 |
| Directory | /workspace/43.edn_disable/latest |
| Test location | /workspace/coverage/default/43.edn_disable_auto_req_mode.2499591170 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 40944110 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:26:48 PM PST 24 |
| Finished | Jan 14 12:26:50 PM PST 24 |
| Peak memory | 214296 kb |
| Host | smart-345ca77d-b86f-4fb2-9e61-5918cf3418e4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499591170 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d isable_auto_req_mode.2499591170 |
| Directory | /workspace/43.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/43.edn_err.444925386 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 61707123 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:26:51 PM PST 24 |
| Finished | Jan 14 12:26:53 PM PST 24 |
| Peak memory | 216196 kb |
| Host | smart-b978ea60-148b-4dc8-9598-219083271fa1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=444925386 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.444925386 |
| Directory | /workspace/43.edn_err/latest |
| Test location | /workspace/coverage/default/43.edn_genbits.2954754496 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 35598986 ps |
| CPU time | 1.13 seconds |
| Started | Jan 14 12:26:31 PM PST 24 |
| Finished | Jan 14 12:26:33 PM PST 24 |
| Peak memory | 205312 kb |
| Host | smart-041f7d21-50ec-41ed-a069-a4315dd5732a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2954754496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2954754496 |
| Directory | /workspace/43.edn_genbits/latest |
| Test location | /workspace/coverage/default/43.edn_intr.3434179141 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 26144722 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:26:45 PM PST 24 |
| Finished | Jan 14 12:26:47 PM PST 24 |
| Peak memory | 214280 kb |
| Host | smart-37c0bf78-3469-4a19-8824-26dbc96c2d8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3434179141 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3434179141 |
| Directory | /workspace/43.edn_intr/latest |
| Test location | /workspace/coverage/default/43.edn_smoke.322865455 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 34595137 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:26:49 PM PST 24 |
| Finished | Jan 14 12:26:50 PM PST 24 |
| Peak memory | 204756 kb |
| Host | smart-51cc1f90-95be-4396-8ae6-8b773029de4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=322865455 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.322865455 |
| Directory | /workspace/43.edn_smoke/latest |
| Test location | /workspace/coverage/default/43.edn_stress_all.1749452169 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 394840976 ps |
| CPU time | 2.69 seconds |
| Started | Jan 14 12:26:45 PM PST 24 |
| Finished | Jan 14 12:26:48 PM PST 24 |
| Peak memory | 205588 kb |
| Host | smart-a25936fc-e018-4a61-88be-5e9e3d79389c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749452169 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1749452169 |
| Directory | /workspace/43.edn_stress_all/latest |
| Test location | /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3958583616 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 52445033683 ps |
| CPU time | 785.68 seconds |
| Started | Jan 14 12:26:29 PM PST 24 |
| Finished | Jan 14 12:39:35 PM PST 24 |
| Peak memory | 215500 kb |
| Host | smart-8704fc90-76f3-4e39-a0e1-16e931568f82 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958583616 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3958583616 |
| Directory | /workspace/43.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.edn_alert.249947173 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 106148957 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:26:31 PM PST 24 |
| Finished | Jan 14 12:26:32 PM PST 24 |
| Peak memory | 205824 kb |
| Host | smart-99d1520b-b6be-49a3-b82e-bf2cb5fc3bea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=249947173 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.249947173 |
| Directory | /workspace/44.edn_alert/latest |
| Test location | /workspace/coverage/default/44.edn_alert_test.2560353528 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 53590815 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:26:32 PM PST 24 |
| Finished | Jan 14 12:26:33 PM PST 24 |
| Peak memory | 204396 kb |
| Host | smart-ea41693e-b99a-41a9-9ca5-b49f555dad4b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560353528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2560353528 |
| Directory | /workspace/44.edn_alert_test/latest |
| Test location | /workspace/coverage/default/44.edn_disable.3004381905 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 12356710 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:26:48 PM PST 24 |
| Finished | Jan 14 12:26:50 PM PST 24 |
| Peak memory | 214276 kb |
| Host | smart-a29521fd-c1cb-401d-9f65-561408fa463f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004381905 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.3004381905 |
| Directory | /workspace/44.edn_disable/latest |
| Test location | /workspace/coverage/default/44.edn_disable_auto_req_mode.2336161591 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 17904902 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:26:45 PM PST 24 |
| Finished | Jan 14 12:26:56 PM PST 24 |
| Peak memory | 214436 kb |
| Host | smart-0d3e1551-cefd-468a-a6af-cfe56be59319 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336161591 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d isable_auto_req_mode.2336161591 |
| Directory | /workspace/44.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/44.edn_err.2896133433 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 30543595 ps |
| CPU time | 1.17 seconds |
| Started | Jan 14 12:26:55 PM PST 24 |
| Finished | Jan 14 12:26:57 PM PST 24 |
| Peak memory | 216844 kb |
| Host | smart-e54c6956-2cf3-4c8a-be47-ba788a874b36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896133433 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2896133433 |
| Directory | /workspace/44.edn_err/latest |
| Test location | /workspace/coverage/default/44.edn_genbits.1720814922 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 80992395 ps |
| CPU time | 1.04 seconds |
| Started | Jan 14 12:26:46 PM PST 24 |
| Finished | Jan 14 12:26:48 PM PST 24 |
| Peak memory | 205324 kb |
| Host | smart-5d68435a-9dc3-4e60-8975-9382fd27f3a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1720814922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1720814922 |
| Directory | /workspace/44.edn_genbits/latest |
| Test location | /workspace/coverage/default/44.edn_intr.3917251804 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 17583892 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:26:18 PM PST 24 |
| Finished | Jan 14 12:26:20 PM PST 24 |
| Peak memory | 214416 kb |
| Host | smart-22bb7c3a-4bed-4779-81f4-d9609a592de6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3917251804 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3917251804 |
| Directory | /workspace/44.edn_intr/latest |
| Test location | /workspace/coverage/default/44.edn_smoke.1090678612 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 13880331 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:26:32 PM PST 24 |
| Finished | Jan 14 12:26:34 PM PST 24 |
| Peak memory | 204784 kb |
| Host | smart-b2a1137f-f25f-4c57-a552-80e9a4740ac2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1090678612 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1090678612 |
| Directory | /workspace/44.edn_smoke/latest |
| Test location | /workspace/coverage/default/44.edn_stress_all.636259839 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 69092642 ps |
| CPU time | 1.85 seconds |
| Started | Jan 14 12:26:27 PM PST 24 |
| Finished | Jan 14 12:26:29 PM PST 24 |
| Peak memory | 205612 kb |
| Host | smart-ee498e53-6d12-4eab-8ced-fb5daf7ef4cc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636259839 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.636259839 |
| Directory | /workspace/44.edn_stress_all/latest |
| Test location | /workspace/coverage/default/44.edn_stress_all_with_rand_reset.4227344945 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 181519673592 ps |
| CPU time | 1042.37 seconds |
| Started | Jan 14 12:26:38 PM PST 24 |
| Finished | Jan 14 12:44:01 PM PST 24 |
| Peak memory | 216184 kb |
| Host | smart-352bc2a5-68fc-40e2-9b30-fb3e6de4d485 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227344945 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.4227344945 |
| Directory | /workspace/44.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.edn_alert.1698878629 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 37009501 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:26:47 PM PST 24 |
| Finished | Jan 14 12:26:49 PM PST 24 |
| Peak memory | 205224 kb |
| Host | smart-82cf2ea2-f7b5-49f3-b949-a96e07356d68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1698878629 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1698878629 |
| Directory | /workspace/45.edn_alert/latest |
| Test location | /workspace/coverage/default/45.edn_alert_test.1835641698 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 46260952 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:26:34 PM PST 24 |
| Finished | Jan 14 12:26:35 PM PST 24 |
| Peak memory | 204492 kb |
| Host | smart-1048dc65-56d1-469c-9c12-f31962495e46 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835641698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.1835641698 |
| Directory | /workspace/45.edn_alert_test/latest |
| Test location | /workspace/coverage/default/45.edn_disable.4285708782 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 11841325 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:26:52 PM PST 24 |
| Finished | Jan 14 12:26:53 PM PST 24 |
| Peak memory | 214320 kb |
| Host | smart-10b386de-51f3-4190-b5d1-27ed33e22aa3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285708782 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.4285708782 |
| Directory | /workspace/45.edn_disable/latest |
| Test location | /workspace/coverage/default/45.edn_disable_auto_req_mode.2679198388 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 69126806 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:26:37 PM PST 24 |
| Finished | Jan 14 12:26:39 PM PST 24 |
| Peak memory | 214384 kb |
| Host | smart-54bdfa75-00bc-4ac7-b8d9-dca401fb8ccf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679198388 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d isable_auto_req_mode.2679198388 |
| Directory | /workspace/45.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/45.edn_err.2881271325 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 36893759 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:26:50 PM PST 24 |
| Finished | Jan 14 12:26:52 PM PST 24 |
| Peak memory | 215508 kb |
| Host | smart-a8e2bf35-3bcd-4563-bcab-542042c6bc42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2881271325 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2881271325 |
| Directory | /workspace/45.edn_err/latest |
| Test location | /workspace/coverage/default/45.edn_genbits.55169523 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 17095654 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:26:45 PM PST 24 |
| Finished | Jan 14 12:26:47 PM PST 24 |
| Peak memory | 205412 kb |
| Host | smart-bcfbdad0-434c-4e11-8299-9918e09462aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=55169523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.55169523 |
| Directory | /workspace/45.edn_genbits/latest |
| Test location | /workspace/coverage/default/45.edn_intr.3354129758 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 21171330 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:26:59 PM PST 24 |
| Finished | Jan 14 12:27:01 PM PST 24 |
| Peak memory | 214360 kb |
| Host | smart-3014e7ea-eb85-4af7-82d6-d80bcf901ced |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3354129758 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3354129758 |
| Directory | /workspace/45.edn_intr/latest |
| Test location | /workspace/coverage/default/45.edn_smoke.2653121989 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 29171028 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:26:47 PM PST 24 |
| Finished | Jan 14 12:26:48 PM PST 24 |
| Peak memory | 204524 kb |
| Host | smart-386bc4b2-aea6-4cc9-9e9b-20a83cb191b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2653121989 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2653121989 |
| Directory | /workspace/45.edn_smoke/latest |
| Test location | /workspace/coverage/default/45.edn_stress_all.3853522427 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 65679940 ps |
| CPU time | 1.84 seconds |
| Started | Jan 14 12:26:39 PM PST 24 |
| Finished | Jan 14 12:26:41 PM PST 24 |
| Peak memory | 205676 kb |
| Host | smart-4f31a5d1-7508-4478-994a-b68655b53a2d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853522427 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3853522427 |
| Directory | /workspace/45.edn_stress_all/latest |
| Test location | /workspace/coverage/default/45.edn_stress_all_with_rand_reset.4092115589 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 39615587070 ps |
| CPU time | 456.15 seconds |
| Started | Jan 14 12:26:42 PM PST 24 |
| Finished | Jan 14 12:34:19 PM PST 24 |
| Peak memory | 215260 kb |
| Host | smart-8618ad9f-83b6-4776-bccb-c170d6b1c7ac |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092115589 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.4092115589 |
| Directory | /workspace/45.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.edn_alert.507292382 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 32143550 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:26:31 PM PST 24 |
| Finished | Jan 14 12:26:32 PM PST 24 |
| Peak memory | 205860 kb |
| Host | smart-d1578172-c05c-4f8b-93bd-378d68f6c7a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=507292382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.507292382 |
| Directory | /workspace/46.edn_alert/latest |
| Test location | /workspace/coverage/default/46.edn_alert_test.2196688796 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 16191529 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:26:53 PM PST 24 |
| Finished | Jan 14 12:26:55 PM PST 24 |
| Peak memory | 204952 kb |
| Host | smart-139de011-8193-4642-90da-ecfb9760087c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196688796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2196688796 |
| Directory | /workspace/46.edn_alert_test/latest |
| Test location | /workspace/coverage/default/46.edn_disable.844483773 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 14005000 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:26:55 PM PST 24 |
| Finished | Jan 14 12:26:57 PM PST 24 |
| Peak memory | 214388 kb |
| Host | smart-c0530fc0-f378-47cb-821e-bd91353e775b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844483773 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.844483773 |
| Directory | /workspace/46.edn_disable/latest |
| Test location | /workspace/coverage/default/46.edn_disable_auto_req_mode.2849659549 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 76618491 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:26:54 PM PST 24 |
| Finished | Jan 14 12:26:55 PM PST 24 |
| Peak memory | 214460 kb |
| Host | smart-42d54ad5-3419-45dc-a277-edf85145e908 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849659549 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d isable_auto_req_mode.2849659549 |
| Directory | /workspace/46.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/46.edn_err.609649086 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 24409502 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:54 PM PST 24 |
| Finished | Jan 14 12:26:56 PM PST 24 |
| Peak memory | 215980 kb |
| Host | smart-95e1a775-06ab-4149-af8b-fd71a7817268 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=609649086 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.609649086 |
| Directory | /workspace/46.edn_err/latest |
| Test location | /workspace/coverage/default/46.edn_genbits.3305268741 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 32743313 ps |
| CPU time | 1.44 seconds |
| Started | Jan 14 12:26:45 PM PST 24 |
| Finished | Jan 14 12:26:47 PM PST 24 |
| Peak memory | 214148 kb |
| Host | smart-10378edc-a6a3-42ab-a494-6189818a685a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3305268741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3305268741 |
| Directory | /workspace/46.edn_genbits/latest |
| Test location | /workspace/coverage/default/46.edn_intr.802232061 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 20310807 ps |
| CPU time | 1.11 seconds |
| Started | Jan 14 12:26:48 PM PST 24 |
| Finished | Jan 14 12:26:50 PM PST 24 |
| Peak memory | 221932 kb |
| Host | smart-e357ef2c-e580-459f-935a-7ecd1882e766 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=802232061 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.802232061 |
| Directory | /workspace/46.edn_intr/latest |
| Test location | /workspace/coverage/default/46.edn_smoke.2589675016 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 18682252 ps |
| CPU time | 0.79 seconds |
| Started | Jan 14 12:26:54 PM PST 24 |
| Finished | Jan 14 12:26:56 PM PST 24 |
| Peak memory | 204596 kb |
| Host | smart-e9fd1d29-38f1-4afb-a51a-e2aeedc5d7e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2589675016 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2589675016 |
| Directory | /workspace/46.edn_smoke/latest |
| Test location | /workspace/coverage/default/46.edn_stress_all.2715471475 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 523879203 ps |
| CPU time | 2.95 seconds |
| Started | Jan 14 12:26:43 PM PST 24 |
| Finished | Jan 14 12:26:47 PM PST 24 |
| Peak memory | 205588 kb |
| Host | smart-6c7141a5-c547-409a-a9db-feaf568831ab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715471475 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2715471475 |
| Directory | /workspace/46.edn_stress_all/latest |
| Test location | /workspace/coverage/default/46.edn_stress_all_with_rand_reset.691929237 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 166327388696 ps |
| CPU time | 1829.62 seconds |
| Started | Jan 14 12:26:46 PM PST 24 |
| Finished | Jan 14 12:57:17 PM PST 24 |
| Peak memory | 219016 kb |
| Host | smart-31886229-aad6-4111-9f1a-81483ed0296b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691929237 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.691929237 |
| Directory | /workspace/46.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.edn_alert.2709924794 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 129643088 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:26:50 PM PST 24 |
| Finished | Jan 14 12:26:52 PM PST 24 |
| Peak memory | 205820 kb |
| Host | smart-926aa7c1-83ae-4db8-82f9-b296ae21ebb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2709924794 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2709924794 |
| Directory | /workspace/47.edn_alert/latest |
| Test location | /workspace/coverage/default/47.edn_alert_test.2944483532 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 25871977 ps |
| CPU time | 0.78 seconds |
| Started | Jan 14 12:26:37 PM PST 24 |
| Finished | Jan 14 12:26:39 PM PST 24 |
| Peak memory | 204220 kb |
| Host | smart-9fa567b5-46e2-4719-8df5-97872814e2af |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944483532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2944483532 |
| Directory | /workspace/47.edn_alert_test/latest |
| Test location | /workspace/coverage/default/47.edn_disable.4160411300 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 21948838 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:26:22 PM PST 24 |
| Finished | Jan 14 12:26:23 PM PST 24 |
| Peak memory | 214284 kb |
| Host | smart-1d5ba0ee-b9bc-44b6-bdb6-d683cc30fa46 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160411300 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.4160411300 |
| Directory | /workspace/47.edn_disable/latest |
| Test location | /workspace/coverage/default/47.edn_disable_auto_req_mode.1339911741 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 15417069 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:26:48 PM PST 24 |
| Finished | Jan 14 12:26:50 PM PST 24 |
| Peak memory | 214412 kb |
| Host | smart-e75ed785-2bcd-46ee-a316-6928280114ef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339911741 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d isable_auto_req_mode.1339911741 |
| Directory | /workspace/47.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/47.edn_err.2100974574 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 42834747 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:27:01 PM PST 24 |
| Finished | Jan 14 12:27:02 PM PST 24 |
| Peak memory | 221828 kb |
| Host | smart-467326f7-f432-431e-b1ee-2fa39c372820 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2100974574 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2100974574 |
| Directory | /workspace/47.edn_err/latest |
| Test location | /workspace/coverage/default/47.edn_genbits.792126325 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 29648367 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:26:35 PM PST 24 |
| Finished | Jan 14 12:26:36 PM PST 24 |
| Peak memory | 205272 kb |
| Host | smart-338c7e61-18cb-4685-9045-cd83468bb536 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=792126325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.792126325 |
| Directory | /workspace/47.edn_genbits/latest |
| Test location | /workspace/coverage/default/47.edn_intr.2562547577 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 21532854 ps |
| CPU time | 1.11 seconds |
| Started | Jan 14 12:26:46 PM PST 24 |
| Finished | Jan 14 12:26:47 PM PST 24 |
| Peak memory | 221388 kb |
| Host | smart-8b4d15ed-b71d-4485-a9cb-9d8c026e4ff3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2562547577 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2562547577 |
| Directory | /workspace/47.edn_intr/latest |
| Test location | /workspace/coverage/default/47.edn_smoke.2618277769 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 16171016 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:30 PM PST 24 |
| Finished | Jan 14 12:26:31 PM PST 24 |
| Peak memory | 204832 kb |
| Host | smart-3f591b82-e88e-43ec-9bea-f457a1adab7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2618277769 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2618277769 |
| Directory | /workspace/47.edn_smoke/latest |
| Test location | /workspace/coverage/default/47.edn_stress_all.1992083018 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 305132047 ps |
| CPU time | 2.18 seconds |
| Started | Jan 14 12:26:56 PM PST 24 |
| Finished | Jan 14 12:27:00 PM PST 24 |
| Peak memory | 205648 kb |
| Host | smart-82c1c5c6-2779-45d1-96cb-66c7418de0f9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992083018 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1992083018 |
| Directory | /workspace/47.edn_stress_all/latest |
| Test location | /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3615294114 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 106801475176 ps |
| CPU time | 796.37 seconds |
| Started | Jan 14 12:26:54 PM PST 24 |
| Finished | Jan 14 12:40:11 PM PST 24 |
| Peak memory | 215608 kb |
| Host | smart-505ef39e-efdc-424c-81a2-6858ba9552ea |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615294114 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3615294114 |
| Directory | /workspace/47.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.edn_alert.1556760483 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 61361693 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:26:46 PM PST 24 |
| Finished | Jan 14 12:26:48 PM PST 24 |
| Peak memory | 205816 kb |
| Host | smart-380e7c76-ed74-4f38-9f48-b8847f7a113d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1556760483 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1556760483 |
| Directory | /workspace/48.edn_alert/latest |
| Test location | /workspace/coverage/default/48.edn_alert_test.2792862586 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 34657763 ps |
| CPU time | 0.79 seconds |
| Started | Jan 14 12:27:01 PM PST 24 |
| Finished | Jan 14 12:27:07 PM PST 24 |
| Peak memory | 204216 kb |
| Host | smart-23c0f068-91da-4958-9e0d-84fe7205b90a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792862586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2792862586 |
| Directory | /workspace/48.edn_alert_test/latest |
| Test location | /workspace/coverage/default/48.edn_disable.3747665448 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 30997111 ps |
| CPU time | 0.79 seconds |
| Started | Jan 14 12:26:46 PM PST 24 |
| Finished | Jan 14 12:26:48 PM PST 24 |
| Peak memory | 214140 kb |
| Host | smart-e3b46501-38d8-49e1-9572-c9597f23745f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747665448 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3747665448 |
| Directory | /workspace/48.edn_disable/latest |
| Test location | /workspace/coverage/default/48.edn_disable_auto_req_mode.3793774892 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 18228422 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:26:29 PM PST 24 |
| Finished | Jan 14 12:26:31 PM PST 24 |
| Peak memory | 214380 kb |
| Host | smart-3242de4e-4075-4091-8810-a448ff4f434e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793774892 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d isable_auto_req_mode.3793774892 |
| Directory | /workspace/48.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/48.edn_err.2229565733 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 20757910 ps |
| CPU time | 0.87 seconds |
| Started | Jan 14 12:26:28 PM PST 24 |
| Finished | Jan 14 12:26:30 PM PST 24 |
| Peak memory | 215564 kb |
| Host | smart-c3bc741d-3f78-43d1-8e04-24690081fb92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2229565733 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2229565733 |
| Directory | /workspace/48.edn_err/latest |
| Test location | /workspace/coverage/default/48.edn_genbits.692652278 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 27254623 ps |
| CPU time | 1.23 seconds |
| Started | Jan 14 12:26:52 PM PST 24 |
| Finished | Jan 14 12:26:54 PM PST 24 |
| Peak memory | 205404 kb |
| Host | smart-7b38afcc-c56d-4141-98d8-ce4f63b72ec9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=692652278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.692652278 |
| Directory | /workspace/48.edn_genbits/latest |
| Test location | /workspace/coverage/default/48.edn_intr.3407942976 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 38369634 ps |
| CPU time | 0.78 seconds |
| Started | Jan 14 12:26:43 PM PST 24 |
| Finished | Jan 14 12:26:44 PM PST 24 |
| Peak memory | 214212 kb |
| Host | smart-b07eeab6-2c9d-4e72-95b1-9a82996adf24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3407942976 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3407942976 |
| Directory | /workspace/48.edn_intr/latest |
| Test location | /workspace/coverage/default/48.edn_smoke.3168704629 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 39459513 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:26:53 PM PST 24 |
| Finished | Jan 14 12:26:55 PM PST 24 |
| Peak memory | 204660 kb |
| Host | smart-e2dc89b4-67ab-4fd9-91b1-c64e2e7d60ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3168704629 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3168704629 |
| Directory | /workspace/48.edn_smoke/latest |
| Test location | /workspace/coverage/default/48.edn_stress_all.1484708697 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 378634004 ps |
| CPU time | 2.04 seconds |
| Started | Jan 14 12:26:50 PM PST 24 |
| Finished | Jan 14 12:26:53 PM PST 24 |
| Peak memory | 205624 kb |
| Host | smart-d4c9f461-bb41-4c3c-9f7b-d871e7469314 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484708697 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1484708697 |
| Directory | /workspace/48.edn_stress_all/latest |
| Test location | /workspace/coverage/default/48.edn_stress_all_with_rand_reset.172166286 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 236169060576 ps |
| CPU time | 609.98 seconds |
| Started | Jan 14 12:27:03 PM PST 24 |
| Finished | Jan 14 12:37:14 PM PST 24 |
| Peak memory | 218728 kb |
| Host | smart-7b743804-6748-4789-855a-39ad16e0447c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172166286 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.172166286 |
| Directory | /workspace/48.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.edn_alert.3590104820 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 19882759 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:26:45 PM PST 24 |
| Finished | Jan 14 12:26:47 PM PST 24 |
| Peak memory | 205868 kb |
| Host | smart-7b61c5b3-6b8b-43fb-a649-5f7780bdcb15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3590104820 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3590104820 |
| Directory | /workspace/49.edn_alert/latest |
| Test location | /workspace/coverage/default/49.edn_alert_test.3329591130 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 40317868 ps |
| CPU time | 0.8 seconds |
| Started | Jan 14 12:26:34 PM PST 24 |
| Finished | Jan 14 12:26:35 PM PST 24 |
| Peak memory | 204940 kb |
| Host | smart-beff5b99-a6b8-4153-9809-917c3c732674 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329591130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3329591130 |
| Directory | /workspace/49.edn_alert_test/latest |
| Test location | /workspace/coverage/default/49.edn_disable.2000195704 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 15316177 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:26:33 PM PST 24 |
| Finished | Jan 14 12:26:34 PM PST 24 |
| Peak memory | 214188 kb |
| Host | smart-479ef2ae-4749-498c-ba64-ebc7d103d3eb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000195704 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2000195704 |
| Directory | /workspace/49.edn_disable/latest |
| Test location | /workspace/coverage/default/49.edn_disable_auto_req_mode.656856283 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 79782920 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:26:28 PM PST 24 |
| Finished | Jan 14 12:26:29 PM PST 24 |
| Peak memory | 214392 kb |
| Host | smart-f532c8e9-bb9a-4c23-9dbc-7ff9bac83c63 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656856283 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di sable_auto_req_mode.656856283 |
| Directory | /workspace/49.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/49.edn_err.4249028259 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 19654226 ps |
| CPU time | 1.1 seconds |
| Started | Jan 14 12:26:38 PM PST 24 |
| Finished | Jan 14 12:26:39 PM PST 24 |
| Peak memory | 221844 kb |
| Host | smart-728f9b8f-c296-478d-b63c-197e4937bb8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4249028259 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.4249028259 |
| Directory | /workspace/49.edn_err/latest |
| Test location | /workspace/coverage/default/49.edn_genbits.2169675487 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 119536632 ps |
| CPU time | 1.78 seconds |
| Started | Jan 14 12:26:35 PM PST 24 |
| Finished | Jan 14 12:26:37 PM PST 24 |
| Peak memory | 214056 kb |
| Host | smart-f66c3314-641a-4c85-af23-aa3b7d8d9cc0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2169675487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2169675487 |
| Directory | /workspace/49.edn_genbits/latest |
| Test location | /workspace/coverage/default/49.edn_intr.3454873510 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 25121894 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:26:46 PM PST 24 |
| Finished | Jan 14 12:26:47 PM PST 24 |
| Peak memory | 214176 kb |
| Host | smart-a289c5a6-48fc-4218-9c82-764a06cbe7d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3454873510 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3454873510 |
| Directory | /workspace/49.edn_intr/latest |
| Test location | /workspace/coverage/default/49.edn_smoke.2862597017 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 37273412 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:26:34 PM PST 24 |
| Finished | Jan 14 12:26:36 PM PST 24 |
| Peak memory | 204416 kb |
| Host | smart-5d0814ae-03cd-4376-851d-d8c91cb4ffc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2862597017 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2862597017 |
| Directory | /workspace/49.edn_smoke/latest |
| Test location | /workspace/coverage/default/49.edn_stress_all.2359630120 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 66267502 ps |
| CPU time | 1.82 seconds |
| Started | Jan 14 12:26:54 PM PST 24 |
| Finished | Jan 14 12:26:56 PM PST 24 |
| Peak memory | 205836 kb |
| Host | smart-5ce8da0f-77c5-44d3-8764-e6bab140a948 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359630120 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2359630120 |
| Directory | /workspace/49.edn_stress_all/latest |
| Test location | /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1431027555 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 34120148290 ps |
| CPU time | 865.52 seconds |
| Started | Jan 14 12:26:21 PM PST 24 |
| Finished | Jan 14 12:40:48 PM PST 24 |
| Peak memory | 214956 kb |
| Host | smart-677cae0a-48fa-4174-927a-03c86e1e3d94 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431027555 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1431027555 |
| Directory | /workspace/49.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.edn_alert.1569612820 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 21979315 ps |
| CPU time | 1 seconds |
| Started | Jan 14 12:25:26 PM PST 24 |
| Finished | Jan 14 12:25:31 PM PST 24 |
| Peak memory | 205596 kb |
| Host | smart-d055e91a-ab35-49b8-ac25-4c1c7f28aa4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1569612820 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1569612820 |
| Directory | /workspace/5.edn_alert/latest |
| Test location | /workspace/coverage/default/5.edn_alert_test.2764432993 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 32907018 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:25:32 PM PST 24 |
| Finished | Jan 14 12:25:38 PM PST 24 |
| Peak memory | 204380 kb |
| Host | smart-97588e82-9852-4d81-961d-5b8b531ea0e2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764432993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2764432993 |
| Directory | /workspace/5.edn_alert_test/latest |
| Test location | /workspace/coverage/default/5.edn_disable.92257182 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 13364438 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:25:17 PM PST 24 |
| Finished | Jan 14 12:25:19 PM PST 24 |
| Peak memory | 214144 kb |
| Host | smart-776ce925-6cf3-466f-b10f-66ed9bf92c02 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92257182 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.92257182 |
| Directory | /workspace/5.edn_disable/latest |
| Test location | /workspace/coverage/default/5.edn_disable_auto_req_mode.3847927425 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 39052797 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:25:59 PM PST 24 |
| Finished | Jan 14 12:26:01 PM PST 24 |
| Peak memory | 214292 kb |
| Host | smart-337c1295-6ba8-41a9-aaf0-d214bcf8203f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847927425 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di sable_auto_req_mode.3847927425 |
| Directory | /workspace/5.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/5.edn_err.1887054742 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 23948491 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:25:27 PM PST 24 |
| Finished | Jan 14 12:25:31 PM PST 24 |
| Peak memory | 221332 kb |
| Host | smart-cd23adba-e652-4c9b-83e3-f901608b3a90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1887054742 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1887054742 |
| Directory | /workspace/5.edn_err/latest |
| Test location | /workspace/coverage/default/5.edn_genbits.1420419439 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 366451665 ps |
| CPU time | 3.44 seconds |
| Started | Jan 14 12:25:36 PM PST 24 |
| Finished | Jan 14 12:25:42 PM PST 24 |
| Peak memory | 214060 kb |
| Host | smart-3f347f91-77e8-4ef2-bc26-600d4c719fff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1420419439 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1420419439 |
| Directory | /workspace/5.edn_genbits/latest |
| Test location | /workspace/coverage/default/5.edn_intr.654976371 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 23589447 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:25:39 PM PST 24 |
| Finished | Jan 14 12:25:45 PM PST 24 |
| Peak memory | 214428 kb |
| Host | smart-ff42f12a-0ac5-4970-9221-fc1f8c492a02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=654976371 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.654976371 |
| Directory | /workspace/5.edn_intr/latest |
| Test location | /workspace/coverage/default/5.edn_regwen.2668658052 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 29714266 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:25:29 PM PST 24 |
| Finished | Jan 14 12:25:35 PM PST 24 |
| Peak memory | 204556 kb |
| Host | smart-d610399b-114c-43be-b26f-d847ea5ae22f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2668658052 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.2668658052 |
| Directory | /workspace/5.edn_regwen/latest |
| Test location | /workspace/coverage/default/5.edn_smoke.1030523382 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 15479702 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:25:17 PM PST 24 |
| Finished | Jan 14 12:25:19 PM PST 24 |
| Peak memory | 204756 kb |
| Host | smart-77cd17ff-fa8a-42bd-8530-e664ea370fe7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1030523382 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1030523382 |
| Directory | /workspace/5.edn_smoke/latest |
| Test location | /workspace/coverage/default/5.edn_stress_all.1697958197 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 142703656 ps |
| CPU time | 1.98 seconds |
| Started | Jan 14 12:25:13 PM PST 24 |
| Finished | Jan 14 12:25:16 PM PST 24 |
| Peak memory | 205948 kb |
| Host | smart-44bab77e-0bfe-4e9f-9929-fd428568457b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697958197 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1697958197 |
| Directory | /workspace/5.edn_stress_all/latest |
| Test location | /workspace/coverage/default/5.edn_stress_all_with_rand_reset.481296264 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 23061228583 ps |
| CPU time | 444.75 seconds |
| Started | Jan 14 12:25:33 PM PST 24 |
| Finished | Jan 14 12:33:02 PM PST 24 |
| Peak memory | 214532 kb |
| Host | smart-009eb992-cdf1-48db-8d83-a9b75f28b5dd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481296264 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.481296264 |
| Directory | /workspace/5.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/50.edn_err.974652475 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 19212581 ps |
| CPU time | 1.13 seconds |
| Started | Jan 14 12:26:37 PM PST 24 |
| Finished | Jan 14 12:26:39 PM PST 24 |
| Peak memory | 221784 kb |
| Host | smart-2452357d-159f-4c21-90d9-eb4facf28be5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=974652475 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.974652475 |
| Directory | /workspace/50.edn_err/latest |
| Test location | /workspace/coverage/default/50.edn_genbits.831002102 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 70681832 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:26:33 PM PST 24 |
| Finished | Jan 14 12:26:35 PM PST 24 |
| Peak memory | 205240 kb |
| Host | smart-9c4289c3-5c26-4668-884e-554b08fa9ddb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=831002102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.831002102 |
| Directory | /workspace/50.edn_genbits/latest |
| Test location | /workspace/coverage/default/51.edn_err.1349886265 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 27565123 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:26:53 PM PST 24 |
| Finished | Jan 14 12:26:55 PM PST 24 |
| Peak memory | 215480 kb |
| Host | smart-3d3d4dc4-6454-4964-be92-dec8fd06c83c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1349886265 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1349886265 |
| Directory | /workspace/51.edn_err/latest |
| Test location | /workspace/coverage/default/51.edn_genbits.1383668071 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 12167055 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:26:50 PM PST 24 |
| Finished | Jan 14 12:26:51 PM PST 24 |
| Peak memory | 205100 kb |
| Host | smart-2e774723-0be3-4711-8790-f9f8c207a6a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1383668071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1383668071 |
| Directory | /workspace/51.edn_genbits/latest |
| Test location | /workspace/coverage/default/52.edn_err.2835473133 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 62280789 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:26:48 PM PST 24 |
| Finished | Jan 14 12:26:50 PM PST 24 |
| Peak memory | 217224 kb |
| Host | smart-a45acc8d-e334-46e0-8bdb-5d13727c3a6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2835473133 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2835473133 |
| Directory | /workspace/52.edn_err/latest |
| Test location | /workspace/coverage/default/52.edn_genbits.2236976178 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 19430881 ps |
| CPU time | 1.06 seconds |
| Started | Jan 14 12:26:45 PM PST 24 |
| Finished | Jan 14 12:26:47 PM PST 24 |
| Peak memory | 205300 kb |
| Host | smart-ab2b9462-f759-424b-b30e-c8856ab5d703 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2236976178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2236976178 |
| Directory | /workspace/52.edn_genbits/latest |
| Test location | /workspace/coverage/default/53.edn_err.3453680593 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 18678076 ps |
| CPU time | 1.11 seconds |
| Started | Jan 14 12:26:45 PM PST 24 |
| Finished | Jan 14 12:26:47 PM PST 24 |
| Peak memory | 221220 kb |
| Host | smart-a0d41fe5-25bc-4d15-ae42-502fcd810ba1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3453680593 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3453680593 |
| Directory | /workspace/53.edn_err/latest |
| Test location | /workspace/coverage/default/53.edn_genbits.1032889905 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 193060981 ps |
| CPU time | 2.83 seconds |
| Started | Jan 14 12:26:38 PM PST 24 |
| Finished | Jan 14 12:26:41 PM PST 24 |
| Peak memory | 214112 kb |
| Host | smart-1a857cd3-4f27-4f6c-ae3c-ae4146bb38bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1032889905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1032889905 |
| Directory | /workspace/53.edn_genbits/latest |
| Test location | /workspace/coverage/default/54.edn_err.3374018590 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 32404211 ps |
| CPU time | 1.32 seconds |
| Started | Jan 14 12:26:42 PM PST 24 |
| Finished | Jan 14 12:26:44 PM PST 24 |
| Peak memory | 221820 kb |
| Host | smart-64be29f2-090a-4dd3-bfb6-c45e2447bf38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3374018590 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3374018590 |
| Directory | /workspace/54.edn_err/latest |
| Test location | /workspace/coverage/default/54.edn_genbits.4067164442 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 41091529 ps |
| CPU time | 1.81 seconds |
| Started | Jan 14 12:26:47 PM PST 24 |
| Finished | Jan 14 12:26:49 PM PST 24 |
| Peak memory | 214120 kb |
| Host | smart-644cfb9a-1cb8-43d0-8a7c-6143964299a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4067164442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.4067164442 |
| Directory | /workspace/54.edn_genbits/latest |
| Test location | /workspace/coverage/default/55.edn_err.480554867 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 23530444 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:26:55 PM PST 24 |
| Finished | Jan 14 12:26:57 PM PST 24 |
| Peak memory | 215656 kb |
| Host | smart-4d280da6-6c82-4766-b5f9-c4416623b180 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=480554867 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.480554867 |
| Directory | /workspace/55.edn_err/latest |
| Test location | /workspace/coverage/default/55.edn_genbits.1830910556 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 18471094 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:26:52 PM PST 24 |
| Finished | Jan 14 12:26:54 PM PST 24 |
| Peak memory | 204744 kb |
| Host | smart-f77d5161-326d-4e5b-9850-bf6bfa5024e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1830910556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1830910556 |
| Directory | /workspace/55.edn_genbits/latest |
| Test location | /workspace/coverage/default/56.edn_err.4054473407 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 18176029 ps |
| CPU time | 1.06 seconds |
| Started | Jan 14 12:26:56 PM PST 24 |
| Finished | Jan 14 12:26:59 PM PST 24 |
| Peak memory | 221316 kb |
| Host | smart-81aeb669-7a3b-4fbf-9030-8ec8b26543cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4054473407 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.4054473407 |
| Directory | /workspace/56.edn_err/latest |
| Test location | /workspace/coverage/default/56.edn_genbits.1856550419 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 168766821 ps |
| CPU time | 2.58 seconds |
| Started | Jan 14 12:26:54 PM PST 24 |
| Finished | Jan 14 12:26:57 PM PST 24 |
| Peak memory | 214028 kb |
| Host | smart-5cdc751c-9e35-49b4-b3a4-028a74a875f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1856550419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1856550419 |
| Directory | /workspace/56.edn_genbits/latest |
| Test location | /workspace/coverage/default/57.edn_err.3168676885 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 61334056 ps |
| CPU time | 1.08 seconds |
| Started | Jan 14 12:26:53 PM PST 24 |
| Finished | Jan 14 12:26:54 PM PST 24 |
| Peak memory | 230048 kb |
| Host | smart-4dc2bed6-c9e2-4ba3-9876-049f6a1e1510 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3168676885 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3168676885 |
| Directory | /workspace/57.edn_err/latest |
| Test location | /workspace/coverage/default/57.edn_genbits.3424111588 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 17413253 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:26:53 PM PST 24 |
| Finished | Jan 14 12:26:54 PM PST 24 |
| Peak memory | 204984 kb |
| Host | smart-7f94dc42-8368-46d9-abad-7a6729a47c0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3424111588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3424111588 |
| Directory | /workspace/57.edn_genbits/latest |
| Test location | /workspace/coverage/default/58.edn_err.2596086914 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 115110093 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:26:57 PM PST 24 |
| Finished | Jan 14 12:26:59 PM PST 24 |
| Peak memory | 216196 kb |
| Host | smart-6fb4ff4c-6265-4d9a-811a-2de7ca8e9a19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2596086914 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2596086914 |
| Directory | /workspace/58.edn_err/latest |
| Test location | /workspace/coverage/default/58.edn_genbits.1994294330 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 47075645 ps |
| CPU time | 1.17 seconds |
| Started | Jan 14 12:26:43 PM PST 24 |
| Finished | Jan 14 12:26:45 PM PST 24 |
| Peak memory | 213964 kb |
| Host | smart-6d14b80a-10f3-4443-8cf2-39f4f814ef4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1994294330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1994294330 |
| Directory | /workspace/58.edn_genbits/latest |
| Test location | /workspace/coverage/default/59.edn_err.167675843 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 172487136 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:26:54 PM PST 24 |
| Finished | Jan 14 12:26:56 PM PST 24 |
| Peak memory | 216248 kb |
| Host | smart-1f99a72c-9dba-487b-a844-183d3d2f713f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=167675843 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.167675843 |
| Directory | /workspace/59.edn_err/latest |
| Test location | /workspace/coverage/default/59.edn_genbits.2152802777 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 33414384 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:26:58 PM PST 24 |
| Finished | Jan 14 12:27:00 PM PST 24 |
| Peak memory | 204980 kb |
| Host | smart-328bacb2-33f5-4e4b-be5d-5a7a7ef61a39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2152802777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2152802777 |
| Directory | /workspace/59.edn_genbits/latest |
| Test location | /workspace/coverage/default/6.edn_alert_test.2331096364 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 23966091 ps |
| CPU time | 0.84 seconds |
| Started | Jan 14 12:25:20 PM PST 24 |
| Finished | Jan 14 12:25:23 PM PST 24 |
| Peak memory | 204368 kb |
| Host | smart-6b293a43-3063-41eb-af26-765966dccb13 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331096364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2331096364 |
| Directory | /workspace/6.edn_alert_test/latest |
| Test location | /workspace/coverage/default/6.edn_disable.3796999128 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 32291663 ps |
| CPU time | 0.78 seconds |
| Started | Jan 14 12:25:19 PM PST 24 |
| Finished | Jan 14 12:25:23 PM PST 24 |
| Peak memory | 214204 kb |
| Host | smart-1b17dc7d-5771-45ba-8ca9-62612264cc0f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796999128 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3796999128 |
| Directory | /workspace/6.edn_disable/latest |
| Test location | /workspace/coverage/default/6.edn_disable_auto_req_mode.3243216265 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 75423370 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:25:21 PM PST 24 |
| Finished | Jan 14 12:25:24 PM PST 24 |
| Peak memory | 214388 kb |
| Host | smart-a17d42cb-1cff-4023-b4bb-8fd6ab56d884 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243216265 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di sable_auto_req_mode.3243216265 |
| Directory | /workspace/6.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/6.edn_err.549542730 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 29745472 ps |
| CPU time | 1.33 seconds |
| Started | Jan 14 12:25:46 PM PST 24 |
| Finished | Jan 14 12:25:50 PM PST 24 |
| Peak memory | 221876 kb |
| Host | smart-c114b929-2f09-4b99-912b-70e19708db3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=549542730 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.549542730 |
| Directory | /workspace/6.edn_err/latest |
| Test location | /workspace/coverage/default/6.edn_genbits.226499616 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 30593955 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:25:21 PM PST 24 |
| Finished | Jan 14 12:25:24 PM PST 24 |
| Peak memory | 205116 kb |
| Host | smart-5ecfad41-5a06-4b34-949b-f6c84c6cbc26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=226499616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.226499616 |
| Directory | /workspace/6.edn_genbits/latest |
| Test location | /workspace/coverage/default/6.edn_intr.3341055370 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 18913414 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:25:35 PM PST 24 |
| Finished | Jan 14 12:25:40 PM PST 24 |
| Peak memory | 214276 kb |
| Host | smart-4df2558b-6640-40ea-880d-cbeb3d6a8c01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3341055370 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3341055370 |
| Directory | /workspace/6.edn_intr/latest |
| Test location | /workspace/coverage/default/6.edn_regwen.1361145543 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 15794295 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:25:32 PM PST 24 |
| Finished | Jan 14 12:25:38 PM PST 24 |
| Peak memory | 204996 kb |
| Host | smart-3be60384-5bd6-499e-83a7-dfecb22be757 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1361145543 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1361145543 |
| Directory | /workspace/6.edn_regwen/latest |
| Test location | /workspace/coverage/default/6.edn_smoke.664388852 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 39660608 ps |
| CPU time | 0.82 seconds |
| Started | Jan 14 12:25:32 PM PST 24 |
| Finished | Jan 14 12:25:37 PM PST 24 |
| Peak memory | 204668 kb |
| Host | smart-bb634f49-8970-47b7-b6cc-7b72fa6ea003 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=664388852 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.664388852 |
| Directory | /workspace/6.edn_smoke/latest |
| Test location | /workspace/coverage/default/6.edn_stress_all.4288692400 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 145834510 ps |
| CPU time | 1.33 seconds |
| Started | Jan 14 12:25:26 PM PST 24 |
| Finished | Jan 14 12:25:32 PM PST 24 |
| Peak memory | 204712 kb |
| Host | smart-e8370c54-7a8f-4ad9-9cb7-2bbf3a7a5f78 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288692400 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.4288692400 |
| Directory | /workspace/6.edn_stress_all/latest |
| Test location | /workspace/coverage/default/6.edn_stress_all_with_rand_reset.731677146 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 775054361536 ps |
| CPU time | 1609.23 seconds |
| Started | Jan 14 12:25:40 PM PST 24 |
| Finished | Jan 14 12:52:34 PM PST 24 |
| Peak memory | 218968 kb |
| Host | smart-7c0f4ea0-ddb4-4bb3-98c6-f803f2d5a7a6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731677146 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.731677146 |
| Directory | /workspace/6.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/60.edn_err.495658996 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 55175388 ps |
| CPU time | 1.17 seconds |
| Started | Jan 14 12:26:50 PM PST 24 |
| Finished | Jan 14 12:26:52 PM PST 24 |
| Peak memory | 217024 kb |
| Host | smart-1885b761-8cf1-4034-9af0-1f03fd43b906 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=495658996 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.495658996 |
| Directory | /workspace/60.edn_err/latest |
| Test location | /workspace/coverage/default/60.edn_genbits.12114471 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 193551688 ps |
| CPU time | 1.27 seconds |
| Started | Jan 14 12:26:40 PM PST 24 |
| Finished | Jan 14 12:26:42 PM PST 24 |
| Peak memory | 214060 kb |
| Host | smart-94c3bd88-953c-460f-89cf-03fc4dbf50db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12114471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.12114471 |
| Directory | /workspace/60.edn_genbits/latest |
| Test location | /workspace/coverage/default/61.edn_err.134915222 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 22733863 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:26:31 PM PST 24 |
| Finished | Jan 14 12:26:32 PM PST 24 |
| Peak memory | 215388 kb |
| Host | smart-930fe6d1-4f8e-4b1c-97e8-ad6bd28b4bdf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=134915222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.134915222 |
| Directory | /workspace/61.edn_err/latest |
| Test location | /workspace/coverage/default/61.edn_genbits.4078635141 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 15952414 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:26:49 PM PST 24 |
| Finished | Jan 14 12:26:51 PM PST 24 |
| Peak memory | 205312 kb |
| Host | smart-7b37f555-bb0a-42f2-ac45-06e0ed68d432 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4078635141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.4078635141 |
| Directory | /workspace/61.edn_genbits/latest |
| Test location | /workspace/coverage/default/62.edn_err.1642252003 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 18350236 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:26:49 PM PST 24 |
| Finished | Jan 14 12:26:51 PM PST 24 |
| Peak memory | 215624 kb |
| Host | smart-79f27ae8-63f5-4226-ae33-60c483855dc0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1642252003 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.1642252003 |
| Directory | /workspace/62.edn_err/latest |
| Test location | /workspace/coverage/default/62.edn_genbits.1024337319 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 15523506 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:50 PM PST 24 |
| Finished | Jan 14 12:26:52 PM PST 24 |
| Peak memory | 204876 kb |
| Host | smart-ec323ff1-1a68-47b3-9e8a-0ae1daec36f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1024337319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1024337319 |
| Directory | /workspace/62.edn_genbits/latest |
| Test location | /workspace/coverage/default/63.edn_err.839487600 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 35970732 ps |
| CPU time | 0.8 seconds |
| Started | Jan 14 12:26:55 PM PST 24 |
| Finished | Jan 14 12:26:57 PM PST 24 |
| Peak memory | 215652 kb |
| Host | smart-c60aaa9a-9c95-4403-b8a7-15523e99f5f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=839487600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.839487600 |
| Directory | /workspace/63.edn_err/latest |
| Test location | /workspace/coverage/default/63.edn_genbits.1622395211 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 121083326 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:26:52 PM PST 24 |
| Finished | Jan 14 12:26:53 PM PST 24 |
| Peak memory | 205080 kb |
| Host | smart-fe54a1c7-7cee-4464-877c-5e817a41f3fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1622395211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1622395211 |
| Directory | /workspace/63.edn_genbits/latest |
| Test location | /workspace/coverage/default/64.edn_err.2990042876 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 22321325 ps |
| CPU time | 1.01 seconds |
| Started | Jan 14 12:26:48 PM PST 24 |
| Finished | Jan 14 12:26:50 PM PST 24 |
| Peak memory | 215980 kb |
| Host | smart-cb14e11a-34eb-458d-b0f5-cd3694cb3ef4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2990042876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2990042876 |
| Directory | /workspace/64.edn_err/latest |
| Test location | /workspace/coverage/default/64.edn_genbits.205603684 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 33151534 ps |
| CPU time | 1.08 seconds |
| Started | Jan 14 12:26:56 PM PST 24 |
| Finished | Jan 14 12:26:59 PM PST 24 |
| Peak memory | 214056 kb |
| Host | smart-4bb6b948-6382-494e-8ae0-7cb0d9422794 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=205603684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.205603684 |
| Directory | /workspace/64.edn_genbits/latest |
| Test location | /workspace/coverage/default/65.edn_err.701733171 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 23998913 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:27:00 PM PST 24 |
| Finished | Jan 14 12:27:02 PM PST 24 |
| Peak memory | 221764 kb |
| Host | smart-635a3007-ef2f-4f2e-9ffe-3449d3b78ac2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=701733171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.701733171 |
| Directory | /workspace/65.edn_err/latest |
| Test location | /workspace/coverage/default/65.edn_genbits.1326362178 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 57662990 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:27:02 PM PST 24 |
| Finished | Jan 14 12:27:05 PM PST 24 |
| Peak memory | 205028 kb |
| Host | smart-a133c8f0-fc14-4990-a774-dbf8924fbd29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1326362178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1326362178 |
| Directory | /workspace/65.edn_genbits/latest |
| Test location | /workspace/coverage/default/66.edn_err.1820670412 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 57142071 ps |
| CPU time | 1 seconds |
| Started | Jan 14 12:27:01 PM PST 24 |
| Finished | Jan 14 12:27:03 PM PST 24 |
| Peak memory | 216224 kb |
| Host | smart-5b6e92f0-a698-46e8-8e87-d47935afa560 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1820670412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1820670412 |
| Directory | /workspace/66.edn_err/latest |
| Test location | /workspace/coverage/default/66.edn_genbits.3412852106 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 55933350 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:27:04 PM PST 24 |
| Finished | Jan 14 12:27:11 PM PST 24 |
| Peak memory | 214016 kb |
| Host | smart-9178cd4d-e344-4380-9a7f-5df1a95ae1e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3412852106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3412852106 |
| Directory | /workspace/66.edn_genbits/latest |
| Test location | /workspace/coverage/default/67.edn_err.2000816296 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 18903623 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:26:54 PM PST 24 |
| Finished | Jan 14 12:26:55 PM PST 24 |
| Peak memory | 215460 kb |
| Host | smart-0039097d-2584-4f00-a888-fc27a83fc8f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2000816296 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2000816296 |
| Directory | /workspace/67.edn_err/latest |
| Test location | /workspace/coverage/default/67.edn_genbits.973019909 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 17921496 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:40 PM PST 24 |
| Finished | Jan 14 12:26:42 PM PST 24 |
| Peak memory | 204740 kb |
| Host | smart-247a4af1-bab6-400c-bc71-a58645554c33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=973019909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.973019909 |
| Directory | /workspace/67.edn_genbits/latest |
| Test location | /workspace/coverage/default/68.edn_err.2219532882 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 51072708 ps |
| CPU time | 1.22 seconds |
| Started | Jan 14 12:26:54 PM PST 24 |
| Finished | Jan 14 12:26:56 PM PST 24 |
| Peak memory | 216904 kb |
| Host | smart-6d7d05f0-70f9-4473-8629-9f9e9d98a5a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2219532882 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2219532882 |
| Directory | /workspace/68.edn_err/latest |
| Test location | /workspace/coverage/default/68.edn_genbits.1083426563 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 27174983 ps |
| CPU time | 1.11 seconds |
| Started | Jan 14 12:26:56 PM PST 24 |
| Finished | Jan 14 12:26:58 PM PST 24 |
| Peak memory | 205424 kb |
| Host | smart-03c03eac-4f6d-43e7-87bb-3c7cc7509dca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1083426563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1083426563 |
| Directory | /workspace/68.edn_genbits/latest |
| Test location | /workspace/coverage/default/69.edn_err.2111731363 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 31577407 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:27:02 PM PST 24 |
| Finished | Jan 14 12:27:04 PM PST 24 |
| Peak memory | 221832 kb |
| Host | smart-d5120400-3035-4bff-967e-1da02512e44a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2111731363 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2111731363 |
| Directory | /workspace/69.edn_err/latest |
| Test location | /workspace/coverage/default/69.edn_genbits.2585072938 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 38375127 ps |
| CPU time | 1.06 seconds |
| Started | Jan 14 12:26:48 PM PST 24 |
| Finished | Jan 14 12:26:50 PM PST 24 |
| Peak memory | 205632 kb |
| Host | smart-7dc31d1b-213a-4cf6-a1ba-ffb88cf606ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2585072938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2585072938 |
| Directory | /workspace/69.edn_genbits/latest |
| Test location | /workspace/coverage/default/7.edn_alert.2517491449 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 64231340 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:25:15 PM PST 24 |
| Finished | Jan 14 12:25:17 PM PST 24 |
| Peak memory | 205152 kb |
| Host | smart-95b9b5bf-d38d-451e-92b9-b3161e4a538d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2517491449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.2517491449 |
| Directory | /workspace/7.edn_alert/latest |
| Test location | /workspace/coverage/default/7.edn_alert_test.3985343641 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 71912808 ps |
| CPU time | 1.18 seconds |
| Started | Jan 14 12:25:20 PM PST 24 |
| Finished | Jan 14 12:25:23 PM PST 24 |
| Peak memory | 204616 kb |
| Host | smart-4c99f6f5-1253-486a-9fc3-6685293832fd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985343641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3985343641 |
| Directory | /workspace/7.edn_alert_test/latest |
| Test location | /workspace/coverage/default/7.edn_disable.3205503889 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 14915318 ps |
| CPU time | 0.9 seconds |
| Started | Jan 14 12:25:16 PM PST 24 |
| Finished | Jan 14 12:25:18 PM PST 24 |
| Peak memory | 214232 kb |
| Host | smart-f71d8c1b-4e23-464e-a7e4-210343c25895 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205503889 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3205503889 |
| Directory | /workspace/7.edn_disable/latest |
| Test location | /workspace/coverage/default/7.edn_err.4127445322 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 48056152 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:25:19 PM PST 24 |
| Finished | Jan 14 12:25:21 PM PST 24 |
| Peak memory | 216156 kb |
| Host | smart-dad73346-3e22-444e-a9e9-9b458384c9ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4127445322 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.4127445322 |
| Directory | /workspace/7.edn_err/latest |
| Test location | /workspace/coverage/default/7.edn_genbits.3302719096 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 29707539 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:25:26 PM PST 24 |
| Finished | Jan 14 12:25:31 PM PST 24 |
| Peak memory | 204872 kb |
| Host | smart-b2c6dd3e-30d4-478d-8416-cf8832c29590 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3302719096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3302719096 |
| Directory | /workspace/7.edn_genbits/latest |
| Test location | /workspace/coverage/default/7.edn_intr.2622254736 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 19358616 ps |
| CPU time | 1.07 seconds |
| Started | Jan 14 12:25:43 PM PST 24 |
| Finished | Jan 14 12:25:45 PM PST 24 |
| Peak memory | 214364 kb |
| Host | smart-42c4a13a-0525-4a5c-8b25-bfd35395e970 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2622254736 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2622254736 |
| Directory | /workspace/7.edn_intr/latest |
| Test location | /workspace/coverage/default/7.edn_regwen.219869029 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 31983343 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:25:37 PM PST 24 |
| Finished | Jan 14 12:25:40 PM PST 24 |
| Peak memory | 204720 kb |
| Host | smart-cadb6b02-55f1-404c-b2e4-1cc883001f30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219869029 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.219869029 |
| Directory | /workspace/7.edn_regwen/latest |
| Test location | /workspace/coverage/default/7.edn_smoke.3038587944 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 37191476 ps |
| CPU time | 0.84 seconds |
| Started | Jan 14 12:25:42 PM PST 24 |
| Finished | Jan 14 12:25:45 PM PST 24 |
| Peak memory | 204824 kb |
| Host | smart-50359b78-804b-412f-8498-e0f0ea2332ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3038587944 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3038587944 |
| Directory | /workspace/7.edn_smoke/latest |
| Test location | /workspace/coverage/default/7.edn_stress_all.909626151 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 111161286 ps |
| CPU time | 1.72 seconds |
| Started | Jan 14 12:25:26 PM PST 24 |
| Finished | Jan 14 12:25:32 PM PST 24 |
| Peak memory | 205500 kb |
| Host | smart-83e3af58-af7a-4833-9aff-6dfcc4836462 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909626151 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.909626151 |
| Directory | /workspace/7.edn_stress_all/latest |
| Test location | /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1376776199 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 44380153812 ps |
| CPU time | 570.71 seconds |
| Started | Jan 14 12:25:22 PM PST 24 |
| Finished | Jan 14 12:34:58 PM PST 24 |
| Peak memory | 214556 kb |
| Host | smart-34f34cd5-d334-470f-86da-54b8b89d2a35 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376776199 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1376776199 |
| Directory | /workspace/7.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/70.edn_err.1211787022 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 76171202 ps |
| CPU time | 1.09 seconds |
| Started | Jan 14 12:26:59 PM PST 24 |
| Finished | Jan 14 12:27:01 PM PST 24 |
| Peak memory | 217260 kb |
| Host | smart-4bde350d-ecea-49e1-a90f-ea0711f89275 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1211787022 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1211787022 |
| Directory | /workspace/70.edn_err/latest |
| Test location | /workspace/coverage/default/70.edn_genbits.3332785307 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 23392212 ps |
| CPU time | 1.12 seconds |
| Started | Jan 14 12:26:58 PM PST 24 |
| Finished | Jan 14 12:27:00 PM PST 24 |
| Peak memory | 205232 kb |
| Host | smart-23d511a2-1a95-46cb-a718-2462978fa63a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3332785307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3332785307 |
| Directory | /workspace/70.edn_genbits/latest |
| Test location | /workspace/coverage/default/71.edn_err.3694004592 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 36840347 ps |
| CPU time | 0.77 seconds |
| Started | Jan 14 12:26:50 PM PST 24 |
| Finished | Jan 14 12:26:52 PM PST 24 |
| Peak memory | 215240 kb |
| Host | smart-55356923-41fe-4d76-a8c6-df9e5c2033bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3694004592 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3694004592 |
| Directory | /workspace/71.edn_err/latest |
| Test location | /workspace/coverage/default/71.edn_genbits.1681103192 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 60074281 ps |
| CPU time | 2.32 seconds |
| Started | Jan 14 12:26:58 PM PST 24 |
| Finished | Jan 14 12:27:02 PM PST 24 |
| Peak memory | 214036 kb |
| Host | smart-de26ae4a-d2b0-4f92-8e17-c840e8572bdc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1681103192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1681103192 |
| Directory | /workspace/71.edn_genbits/latest |
| Test location | /workspace/coverage/default/72.edn_err.3304404435 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 28556260 ps |
| CPU time | 0.84 seconds |
| Started | Jan 14 12:26:48 PM PST 24 |
| Finished | Jan 14 12:26:49 PM PST 24 |
| Peak memory | 215488 kb |
| Host | smart-9f9346cc-561c-4c55-b54c-4d3a5ea0ffec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3304404435 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3304404435 |
| Directory | /workspace/72.edn_err/latest |
| Test location | /workspace/coverage/default/72.edn_genbits.3024711084 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 122521556 ps |
| CPU time | 2.85 seconds |
| Started | Jan 14 12:26:38 PM PST 24 |
| Finished | Jan 14 12:26:42 PM PST 24 |
| Peak memory | 214096 kb |
| Host | smart-7420980b-0d33-480f-aa3b-f8bb9a825f48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3024711084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3024711084 |
| Directory | /workspace/72.edn_genbits/latest |
| Test location | /workspace/coverage/default/73.edn_err.572638298 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 45537873 ps |
| CPU time | 1.15 seconds |
| Started | Jan 14 12:26:44 PM PST 24 |
| Finished | Jan 14 12:26:46 PM PST 24 |
| Peak memory | 221852 kb |
| Host | smart-48f33b48-f6db-47d7-b726-9a47469d2855 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=572638298 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.572638298 |
| Directory | /workspace/73.edn_err/latest |
| Test location | /workspace/coverage/default/73.edn_genbits.619872445 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 61181053 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:27:08 PM PST 24 |
| Finished | Jan 14 12:27:09 PM PST 24 |
| Peak memory | 205336 kb |
| Host | smart-0b12a427-e11a-4c1a-9bc0-e4eebb823a59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=619872445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.619872445 |
| Directory | /workspace/73.edn_genbits/latest |
| Test location | /workspace/coverage/default/74.edn_err.1178788732 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 56900838 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:26:30 PM PST 24 |
| Finished | Jan 14 12:26:32 PM PST 24 |
| Peak memory | 215792 kb |
| Host | smart-1c9af312-e87a-4ab6-9139-a7d80de8c7e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1178788732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1178788732 |
| Directory | /workspace/74.edn_err/latest |
| Test location | /workspace/coverage/default/74.edn_genbits.2016952139 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 31681020 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:26:34 PM PST 24 |
| Finished | Jan 14 12:26:36 PM PST 24 |
| Peak memory | 204936 kb |
| Host | smart-c44efc39-a456-42f7-8d30-aaa0755e1323 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2016952139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2016952139 |
| Directory | /workspace/74.edn_genbits/latest |
| Test location | /workspace/coverage/default/75.edn_err.1111847767 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 40147643 ps |
| CPU time | 1.07 seconds |
| Started | Jan 14 12:26:35 PM PST 24 |
| Finished | Jan 14 12:26:37 PM PST 24 |
| Peak memory | 221700 kb |
| Host | smart-ed29a31d-d90f-40f2-a945-87e6d423dcd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1111847767 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1111847767 |
| Directory | /workspace/75.edn_err/latest |
| Test location | /workspace/coverage/default/75.edn_genbits.2673083026 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 59075434 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:26:46 PM PST 24 |
| Finished | Jan 14 12:26:47 PM PST 24 |
| Peak memory | 204808 kb |
| Host | smart-de0400e8-91bb-4de0-aa5f-cacc7e903cf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2673083026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2673083026 |
| Directory | /workspace/75.edn_genbits/latest |
| Test location | /workspace/coverage/default/76.edn_err.1084570910 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 31479701 ps |
| CPU time | 0.83 seconds |
| Started | Jan 14 12:26:38 PM PST 24 |
| Finished | Jan 14 12:26:39 PM PST 24 |
| Peak memory | 215348 kb |
| Host | smart-6fed900a-68d0-4b7e-a737-f109a16f705b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1084570910 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1084570910 |
| Directory | /workspace/76.edn_err/latest |
| Test location | /workspace/coverage/default/76.edn_genbits.2685339272 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 22003073 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:26:48 PM PST 24 |
| Finished | Jan 14 12:26:50 PM PST 24 |
| Peak memory | 205116 kb |
| Host | smart-24bb1a89-735f-4d56-bd42-81472887eb2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2685339272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2685339272 |
| Directory | /workspace/76.edn_genbits/latest |
| Test location | /workspace/coverage/default/77.edn_err.3958889592 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 58373456 ps |
| CPU time | 1.06 seconds |
| Started | Jan 14 12:26:32 PM PST 24 |
| Finished | Jan 14 12:26:34 PM PST 24 |
| Peak memory | 216084 kb |
| Host | smart-5afc3706-3355-429e-a4c2-eac7dd0cb3f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3958889592 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3958889592 |
| Directory | /workspace/77.edn_err/latest |
| Test location | /workspace/coverage/default/77.edn_genbits.2372878146 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 66008594 ps |
| CPU time | 1.04 seconds |
| Started | Jan 14 12:26:44 PM PST 24 |
| Finished | Jan 14 12:26:46 PM PST 24 |
| Peak memory | 205008 kb |
| Host | smart-0c46d81e-cea3-480d-8feb-de2613ea7ca1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2372878146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2372878146 |
| Directory | /workspace/77.edn_genbits/latest |
| Test location | /workspace/coverage/default/78.edn_err.970790970 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 18170056 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:26:56 PM PST 24 |
| Finished | Jan 14 12:26:59 PM PST 24 |
| Peak memory | 215728 kb |
| Host | smart-e190b703-519f-4767-b23e-6b1cd43bc457 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=970790970 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.970790970 |
| Directory | /workspace/78.edn_err/latest |
| Test location | /workspace/coverage/default/78.edn_genbits.1101755689 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 72589102 ps |
| CPU time | 1.07 seconds |
| Started | Jan 14 12:26:47 PM PST 24 |
| Finished | Jan 14 12:26:49 PM PST 24 |
| Peak memory | 214076 kb |
| Host | smart-994c5596-c633-4275-a5b3-dbf9ad3d1718 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1101755689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1101755689 |
| Directory | /workspace/78.edn_genbits/latest |
| Test location | /workspace/coverage/default/79.edn_err.777809525 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 32090172 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:26:37 PM PST 24 |
| Finished | Jan 14 12:26:39 PM PST 24 |
| Peak memory | 215416 kb |
| Host | smart-322eab01-8bca-41cb-a9cc-f0c6a925ff97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=777809525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.777809525 |
| Directory | /workspace/79.edn_err/latest |
| Test location | /workspace/coverage/default/79.edn_genbits.4017940733 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 135608863 ps |
| CPU time | 1.68 seconds |
| Started | Jan 14 12:26:51 PM PST 24 |
| Finished | Jan 14 12:26:53 PM PST 24 |
| Peak memory | 214128 kb |
| Host | smart-ec556114-249a-4560-8413-044fdb633ee8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017940733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.4017940733 |
| Directory | /workspace/79.edn_genbits/latest |
| Test location | /workspace/coverage/default/8.edn_alert.214552703 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 33819071 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:25:36 PM PST 24 |
| Finished | Jan 14 12:25:40 PM PST 24 |
| Peak memory | 205652 kb |
| Host | smart-3d6ba339-cea8-482a-84ef-40a108036222 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=214552703 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.214552703 |
| Directory | /workspace/8.edn_alert/latest |
| Test location | /workspace/coverage/default/8.edn_alert_test.719582610 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 30459825 ps |
| CPU time | 0.92 seconds |
| Started | Jan 14 12:25:48 PM PST 24 |
| Finished | Jan 14 12:25:49 PM PST 24 |
| Peak memory | 204408 kb |
| Host | smart-136c5b59-cef5-421d-b722-e12c50f49883 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719582610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.719582610 |
| Directory | /workspace/8.edn_alert_test/latest |
| Test location | /workspace/coverage/default/8.edn_disable.3578375324 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 16344753 ps |
| CPU time | 0.8 seconds |
| Started | Jan 14 12:25:21 PM PST 24 |
| Finished | Jan 14 12:25:24 PM PST 24 |
| Peak memory | 214232 kb |
| Host | smart-3f2056c5-734b-4179-b5b8-a8978c9c48c4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578375324 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3578375324 |
| Directory | /workspace/8.edn_disable/latest |
| Test location | /workspace/coverage/default/8.edn_disable_auto_req_mode.2509689041 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 53958504 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:25:51 PM PST 24 |
| Finished | Jan 14 12:25:52 PM PST 24 |
| Peak memory | 214316 kb |
| Host | smart-e49ffe1e-89e0-4505-98de-433aad0c4734 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509689041 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di sable_auto_req_mode.2509689041 |
| Directory | /workspace/8.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/8.edn_err.3821993059 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 28601666 ps |
| CPU time | 1.19 seconds |
| Started | Jan 14 12:25:20 PM PST 24 |
| Finished | Jan 14 12:25:24 PM PST 24 |
| Peak memory | 214332 kb |
| Host | smart-fa5a431d-610d-44d6-a077-f87590a6a541 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3821993059 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3821993059 |
| Directory | /workspace/8.edn_err/latest |
| Test location | /workspace/coverage/default/8.edn_genbits.1275092471 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 67141083 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:25:21 PM PST 24 |
| Finished | Jan 14 12:25:24 PM PST 24 |
| Peak memory | 205376 kb |
| Host | smart-0d1245b3-011f-451c-af29-f3fc1bc345bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1275092471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1275092471 |
| Directory | /workspace/8.edn_genbits/latest |
| Test location | /workspace/coverage/default/8.edn_intr.1042035320 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 32869463 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:25:46 PM PST 24 |
| Finished | Jan 14 12:25:49 PM PST 24 |
| Peak memory | 214220 kb |
| Host | smart-3fe08edd-98d5-4a4a-ab53-83ac5d629af7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1042035320 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1042035320 |
| Directory | /workspace/8.edn_intr/latest |
| Test location | /workspace/coverage/default/8.edn_regwen.779486876 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 15229817 ps |
| CPU time | 0.88 seconds |
| Started | Jan 14 12:25:21 PM PST 24 |
| Finished | Jan 14 12:25:24 PM PST 24 |
| Peak memory | 204592 kb |
| Host | smart-1ef0de3b-81ae-4fb9-bbe5-36acfcdda006 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=779486876 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.779486876 |
| Directory | /workspace/8.edn_regwen/latest |
| Test location | /workspace/coverage/default/8.edn_smoke.3754924876 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 16895504 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:25:31 PM PST 24 |
| Finished | Jan 14 12:25:36 PM PST 24 |
| Peak memory | 204596 kb |
| Host | smart-1d309937-e3f9-4970-98ce-13885f18d66c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3754924876 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3754924876 |
| Directory | /workspace/8.edn_smoke/latest |
| Test location | /workspace/coverage/default/8.edn_stress_all.379070562 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 782077041 ps |
| CPU time | 4.26 seconds |
| Started | Jan 14 12:25:43 PM PST 24 |
| Finished | Jan 14 12:25:48 PM PST 24 |
| Peak memory | 205868 kb |
| Host | smart-4a67197e-870e-4c3a-a9a3-b013026e12d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379070562 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.379070562 |
| Directory | /workspace/8.edn_stress_all/latest |
| Test location | /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2673329600 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 96424205257 ps |
| CPU time | 1232.83 seconds |
| Started | Jan 14 12:25:19 PM PST 24 |
| Finished | Jan 14 12:45:53 PM PST 24 |
| Peak memory | 218920 kb |
| Host | smart-0b09e886-c706-4713-972f-bad7451c8898 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673329600 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2673329600 |
| Directory | /workspace/8.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/80.edn_err.1596519018 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 23039947 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:27:01 PM PST 24 |
| Finished | Jan 14 12:27:03 PM PST 24 |
| Peak memory | 215900 kb |
| Host | smart-8b3a5e4e-1838-4c25-aa32-b260067085d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1596519018 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1596519018 |
| Directory | /workspace/80.edn_err/latest |
| Test location | /workspace/coverage/default/80.edn_genbits.842247163 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 25654505 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:26:53 PM PST 24 |
| Finished | Jan 14 12:26:55 PM PST 24 |
| Peak memory | 205680 kb |
| Host | smart-11bfdcfc-87c2-4939-9c97-71272704ac53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=842247163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.842247163 |
| Directory | /workspace/80.edn_genbits/latest |
| Test location | /workspace/coverage/default/81.edn_err.2967106843 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 25681872 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:26:56 PM PST 24 |
| Finished | Jan 14 12:26:58 PM PST 24 |
| Peak memory | 215372 kb |
| Host | smart-5fdfda5d-bc10-49b8-a883-6886b8f39243 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2967106843 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2967106843 |
| Directory | /workspace/81.edn_err/latest |
| Test location | /workspace/coverage/default/81.edn_genbits.2256182754 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 22777957 ps |
| CPU time | 1.13 seconds |
| Started | Jan 14 12:26:53 PM PST 24 |
| Finished | Jan 14 12:26:55 PM PST 24 |
| Peak memory | 205284 kb |
| Host | smart-0cd15c0a-f611-453d-89d9-961c2621accd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2256182754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2256182754 |
| Directory | /workspace/81.edn_genbits/latest |
| Test location | /workspace/coverage/default/82.edn_err.1586180872 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 24038600 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:26:55 PM PST 24 |
| Finished | Jan 14 12:26:59 PM PST 24 |
| Peak memory | 221844 kb |
| Host | smart-c0523ba5-07f0-4583-b00b-4ed3ab6dba3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1586180872 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1586180872 |
| Directory | /workspace/82.edn_err/latest |
| Test location | /workspace/coverage/default/82.edn_genbits.870126232 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 29468594 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:26:46 PM PST 24 |
| Finished | Jan 14 12:26:48 PM PST 24 |
| Peak memory | 205288 kb |
| Host | smart-ce40be40-5396-4527-9ac4-495c5c0a4621 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=870126232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.870126232 |
| Directory | /workspace/82.edn_genbits/latest |
| Test location | /workspace/coverage/default/83.edn_err.517747031 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 18836288 ps |
| CPU time | 1.08 seconds |
| Started | Jan 14 12:26:57 PM PST 24 |
| Finished | Jan 14 12:26:59 PM PST 24 |
| Peak memory | 221844 kb |
| Host | smart-e396cf08-db48-4d6c-b293-1aab3cbb8e54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=517747031 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.517747031 |
| Directory | /workspace/83.edn_err/latest |
| Test location | /workspace/coverage/default/83.edn_genbits.1037476602 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 46471069 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:26:52 PM PST 24 |
| Finished | Jan 14 12:26:53 PM PST 24 |
| Peak memory | 205228 kb |
| Host | smart-afaf3566-87dc-4f56-a771-2fac063c3dc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1037476602 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1037476602 |
| Directory | /workspace/83.edn_genbits/latest |
| Test location | /workspace/coverage/default/84.edn_err.1993250481 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 128103980 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:27:04 PM PST 24 |
| Finished | Jan 14 12:27:06 PM PST 24 |
| Peak memory | 216160 kb |
| Host | smart-691afade-2d9e-4a04-a0fc-24e5b203d17d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1993250481 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1993250481 |
| Directory | /workspace/84.edn_err/latest |
| Test location | /workspace/coverage/default/84.edn_genbits.822787468 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 246899690 ps |
| CPU time | 1.16 seconds |
| Started | Jan 14 12:26:56 PM PST 24 |
| Finished | Jan 14 12:26:58 PM PST 24 |
| Peak memory | 205244 kb |
| Host | smart-c1034481-b721-4b30-96b4-e369e95e210e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=822787468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.822787468 |
| Directory | /workspace/84.edn_genbits/latest |
| Test location | /workspace/coverage/default/85.edn_err.941183257 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 17937982 ps |
| CPU time | 1.01 seconds |
| Started | Jan 14 12:26:36 PM PST 24 |
| Finished | Jan 14 12:26:38 PM PST 24 |
| Peak memory | 215192 kb |
| Host | smart-c28b8195-9ee8-4b1a-9ecd-7de631c2ea86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=941183257 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.941183257 |
| Directory | /workspace/85.edn_err/latest |
| Test location | /workspace/coverage/default/85.edn_genbits.4225501027 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 64683292 ps |
| CPU time | 1.18 seconds |
| Started | Jan 14 12:26:55 PM PST 24 |
| Finished | Jan 14 12:26:57 PM PST 24 |
| Peak memory | 214128 kb |
| Host | smart-85f92159-a6da-46cf-b5d2-11af496e3d51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4225501027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.4225501027 |
| Directory | /workspace/85.edn_genbits/latest |
| Test location | /workspace/coverage/default/86.edn_err.3282161922 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 45344821 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:26:50 PM PST 24 |
| Finished | Jan 14 12:26:52 PM PST 24 |
| Peak memory | 215384 kb |
| Host | smart-c3711ff6-3094-4bed-b75e-5d47b4a7aced |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3282161922 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3282161922 |
| Directory | /workspace/86.edn_err/latest |
| Test location | /workspace/coverage/default/86.edn_genbits.1653153843 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 57896887 ps |
| CPU time | 1 seconds |
| Started | Jan 14 12:26:37 PM PST 24 |
| Finished | Jan 14 12:26:38 PM PST 24 |
| Peak memory | 204756 kb |
| Host | smart-e111c065-9c67-4b15-9ca3-dc74d8fb0138 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1653153843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1653153843 |
| Directory | /workspace/86.edn_genbits/latest |
| Test location | /workspace/coverage/default/87.edn_genbits.1576484839 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 42532870 ps |
| CPU time | 1.64 seconds |
| Started | Jan 14 12:26:50 PM PST 24 |
| Finished | Jan 14 12:27:00 PM PST 24 |
| Peak memory | 214068 kb |
| Host | smart-070ca204-bdba-405d-b06a-3fc1373db644 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1576484839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1576484839 |
| Directory | /workspace/87.edn_genbits/latest |
| Test location | /workspace/coverage/default/88.edn_err.3230401294 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 35105087 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:26:51 PM PST 24 |
| Finished | Jan 14 12:26:53 PM PST 24 |
| Peak memory | 221852 kb |
| Host | smart-a82ad0e8-6a19-4fd6-9bdd-086f97728a7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3230401294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3230401294 |
| Directory | /workspace/88.edn_err/latest |
| Test location | /workspace/coverage/default/88.edn_genbits.4250914273 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 61528945 ps |
| CPU time | 0.89 seconds |
| Started | Jan 14 12:26:29 PM PST 24 |
| Finished | Jan 14 12:26:30 PM PST 24 |
| Peak memory | 204896 kb |
| Host | smart-cbc4264f-57f6-442a-9c25-6684bdc800a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4250914273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.4250914273 |
| Directory | /workspace/88.edn_genbits/latest |
| Test location | /workspace/coverage/default/89.edn_err.433160641 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 96600924 ps |
| CPU time | 1.16 seconds |
| Started | Jan 14 12:27:02 PM PST 24 |
| Finished | Jan 14 12:27:05 PM PST 24 |
| Peak memory | 216872 kb |
| Host | smart-a9bedcbc-f651-47fe-8df0-b86ed3753967 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=433160641 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.433160641 |
| Directory | /workspace/89.edn_err/latest |
| Test location | /workspace/coverage/default/89.edn_genbits.1711853428 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 27461430 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:26:45 PM PST 24 |
| Finished | Jan 14 12:26:47 PM PST 24 |
| Peak memory | 204708 kb |
| Host | smart-b71f77f7-5a82-4bcd-86e3-89f720c5322e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1711853428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1711853428 |
| Directory | /workspace/89.edn_genbits/latest |
| Test location | /workspace/coverage/default/9.edn_alert.1136441110 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 58607496 ps |
| CPU time | 0.94 seconds |
| Started | Jan 14 12:25:47 PM PST 24 |
| Finished | Jan 14 12:25:49 PM PST 24 |
| Peak memory | 205168 kb |
| Host | smart-03d613af-3d68-4a11-bb4a-6d8df612c696 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1136441110 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1136441110 |
| Directory | /workspace/9.edn_alert/latest |
| Test location | /workspace/coverage/default/9.edn_alert_test.262964371 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 34373186 ps |
| CPU time | 0.79 seconds |
| Started | Jan 14 12:25:34 PM PST 24 |
| Finished | Jan 14 12:25:38 PM PST 24 |
| Peak memory | 204240 kb |
| Host | smart-8edc7c4c-423f-43cc-9eb1-9dc58648f524 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262964371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.262964371 |
| Directory | /workspace/9.edn_alert_test/latest |
| Test location | /workspace/coverage/default/9.edn_disable.132160039 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 12663947 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:25:26 PM PST 24 |
| Finished | Jan 14 12:25:31 PM PST 24 |
| Peak memory | 214268 kb |
| Host | smart-b4d2618f-2f2b-4615-b45d-5532f616dfcd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132160039 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.132160039 |
| Directory | /workspace/9.edn_disable/latest |
| Test location | /workspace/coverage/default/9.edn_disable_auto_req_mode.3493230535 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 27993212 ps |
| CPU time | 1.06 seconds |
| Started | Jan 14 12:25:33 PM PST 24 |
| Finished | Jan 14 12:25:38 PM PST 24 |
| Peak memory | 214352 kb |
| Host | smart-1c1b41ed-6ec8-4324-9d96-5dac4606286b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493230535 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di sable_auto_req_mode.3493230535 |
| Directory | /workspace/9.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/9.edn_err.3094476273 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 30392467 ps |
| CPU time | 0.87 seconds |
| Started | Jan 14 12:25:56 PM PST 24 |
| Finished | Jan 14 12:25:58 PM PST 24 |
| Peak memory | 215832 kb |
| Host | smart-62785eeb-90b7-4b29-b169-0287284f22fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3094476273 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3094476273 |
| Directory | /workspace/9.edn_err/latest |
| Test location | /workspace/coverage/default/9.edn_genbits.3044426303 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 70936269 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:25:22 PM PST 24 |
| Finished | Jan 14 12:25:25 PM PST 24 |
| Peak memory | 204936 kb |
| Host | smart-3e12f7da-e5ae-4519-b5aa-ac25136cc560 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3044426303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3044426303 |
| Directory | /workspace/9.edn_genbits/latest |
| Test location | /workspace/coverage/default/9.edn_smoke.2896881121 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 22506941 ps |
| CPU time | 0.85 seconds |
| Started | Jan 14 12:25:26 PM PST 24 |
| Finished | Jan 14 12:25:31 PM PST 24 |
| Peak memory | 204644 kb |
| Host | smart-07d34808-1713-47a2-9c95-7ecfee017732 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896881121 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2896881121 |
| Directory | /workspace/9.edn_smoke/latest |
| Test location | /workspace/coverage/default/9.edn_stress_all.3596230926 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 339395586 ps |
| CPU time | 3.65 seconds |
| Started | Jan 14 12:25:26 PM PST 24 |
| Finished | Jan 14 12:25:34 PM PST 24 |
| Peak memory | 205640 kb |
| Host | smart-be965b41-5796-4b59-9ba4-732241c1318c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596230926 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3596230926 |
| Directory | /workspace/9.edn_stress_all/latest |
| Test location | /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2311090827 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 145111440409 ps |
| CPU time | 1625.17 seconds |
| Started | Jan 14 12:25:18 PM PST 24 |
| Finished | Jan 14 12:52:25 PM PST 24 |
| Peak memory | 219168 kb |
| Host | smart-69307e14-fc2d-47f6-b60d-dcbb962a587f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311090827 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2311090827 |
| Directory | /workspace/9.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/90.edn_err.3404816979 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 53916197 ps |
| CPU time | 0.81 seconds |
| Started | Jan 14 12:26:50 PM PST 24 |
| Finished | Jan 14 12:26:52 PM PST 24 |
| Peak memory | 214940 kb |
| Host | smart-d9bce79f-a8e7-4086-a28f-34de8f17568e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3404816979 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3404816979 |
| Directory | /workspace/90.edn_err/latest |
| Test location | /workspace/coverage/default/90.edn_genbits.3989658291 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 31774765 ps |
| CPU time | 0.99 seconds |
| Started | Jan 14 12:26:44 PM PST 24 |
| Finished | Jan 14 12:26:46 PM PST 24 |
| Peak memory | 205416 kb |
| Host | smart-fcbe8b7f-a6fe-4ab7-be30-3cc222a68c8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3989658291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3989658291 |
| Directory | /workspace/90.edn_genbits/latest |
| Test location | /workspace/coverage/default/91.edn_err.3537158774 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 26719781 ps |
| CPU time | 1.14 seconds |
| Started | Jan 14 12:26:39 PM PST 24 |
| Finished | Jan 14 12:26:40 PM PST 24 |
| Peak memory | 214424 kb |
| Host | smart-9749c789-863b-4aba-b0f2-414c545fc9f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3537158774 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3537158774 |
| Directory | /workspace/91.edn_err/latest |
| Test location | /workspace/coverage/default/91.edn_genbits.2681997451 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 147181913 ps |
| CPU time | 1.03 seconds |
| Started | Jan 14 12:26:53 PM PST 24 |
| Finished | Jan 14 12:26:55 PM PST 24 |
| Peak memory | 205368 kb |
| Host | smart-586de559-43ce-45cc-b76e-f993e03a2de0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2681997451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2681997451 |
| Directory | /workspace/91.edn_genbits/latest |
| Test location | /workspace/coverage/default/92.edn_err.1227074541 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 44931866 ps |
| CPU time | 0.91 seconds |
| Started | Jan 14 12:26:40 PM PST 24 |
| Finished | Jan 14 12:26:42 PM PST 24 |
| Peak memory | 215992 kb |
| Host | smart-26a93485-28e8-48a1-b549-41da1b8e4d2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1227074541 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1227074541 |
| Directory | /workspace/92.edn_err/latest |
| Test location | /workspace/coverage/default/92.edn_genbits.2096909830 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 19356136 ps |
| CPU time | 1.05 seconds |
| Started | Jan 14 12:26:46 PM PST 24 |
| Finished | Jan 14 12:26:47 PM PST 24 |
| Peak memory | 205036 kb |
| Host | smart-52664b5d-9856-494f-b3e8-8c06e72987b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2096909830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2096909830 |
| Directory | /workspace/92.edn_genbits/latest |
| Test location | /workspace/coverage/default/93.edn_err.219443442 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 18458360 ps |
| CPU time | 1.01 seconds |
| Started | Jan 14 12:27:01 PM PST 24 |
| Finished | Jan 14 12:27:03 PM PST 24 |
| Peak memory | 215596 kb |
| Host | smart-fc99bfe5-08b2-4a4c-9e5f-f13158305bcb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=219443442 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.219443442 |
| Directory | /workspace/93.edn_err/latest |
| Test location | /workspace/coverage/default/93.edn_genbits.174476197 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 33597566 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:27:01 PM PST 24 |
| Finished | Jan 14 12:27:03 PM PST 24 |
| Peak memory | 205416 kb |
| Host | smart-f7699c1f-8cd0-48ba-82e9-ebe27cfbdb33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=174476197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.174476197 |
| Directory | /workspace/93.edn_genbits/latest |
| Test location | /workspace/coverage/default/94.edn_err.123146831 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 58909420 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:26:50 PM PST 24 |
| Finished | Jan 14 12:26:52 PM PST 24 |
| Peak memory | 215840 kb |
| Host | smart-e5a71bd7-33f1-4582-afc6-e25f4e5198eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=123146831 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.123146831 |
| Directory | /workspace/94.edn_err/latest |
| Test location | /workspace/coverage/default/94.edn_genbits.2407327174 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 33047417 ps |
| CPU time | 0.96 seconds |
| Started | Jan 14 12:26:41 PM PST 24 |
| Finished | Jan 14 12:26:42 PM PST 24 |
| Peak memory | 214048 kb |
| Host | smart-92285d7f-b350-4fd4-b470-d2cb2edb9395 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2407327174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2407327174 |
| Directory | /workspace/94.edn_genbits/latest |
| Test location | /workspace/coverage/default/95.edn_err.2551045285 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 58607144 ps |
| CPU time | 0.86 seconds |
| Started | Jan 14 12:26:56 PM PST 24 |
| Finished | Jan 14 12:26:58 PM PST 24 |
| Peak memory | 221188 kb |
| Host | smart-d4e58a2f-f900-4595-bb70-903b2ea1825f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2551045285 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2551045285 |
| Directory | /workspace/95.edn_err/latest |
| Test location | /workspace/coverage/default/95.edn_genbits.4016204502 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 27381540 ps |
| CPU time | 0.98 seconds |
| Started | Jan 14 12:27:01 PM PST 24 |
| Finished | Jan 14 12:27:03 PM PST 24 |
| Peak memory | 205544 kb |
| Host | smart-f7d2736b-4fc7-4654-801f-e7ffe687e64f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4016204502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.4016204502 |
| Directory | /workspace/95.edn_genbits/latest |
| Test location | /workspace/coverage/default/96.edn_err.2763173091 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 24207231 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:27:04 PM PST 24 |
| Finished | Jan 14 12:27:06 PM PST 24 |
| Peak memory | 215568 kb |
| Host | smart-a53c4f9e-a989-4310-89dd-30ed5cecc488 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2763173091 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2763173091 |
| Directory | /workspace/96.edn_err/latest |
| Test location | /workspace/coverage/default/96.edn_genbits.1900222709 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 19567075 ps |
| CPU time | 1.02 seconds |
| Started | Jan 14 12:26:59 PM PST 24 |
| Finished | Jan 14 12:27:01 PM PST 24 |
| Peak memory | 205216 kb |
| Host | smart-bc7d35ac-4797-47ad-b396-0a93294edc53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1900222709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1900222709 |
| Directory | /workspace/96.edn_genbits/latest |
| Test location | /workspace/coverage/default/97.edn_err.2011575968 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 34688682 ps |
| CPU time | 1.15 seconds |
| Started | Jan 14 12:26:51 PM PST 24 |
| Finished | Jan 14 12:26:53 PM PST 24 |
| Peak memory | 221844 kb |
| Host | smart-2f7de91a-6b8b-4b24-821f-9be982ace056 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2011575968 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2011575968 |
| Directory | /workspace/97.edn_err/latest |
| Test location | /workspace/coverage/default/97.edn_genbits.480652182 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 76825690 ps |
| CPU time | 1.06 seconds |
| Started | Jan 14 12:27:06 PM PST 24 |
| Finished | Jan 14 12:27:08 PM PST 24 |
| Peak memory | 214140 kb |
| Host | smart-87768099-f6cf-40cf-bf42-ddeffbdc5d8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=480652182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.480652182 |
| Directory | /workspace/97.edn_genbits/latest |
| Test location | /workspace/coverage/default/98.edn_err.2809098058 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 43274934 ps |
| CPU time | 0.77 seconds |
| Started | Jan 14 12:26:53 PM PST 24 |
| Finished | Jan 14 12:26:55 PM PST 24 |
| Peak memory | 215392 kb |
| Host | smart-ed9353d4-b673-4c4d-a6c2-a72bc5d7f379 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2809098058 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2809098058 |
| Directory | /workspace/98.edn_err/latest |
| Test location | /workspace/coverage/default/98.edn_genbits.441960883 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 59944323 ps |
| CPU time | 0.93 seconds |
| Started | Jan 14 12:26:53 PM PST 24 |
| Finished | Jan 14 12:26:55 PM PST 24 |
| Peak memory | 204968 kb |
| Host | smart-1e1176c2-e184-4493-8d26-09dc0c300511 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=441960883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.441960883 |
| Directory | /workspace/98.edn_genbits/latest |
| Test location | /workspace/coverage/default/99.edn_err.1893779231 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 18458778 ps |
| CPU time | 0.97 seconds |
| Started | Jan 14 12:26:46 PM PST 24 |
| Finished | Jan 14 12:26:48 PM PST 24 |
| Peak memory | 215216 kb |
| Host | smart-d4110b36-3640-4214-baae-e65f313b069a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1893779231 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1893779231 |
| Directory | /workspace/99.edn_err/latest |
| Test location | /workspace/coverage/default/99.edn_genbits.898747500 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 58369609 ps |
| CPU time | 0.95 seconds |
| Started | Jan 14 12:27:05 PM PST 24 |
| Finished | Jan 14 12:27:06 PM PST 24 |
| Peak memory | 205128 kb |
| Host | smart-0e573cab-3b80-4fbf-a7bb-7a68eeb345eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=898747500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.898747500 |
| Directory | /workspace/99.edn_genbits/latest |
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