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LINE 298
EXPRESSION (edn_cntr_err_sum || edn_main_sm_err_sum || edn_ack_sm_err_sum)
--------1------- ---------2--------- ---------3--------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T64,T78,T79 |
0 | 1 | 0 | Covered | T62,T63,T65 |
1 | 0 | 0 | Covered | T4,T6,T12 |
LINE 303
EXPRESSION ((edn_enable_fo[FatalErr] && (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum || sfifo_output_err_sum)) || fatal_loc_events)
-------------------------------------------------1------------------------------------------------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T4,T6,T12 |
1 | 0 | Covered | T61,T80,T81 |
LINE 303
SUB-EXPRESSION (edn_enable_fo[FatalErr] && (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum || sfifo_output_err_sum))
-----------1----------- -----------------------------------2----------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T61,T80,T81 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T61,T80,T81 |
LINE 303
SUB-EXPRESSION (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum || sfifo_output_err_sum)
----------1--------- ----------2--------- ----------3---------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Not Covered | |
0 | 1 | 0 | Covered | T61,T80,T81 |
1 | 0 | 0 | Covered | T82,T83,T84 |
LINE 310
EXPRESSION (((|sfifo_rescmd_err)) || err_code_test_bit[0])
----------1---------- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T82,T83,T84 |
LINE 312
EXPRESSION (((|sfifo_gencmd_err)) || err_code_test_bit[1])
----------1---------- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T61,T80,T81 |
LINE 314
EXPRESSION (((|sfifo_output_err)) || err_code_test_bit[2])
----------1---------- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 316
EXPRESSION (((|edn_ack_sm_err)) || err_code_test_bit[20])
---------1--------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T6,T12 |
LINE 318
EXPRESSION (edn_main_sm_err || err_code_test_bit[21])
-------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T6,T12 |
LINE 320
EXPRESSION (edn_cntr_err || err_code_test_bit[22])
------1----- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T6,T12 |
LINE 323
EXPRESSION (sfifo_rescmd_err[2] || sfifo_gencmd_err[2] || sfifo_output_err[2] || err_code_test_bit[28])
---------1--------- ---------2--------- ---------3--------- ----------4----------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 1 | 0 | Not Covered | |
0 | 1 | 0 | 0 | Covered | T85 |
1 | 0 | 0 | 0 | Covered | T86 |
LINE 328
EXPRESSION (sfifo_rescmd_err[1] || sfifo_gencmd_err[1] || sfifo_output_err[1] || err_code_test_bit[29])
---------1--------- ---------2--------- ---------3--------- ----------4----------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 1 | 0 | Not Covered | |
0 | 1 | 0 | 0 | Covered | T61,T80,T81 |
1 | 0 | 0 | 0 | Covered | T82,T84,T87 |
LINE 333
EXPRESSION (sfifo_rescmd_err[0] || sfifo_gencmd_err[0] || sfifo_output_err[0] || err_code_test_bit[30])
---------1--------- ---------2--------- ---------3--------- ----------4----------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 1 | 0 | Not Covered | |
0 | 1 | 0 | 0 | Covered | T88,T89,T85 |
1 | 0 | 0 | 0 | Covered | T83,T90,T91 |
LINE 342
EXPRESSION (edn_enable_fo[ReseedCmdErr] && sfifo_rescmd_err_sum)
-------------1------------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T82,T83,T84 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T82,T83,T84 |
LINE 345
EXPRESSION (edn_enable_fo[GenCmdErr] && sfifo_gencmd_err_sum)
------------1----------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T61,T80,T81 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T61,T80,T81 |
LINE 348
EXPRESSION (edn_enable_fo[OutputErr] && sfifo_output_err_sum)
------------1----------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Not Covered | |
LINE 365
EXPRESSION (edn_enable_fo[FifoWrErr] && fifo_write_err_sum)
------------1----------- ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T85,T86 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T85,T86 |
LINE 368
EXPRESSION (edn_enable_fo[FifoRdErr] && fifo_read_err_sum)
------------1----------- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T61,T80,T81 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T61,T80,T81 |
LINE 371
EXPRESSION (edn_enable_fo[FifoStErr] && fifo_status_err_sum)
------------1----------- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T83,T88,T89 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T83,T88,T89 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 0) && reg2hw.err_code_test.qe)
--------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Not Covered | |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 0)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 1) && reg2hw.err_code_test.qe)
--------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 1)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 2) && reg2hw.err_code_test.qe)
--------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 2)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 3) && reg2hw.err_code_test.qe)
--------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T6,T62,T63 |
1 | 1 | Covered | T6,T62,T63 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 3)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T62,T63 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 4) && reg2hw.err_code_test.qe)
--------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T2,T5,T92 |
1 | 1 | Covered | T2,T5,T92 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 4)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T92 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 5) && reg2hw.err_code_test.qe)
--------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T2,T5,T93 |
1 | 1 | Covered | T2,T5,T93 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 5)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T93 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 6) && reg2hw.err_code_test.qe)
--------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T7,T93,T92 |
1 | 1 | Covered | T7,T93,T92 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 6)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T7,T93,T92 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 7) && reg2hw.err_code_test.qe)
--------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T92,T94,T95 |
1 | 1 | Covered | T92,T94,T95 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 7)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T92,T94,T95 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 8) && reg2hw.err_code_test.qe)
--------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T5,T93,T96 |
1 | 1 | Covered | T5,T93,T96 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 8)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T93,T96 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 9) && reg2hw.err_code_test.qe)
--------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T2,T5,T92 |
1 | 1 | Covered | T2,T5,T92 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 9)
--------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T92 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 10) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T5,T6,T95 |
1 | 1 | Covered | T5,T6,T95 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 10)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T95 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 11) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T5,T8,T68 |
1 | 1 | Covered | T5,T8,T68 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 11)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T8,T68 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 12) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T5,T97,T26 |
1 | 1 | Covered | T5,T97,T26 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 12)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T97,T26 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 13) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T2,T7,T93 |
1 | 1 | Covered | T2,T7,T93 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 13)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T7,T93 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 14) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T5,T62,T63 |
1 | 1 | Covered | T5,T62,T63 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 14)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T62,T63 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 15) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T14,T44 |
1 | 0 | Covered | T13,T5,T12 |
1 | 1 | Covered | T13,T5,T12 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 15)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T13,T5,T12 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 16) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T44 |
1 | 0 | Covered | T14,T5,T92 |
1 | 1 | Covered | T14,T5,T92 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 16)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T14,T5,T92 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 17) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T45,T5,T97 |
1 | 1 | Covered | T45,T5,T97 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 17)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T45,T5,T97 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 18) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T5,T93,T31 |
1 | 1 | Covered | T5,T93,T31 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 18)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T93,T31 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 19) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T2,T44,T98 |
1 | 1 | Covered | T2,T44,T98 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 19)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T44,T98 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 20) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 20)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 21) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 21)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 22) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 22)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 23) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T5,T93,T99 |
1 | 1 | Covered | T5,T93,T99 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 23)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T93,T99 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 24) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T97,T100,T92 |
1 | 1 | Covered | T97,T100,T92 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 24)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T97,T100,T92 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 25) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T2,T5,T93 |
1 | 1 | Covered | T2,T5,T93 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 25)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T93 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 26) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T2,T5,T15 |
1 | 1 | Covered | T2,T5,T15 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 26)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T5,T15 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 27) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Covered | T5,T97,T101 |
1 | 1 | Covered | T5,T97,T101 |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 27)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T97,T101 |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 28) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 28)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 29) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 29)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 376
EXPRESSION ((reg2hw.err_code_test.q == 30) && reg2hw.err_code_test.qe)
---------------1-------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T2,T13,T14 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 376
SUB-EXPRESSION (reg2hw.err_code_test.q == 30)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 384
SUB-EXPRESSION (reg2hw.alert_test.recov_alert.q && reg2hw.alert_test.recov_alert.qe)
---------------1--------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T47,T48 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T16,T47,T48 |
LINE 388
SUB-EXPRESSION (reg2hw.alert_test.fatal_alert.q && reg2hw.alert_test.fatal_alert.qe)
---------------1--------------- ----------------2---------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T47,T48 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T16,T47,T48 |
LINE 464
EXPRESSION (reg2hw.sw_cmd_req.qe & sw_cmd_valid)
----------1--------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T8,T9 |
1 | 1 | Covered | T1,T2,T3 |
LINE 476
EXPRESSION (((!edn_enable_fo[CsrngCmdReq])) ? '0 : (boot_wr_cmd_reg ? boot_ins_cmd : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)))
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 476
SUB-EXPRESSION (boot_wr_cmd_reg ? boot_ins_cmd : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q))
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T19,T27,T12 |
LINE 476
SUB-EXPRESSION (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 482
EXPRESSION (((!edn_enable_fo[CsrngCmdReqValid])) ? '0 : (sw_cmd_req_load || boot_wr_cmd_reg))
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 482
SUB-EXPRESSION (sw_cmd_req_load || boot_wr_cmd_reg)
-------1------- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T19,T27,T12 |
1 | 0 | Covered | T1,T2,T3 |
LINE 486
EXPRESSION
Number Term
1 ((!edn_enable_fo[CsrngCmdReqOut])) ? '0 : (send_rescmd ? sfifo_rescmd_rdata : ((send_gencmd || boot_send_gencmd) ? sfifo_gencmd_rdata : cs_cmd_req_q)))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 486
SUB-EXPRESSION (send_rescmd ? sfifo_rescmd_rdata : ((send_gencmd || boot_send_gencmd) ? sfifo_gencmd_rdata : cs_cmd_req_q))
-----1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T8,T9 |
LINE 486
SUB-EXPRESSION ((send_gencmd || boot_send_gencmd) ? sfifo_gencmd_rdata : cs_cmd_req_q)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T19,T27 |
LINE 486
SUB-EXPRESSION (send_gencmd || boot_send_gencmd)
-----1----- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T19,T27,T12 |
1 | 0 | Covered | T3,T8,T7 |
LINE 492
EXPRESSION (((!edn_enable_fo[CsrngCmdReqValidOut])) ? '0 : ((send_rescmd || send_gencmd || (boot_send_gencmd && cmd_sent)) ? 1'b1 : cs_cmd_req_vld_q))
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 492
SUB-EXPRESSION ((send_rescmd || send_gencmd || (boot_send_gencmd && cmd_sent)) ? 1'b1 : cs_cmd_req_vld_q)
-------------------------------1------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T19,T27 |
LINE 492
SUB-EXPRESSION (send_rescmd || send_gencmd || (boot_send_gencmd && cmd_sent))
-----1----- -----2----- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T19,T27,T12 |
0 | 1 | 0 | Covered | T3,T8,T7 |
1 | 0 | 0 | Covered | T3,T8,T9 |
LINE 492
SUB-EXPRESSION (boot_send_gencmd && cmd_sent)
--------1------- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T8,T7 |
1 | 0 | Covered | T12,T67,T102 |
1 | 1 | Covered | T19,T27,T12 |
LINE 501
EXPRESSION (((!sw_cmd_req_load)) && sw_rdy_sts_q)
----------1--------- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 502
EXPRESSION
Number Term
1 ((!edn_enable_q)) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (auto_first_ack_wait ? 1'b1 : (main_sm_busy ? 1'b0 : (csrng_cmd_i.csrng_req_ready ? 1'b1 : sw_rdy_sts_q)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 502
SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : (auto_first_ack_wait ? 1'b1 : (main_sm_busy ? 1'b0 : (csrng_cmd_i.csrng_req_ready ? 1'b1 : sw_rdy_sts_q))))
-------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 502
SUB-EXPRESSION (auto_first_ack_wait ? 1'b1 : (main_sm_busy ? 1'b0 : (csrng_cmd_i.csrng_req_ready ? 1'b1 : sw_rdy_sts_q)))
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T6 |
LINE 502
SUB-EXPRESSION (main_sm_busy ? 1'b0 : (csrng_cmd_i.csrng_req_ready ? 1'b1 : sw_rdy_sts_q))
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T19,T4 |
LINE 502
SUB-EXPRESSION (csrng_cmd_i.csrng_req_ready ? 1'b1 : sw_rdy_sts_q)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 514
EXPRESSION (csrng_cmd_ack && intr_sts_gate_q)
------1------ -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T19,T27 |
1 | 1 | Covered | T1,T2,T3 |
LINE 518
EXPRESSION (((!edn_enable_fo[IntrStatus])) ? 1'b0 : (main_sm_done_pulse ? 1'b1 : (auto_set_intr_gate ? 1'b1 : (auto_clr_intr_gate ? 1'b0 : intr_sts_gate_q))))
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 518
SUB-EXPRESSION (main_sm_done_pulse ? 1'b1 : (auto_set_intr_gate ? 1'b1 : (auto_clr_intr_gate ? 1'b0 : intr_sts_gate_q)))
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 518
SUB-EXPRESSION (auto_set_intr_gate ? 1'b1 : (auto_clr_intr_gate ? 1'b0 : intr_sts_gate_q))
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T6 |
LINE 518
SUB-EXPRESSION (auto_clr_intr_gate ? 1'b0 : intr_sts_gate_q)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T6,T8 |
LINE 548
EXPRESSION ((send_rescmd_q & edn_enable_fo[SendReseedCmd]) ? 1'b1 : reseed_cmd_load)
-----------------------1----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T8,T9 |
LINE 548
SUB-EXPRESSION (send_rescmd_q & edn_enable_fo[SendReseedCmd])
------1------ --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T103,T104 |
1 | 1 | Covered | T3,T8,T9 |
LINE 552
EXPRESSION (auto_req_mode_busy ? cs_cmd_req_out_q : reseed_cmd_bus)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T6,T8 |
LINE 558
EXPRESSION (cmd_fifo_rst_fo[1] || main_sm_done_pulse)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T13,T14 |
LINE 560
SUB-EXPRESSION (sfifo_rescmd_push && sfifo_rescmd_full)
--------1-------- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T7,T9,T68 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T86 |
LINE 560
SUB-EXPRESSION (sfifo_rescmd_pop && ((!sfifo_rescmd_not_empty)))
--------1------- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T8,T9 |
1 | 1 | Covered | T82,T84,T87 |
LINE 560
SUB-EXPRESSION (sfifo_rescmd_full && ((!sfifo_rescmd_not_empty)))
--------1-------- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T7,T9,T68 |
1 | 1 | Covered | T83,T90,T91 |
LINE 588
EXPRESSION ((boot_wr_cmd_genfifo & edn_enable_fo[SendGenCmd]) ? 1'b1 : ((send_gencmd_q & edn_enable_fo[SendGenCmd]) ? 1'b1 : generate_cmd_load))
------------------------1------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T19,T27,T12 |
LINE 588
SUB-EXPRESSION (boot_wr_cmd_genfifo & edn_enable_fo[SendGenCmd])
---------1--------- ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T19,T27,T12 |
LINE 588
SUB-EXPRESSION ((send_gencmd_q & edn_enable_fo[SendGenCmd]) ? 1'b1 : generate_cmd_load)
---------------------1---------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T8,T7 |
LINE 588
SUB-EXPRESSION (send_gencmd_q & edn_enable_fo[SendGenCmd])
------1------ ------------2------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T8,T7 |
LINE 593
EXPRESSION (boot_wr_cmd_genfifo ? boot_gen_cmd : (auto_req_mode_busy ? cs_cmd_req_out_q : generate_cmd_bus))
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T19,T27,T12 |
LINE 593
SUB-EXPRESSION (auto_req_mode_busy ? cs_cmd_req_out_q : generate_cmd_bus)
---------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T6,T8 |
LINE 598
EXPRESSION (send_gencmd || boot_send_gencmd)
-----1----- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T19,T27,T12 |
1 | 0 | Covered | T3,T8,T7 |
LINE 600
EXPRESSION (cmd_fifo_rst_fo[2] || main_sm_done_pulse)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T13,T14 |
LINE 602
SUB-EXPRESSION (sfifo_gencmd_push && sfifo_gencmd_full)
--------1-------- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T6 |
1 | 0 | Covered | T3,T19,T4 |
1 | 1 | Covered | T85 |
LINE 602
SUB-EXPRESSION (sfifo_gencmd_pop && ((!sfifo_gencmd_not_empty)))
--------1------- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T19,T27 |
1 | 1 | Covered | T61,T80,T81 |
LINE 602
SUB-EXPRESSION (sfifo_gencmd_full && ((!sfifo_gencmd_not_empty)))
--------1-------- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T88,T89,T85 |
LINE 634
EXPRESSION (sfifo_output_not_empty && csrng_cmd_i.csrng_req_ready)
-----------1---------- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 636
SUB-EXPRESSION (sfifo_output_push && sfifo_output_full)
--------1-------- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Not Covered | |
LINE 636
SUB-EXPRESSION (sfifo_output_pop && ((!sfifo_output_not_empty)))
--------1------- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Not Covered | |
LINE 636
SUB-EXPRESSION (sfifo_output_full && ((!sfifo_output_not_empty)))
--------1-------- -------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 680
EXPRESSION (send_gencmd && cmd_sent)
-----1----- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T19,T27 |
1 | 0 | Covered | T3,T8,T7 |
1 | 1 | Covered | T3,T8,T7 |
LINE 695
EXPRESSION (max_reqs_between_reseed_load || (send_rescmd && cmd_sent) || main_sm_done_pulse)
--------------1------------- ------------2------------ ---------3--------
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T3,T8,T9 |
1 | 0 | 0 | Covered | T3,T4,T6 |
LINE 695
SUB-EXPRESSION (send_rescmd && cmd_sent)
-----1----- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T19,T27 |
1 | 0 | Covered | T3,T8,T9 |
1 | 1 | Covered | T3,T8,T9 |
LINE 699
EXPRESSION (max_reqs_cnt == '0)
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 702
EXPRESSION
Number Term
1 ((!edn_enable_fo[CmdFifoCnt])) ? '0 : ((cmd_fifo_rst_fo[3] || main_sm_done_pulse) ? '0 : (capt_gencmd_fifo_cnt ? sfifo_gencmd_depth : (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((send_gencmd || boot_send_gencmd || send_rescmd) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q)))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 702
SUB-EXPRESSION
Number Term
1 (cmd_fifo_rst_fo[3] || main_sm_done_pulse) ? '0 : (capt_gencmd_fifo_cnt ? sfifo_gencmd_depth : (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((send_gencmd || boot_send_gencmd || send_rescmd) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 702
SUB-EXPRESSION (cmd_fifo_rst_fo[3] || main_sm_done_pulse)
---------1-------- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T13,T14,T15 |
LINE 702
SUB-EXPRESSION
Number Term
1 capt_gencmd_fifo_cnt ? sfifo_gencmd_depth : (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((send_gencmd || boot_send_gencmd || send_rescmd) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q)))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T19,T27 |
LINE 702
SUB-EXPRESSION (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((send_gencmd || boot_send_gencmd || send_rescmd) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q))
----------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T8,T7 |
LINE 702
SUB-EXPRESSION ((send_gencmd || boot_send_gencmd || send_rescmd) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q)
------------------------1-----------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T19,T27 |
LINE 702
SUB-EXPRESSION (send_gencmd || boot_send_gencmd || send_rescmd)
-----1----- --------2------- -----3-----
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T3,T8,T9 |
0 | 1 | 0 | Covered | T19,T27,T12 |
1 | 0 | 0 | Covered | T3,T8,T7 |
LINE 710
EXPRESSION (cmd_fifo_cnt_q == 4'(1))
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T19,T27 |
LINE 756
EXPRESSION (((!packer_ep_rvalid[0])) && edn_i[0].edn_req)
------------1----------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 756
EXPRESSION (((!packer_ep_rvalid[1])) && edn_i[1].edn_req)
------------1----------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T18,T25,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T18,T25,T8 |
LINE 756
EXPRESSION (((!packer_ep_rvalid[2])) && edn_i[2].edn_req)
------------1----------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T14,T19,T25 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T14,T19,T25 |
LINE 756
EXPRESSION (((!packer_ep_rvalid[3])) && edn_i[3].edn_req)
------------1----------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T13,T25 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T13,T25 |
LINE 756
EXPRESSION (((!packer_ep_rvalid[4])) && edn_i[4].edn_req)
------------1----------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T25,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T25,T8 |
LINE 756
EXPRESSION (((!packer_ep_rvalid[5])) && edn_i[5].edn_req)
------------1----------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T25,T8,T26 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T25,T8,T26 |
LINE 756
EXPRESSION (((!packer_ep_rvalid[6])) && edn_i[6].edn_req)
------------1----------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T25,T8,T26 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T25,T8 |
LINE 787
EXPRESSION (((!edn_enable_fo[CsrngFipsEn])) ? 1'b0 : ((packer_cs_push && packer_cs_wready) ? csrng_cmd_i.genbits_fips : csrng_fips_q))
---------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 787
SUB-EXPRESSION ((packer_cs_push && packer_cs_wready) ? csrng_cmd_i.genbits_fips : csrng_fips_q)
------------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 787
SUB-EXPRESSION (packer_cs_push && packer_cs_wready)
-------1------ --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 802
EXPRESSION (packer_cs_rvalid && packer_cs_rready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T13,T18 |
1 | 1 | Covered | T1,T2,T3 |
LINE 804
EXPRESSION (cs_rdata_capt_vld ? packer_cs_rdata[63:0] : cs_rdata_capt_q)
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 806
EXPRESSION (((!edn_enable_fo[CsrngDataVld])) ? 1'b0 : (cs_rdata_capt_vld ? 1'b1 : cs_rdata_capt_vld_q))
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 806
SUB-EXPRESSION (cs_rdata_capt_vld ? 1'b1 : cs_rdata_capt_vld_q)
--------1--------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 812
EXPRESSION (cs_rdata_capt_vld && cs_rdata_capt_vld_q && (cs_rdata_capt_q == packer_cs_rdata[63:0]))
--------1-------- ---------2--------- ---------------------3--------------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T2,T3,T18 |
1 | 1 | 1 | Covered | T13,T14,T15 |
LINE 812
SUB-EXPRESSION (cs_rdata_capt_q == packer_cs_rdata[63:0])
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 855
EXPRESSION (packer_arb_valid && packer_ep_wready[0] && packer_arb_gnt[0])
--------1------- ---------2--------- --------3--------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 855
EXPRESSION (packer_arb_valid && packer_ep_wready[1] && packer_arb_gnt[1])
--------1------- ---------2--------- --------3--------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T18,T25,T8 |
LINE 855
EXPRESSION (packer_arb_valid && packer_ep_wready[2] && packer_arb_gnt[2])
--------1------- ---------2--------- --------3--------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T14,T19,T25 |
LINE 855
EXPRESSION (packer_arb_valid && packer_ep_wready[3] && packer_arb_gnt[3])
--------1------- ---------2--------- --------3--------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T3,T13,T25 |
LINE 855
EXPRESSION (packer_arb_valid && packer_ep_wready[4] && packer_arb_gnt[4])
--------1------- ---------2--------- --------3--------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T3,T25,T8 |
LINE 855
EXPRESSION (packer_arb_valid && packer_ep_wready[5] && packer_arb_gnt[5])
--------1------- ---------2--------- --------3--------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T25,T8,T26 |
LINE 855
EXPRESSION (packer_arb_valid && packer_ep_wready[6] && packer_arb_gnt[6])
--------1------- ---------2--------- --------3--------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Covered | T1,T2,T3 |
1 | 1 | 1 | Covered | T25,T8,T26 |
LINE 859
EXPRESSION (packer_ep_clr[0] ? 1'b0 : ((packer_ep_push[0] && packer_ep_wready[0]) ? csrng_fips_q : edn_fips_q[0]))
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 859
SUB-EXPRESSION ((packer_ep_push[0] && packer_ep_wready[0]) ? csrng_fips_q : edn_fips_q[0])
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 859
SUB-EXPRESSION (packer_ep_push[0] && packer_ep_wready[0])
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 859
EXPRESSION (packer_ep_clr[1] ? 1'b0 : ((packer_ep_push[1] && packer_ep_wready[1]) ? csrng_fips_q : edn_fips_q[1]))
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 859
SUB-EXPRESSION ((packer_ep_push[1] && packer_ep_wready[1]) ? csrng_fips_q : edn_fips_q[1])
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T18,T25,T8 |
LINE 859
SUB-EXPRESSION (packer_ep_push[1] && packer_ep_wready[1])
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T18,T25,T8 |
LINE 859
EXPRESSION (packer_ep_clr[2] ? 1'b0 : ((packer_ep_push[2] && packer_ep_wready[2]) ? csrng_fips_q : edn_fips_q[2]))
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 859
SUB-EXPRESSION ((packer_ep_push[2] && packer_ep_wready[2]) ? csrng_fips_q : edn_fips_q[2])
---------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T14,T19,T25 |