| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.62 | 99.02 | 92.32 | 96.79 | 91.45 | 98.62 | 99.77 | 98.39 |
| T775 | /workspace/coverage/default/36.edn_disable_auto_req_mode.1070996698 | Jan 17 01:38:48 PM PST 24 | Jan 17 01:38:49 PM PST 24 | 199749218 ps | ||
| T776 | /workspace/coverage/default/9.edn_stress_all.3368727289 | Jan 17 01:36:47 PM PST 24 | Jan 17 01:36:54 PM PST 24 | 172314667 ps | ||
| T121 | /workspace/coverage/default/14.edn_err.4070843485 | Jan 17 01:37:06 PM PST 24 | Jan 17 01:37:09 PM PST 24 | 19376879 ps | ||
| T127 | /workspace/coverage/default/21.edn_disable.1456369754 | Jan 17 01:37:39 PM PST 24 | Jan 17 01:37:42 PM PST 24 | 11553042 ps | ||
| T777 | /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2414738175 | Jan 17 01:35:20 PM PST 24 | Jan 17 01:45:18 PM PST 24 | 68720911004 ps | ||
| T283 | /workspace/coverage/default/72.edn_genbits.1855481500 | Jan 17 01:39:56 PM PST 24 | Jan 17 01:39:58 PM PST 24 | 22977391 ps | ||
| T778 | /workspace/coverage/default/59.edn_err.1718790133 | Jan 17 01:39:45 PM PST 24 | Jan 17 01:39:51 PM PST 24 | 22632197 ps | ||
| T779 | /workspace/coverage/default/26.edn_stress_all.3312867002 | Jan 17 01:38:05 PM PST 24 | Jan 17 01:38:09 PM PST 24 | 77530742 ps | ||
| T780 | /workspace/coverage/default/27.edn_smoke.1785476717 | Jan 17 01:38:08 PM PST 24 | Jan 17 01:38:10 PM PST 24 | 26275680 ps | ||
| T106 | /workspace/coverage/default/39.edn_disable.911358118 | Jan 17 01:38:57 PM PST 24 | Jan 17 01:39:01 PM PST 24 | 10463570 ps | ||
| T781 | /workspace/coverage/default/264.edn_genbits.1852925486 | Jan 17 01:41:16 PM PST 24 | Jan 17 01:41:20 PM PST 24 | 19705433 ps | ||
| T782 | /workspace/coverage/default/20.edn_smoke.4136724997 | Jan 17 01:37:49 PM PST 24 | Jan 17 01:37:51 PM PST 24 | 49918457 ps | ||
| T276 | /workspace/coverage/default/216.edn_genbits.1245641009 | Jan 17 01:40:57 PM PST 24 | Jan 17 01:40:59 PM PST 24 | 17271512 ps | ||
| T783 | /workspace/coverage/default/11.edn_alert.18721125 | Jan 17 01:37:00 PM PST 24 | Jan 17 01:37:01 PM PST 24 | 228886064 ps | ||
| T784 | /workspace/coverage/default/17.edn_genbits.3505903977 | Jan 17 01:37:16 PM PST 24 | Jan 17 01:37:18 PM PST 24 | 54980575 ps | ||
| T785 | /workspace/coverage/default/292.edn_genbits.738836230 | Jan 17 01:41:20 PM PST 24 | Jan 17 01:41:28 PM PST 24 | 25764040 ps | ||
| T786 | /workspace/coverage/default/258.edn_genbits.365500794 | Jan 17 01:41:14 PM PST 24 | Jan 17 01:41:18 PM PST 24 | 127710167 ps | ||
| T184 | /workspace/coverage/default/24.edn_err.2479696249 | Jan 17 01:37:57 PM PST 24 | Jan 17 01:37:59 PM PST 24 | 34835696 ps | ||
| T303 | /workspace/coverage/default/45.edn_alert.4215685154 | Jan 17 01:39:40 PM PST 24 | Jan 17 01:39:49 PM PST 24 | 29412270 ps | ||
| T787 | /workspace/coverage/default/28.edn_alert.2165477878 | Jan 17 01:38:23 PM PST 24 | Jan 17 01:38:25 PM PST 24 | 20400508 ps | ||
| T788 | /workspace/coverage/default/3.edn_regwen.4224192548 | Jan 17 01:35:52 PM PST 24 | Jan 17 01:35:53 PM PST 24 | 44763489 ps | ||
| T789 | /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1501911648 | Jan 17 01:37:30 PM PST 24 | Jan 17 01:43:20 PM PST 24 | 16508965640 ps | ||
| T790 | /workspace/coverage/default/7.edn_stress_all.3887670762 | Jan 17 01:36:28 PM PST 24 | Jan 17 01:36:32 PM PST 24 | 190319074 ps | ||
| T791 | /workspace/coverage/default/37.edn_intr.4173961607 | Jan 17 01:38:58 PM PST 24 | Jan 17 01:39:01 PM PST 24 | 19186403 ps | ||
| T792 | /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2517025229 | Jan 17 01:39:34 PM PST 24 | Jan 17 02:10:28 PM PST 24 | 299723182364 ps | ||
| T793 | /workspace/coverage/default/190.edn_genbits.2618866731 | Jan 17 01:40:41 PM PST 24 | Jan 17 01:40:46 PM PST 24 | 118288226 ps | ||
| T794 | /workspace/coverage/default/180.edn_genbits.3452998769 | Jan 17 01:40:41 PM PST 24 | Jan 17 01:40:45 PM PST 24 | 35087046 ps | ||
| T795 | /workspace/coverage/default/116.edn_genbits.2066579345 | Jan 17 01:40:27 PM PST 24 | Jan 17 01:40:29 PM PST 24 | 53178099 ps | ||
| T796 | /workspace/coverage/default/282.edn_genbits.1483283522 | Jan 17 01:41:16 PM PST 24 | Jan 17 01:41:20 PM PST 24 | 13110769 ps | ||
| T797 | /workspace/coverage/default/5.edn_genbits.448968952 | Jan 17 01:36:07 PM PST 24 | Jan 17 01:36:12 PM PST 24 | 260027043 ps | ||
| T798 | /workspace/coverage/default/8.edn_alert_test.2813553359 | Jan 17 01:36:37 PM PST 24 | Jan 17 01:36:39 PM PST 24 | 143214030 ps | ||
| T799 | /workspace/coverage/default/47.edn_disable.849103398 | Jan 17 01:39:43 PM PST 24 | Jan 17 01:39:51 PM PST 24 | 45479625 ps | ||
| T800 | /workspace/coverage/default/123.edn_genbits.1692776195 | Jan 17 01:40:32 PM PST 24 | Jan 17 01:40:34 PM PST 24 | 15872737 ps | ||
| T801 | /workspace/coverage/default/45.edn_alert_test.80425203 | Jan 17 01:39:30 PM PST 24 | Jan 17 01:39:32 PM PST 24 | 59098892 ps | ||
| T802 | /workspace/coverage/default/37.edn_alert.32795302 | Jan 17 01:38:56 PM PST 24 | Jan 17 01:38:59 PM PST 24 | 18651624 ps | ||
| T803 | /workspace/coverage/default/247.edn_genbits.107372255 | Jan 17 01:41:13 PM PST 24 | Jan 17 01:41:17 PM PST 24 | 28997442 ps | ||
| T804 | /workspace/coverage/default/18.edn_stress_all.3345818301 | Jan 17 01:37:23 PM PST 24 | Jan 17 01:37:26 PM PST 24 | 535124415 ps | ||
| T805 | /workspace/coverage/default/245.edn_genbits.2818194904 | Jan 17 01:41:08 PM PST 24 | Jan 17 01:41:10 PM PST 24 | 26141021 ps | ||
| T806 | /workspace/coverage/default/59.edn_genbits.902071827 | Jan 17 01:39:42 PM PST 24 | Jan 17 01:39:51 PM PST 24 | 14949448 ps | ||
| T807 | /workspace/coverage/default/0.edn_intr.1048579587 | Jan 17 01:35:18 PM PST 24 | Jan 17 01:35:24 PM PST 24 | 27947493 ps | ||
| T808 | /workspace/coverage/default/14.edn_smoke.2482199179 | Jan 17 01:37:06 PM PST 24 | Jan 17 01:37:08 PM PST 24 | 14177142 ps | ||
| T809 | /workspace/coverage/default/31.edn_err.381254148 | Jan 17 01:38:34 PM PST 24 | Jan 17 01:38:36 PM PST 24 | 18922783 ps | ||
| T810 | /workspace/coverage/default/205.edn_genbits.3475455445 | Jan 17 01:40:59 PM PST 24 | Jan 17 01:41:03 PM PST 24 | 96820180 ps | ||
| T811 | /workspace/coverage/default/3.edn_smoke.2522350187 | Jan 17 01:35:59 PM PST 24 | Jan 17 01:36:01 PM PST 24 | 13583535 ps | ||
| T812 | /workspace/coverage/default/9.edn_err.3328038378 | Jan 17 01:36:47 PM PST 24 | Jan 17 01:36:51 PM PST 24 | 28251990 ps | ||
| T813 | /workspace/coverage/default/12.edn_smoke.3757052794 | Jan 17 01:36:48 PM PST 24 | Jan 17 01:36:51 PM PST 24 | 21745684 ps | ||
| T814 | /workspace/coverage/default/63.edn_genbits.1950312783 | Jan 17 01:39:48 PM PST 24 | Jan 17 01:39:52 PM PST 24 | 17820774 ps | ||
| T815 | /workspace/coverage/default/29.edn_genbits.1341861943 | Jan 17 01:38:25 PM PST 24 | Jan 17 01:38:32 PM PST 24 | 36012716 ps | ||
| T816 | /workspace/coverage/default/248.edn_genbits.3550470255 | Jan 17 01:41:12 PM PST 24 | Jan 17 01:41:16 PM PST 24 | 17789807 ps | ||
| T817 | /workspace/coverage/default/111.edn_genbits.719177091 | Jan 17 01:40:28 PM PST 24 | Jan 17 01:40:30 PM PST 24 | 17753364 ps | ||
| T818 | /workspace/coverage/default/86.edn_err.2556284987 | Jan 17 01:40:23 PM PST 24 | Jan 17 01:40:26 PM PST 24 | 32872625 ps | ||
| T819 | /workspace/coverage/default/219.edn_genbits.2312904779 | Jan 17 01:41:01 PM PST 24 | Jan 17 01:41:05 PM PST 24 | 15077966 ps | ||
| T820 | /workspace/coverage/default/50.edn_genbits.3352598597 | Jan 17 01:39:42 PM PST 24 | Jan 17 01:39:51 PM PST 24 | 81715377 ps | ||
| T821 | /workspace/coverage/default/14.edn_alert.1093663834 | Jan 17 01:37:09 PM PST 24 | Jan 17 01:37:15 PM PST 24 | 69838135 ps | ||
| T822 | /workspace/coverage/default/81.edn_genbits.2526853553 | Jan 17 01:40:17 PM PST 24 | Jan 17 01:40:25 PM PST 24 | 205527178 ps | ||
| T284 | /workspace/coverage/default/33.edn_genbits.3046030526 | Jan 17 01:38:36 PM PST 24 | Jan 17 01:38:38 PM PST 24 | 79015318 ps | ||
| T823 | /workspace/coverage/default/26.edn_err.4221250397 | Jan 17 01:38:10 PM PST 24 | Jan 17 01:38:11 PM PST 24 | 40298316 ps | ||
| T85 | /workspace/coverage/default/10.edn_intr.1035728902 | Jan 17 01:36:51 PM PST 24 | Jan 17 01:36:53 PM PST 24 | 20344203 ps | ||
| T159 | /workspace/coverage/default/49.edn_err.1721712220 | Jan 17 01:39:42 PM PST 24 | Jan 17 01:39:50 PM PST 24 | 36069163 ps | ||
| T824 | /workspace/coverage/default/46.edn_intr.2545710292 | Jan 17 01:39:29 PM PST 24 | Jan 17 01:39:30 PM PST 24 | 33351311 ps | ||
| T825 | /workspace/coverage/default/40.edn_alert_test.1881308031 | Jan 17 01:39:17 PM PST 24 | Jan 17 01:39:20 PM PST 24 | 16107047 ps | ||
| T826 | /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3531161759 | Jan 17 01:38:58 PM PST 24 | Jan 17 01:48:42 PM PST 24 | 25936057052 ps | ||
| T827 | /workspace/coverage/default/230.edn_genbits.1185552638 | Jan 17 01:41:16 PM PST 24 | Jan 17 01:41:19 PM PST 24 | 33855593 ps | ||
| T828 | /workspace/coverage/default/117.edn_genbits.3547630355 | Jan 17 01:40:31 PM PST 24 | Jan 17 01:40:33 PM PST 24 | 13842995 ps | ||
| T829 | /workspace/coverage/default/85.edn_genbits.1664605178 | Jan 17 01:40:28 PM PST 24 | Jan 17 01:40:30 PM PST 24 | 80627159 ps | ||
| T830 | /workspace/coverage/default/38.edn_genbits.2480151769 | Jan 17 01:38:54 PM PST 24 | Jan 17 01:40:06 PM PST 24 | 2265363070 ps | ||
| T831 | /workspace/coverage/default/105.edn_genbits.4216100889 | Jan 17 01:40:28 PM PST 24 | Jan 17 01:40:30 PM PST 24 | 33128158 ps | ||
| T832 | /workspace/coverage/default/66.edn_err.3843931283 | Jan 17 01:39:52 PM PST 24 | Jan 17 01:39:54 PM PST 24 | 19435189 ps | ||
| T833 | /workspace/coverage/default/287.edn_genbits.3593689735 | Jan 17 01:41:19 PM PST 24 | Jan 17 01:41:30 PM PST 24 | 118742143 ps | ||
| T834 | /workspace/coverage/default/67.edn_err.1012765678 | Jan 17 01:39:48 PM PST 24 | Jan 17 01:39:53 PM PST 24 | 60351993 ps | ||
| T140 | /workspace/coverage/default/28.edn_disable.1259571920 | Jan 17 01:38:21 PM PST 24 | Jan 17 01:38:24 PM PST 24 | 10777142 ps | ||
| T86 | /workspace/coverage/default/5.edn_intr.843072840 | Jan 17 01:36:08 PM PST 24 | Jan 17 01:36:10 PM PST 24 | 20392404 ps | ||
| T835 | /workspace/coverage/default/15.edn_stress_all.2387437227 | Jan 17 01:37:08 PM PST 24 | Jan 17 01:37:16 PM PST 24 | 164642625 ps | ||
| T836 | /workspace/coverage/default/4.edn_disable_auto_req_mode.3507610313 | Jan 17 01:36:10 PM PST 24 | Jan 17 01:36:17 PM PST 24 | 96237324 ps | ||
| T837 | /workspace/coverage/default/70.edn_genbits.1238203402 | Jan 17 01:39:57 PM PST 24 | Jan 17 01:39:59 PM PST 24 | 51491828 ps | ||
| T838 | /workspace/coverage/default/0.edn_smoke.4045128981 | Jan 17 01:35:12 PM PST 24 | Jan 17 01:35:15 PM PST 24 | 13318706 ps | ||
| T839 | /workspace/coverage/default/195.edn_genbits.4248959131 | Jan 17 01:40:41 PM PST 24 | Jan 17 01:40:45 PM PST 24 | 16977367 ps | ||
| T840 | /workspace/coverage/default/22.edn_genbits.1360020634 | Jan 17 01:37:48 PM PST 24 | Jan 17 01:37:51 PM PST 24 | 48889841 ps | ||
| T296 | /workspace/coverage/default/168.edn_genbits.1927799148 | Jan 17 01:40:41 PM PST 24 | Jan 17 01:40:45 PM PST 24 | 67346338 ps | ||
| T841 | /workspace/coverage/default/102.edn_genbits.1815196463 | Jan 17 01:40:31 PM PST 24 | Jan 17 01:40:33 PM PST 24 | 35413003 ps | ||
| T842 | /workspace/coverage/default/71.edn_genbits.2896067055 | Jan 17 01:39:55 PM PST 24 | Jan 17 01:39:57 PM PST 24 | 66862316 ps | ||
| T843 | /workspace/coverage/default/81.edn_err.3553228612 | Jan 17 01:40:16 PM PST 24 | Jan 17 01:40:24 PM PST 24 | 62053616 ps | ||
| T844 | /workspace/coverage/default/40.edn_alert.2575457754 | Jan 17 01:39:07 PM PST 24 | Jan 17 01:39:09 PM PST 24 | 28377701 ps | ||
| T845 | /workspace/coverage/default/3.edn_disable.1052439512 | Jan 17 01:36:01 PM PST 24 | Jan 17 01:36:03 PM PST 24 | 12434921 ps | ||
| T846 | /workspace/coverage/default/169.edn_genbits.3077246389 | Jan 17 01:40:39 PM PST 24 | Jan 17 01:40:43 PM PST 24 | 57311735 ps | ||
| T847 | /workspace/coverage/default/237.edn_genbits.1482926740 | Jan 17 01:41:10 PM PST 24 | Jan 17 01:41:12 PM PST 24 | 38570808 ps | ||
| T848 | /workspace/coverage/default/87.edn_genbits.1155309495 | Jan 17 01:40:22 PM PST 24 | Jan 17 01:40:25 PM PST 24 | 59760039 ps | ||
| T849 | /workspace/coverage/default/15.edn_genbits.504656131 | Jan 17 01:37:07 PM PST 24 | Jan 17 01:37:09 PM PST 24 | 58274405 ps | ||
| T850 | /workspace/coverage/default/29.edn_alert.23673282 | Jan 17 01:38:33 PM PST 24 | Jan 17 01:38:34 PM PST 24 | 30517297 ps | ||
| T851 | /workspace/coverage/default/39.edn_intr.1055864060 | Jan 17 01:38:55 PM PST 24 | Jan 17 01:38:58 PM PST 24 | 26212518 ps | ||
| T852 | /workspace/coverage/default/18.edn_genbits.1734205760 | Jan 17 01:37:20 PM PST 24 | Jan 17 01:37:22 PM PST 24 | 14414570 ps | ||
| T853 | /workspace/coverage/default/118.edn_genbits.1449752711 | Jan 17 01:40:33 PM PST 24 | Jan 17 01:40:35 PM PST 24 | 120096839 ps | ||
| T854 | /workspace/coverage/default/234.edn_genbits.2776529401 | Jan 17 01:41:08 PM PST 24 | Jan 17 01:41:09 PM PST 24 | 38577618 ps | ||
| T855 | /workspace/coverage/default/76.edn_genbits.2658116513 | Jan 17 01:40:09 PM PST 24 | Jan 17 01:40:13 PM PST 24 | 120097067 ps | ||
| T856 | /workspace/coverage/default/35.edn_alert_test.2058250552 | Jan 17 01:38:49 PM PST 24 | Jan 17 01:38:50 PM PST 24 | 18430758 ps | ||
| T857 | /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3724795168 | Jan 17 01:39:35 PM PST 24 | Jan 17 01:52:26 PM PST 24 | 90057497536 ps | ||
| T858 | /workspace/coverage/default/51.edn_err.350155600 | Jan 17 01:39:43 PM PST 24 | Jan 17 01:39:51 PM PST 24 | 24433106 ps | ||
| T859 | /workspace/coverage/default/35.edn_disable.2337719894 | Jan 17 01:38:50 PM PST 24 | Jan 17 01:38:51 PM PST 24 | 38135308 ps | ||
| T860 | /workspace/coverage/default/181.edn_genbits.831995198 | Jan 17 01:40:48 PM PST 24 | Jan 17 01:40:54 PM PST 24 | 29124696 ps | ||
| T861 | /workspace/coverage/default/263.edn_genbits.2166980958 | Jan 17 01:41:18 PM PST 24 | Jan 17 01:41:28 PM PST 24 | 54080471 ps | ||
| T862 | /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2383590630 | Jan 17 01:37:57 PM PST 24 | Jan 17 01:57:11 PM PST 24 | 103551358794 ps | ||
| T863 | /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2752725128 | Jan 17 01:38:36 PM PST 24 | Jan 17 02:05:54 PM PST 24 | 110559860799 ps | ||
| T864 | /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3114986570 | Jan 17 01:38:52 PM PST 24 | Jan 17 01:41:52 PM PST 24 | 102443406182 ps | ||
| T865 | /workspace/coverage/default/131.edn_genbits.2982260881 | Jan 17 01:40:43 PM PST 24 | Jan 17 01:40:53 PM PST 24 | 37673701 ps | ||
| T866 | /workspace/coverage/default/187.edn_genbits.2286378144 | Jan 17 01:40:46 PM PST 24 | Jan 17 01:40:54 PM PST 24 | 37140886 ps | ||
| T867 | /workspace/coverage/default/119.edn_genbits.2969637120 | Jan 17 01:40:32 PM PST 24 | Jan 17 01:40:34 PM PST 24 | 16117784 ps | ||
| T868 | /workspace/coverage/default/40.edn_intr.649634546 | Jan 17 01:39:11 PM PST 24 | Jan 17 01:39:13 PM PST 24 | 34120833 ps | ||
| T869 | /workspace/coverage/default/94.edn_genbits.785910675 | Jan 17 01:40:20 PM PST 24 | Jan 17 01:40:24 PM PST 24 | 13724025 ps | ||
| T870 | /workspace/coverage/default/40.edn_stress_all.3668212397 | Jan 17 01:39:08 PM PST 24 | Jan 17 01:39:09 PM PST 24 | 142432497 ps | ||
| T871 | /workspace/coverage/default/5.edn_smoke.687958604 | Jan 17 01:36:07 PM PST 24 | Jan 17 01:36:10 PM PST 24 | 11455527 ps | ||
| T872 | /workspace/coverage/default/55.edn_genbits.1069036223 | Jan 17 01:39:43 PM PST 24 | Jan 17 01:39:51 PM PST 24 | 42288859 ps | ||
| T873 | /workspace/coverage/default/268.edn_genbits.1877645990 | Jan 17 01:41:20 PM PST 24 | Jan 17 01:41:28 PM PST 24 | 60957051 ps | ||
| T874 | /workspace/coverage/default/30.edn_err.2559417494 | Jan 17 01:38:21 PM PST 24 | Jan 17 01:38:24 PM PST 24 | 22823954 ps | ||
| T875 | /workspace/coverage/default/49.edn_disable_auto_req_mode.1553138047 | Jan 17 01:39:43 PM PST 24 | Jan 17 01:39:51 PM PST 24 | 96147372 ps | ||
| T876 | /workspace/coverage/default/155.edn_genbits.3891723974 | Jan 17 01:40:40 PM PST 24 | Jan 17 01:40:44 PM PST 24 | 46903938 ps | ||
| T877 | /workspace/coverage/default/192.edn_genbits.643130784 | Jan 17 01:40:44 PM PST 24 | Jan 17 01:40:53 PM PST 24 | 118291943 ps | ||
| T878 | /workspace/coverage/default/40.edn_err.2188356566 | Jan 17 01:39:08 PM PST 24 | Jan 17 01:39:10 PM PST 24 | 24344605 ps | ||
| T879 | /workspace/coverage/default/231.edn_genbits.23691611 | Jan 17 01:41:11 PM PST 24 | Jan 17 01:41:17 PM PST 24 | 82048866 ps | ||
| T880 | /workspace/coverage/default/11.edn_alert_test.3255898720 | Jan 17 01:36:49 PM PST 24 | Jan 17 01:36:51 PM PST 24 | 14717007 ps | ||
| T881 | /workspace/coverage/default/73.edn_err.259751797 | Jan 17 01:40:00 PM PST 24 | Jan 17 01:40:02 PM PST 24 | 46716503 ps | ||
| T882 | /workspace/coverage/default/44.edn_genbits.1409224526 | Jan 17 01:39:43 PM PST 24 | Jan 17 01:39:53 PM PST 24 | 167635783 ps | ||
| T160 | /workspace/coverage/default/4.edn_err.885480833 | Jan 17 01:36:05 PM PST 24 | Jan 17 01:36:07 PM PST 24 | 24376928 ps | ||
| T883 | /workspace/coverage/default/182.edn_genbits.3838951810 | Jan 17 01:40:44 PM PST 24 | Jan 17 01:40:54 PM PST 24 | 23041055 ps | ||
| T884 | /workspace/coverage/default/86.edn_genbits.1304809518 | Jan 17 01:40:18 PM PST 24 | Jan 17 01:40:24 PM PST 24 | 67783804 ps | ||
| T885 | /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1336294531 | Jan 17 01:38:00 PM PST 24 | Jan 17 01:48:47 PM PST 24 | 115905571644 ps | ||
| T886 | /workspace/coverage/default/30.edn_disable_auto_req_mode.3234925798 | Jan 17 01:38:27 PM PST 24 | Jan 17 01:38:31 PM PST 24 | 32970382 ps | ||
| T887 | /workspace/coverage/default/6.edn_genbits.2169020536 | Jan 17 01:36:09 PM PST 24 | Jan 17 01:36:17 PM PST 24 | 33069784 ps | ||
| T888 | /workspace/coverage/default/17.edn_intr.1909915741 | Jan 17 01:37:24 PM PST 24 | Jan 17 01:37:27 PM PST 24 | 25000983 ps | ||
| T889 | /workspace/coverage/default/72.edn_err.411977001 | Jan 17 01:39:59 PM PST 24 | Jan 17 01:40:00 PM PST 24 | 23524634 ps | ||
| T890 | /workspace/coverage/default/8.edn_smoke.2574530253 | Jan 17 01:36:22 PM PST 24 | Jan 17 01:36:23 PM PST 24 | 13483059 ps | ||
| T891 | /workspace/coverage/default/199.edn_genbits.2223772992 | Jan 17 01:40:49 PM PST 24 | Jan 17 01:40:54 PM PST 24 | 40141406 ps | ||
| T892 | /workspace/coverage/default/35.edn_smoke.3663502195 | Jan 17 01:38:41 PM PST 24 | Jan 17 01:38:44 PM PST 24 | 35166075 ps | ||
| T893 | /workspace/coverage/default/60.edn_err.1645760308 | Jan 17 01:39:52 PM PST 24 | Jan 17 01:39:54 PM PST 24 | 28693708 ps | ||
| T894 | /workspace/coverage/default/27.edn_disable_auto_req_mode.2466489383 | Jan 17 01:38:36 PM PST 24 | Jan 17 01:38:38 PM PST 24 | 38769713 ps | ||
| T895 | /workspace/coverage/default/19.edn_genbits.2934354218 | Jan 17 01:37:38 PM PST 24 | Jan 17 01:37:42 PM PST 24 | 30260125 ps | ||
| T896 | /workspace/coverage/default/126.edn_genbits.2912487347 | Jan 17 01:40:40 PM PST 24 | Jan 17 01:40:44 PM PST 24 | 89021570 ps | ||
| T897 | /workspace/coverage/default/14.edn_genbits.1244892423 | Jan 17 01:37:07 PM PST 24 | Jan 17 01:37:09 PM PST 24 | 51268491 ps | ||
| T898 | /workspace/coverage/default/2.edn_alert_test.4052920658 | Jan 17 01:35:52 PM PST 24 | Jan 17 01:35:53 PM PST 24 | 25529980 ps | ||
| T899 | /workspace/coverage/default/283.edn_genbits.2579875392 | Jan 17 01:41:20 PM PST 24 | Jan 17 01:41:28 PM PST 24 | 47330201 ps | ||
| T900 | /workspace/coverage/default/244.edn_genbits.3295941841 | Jan 17 01:41:08 PM PST 24 | Jan 17 01:41:10 PM PST 24 | 75698539 ps | ||
| T901 | /workspace/coverage/default/152.edn_genbits.3205721872 | Jan 17 01:40:38 PM PST 24 | Jan 17 01:40:42 PM PST 24 | 56353898 ps | ||
| T129 | /workspace/coverage/default/28.edn_err.1161775567 | Jan 17 01:38:33 PM PST 24 | Jan 17 01:38:35 PM PST 24 | 73242064 ps | ||
| T902 | /workspace/coverage/default/1.edn_alert.2678039953 | Jan 17 01:35:23 PM PST 24 | Jan 17 01:35:25 PM PST 24 | 35273402 ps | ||
| T903 | /workspace/coverage/default/12.edn_alert_test.4089014102 | Jan 17 01:37:02 PM PST 24 | Jan 17 01:37:05 PM PST 24 | 94468717 ps | ||
| T904 | /workspace/coverage/default/28.edn_genbits.2206540542 | Jan 17 01:38:31 PM PST 24 | Jan 17 01:38:32 PM PST 24 | 14339769 ps | ||
| T905 | /workspace/coverage/default/47.edn_err.2658507743 | Jan 17 01:39:34 PM PST 24 | Jan 17 01:39:39 PM PST 24 | 70477692 ps | ||
| T104 | /workspace/coverage/default/21.edn_disable_auto_req_mode.244559564 | Jan 17 01:37:39 PM PST 24 | Jan 17 01:37:42 PM PST 24 | 17264581 ps | ||
| T906 | /workspace/coverage/default/196.edn_genbits.1831707121 | Jan 17 01:40:45 PM PST 24 | Jan 17 01:40:53 PM PST 24 | 46991781 ps | ||
| T907 | /workspace/coverage/default/30.edn_genbits.1220669766 | Jan 17 01:38:34 PM PST 24 | Jan 17 01:38:36 PM PST 24 | 82393204 ps | ||
| T908 | /workspace/coverage/default/41.edn_disable_auto_req_mode.2590083879 | Jan 17 01:39:28 PM PST 24 | Jan 17 01:39:29 PM PST 24 | 208239314 ps | ||
| T909 | /workspace/coverage/default/257.edn_genbits.3014744071 | Jan 17 01:41:14 PM PST 24 | Jan 17 01:41:18 PM PST 24 | 49414099 ps | ||
| T910 | /workspace/coverage/default/272.edn_genbits.2168202774 | Jan 17 01:41:13 PM PST 24 | Jan 17 01:41:18 PM PST 24 | 34936763 ps | ||
| T179 | /workspace/coverage/default/52.edn_err.1702132397 | Jan 17 01:39:43 PM PST 24 | Jan 17 01:39:51 PM PST 24 | 33001524 ps | ||
| T911 | /workspace/coverage/default/10.edn_disable_auto_req_mode.794607198 | Jan 17 01:37:00 PM PST 24 | Jan 17 01:37:02 PM PST 24 | 29101438 ps | ||
| T912 | /workspace/coverage/default/35.edn_disable_auto_req_mode.2810653491 | Jan 17 01:38:50 PM PST 24 | Jan 17 01:38:52 PM PST 24 | 15384633 ps | ||
| T913 | /workspace/coverage/default/32.edn_intr.3629726468 | Jan 17 01:38:32 PM PST 24 | Jan 17 01:38:34 PM PST 24 | 19691408 ps | ||
| T50 | /workspace/coverage/default/0.edn_sec_cm.1617280871 | Jan 17 01:35:17 PM PST 24 | Jan 17 01:35:29 PM PST 24 | 676766824 ps | ||
| T914 | /workspace/coverage/default/4.edn_stress_all.2173474592 | Jan 17 01:36:00 PM PST 24 | Jan 17 01:36:04 PM PST 24 | 108603435 ps | ||
| T915 | /workspace/coverage/default/22.edn_alert_test.1754688893 | Jan 17 01:38:01 PM PST 24 | Jan 17 01:38:04 PM PST 24 | 20704817 ps | ||
| T916 | /workspace/coverage/default/41.edn_intr.1517046862 | Jan 17 01:39:31 PM PST 24 | Jan 17 01:39:33 PM PST 24 | 24941102 ps | ||
| T917 | /workspace/coverage/default/0.edn_genbits.3128117984 | Jan 17 01:35:09 PM PST 24 | Jan 17 01:35:11 PM PST 24 | 53977216 ps | ||
| T918 | /workspace/coverage/default/165.edn_genbits.4106795788 | Jan 17 01:40:44 PM PST 24 | Jan 17 01:40:53 PM PST 24 | 24024359 ps | ||
| T919 | /workspace/coverage/default/120.edn_genbits.3238655409 | Jan 17 01:40:38 PM PST 24 | Jan 17 01:40:42 PM PST 24 | 53510579 ps | ||
| T920 | /workspace/coverage/default/159.edn_genbits.2767307685 | Jan 17 01:40:38 PM PST 24 | Jan 17 01:40:42 PM PST 24 | 40772374 ps | ||
| T921 | /workspace/coverage/default/32.edn_alert.2630362990 | Jan 17 01:38:35 PM PST 24 | Jan 17 01:38:36 PM PST 24 | 58595973 ps | ||
| T922 | /workspace/coverage/default/80.edn_err.3874139432 | Jan 17 01:40:18 PM PST 24 | Jan 17 01:40:24 PM PST 24 | 43870805 ps | ||
| T923 | /workspace/coverage/default/17.edn_alert_test.2137490959 | Jan 17 01:37:22 PM PST 24 | Jan 17 01:37:25 PM PST 24 | 42425379 ps | ||
| T924 | /workspace/coverage/default/296.edn_genbits.2936837094 | Jan 17 01:41:25 PM PST 24 | Jan 17 01:41:28 PM PST 24 | 56903423 ps | ||
| T925 | /workspace/coverage/default/22.edn_intr.1295763894 | Jan 17 01:37:47 PM PST 24 | Jan 17 01:37:51 PM PST 24 | 19430487 ps | ||
| T926 | /workspace/coverage/default/79.edn_err.2493940296 | Jan 17 01:40:17 PM PST 24 | Jan 17 01:40:24 PM PST 24 | 35432425 ps | ||
| T927 | /workspace/coverage/default/261.edn_genbits.2833131268 | Jan 17 01:41:08 PM PST 24 | Jan 17 01:41:10 PM PST 24 | 16465096 ps | ||
| T928 | /workspace/coverage/default/235.edn_genbits.2742013085 | Jan 17 01:41:14 PM PST 24 | Jan 17 01:41:18 PM PST 24 | 17468084 ps | ||
| T929 | /workspace/coverage/default/62.edn_genbits.3685635190 | Jan 17 01:39:47 PM PST 24 | Jan 17 01:39:51 PM PST 24 | 22490369 ps | ||
| T930 | /workspace/coverage/default/4.edn_smoke.3661948753 | Jan 17 01:35:59 PM PST 24 | Jan 17 01:36:01 PM PST 24 | 20058847 ps | ||
| T931 | /workspace/coverage/default/76.edn_err.3678233509 | Jan 17 01:40:08 PM PST 24 | Jan 17 01:40:10 PM PST 24 | 32517863 ps | ||
| T932 | /workspace/coverage/default/74.edn_genbits.3654307437 | Jan 17 01:39:58 PM PST 24 | Jan 17 01:39:59 PM PST 24 | 29529255 ps | ||
| T933 | /workspace/coverage/default/24.edn_smoke.537539496 | Jan 17 01:38:06 PM PST 24 | Jan 17 01:38:08 PM PST 24 | 45584937 ps | ||
| T934 | /workspace/coverage/default/42.edn_genbits.2403222859 | Jan 17 01:39:27 PM PST 24 | Jan 17 01:39:28 PM PST 24 | 47663366 ps | ||
| T935 | /workspace/coverage/default/262.edn_genbits.3362239795 | Jan 17 01:41:18 PM PST 24 | Jan 17 01:41:28 PM PST 24 | 37436845 ps | ||
| T936 | /workspace/coverage/default/295.edn_genbits.3813716547 | Jan 17 01:41:19 PM PST 24 | Jan 17 01:41:30 PM PST 24 | 72070106 ps | ||
| T937 | /workspace/coverage/default/46.edn_stress_all_with_rand_reset.487258556 | Jan 17 01:39:29 PM PST 24 | Jan 17 02:05:55 PM PST 24 | 131710461524 ps | ||
| T938 | /workspace/coverage/default/83.edn_err.340474512 | Jan 17 01:40:24 PM PST 24 | Jan 17 01:40:26 PM PST 24 | 20910633 ps | ||
| T939 | /workspace/coverage/default/12.edn_err.3987816602 | Jan 17 01:37:01 PM PST 24 | Jan 17 01:37:04 PM PST 24 | 44652061 ps | ||
| T940 | /workspace/coverage/default/16.edn_disable_auto_req_mode.3956095170 | Jan 17 01:37:11 PM PST 24 | Jan 17 01:37:15 PM PST 24 | 34913627 ps | ||
| T941 | /workspace/coverage/default/18.edn_disable_auto_req_mode.2573499307 | Jan 17 01:37:38 PM PST 24 | Jan 17 01:37:42 PM PST 24 | 98222815 ps | ||
| T942 | /workspace/coverage/default/227.edn_genbits.3174770221 | Jan 17 01:41:12 PM PST 24 | Jan 17 01:41:19 PM PST 24 | 129272476 ps | ||
| T943 | /workspace/coverage/default/109.edn_genbits.3168143093 | Jan 17 01:40:25 PM PST 24 | Jan 17 01:40:27 PM PST 24 | 53202480 ps | ||
| T944 | /workspace/coverage/default/32.edn_disable.2915448643 | Jan 17 01:38:43 PM PST 24 | Jan 17 01:38:45 PM PST 24 | 14906639 ps | ||
| T945 | /workspace/coverage/default/95.edn_genbits.1430386700 | Jan 17 01:40:24 PM PST 24 | Jan 17 01:40:26 PM PST 24 | 18803222 ps | ||
| T946 | /workspace/coverage/default/16.edn_intr.3798273801 | Jan 17 01:37:21 PM PST 24 | Jan 17 01:37:22 PM PST 24 | 27219201 ps | ||
| T947 | /workspace/coverage/default/251.edn_genbits.1646248295 | Jan 17 01:41:09 PM PST 24 | Jan 17 01:41:11 PM PST 24 | 16528421 ps | ||
| T948 | /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2033989401 | Jan 17 01:37:38 PM PST 24 | Jan 17 02:24:59 PM PST 24 | 461700879657 ps | ||
| T949 | /workspace/coverage/default/30.edn_smoke.3874760508 | Jan 17 01:38:34 PM PST 24 | Jan 17 01:38:35 PM PST 24 | 17910940 ps | ||
| T149 | /workspace/coverage/default/18.edn_disable.2490995784 | Jan 17 01:37:29 PM PST 24 | Jan 17 01:37:30 PM PST 24 | 22479649 ps | ||
| T950 | /workspace/coverage/default/16.edn_genbits.3276486284 | Jan 17 01:37:23 PM PST 24 | Jan 17 01:37:26 PM PST 24 | 38497094 ps | ||
| T951 | /workspace/coverage/default/260.edn_genbits.23207218 | Jan 17 01:41:16 PM PST 24 | Jan 17 01:41:19 PM PST 24 | 72644616 ps | ||
| T265 | /workspace/coverage/default/178.edn_genbits.1409627198 | Jan 17 01:40:44 PM PST 24 | Jan 17 01:40:53 PM PST 24 | 24863726 ps | ||
| T952 | /workspace/coverage/default/229.edn_genbits.1149199561 | Jan 17 01:41:10 PM PST 24 | Jan 17 01:41:12 PM PST 24 | 15984467 ps | ||
| T953 | /workspace/coverage/default/49.edn_stress_all_with_rand_reset.193497937 | Jan 17 01:39:40 PM PST 24 | Jan 17 01:50:37 PM PST 24 | 27807788890 ps | ||
| T142 | /workspace/coverage/default/10.edn_disable.2800165976 | Jan 17 01:36:59 PM PST 24 | Jan 17 01:37:00 PM PST 24 | 14633364 ps | ||
| T954 | /workspace/coverage/default/12.edn_intr.523330875 | Jan 17 01:37:04 PM PST 24 | Jan 17 01:37:07 PM PST 24 | 31528619 ps | ||
| T955 | /workspace/coverage/default/2.edn_intr.1274069269 | Jan 17 01:35:46 PM PST 24 | Jan 17 01:35:52 PM PST 24 | 19949618 ps | ||
| T956 | /workspace/coverage/default/13.edn_disable_auto_req_mode.840411884 | Jan 17 01:37:05 PM PST 24 | Jan 17 01:37:08 PM PST 24 | 56377167 ps | ||
| T957 | /workspace/coverage/default/7.edn_stress_all_with_rand_reset.533642607 | Jan 17 01:36:26 PM PST 24 | Jan 17 02:12:58 PM PST 24 | 701017224989 ps | ||
| T958 | /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1278043458 | Jan 17 01:38:54 PM PST 24 | Jan 17 02:12:10 PM PST 24 | 378242449548 ps | ||
| T959 | /workspace/coverage/default/275.edn_genbits.3558882339 | Jan 17 01:41:20 PM PST 24 | Jan 17 01:41:28 PM PST 24 | 35573334 ps | ||
| T960 | /workspace/coverage/default/53.edn_err.1005917985 | Jan 17 01:39:41 PM PST 24 | Jan 17 01:39:50 PM PST 24 | 32626634 ps | ||
| T961 | /workspace/coverage/default/139.edn_genbits.3403811628 | Jan 17 01:40:41 PM PST 24 | Jan 17 01:40:46 PM PST 24 | 24177102 ps | ||
| T962 | /workspace/coverage/default/33.edn_alert_test.2352854533 | Jan 17 01:38:43 PM PST 24 | Jan 17 01:38:45 PM PST 24 | 50356231 ps | ||
| T963 | /workspace/coverage/default/4.edn_alert.2352358642 | Jan 17 01:36:08 PM PST 24 | Jan 17 01:36:10 PM PST 24 | 30603341 ps | ||
| T964 | /workspace/coverage/default/291.edn_genbits.233260842 | Jan 17 01:41:18 PM PST 24 | Jan 17 01:41:28 PM PST 24 | 42024274 ps | ||
| T965 | /workspace/coverage/default/284.edn_genbits.3824584004 | Jan 17 01:41:19 PM PST 24 | Jan 17 01:41:28 PM PST 24 | 50055549 ps | ||
| T966 | /workspace/coverage/default/26.edn_genbits.3669108712 | Jan 17 01:38:05 PM PST 24 | Jan 17 01:38:08 PM PST 24 | 13867623 ps | ||
| T967 | /workspace/coverage/default/46.edn_stress_all.70577112 | Jan 17 01:39:33 PM PST 24 | Jan 17 01:39:42 PM PST 24 | 714833005 ps | ||
| T968 | /workspace/coverage/default/238.edn_genbits.2351575993 | Jan 17 01:41:14 PM PST 24 | Jan 17 01:41:18 PM PST 24 | 26007611 ps | ||
| T969 | /workspace/coverage/default/34.edn_err.1340237791 | Jan 17 01:38:43 PM PST 24 | Jan 17 01:38:45 PM PST 24 | 35625138 ps | ||
| T970 | /workspace/coverage/default/34.edn_disable_auto_req_mode.1233558064 | Jan 17 01:38:48 PM PST 24 | Jan 17 01:38:49 PM PST 24 | 51734679 ps | ||
| T971 | /workspace/coverage/default/121.edn_genbits.277608929 | Jan 17 01:40:32 PM PST 24 | Jan 17 01:40:34 PM PST 24 | 13829212 ps | ||
| T135 | /workspace/coverage/default/23.edn_disable_auto_req_mode.1047070839 | Jan 17 01:37:57 PM PST 24 | Jan 17 01:37:59 PM PST 24 | 269071185 ps | ||
| T972 | /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1588336625 | Jan 17 01:37:47 PM PST 24 | Jan 17 01:54:26 PM PST 24 | 123006402638 ps | ||
| T973 | /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3068489928 | Jan 17 01:36:51 PM PST 24 | Jan 17 01:43:53 PM PST 24 | 17131550287 ps | ||
| T974 | /workspace/coverage/default/8.edn_genbits.2487778510 | Jan 17 01:36:28 PM PST 24 | Jan 17 01:36:33 PM PST 24 | 68954102 ps | ||
| T975 | /workspace/coverage/default/79.edn_genbits.3523142191 | Jan 17 01:40:20 PM PST 24 | Jan 17 01:40:24 PM PST 24 | 47744559 ps | ||
| T147 | /workspace/coverage/default/44.edn_disable.2577684729 | Jan 17 01:39:43 PM PST 24 | Jan 17 01:39:51 PM PST 24 | 65213849 ps | ||
| T976 | /workspace/coverage/default/45.edn_smoke.273845873 | Jan 17 01:39:30 PM PST 24 | Jan 17 01:39:32 PM PST 24 | 25260571 ps | ||
| T977 | /workspace/coverage/default/32.edn_smoke.4288469507 | Jan 17 01:38:32 PM PST 24 | Jan 17 01:38:33 PM PST 24 | 27404964 ps | ||
| T312 | /workspace/coverage/default/2.edn_regwen.2730638882 | Jan 17 01:35:47 PM PST 24 | Jan 17 01:35:52 PM PST 24 | 23944000 ps | ||
| T978 | /workspace/coverage/default/164.edn_genbits.1816999759 | Jan 17 01:40:39 PM PST 24 | Jan 17 01:40:43 PM PST 24 | 33582501 ps | ||
| T979 | /workspace/coverage/default/75.edn_genbits.3104128880 | Jan 17 01:40:07 PM PST 24 | Jan 17 01:40:10 PM PST 24 | 98617180 ps |
| Test location | /workspace/coverage/default/18.edn_stress_all_with_rand_reset.4149710661 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 108245133936 ps |
| CPU time | 475.38 seconds |
| Started | Jan 17 01:37:22 PM PST 24 |
| Finished | Jan 17 01:45:18 PM PST 24 |
| Peak memory | 215844 kb |
| Host | smart-65a0f05c-32b9-45e3-9e0b-f21a924a069e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149710661 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.4149710661 |
| Directory | /workspace/18.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/77.edn_genbits.3145497201 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 219236295 ps |
| CPU time | 2.41 seconds |
| Started | Jan 17 01:40:07 PM PST 24 |
| Finished | Jan 17 01:40:10 PM PST 24 |
| Peak memory | 214216 kb |
| Host | smart-ff6c5dde-65b5-455a-9228-56ee5d3577b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3145497201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3145497201 |
| Directory | /workspace/77.edn_genbits/latest |
| Test location | /workspace/coverage/default/50.edn_err.873273151 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 46888686 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:39:43 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 221592 kb |
| Host | smart-c350043c-b72c-43f5-918f-33566824b6aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=873273151 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.873273151 |
| Directory | /workspace/50.edn_err/latest |
| Test location | /workspace/coverage/default/2.edn_sec_cm.4067488416 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 816576683 ps |
| CPU time | 6.75 seconds |
| Started | Jan 17 01:35:49 PM PST 24 |
| Finished | Jan 17 01:35:58 PM PST 24 |
| Peak memory | 233916 kb |
| Host | smart-1bf00566-c13e-4ef6-9558-da6919c69a89 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067488416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.4067488416 |
| Directory | /workspace/2.edn_sec_cm/latest |
| Test location | /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3331774490 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 169524911 ps |
| CPU time | 1.57 seconds |
| Started | Jan 17 12:31:28 PM PST 24 |
| Finished | Jan 17 12:31:35 PM PST 24 |
| Peak memory | 206284 kb |
| Host | smart-e537dce4-6ab1-49ca-9843-34f43d5040da |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331774490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3331774490 |
| Directory | /workspace/11.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.edn_disable.2820177289 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 45929529 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:35:20 PM PST 24 |
| Finished | Jan 17 01:35:24 PM PST 24 |
| Peak memory | 213972 kb |
| Host | smart-aaf9f577-adcf-4f05-aaa1-b6c5178556c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820177289 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2820177289 |
| Directory | /workspace/0.edn_disable/latest |
| Test location | /workspace/coverage/default/1.edn_sec_cm.2753936398 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 201975533 ps |
| CPU time | 3.74 seconds |
| Started | Jan 17 01:35:30 PM PST 24 |
| Finished | Jan 17 01:35:35 PM PST 24 |
| Peak memory | 231888 kb |
| Host | smart-58ee953d-8f8c-46bd-af99-3c9a4761ff60 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753936398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2753936398 |
| Directory | /workspace/1.edn_sec_cm/latest |
| Test location | /workspace/coverage/default/24.edn_stress_all_with_rand_reset.220158713 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 148919700702 ps |
| CPU time | 945.07 seconds |
| Started | Jan 17 01:38:07 PM PST 24 |
| Finished | Jan 17 01:53:54 PM PST 24 |
| Peak memory | 217464 kb |
| Host | smart-9f45578b-e568-4d27-b56d-47b1d689dd41 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220158713 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.220158713 |
| Directory | /workspace/24.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/14.edn_disable_auto_req_mode.1019415145 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 26852025 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:37:08 PM PST 24 |
| Finished | Jan 17 01:37:15 PM PST 24 |
| Peak memory | 214496 kb |
| Host | smart-88bdfeac-107b-4527-a170-420a9ec6cc7a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019415145 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d isable_auto_req_mode.1019415145 |
| Directory | /workspace/14.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/8.edn_alert.2682175894 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 126045600 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:36:27 PM PST 24 |
| Finished | Jan 17 01:36:31 PM PST 24 |
| Peak memory | 205876 kb |
| Host | smart-db081501-e306-422d-a8c6-3700d7f92c96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2682175894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2682175894 |
| Directory | /workspace/8.edn_alert/latest |
| Test location | /workspace/coverage/default/6.edn_err.2325100195 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 42046838 ps |
| CPU time | 1.18 seconds |
| Started | Jan 17 01:36:28 PM PST 24 |
| Finished | Jan 17 01:36:31 PM PST 24 |
| Peak memory | 217028 kb |
| Host | smart-bd7d797f-fc40-4a36-b709-decc9f4274e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2325100195 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2325100195 |
| Directory | /workspace/6.edn_err/latest |
| Test location | /workspace/coverage/default/10.edn_intr.1035728902 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 20344203 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:36:51 PM PST 24 |
| Finished | Jan 17 01:36:53 PM PST 24 |
| Peak memory | 214448 kb |
| Host | smart-521928b7-e0db-4aae-9259-1fd4473417f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1035728902 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1035728902 |
| Directory | /workspace/10.edn_intr/latest |
| Test location | /workspace/coverage/default/208.edn_genbits.4155518318 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 164315066 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:40:50 PM PST 24 |
| Finished | Jan 17 01:40:54 PM PST 24 |
| Peak memory | 205352 kb |
| Host | smart-42c47171-f4ec-484c-bd70-8e52eb0815be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4155518318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.4155518318 |
| Directory | /workspace/208.edn_genbits/latest |
| Test location | /workspace/coverage/default/46.edn_disable.3741085406 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 14000852 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 01:39:37 PM PST 24 |
| Finished | Jan 17 01:39:40 PM PST 24 |
| Peak memory | 214488 kb |
| Host | smart-c308dee6-8ffc-4e11-84ae-4a3c74036768 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741085406 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3741085406 |
| Directory | /workspace/46.edn_disable/latest |
| Test location | /workspace/coverage/default/49.edn_disable.3048932290 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 13967003 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:39:45 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 214664 kb |
| Host | smart-be4164f8-e4ca-4402-95c8-2b89cd9f093d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048932290 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3048932290 |
| Directory | /workspace/49.edn_disable/latest |
| Test location | /workspace/coverage/default/15.edn_disable_auto_req_mode.2903979302 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 47966047 ps |
| CPU time | 1.05 seconds |
| Started | Jan 17 01:37:21 PM PST 24 |
| Finished | Jan 17 01:37:23 PM PST 24 |
| Peak memory | 214396 kb |
| Host | smart-48dfdc7e-61b5-4193-8044-0fd71656bdf0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903979302 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d isable_auto_req_mode.2903979302 |
| Directory | /workspace/15.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/cover_reg_top/12.edn_csr_rw.684941249 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 11425881 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 12:31:31 PM PST 24 |
| Finished | Jan 17 12:31:37 PM PST 24 |
| Peak memory | 205996 kb |
| Host | smart-3cefc48b-a7bc-4666-8b27-3878f71537ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684941249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.684941249 |
| Directory | /workspace/12.edn_csr_rw/latest |
| Test location | /workspace/coverage/default/36.edn_intr.3043920034 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 17728348 ps |
| CPU time | 1.16 seconds |
| Started | Jan 17 01:38:49 PM PST 24 |
| Finished | Jan 17 01:38:51 PM PST 24 |
| Peak memory | 225760 kb |
| Host | smart-47fdec84-0f33-4625-bdb3-bd9b3d5f6019 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3043920034 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.3043920034 |
| Directory | /workspace/36.edn_intr/latest |
| Test location | /workspace/coverage/default/0.edn_regwen.2380086742 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 29160289 ps |
| CPU time | 0.84 seconds |
| Started | Jan 17 01:35:15 PM PST 24 |
| Finished | Jan 17 01:35:23 PM PST 24 |
| Peak memory | 204872 kb |
| Host | smart-96ef0b17-1cea-4bed-b223-fc286ec475bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2380086742 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2380086742 |
| Directory | /workspace/0.edn_regwen/latest |
| Test location | /workspace/coverage/default/20.edn_disable.2687240288 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 17020269 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:37:37 PM PST 24 |
| Finished | Jan 17 01:37:40 PM PST 24 |
| Peak memory | 214328 kb |
| Host | smart-d2fbcd76-9c63-4284-9eef-f0b7adf3d21b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687240288 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2687240288 |
| Directory | /workspace/20.edn_disable/latest |
| Test location | /workspace/coverage/default/22.edn_disable_auto_req_mode.4165588611 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 49692042 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 01:38:02 PM PST 24 |
| Finished | Jan 17 01:38:07 PM PST 24 |
| Peak memory | 214472 kb |
| Host | smart-99800143-e02d-4e5f-bd7b-37ea1a44b91f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165588611 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d isable_auto_req_mode.4165588611 |
| Directory | /workspace/22.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/31.edn_disable.3961039284 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 10725017 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:38:37 PM PST 24 |
| Finished | Jan 17 01:38:38 PM PST 24 |
| Peak memory | 214352 kb |
| Host | smart-7246c08f-8582-4102-bb4a-459435dbae4d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961039284 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3961039284 |
| Directory | /workspace/31.edn_disable/latest |
| Test location | /workspace/coverage/default/124.edn_genbits.140778274 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 47045072 ps |
| CPU time | 1.06 seconds |
| Started | Jan 17 01:40:33 PM PST 24 |
| Finished | Jan 17 01:40:35 PM PST 24 |
| Peak memory | 214068 kb |
| Host | smart-a5e9b492-811b-4de5-aa1d-5405e6a3a942 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=140778274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.140778274 |
| Directory | /workspace/124.edn_genbits/latest |
| Test location | /workspace/coverage/default/6.edn_disable_auto_req_mode.813417553 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 29445499 ps |
| CPU time | 1.07 seconds |
| Started | Jan 17 01:36:22 PM PST 24 |
| Finished | Jan 17 01:36:24 PM PST 24 |
| Peak memory | 214456 kb |
| Host | smart-9023ca66-5e98-4d37-91c9-152a016105d9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813417553 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis able_auto_req_mode.813417553 |
| Directory | /workspace/6.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/48.edn_genbits.3821955552 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 53685572 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:39:44 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 205052 kb |
| Host | smart-57771c99-49a7-48c5-9908-cd0a3444cc32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3821955552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3821955552 |
| Directory | /workspace/48.edn_genbits/latest |
| Test location | /workspace/coverage/cover_reg_top/10.edn_tl_errors.3619214242 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 482333163 ps |
| CPU time | 4.09 seconds |
| Started | Jan 17 12:31:15 PM PST 24 |
| Finished | Jan 17 12:31:23 PM PST 24 |
| Peak memory | 214272 kb |
| Host | smart-e99c4797-ef32-4c80-9ae5-1402e4c92c09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619214242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3619214242 |
| Directory | /workspace/10.edn_tl_errors/latest |
| Test location | /workspace/coverage/default/1.edn_disable.3055876922 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 66790611 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:35:33 PM PST 24 |
| Finished | Jan 17 01:35:35 PM PST 24 |
| Peak memory | 214292 kb |
| Host | smart-ed76257a-7928-4f5c-8cb1-f4180eb0a72c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055876922 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3055876922 |
| Directory | /workspace/1.edn_disable/latest |
| Test location | /workspace/coverage/default/21.edn_disable_auto_req_mode.244559564 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 17264581 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:37:39 PM PST 24 |
| Finished | Jan 17 01:37:42 PM PST 24 |
| Peak memory | 214500 kb |
| Host | smart-bdee517c-829e-4c73-b210-83ac8f72993b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244559564 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di sable_auto_req_mode.244559564 |
| Directory | /workspace/21.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/39.edn_disable.911358118 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 10463570 ps |
| CPU time | 0.9 seconds |
| Started | Jan 17 01:38:57 PM PST 24 |
| Finished | Jan 17 01:39:01 PM PST 24 |
| Peak memory | 214328 kb |
| Host | smart-00d94c0d-8f3d-4501-b922-5ba83df32eaf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911358118 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.911358118 |
| Directory | /workspace/39.edn_disable/latest |
| Test location | /workspace/coverage/default/249.edn_genbits.699483665 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 42878015 ps |
| CPU time | 1.23 seconds |
| Started | Jan 17 01:41:07 PM PST 24 |
| Finished | Jan 17 01:41:09 PM PST 24 |
| Peak memory | 214208 kb |
| Host | smart-cc998da2-e8e6-4416-b8cc-02239e1852c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=699483665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.699483665 |
| Directory | /workspace/249.edn_genbits/latest |
| Test location | /workspace/coverage/default/18.edn_disable_auto_req_mode.2573499307 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 98222815 ps |
| CPU time | 1.09 seconds |
| Started | Jan 17 01:37:38 PM PST 24 |
| Finished | Jan 17 01:37:42 PM PST 24 |
| Peak memory | 214532 kb |
| Host | smart-e7fa95ca-804a-4f4d-b72c-f149dcdc96f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573499307 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d isable_auto_req_mode.2573499307 |
| Directory | /workspace/18.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/2.edn_disable.1488281202 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 19152334 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:35:55 PM PST 24 |
| Finished | Jan 17 01:35:57 PM PST 24 |
| Peak memory | 214372 kb |
| Host | smart-bd0d4a41-150c-40d1-b0ab-dc1f00bbef12 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488281202 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1488281202 |
| Directory | /workspace/2.edn_disable/latest |
| Test location | /workspace/coverage/default/23.edn_disable_auto_req_mode.1047070839 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 269071185 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:37:57 PM PST 24 |
| Finished | Jan 17 01:37:59 PM PST 24 |
| Peak memory | 214548 kb |
| Host | smart-d05610cb-5bcc-4a20-a121-f26e0bb0fba5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047070839 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d isable_auto_req_mode.1047070839 |
| Directory | /workspace/23.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/34.edn_stress_all_with_rand_reset.366985761 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 413862195209 ps |
| CPU time | 2367.78 seconds |
| Started | Jan 17 01:38:40 PM PST 24 |
| Finished | Jan 17 02:18:11 PM PST 24 |
| Peak memory | 225004 kb |
| Host | smart-f1688efc-0f8b-42af-acdd-e225564df19d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366985761 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.366985761 |
| Directory | /workspace/34.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.edn_regwen.4128774013 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 13540180 ps |
| CPU time | 0.91 seconds |
| Started | Jan 17 01:36:26 PM PST 24 |
| Finished | Jan 17 01:36:28 PM PST 24 |
| Peak memory | 204848 kb |
| Host | smart-591ac235-97c1-41cf-888e-7d9f49e5d63e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4128774013 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.4128774013 |
| Directory | /workspace/7.edn_regwen/latest |
| Test location | /workspace/coverage/default/0.edn_alert.3413422890 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 19159190 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:35:16 PM PST 24 |
| Finished | Jan 17 01:35:24 PM PST 24 |
| Peak memory | 205144 kb |
| Host | smart-850d3af2-177e-426c-a874-e3f81b097786 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3413422890 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3413422890 |
| Directory | /workspace/0.edn_alert/latest |
| Test location | /workspace/coverage/default/16.edn_alert.3303436020 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 31799170 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:37:21 PM PST 24 |
| Finished | Jan 17 01:37:23 PM PST 24 |
| Peak memory | 205876 kb |
| Host | smart-1a224894-e951-440d-a130-5e13750a9368 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3303436020 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3303436020 |
| Directory | /workspace/16.edn_alert/latest |
| Test location | /workspace/coverage/default/17.edn_alert.1788460655 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 20422045 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:37:38 PM PST 24 |
| Finished | Jan 17 01:37:41 PM PST 24 |
| Peak memory | 205932 kb |
| Host | smart-4b6d2f70-f4e9-4f11-bf8f-50db5a3a05a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1788460655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1788460655 |
| Directory | /workspace/17.edn_alert/latest |
| Test location | /workspace/coverage/default/122.edn_genbits.409172371 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 21100352 ps |
| CPU time | 1.07 seconds |
| Started | Jan 17 01:40:33 PM PST 24 |
| Finished | Jan 17 01:40:35 PM PST 24 |
| Peak memory | 205148 kb |
| Host | smart-ba139ba2-2895-4f29-82b9-3dea92d78377 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=409172371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.409172371 |
| Directory | /workspace/122.edn_genbits/latest |
| Test location | /workspace/coverage/default/201.edn_genbits.1206376360 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 28755404 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:40:51 PM PST 24 |
| Finished | Jan 17 01:40:54 PM PST 24 |
| Peak memory | 205580 kb |
| Host | smart-f424c5f5-c05f-4052-8970-25a857df851c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1206376360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1206376360 |
| Directory | /workspace/201.edn_genbits/latest |
| Test location | /workspace/coverage/default/213.edn_genbits.2025880131 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 25195895 ps |
| CPU time | 1.11 seconds |
| Started | Jan 17 01:41:01 PM PST 24 |
| Finished | Jan 17 01:41:05 PM PST 24 |
| Peak memory | 214120 kb |
| Host | smart-f188b055-ad96-4ea8-b8a3-248c152d2588 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2025880131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2025880131 |
| Directory | /workspace/213.edn_genbits/latest |
| Test location | /workspace/coverage/default/216.edn_genbits.1245641009 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 17271512 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:40:57 PM PST 24 |
| Finished | Jan 17 01:40:59 PM PST 24 |
| Peak memory | 204716 kb |
| Host | smart-ff1ebf69-2c0c-4c01-9a80-b56fe9491603 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1245641009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1245641009 |
| Directory | /workspace/216.edn_genbits/latest |
| Test location | /workspace/coverage/default/279.edn_genbits.3347045551 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 134068958 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:41:18 PM PST 24 |
| Finished | Jan 17 01:41:27 PM PST 24 |
| Peak memory | 205332 kb |
| Host | smart-6d998318-52d8-495f-a4ba-612e143a9e43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3347045551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3347045551 |
| Directory | /workspace/279.edn_genbits/latest |
| Test location | /workspace/coverage/default/106.edn_genbits.937597442 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 16095904 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:40:26 PM PST 24 |
| Finished | Jan 17 01:40:28 PM PST 24 |
| Peak memory | 204984 kb |
| Host | smart-50f2fec1-7156-42a4-9690-3f4c438a48b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=937597442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.937597442 |
| Directory | /workspace/106.edn_genbits/latest |
| Test location | /workspace/coverage/default/177.edn_genbits.1752388503 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 19314440 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:40:42 PM PST 24 |
| Finished | Jan 17 01:40:46 PM PST 24 |
| Peak memory | 205088 kb |
| Host | smart-078bb339-831b-4a82-9052-954e67b88247 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1752388503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1752388503 |
| Directory | /workspace/177.edn_genbits/latest |
| Test location | /workspace/coverage/default/250.edn_genbits.1702654032 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 33339536 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:41:16 PM PST 24 |
| Finished | Jan 17 01:41:20 PM PST 24 |
| Peak memory | 205416 kb |
| Host | smart-f63c19e3-c254-40b0-9777-08d0ba3a2e3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1702654032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1702654032 |
| Directory | /workspace/250.edn_genbits/latest |
| Test location | /workspace/coverage/default/259.edn_genbits.3372218956 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 67307208 ps |
| CPU time | 2.78 seconds |
| Started | Jan 17 01:41:11 PM PST 24 |
| Finished | Jan 17 01:41:17 PM PST 24 |
| Peak memory | 214152 kb |
| Host | smart-809e1e3b-faff-4bca-8b5d-eaf59c1c420e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3372218956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3372218956 |
| Directory | /workspace/259.edn_genbits/latest |
| Test location | /workspace/coverage/default/276.edn_genbits.3812570186 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 17003000 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:41:15 PM PST 24 |
| Finished | Jan 17 01:41:19 PM PST 24 |
| Peak memory | 205636 kb |
| Host | smart-3a2c5115-28bc-484a-a9ec-69cc7809b1cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3812570186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3812570186 |
| Directory | /workspace/276.edn_genbits/latest |
| Test location | /workspace/coverage/default/13.edn_alert_test.3438014721 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 38571473 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 01:37:06 PM PST 24 |
| Finished | Jan 17 01:37:08 PM PST 24 |
| Peak memory | 204504 kb |
| Host | smart-3671f813-9cb1-4bdf-a498-201d2d87de46 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438014721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3438014721 |
| Directory | /workspace/13.edn_alert_test/latest |
| Test location | /workspace/coverage/default/5.edn_intr.843072840 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 20392404 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:36:08 PM PST 24 |
| Finished | Jan 17 01:36:10 PM PST 24 |
| Peak memory | 214556 kb |
| Host | smart-84494c5b-3682-41c6-b231-7540e7f2f479 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=843072840 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.843072840 |
| Directory | /workspace/5.edn_intr/latest |
| Test location | /workspace/coverage/default/19.edn_intr.4229544793 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 20617530 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 01:37:45 PM PST 24 |
| Finished | Jan 17 01:37:51 PM PST 24 |
| Peak memory | 214496 kb |
| Host | smart-7c1db8e5-9cc1-41ab-89a9-672a9dc2446f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4229544793 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.4229544793 |
| Directory | /workspace/19.edn_intr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3225659129 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 130979212 ps |
| CPU time | 2.2 seconds |
| Started | Jan 17 12:31:18 PM PST 24 |
| Finished | Jan 17 12:31:22 PM PST 24 |
| Peak memory | 205852 kb |
| Host | smart-f8152778-93b9-4294-a6a6-000634375378 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225659129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3225659129 |
| Directory | /workspace/0.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/default/1.edn_alert.2678039953 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 35273402 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:35:23 PM PST 24 |
| Finished | Jan 17 01:35:25 PM PST 24 |
| Peak memory | 205120 kb |
| Host | smart-e3f0eadf-c6fb-45e4-af51-2d6b94bcb408 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2678039953 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2678039953 |
| Directory | /workspace/1.edn_alert/latest |
| Test location | /workspace/coverage/default/1.edn_stress_all.3231908668 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 192554669 ps |
| CPU time | 2.67 seconds |
| Started | Jan 17 01:35:23 PM PST 24 |
| Finished | Jan 17 01:35:26 PM PST 24 |
| Peak memory | 205948 kb |
| Host | smart-5be985f6-e724-49ad-8a7a-abde4e8528ae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231908668 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3231908668 |
| Directory | /workspace/1.edn_stress_all/latest |
| Test location | /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1573886571 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 40572668381 ps |
| CPU time | 805.57 seconds |
| Started | Jan 17 01:35:24 PM PST 24 |
| Finished | Jan 17 01:48:51 PM PST 24 |
| Peak memory | 215264 kb |
| Host | smart-b0c4632b-9df0-41e7-b3a8-6886015bf86a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573886571 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1573886571 |
| Directory | /workspace/1.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/100.edn_genbits.1481431077 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 54832009 ps |
| CPU time | 2.1 seconds |
| Started | Jan 17 01:40:24 PM PST 24 |
| Finished | Jan 17 01:40:27 PM PST 24 |
| Peak memory | 214172 kb |
| Host | smart-ed047750-1e5f-4e64-9d45-a46148a3cda1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1481431077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1481431077 |
| Directory | /workspace/100.edn_genbits/latest |
| Test location | /workspace/coverage/default/101.edn_genbits.1153357220 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 19317426 ps |
| CPU time | 1.05 seconds |
| Started | Jan 17 01:40:24 PM PST 24 |
| Finished | Jan 17 01:40:26 PM PST 24 |
| Peak memory | 205260 kb |
| Host | smart-65cfcc2a-ca0f-4043-9245-68430c0fd9cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1153357220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.1153357220 |
| Directory | /workspace/101.edn_genbits/latest |
| Test location | /workspace/coverage/default/110.edn_genbits.3359902438 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 27967734 ps |
| CPU time | 0.9 seconds |
| Started | Jan 17 01:40:29 PM PST 24 |
| Finished | Jan 17 01:40:30 PM PST 24 |
| Peak memory | 205016 kb |
| Host | smart-999c2e55-1834-40ca-9261-a8a023774a37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3359902438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3359902438 |
| Directory | /workspace/110.edn_genbits/latest |
| Test location | /workspace/coverage/default/113.edn_genbits.3040832759 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 14647707 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:40:24 PM PST 24 |
| Finished | Jan 17 01:40:26 PM PST 24 |
| Peak memory | 205172 kb |
| Host | smart-8100dbe2-4059-45c1-a668-1631b1c0fa3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3040832759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.3040832759 |
| Directory | /workspace/113.edn_genbits/latest |
| Test location | /workspace/coverage/default/198.edn_genbits.287227131 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 22281486 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 01:40:44 PM PST 24 |
| Finished | Jan 17 01:40:53 PM PST 24 |
| Peak memory | 214136 kb |
| Host | smart-a2960fab-d679-42e5-b85f-110f38afa3d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=287227131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.287227131 |
| Directory | /workspace/198.edn_genbits/latest |
| Test location | /workspace/coverage/default/2.edn_regwen.2730638882 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 23944000 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:35:47 PM PST 24 |
| Finished | Jan 17 01:35:52 PM PST 24 |
| Peak memory | 205028 kb |
| Host | smart-56271497-8f35-43d9-81d5-5083b1522c67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2730638882 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2730638882 |
| Directory | /workspace/2.edn_regwen/latest |
| Test location | /workspace/coverage/default/209.edn_genbits.1121382634 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 16030151 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:41:00 PM PST 24 |
| Finished | Jan 17 01:41:04 PM PST 24 |
| Peak memory | 205008 kb |
| Host | smart-229028de-815f-42f9-a3ae-9f8f9eef0ee3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1121382634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.1121382634 |
| Directory | /workspace/209.edn_genbits/latest |
| Test location | /workspace/coverage/default/33.edn_genbits.3046030526 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 79015318 ps |
| CPU time | 1.13 seconds |
| Started | Jan 17 01:38:36 PM PST 24 |
| Finished | Jan 17 01:38:38 PM PST 24 |
| Peak memory | 214160 kb |
| Host | smart-34839018-c138-4237-bb69-e2e53edcfecc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3046030526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3046030526 |
| Directory | /workspace/33.edn_genbits/latest |
| Test location | /workspace/coverage/default/34.edn_alert.282375845 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 61367439 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 01:38:39 PM PST 24 |
| Finished | Jan 17 01:38:43 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-d32f8951-cd82-48eb-a7fb-5a6ef1197bdc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=282375845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.282375845 |
| Directory | /workspace/34.edn_alert/latest |
| Test location | /workspace/coverage/default/145.edn_genbits.357045781 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 359601350 ps |
| CPU time | 1.66 seconds |
| Started | Jan 17 01:40:44 PM PST 24 |
| Finished | Jan 17 01:40:54 PM PST 24 |
| Peak memory | 214132 kb |
| Host | smart-b1dbdda2-aa5d-4f9a-8d57-c9e3883352bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=357045781 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.357045781 |
| Directory | /workspace/145.edn_genbits/latest |
| Test location | /workspace/coverage/default/13.edn_disable.2569368784 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 95649647 ps |
| CPU time | 0.84 seconds |
| Started | Jan 17 01:37:06 PM PST 24 |
| Finished | Jan 17 01:37:08 PM PST 24 |
| Peak memory | 214184 kb |
| Host | smart-295c6259-82c5-4de8-a9f7-a9d4bc470422 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569368784 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2569368784 |
| Directory | /workspace/13.edn_disable/latest |
| Test location | /workspace/coverage/default/18.edn_disable.2490995784 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 22479649 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:37:29 PM PST 24 |
| Finished | Jan 17 01:37:30 PM PST 24 |
| Peak memory | 214376 kb |
| Host | smart-0616cb25-4071-486d-9daa-b0013e47b18f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490995784 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2490995784 |
| Directory | /workspace/18.edn_disable/latest |
| Test location | /workspace/coverage/default/19.edn_disable.2149598646 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 26636345 ps |
| CPU time | 0.79 seconds |
| Started | Jan 17 01:37:41 PM PST 24 |
| Finished | Jan 17 01:37:44 PM PST 24 |
| Peak memory | 214344 kb |
| Host | smart-594a3017-52e8-4382-a11f-975245ea8314 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149598646 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2149598646 |
| Directory | /workspace/19.edn_disable/latest |
| Test location | /workspace/coverage/default/11.edn_disable.3838628912 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 25345613 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:36:50 PM PST 24 |
| Finished | Jan 17 01:36:52 PM PST 24 |
| Peak memory | 214580 kb |
| Host | smart-a79b5436-cdcd-4ab3-99bb-313800be765e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838628912 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3838628912 |
| Directory | /workspace/11.edn_disable/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3583933709 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 69876187 ps |
| CPU time | 1.1 seconds |
| Started | Jan 17 12:31:04 PM PST 24 |
| Finished | Jan 17 12:31:07 PM PST 24 |
| Peak memory | 205944 kb |
| Host | smart-923443b9-0f5a-4fee-ad49-01d9fbe15aaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583933709 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3583933709 |
| Directory | /workspace/0.edn_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.254843827 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 521505730 ps |
| CPU time | 6.34 seconds |
| Started | Jan 17 12:31:06 PM PST 24 |
| Finished | Jan 17 12:31:13 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-a506e5e3-6186-46df-9587-7984428c4722 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254843827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.254843827 |
| Directory | /workspace/0.edn_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1871858670 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 102385914 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 12:31:11 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-ba356945-610b-4ce8-b055-55cb6320ade0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871858670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1871858670 |
| Directory | /workspace/0.edn_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3841828320 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 181116209 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 12:31:21 PM PST 24 |
| Finished | Jan 17 12:31:23 PM PST 24 |
| Peak memory | 205912 kb |
| Host | smart-55d88b25-f907-451c-8a26-954aeb1feed1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841828320 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3841828320 |
| Directory | /workspace/0.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_csr_rw.1331409931 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 18203493 ps |
| CPU time | 0.78 seconds |
| Started | Jan 17 12:31:15 PM PST 24 |
| Finished | Jan 17 12:31:20 PM PST 24 |
| Peak memory | 205660 kb |
| Host | smart-f3b7413f-3caf-43e3-9612-fe60662640e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331409931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1331409931 |
| Directory | /workspace/0.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_intr_test.39561079 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 20889137 ps |
| CPU time | 0.76 seconds |
| Started | Jan 17 12:31:11 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205816 kb |
| Host | smart-47d55fb0-2493-489a-8179-8ffe3c0b1620 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39561079 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.39561079 |
| Directory | /workspace/0.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.626112046 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 31946190 ps |
| CPU time | 1.25 seconds |
| Started | Jan 17 12:31:03 PM PST 24 |
| Finished | Jan 17 12:31:07 PM PST 24 |
| Peak memory | 205988 kb |
| Host | smart-9a947c6e-7f0f-482e-8dbd-b3b1a3ddf502 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626112046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out standing.626112046 |
| Directory | /workspace/0.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_tl_errors.1434962439 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 171550178 ps |
| CPU time | 1.6 seconds |
| Started | Jan 17 12:31:04 PM PST 24 |
| Finished | Jan 17 12:31:08 PM PST 24 |
| Peak memory | 214304 kb |
| Host | smart-534f40b5-2954-41ae-b791-cd1eeac801b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434962439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1434962439 |
| Directory | /workspace/0.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2629999265 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 61468355 ps |
| CPU time | 1.13 seconds |
| Started | Jan 17 12:31:10 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205952 kb |
| Host | smart-12abf50b-d9ef-49b5-b78d-6cdf520a1515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629999265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2629999265 |
| Directory | /workspace/1.edn_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.46037463 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 1015262477 ps |
| CPU time | 3.9 seconds |
| Started | Jan 17 12:31:09 PM PST 24 |
| Finished | Jan 17 12:31:20 PM PST 24 |
| Peak memory | 205964 kb |
| Host | smart-68fc03a6-9841-4ab8-85c5-0b5ccad9b091 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46037463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.46037463 |
| Directory | /workspace/1.edn_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2777292434 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 16287547 ps |
| CPU time | 0.91 seconds |
| Started | Jan 17 12:31:09 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205956 kb |
| Host | smart-07f0b7a5-c1b4-411b-865e-ba73f9fa5c54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777292434 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2777292434 |
| Directory | /workspace/1.edn_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.351498729 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 31441871 ps |
| CPU time | 1.1 seconds |
| Started | Jan 17 12:31:07 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 214272 kb |
| Host | smart-80bad514-f3dd-4c6f-9bd6-f540f6c9e3e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351498729 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.351498729 |
| Directory | /workspace/1.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_csr_rw.199367334 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 29980996 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 12:31:06 PM PST 24 |
| Finished | Jan 17 12:31:08 PM PST 24 |
| Peak memory | 205676 kb |
| Host | smart-00ae6c01-fb19-4cc7-b8d9-cc8eff0d6d42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199367334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.199367334 |
| Directory | /workspace/1.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_intr_test.3965585343 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 17925293 ps |
| CPU time | 0.79 seconds |
| Started | Jan 17 12:31:12 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205756 kb |
| Host | smart-862ad39f-ff72-451d-9ad7-bcf98eaedc27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965585343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3965585343 |
| Directory | /workspace/1.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2741465459 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 22012149 ps |
| CPU time | 1.07 seconds |
| Started | Jan 17 12:31:04 PM PST 24 |
| Finished | Jan 17 12:31:07 PM PST 24 |
| Peak memory | 205908 kb |
| Host | smart-c22df11c-2a81-4bce-b126-caa58d25a235 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741465459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou tstanding.2741465459 |
| Directory | /workspace/1.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_tl_errors.2198931606 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 93592786 ps |
| CPU time | 1.84 seconds |
| Started | Jan 17 12:31:04 PM PST 24 |
| Finished | Jan 17 12:31:08 PM PST 24 |
| Peak memory | 214116 kb |
| Host | smart-81a9e857-4733-4c92-800c-12af3c67a18c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198931606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2198931606 |
| Directory | /workspace/1.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.630799036 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 178773000 ps |
| CPU time | 1.56 seconds |
| Started | Jan 17 12:31:07 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-abc0dfae-74dd-4158-9a6a-1a52bd443a52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630799036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.630799036 |
| Directory | /workspace/1.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.121172661 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 16287215 ps |
| CPU time | 1.06 seconds |
| Started | Jan 17 12:31:14 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 214168 kb |
| Host | smart-e8c47415-d725-4fec-aed0-b21c0e3d7e85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121172661 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.121172661 |
| Directory | /workspace/10.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.edn_csr_rw.3725797066 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 17785436 ps |
| CPU time | 0.84 seconds |
| Started | Jan 17 12:31:13 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205908 kb |
| Host | smart-d12fd3ae-374e-40ea-a96b-3f37d8a1a4bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725797066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3725797066 |
| Directory | /workspace/10.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.edn_intr_test.164917711 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 40730980 ps |
| CPU time | 0.79 seconds |
| Started | Jan 17 12:31:08 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-36e0f9f9-7a20-4aaa-aae3-534533e5cdca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164917711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.164917711 |
| Directory | /workspace/10.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1380048396 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 35934186 ps |
| CPU time | 1 seconds |
| Started | Jan 17 12:31:18 PM PST 24 |
| Finished | Jan 17 12:31:21 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-c6c650c7-0b50-4087-97fd-3ef3ad81fca3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380048396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o utstanding.1380048396 |
| Directory | /workspace/10.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1862358674 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 69329125 ps |
| CPU time | 1.87 seconds |
| Started | Jan 17 12:31:15 PM PST 24 |
| Finished | Jan 17 12:31:21 PM PST 24 |
| Peak memory | 205936 kb |
| Host | smart-be309f2d-b830-4032-afea-d3d5bbf469fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862358674 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1862358674 |
| Directory | /workspace/10.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.4260887333 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 93565591 ps |
| CPU time | 1.81 seconds |
| Started | Jan 17 12:31:20 PM PST 24 |
| Finished | Jan 17 12:31:24 PM PST 24 |
| Peak memory | 217620 kb |
| Host | smart-6ca80e79-91f7-4345-833c-cb5153ffeca3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260887333 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.4260887333 |
| Directory | /workspace/11.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.edn_csr_rw.2307869582 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 25125878 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 12:31:28 PM PST 24 |
| Finished | Jan 17 12:31:33 PM PST 24 |
| Peak memory | 205988 kb |
| Host | smart-c4419d2a-25b9-499c-81c1-a4ff8e228191 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307869582 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2307869582 |
| Directory | /workspace/11.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.edn_intr_test.4147055326 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 10928379 ps |
| CPU time | 0.78 seconds |
| Started | Jan 17 12:31:13 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-d23334e0-aaa6-4859-a3b5-9cecfa6b87ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147055326 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.4147055326 |
| Directory | /workspace/11.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1975945529 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 15321523 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 12:31:14 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-4dd78efe-1681-4483-b67f-e4b1a34a92ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975945529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o utstanding.1975945529 |
| Directory | /workspace/11.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.edn_tl_errors.1642941607 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 66195839 ps |
| CPU time | 2.69 seconds |
| Started | Jan 17 12:31:16 PM PST 24 |
| Finished | Jan 17 12:31:22 PM PST 24 |
| Peak memory | 214236 kb |
| Host | smart-0859d1e6-2eab-4a3b-a6ea-8f69d9910400 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642941607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1642941607 |
| Directory | /workspace/11.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3562008336 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 115245861 ps |
| CPU time | 1.34 seconds |
| Started | Jan 17 12:31:17 PM PST 24 |
| Finished | Jan 17 12:31:21 PM PST 24 |
| Peak memory | 214172 kb |
| Host | smart-cb03bb59-dffb-44a3-8709-04fe32c9e652 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562008336 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3562008336 |
| Directory | /workspace/12.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.edn_intr_test.3108849995 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 16638053 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 12:31:34 PM PST 24 |
| Finished | Jan 17 12:31:38 PM PST 24 |
| Peak memory | 205992 kb |
| Host | smart-bc802b50-e3a7-4be8-a146-eb121979718b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108849995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3108849995 |
| Directory | /workspace/12.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1745813959 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 23345219 ps |
| CPU time | 1.04 seconds |
| Started | Jan 17 12:31:29 PM PST 24 |
| Finished | Jan 17 12:31:35 PM PST 24 |
| Peak memory | 205964 kb |
| Host | smart-117a60a1-d068-4e21-9e13-1c57d16e916c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745813959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o utstanding.1745813959 |
| Directory | /workspace/12.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.edn_tl_errors.2310658011 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 123371667 ps |
| CPU time | 4.28 seconds |
| Started | Jan 17 12:31:31 PM PST 24 |
| Finished | Jan 17 12:31:40 PM PST 24 |
| Peak memory | 214260 kb |
| Host | smart-b8fd3266-c49c-4a97-987c-a0a494b6ea05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310658011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2310658011 |
| Directory | /workspace/12.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.1543187848 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 271288345 ps |
| CPU time | 2.93 seconds |
| Started | Jan 17 12:31:25 PM PST 24 |
| Finished | Jan 17 12:31:29 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-fc77a3a9-2fca-4d94-ae90-8564b9b28462 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543187848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.1543187848 |
| Directory | /workspace/12.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2066299886 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 76035067 ps |
| CPU time | 1.55 seconds |
| Started | Jan 17 12:31:37 PM PST 24 |
| Finished | Jan 17 12:31:41 PM PST 24 |
| Peak memory | 218252 kb |
| Host | smart-9e62dd04-af4f-42ab-9f1f-c778a892dfd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066299886 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2066299886 |
| Directory | /workspace/13.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.edn_csr_rw.1022059789 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 12791356 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 12:31:26 PM PST 24 |
| Finished | Jan 17 12:31:30 PM PST 24 |
| Peak memory | 206008 kb |
| Host | smart-7c6f5aa0-6e24-4251-9795-94879081fbc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022059789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1022059789 |
| Directory | /workspace/13.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.edn_intr_test.1101819973 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 24593591 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 12:31:12 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205936 kb |
| Host | smart-0c57a4f5-2096-490e-8c08-3815805ec463 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101819973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1101819973 |
| Directory | /workspace/13.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3415206826 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 223657689 ps |
| CPU time | 1.04 seconds |
| Started | Jan 17 12:31:14 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205952 kb |
| Host | smart-d92522af-15f4-4832-9424-49c5668683a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415206826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o utstanding.3415206826 |
| Directory | /workspace/13.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.edn_tl_errors.3115096195 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 130173215 ps |
| CPU time | 4.28 seconds |
| Started | Jan 17 12:31:51 PM PST 24 |
| Finished | Jan 17 12:31:58 PM PST 24 |
| Peak memory | 214300 kb |
| Host | smart-15a7f245-9bb4-4ce4-a080-497885751d94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115096195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3115096195 |
| Directory | /workspace/13.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1827848945 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 512345992 ps |
| CPU time | 8.42 seconds |
| Started | Jan 17 12:31:19 PM PST 24 |
| Finished | Jan 17 12:31:29 PM PST 24 |
| Peak memory | 206000 kb |
| Host | smart-926765e5-7ef2-4942-b6b1-1ef2f81da73d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827848945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1827848945 |
| Directory | /workspace/13.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2397650375 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 25598347 ps |
| CPU time | 1.27 seconds |
| Started | Jan 17 12:31:19 PM PST 24 |
| Finished | Jan 17 12:31:22 PM PST 24 |
| Peak memory | 214196 kb |
| Host | smart-8f8a820a-867e-4678-aa31-59a069a6c029 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397650375 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2397650375 |
| Directory | /workspace/14.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.edn_csr_rw.3584263942 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 43666333 ps |
| CPU time | 0.82 seconds |
| Started | Jan 17 12:31:36 PM PST 24 |
| Finished | Jan 17 12:31:39 PM PST 24 |
| Peak memory | 205768 kb |
| Host | smart-9c5f7ca2-f26c-48f3-826f-523e122f44c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584263942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3584263942 |
| Directory | /workspace/14.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.edn_intr_test.4116484306 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 23035719 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 12:31:15 PM PST 24 |
| Finished | Jan 17 12:31:20 PM PST 24 |
| Peak memory | 206048 kb |
| Host | smart-1efdac1e-15b2-48dc-aaf8-116d0e93bc61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116484306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.4116484306 |
| Directory | /workspace/14.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3097632493 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 50881255 ps |
| CPU time | 1 seconds |
| Started | Jan 17 12:31:16 PM PST 24 |
| Finished | Jan 17 12:31:20 PM PST 24 |
| Peak memory | 206324 kb |
| Host | smart-86427ebd-fe21-4af7-83fd-d5b20e7ce281 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097632493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o utstanding.3097632493 |
| Directory | /workspace/14.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.edn_tl_errors.1281056814 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 25266965 ps |
| CPU time | 1.53 seconds |
| Started | Jan 17 12:31:31 PM PST 24 |
| Finished | Jan 17 12:31:37 PM PST 24 |
| Peak memory | 214240 kb |
| Host | smart-e7323ab1-d989-450f-b309-902adf68b55b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281056814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1281056814 |
| Directory | /workspace/14.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1651548458 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 92601417 ps |
| CPU time | 1.6 seconds |
| Started | Jan 17 12:31:17 PM PST 24 |
| Finished | Jan 17 12:31:22 PM PST 24 |
| Peak memory | 205920 kb |
| Host | smart-ff8f8d8e-e99d-4dc5-b060-5f3c03f237aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651548458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1651548458 |
| Directory | /workspace/14.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.483182108 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 34390401 ps |
| CPU time | 1.37 seconds |
| Started | Jan 17 12:31:23 PM PST 24 |
| Finished | Jan 17 12:31:25 PM PST 24 |
| Peak memory | 214268 kb |
| Host | smart-5cc0b629-bcfe-4a47-af2c-288b073133bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483182108 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.483182108 |
| Directory | /workspace/15.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.edn_csr_rw.3616847991 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 44716043 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 12:31:18 PM PST 24 |
| Finished | Jan 17 12:31:21 PM PST 24 |
| Peak memory | 205900 kb |
| Host | smart-707c1550-864f-4b1f-aaa5-389cae0ef6e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616847991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3616847991 |
| Directory | /workspace/15.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.edn_intr_test.1255884929 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 14601411 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 12:31:51 PM PST 24 |
| Finished | Jan 17 12:31:55 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-a954cbba-65f6-41c9-9b0b-108b79f7f0c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255884929 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1255884929 |
| Directory | /workspace/15.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3838353621 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 25691965 ps |
| CPU time | 1.05 seconds |
| Started | Jan 17 12:31:15 PM PST 24 |
| Finished | Jan 17 12:31:20 PM PST 24 |
| Peak memory | 206032 kb |
| Host | smart-998f0208-c1d0-46c4-88f8-ffe6a5ca6b15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838353621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o utstanding.3838353621 |
| Directory | /workspace/15.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.edn_tl_errors.2578580274 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 181987632 ps |
| CPU time | 1.96 seconds |
| Started | Jan 17 12:31:24 PM PST 24 |
| Finished | Jan 17 12:31:26 PM PST 24 |
| Peak memory | 214216 kb |
| Host | smart-00c76b58-3f15-473d-9672-47d65d958cfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578580274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2578580274 |
| Directory | /workspace/15.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2937978261 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 335797430 ps |
| CPU time | 2.27 seconds |
| Started | Jan 17 12:31:23 PM PST 24 |
| Finished | Jan 17 12:31:26 PM PST 24 |
| Peak memory | 205956 kb |
| Host | smart-806ae7c4-fd45-49e2-8768-6824b6b98d84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937978261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2937978261 |
| Directory | /workspace/15.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.509898597 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 31782011 ps |
| CPU time | 1 seconds |
| Started | Jan 17 12:31:29 PM PST 24 |
| Finished | Jan 17 12:31:34 PM PST 24 |
| Peak memory | 213940 kb |
| Host | smart-89ea767d-e3b3-4df3-9757-5f60122e8bc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509898597 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.509898597 |
| Directory | /workspace/16.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.edn_csr_rw.2345993316 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 15883002 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 12:31:16 PM PST 24 |
| Finished | Jan 17 12:31:20 PM PST 24 |
| Peak memory | 206004 kb |
| Host | smart-9f81721c-5310-4923-92c1-d623f6b5cff8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345993316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2345993316 |
| Directory | /workspace/16.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.edn_intr_test.2636900971 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 20704653 ps |
| CPU time | 0.9 seconds |
| Started | Jan 17 12:31:14 PM PST 24 |
| Finished | Jan 17 12:31:18 PM PST 24 |
| Peak memory | 205944 kb |
| Host | smart-fe65ed7a-37fc-4d3b-963b-6210c1f5a522 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636900971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2636900971 |
| Directory | /workspace/16.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4173766744 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 114933586 ps |
| CPU time | 1.28 seconds |
| Started | Jan 17 12:31:23 PM PST 24 |
| Finished | Jan 17 12:31:26 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-d09902ea-2c4d-4195-9770-99c425ecd257 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173766744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o utstanding.4173766744 |
| Directory | /workspace/16.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.edn_tl_errors.927730757 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 65524462 ps |
| CPU time | 2.37 seconds |
| Started | Jan 17 12:31:28 PM PST 24 |
| Finished | Jan 17 12:31:36 PM PST 24 |
| Peak memory | 214200 kb |
| Host | smart-c722ddee-4bc1-4304-950a-08d5b5d69b65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927730757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.927730757 |
| Directory | /workspace/16.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.840459349 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 84893484 ps |
| CPU time | 1.49 seconds |
| Started | Jan 17 12:31:24 PM PST 24 |
| Finished | Jan 17 12:31:26 PM PST 24 |
| Peak memory | 205884 kb |
| Host | smart-ac0cf964-f322-4bac-8d55-30c572b15122 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840459349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.840459349 |
| Directory | /workspace/16.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.203612582 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 41107101 ps |
| CPU time | 1.34 seconds |
| Started | Jan 17 12:31:30 PM PST 24 |
| Finished | Jan 17 12:31:36 PM PST 24 |
| Peak memory | 214216 kb |
| Host | smart-a0ce54f2-1590-4d7e-ab13-e49a4f293950 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203612582 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.203612582 |
| Directory | /workspace/17.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.edn_csr_rw.940429207 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 22158439 ps |
| CPU time | 0.8 seconds |
| Started | Jan 17 12:31:32 PM PST 24 |
| Finished | Jan 17 12:31:37 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-6e324a74-925f-4e0b-a7fb-7f3cd4951c34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940429207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.940429207 |
| Directory | /workspace/17.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.edn_intr_test.1699153658 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 14878162 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 12:31:26 PM PST 24 |
| Finished | Jan 17 12:31:30 PM PST 24 |
| Peak memory | 205932 kb |
| Host | smart-2b98a82f-1f6f-4eb8-af28-4648bd8e4336 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699153658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1699153658 |
| Directory | /workspace/17.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.753678690 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 63203544 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 12:31:42 PM PST 24 |
| Finished | Jan 17 12:31:44 PM PST 24 |
| Peak memory | 206032 kb |
| Host | smart-d321671e-deb9-4dc5-8fb8-f9c4bb6d79dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753678690 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou tstanding.753678690 |
| Directory | /workspace/17.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.edn_tl_errors.2265364895 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 39011124 ps |
| CPU time | 2.17 seconds |
| Started | Jan 17 12:31:19 PM PST 24 |
| Finished | Jan 17 12:31:24 PM PST 24 |
| Peak memory | 214232 kb |
| Host | smart-76553605-47a2-4130-9f11-b29fe15d61d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265364895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2265364895 |
| Directory | /workspace/17.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1269241450 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 47410343 ps |
| CPU time | 1.66 seconds |
| Started | Jan 17 12:31:13 PM PST 24 |
| Finished | Jan 17 12:31:18 PM PST 24 |
| Peak memory | 206268 kb |
| Host | smart-c10eae39-74e4-4384-8f4d-56dcdc69dfe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269241450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1269241450 |
| Directory | /workspace/17.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3600638917 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 61706472 ps |
| CPU time | 1.37 seconds |
| Started | Jan 17 12:31:24 PM PST 24 |
| Finished | Jan 17 12:31:26 PM PST 24 |
| Peak memory | 216908 kb |
| Host | smart-9703f5bd-4958-493e-b2c8-5f3382c470ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600638917 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3600638917 |
| Directory | /workspace/18.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.edn_csr_rw.3941174943 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 85119744 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 12:31:28 PM PST 24 |
| Finished | Jan 17 12:31:33 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-b57eb737-b1f8-49c1-9f21-4645e794e90c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941174943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3941174943 |
| Directory | /workspace/18.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.edn_intr_test.1140369129 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 44357476 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 12:31:34 PM PST 24 |
| Finished | Jan 17 12:31:38 PM PST 24 |
| Peak memory | 205932 kb |
| Host | smart-0d72c1b8-977c-44d8-a779-2d7eb930a6d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140369129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1140369129 |
| Directory | /workspace/18.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.603258609 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 23662136 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 12:31:18 PM PST 24 |
| Finished | Jan 17 12:31:21 PM PST 24 |
| Peak memory | 205948 kb |
| Host | smart-8a04390c-0bad-4b15-8304-052e22fd14b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603258609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou tstanding.603258609 |
| Directory | /workspace/18.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.edn_tl_errors.1246469050 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 102763978 ps |
| CPU time | 3.58 seconds |
| Started | Jan 17 12:31:31 PM PST 24 |
| Finished | Jan 17 12:31:40 PM PST 24 |
| Peak memory | 214524 kb |
| Host | smart-00363505-f44d-4c51-a22d-86a5012cb96c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246469050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1246469050 |
| Directory | /workspace/18.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1300904878 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 553082908 ps |
| CPU time | 1.5 seconds |
| Started | Jan 17 12:31:16 PM PST 24 |
| Finished | Jan 17 12:31:21 PM PST 24 |
| Peak memory | 205920 kb |
| Host | smart-ab26cd0a-31ed-417f-b654-cadbbe76c0b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300904878 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1300904878 |
| Directory | /workspace/18.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.642688447 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 16497418 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 12:31:18 PM PST 24 |
| Finished | Jan 17 12:31:21 PM PST 24 |
| Peak memory | 214228 kb |
| Host | smart-112961db-3d25-476b-8a02-ec11fead86b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642688447 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.642688447 |
| Directory | /workspace/19.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.edn_csr_rw.4132353861 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 18662310 ps |
| CPU time | 0.8 seconds |
| Started | Jan 17 12:31:26 PM PST 24 |
| Finished | Jan 17 12:31:30 PM PST 24 |
| Peak memory | 206008 kb |
| Host | smart-0a1d6af3-f9c6-4e28-93aa-3cfeacebceae |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132353861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.4132353861 |
| Directory | /workspace/19.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.edn_intr_test.1225351373 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 35501848 ps |
| CPU time | 0.78 seconds |
| Started | Jan 17 12:31:33 PM PST 24 |
| Finished | Jan 17 12:31:38 PM PST 24 |
| Peak memory | 206008 kb |
| Host | smart-5e457fac-0ed5-4653-8507-3d93e44c8b08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225351373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.1225351373 |
| Directory | /workspace/19.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3486191369 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 66821387 ps |
| CPU time | 1.33 seconds |
| Started | Jan 17 12:31:16 PM PST 24 |
| Finished | Jan 17 12:31:20 PM PST 24 |
| Peak memory | 205924 kb |
| Host | smart-2889db66-542f-4352-9f51-d97d53bc1d02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486191369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o utstanding.3486191369 |
| Directory | /workspace/19.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.edn_tl_errors.3626138446 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 305961038 ps |
| CPU time | 2.82 seconds |
| Started | Jan 17 12:31:27 PM PST 24 |
| Finished | Jan 17 12:31:35 PM PST 24 |
| Peak memory | 214304 kb |
| Host | smart-e85580ef-12f8-4eda-bd6c-2836cad22c42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626138446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3626138446 |
| Directory | /workspace/19.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.912129423 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 153360096 ps |
| CPU time | 1.55 seconds |
| Started | Jan 17 12:31:16 PM PST 24 |
| Finished | Jan 17 12:31:21 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-8b5a3a84-cab5-4d5f-a604-2dd7105d4d44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912129423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.912129423 |
| Directory | /workspace/19.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1092109773 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 18759756 ps |
| CPU time | 1.07 seconds |
| Started | Jan 17 12:31:02 PM PST 24 |
| Finished | Jan 17 12:31:07 PM PST 24 |
| Peak memory | 206032 kb |
| Host | smart-b97dac3d-ab1e-4ef1-aacc-7b1aaea6ad2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092109773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1092109773 |
| Directory | /workspace/2.edn_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1554739349 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 673713763 ps |
| CPU time | 5.02 seconds |
| Started | Jan 17 12:31:07 PM PST 24 |
| Finished | Jan 17 12:31:21 PM PST 24 |
| Peak memory | 205556 kb |
| Host | smart-c971df9f-21bf-4f15-a73f-22c9dfd664aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554739349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1554739349 |
| Directory | /workspace/2.edn_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1300325846 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 28709192 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 12:31:18 PM PST 24 |
| Finished | Jan 17 12:31:21 PM PST 24 |
| Peak memory | 205852 kb |
| Host | smart-ef5eb077-3afd-4df3-8425-490e8649bc76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300325846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1300325846 |
| Directory | /workspace/2.edn_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1316381462 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 113204970 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 12:31:12 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 215220 kb |
| Host | smart-d8993046-d3c3-4caa-9de8-e06525b6252a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316381462 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1316381462 |
| Directory | /workspace/2.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_csr_rw.3219387874 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 15494392 ps |
| CPU time | 0.91 seconds |
| Started | Jan 17 12:31:07 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205584 kb |
| Host | smart-0fa3f394-10b0-4e47-873f-1dcee73876bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219387874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3219387874 |
| Directory | /workspace/2.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_intr_test.687144038 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 35705300 ps |
| CPU time | 0.79 seconds |
| Started | Jan 17 12:31:12 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205952 kb |
| Host | smart-ee167551-c868-4d07-9fc0-50062f6d2053 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687144038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.687144038 |
| Directory | /workspace/2.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4117683890 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 166396316 ps |
| CPU time | 1.19 seconds |
| Started | Jan 17 12:31:12 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205988 kb |
| Host | smart-1cc7d0a2-6831-4e8f-83d7-4da900df45cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117683890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou tstanding.4117683890 |
| Directory | /workspace/2.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_tl_errors.535409389 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 62730425 ps |
| CPU time | 2.32 seconds |
| Started | Jan 17 12:31:12 PM PST 24 |
| Finished | Jan 17 12:31:18 PM PST 24 |
| Peak memory | 214280 kb |
| Host | smart-699ed044-fa8b-406b-82c2-2c66af8eb7a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535409389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.535409389 |
| Directory | /workspace/2.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3691861593 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 447659623 ps |
| CPU time | 2.24 seconds |
| Started | Jan 17 12:31:27 PM PST 24 |
| Finished | Jan 17 12:31:33 PM PST 24 |
| Peak memory | 205852 kb |
| Host | smart-52cc796a-78f2-4889-afc3-89dda3e837cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691861593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3691861593 |
| Directory | /workspace/2.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.edn_intr_test.4291538549 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 40069958 ps |
| CPU time | 0.8 seconds |
| Started | Jan 17 12:31:18 PM PST 24 |
| Finished | Jan 17 12:31:21 PM PST 24 |
| Peak memory | 205776 kb |
| Host | smart-7ec6cf21-5dc3-42ff-89fd-df2bd32f9367 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291538549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.4291538549 |
| Directory | /workspace/20.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.edn_intr_test.732246707 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 31647004 ps |
| CPU time | 0.84 seconds |
| Started | Jan 17 12:31:24 PM PST 24 |
| Finished | Jan 17 12:31:25 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-27bbbb73-594f-445a-a9b9-8dda11093677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732246707 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.732246707 |
| Directory | /workspace/21.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.edn_intr_test.3373223937 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 12975514 ps |
| CPU time | 0.84 seconds |
| Started | Jan 17 12:31:24 PM PST 24 |
| Finished | Jan 17 12:31:26 PM PST 24 |
| Peak memory | 206012 kb |
| Host | smart-1fe892e1-eba3-4af4-aeb4-eb321bfa49b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373223937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3373223937 |
| Directory | /workspace/22.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.edn_intr_test.4241665963 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 105238861 ps |
| CPU time | 0.79 seconds |
| Started | Jan 17 12:31:18 PM PST 24 |
| Finished | Jan 17 12:31:21 PM PST 24 |
| Peak memory | 205892 kb |
| Host | smart-9ef902a0-a8c6-4262-93d6-297c200059f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241665963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.4241665963 |
| Directory | /workspace/23.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.edn_intr_test.4174836194 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 56930926 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 12:31:44 PM PST 24 |
| Finished | Jan 17 12:31:46 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-23260ff8-5318-4469-8dc2-f92e86f47116 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174836194 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.4174836194 |
| Directory | /workspace/24.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.edn_intr_test.3814022317 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 56221929 ps |
| CPU time | 0.78 seconds |
| Started | Jan 17 12:31:29 PM PST 24 |
| Finished | Jan 17 12:31:35 PM PST 24 |
| Peak memory | 205800 kb |
| Host | smart-2fbfcbf4-6993-4e00-b018-95586f46dd51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814022317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3814022317 |
| Directory | /workspace/25.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.edn_intr_test.3249796614 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 53058172 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 12:31:36 PM PST 24 |
| Finished | Jan 17 12:31:39 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-0304bd46-6a3e-481f-86c0-c1517b1f7765 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249796614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3249796614 |
| Directory | /workspace/26.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.edn_intr_test.598398848 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 55894100 ps |
| CPU time | 0.75 seconds |
| Started | Jan 17 12:31:29 PM PST 24 |
| Finished | Jan 17 12:31:34 PM PST 24 |
| Peak memory | 205824 kb |
| Host | smart-541c87f5-08a0-4bac-a156-2cc6241f5e98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598398848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.598398848 |
| Directory | /workspace/27.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.edn_intr_test.740982619 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 22607780 ps |
| CPU time | 0.81 seconds |
| Started | Jan 17 12:31:18 PM PST 24 |
| Finished | Jan 17 12:31:25 PM PST 24 |
| Peak memory | 205980 kb |
| Host | smart-63bb07d0-0732-4174-a7d9-9ec41f12770b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740982619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.740982619 |
| Directory | /workspace/28.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.edn_intr_test.1015739364 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 19619881 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 12:31:25 PM PST 24 |
| Finished | Jan 17 12:31:27 PM PST 24 |
| Peak memory | 205768 kb |
| Host | smart-6ff9f341-c287-466f-9cb9-805ec858719a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015739364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1015739364 |
| Directory | /workspace/29.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2456198120 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 14747561 ps |
| CPU time | 1 seconds |
| Started | Jan 17 12:31:11 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 206020 kb |
| Host | smart-db85c8eb-35a0-4400-8f60-40ef7dc77748 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456198120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2456198120 |
| Directory | /workspace/3.edn_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.573558077 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 113954196 ps |
| CPU time | 3.11 seconds |
| Started | Jan 17 12:31:24 PM PST 24 |
| Finished | Jan 17 12:31:28 PM PST 24 |
| Peak memory | 205996 kb |
| Host | smart-d86c1738-c97c-42da-a633-0ed1137c1ac6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573558077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.573558077 |
| Directory | /workspace/3.edn_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3414551069 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 27373493 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 12:31:36 PM PST 24 |
| Finished | Jan 17 12:31:39 PM PST 24 |
| Peak memory | 205964 kb |
| Host | smart-c935afe3-e3ef-4ab7-b3ef-0a22a26a6b81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414551069 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3414551069 |
| Directory | /workspace/3.edn_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2616381294 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 33777652 ps |
| CPU time | 1.18 seconds |
| Started | Jan 17 12:31:29 PM PST 24 |
| Finished | Jan 17 12:31:35 PM PST 24 |
| Peak memory | 213924 kb |
| Host | smart-02cb405b-5a68-4332-ab2a-e31e9a6590e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616381294 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2616381294 |
| Directory | /workspace/3.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_csr_rw.2738548611 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 51076369 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 12:31:16 PM PST 24 |
| Finished | Jan 17 12:31:20 PM PST 24 |
| Peak memory | 205996 kb |
| Host | smart-ad4a6f1a-adde-4374-9ff6-77bd923fddb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738548611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2738548611 |
| Directory | /workspace/3.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_intr_test.3676941886 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 44901733 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 12:31:14 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205924 kb |
| Host | smart-3706c796-f1ea-4d2d-bc26-90346a6518c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676941886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3676941886 |
| Directory | /workspace/3.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3203894301 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 14746773 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 12:31:15 PM PST 24 |
| Finished | Jan 17 12:31:20 PM PST 24 |
| Peak memory | 205988 kb |
| Host | smart-fd236ac0-4836-46fc-b062-aa6f29c7ecec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203894301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou tstanding.3203894301 |
| Directory | /workspace/3.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_tl_errors.659242219 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 120478936 ps |
| CPU time | 2.25 seconds |
| Started | Jan 17 12:31:13 PM PST 24 |
| Finished | Jan 17 12:31:18 PM PST 24 |
| Peak memory | 214232 kb |
| Host | smart-87003b46-da70-49d2-94a8-1cc81f3f7e7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659242219 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.659242219 |
| Directory | /workspace/3.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.983773028 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 71636524 ps |
| CPU time | 1.39 seconds |
| Started | Jan 17 12:31:15 PM PST 24 |
| Finished | Jan 17 12:31:20 PM PST 24 |
| Peak memory | 205980 kb |
| Host | smart-3fbc8ad1-ac8f-4ca6-aa6c-6d77a40a72cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983773028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.983773028 |
| Directory | /workspace/3.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.edn_intr_test.157872193 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 19235777 ps |
| CPU time | 0.8 seconds |
| Started | Jan 17 12:31:34 PM PST 24 |
| Finished | Jan 17 12:31:38 PM PST 24 |
| Peak memory | 205776 kb |
| Host | smart-d82e5220-9fdd-440d-9b03-1712676e4086 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157872193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.157872193 |
| Directory | /workspace/30.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.edn_intr_test.1313086644 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 57199155 ps |
| CPU time | 0.78 seconds |
| Started | Jan 17 12:31:20 PM PST 24 |
| Finished | Jan 17 12:31:23 PM PST 24 |
| Peak memory | 205776 kb |
| Host | smart-3afc776d-192c-4f02-b5f5-9e51f736b02e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313086644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1313086644 |
| Directory | /workspace/31.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.edn_intr_test.3592736495 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 26010401 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 12:31:11 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 206008 kb |
| Host | smart-0ebb3415-0ac3-4fde-9d69-bd265e2dcdf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592736495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3592736495 |
| Directory | /workspace/32.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.edn_intr_test.2621719858 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 15059483 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 12:31:23 PM PST 24 |
| Finished | Jan 17 12:31:25 PM PST 24 |
| Peak memory | 205904 kb |
| Host | smart-46e817ac-1bf9-497d-a9d7-93cf35fa6d90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621719858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2621719858 |
| Directory | /workspace/33.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.edn_intr_test.3342595317 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 46266679 ps |
| CPU time | 0.78 seconds |
| Started | Jan 17 12:31:47 PM PST 24 |
| Finished | Jan 17 12:31:53 PM PST 24 |
| Peak memory | 205676 kb |
| Host | smart-67ec03d7-63ca-41a0-a893-b7e6f4a81515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342595317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3342595317 |
| Directory | /workspace/34.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.edn_intr_test.1443003407 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 20814734 ps |
| CPU time | 0.84 seconds |
| Started | Jan 17 12:31:27 PM PST 24 |
| Finished | Jan 17 12:31:30 PM PST 24 |
| Peak memory | 206264 kb |
| Host | smart-49ae1e12-6593-4ef8-a131-c4735c7722fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443003407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1443003407 |
| Directory | /workspace/35.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.edn_intr_test.140861048 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 52361720 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 12:31:20 PM PST 24 |
| Finished | Jan 17 12:31:23 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-db92e413-bab2-485f-8dff-fa500a04e7ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140861048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.140861048 |
| Directory | /workspace/36.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.edn_intr_test.3193951653 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 56416155 ps |
| CPU time | 0.76 seconds |
| Started | Jan 17 12:31:32 PM PST 24 |
| Finished | Jan 17 12:31:37 PM PST 24 |
| Peak memory | 205752 kb |
| Host | smart-5819a0b2-f905-4979-a1af-1d105793f75b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193951653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3193951653 |
| Directory | /workspace/37.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.edn_intr_test.2109133567 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 23249948 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 12:31:26 PM PST 24 |
| Finished | Jan 17 12:31:30 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-1e02ce7e-a4b4-488c-8fdd-7447f8337ab3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109133567 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2109133567 |
| Directory | /workspace/38.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.edn_intr_test.2398317548 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 14953248 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 12:31:15 PM PST 24 |
| Finished | Jan 17 12:31:20 PM PST 24 |
| Peak memory | 205924 kb |
| Host | smart-ba205ec3-72fc-4a12-ae90-60e687042740 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398317548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2398317548 |
| Directory | /workspace/39.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.1905132346 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 28711540 ps |
| CPU time | 1.18 seconds |
| Started | Jan 17 12:31:07 PM PST 24 |
| Finished | Jan 17 12:31:16 PM PST 24 |
| Peak memory | 205964 kb |
| Host | smart-0b56c024-3cc8-4cb0-b93a-1b5e9611aecf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905132346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.1905132346 |
| Directory | /workspace/4.edn_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1048088227 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 57506248 ps |
| CPU time | 3.16 seconds |
| Started | Jan 17 12:31:25 PM PST 24 |
| Finished | Jan 17 12:31:31 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-9ebdd09c-de47-4891-8fb5-b506a17aae06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048088227 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1048088227 |
| Directory | /workspace/4.edn_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2113239644 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 41131547 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 12:31:03 PM PST 24 |
| Finished | Jan 17 12:31:07 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-36b6b8f0-9e1e-4fb7-8922-d7ec1502c277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113239644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2113239644 |
| Directory | /workspace/4.edn_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3139998 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 84015995 ps |
| CPU time | 1.1 seconds |
| Started | Jan 17 12:31:13 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 214276 kb |
| Host | smart-1a8a45da-4f00-4e56-ae73-b604c5f1792c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139998 -assert nopostproc +UVM_TESTNAME=ed n_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3139998 |
| Directory | /workspace/4.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_csr_rw.374321763 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 13125216 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 12:31:09 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-e49bf4af-3279-41e1-846d-fc7333689759 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374321763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.374321763 |
| Directory | /workspace/4.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_intr_test.2250265931 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 13671478 ps |
| CPU time | 0.84 seconds |
| Started | Jan 17 12:31:17 PM PST 24 |
| Finished | Jan 17 12:31:21 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-075ef7d2-dc56-443a-8643-347bcd5d3051 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250265931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2250265931 |
| Directory | /workspace/4.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3009362879 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 67172410 ps |
| CPU time | 1.34 seconds |
| Started | Jan 17 12:31:15 PM PST 24 |
| Finished | Jan 17 12:31:20 PM PST 24 |
| Peak memory | 205924 kb |
| Host | smart-c9334d67-2757-40c9-a836-2346aa513850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009362879 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou tstanding.3009362879 |
| Directory | /workspace/4.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_tl_errors.1217162004 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 63454457 ps |
| CPU time | 2.54 seconds |
| Started | Jan 17 12:31:19 PM PST 24 |
| Finished | Jan 17 12:31:24 PM PST 24 |
| Peak memory | 214308 kb |
| Host | smart-f417ffc2-738e-4ab2-a656-55fbd0a95d16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217162004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1217162004 |
| Directory | /workspace/4.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1453045467 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 162170735 ps |
| CPU time | 2.36 seconds |
| Started | Jan 17 12:31:13 PM PST 24 |
| Finished | Jan 17 12:31:18 PM PST 24 |
| Peak memory | 205948 kb |
| Host | smart-fffff399-fd4e-4158-8c59-6068b0758170 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453045467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1453045467 |
| Directory | /workspace/4.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.edn_intr_test.1585647608 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 27237539 ps |
| CPU time | 0.84 seconds |
| Started | Jan 17 12:31:27 PM PST 24 |
| Finished | Jan 17 12:31:32 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-b328d7c4-b3cb-44d2-8a78-f27f63100d93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585647608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1585647608 |
| Directory | /workspace/40.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.edn_intr_test.3080697310 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 15769523 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 12:31:16 PM PST 24 |
| Finished | Jan 17 12:31:25 PM PST 24 |
| Peak memory | 205952 kb |
| Host | smart-eba7beaa-fd89-49fe-b54c-b846591d7b95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080697310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3080697310 |
| Directory | /workspace/41.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.edn_intr_test.1038200777 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 34908258 ps |
| CPU time | 0.77 seconds |
| Started | Jan 17 12:31:21 PM PST 24 |
| Finished | Jan 17 12:31:26 PM PST 24 |
| Peak memory | 205760 kb |
| Host | smart-7c5a5038-938f-426c-a155-3a4be2499236 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038200777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1038200777 |
| Directory | /workspace/42.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.edn_intr_test.701945229 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 100924005 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 12:31:39 PM PST 24 |
| Finished | Jan 17 12:31:42 PM PST 24 |
| Peak memory | 205980 kb |
| Host | smart-812a6cd4-e1f2-474e-b70c-1681b67cb42c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701945229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.701945229 |
| Directory | /workspace/43.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.edn_intr_test.2636889783 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 18149703 ps |
| CPU time | 0.81 seconds |
| Started | Jan 17 12:31:26 PM PST 24 |
| Finished | Jan 17 12:31:29 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-96df07bc-a88c-4a01-9ddf-bb55714d5ece |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636889783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2636889783 |
| Directory | /workspace/44.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.edn_intr_test.1198013485 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 31441194 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 12:31:31 PM PST 24 |
| Finished | Jan 17 12:31:36 PM PST 24 |
| Peak memory | 206264 kb |
| Host | smart-1e431d70-7962-4b65-93d3-2ad045cbfade |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198013485 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1198013485 |
| Directory | /workspace/45.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.edn_intr_test.2253364815 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 20004284 ps |
| CPU time | 0.81 seconds |
| Started | Jan 17 12:31:18 PM PST 24 |
| Finished | Jan 17 12:31:21 PM PST 24 |
| Peak memory | 205776 kb |
| Host | smart-0accb098-522b-40f5-bfb2-f0320038a1c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253364815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2253364815 |
| Directory | /workspace/46.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.edn_intr_test.963116980 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 21309484 ps |
| CPU time | 0.81 seconds |
| Started | Jan 17 12:31:40 PM PST 24 |
| Finished | Jan 17 12:31:43 PM PST 24 |
| Peak memory | 205936 kb |
| Host | smart-419e4426-ce21-4193-903d-a75e265e402d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963116980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.963116980 |
| Directory | /workspace/47.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.edn_intr_test.2563052895 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 18618772 ps |
| CPU time | 0.78 seconds |
| Started | Jan 17 12:31:46 PM PST 24 |
| Finished | Jan 17 12:31:52 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-35694279-48f8-4d3d-b3e8-832a12f9e763 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563052895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2563052895 |
| Directory | /workspace/48.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.edn_intr_test.4092203829 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 15690690 ps |
| CPU time | 0.8 seconds |
| Started | Jan 17 12:31:37 PM PST 24 |
| Finished | Jan 17 12:31:40 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-abedca06-6933-4018-95b6-25bccbd35b51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092203829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.4092203829 |
| Directory | /workspace/49.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.769828381 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 20021096 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 12:31:21 PM PST 24 |
| Finished | Jan 17 12:31:23 PM PST 24 |
| Peak memory | 214172 kb |
| Host | smart-6602fd23-bb23-44e2-8f9f-ea4c45cb0782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769828381 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.769828381 |
| Directory | /workspace/5.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.edn_csr_rw.2780404734 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 22088450 ps |
| CPU time | 0.81 seconds |
| Started | Jan 17 12:31:09 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205816 kb |
| Host | smart-f39aede7-3b66-489c-98f0-5c74064be4b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780404734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2780404734 |
| Directory | /workspace/5.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.edn_intr_test.3423755264 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 23465444 ps |
| CPU time | 0.8 seconds |
| Started | Jan 17 12:31:25 PM PST 24 |
| Finished | Jan 17 12:31:26 PM PST 24 |
| Peak memory | 205776 kb |
| Host | smart-a9a6a3f8-ce32-4a67-8be5-949773d98d9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423755264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.3423755264 |
| Directory | /workspace/5.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1431728856 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 67863364 ps |
| CPU time | 1.05 seconds |
| Started | Jan 17 12:31:12 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205956 kb |
| Host | smart-13432adb-c1a6-4d13-87fe-04a73da5816e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431728856 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou tstanding.1431728856 |
| Directory | /workspace/5.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.edn_tl_errors.1848470302 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 94155968 ps |
| CPU time | 1.47 seconds |
| Started | Jan 17 12:31:26 PM PST 24 |
| Finished | Jan 17 12:31:31 PM PST 24 |
| Peak memory | 214300 kb |
| Host | smart-a4e5c5dc-5ca8-40fc-b4a9-85af9c596c4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848470302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1848470302 |
| Directory | /workspace/5.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2726183282 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 590022272 ps |
| CPU time | 2.69 seconds |
| Started | Jan 17 12:31:12 PM PST 24 |
| Finished | Jan 17 12:31:18 PM PST 24 |
| Peak memory | 205964 kb |
| Host | smart-36ccc0ad-dc74-4207-9023-a0301176696f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726183282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2726183282 |
| Directory | /workspace/5.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3743695975 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 84088869 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 12:31:24 PM PST 24 |
| Finished | Jan 17 12:31:26 PM PST 24 |
| Peak memory | 206008 kb |
| Host | smart-81c5b641-88f0-4a18-b1d9-88797389a097 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743695975 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3743695975 |
| Directory | /workspace/6.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.edn_csr_rw.2605784490 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 24329783 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 12:31:25 PM PST 24 |
| Finished | Jan 17 12:31:29 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-2385af2b-d46f-4ba9-89b7-d4640a9c3577 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605784490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2605784490 |
| Directory | /workspace/6.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.edn_intr_test.1784716100 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 23110210 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 12:31:20 PM PST 24 |
| Finished | Jan 17 12:31:23 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-66c45830-8ea0-40b6-88fb-666ce8b4ae26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784716100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1784716100 |
| Directory | /workspace/6.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.359476608 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 35718416 ps |
| CPU time | 1.42 seconds |
| Started | Jan 17 12:31:29 PM PST 24 |
| Finished | Jan 17 12:31:35 PM PST 24 |
| Peak memory | 206088 kb |
| Host | smart-dc1b0a3b-e26d-4af3-b1ee-f1944d942068 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359476608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out standing.359476608 |
| Directory | /workspace/6.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.edn_tl_errors.2293039894 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 297703140 ps |
| CPU time | 2.64 seconds |
| Started | Jan 17 12:31:09 PM PST 24 |
| Finished | Jan 17 12:31:18 PM PST 24 |
| Peak memory | 214228 kb |
| Host | smart-8e881afd-f3ce-4707-aac4-216806dbdde6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293039894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2293039894 |
| Directory | /workspace/6.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2791267997 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 289242773 ps |
| CPU time | 2.36 seconds |
| Started | Jan 17 12:31:20 PM PST 24 |
| Finished | Jan 17 12:31:24 PM PST 24 |
| Peak memory | 205860 kb |
| Host | smart-6e4038fb-54b1-452a-b8a3-5b96cfd0709f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791267997 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2791267997 |
| Directory | /workspace/6.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1822578105 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 34495305 ps |
| CPU time | 1.36 seconds |
| Started | Jan 17 12:31:43 PM PST 24 |
| Finished | Jan 17 12:31:45 PM PST 24 |
| Peak memory | 214308 kb |
| Host | smart-4a92be87-25da-4fd7-ae5f-93f46d044dc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822578105 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1822578105 |
| Directory | /workspace/7.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.edn_csr_rw.1207674946 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 55434369 ps |
| CPU time | 0.81 seconds |
| Started | Jan 17 12:31:05 PM PST 24 |
| Finished | Jan 17 12:31:07 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-89d569e3-bb4a-4a65-99b5-46b2df7b90d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207674946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1207674946 |
| Directory | /workspace/7.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.edn_intr_test.1752115825 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 36897789 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 12:31:25 PM PST 24 |
| Finished | Jan 17 12:31:27 PM PST 24 |
| Peak memory | 205948 kb |
| Host | smart-380bce15-6820-4e76-a0af-13001b2c9b34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752115825 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1752115825 |
| Directory | /workspace/7.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1890967019 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 174159678 ps |
| CPU time | 1.39 seconds |
| Started | Jan 17 12:31:25 PM PST 24 |
| Finished | Jan 17 12:31:27 PM PST 24 |
| Peak memory | 205948 kb |
| Host | smart-a106469e-62a0-4716-b36b-42bf9850e695 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890967019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou tstanding.1890967019 |
| Directory | /workspace/7.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.edn_tl_errors.330761424 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 756240899 ps |
| CPU time | 3.46 seconds |
| Started | Jan 17 12:31:06 PM PST 24 |
| Finished | Jan 17 12:31:10 PM PST 24 |
| Peak memory | 214272 kb |
| Host | smart-0d031167-12a8-40ec-abbf-073319c204dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330761424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.330761424 |
| Directory | /workspace/7.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1186766638 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 167313159 ps |
| CPU time | 1.53 seconds |
| Started | Jan 17 12:31:10 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205972 kb |
| Host | smart-de2b1795-9747-4d00-ad09-6019ae7d23e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186766638 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1186766638 |
| Directory | /workspace/7.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3129318638 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 22529601 ps |
| CPU time | 1.19 seconds |
| Started | Jan 17 12:31:16 PM PST 24 |
| Finished | Jan 17 12:31:20 PM PST 24 |
| Peak memory | 214256 kb |
| Host | smart-093bd1e7-e9e8-46dd-8c08-9725aeedded2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129318638 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3129318638 |
| Directory | /workspace/8.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.edn_csr_rw.2419458972 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 13185603 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 12:31:22 PM PST 24 |
| Finished | Jan 17 12:31:24 PM PST 24 |
| Peak memory | 205960 kb |
| Host | smart-68368243-ee9c-4b52-ae38-a3691713a008 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419458972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2419458972 |
| Directory | /workspace/8.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.edn_intr_test.2678657598 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 51715715 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 12:31:16 PM PST 24 |
| Finished | Jan 17 12:31:20 PM PST 24 |
| Peak memory | 205892 kb |
| Host | smart-b5b190fc-397f-4e3f-b8fa-39b153c1426b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678657598 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2678657598 |
| Directory | /workspace/8.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1130666795 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 16353217 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 12:31:28 PM PST 24 |
| Finished | Jan 17 12:31:33 PM PST 24 |
| Peak memory | 205936 kb |
| Host | smart-23ba76cc-94b2-4e3b-b796-bde67f9389ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130666795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou tstanding.1130666795 |
| Directory | /workspace/8.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.edn_tl_errors.3293175543 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 78667510 ps |
| CPU time | 2.44 seconds |
| Started | Jan 17 12:31:10 PM PST 24 |
| Finished | Jan 17 12:31:18 PM PST 24 |
| Peak memory | 214328 kb |
| Host | smart-1d5de829-e704-4ceb-a6b8-65a10de214d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293175543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3293175543 |
| Directory | /workspace/8.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1281182015 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 142360659 ps |
| CPU time | 1.45 seconds |
| Started | Jan 17 12:31:18 PM PST 24 |
| Finished | Jan 17 12:31:21 PM PST 24 |
| Peak memory | 206016 kb |
| Host | smart-52383569-2b3d-44b1-8e4e-c3181851bc55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281182015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1281182015 |
| Directory | /workspace/8.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1257122004 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 67339057 ps |
| CPU time | 1.19 seconds |
| Started | Jan 17 12:31:10 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 214264 kb |
| Host | smart-84a486cb-452c-4419-b1d8-ba8c7b89bea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257122004 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1257122004 |
| Directory | /workspace/9.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.edn_csr_rw.2654785670 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 43549191 ps |
| CPU time | 0.82 seconds |
| Started | Jan 17 12:31:13 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 205936 kb |
| Host | smart-ac0d2b41-969f-469d-8538-864c703f3a28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654785670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2654785670 |
| Directory | /workspace/9.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.edn_intr_test.2489177898 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 35028687 ps |
| CPU time | 0.79 seconds |
| Started | Jan 17 12:31:21 PM PST 24 |
| Finished | Jan 17 12:31:23 PM PST 24 |
| Peak memory | 205748 kb |
| Host | smart-e1db4d5f-6ee2-4103-8bac-f79788184759 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489177898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2489177898 |
| Directory | /workspace/9.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1699555442 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 217151382 ps |
| CPU time | 1.29 seconds |
| Started | Jan 17 12:31:14 PM PST 24 |
| Finished | Jan 17 12:31:17 PM PST 24 |
| Peak memory | 206068 kb |
| Host | smart-afebad11-9c2d-40a4-9347-160b3cb7bc25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699555442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou tstanding.1699555442 |
| Directory | /workspace/9.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.edn_tl_errors.137482952 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 40185292 ps |
| CPU time | 2.45 seconds |
| Started | Jan 17 12:31:09 PM PST 24 |
| Finished | Jan 17 12:31:18 PM PST 24 |
| Peak memory | 214260 kb |
| Host | smart-10100c21-7182-4087-bdb4-4a798d5a1d67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137482952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.137482952 |
| Directory | /workspace/9.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.939925544 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 62350165 ps |
| CPU time | 1.46 seconds |
| Started | Jan 17 12:31:16 PM PST 24 |
| Finished | Jan 17 12:31:20 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-634daf1e-ce89-4ade-9b86-de972d9d8afd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939925544 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.939925544 |
| Directory | /workspace/9.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.edn_alert_test.3529289954 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 16937407 ps |
| CPU time | 0.82 seconds |
| Started | Jan 17 01:35:18 PM PST 24 |
| Finished | Jan 17 01:35:24 PM PST 24 |
| Peak memory | 204456 kb |
| Host | smart-a9c32d83-6210-480d-93df-256a60c303fe |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529289954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3529289954 |
| Directory | /workspace/0.edn_alert_test/latest |
| Test location | /workspace/coverage/default/0.edn_disable_auto_req_mode.3488833502 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 35732356 ps |
| CPU time | 1.02 seconds |
| Started | Jan 17 01:35:15 PM PST 24 |
| Finished | Jan 17 01:35:17 PM PST 24 |
| Peak memory | 214552 kb |
| Host | smart-e66e67f8-1249-4185-bdfb-02fe886d3082 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488833502 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di sable_auto_req_mode.3488833502 |
| Directory | /workspace/0.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/0.edn_err.2907296782 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 34507389 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:35:19 PM PST 24 |
| Finished | Jan 17 01:35:24 PM PST 24 |
| Peak memory | 215860 kb |
| Host | smart-2dde9f50-fbd5-4fd4-816a-2eb3b8048d6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2907296782 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2907296782 |
| Directory | /workspace/0.edn_err/latest |
| Test location | /workspace/coverage/default/0.edn_genbits.3128117984 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 53977216 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 01:35:09 PM PST 24 |
| Finished | Jan 17 01:35:11 PM PST 24 |
| Peak memory | 205448 kb |
| Host | smart-b2d943f0-ceba-426f-9ef6-e1aa9457035d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3128117984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3128117984 |
| Directory | /workspace/0.edn_genbits/latest |
| Test location | /workspace/coverage/default/0.edn_intr.1048579587 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 27947493 ps |
| CPU time | 0.91 seconds |
| Started | Jan 17 01:35:18 PM PST 24 |
| Finished | Jan 17 01:35:24 PM PST 24 |
| Peak memory | 214164 kb |
| Host | smart-644af97a-6643-45cb-bd55-af26234e6d0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1048579587 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1048579587 |
| Directory | /workspace/0.edn_intr/latest |
| Test location | /workspace/coverage/default/0.edn_sec_cm.1617280871 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 676766824 ps |
| CPU time | 5.58 seconds |
| Started | Jan 17 01:35:17 PM PST 24 |
| Finished | Jan 17 01:35:29 PM PST 24 |
| Peak memory | 235208 kb |
| Host | smart-a771ebde-3271-4743-971b-5ce73624aa11 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617280871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1617280871 |
| Directory | /workspace/0.edn_sec_cm/latest |
| Test location | /workspace/coverage/default/0.edn_smoke.4045128981 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 13318706 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 01:35:12 PM PST 24 |
| Finished | Jan 17 01:35:15 PM PST 24 |
| Peak memory | 204512 kb |
| Host | smart-48fa06bf-fbea-4832-b863-b4151945d234 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4045128981 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.4045128981 |
| Directory | /workspace/0.edn_smoke/latest |
| Test location | /workspace/coverage/default/0.edn_stress_all.1997689470 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 660194632 ps |
| CPU time | 2.07 seconds |
| Started | Jan 17 01:35:20 PM PST 24 |
| Finished | Jan 17 01:35:25 PM PST 24 |
| Peak memory | 205572 kb |
| Host | smart-2447edcb-ea32-483b-ad65-3651d57f4d16 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997689470 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1997689470 |
| Directory | /workspace/0.edn_stress_all/latest |
| Test location | /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2414738175 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 68720911004 ps |
| CPU time | 594.64 seconds |
| Started | Jan 17 01:35:20 PM PST 24 |
| Finished | Jan 17 01:45:18 PM PST 24 |
| Peak memory | 215644 kb |
| Host | smart-f74c2f3c-b26c-4b66-8399-d03762b71b74 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414738175 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2414738175 |
| Directory | /workspace/0.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.edn_alert_test.2095403110 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 52044333 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 01:35:41 PM PST 24 |
| Finished | Jan 17 01:35:44 PM PST 24 |
| Peak memory | 205096 kb |
| Host | smart-2db32044-ce89-401c-9b98-099bd40ab374 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095403110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2095403110 |
| Directory | /workspace/1.edn_alert_test/latest |
| Test location | /workspace/coverage/default/1.edn_disable_auto_req_mode.1600335533 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 59540783 ps |
| CPU time | 1.09 seconds |
| Started | Jan 17 01:35:30 PM PST 24 |
| Finished | Jan 17 01:35:32 PM PST 24 |
| Peak memory | 214480 kb |
| Host | smart-37058523-24db-431d-be2d-6676111e4bdc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600335533 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di sable_auto_req_mode.1600335533 |
| Directory | /workspace/1.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/1.edn_err.2073604193 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 75084305 ps |
| CPU time | 1.23 seconds |
| Started | Jan 17 01:35:23 PM PST 24 |
| Finished | Jan 17 01:35:25 PM PST 24 |
| Peak memory | 222192 kb |
| Host | smart-a161c3f4-a6c9-40ea-b94a-f5bdc832c5aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2073604193 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2073604193 |
| Directory | /workspace/1.edn_err/latest |
| Test location | /workspace/coverage/default/1.edn_genbits.1113288021 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 27564393 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:35:22 PM PST 24 |
| Finished | Jan 17 01:35:24 PM PST 24 |
| Peak memory | 204864 kb |
| Host | smart-3864317c-1057-43b0-814b-a2c116890f76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1113288021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1113288021 |
| Directory | /workspace/1.edn_genbits/latest |
| Test location | /workspace/coverage/default/1.edn_intr.422834611 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 19874529 ps |
| CPU time | 1.05 seconds |
| Started | Jan 17 01:35:23 PM PST 24 |
| Finished | Jan 17 01:35:25 PM PST 24 |
| Peak memory | 214472 kb |
| Host | smart-bc6e06fc-4fa2-46ad-aa9a-9a2b2af60805 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=422834611 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.422834611 |
| Directory | /workspace/1.edn_intr/latest |
| Test location | /workspace/coverage/default/1.edn_regwen.946679064 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 39228521 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:35:24 PM PST 24 |
| Finished | Jan 17 01:35:25 PM PST 24 |
| Peak memory | 204660 kb |
| Host | smart-a61d41d3-d9b8-41a3-a7b0-60f65909483a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=946679064 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.946679064 |
| Directory | /workspace/1.edn_regwen/latest |
| Test location | /workspace/coverage/default/1.edn_smoke.873743890 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 21140887 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:35:24 PM PST 24 |
| Finished | Jan 17 01:35:26 PM PST 24 |
| Peak memory | 204736 kb |
| Host | smart-76527d25-ef98-425f-9beb-d506005e8b9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=873743890 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.873743890 |
| Directory | /workspace/1.edn_smoke/latest |
| Test location | /workspace/coverage/default/10.edn_alert.3717485408 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 34467926 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:37:01 PM PST 24 |
| Finished | Jan 17 01:37:03 PM PST 24 |
| Peak memory | 205296 kb |
| Host | smart-48add5b0-8a09-4bd6-8b40-3b7846eb6fc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3717485408 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3717485408 |
| Directory | /workspace/10.edn_alert/latest |
| Test location | /workspace/coverage/default/10.edn_alert_test.1946904084 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 66609294 ps |
| CPU time | 0.81 seconds |
| Started | Jan 17 01:37:00 PM PST 24 |
| Finished | Jan 17 01:37:01 PM PST 24 |
| Peak memory | 205212 kb |
| Host | smart-c0844de6-cc40-4965-a208-8b33ccb86c63 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946904084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1946904084 |
| Directory | /workspace/10.edn_alert_test/latest |
| Test location | /workspace/coverage/default/10.edn_disable.2800165976 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 14633364 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:36:59 PM PST 24 |
| Finished | Jan 17 01:37:00 PM PST 24 |
| Peak memory | 214444 kb |
| Host | smart-229f3c37-2e1b-40f8-96a7-62ab8420ccca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800165976 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2800165976 |
| Directory | /workspace/10.edn_disable/latest |
| Test location | /workspace/coverage/default/10.edn_disable_auto_req_mode.794607198 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 29101438 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:37:00 PM PST 24 |
| Finished | Jan 17 01:37:02 PM PST 24 |
| Peak memory | 214464 kb |
| Host | smart-b31ece90-8839-4f73-953d-120573e0416b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794607198 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_di sable_auto_req_mode.794607198 |
| Directory | /workspace/10.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/10.edn_err.3202145884 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 25574174 ps |
| CPU time | 1.09 seconds |
| Started | Jan 17 01:36:49 PM PST 24 |
| Finished | Jan 17 01:36:51 PM PST 24 |
| Peak memory | 215996 kb |
| Host | smart-eeb84e9c-c6bc-47b5-b345-ee6ae0ab944f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3202145884 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3202145884 |
| Directory | /workspace/10.edn_err/latest |
| Test location | /workspace/coverage/default/10.edn_genbits.33058082 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 26624827 ps |
| CPU time | 1.3 seconds |
| Started | Jan 17 01:36:46 PM PST 24 |
| Finished | Jan 17 01:36:51 PM PST 24 |
| Peak memory | 205648 kb |
| Host | smart-972c52c2-1165-4497-8d67-f0546a5df594 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33058082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.33058082 |
| Directory | /workspace/10.edn_genbits/latest |
| Test location | /workspace/coverage/default/10.edn_smoke.343814179 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 48113829 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:36:46 PM PST 24 |
| Finished | Jan 17 01:36:51 PM PST 24 |
| Peak memory | 204744 kb |
| Host | smart-1e928fcb-7238-4d7b-902f-880f2e50ab2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=343814179 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.343814179 |
| Directory | /workspace/10.edn_smoke/latest |
| Test location | /workspace/coverage/default/10.edn_stress_all.230245797 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 190996090 ps |
| CPU time | 2.42 seconds |
| Started | Jan 17 01:36:46 PM PST 24 |
| Finished | Jan 17 01:36:52 PM PST 24 |
| Peak memory | 205556 kb |
| Host | smart-fc810299-a99e-4a24-b1dc-e483d41b3a61 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230245797 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.230245797 |
| Directory | /workspace/10.edn_stress_all/latest |
| Test location | /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1947513631 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 31625743055 ps |
| CPU time | 354.31 seconds |
| Started | Jan 17 01:36:47 PM PST 24 |
| Finished | Jan 17 01:42:44 PM PST 24 |
| Peak memory | 215032 kb |
| Host | smart-aa8238a3-7ddc-43ac-a01b-1d3fd52ddf8b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947513631 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1947513631 |
| Directory | /workspace/10.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/102.edn_genbits.1815196463 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 35413003 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:40:31 PM PST 24 |
| Finished | Jan 17 01:40:33 PM PST 24 |
| Peak memory | 205200 kb |
| Host | smart-4fe1722d-42d2-4c8c-a08e-282af849f696 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1815196463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1815196463 |
| Directory | /workspace/102.edn_genbits/latest |
| Test location | /workspace/coverage/default/103.edn_genbits.3810315782 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 92041287 ps |
| CPU time | 1.1 seconds |
| Started | Jan 17 01:40:29 PM PST 24 |
| Finished | Jan 17 01:40:31 PM PST 24 |
| Peak memory | 205308 kb |
| Host | smart-4b9887b1-45db-438c-8d13-79f58093ad5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3810315782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3810315782 |
| Directory | /workspace/103.edn_genbits/latest |
| Test location | /workspace/coverage/default/104.edn_genbits.475461389 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 23572158 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:40:26 PM PST 24 |
| Finished | Jan 17 01:40:28 PM PST 24 |
| Peak memory | 204972 kb |
| Host | smart-701175bc-10dc-4ecb-9a40-555224185408 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=475461389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.475461389 |
| Directory | /workspace/104.edn_genbits/latest |
| Test location | /workspace/coverage/default/105.edn_genbits.4216100889 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 33128158 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:40:28 PM PST 24 |
| Finished | Jan 17 01:40:30 PM PST 24 |
| Peak memory | 204904 kb |
| Host | smart-3b9efe00-65d8-4615-8b71-027f4e03b041 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4216100889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.4216100889 |
| Directory | /workspace/105.edn_genbits/latest |
| Test location | /workspace/coverage/default/107.edn_genbits.2795439396 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 33315150 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 01:40:24 PM PST 24 |
| Finished | Jan 17 01:40:26 PM PST 24 |
| Peak memory | 205420 kb |
| Host | smart-b9b63f7b-757d-4f1e-ac71-9551747a2167 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2795439396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2795439396 |
| Directory | /workspace/107.edn_genbits/latest |
| Test location | /workspace/coverage/default/108.edn_genbits.402448848 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 40446647 ps |
| CPU time | 1.69 seconds |
| Started | Jan 17 01:40:24 PM PST 24 |
| Finished | Jan 17 01:40:27 PM PST 24 |
| Peak memory | 214176 kb |
| Host | smart-f396bcb9-fcbc-4760-b927-bc9e4594d83e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=402448848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.402448848 |
| Directory | /workspace/108.edn_genbits/latest |
| Test location | /workspace/coverage/default/109.edn_genbits.3168143093 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 53202480 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:40:25 PM PST 24 |
| Finished | Jan 17 01:40:27 PM PST 24 |
| Peak memory | 205372 kb |
| Host | smart-28d08b67-bf15-4668-9bd1-4231207b023a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3168143093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3168143093 |
| Directory | /workspace/109.edn_genbits/latest |
| Test location | /workspace/coverage/default/11.edn_alert.18721125 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 228886064 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:37:00 PM PST 24 |
| Finished | Jan 17 01:37:01 PM PST 24 |
| Peak memory | 205916 kb |
| Host | smart-c75d7a91-01d8-41c9-b7ce-548d158fd968 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=18721125 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.18721125 |
| Directory | /workspace/11.edn_alert/latest |
| Test location | /workspace/coverage/default/11.edn_alert_test.3255898720 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 14717007 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 01:36:49 PM PST 24 |
| Finished | Jan 17 01:36:51 PM PST 24 |
| Peak memory | 205092 kb |
| Host | smart-401d70f2-e569-4acc-960c-78a1d39a9feb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255898720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3255898720 |
| Directory | /workspace/11.edn_alert_test/latest |
| Test location | /workspace/coverage/default/11.edn_disable_auto_req_mode.3302628749 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 30077009 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 01:37:01 PM PST 24 |
| Finished | Jan 17 01:37:03 PM PST 24 |
| Peak memory | 214472 kb |
| Host | smart-c7ce618c-212c-4c0e-8ba0-2eb209ec4c26 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302628749 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d isable_auto_req_mode.3302628749 |
| Directory | /workspace/11.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/11.edn_err.169343467 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 29529863 ps |
| CPU time | 1.13 seconds |
| Started | Jan 17 01:36:53 PM PST 24 |
| Finished | Jan 17 01:36:55 PM PST 24 |
| Peak memory | 222040 kb |
| Host | smart-1c4a88a3-f6c7-421e-8c4b-1de8a614ae80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=169343467 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.169343467 |
| Directory | /workspace/11.edn_err/latest |
| Test location | /workspace/coverage/default/11.edn_genbits.188646960 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 61033251 ps |
| CPU time | 1.13 seconds |
| Started | Jan 17 01:36:59 PM PST 24 |
| Finished | Jan 17 01:37:01 PM PST 24 |
| Peak memory | 214164 kb |
| Host | smart-480ac8ad-c757-43c5-a57b-f3502d2e54dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=188646960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.188646960 |
| Directory | /workspace/11.edn_genbits/latest |
| Test location | /workspace/coverage/default/11.edn_intr.2735510252 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 19545611 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:37:00 PM PST 24 |
| Finished | Jan 17 01:37:02 PM PST 24 |
| Peak memory | 214460 kb |
| Host | smart-4f9ae02b-87a3-4b15-b86c-e605b8bb4006 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2735510252 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2735510252 |
| Directory | /workspace/11.edn_intr/latest |
| Test location | /workspace/coverage/default/11.edn_smoke.1278560382 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 34937910 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 01:36:55 PM PST 24 |
| Finished | Jan 17 01:36:56 PM PST 24 |
| Peak memory | 204792 kb |
| Host | smart-6cf61d78-e626-454d-8faf-455ff80b9a4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1278560382 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1278560382 |
| Directory | /workspace/11.edn_smoke/latest |
| Test location | /workspace/coverage/default/11.edn_stress_all.4110548756 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 212812045 ps |
| CPU time | 3.3 seconds |
| Started | Jan 17 01:36:48 PM PST 24 |
| Finished | Jan 17 01:36:53 PM PST 24 |
| Peak memory | 205860 kb |
| Host | smart-dc393fee-dbfe-4661-9aeb-2d6139dea029 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110548756 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.4110548756 |
| Directory | /workspace/11.edn_stress_all/latest |
| Test location | /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2366682786 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 227952341401 ps |
| CPU time | 1581.38 seconds |
| Started | Jan 17 01:37:01 PM PST 24 |
| Finished | Jan 17 02:03:23 PM PST 24 |
| Peak memory | 220592 kb |
| Host | smart-ae566d6d-2481-48c3-a130-25be71636537 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366682786 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2366682786 |
| Directory | /workspace/11.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/111.edn_genbits.719177091 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 17753364 ps |
| CPU time | 1.05 seconds |
| Started | Jan 17 01:40:28 PM PST 24 |
| Finished | Jan 17 01:40:30 PM PST 24 |
| Peak memory | 205512 kb |
| Host | smart-f0c2c8b5-ca1e-46e2-a9c0-3f708397b280 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=719177091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.719177091 |
| Directory | /workspace/111.edn_genbits/latest |
| Test location | /workspace/coverage/default/112.edn_genbits.4284245759 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 29566555 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:40:31 PM PST 24 |
| Finished | Jan 17 01:40:33 PM PST 24 |
| Peak memory | 205376 kb |
| Host | smart-7cf1a6d1-556f-4fd3-9e92-29bc3527ed49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4284245759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.4284245759 |
| Directory | /workspace/112.edn_genbits/latest |
| Test location | /workspace/coverage/default/114.edn_genbits.1712473616 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 60608695 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:40:26 PM PST 24 |
| Finished | Jan 17 01:40:28 PM PST 24 |
| Peak memory | 205224 kb |
| Host | smart-e68fbdc8-63e8-4667-8a9b-1ab4778ad28a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1712473616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1712473616 |
| Directory | /workspace/114.edn_genbits/latest |
| Test location | /workspace/coverage/default/115.edn_genbits.983414769 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 255378162 ps |
| CPU time | 3.68 seconds |
| Started | Jan 17 01:40:32 PM PST 24 |
| Finished | Jan 17 01:40:36 PM PST 24 |
| Peak memory | 214128 kb |
| Host | smart-0a1a9cbe-6ead-4b6a-bcec-e5dbc26b5cba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=983414769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.983414769 |
| Directory | /workspace/115.edn_genbits/latest |
| Test location | /workspace/coverage/default/116.edn_genbits.2066579345 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 53178099 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:40:27 PM PST 24 |
| Finished | Jan 17 01:40:29 PM PST 24 |
| Peak memory | 204932 kb |
| Host | smart-b6bba756-ec1b-4ae2-b778-4528f78e811d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2066579345 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2066579345 |
| Directory | /workspace/116.edn_genbits/latest |
| Test location | /workspace/coverage/default/117.edn_genbits.3547630355 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 13842995 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:40:31 PM PST 24 |
| Finished | Jan 17 01:40:33 PM PST 24 |
| Peak memory | 205544 kb |
| Host | smart-2769932a-25f8-4e79-8f94-6374549e53f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3547630355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3547630355 |
| Directory | /workspace/117.edn_genbits/latest |
| Test location | /workspace/coverage/default/118.edn_genbits.1449752711 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 120096839 ps |
| CPU time | 1.6 seconds |
| Started | Jan 17 01:40:33 PM PST 24 |
| Finished | Jan 17 01:40:35 PM PST 24 |
| Peak memory | 214148 kb |
| Host | smart-c239f6a9-236b-4a30-bc87-2adc41a71237 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1449752711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1449752711 |
| Directory | /workspace/118.edn_genbits/latest |
| Test location | /workspace/coverage/default/119.edn_genbits.2969637120 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 16117784 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 01:40:32 PM PST 24 |
| Finished | Jan 17 01:40:34 PM PST 24 |
| Peak memory | 214124 kb |
| Host | smart-0f13a34b-cc92-4814-9b3f-e49437965455 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2969637120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2969637120 |
| Directory | /workspace/119.edn_genbits/latest |
| Test location | /workspace/coverage/default/12.edn_alert.688098114 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 53016940 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:37:03 PM PST 24 |
| Finished | Jan 17 01:37:07 PM PST 24 |
| Peak memory | 205100 kb |
| Host | smart-0923b171-9b4b-4a49-9e02-710173203580 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=688098114 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.688098114 |
| Directory | /workspace/12.edn_alert/latest |
| Test location | /workspace/coverage/default/12.edn_alert_test.4089014102 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 94468717 ps |
| CPU time | 0.82 seconds |
| Started | Jan 17 01:37:02 PM PST 24 |
| Finished | Jan 17 01:37:05 PM PST 24 |
| Peak memory | 204516 kb |
| Host | smart-40037a51-7f38-40f5-96a6-d35ad98ff091 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089014102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.4089014102 |
| Directory | /workspace/12.edn_alert_test/latest |
| Test location | /workspace/coverage/default/12.edn_disable.2037401015 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 43553689 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 01:37:04 PM PST 24 |
| Finished | Jan 17 01:37:08 PM PST 24 |
| Peak memory | 214288 kb |
| Host | smart-2f580d8d-afc7-4e0c-ba5b-b47307f1fb05 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037401015 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2037401015 |
| Directory | /workspace/12.edn_disable/latest |
| Test location | /workspace/coverage/default/12.edn_disable_auto_req_mode.3583694520 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 83668504 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 01:37:03 PM PST 24 |
| Finished | Jan 17 01:37:07 PM PST 24 |
| Peak memory | 214468 kb |
| Host | smart-de1f5695-20c8-49ea-ad9b-06e6ebabe9ae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583694520 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d isable_auto_req_mode.3583694520 |
| Directory | /workspace/12.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/12.edn_err.3987816602 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 44652061 ps |
| CPU time | 1.19 seconds |
| Started | Jan 17 01:37:01 PM PST 24 |
| Finished | Jan 17 01:37:04 PM PST 24 |
| Peak memory | 221936 kb |
| Host | smart-5548642f-cd5e-4f3a-833b-e1802236a1d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3987816602 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3987816602 |
| Directory | /workspace/12.edn_err/latest |
| Test location | /workspace/coverage/default/12.edn_genbits.245895099 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 46646170 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:37:02 PM PST 24 |
| Finished | Jan 17 01:37:05 PM PST 24 |
| Peak memory | 204972 kb |
| Host | smart-f1152f53-33a1-4948-97eb-048f0aa76f8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=245895099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.245895099 |
| Directory | /workspace/12.edn_genbits/latest |
| Test location | /workspace/coverage/default/12.edn_intr.523330875 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 31528619 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:37:04 PM PST 24 |
| Finished | Jan 17 01:37:07 PM PST 24 |
| Peak memory | 221432 kb |
| Host | smart-58a49e2c-9ef8-4d94-8eee-a9f9bef65d2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=523330875 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.523330875 |
| Directory | /workspace/12.edn_intr/latest |
| Test location | /workspace/coverage/default/12.edn_smoke.3757052794 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 21745684 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:36:48 PM PST 24 |
| Finished | Jan 17 01:36:51 PM PST 24 |
| Peak memory | 204652 kb |
| Host | smart-dd0201fb-4446-4a32-bfa5-fa6c8d773d04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3757052794 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3757052794 |
| Directory | /workspace/12.edn_smoke/latest |
| Test location | /workspace/coverage/default/12.edn_stress_all.2931044777 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 213001387 ps |
| CPU time | 4.54 seconds |
| Started | Jan 17 01:37:00 PM PST 24 |
| Finished | Jan 17 01:37:05 PM PST 24 |
| Peak memory | 205928 kb |
| Host | smart-9021de71-05e4-4d1d-bb30-976d99d06084 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931044777 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2931044777 |
| Directory | /workspace/12.edn_stress_all/latest |
| Test location | /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3068489928 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 17131550287 ps |
| CPU time | 420.6 seconds |
| Started | Jan 17 01:36:51 PM PST 24 |
| Finished | Jan 17 01:43:53 PM PST 24 |
| Peak memory | 215232 kb |
| Host | smart-dca7f94e-5b95-4463-a798-d0b817b403c1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068489928 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3068489928 |
| Directory | /workspace/12.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/120.edn_genbits.3238655409 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 53510579 ps |
| CPU time | 1.02 seconds |
| Started | Jan 17 01:40:38 PM PST 24 |
| Finished | Jan 17 01:40:42 PM PST 24 |
| Peak memory | 205476 kb |
| Host | smart-2c21d262-2be9-42c3-ac9c-5c34a0b058fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3238655409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3238655409 |
| Directory | /workspace/120.edn_genbits/latest |
| Test location | /workspace/coverage/default/121.edn_genbits.277608929 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 13829212 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:40:32 PM PST 24 |
| Finished | Jan 17 01:40:34 PM PST 24 |
| Peak memory | 204980 kb |
| Host | smart-289e9924-87b7-49a3-8fec-e53036eaff95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=277608929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.277608929 |
| Directory | /workspace/121.edn_genbits/latest |
| Test location | /workspace/coverage/default/123.edn_genbits.1692776195 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 15872737 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:40:32 PM PST 24 |
| Finished | Jan 17 01:40:34 PM PST 24 |
| Peak memory | 204956 kb |
| Host | smart-493526b1-7823-491c-be5d-2c30a7b85cec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1692776195 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1692776195 |
| Directory | /workspace/123.edn_genbits/latest |
| Test location | /workspace/coverage/default/125.edn_genbits.3434231327 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 16430575 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:40:32 PM PST 24 |
| Finished | Jan 17 01:40:34 PM PST 24 |
| Peak memory | 204848 kb |
| Host | smart-8d84578d-0626-4055-915f-4a6d9f1c3522 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3434231327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3434231327 |
| Directory | /workspace/125.edn_genbits/latest |
| Test location | /workspace/coverage/default/126.edn_genbits.2912487347 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 89021570 ps |
| CPU time | 1.37 seconds |
| Started | Jan 17 01:40:40 PM PST 24 |
| Finished | Jan 17 01:40:44 PM PST 24 |
| Peak memory | 214220 kb |
| Host | smart-328488ca-251c-47f9-a92e-1621b8ec6590 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2912487347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2912487347 |
| Directory | /workspace/126.edn_genbits/latest |
| Test location | /workspace/coverage/default/127.edn_genbits.2992614734 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 35456238 ps |
| CPU time | 1.21 seconds |
| Started | Jan 17 01:40:40 PM PST 24 |
| Finished | Jan 17 01:40:44 PM PST 24 |
| Peak memory | 205220 kb |
| Host | smart-c2fdf0b9-6abd-4b86-85e4-a5c6d96ebf68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2992614734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.2992614734 |
| Directory | /workspace/127.edn_genbits/latest |
| Test location | /workspace/coverage/default/128.edn_genbits.2574026204 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 159662553 ps |
| CPU time | 1.92 seconds |
| Started | Jan 17 01:40:38 PM PST 24 |
| Finished | Jan 17 01:40:43 PM PST 24 |
| Peak memory | 214032 kb |
| Host | smart-a1ce5645-90b0-495b-bc19-70c766176799 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2574026204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2574026204 |
| Directory | /workspace/128.edn_genbits/latest |
| Test location | /workspace/coverage/default/129.edn_genbits.2136288885 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 89791762 ps |
| CPU time | 1.15 seconds |
| Started | Jan 17 01:40:38 PM PST 24 |
| Finished | Jan 17 01:40:41 PM PST 24 |
| Peak memory | 205660 kb |
| Host | smart-f29b64e0-4f5c-41ac-99a6-b12c92e3e636 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136288885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2136288885 |
| Directory | /workspace/129.edn_genbits/latest |
| Test location | /workspace/coverage/default/13.edn_alert.1152593022 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 88556369 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:37:02 PM PST 24 |
| Finished | Jan 17 01:37:05 PM PST 24 |
| Peak memory | 205136 kb |
| Host | smart-64170760-b558-4463-ad32-88f4d4d70ec3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1152593022 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1152593022 |
| Directory | /workspace/13.edn_alert/latest |
| Test location | /workspace/coverage/default/13.edn_disable_auto_req_mode.840411884 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 56377167 ps |
| CPU time | 1.06 seconds |
| Started | Jan 17 01:37:05 PM PST 24 |
| Finished | Jan 17 01:37:08 PM PST 24 |
| Peak memory | 214456 kb |
| Host | smart-210e7e58-2b37-4a70-b1de-17bc3de46ebd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840411884 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di sable_auto_req_mode.840411884 |
| Directory | /workspace/13.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/13.edn_err.2758438725 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 29730909 ps |
| CPU time | 1.06 seconds |
| Started | Jan 17 01:37:06 PM PST 24 |
| Finished | Jan 17 01:37:08 PM PST 24 |
| Peak memory | 221908 kb |
| Host | smart-d3dc0814-d7da-4109-b899-bf956daaf29c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758438725 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2758438725 |
| Directory | /workspace/13.edn_err/latest |
| Test location | /workspace/coverage/default/13.edn_genbits.240706357 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 52888747 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:37:04 PM PST 24 |
| Finished | Jan 17 01:37:07 PM PST 24 |
| Peak memory | 205016 kb |
| Host | smart-c485a98c-b8d1-4922-a508-5c9a73fb210d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240706357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.240706357 |
| Directory | /workspace/13.edn_genbits/latest |
| Test location | /workspace/coverage/default/13.edn_intr.1095529962 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 26545387 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:37:07 PM PST 24 |
| Finished | Jan 17 01:37:15 PM PST 24 |
| Peak memory | 214460 kb |
| Host | smart-bc971d5e-687f-4773-8182-a6b2065d0de5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1095529962 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.1095529962 |
| Directory | /workspace/13.edn_intr/latest |
| Test location | /workspace/coverage/default/13.edn_smoke.1090922988 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 13754828 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:37:08 PM PST 24 |
| Finished | Jan 17 01:37:15 PM PST 24 |
| Peak memory | 205068 kb |
| Host | smart-c6e5880e-ac21-45d8-80f3-6b92ca9e237d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1090922988 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1090922988 |
| Directory | /workspace/13.edn_smoke/latest |
| Test location | /workspace/coverage/default/13.edn_stress_all.135929578 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 155232570 ps |
| CPU time | 3.57 seconds |
| Started | Jan 17 01:37:02 PM PST 24 |
| Finished | Jan 17 01:37:08 PM PST 24 |
| Peak memory | 205956 kb |
| Host | smart-16103e76-e29d-4c42-a7b0-66396a5eb502 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135929578 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.135929578 |
| Directory | /workspace/13.edn_stress_all/latest |
| Test location | /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3191660845 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 20054046226 ps |
| CPU time | 491.17 seconds |
| Started | Jan 17 01:37:00 PM PST 24 |
| Finished | Jan 17 01:45:12 PM PST 24 |
| Peak memory | 215576 kb |
| Host | smart-7f94a45b-0e2c-4ebb-b71e-99e52a62846c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191660845 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3191660845 |
| Directory | /workspace/13.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/130.edn_genbits.3005639191 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 147569033 ps |
| CPU time | 1.18 seconds |
| Started | Jan 17 01:40:44 PM PST 24 |
| Finished | Jan 17 01:40:53 PM PST 24 |
| Peak memory | 214172 kb |
| Host | smart-baa14ab3-df6a-4c8e-ad09-c26c6ab2b5b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3005639191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.3005639191 |
| Directory | /workspace/130.edn_genbits/latest |
| Test location | /workspace/coverage/default/131.edn_genbits.2982260881 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 37673701 ps |
| CPU time | 1.07 seconds |
| Started | Jan 17 01:40:43 PM PST 24 |
| Finished | Jan 17 01:40:53 PM PST 24 |
| Peak memory | 205060 kb |
| Host | smart-abe0eec2-6d97-49c5-80ec-4eb8b37b9910 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2982260881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2982260881 |
| Directory | /workspace/131.edn_genbits/latest |
| Test location | /workspace/coverage/default/132.edn_genbits.1349328240 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 37297132 ps |
| CPU time | 1.1 seconds |
| Started | Jan 17 01:40:40 PM PST 24 |
| Finished | Jan 17 01:40:44 PM PST 24 |
| Peak memory | 205436 kb |
| Host | smart-4eb73b03-7d99-4a8b-b22e-260dcac4d374 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1349328240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1349328240 |
| Directory | /workspace/132.edn_genbits/latest |
| Test location | /workspace/coverage/default/133.edn_genbits.1442730539 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 443092849 ps |
| CPU time | 3.14 seconds |
| Started | Jan 17 01:40:38 PM PST 24 |
| Finished | Jan 17 01:40:44 PM PST 24 |
| Peak memory | 214164 kb |
| Host | smart-a5eb5754-29be-44c8-8630-3cf90fb9bd9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1442730539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1442730539 |
| Directory | /workspace/133.edn_genbits/latest |
| Test location | /workspace/coverage/default/134.edn_genbits.3421703729 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 20225416 ps |
| CPU time | 1.17 seconds |
| Started | Jan 17 01:40:41 PM PST 24 |
| Finished | Jan 17 01:40:46 PM PST 24 |
| Peak memory | 205548 kb |
| Host | smart-42c0903e-267f-4dbe-ad82-fccc8492a796 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3421703729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3421703729 |
| Directory | /workspace/134.edn_genbits/latest |
| Test location | /workspace/coverage/default/135.edn_genbits.870862160 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 49298176 ps |
| CPU time | 1.07 seconds |
| Started | Jan 17 01:40:39 PM PST 24 |
| Finished | Jan 17 01:40:43 PM PST 24 |
| Peak memory | 214148 kb |
| Host | smart-6307ab6a-36c9-4d2f-b4f7-16d44cfdabb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=870862160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.870862160 |
| Directory | /workspace/135.edn_genbits/latest |
| Test location | /workspace/coverage/default/136.edn_genbits.3834820220 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 187062517 ps |
| CPU time | 2.72 seconds |
| Started | Jan 17 01:40:40 PM PST 24 |
| Finished | Jan 17 01:40:46 PM PST 24 |
| Peak memory | 214152 kb |
| Host | smart-0db4f877-6533-42e5-8098-6d1a55295277 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3834820220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3834820220 |
| Directory | /workspace/136.edn_genbits/latest |
| Test location | /workspace/coverage/default/137.edn_genbits.2350901878 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 24924330 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:40:38 PM PST 24 |
| Finished | Jan 17 01:40:42 PM PST 24 |
| Peak memory | 205164 kb |
| Host | smart-602ac9d3-b589-46f1-a405-875542dff439 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2350901878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2350901878 |
| Directory | /workspace/137.edn_genbits/latest |
| Test location | /workspace/coverage/default/138.edn_genbits.1907626242 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 122723930 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:40:41 PM PST 24 |
| Finished | Jan 17 01:40:44 PM PST 24 |
| Peak memory | 205000 kb |
| Host | smart-f85da97d-6799-40e1-8f6a-48ba42af96aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1907626242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1907626242 |
| Directory | /workspace/138.edn_genbits/latest |
| Test location | /workspace/coverage/default/139.edn_genbits.3403811628 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 24177102 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:40:41 PM PST 24 |
| Finished | Jan 17 01:40:46 PM PST 24 |
| Peak memory | 205156 kb |
| Host | smart-6485d027-5536-4334-a671-7266e78a461f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3403811628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3403811628 |
| Directory | /workspace/139.edn_genbits/latest |
| Test location | /workspace/coverage/default/14.edn_alert.1093663834 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 69838135 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:37:09 PM PST 24 |
| Finished | Jan 17 01:37:15 PM PST 24 |
| Peak memory | 205120 kb |
| Host | smart-7ced1193-5233-4d12-8d19-9960eb172b64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1093663834 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1093663834 |
| Directory | /workspace/14.edn_alert/latest |
| Test location | /workspace/coverage/default/14.edn_alert_test.1839611866 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 42510473 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:37:06 PM PST 24 |
| Finished | Jan 17 01:37:08 PM PST 24 |
| Peak memory | 205100 kb |
| Host | smart-1a73c9aa-c0d1-42d9-a49c-26198d8400ba |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839611866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1839611866 |
| Directory | /workspace/14.edn_alert_test/latest |
| Test location | /workspace/coverage/default/14.edn_disable.30404260 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 38721281 ps |
| CPU time | 0.84 seconds |
| Started | Jan 17 01:37:08 PM PST 24 |
| Finished | Jan 17 01:37:15 PM PST 24 |
| Peak memory | 214408 kb |
| Host | smart-f870aad5-f0e5-471b-bde4-ee9970ee199e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30404260 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.30404260 |
| Directory | /workspace/14.edn_disable/latest |
| Test location | /workspace/coverage/default/14.edn_err.4070843485 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 19376879 ps |
| CPU time | 1.11 seconds |
| Started | Jan 17 01:37:06 PM PST 24 |
| Finished | Jan 17 01:37:09 PM PST 24 |
| Peak memory | 221900 kb |
| Host | smart-c3083492-8943-45c0-ab1c-f3c6e5f71fdc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4070843485 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.4070843485 |
| Directory | /workspace/14.edn_err/latest |
| Test location | /workspace/coverage/default/14.edn_genbits.1244892423 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 51268491 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:37:07 PM PST 24 |
| Finished | Jan 17 01:37:09 PM PST 24 |
| Peak memory | 204920 kb |
| Host | smart-2ab203ac-734f-4b82-9298-2efe062dfc52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1244892423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.1244892423 |
| Directory | /workspace/14.edn_genbits/latest |
| Test location | /workspace/coverage/default/14.edn_intr.1725877002 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 56386333 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:37:09 PM PST 24 |
| Finished | Jan 17 01:37:15 PM PST 24 |
| Peak memory | 221940 kb |
| Host | smart-9af5f3ef-11d5-4871-9409-bcd9125bd19e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1725877002 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1725877002 |
| Directory | /workspace/14.edn_intr/latest |
| Test location | /workspace/coverage/default/14.edn_smoke.2482199179 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 14177142 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:37:06 PM PST 24 |
| Finished | Jan 17 01:37:08 PM PST 24 |
| Peak memory | 204800 kb |
| Host | smart-64fc0248-825c-4f4a-acca-470d7a23aff8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2482199179 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2482199179 |
| Directory | /workspace/14.edn_smoke/latest |
| Test location | /workspace/coverage/default/14.edn_stress_all.1498822827 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 49520992 ps |
| CPU time | 1.33 seconds |
| Started | Jan 17 01:37:08 PM PST 24 |
| Finished | Jan 17 01:37:16 PM PST 24 |
| Peak memory | 205080 kb |
| Host | smart-e98ad627-2091-40f4-8961-6c138fda74de |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498822827 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1498822827 |
| Directory | /workspace/14.edn_stress_all/latest |
| Test location | /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1982943958 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 18635566182 ps |
| CPU time | 106.85 seconds |
| Started | Jan 17 01:37:08 PM PST 24 |
| Finished | Jan 17 01:39:01 PM PST 24 |
| Peak memory | 215212 kb |
| Host | smart-127b3c47-6f57-4304-8b3d-4238a04a64a9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982943958 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1982943958 |
| Directory | /workspace/14.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/140.edn_genbits.3639026528 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 99157309 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:40:40 PM PST 24 |
| Finished | Jan 17 01:40:43 PM PST 24 |
| Peak memory | 205496 kb |
| Host | smart-1c6efa72-ba6a-4ab0-b007-eaa1cbb11a56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3639026528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3639026528 |
| Directory | /workspace/140.edn_genbits/latest |
| Test location | /workspace/coverage/default/141.edn_genbits.267254263 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 20663929 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 01:40:38 PM PST 24 |
| Finished | Jan 17 01:40:42 PM PST 24 |
| Peak memory | 205388 kb |
| Host | smart-539dfd0d-8363-4248-974a-f628d6e68a4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=267254263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.267254263 |
| Directory | /workspace/141.edn_genbits/latest |
| Test location | /workspace/coverage/default/142.edn_genbits.3339085922 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 18202808 ps |
| CPU time | 1.04 seconds |
| Started | Jan 17 01:40:39 PM PST 24 |
| Finished | Jan 17 01:40:43 PM PST 24 |
| Peak memory | 205288 kb |
| Host | smart-4e3dcac9-43be-4a6b-bb33-17f30cb02c1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3339085922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3339085922 |
| Directory | /workspace/142.edn_genbits/latest |
| Test location | /workspace/coverage/default/143.edn_genbits.2054672025 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 26049106 ps |
| CPU time | 1.33 seconds |
| Started | Jan 17 01:40:40 PM PST 24 |
| Finished | Jan 17 01:40:44 PM PST 24 |
| Peak memory | 214212 kb |
| Host | smart-27be53b3-f49c-48b9-a2c4-fc570844619e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2054672025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2054672025 |
| Directory | /workspace/143.edn_genbits/latest |
| Test location | /workspace/coverage/default/144.edn_genbits.3446925156 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 16605429 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:40:43 PM PST 24 |
| Finished | Jan 17 01:40:53 PM PST 24 |
| Peak memory | 204812 kb |
| Host | smart-21e35987-951d-4964-b907-33383827eff4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3446925156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3446925156 |
| Directory | /workspace/144.edn_genbits/latest |
| Test location | /workspace/coverage/default/146.edn_genbits.2309131212 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 61920626 ps |
| CPU time | 1.19 seconds |
| Started | Jan 17 01:40:44 PM PST 24 |
| Finished | Jan 17 01:40:53 PM PST 24 |
| Peak memory | 214076 kb |
| Host | smart-39b12621-1824-492c-956d-cc40503bb7d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2309131212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2309131212 |
| Directory | /workspace/146.edn_genbits/latest |
| Test location | /workspace/coverage/default/147.edn_genbits.408212751 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 39793283 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:40:41 PM PST 24 |
| Finished | Jan 17 01:40:45 PM PST 24 |
| Peak memory | 204900 kb |
| Host | smart-cfe7dbd0-f126-4700-91ee-276f1a946728 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=408212751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.408212751 |
| Directory | /workspace/147.edn_genbits/latest |
| Test location | /workspace/coverage/default/148.edn_genbits.634794030 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 19896123 ps |
| CPU time | 1.06 seconds |
| Started | Jan 17 01:40:41 PM PST 24 |
| Finished | Jan 17 01:40:44 PM PST 24 |
| Peak memory | 205404 kb |
| Host | smart-165229b0-da2d-4229-a78a-01495da44afd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=634794030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.634794030 |
| Directory | /workspace/148.edn_genbits/latest |
| Test location | /workspace/coverage/default/149.edn_genbits.1222711726 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 38076115 ps |
| CPU time | 1.76 seconds |
| Started | Jan 17 01:40:43 PM PST 24 |
| Finished | Jan 17 01:40:54 PM PST 24 |
| Peak memory | 214104 kb |
| Host | smart-6f677f36-33c6-4fab-81bf-336ca887f00e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1222711726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1222711726 |
| Directory | /workspace/149.edn_genbits/latest |
| Test location | /workspace/coverage/default/15.edn_alert.1921708163 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 19640009 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:37:15 PM PST 24 |
| Finished | Jan 17 01:37:17 PM PST 24 |
| Peak memory | 205224 kb |
| Host | smart-1e9f7dac-a604-4da7-b2cc-a2001c7247bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1921708163 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.1921708163 |
| Directory | /workspace/15.edn_alert/latest |
| Test location | /workspace/coverage/default/15.edn_alert_test.3678503244 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 24456721 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:37:38 PM PST 24 |
| Finished | Jan 17 01:37:42 PM PST 24 |
| Peak memory | 204564 kb |
| Host | smart-adcd366e-3d66-4a42-ad21-61e923588e59 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678503244 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3678503244 |
| Directory | /workspace/15.edn_alert_test/latest |
| Test location | /workspace/coverage/default/15.edn_disable.494202225 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 32774939 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:37:20 PM PST 24 |
| Finished | Jan 17 01:37:22 PM PST 24 |
| Peak memory | 214320 kb |
| Host | smart-9ff12658-cb10-4059-94a9-a7478a1a09a7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494202225 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.494202225 |
| Directory | /workspace/15.edn_disable/latest |
| Test location | /workspace/coverage/default/15.edn_err.2159466294 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 29069386 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:37:21 PM PST 24 |
| Finished | Jan 17 01:37:23 PM PST 24 |
| Peak memory | 221864 kb |
| Host | smart-4861a254-7798-483c-82c5-223cd7e4f1aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2159466294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2159466294 |
| Directory | /workspace/15.edn_err/latest |
| Test location | /workspace/coverage/default/15.edn_genbits.504656131 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 58274405 ps |
| CPU time | 1.17 seconds |
| Started | Jan 17 01:37:07 PM PST 24 |
| Finished | Jan 17 01:37:09 PM PST 24 |
| Peak memory | 205584 kb |
| Host | smart-fc24b556-d676-4109-94a0-a3017886268e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=504656131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.504656131 |
| Directory | /workspace/15.edn_genbits/latest |
| Test location | /workspace/coverage/default/15.edn_intr.2793294760 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 27691822 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:37:20 PM PST 24 |
| Finished | Jan 17 01:37:22 PM PST 24 |
| Peak memory | 221528 kb |
| Host | smart-b81dc6b1-1c75-42c8-a8dd-25e2370ba590 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2793294760 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2793294760 |
| Directory | /workspace/15.edn_intr/latest |
| Test location | /workspace/coverage/default/15.edn_smoke.3972408746 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 15768678 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:37:06 PM PST 24 |
| Finished | Jan 17 01:37:08 PM PST 24 |
| Peak memory | 204808 kb |
| Host | smart-6d0337e1-bdb9-477c-9e99-74a2c3053938 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3972408746 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3972408746 |
| Directory | /workspace/15.edn_smoke/latest |
| Test location | /workspace/coverage/default/15.edn_stress_all.2387437227 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 164642625 ps |
| CPU time | 1.57 seconds |
| Started | Jan 17 01:37:08 PM PST 24 |
| Finished | Jan 17 01:37:16 PM PST 24 |
| Peak memory | 205824 kb |
| Host | smart-cc24571d-a2dd-4b7b-a890-e0c54217da62 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387437227 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2387437227 |
| Directory | /workspace/15.edn_stress_all/latest |
| Test location | /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2348006403 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 56411547385 ps |
| CPU time | 883.28 seconds |
| Started | Jan 17 01:37:22 PM PST 24 |
| Finished | Jan 17 01:52:07 PM PST 24 |
| Peak memory | 215232 kb |
| Host | smart-d737ef31-9122-4653-8922-6383c87d539d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348006403 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2348006403 |
| Directory | /workspace/15.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/150.edn_genbits.3210970842 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 27261444 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 01:40:41 PM PST 24 |
| Finished | Jan 17 01:40:45 PM PST 24 |
| Peak memory | 204940 kb |
| Host | smart-2c8f42a3-3e8d-4ed2-b62e-b39e9219b643 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3210970842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3210970842 |
| Directory | /workspace/150.edn_genbits/latest |
| Test location | /workspace/coverage/default/151.edn_genbits.566677560 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 76690161 ps |
| CPU time | 1.12 seconds |
| Started | Jan 17 01:40:48 PM PST 24 |
| Finished | Jan 17 01:40:54 PM PST 24 |
| Peak memory | 205188 kb |
| Host | smart-b567c411-36f3-440f-9a50-5f79e90c7026 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=566677560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.566677560 |
| Directory | /workspace/151.edn_genbits/latest |
| Test location | /workspace/coverage/default/152.edn_genbits.3205721872 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 56353898 ps |
| CPU time | 1.15 seconds |
| Started | Jan 17 01:40:38 PM PST 24 |
| Finished | Jan 17 01:40:42 PM PST 24 |
| Peak memory | 205632 kb |
| Host | smart-3555a7da-6b91-46a0-a668-72d2a1070021 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3205721872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3205721872 |
| Directory | /workspace/152.edn_genbits/latest |
| Test location | /workspace/coverage/default/153.edn_genbits.834786564 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 184153503 ps |
| CPU time | 1.06 seconds |
| Started | Jan 17 01:40:40 PM PST 24 |
| Finished | Jan 17 01:40:44 PM PST 24 |
| Peak memory | 205268 kb |
| Host | smart-6416481c-8861-45f1-a733-d9934d811e9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834786564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.834786564 |
| Directory | /workspace/153.edn_genbits/latest |
| Test location | /workspace/coverage/default/154.edn_genbits.3297122218 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 49712889 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:40:43 PM PST 24 |
| Finished | Jan 17 01:40:53 PM PST 24 |
| Peak memory | 205200 kb |
| Host | smart-6517f30c-9981-42bc-bfe8-91019e699965 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3297122218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3297122218 |
| Directory | /workspace/154.edn_genbits/latest |
| Test location | /workspace/coverage/default/155.edn_genbits.3891723974 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 46903938 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:40:40 PM PST 24 |
| Finished | Jan 17 01:40:44 PM PST 24 |
| Peak memory | 205464 kb |
| Host | smart-ee0ea8a9-017c-499b-8147-af7341f12226 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3891723974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3891723974 |
| Directory | /workspace/155.edn_genbits/latest |
| Test location | /workspace/coverage/default/156.edn_genbits.1469906193 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 127199603 ps |
| CPU time | 1.46 seconds |
| Started | Jan 17 01:40:43 PM PST 24 |
| Finished | Jan 17 01:40:53 PM PST 24 |
| Peak memory | 214100 kb |
| Host | smart-e3ec2a89-14d7-4ae0-81dc-7b7afb9e8c3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1469906193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.1469906193 |
| Directory | /workspace/156.edn_genbits/latest |
| Test location | /workspace/coverage/default/157.edn_genbits.1289616017 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 76612580 ps |
| CPU time | 1.11 seconds |
| Started | Jan 17 01:40:41 PM PST 24 |
| Finished | Jan 17 01:40:45 PM PST 24 |
| Peak memory | 214160 kb |
| Host | smart-0c039adc-ac14-4eac-af54-5248562e30d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1289616017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1289616017 |
| Directory | /workspace/157.edn_genbits/latest |
| Test location | /workspace/coverage/default/158.edn_genbits.3879783092 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 9558165597 ps |
| CPU time | 134.48 seconds |
| Started | Jan 17 01:40:40 PM PST 24 |
| Finished | Jan 17 01:42:58 PM PST 24 |
| Peak memory | 214284 kb |
| Host | smart-cdc06847-2408-4c1f-9519-74f84743d826 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3879783092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3879783092 |
| Directory | /workspace/158.edn_genbits/latest |
| Test location | /workspace/coverage/default/159.edn_genbits.2767307685 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 40772374 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 01:40:38 PM PST 24 |
| Finished | Jan 17 01:40:42 PM PST 24 |
| Peak memory | 205484 kb |
| Host | smart-f267c9f0-3cb5-415e-9b77-842234a3b80c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2767307685 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2767307685 |
| Directory | /workspace/159.edn_genbits/latest |
| Test location | /workspace/coverage/default/16.edn_alert_test.2278566363 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 17102128 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:37:24 PM PST 24 |
| Finished | Jan 17 01:37:28 PM PST 24 |
| Peak memory | 204720 kb |
| Host | smart-cee0f359-413e-4420-be50-43d280ce309d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278566363 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2278566363 |
| Directory | /workspace/16.edn_alert_test/latest |
| Test location | /workspace/coverage/default/16.edn_disable.248802171 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 11138660 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:37:17 PM PST 24 |
| Finished | Jan 17 01:37:19 PM PST 24 |
| Peak memory | 214264 kb |
| Host | smart-8beacb04-7bdb-42df-a38d-b860de0913e6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248802171 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.248802171 |
| Directory | /workspace/16.edn_disable/latest |
| Test location | /workspace/coverage/default/16.edn_disable_auto_req_mode.3956095170 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 34913627 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:37:11 PM PST 24 |
| Finished | Jan 17 01:37:15 PM PST 24 |
| Peak memory | 214512 kb |
| Host | smart-caa1ecd0-0b3b-4e5c-96b1-3e70a1540158 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956095170 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d isable_auto_req_mode.3956095170 |
| Directory | /workspace/16.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/16.edn_err.429964842 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 25801438 ps |
| CPU time | 1.17 seconds |
| Started | Jan 17 01:37:22 PM PST 24 |
| Finished | Jan 17 01:37:24 PM PST 24 |
| Peak memory | 215596 kb |
| Host | smart-415377ac-a9b3-441b-a341-6f46babbc3e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=429964842 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.429964842 |
| Directory | /workspace/16.edn_err/latest |
| Test location | /workspace/coverage/default/16.edn_genbits.3276486284 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 38497094 ps |
| CPU time | 1.12 seconds |
| Started | Jan 17 01:37:23 PM PST 24 |
| Finished | Jan 17 01:37:26 PM PST 24 |
| Peak memory | 214188 kb |
| Host | smart-c77e95f2-f031-4364-8484-a32d9cc4c033 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3276486284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3276486284 |
| Directory | /workspace/16.edn_genbits/latest |
| Test location | /workspace/coverage/default/16.edn_intr.3798273801 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 27219201 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:37:21 PM PST 24 |
| Finished | Jan 17 01:37:22 PM PST 24 |
| Peak memory | 214396 kb |
| Host | smart-5f6ecd2a-28c2-448c-9105-6c46e0178ef2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3798273801 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3798273801 |
| Directory | /workspace/16.edn_intr/latest |
| Test location | /workspace/coverage/default/16.edn_smoke.1692722942 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 12099607 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:37:17 PM PST 24 |
| Finished | Jan 17 01:37:18 PM PST 24 |
| Peak memory | 204896 kb |
| Host | smart-6ac0e5a9-9279-4afe-9246-dc79d379a622 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1692722942 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1692722942 |
| Directory | /workspace/16.edn_smoke/latest |
| Test location | /workspace/coverage/default/16.edn_stress_all.3103681609 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 101912239 ps |
| CPU time | 2.36 seconds |
| Started | Jan 17 01:37:21 PM PST 24 |
| Finished | Jan 17 01:37:24 PM PST 24 |
| Peak memory | 205932 kb |
| Host | smart-dcac331f-9dfe-4787-baf9-214364563ac2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103681609 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3103681609 |
| Directory | /workspace/16.edn_stress_all/latest |
| Test location | /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2457740873 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 201583764985 ps |
| CPU time | 2377.33 seconds |
| Started | Jan 17 01:37:23 PM PST 24 |
| Finished | Jan 17 02:17:03 PM PST 24 |
| Peak memory | 225864 kb |
| Host | smart-66518e91-2a7c-495e-803a-2b8a0b85e0c0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457740873 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2457740873 |
| Directory | /workspace/16.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/160.edn_genbits.1331561551 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 20130300 ps |
| CPU time | 1.15 seconds |
| Started | Jan 17 01:40:41 PM PST 24 |
| Finished | Jan 17 01:40:46 PM PST 24 |
| Peak memory | 205680 kb |
| Host | smart-971fb37f-45e9-4f5c-9e79-7fe0dab51f19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1331561551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1331561551 |
| Directory | /workspace/160.edn_genbits/latest |
| Test location | /workspace/coverage/default/161.edn_genbits.1801206636 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 70065748 ps |
| CPU time | 1.82 seconds |
| Started | Jan 17 01:40:44 PM PST 24 |
| Finished | Jan 17 01:40:54 PM PST 24 |
| Peak memory | 214156 kb |
| Host | smart-0c041aa0-3205-495b-8829-1e5f35c69ea6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1801206636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.1801206636 |
| Directory | /workspace/161.edn_genbits/latest |
| Test location | /workspace/coverage/default/162.edn_genbits.2205237050 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 29945688 ps |
| CPU time | 1.1 seconds |
| Started | Jan 17 01:40:39 PM PST 24 |
| Finished | Jan 17 01:40:43 PM PST 24 |
| Peak memory | 205504 kb |
| Host | smart-839c32b4-33cd-4d84-becb-8708878e3d92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2205237050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2205237050 |
| Directory | /workspace/162.edn_genbits/latest |
| Test location | /workspace/coverage/default/163.edn_genbits.2096605171 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 19283158 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:40:40 PM PST 24 |
| Finished | Jan 17 01:40:44 PM PST 24 |
| Peak memory | 204800 kb |
| Host | smart-71a4fea4-01ef-436a-a52b-b673cf2c593e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2096605171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2096605171 |
| Directory | /workspace/163.edn_genbits/latest |
| Test location | /workspace/coverage/default/164.edn_genbits.1816999759 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 33582501 ps |
| CPU time | 1.05 seconds |
| Started | Jan 17 01:40:39 PM PST 24 |
| Finished | Jan 17 01:40:43 PM PST 24 |
| Peak memory | 205416 kb |
| Host | smart-ef6ccabe-0572-4582-ae54-3c0d3e931c64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1816999759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.1816999759 |
| Directory | /workspace/164.edn_genbits/latest |
| Test location | /workspace/coverage/default/165.edn_genbits.4106795788 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 24024359 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:40:44 PM PST 24 |
| Finished | Jan 17 01:40:53 PM PST 24 |
| Peak memory | 205364 kb |
| Host | smart-737b5d0e-73f4-41a5-afe3-01444088cac7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4106795788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.4106795788 |
| Directory | /workspace/165.edn_genbits/latest |
| Test location | /workspace/coverage/default/166.edn_genbits.543627289 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 60556865 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:40:40 PM PST 24 |
| Finished | Jan 17 01:40:44 PM PST 24 |
| Peak memory | 205492 kb |
| Host | smart-503e96ef-71fb-4ba6-9f49-01698184677b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=543627289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.543627289 |
| Directory | /workspace/166.edn_genbits/latest |
| Test location | /workspace/coverage/default/167.edn_genbits.1695597104 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 23192230 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:40:43 PM PST 24 |
| Finished | Jan 17 01:40:52 PM PST 24 |
| Peak memory | 204996 kb |
| Host | smart-d8fb0cd9-0bd8-4222-8340-40fef84b70d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1695597104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1695597104 |
| Directory | /workspace/167.edn_genbits/latest |
| Test location | /workspace/coverage/default/168.edn_genbits.1927799148 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 67346338 ps |
| CPU time | 1.04 seconds |
| Started | Jan 17 01:40:41 PM PST 24 |
| Finished | Jan 17 01:40:45 PM PST 24 |
| Peak memory | 205368 kb |
| Host | smart-bebf49b5-c72a-440b-ab78-00e302404a1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1927799148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1927799148 |
| Directory | /workspace/168.edn_genbits/latest |
| Test location | /workspace/coverage/default/169.edn_genbits.3077246389 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 57311735 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:40:39 PM PST 24 |
| Finished | Jan 17 01:40:43 PM PST 24 |
| Peak memory | 205080 kb |
| Host | smart-ffc07f8b-ac56-44f5-8334-f872f39dc1ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3077246389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3077246389 |
| Directory | /workspace/169.edn_genbits/latest |
| Test location | /workspace/coverage/default/17.edn_alert_test.2137490959 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 42425379 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:37:22 PM PST 24 |
| Finished | Jan 17 01:37:25 PM PST 24 |
| Peak memory | 205104 kb |
| Host | smart-841f77ad-37b0-4f97-acea-ead8137a2f50 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137490959 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2137490959 |
| Directory | /workspace/17.edn_alert_test/latest |
| Test location | /workspace/coverage/default/17.edn_disable.1169787192 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 12501478 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 01:37:21 PM PST 24 |
| Finished | Jan 17 01:37:22 PM PST 24 |
| Peak memory | 214424 kb |
| Host | smart-e8fd64ac-ebdf-4c73-9217-6123327a0e5b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169787192 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1169787192 |
| Directory | /workspace/17.edn_disable/latest |
| Test location | /workspace/coverage/default/17.edn_disable_auto_req_mode.3777035726 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 97395069 ps |
| CPU time | 1.04 seconds |
| Started | Jan 17 01:37:21 PM PST 24 |
| Finished | Jan 17 01:37:23 PM PST 24 |
| Peak memory | 214568 kb |
| Host | smart-136703a3-98cf-4707-b738-8fb72c27a99f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777035726 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d isable_auto_req_mode.3777035726 |
| Directory | /workspace/17.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/17.edn_err.1946164709 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 44081069 ps |
| CPU time | 1.12 seconds |
| Started | Jan 17 01:37:38 PM PST 24 |
| Finished | Jan 17 01:37:42 PM PST 24 |
| Peak memory | 214252 kb |
| Host | smart-039c99ee-0f86-4303-95c4-7ff60744ffda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1946164709 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1946164709 |
| Directory | /workspace/17.edn_err/latest |
| Test location | /workspace/coverage/default/17.edn_genbits.3505903977 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 54980575 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:37:16 PM PST 24 |
| Finished | Jan 17 01:37:18 PM PST 24 |
| Peak memory | 205560 kb |
| Host | smart-ec372fb4-ba8e-4922-98fc-d3b58694b931 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3505903977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3505903977 |
| Directory | /workspace/17.edn_genbits/latest |
| Test location | /workspace/coverage/default/17.edn_intr.1909915741 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 25000983 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:37:24 PM PST 24 |
| Finished | Jan 17 01:37:27 PM PST 24 |
| Peak memory | 214484 kb |
| Host | smart-c883b757-6cbb-46c5-95e5-2a62e949395a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1909915741 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1909915741 |
| Directory | /workspace/17.edn_intr/latest |
| Test location | /workspace/coverage/default/17.edn_smoke.3774256655 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 104890223 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:37:22 PM PST 24 |
| Finished | Jan 17 01:37:23 PM PST 24 |
| Peak memory | 204492 kb |
| Host | smart-50ecf636-0e00-4c76-beeb-ddc703e75715 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3774256655 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3774256655 |
| Directory | /workspace/17.edn_smoke/latest |
| Test location | /workspace/coverage/default/17.edn_stress_all.2795196167 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 381838198 ps |
| CPU time | 3.01 seconds |
| Started | Jan 17 01:37:22 PM PST 24 |
| Finished | Jan 17 01:37:25 PM PST 24 |
| Peak memory | 206052 kb |
| Host | smart-af3b762f-e441-440e-8e21-d1a96ee0022a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795196167 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2795196167 |
| Directory | /workspace/17.edn_stress_all/latest |
| Test location | /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2027043084 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 82625636780 ps |
| CPU time | 1984.17 seconds |
| Started | Jan 17 01:37:38 PM PST 24 |
| Finished | Jan 17 02:10:43 PM PST 24 |
| Peak memory | 223456 kb |
| Host | smart-9001108c-ad48-4db5-b23b-cadbc3f9fcfa |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027043084 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2027043084 |
| Directory | /workspace/17.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/170.edn_genbits.2747211067 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 19924809 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:40:40 PM PST 24 |
| Finished | Jan 17 01:40:44 PM PST 24 |
| Peak memory | 204996 kb |
| Host | smart-935bfdb7-a241-485f-81c2-bb161b4ba7ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2747211067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2747211067 |
| Directory | /workspace/170.edn_genbits/latest |
| Test location | /workspace/coverage/default/171.edn_genbits.2591271344 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 44082350 ps |
| CPU time | 1.18 seconds |
| Started | Jan 17 01:40:42 PM PST 24 |
| Finished | Jan 17 01:40:46 PM PST 24 |
| Peak memory | 214132 kb |
| Host | smart-95374aba-bbf2-4fac-80bc-cde03d0c2a72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2591271344 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2591271344 |
| Directory | /workspace/171.edn_genbits/latest |
| Test location | /workspace/coverage/default/172.edn_genbits.1351502376 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 28034244 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:40:45 PM PST 24 |
| Finished | Jan 17 01:40:54 PM PST 24 |
| Peak memory | 204836 kb |
| Host | smart-a572658e-3c41-46bc-a9e7-019dc5fd7ba0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1351502376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1351502376 |
| Directory | /workspace/172.edn_genbits/latest |
| Test location | /workspace/coverage/default/173.edn_genbits.3785478280 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 38370310 ps |
| CPU time | 1.15 seconds |
| Started | Jan 17 01:40:44 PM PST 24 |
| Finished | Jan 17 01:40:53 PM PST 24 |
| Peak memory | 214156 kb |
| Host | smart-dc458a5c-3b41-4eee-9a60-657f33bca49a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3785478280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3785478280 |
| Directory | /workspace/173.edn_genbits/latest |
| Test location | /workspace/coverage/default/174.edn_genbits.3490724049 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 91059670 ps |
| CPU time | 1.3 seconds |
| Started | Jan 17 01:40:44 PM PST 24 |
| Finished | Jan 17 01:40:54 PM PST 24 |
| Peak memory | 205764 kb |
| Host | smart-9ebfecab-471e-4f50-99ef-b9fb064d14b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3490724049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3490724049 |
| Directory | /workspace/174.edn_genbits/latest |
| Test location | /workspace/coverage/default/175.edn_genbits.2175297277 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 19005285 ps |
| CPU time | 1.23 seconds |
| Started | Jan 17 01:40:45 PM PST 24 |
| Finished | Jan 17 01:40:54 PM PST 24 |
| Peak memory | 214112 kb |
| Host | smart-66dbf9ef-5fc6-4c60-b4d6-418d05bb1531 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2175297277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2175297277 |
| Directory | /workspace/175.edn_genbits/latest |
| Test location | /workspace/coverage/default/176.edn_genbits.3661965274 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 122040171 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:40:42 PM PST 24 |
| Finished | Jan 17 01:40:46 PM PST 24 |
| Peak memory | 205412 kb |
| Host | smart-cfe90402-55c1-4641-a2b3-66362953c514 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3661965274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3661965274 |
| Directory | /workspace/176.edn_genbits/latest |
| Test location | /workspace/coverage/default/178.edn_genbits.1409627198 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 24863726 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:40:44 PM PST 24 |
| Finished | Jan 17 01:40:53 PM PST 24 |
| Peak memory | 204928 kb |
| Host | smart-1f259281-1ecc-426a-8ee6-807967df3c27 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1409627198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1409627198 |
| Directory | /workspace/178.edn_genbits/latest |
| Test location | /workspace/coverage/default/179.edn_genbits.703563478 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 29556143 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:40:44 PM PST 24 |
| Finished | Jan 17 01:40:53 PM PST 24 |
| Peak memory | 205916 kb |
| Host | smart-0e3308c7-42a4-4298-90dd-d198b88e3cac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=703563478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.703563478 |
| Directory | /workspace/179.edn_genbits/latest |
| Test location | /workspace/coverage/default/18.edn_alert.2689477074 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 29009968 ps |
| CPU time | 0.9 seconds |
| Started | Jan 17 01:37:38 PM PST 24 |
| Finished | Jan 17 01:37:40 PM PST 24 |
| Peak memory | 205936 kb |
| Host | smart-e3fea86c-8af7-4ae8-b988-fef82fdbfaa5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2689477074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2689477074 |
| Directory | /workspace/18.edn_alert/latest |
| Test location | /workspace/coverage/default/18.edn_alert_test.4252063869 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 34682189 ps |
| CPU time | 0.9 seconds |
| Started | Jan 17 01:37:30 PM PST 24 |
| Finished | Jan 17 01:37:31 PM PST 24 |
| Peak memory | 205088 kb |
| Host | smart-8d3816d4-2187-4cce-b509-2bb97bd68272 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252063869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.4252063869 |
| Directory | /workspace/18.edn_alert_test/latest |
| Test location | /workspace/coverage/default/18.edn_err.793085111 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 18590425 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:37:38 PM PST 24 |
| Finished | Jan 17 01:37:41 PM PST 24 |
| Peak memory | 221400 kb |
| Host | smart-4465107b-17d0-4c16-a5ce-05a166e10301 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=793085111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.793085111 |
| Directory | /workspace/18.edn_err/latest |
| Test location | /workspace/coverage/default/18.edn_genbits.1734205760 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 14414570 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 01:37:20 PM PST 24 |
| Finished | Jan 17 01:37:22 PM PST 24 |
| Peak memory | 204956 kb |
| Host | smart-0f153ec9-8f11-4132-bbf2-0f6b145bd9bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1734205760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1734205760 |
| Directory | /workspace/18.edn_genbits/latest |
| Test location | /workspace/coverage/default/18.edn_intr.2544065461 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 22438921 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:37:20 PM PST 24 |
| Finished | Jan 17 01:37:22 PM PST 24 |
| Peak memory | 214196 kb |
| Host | smart-97604cc5-6149-43ed-b07d-06c2a33bf4c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2544065461 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2544065461 |
| Directory | /workspace/18.edn_intr/latest |
| Test location | /workspace/coverage/default/18.edn_smoke.3123715264 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 45587622 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:37:22 PM PST 24 |
| Finished | Jan 17 01:37:23 PM PST 24 |
| Peak memory | 204808 kb |
| Host | smart-1bf3b5df-731b-46b8-8c61-1db295490fc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3123715264 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3123715264 |
| Directory | /workspace/18.edn_smoke/latest |
| Test location | /workspace/coverage/default/18.edn_stress_all.3345818301 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 535124415 ps |
| CPU time | 2.08 seconds |
| Started | Jan 17 01:37:23 PM PST 24 |
| Finished | Jan 17 01:37:26 PM PST 24 |
| Peak memory | 205932 kb |
| Host | smart-aafc0302-ef59-4723-87ea-90642a8fdeb9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345818301 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3345818301 |
| Directory | /workspace/18.edn_stress_all/latest |
| Test location | /workspace/coverage/default/180.edn_genbits.3452998769 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 35087046 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:40:41 PM PST 24 |
| Finished | Jan 17 01:40:45 PM PST 24 |
| Peak memory | 204892 kb |
| Host | smart-af7df0c9-8a13-4914-a533-a2e2c28465cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3452998769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3452998769 |
| Directory | /workspace/180.edn_genbits/latest |
| Test location | /workspace/coverage/default/181.edn_genbits.831995198 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 29124696 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:40:48 PM PST 24 |
| Finished | Jan 17 01:40:54 PM PST 24 |
| Peak memory | 205148 kb |
| Host | smart-6bb71975-f2a0-404e-b350-23e29d2e4a1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=831995198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.831995198 |
| Directory | /workspace/181.edn_genbits/latest |
| Test location | /workspace/coverage/default/182.edn_genbits.3838951810 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 23041055 ps |
| CPU time | 1.16 seconds |
| Started | Jan 17 01:40:44 PM PST 24 |
| Finished | Jan 17 01:40:54 PM PST 24 |
| Peak memory | 205480 kb |
| Host | smart-e7e1a5fe-ec75-42e9-a44d-b9efb78d0921 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3838951810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.3838951810 |
| Directory | /workspace/182.edn_genbits/latest |
| Test location | /workspace/coverage/default/183.edn_genbits.3362876150 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 37774424 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 01:40:39 PM PST 24 |
| Finished | Jan 17 01:40:43 PM PST 24 |
| Peak memory | 205404 kb |
| Host | smart-0f941b17-a6f6-4847-b424-e115328bc8bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3362876150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3362876150 |
| Directory | /workspace/183.edn_genbits/latest |
| Test location | /workspace/coverage/default/184.edn_genbits.2660032845 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 149853249 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:40:46 PM PST 24 |
| Finished | Jan 17 01:40:54 PM PST 24 |
| Peak memory | 205612 kb |
| Host | smart-a1fc0cd6-0388-45a5-906f-dca10383d98d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2660032845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2660032845 |
| Directory | /workspace/184.edn_genbits/latest |
| Test location | /workspace/coverage/default/185.edn_genbits.2471733127 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 180160734 ps |
| CPU time | 1.97 seconds |
| Started | Jan 17 01:40:46 PM PST 24 |
| Finished | Jan 17 01:40:55 PM PST 24 |
| Peak memory | 214180 kb |
| Host | smart-2e92e413-8182-4bb8-8f6c-5c8e7cacc946 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2471733127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2471733127 |
| Directory | /workspace/185.edn_genbits/latest |
| Test location | /workspace/coverage/default/186.edn_genbits.1252344141 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 22228327 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:40:44 PM PST 24 |
| Finished | Jan 17 01:40:53 PM PST 24 |
| Peak memory | 205088 kb |
| Host | smart-433e7550-6e6a-4cde-835a-11842cf40c69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252344141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1252344141 |
| Directory | /workspace/186.edn_genbits/latest |
| Test location | /workspace/coverage/default/187.edn_genbits.2286378144 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 37140886 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:40:46 PM PST 24 |
| Finished | Jan 17 01:40:54 PM PST 24 |
| Peak memory | 205460 kb |
| Host | smart-9fd6104b-4b9e-42e1-9612-159f1f740f51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2286378144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2286378144 |
| Directory | /workspace/187.edn_genbits/latest |
| Test location | /workspace/coverage/default/188.edn_genbits.1586844445 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 36336531 ps |
| CPU time | 1.09 seconds |
| Started | Jan 17 01:40:50 PM PST 24 |
| Finished | Jan 17 01:40:54 PM PST 24 |
| Peak memory | 214160 kb |
| Host | smart-cd57700c-e328-4dc7-9ebf-c12a699590ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1586844445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1586844445 |
| Directory | /workspace/188.edn_genbits/latest |
| Test location | /workspace/coverage/default/189.edn_genbits.3244063256 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 52552813 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:40:44 PM PST 24 |
| Finished | Jan 17 01:40:53 PM PST 24 |
| Peak memory | 205084 kb |
| Host | smart-f505c64d-2bd3-4574-ac2b-189afc919710 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244063256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3244063256 |
| Directory | /workspace/189.edn_genbits/latest |
| Test location | /workspace/coverage/default/19.edn_alert.1407447364 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 35519151 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:37:41 PM PST 24 |
| Finished | Jan 17 01:37:44 PM PST 24 |
| Peak memory | 205640 kb |
| Host | smart-c18a53bd-502d-42c6-b1ae-51e58d2da72b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1407447364 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1407447364 |
| Directory | /workspace/19.edn_alert/latest |
| Test location | /workspace/coverage/default/19.edn_alert_test.1251018915 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 72252962 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:37:36 PM PST 24 |
| Finished | Jan 17 01:37:37 PM PST 24 |
| Peak memory | 205096 kb |
| Host | smart-db1bfe8e-c109-451b-b7f5-e30b80c7d11a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251018915 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.1251018915 |
| Directory | /workspace/19.edn_alert_test/latest |
| Test location | /workspace/coverage/default/19.edn_disable_auto_req_mode.3007849192 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 34181148 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 01:37:49 PM PST 24 |
| Finished | Jan 17 01:37:51 PM PST 24 |
| Peak memory | 214348 kb |
| Host | smart-a117d4c6-15e0-4607-85b6-0c12b2c5ff00 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007849192 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d isable_auto_req_mode.3007849192 |
| Directory | /workspace/19.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/19.edn_err.559096023 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 93074347 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:37:57 PM PST 24 |
| Finished | Jan 17 01:37:59 PM PST 24 |
| Peak memory | 221940 kb |
| Host | smart-f45f49b5-2cb8-4b65-9df9-d8df81403640 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=559096023 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.559096023 |
| Directory | /workspace/19.edn_err/latest |
| Test location | /workspace/coverage/default/19.edn_genbits.2934354218 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 30260125 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:37:38 PM PST 24 |
| Finished | Jan 17 01:37:42 PM PST 24 |
| Peak memory | 205228 kb |
| Host | smart-156fdadf-9137-4e37-8964-aa6400da8d45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2934354218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2934354218 |
| Directory | /workspace/19.edn_genbits/latest |
| Test location | /workspace/coverage/default/19.edn_smoke.1505728299 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 15300125 ps |
| CPU time | 0.91 seconds |
| Started | Jan 17 01:37:32 PM PST 24 |
| Finished | Jan 17 01:37:34 PM PST 24 |
| Peak memory | 205188 kb |
| Host | smart-5d62c4bc-045f-4c45-947e-13b6931bcb23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1505728299 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1505728299 |
| Directory | /workspace/19.edn_smoke/latest |
| Test location | /workspace/coverage/default/19.edn_stress_all.460909887 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 55849911 ps |
| CPU time | 1.59 seconds |
| Started | Jan 17 01:37:38 PM PST 24 |
| Finished | Jan 17 01:37:43 PM PST 24 |
| Peak memory | 205756 kb |
| Host | smart-1f368128-2899-462e-80cb-e95a94796e43 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460909887 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.460909887 |
| Directory | /workspace/19.edn_stress_all/latest |
| Test location | /workspace/coverage/default/19.edn_stress_all_with_rand_reset.1501911648 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 16508965640 ps |
| CPU time | 349.65 seconds |
| Started | Jan 17 01:37:30 PM PST 24 |
| Finished | Jan 17 01:43:20 PM PST 24 |
| Peak memory | 214496 kb |
| Host | smart-20e04857-1e4d-44b9-a9e9-d1351b9ecfff |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501911648 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.1501911648 |
| Directory | /workspace/19.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/190.edn_genbits.2618866731 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 118288226 ps |
| CPU time | 1.17 seconds |
| Started | Jan 17 01:40:41 PM PST 24 |
| Finished | Jan 17 01:40:46 PM PST 24 |
| Peak memory | 205472 kb |
| Host | smart-03b81246-765d-4f1e-8abb-ce2800a8a4ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2618866731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2618866731 |
| Directory | /workspace/190.edn_genbits/latest |
| Test location | /workspace/coverage/default/191.edn_genbits.1626756528 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 96608024 ps |
| CPU time | 1.16 seconds |
| Started | Jan 17 01:40:44 PM PST 24 |
| Finished | Jan 17 01:40:53 PM PST 24 |
| Peak memory | 205200 kb |
| Host | smart-fa31e33f-98eb-483b-876b-bb73bf1b1636 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1626756528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1626756528 |
| Directory | /workspace/191.edn_genbits/latest |
| Test location | /workspace/coverage/default/192.edn_genbits.643130784 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 118291943 ps |
| CPU time | 1.17 seconds |
| Started | Jan 17 01:40:44 PM PST 24 |
| Finished | Jan 17 01:40:53 PM PST 24 |
| Peak memory | 214128 kb |
| Host | smart-abf332c3-e525-486c-b822-eaae987bed54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=643130784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.643130784 |
| Directory | /workspace/192.edn_genbits/latest |
| Test location | /workspace/coverage/default/193.edn_genbits.3497300267 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 51837244 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:40:44 PM PST 24 |
| Finished | Jan 17 01:40:53 PM PST 24 |
| Peak memory | 205020 kb |
| Host | smart-ab130366-8058-4a1f-9294-000b0e68d3fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3497300267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3497300267 |
| Directory | /workspace/193.edn_genbits/latest |
| Test location | /workspace/coverage/default/194.edn_genbits.1132796016 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 163641568 ps |
| CPU time | 2.95 seconds |
| Started | Jan 17 01:40:49 PM PST 24 |
| Finished | Jan 17 01:40:56 PM PST 24 |
| Peak memory | 214088 kb |
| Host | smart-4b46c505-5434-46bb-9779-f052bfe4b4d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1132796016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1132796016 |
| Directory | /workspace/194.edn_genbits/latest |
| Test location | /workspace/coverage/default/195.edn_genbits.4248959131 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 16977367 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:40:41 PM PST 24 |
| Finished | Jan 17 01:40:45 PM PST 24 |
| Peak memory | 205504 kb |
| Host | smart-1a70204a-8270-4b57-9af7-7de5430cd4af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4248959131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.4248959131 |
| Directory | /workspace/195.edn_genbits/latest |
| Test location | /workspace/coverage/default/196.edn_genbits.1831707121 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 46991781 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:40:45 PM PST 24 |
| Finished | Jan 17 01:40:53 PM PST 24 |
| Peak memory | 205276 kb |
| Host | smart-506b24b3-d317-45b5-b655-4f5542ea183f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1831707121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1831707121 |
| Directory | /workspace/196.edn_genbits/latest |
| Test location | /workspace/coverage/default/197.edn_genbits.38811127 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 17215547 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:41:00 PM PST 24 |
| Finished | Jan 17 01:41:04 PM PST 24 |
| Peak memory | 204896 kb |
| Host | smart-e08644f4-912e-4ab2-9ba0-cd31f24df1d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=38811127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.38811127 |
| Directory | /workspace/197.edn_genbits/latest |
| Test location | /workspace/coverage/default/199.edn_genbits.2223772992 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 40141406 ps |
| CPU time | 1.18 seconds |
| Started | Jan 17 01:40:49 PM PST 24 |
| Finished | Jan 17 01:40:54 PM PST 24 |
| Peak memory | 214120 kb |
| Host | smart-2f91cd3e-14e3-4770-8a8a-532259a50579 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223772992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2223772992 |
| Directory | /workspace/199.edn_genbits/latest |
| Test location | /workspace/coverage/default/2.edn_alert.1233144985 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 37165026 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:35:52 PM PST 24 |
| Finished | Jan 17 01:35:54 PM PST 24 |
| Peak memory | 205232 kb |
| Host | smart-182b0471-f581-43bd-8385-8a3263545d32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1233144985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1233144985 |
| Directory | /workspace/2.edn_alert/latest |
| Test location | /workspace/coverage/default/2.edn_alert_test.4052920658 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 25529980 ps |
| CPU time | 0.81 seconds |
| Started | Jan 17 01:35:52 PM PST 24 |
| Finished | Jan 17 01:35:53 PM PST 24 |
| Peak memory | 204964 kb |
| Host | smart-4ff2d10c-01cd-4162-821c-064a8b14ad54 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052920658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.4052920658 |
| Directory | /workspace/2.edn_alert_test/latest |
| Test location | /workspace/coverage/default/2.edn_disable_auto_req_mode.148779841 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 76978203 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:35:48 PM PST 24 |
| Finished | Jan 17 01:35:52 PM PST 24 |
| Peak memory | 214468 kb |
| Host | smart-fada26cb-a995-4ff7-8b67-dd919ca4100d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148779841 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis able_auto_req_mode.148779841 |
| Directory | /workspace/2.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/2.edn_err.235907072 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 72972595 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:35:52 PM PST 24 |
| Finished | Jan 17 01:35:54 PM PST 24 |
| Peak memory | 216804 kb |
| Host | smart-329fca7b-6927-4f3c-8ad0-7fe402c8dc36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=235907072 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.235907072 |
| Directory | /workspace/2.edn_err/latest |
| Test location | /workspace/coverage/default/2.edn_genbits.2642614865 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 104742400 ps |
| CPU time | 1.18 seconds |
| Started | Jan 17 01:35:53 PM PST 24 |
| Finished | Jan 17 01:35:55 PM PST 24 |
| Peak memory | 214208 kb |
| Host | smart-542e6ac8-61c1-432c-9d63-f0f2ee946daf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2642614865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2642614865 |
| Directory | /workspace/2.edn_genbits/latest |
| Test location | /workspace/coverage/default/2.edn_intr.1274069269 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 19949618 ps |
| CPU time | 1.05 seconds |
| Started | Jan 17 01:35:46 PM PST 24 |
| Finished | Jan 17 01:35:52 PM PST 24 |
| Peak memory | 214524 kb |
| Host | smart-26f4f081-41b6-4c03-ae2a-c772192e1dac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1274069269 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1274069269 |
| Directory | /workspace/2.edn_intr/latest |
| Test location | /workspace/coverage/default/2.edn_smoke.1936815218 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 21513978 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:35:46 PM PST 24 |
| Finished | Jan 17 01:35:52 PM PST 24 |
| Peak memory | 204808 kb |
| Host | smart-c2661989-a69b-4894-a465-94431bae4026 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1936815218 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1936815218 |
| Directory | /workspace/2.edn_smoke/latest |
| Test location | /workspace/coverage/default/2.edn_stress_all.362367284 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 72861155 ps |
| CPU time | 2.04 seconds |
| Started | Jan 17 01:35:45 PM PST 24 |
| Finished | Jan 17 01:35:53 PM PST 24 |
| Peak memory | 205352 kb |
| Host | smart-43ab1058-82fc-449b-ae6b-6ade0694c5c0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362367284 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.362367284 |
| Directory | /workspace/2.edn_stress_all/latest |
| Test location | /workspace/coverage/default/2.edn_stress_all_with_rand_reset.178849568 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 400016666778 ps |
| CPU time | 2125.68 seconds |
| Started | Jan 17 01:35:46 PM PST 24 |
| Finished | Jan 17 02:11:17 PM PST 24 |
| Peak memory | 221524 kb |
| Host | smart-bbe20f8f-6e27-49eb-a33b-237cec5ea601 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178849568 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.178849568 |
| Directory | /workspace/2.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.edn_alert.418149192 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 26484041 ps |
| CPU time | 0.9 seconds |
| Started | Jan 17 01:37:36 PM PST 24 |
| Finished | Jan 17 01:37:38 PM PST 24 |
| Peak memory | 205272 kb |
| Host | smart-1f388bf2-eac6-42bb-8aad-8c38e66b141c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=418149192 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.418149192 |
| Directory | /workspace/20.edn_alert/latest |
| Test location | /workspace/coverage/default/20.edn_alert_test.4261725529 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 18942282 ps |
| CPU time | 0.91 seconds |
| Started | Jan 17 01:37:38 PM PST 24 |
| Finished | Jan 17 01:37:40 PM PST 24 |
| Peak memory | 204492 kb |
| Host | smart-752117f9-f9f9-4189-bc87-7380ef014834 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261725529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.4261725529 |
| Directory | /workspace/20.edn_alert_test/latest |
| Test location | /workspace/coverage/default/20.edn_disable_auto_req_mode.2839208916 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 80991701 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:37:39 PM PST 24 |
| Finished | Jan 17 01:37:43 PM PST 24 |
| Peak memory | 214452 kb |
| Host | smart-2f25c28a-ee05-43ce-a82d-8d0f2b820f8a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839208916 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d isable_auto_req_mode.2839208916 |
| Directory | /workspace/20.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/20.edn_err.266369813 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 18929647 ps |
| CPU time | 1.15 seconds |
| Started | Jan 17 01:37:46 PM PST 24 |
| Finished | Jan 17 01:37:51 PM PST 24 |
| Peak memory | 221556 kb |
| Host | smart-6aa7ceb1-6881-4c6b-bfbb-b957bb790de1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=266369813 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.266369813 |
| Directory | /workspace/20.edn_err/latest |
| Test location | /workspace/coverage/default/20.edn_genbits.3920819804 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 21956752 ps |
| CPU time | 1.24 seconds |
| Started | Jan 17 01:37:38 PM PST 24 |
| Finished | Jan 17 01:37:42 PM PST 24 |
| Peak memory | 214240 kb |
| Host | smart-df8891ef-093f-4688-a6f6-3650653e117e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3920819804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3920819804 |
| Directory | /workspace/20.edn_genbits/latest |
| Test location | /workspace/coverage/default/20.edn_intr.1863518651 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 18995565 ps |
| CPU time | 1.02 seconds |
| Started | Jan 17 01:37:38 PM PST 24 |
| Finished | Jan 17 01:37:42 PM PST 24 |
| Peak memory | 214448 kb |
| Host | smart-e903bd13-c79d-4a51-b7bd-5b1bcaae5f75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1863518651 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1863518651 |
| Directory | /workspace/20.edn_intr/latest |
| Test location | /workspace/coverage/default/20.edn_smoke.4136724997 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 49918457 ps |
| CPU time | 0.9 seconds |
| Started | Jan 17 01:37:49 PM PST 24 |
| Finished | Jan 17 01:37:51 PM PST 24 |
| Peak memory | 204704 kb |
| Host | smart-bdb073ba-4c80-4843-a298-d72ad0e70be6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4136724997 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.4136724997 |
| Directory | /workspace/20.edn_smoke/latest |
| Test location | /workspace/coverage/default/20.edn_stress_all.1454748917 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 437695041 ps |
| CPU time | 2.44 seconds |
| Started | Jan 17 01:37:37 PM PST 24 |
| Finished | Jan 17 01:37:40 PM PST 24 |
| Peak memory | 205928 kb |
| Host | smart-4720753c-48e8-4a0c-9160-0463a91c42fa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454748917 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1454748917 |
| Directory | /workspace/20.edn_stress_all/latest |
| Test location | /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2033989401 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 461700879657 ps |
| CPU time | 2837.98 seconds |
| Started | Jan 17 01:37:38 PM PST 24 |
| Finished | Jan 17 02:24:59 PM PST 24 |
| Peak memory | 223304 kb |
| Host | smart-68308b09-866d-4705-88d5-43d97f593159 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033989401 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2033989401 |
| Directory | /workspace/20.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/200.edn_genbits.474272521 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 59283329 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:40:59 PM PST 24 |
| Finished | Jan 17 01:41:02 PM PST 24 |
| Peak memory | 205004 kb |
| Host | smart-04b1324e-7c52-4a20-a8c2-4bf292c3691a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=474272521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.474272521 |
| Directory | /workspace/200.edn_genbits/latest |
| Test location | /workspace/coverage/default/202.edn_genbits.4208687664 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 92099637 ps |
| CPU time | 1.22 seconds |
| Started | Jan 17 01:40:59 PM PST 24 |
| Finished | Jan 17 01:41:03 PM PST 24 |
| Peak memory | 205604 kb |
| Host | smart-c1118fc9-a2b5-49c2-94d4-92d260f748bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4208687664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.4208687664 |
| Directory | /workspace/202.edn_genbits/latest |
| Test location | /workspace/coverage/default/203.edn_genbits.4023577830 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 32824324 ps |
| CPU time | 1.65 seconds |
| Started | Jan 17 01:40:51 PM PST 24 |
| Finished | Jan 17 01:40:55 PM PST 24 |
| Peak memory | 214164 kb |
| Host | smart-045ba59a-5d17-47d6-99cb-924289912134 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4023577830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.4023577830 |
| Directory | /workspace/203.edn_genbits/latest |
| Test location | /workspace/coverage/default/204.edn_genbits.3481976146 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 48763641 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:40:49 PM PST 24 |
| Finished | Jan 17 01:40:54 PM PST 24 |
| Peak memory | 205176 kb |
| Host | smart-35931329-9489-46a1-b98c-c1aa6be88af5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3481976146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3481976146 |
| Directory | /workspace/204.edn_genbits/latest |
| Test location | /workspace/coverage/default/205.edn_genbits.3475455445 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 96820180 ps |
| CPU time | 1.09 seconds |
| Started | Jan 17 01:40:59 PM PST 24 |
| Finished | Jan 17 01:41:03 PM PST 24 |
| Peak memory | 205672 kb |
| Host | smart-b2717fe3-9c02-4a45-a332-a0af3fc6f8c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3475455445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3475455445 |
| Directory | /workspace/205.edn_genbits/latest |
| Test location | /workspace/coverage/default/206.edn_genbits.147775255 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 23144268 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:41:00 PM PST 24 |
| Finished | Jan 17 01:41:04 PM PST 24 |
| Peak memory | 205084 kb |
| Host | smart-cdf9fece-e7d3-424c-b845-5023ee4f5c76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=147775255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.147775255 |
| Directory | /workspace/206.edn_genbits/latest |
| Test location | /workspace/coverage/default/207.edn_genbits.301739121 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 90913302 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:40:50 PM PST 24 |
| Finished | Jan 17 01:40:54 PM PST 24 |
| Peak memory | 205100 kb |
| Host | smart-25575c14-3738-47f6-b13c-02c8c477d32c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=301739121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.301739121 |
| Directory | /workspace/207.edn_genbits/latest |
| Test location | /workspace/coverage/default/21.edn_alert.3129193717 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 48836853 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 01:37:38 PM PST 24 |
| Finished | Jan 17 01:37:42 PM PST 24 |
| Peak memory | 205920 kb |
| Host | smart-72fd2739-55dd-4eb9-a5a1-86cfb3d530ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3129193717 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3129193717 |
| Directory | /workspace/21.edn_alert/latest |
| Test location | /workspace/coverage/default/21.edn_alert_test.2849220226 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 74490543 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:37:36 PM PST 24 |
| Finished | Jan 17 01:37:38 PM PST 24 |
| Peak memory | 205408 kb |
| Host | smart-0925cf7e-d533-4e7f-9a48-6f24efe64997 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849220226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2849220226 |
| Directory | /workspace/21.edn_alert_test/latest |
| Test location | /workspace/coverage/default/21.edn_disable.1456369754 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 11553042 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:37:39 PM PST 24 |
| Finished | Jan 17 01:37:42 PM PST 24 |
| Peak memory | 214616 kb |
| Host | smart-c1af6ecb-65f1-45fa-9b3d-4da940cb9e80 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456369754 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1456369754 |
| Directory | /workspace/21.edn_disable/latest |
| Test location | /workspace/coverage/default/21.edn_err.146416086 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 19532261 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:37:45 PM PST 24 |
| Finished | Jan 17 01:37:51 PM PST 24 |
| Peak memory | 215644 kb |
| Host | smart-274c6cb9-9d9f-40a9-bb66-ab7bbff793fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=146416086 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.146416086 |
| Directory | /workspace/21.edn_err/latest |
| Test location | /workspace/coverage/default/21.edn_genbits.3008224576 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 64397840 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:37:45 PM PST 24 |
| Finished | Jan 17 01:37:51 PM PST 24 |
| Peak memory | 205284 kb |
| Host | smart-d3a036ac-342e-4ae8-82a4-7c575ed01c6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3008224576 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3008224576 |
| Directory | /workspace/21.edn_genbits/latest |
| Test location | /workspace/coverage/default/21.edn_intr.3513739580 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 27436268 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:37:37 PM PST 24 |
| Finished | Jan 17 01:37:38 PM PST 24 |
| Peak memory | 214504 kb |
| Host | smart-52db772b-4d87-43cd-9140-7f79dd900082 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3513739580 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3513739580 |
| Directory | /workspace/21.edn_intr/latest |
| Test location | /workspace/coverage/default/21.edn_smoke.929038904 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 40874175 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:37:38 PM PST 24 |
| Finished | Jan 17 01:37:40 PM PST 24 |
| Peak memory | 204616 kb |
| Host | smart-4e4de770-d6d7-4e97-bb96-39334a02f62c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=929038904 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.929038904 |
| Directory | /workspace/21.edn_smoke/latest |
| Test location | /workspace/coverage/default/21.edn_stress_all.935847621 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 599047669 ps |
| CPU time | 3.62 seconds |
| Started | Jan 17 01:37:38 PM PST 24 |
| Finished | Jan 17 01:37:42 PM PST 24 |
| Peak memory | 205668 kb |
| Host | smart-7cda9ce9-685a-43f9-b065-12575946406f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935847621 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.935847621 |
| Directory | /workspace/21.edn_stress_all/latest |
| Test location | /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2107893577 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 226330468213 ps |
| CPU time | 1297.65 seconds |
| Started | Jan 17 01:37:45 PM PST 24 |
| Finished | Jan 17 01:59:28 PM PST 24 |
| Peak memory | 217700 kb |
| Host | smart-ec79bd5e-7084-4fec-9735-5a0340e87484 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107893577 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2107893577 |
| Directory | /workspace/21.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/210.edn_genbits.2544188659 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 21327714 ps |
| CPU time | 1.19 seconds |
| Started | Jan 17 01:40:48 PM PST 24 |
| Finished | Jan 17 01:40:54 PM PST 24 |
| Peak memory | 214128 kb |
| Host | smart-0341c5ec-c4a5-440a-a6e9-18386e3adc7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2544188659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2544188659 |
| Directory | /workspace/210.edn_genbits/latest |
| Test location | /workspace/coverage/default/211.edn_genbits.2437319546 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 221613839 ps |
| CPU time | 3.18 seconds |
| Started | Jan 17 01:40:59 PM PST 24 |
| Finished | Jan 17 01:41:02 PM PST 24 |
| Peak memory | 214208 kb |
| Host | smart-070f3ef8-dfee-4182-979e-60135d0e79f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2437319546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2437319546 |
| Directory | /workspace/211.edn_genbits/latest |
| Test location | /workspace/coverage/default/212.edn_genbits.3612423008 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 32736693 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:40:55 PM PST 24 |
| Finished | Jan 17 01:40:56 PM PST 24 |
| Peak memory | 205396 kb |
| Host | smart-f2fcd915-88d7-47c3-831e-bc675800ad83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3612423008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3612423008 |
| Directory | /workspace/212.edn_genbits/latest |
| Test location | /workspace/coverage/default/214.edn_genbits.2857160992 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 136324075 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:40:56 PM PST 24 |
| Finished | Jan 17 01:40:57 PM PST 24 |
| Peak memory | 204956 kb |
| Host | smart-01bfae6b-9253-464c-a436-7de786e81d98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2857160992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2857160992 |
| Directory | /workspace/214.edn_genbits/latest |
| Test location | /workspace/coverage/default/215.edn_genbits.60973207 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 42659708 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:40:58 PM PST 24 |
| Finished | Jan 17 01:41:00 PM PST 24 |
| Peak memory | 205044 kb |
| Host | smart-3ffdcfd6-02a2-4b80-aff6-576691f78ac0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60973207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.60973207 |
| Directory | /workspace/215.edn_genbits/latest |
| Test location | /workspace/coverage/default/217.edn_genbits.2504524918 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 41284449 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 01:40:59 PM PST 24 |
| Finished | Jan 17 01:41:01 PM PST 24 |
| Peak memory | 205408 kb |
| Host | smart-3a67fcd9-6630-4708-bac3-d48e4f30cd2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2504524918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2504524918 |
| Directory | /workspace/217.edn_genbits/latest |
| Test location | /workspace/coverage/default/218.edn_genbits.3882490641 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 190171900 ps |
| CPU time | 3.03 seconds |
| Started | Jan 17 01:40:56 PM PST 24 |
| Finished | Jan 17 01:41:00 PM PST 24 |
| Peak memory | 214196 kb |
| Host | smart-3f2ac855-3dda-4370-9415-a1cb4e1c5c53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3882490641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3882490641 |
| Directory | /workspace/218.edn_genbits/latest |
| Test location | /workspace/coverage/default/219.edn_genbits.2312904779 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 15077966 ps |
| CPU time | 1.11 seconds |
| Started | Jan 17 01:41:01 PM PST 24 |
| Finished | Jan 17 01:41:05 PM PST 24 |
| Peak memory | 205564 kb |
| Host | smart-b2bcb55e-c2f2-4713-9f36-9d3446c07ad2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2312904779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2312904779 |
| Directory | /workspace/219.edn_genbits/latest |
| Test location | /workspace/coverage/default/22.edn_alert.2529062435 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 20065448 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:37:47 PM PST 24 |
| Finished | Jan 17 01:37:51 PM PST 24 |
| Peak memory | 205908 kb |
| Host | smart-a8533bc3-824a-4834-88b9-57ad929ba26b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2529062435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2529062435 |
| Directory | /workspace/22.edn_alert/latest |
| Test location | /workspace/coverage/default/22.edn_alert_test.1754688893 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 20704817 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:38:01 PM PST 24 |
| Finished | Jan 17 01:38:04 PM PST 24 |
| Peak memory | 204460 kb |
| Host | smart-12e6d6b7-ed70-4127-bb70-afc3f9fbe6a8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754688893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1754688893 |
| Directory | /workspace/22.edn_alert_test/latest |
| Test location | /workspace/coverage/default/22.edn_disable.2561546792 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 13348081 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:37:58 PM PST 24 |
| Finished | Jan 17 01:37:59 PM PST 24 |
| Peak memory | 214432 kb |
| Host | smart-471a0984-c0b3-4f92-b89e-0ec4b642bbe6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561546792 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2561546792 |
| Directory | /workspace/22.edn_disable/latest |
| Test location | /workspace/coverage/default/22.edn_err.1829530661 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 94924261 ps |
| CPU time | 1.1 seconds |
| Started | Jan 17 01:37:47 PM PST 24 |
| Finished | Jan 17 01:37:51 PM PST 24 |
| Peak memory | 217288 kb |
| Host | smart-b6aec0ed-098e-403a-8793-df310dcb4e55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1829530661 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1829530661 |
| Directory | /workspace/22.edn_err/latest |
| Test location | /workspace/coverage/default/22.edn_genbits.1360020634 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 48889841 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:37:48 PM PST 24 |
| Finished | Jan 17 01:37:51 PM PST 24 |
| Peak memory | 204888 kb |
| Host | smart-7ddf29e5-abe3-459c-a77d-de651e38b4c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1360020634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1360020634 |
| Directory | /workspace/22.edn_genbits/latest |
| Test location | /workspace/coverage/default/22.edn_intr.1295763894 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 19430487 ps |
| CPU time | 1.07 seconds |
| Started | Jan 17 01:37:47 PM PST 24 |
| Finished | Jan 17 01:37:51 PM PST 24 |
| Peak memory | 214472 kb |
| Host | smart-319595b9-d6f0-4bf3-a341-680bbba37050 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1295763894 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1295763894 |
| Directory | /workspace/22.edn_intr/latest |
| Test location | /workspace/coverage/default/22.edn_smoke.1209498455 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 15048244 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 01:37:49 PM PST 24 |
| Finished | Jan 17 01:37:51 PM PST 24 |
| Peak memory | 204828 kb |
| Host | smart-6d8c1c3d-c3a7-4a8d-a817-c3970c117ea6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1209498455 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1209498455 |
| Directory | /workspace/22.edn_smoke/latest |
| Test location | /workspace/coverage/default/22.edn_stress_all.1208600370 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 40556325 ps |
| CPU time | 1.34 seconds |
| Started | Jan 17 01:37:48 PM PST 24 |
| Finished | Jan 17 01:37:51 PM PST 24 |
| Peak memory | 205384 kb |
| Host | smart-ea2556bc-d543-451e-b307-84a35097c1c0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208600370 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1208600370 |
| Directory | /workspace/22.edn_stress_all/latest |
| Test location | /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1588336625 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 123006402638 ps |
| CPU time | 995.97 seconds |
| Started | Jan 17 01:37:47 PM PST 24 |
| Finished | Jan 17 01:54:26 PM PST 24 |
| Peak memory | 217512 kb |
| Host | smart-89d2f629-6266-49a3-a8ea-dd2f606e05ce |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588336625 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1588336625 |
| Directory | /workspace/22.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/220.edn_genbits.1191682216 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 23495728 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 01:41:02 PM PST 24 |
| Finished | Jan 17 01:41:05 PM PST 24 |
| Peak memory | 205148 kb |
| Host | smart-3c49148f-d4d0-4382-b2b4-5702c8a22967 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1191682216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1191682216 |
| Directory | /workspace/220.edn_genbits/latest |
| Test location | /workspace/coverage/default/221.edn_genbits.3047356056 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 19686735 ps |
| CPU time | 1.1 seconds |
| Started | Jan 17 01:41:01 PM PST 24 |
| Finished | Jan 17 01:41:05 PM PST 24 |
| Peak memory | 205732 kb |
| Host | smart-34558ce2-93ee-4b4b-a409-0556b2a47b40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3047356056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3047356056 |
| Directory | /workspace/221.edn_genbits/latest |
| Test location | /workspace/coverage/default/222.edn_genbits.3660605527 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 39484785 ps |
| CPU time | 1.06 seconds |
| Started | Jan 17 01:41:15 PM PST 24 |
| Finished | Jan 17 01:41:19 PM PST 24 |
| Peak memory | 205452 kb |
| Host | smart-fa461b17-6525-4dc7-af61-1f0361804955 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3660605527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3660605527 |
| Directory | /workspace/222.edn_genbits/latest |
| Test location | /workspace/coverage/default/223.edn_genbits.3275292719 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 53690637 ps |
| CPU time | 2.37 seconds |
| Started | Jan 17 01:41:07 PM PST 24 |
| Finished | Jan 17 01:41:10 PM PST 24 |
| Peak memory | 214144 kb |
| Host | smart-09162431-325c-458e-a901-34d994478f0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3275292719 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3275292719 |
| Directory | /workspace/223.edn_genbits/latest |
| Test location | /workspace/coverage/default/224.edn_genbits.3508302794 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 28654385 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:41:17 PM PST 24 |
| Finished | Jan 17 01:41:20 PM PST 24 |
| Peak memory | 214164 kb |
| Host | smart-3c856776-ea67-4061-a720-c0f5cecf338a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3508302794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3508302794 |
| Directory | /workspace/224.edn_genbits/latest |
| Test location | /workspace/coverage/default/225.edn_genbits.922605310 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 15112068 ps |
| CPU time | 1.02 seconds |
| Started | Jan 17 01:41:10 PM PST 24 |
| Finished | Jan 17 01:41:11 PM PST 24 |
| Peak memory | 205312 kb |
| Host | smart-09a248af-aefc-4664-9b3d-90188987ee62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=922605310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.922605310 |
| Directory | /workspace/225.edn_genbits/latest |
| Test location | /workspace/coverage/default/226.edn_genbits.2200998881 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 23602974 ps |
| CPU time | 1.19 seconds |
| Started | Jan 17 01:41:12 PM PST 24 |
| Finished | Jan 17 01:41:17 PM PST 24 |
| Peak memory | 214060 kb |
| Host | smart-db13ec53-da47-40d2-89fa-c57bfcc31ed9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2200998881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2200998881 |
| Directory | /workspace/226.edn_genbits/latest |
| Test location | /workspace/coverage/default/227.edn_genbits.3174770221 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 129272476 ps |
| CPU time | 3.06 seconds |
| Started | Jan 17 01:41:12 PM PST 24 |
| Finished | Jan 17 01:41:19 PM PST 24 |
| Peak memory | 214064 kb |
| Host | smart-79195d4c-8a0d-4e35-aab5-8491904f9d2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3174770221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3174770221 |
| Directory | /workspace/227.edn_genbits/latest |
| Test location | /workspace/coverage/default/228.edn_genbits.1468253226 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 30142998 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:41:07 PM PST 24 |
| Finished | Jan 17 01:41:09 PM PST 24 |
| Peak memory | 205160 kb |
| Host | smart-58c02e47-d0e0-488d-b362-3bb2b8f92b90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1468253226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1468253226 |
| Directory | /workspace/228.edn_genbits/latest |
| Test location | /workspace/coverage/default/229.edn_genbits.1149199561 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 15984467 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 01:41:10 PM PST 24 |
| Finished | Jan 17 01:41:12 PM PST 24 |
| Peak memory | 205524 kb |
| Host | smart-c28ff51d-f27f-4423-a260-39c19213dd0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1149199561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1149199561 |
| Directory | /workspace/229.edn_genbits/latest |
| Test location | /workspace/coverage/default/23.edn_alert.3287349912 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 63843201 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:37:58 PM PST 24 |
| Finished | Jan 17 01:38:00 PM PST 24 |
| Peak memory | 205640 kb |
| Host | smart-5beacb99-14a7-498b-948f-d92c779c2b14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3287349912 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3287349912 |
| Directory | /workspace/23.edn_alert/latest |
| Test location | /workspace/coverage/default/23.edn_alert_test.1250503270 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 130860836 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:38:06 PM PST 24 |
| Finished | Jan 17 01:38:09 PM PST 24 |
| Peak memory | 204588 kb |
| Host | smart-fe173423-dd7e-4c6a-ab60-0bb1d6059f0c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250503270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1250503270 |
| Directory | /workspace/23.edn_alert_test/latest |
| Test location | /workspace/coverage/default/23.edn_disable.2074565292 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 12272493 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:37:57 PM PST 24 |
| Finished | Jan 17 01:37:58 PM PST 24 |
| Peak memory | 214336 kb |
| Host | smart-4ada1499-9ce7-455c-aa66-07a00baae6eb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074565292 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.2074565292 |
| Directory | /workspace/23.edn_disable/latest |
| Test location | /workspace/coverage/default/23.edn_err.3294284964 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 32902691 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 01:38:06 PM PST 24 |
| Finished | Jan 17 01:38:09 PM PST 24 |
| Peak memory | 215540 kb |
| Host | smart-b7dff753-2742-4182-b952-4d881acdb7eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3294284964 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3294284964 |
| Directory | /workspace/23.edn_err/latest |
| Test location | /workspace/coverage/default/23.edn_genbits.4220793660 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 46914223 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:37:58 PM PST 24 |
| Finished | Jan 17 01:38:00 PM PST 24 |
| Peak memory | 205120 kb |
| Host | smart-211d1b3c-807f-48bc-a067-ed8215d33fa0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4220793660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.4220793660 |
| Directory | /workspace/23.edn_genbits/latest |
| Test location | /workspace/coverage/default/23.edn_intr.4007505752 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 19469949 ps |
| CPU time | 1.17 seconds |
| Started | Jan 17 01:38:00 PM PST 24 |
| Finished | Jan 17 01:38:02 PM PST 24 |
| Peak memory | 222020 kb |
| Host | smart-ab5e21c9-08b1-4466-a303-f561948b744c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4007505752 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.4007505752 |
| Directory | /workspace/23.edn_intr/latest |
| Test location | /workspace/coverage/default/23.edn_smoke.1707975060 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 44722177 ps |
| CPU time | 0.8 seconds |
| Started | Jan 17 01:37:58 PM PST 24 |
| Finished | Jan 17 01:38:00 PM PST 24 |
| Peak memory | 204708 kb |
| Host | smart-97f1580c-4481-4644-a158-3f25f7fd641e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1707975060 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1707975060 |
| Directory | /workspace/23.edn_smoke/latest |
| Test location | /workspace/coverage/default/23.edn_stress_all.585150455 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 1312462078 ps |
| CPU time | 3.98 seconds |
| Started | Jan 17 01:37:58 PM PST 24 |
| Finished | Jan 17 01:38:03 PM PST 24 |
| Peak memory | 206088 kb |
| Host | smart-9a794c09-410f-4a93-84fd-bfbd1c5f9fd0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585150455 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.585150455 |
| Directory | /workspace/23.edn_stress_all/latest |
| Test location | /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1336294531 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 115905571644 ps |
| CPU time | 644.97 seconds |
| Started | Jan 17 01:38:00 PM PST 24 |
| Finished | Jan 17 01:48:47 PM PST 24 |
| Peak memory | 216100 kb |
| Host | smart-21143ec7-45b0-4366-b177-12a71ebbdd35 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336294531 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.1336294531 |
| Directory | /workspace/23.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/230.edn_genbits.1185552638 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 33855593 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:41:16 PM PST 24 |
| Finished | Jan 17 01:41:19 PM PST 24 |
| Peak memory | 205412 kb |
| Host | smart-6dcf8057-edb1-4ece-bbd5-ab13f8039f78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1185552638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1185552638 |
| Directory | /workspace/230.edn_genbits/latest |
| Test location | /workspace/coverage/default/231.edn_genbits.23691611 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 82048866 ps |
| CPU time | 2.64 seconds |
| Started | Jan 17 01:41:11 PM PST 24 |
| Finished | Jan 17 01:41:17 PM PST 24 |
| Peak memory | 214148 kb |
| Host | smart-024eef15-76c1-44df-8ea4-6518fa9e37f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=23691611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.23691611 |
| Directory | /workspace/231.edn_genbits/latest |
| Test location | /workspace/coverage/default/232.edn_genbits.1849197273 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 16028516 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:41:13 PM PST 24 |
| Finished | Jan 17 01:41:18 PM PST 24 |
| Peak memory | 214168 kb |
| Host | smart-58ce4297-3b42-4506-a37c-9b27afd6f30a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1849197273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1849197273 |
| Directory | /workspace/232.edn_genbits/latest |
| Test location | /workspace/coverage/default/233.edn_genbits.1377881440 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 26564551 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:41:10 PM PST 24 |
| Finished | Jan 17 01:41:12 PM PST 24 |
| Peak memory | 205164 kb |
| Host | smart-aa81cf48-0bf2-4225-89e5-d1af5fc71258 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1377881440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1377881440 |
| Directory | /workspace/233.edn_genbits/latest |
| Test location | /workspace/coverage/default/234.edn_genbits.2776529401 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 38577618 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:41:08 PM PST 24 |
| Finished | Jan 17 01:41:09 PM PST 24 |
| Peak memory | 205604 kb |
| Host | smart-53ca5674-e473-4166-8fa1-5aa1049c4ca4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2776529401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2776529401 |
| Directory | /workspace/234.edn_genbits/latest |
| Test location | /workspace/coverage/default/235.edn_genbits.2742013085 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 17468084 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:41:14 PM PST 24 |
| Finished | Jan 17 01:41:18 PM PST 24 |
| Peak memory | 205068 kb |
| Host | smart-06ad8b45-c3a7-41eb-a2fc-ffce9de12edf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2742013085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2742013085 |
| Directory | /workspace/235.edn_genbits/latest |
| Test location | /workspace/coverage/default/236.edn_genbits.3090031858 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 34094699 ps |
| CPU time | 1.59 seconds |
| Started | Jan 17 01:41:07 PM PST 24 |
| Finished | Jan 17 01:41:09 PM PST 24 |
| Peak memory | 214088 kb |
| Host | smart-4c28ae58-15a6-4e32-82a3-b8916825bfc5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3090031858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3090031858 |
| Directory | /workspace/236.edn_genbits/latest |
| Test location | /workspace/coverage/default/237.edn_genbits.1482926740 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 38570808 ps |
| CPU time | 1.07 seconds |
| Started | Jan 17 01:41:10 PM PST 24 |
| Finished | Jan 17 01:41:12 PM PST 24 |
| Peak memory | 205428 kb |
| Host | smart-aae44837-98da-4c76-b4df-67a7d09bb04e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1482926740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.1482926740 |
| Directory | /workspace/237.edn_genbits/latest |
| Test location | /workspace/coverage/default/238.edn_genbits.2351575993 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 26007611 ps |
| CPU time | 1.21 seconds |
| Started | Jan 17 01:41:14 PM PST 24 |
| Finished | Jan 17 01:41:18 PM PST 24 |
| Peak memory | 205436 kb |
| Host | smart-94da202e-de6d-40f9-a3c6-0afd072b1037 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2351575993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2351575993 |
| Directory | /workspace/238.edn_genbits/latest |
| Test location | /workspace/coverage/default/239.edn_genbits.408276956 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 23641417 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:41:11 PM PST 24 |
| Finished | Jan 17 01:41:14 PM PST 24 |
| Peak memory | 205408 kb |
| Host | smart-4e54bdb6-877f-487c-a445-cb45fb2ec1fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=408276956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.408276956 |
| Directory | /workspace/239.edn_genbits/latest |
| Test location | /workspace/coverage/default/24.edn_alert.451355421 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 41354720 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:38:03 PM PST 24 |
| Finished | Jan 17 01:38:08 PM PST 24 |
| Peak memory | 205940 kb |
| Host | smart-cf954ce2-718c-42a0-89bf-eddbb73ded1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=451355421 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.451355421 |
| Directory | /workspace/24.edn_alert/latest |
| Test location | /workspace/coverage/default/24.edn_alert_test.1424339046 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 16373567 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:37:59 PM PST 24 |
| Finished | Jan 17 01:38:01 PM PST 24 |
| Peak memory | 204340 kb |
| Host | smart-d526a635-9308-429b-908b-91c015f9968b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424339046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1424339046 |
| Directory | /workspace/24.edn_alert_test/latest |
| Test location | /workspace/coverage/default/24.edn_disable.621127077 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 29462545 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:37:58 PM PST 24 |
| Finished | Jan 17 01:37:59 PM PST 24 |
| Peak memory | 214372 kb |
| Host | smart-cc74a122-a9df-4c44-9836-701763086c23 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621127077 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.621127077 |
| Directory | /workspace/24.edn_disable/latest |
| Test location | /workspace/coverage/default/24.edn_disable_auto_req_mode.789682773 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 23173630 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 01:38:06 PM PST 24 |
| Finished | Jan 17 01:38:08 PM PST 24 |
| Peak memory | 214696 kb |
| Host | smart-e33b4966-b873-4c9c-940a-80b748b4e4c9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789682773 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di sable_auto_req_mode.789682773 |
| Directory | /workspace/24.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/24.edn_err.2479696249 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 34835696 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:37:57 PM PST 24 |
| Finished | Jan 17 01:37:59 PM PST 24 |
| Peak memory | 215608 kb |
| Host | smart-54e95212-d180-4297-815d-3960f783b43c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2479696249 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2479696249 |
| Directory | /workspace/24.edn_err/latest |
| Test location | /workspace/coverage/default/24.edn_genbits.1817455236 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 59726742 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:37:59 PM PST 24 |
| Finished | Jan 17 01:38:01 PM PST 24 |
| Peak memory | 204752 kb |
| Host | smart-96a783b2-b886-4b60-9e5b-9a7f719c46bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1817455236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1817455236 |
| Directory | /workspace/24.edn_genbits/latest |
| Test location | /workspace/coverage/default/24.edn_intr.2961736994 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 30344300 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 01:37:57 PM PST 24 |
| Finished | Jan 17 01:37:58 PM PST 24 |
| Peak memory | 221940 kb |
| Host | smart-2ec246df-5577-4fe6-887d-0c9f86f27b8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961736994 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.2961736994 |
| Directory | /workspace/24.edn_intr/latest |
| Test location | /workspace/coverage/default/24.edn_smoke.537539496 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 45584937 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:38:06 PM PST 24 |
| Finished | Jan 17 01:38:08 PM PST 24 |
| Peak memory | 204872 kb |
| Host | smart-8c140a1c-261c-4a65-b931-14436b0c31e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537539496 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.537539496 |
| Directory | /workspace/24.edn_smoke/latest |
| Test location | /workspace/coverage/default/24.edn_stress_all.2066926518 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 113826299 ps |
| CPU time | 2.8 seconds |
| Started | Jan 17 01:38:03 PM PST 24 |
| Finished | Jan 17 01:38:09 PM PST 24 |
| Peak memory | 205860 kb |
| Host | smart-8b299f2f-3a86-4900-b15b-2c134881791f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066926518 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2066926518 |
| Directory | /workspace/24.edn_stress_all/latest |
| Test location | /workspace/coverage/default/240.edn_genbits.12826486 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 33290196 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:41:10 PM PST 24 |
| Finished | Jan 17 01:41:11 PM PST 24 |
| Peak memory | 204880 kb |
| Host | smart-be544484-5dc2-4129-b884-91dc5d633807 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12826486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.12826486 |
| Directory | /workspace/240.edn_genbits/latest |
| Test location | /workspace/coverage/default/241.edn_genbits.427521443 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 21109515 ps |
| CPU time | 1.13 seconds |
| Started | Jan 17 01:41:09 PM PST 24 |
| Finished | Jan 17 01:41:11 PM PST 24 |
| Peak memory | 205624 kb |
| Host | smart-653ba308-dbb2-4f89-a5de-c3ad473fe47f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=427521443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.427521443 |
| Directory | /workspace/241.edn_genbits/latest |
| Test location | /workspace/coverage/default/242.edn_genbits.3659655534 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 78565922 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 01:41:13 PM PST 24 |
| Finished | Jan 17 01:41:18 PM PST 24 |
| Peak memory | 214156 kb |
| Host | smart-5a651cc5-44cc-4a59-8d21-7a0e20a2affa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3659655534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3659655534 |
| Directory | /workspace/242.edn_genbits/latest |
| Test location | /workspace/coverage/default/243.edn_genbits.4002674565 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 78126634 ps |
| CPU time | 1.19 seconds |
| Started | Jan 17 01:41:14 PM PST 24 |
| Finished | Jan 17 01:41:18 PM PST 24 |
| Peak memory | 205524 kb |
| Host | smart-70776ec3-810c-4046-99b9-f6cdf65d9656 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4002674565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.4002674565 |
| Directory | /workspace/243.edn_genbits/latest |
| Test location | /workspace/coverage/default/244.edn_genbits.3295941841 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 75698539 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:41:08 PM PST 24 |
| Finished | Jan 17 01:41:10 PM PST 24 |
| Peak memory | 205208 kb |
| Host | smart-127d4908-13d2-4091-9c8f-99c0096f8dc0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3295941841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3295941841 |
| Directory | /workspace/244.edn_genbits/latest |
| Test location | /workspace/coverage/default/245.edn_genbits.2818194904 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 26141021 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:41:08 PM PST 24 |
| Finished | Jan 17 01:41:10 PM PST 24 |
| Peak memory | 205376 kb |
| Host | smart-eb777f7f-f6fa-49d7-ab4b-541fd403d415 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2818194904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2818194904 |
| Directory | /workspace/245.edn_genbits/latest |
| Test location | /workspace/coverage/default/246.edn_genbits.2156947737 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 55325066 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:41:10 PM PST 24 |
| Finished | Jan 17 01:41:12 PM PST 24 |
| Peak memory | 204864 kb |
| Host | smart-48135064-1446-460e-ad6f-0cfd1d10a9d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2156947737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2156947737 |
| Directory | /workspace/246.edn_genbits/latest |
| Test location | /workspace/coverage/default/247.edn_genbits.107372255 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 28997442 ps |
| CPU time | 1.04 seconds |
| Started | Jan 17 01:41:13 PM PST 24 |
| Finished | Jan 17 01:41:17 PM PST 24 |
| Peak memory | 205400 kb |
| Host | smart-3021d81f-3d9d-40e4-8e3d-0e2e399ca8b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=107372255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.107372255 |
| Directory | /workspace/247.edn_genbits/latest |
| Test location | /workspace/coverage/default/248.edn_genbits.3550470255 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 17789807 ps |
| CPU time | 1.1 seconds |
| Started | Jan 17 01:41:12 PM PST 24 |
| Finished | Jan 17 01:41:16 PM PST 24 |
| Peak memory | 205700 kb |
| Host | smart-29eb34e6-fa86-44c3-ba02-a314c6b415aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550470255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3550470255 |
| Directory | /workspace/248.edn_genbits/latest |
| Test location | /workspace/coverage/default/25.edn_alert.1087713632 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 19472238 ps |
| CPU time | 1.06 seconds |
| Started | Jan 17 01:38:06 PM PST 24 |
| Finished | Jan 17 01:38:08 PM PST 24 |
| Peak memory | 205944 kb |
| Host | smart-30e91143-61a9-4675-8a2b-e4bbbd10e1aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1087713632 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1087713632 |
| Directory | /workspace/25.edn_alert/latest |
| Test location | /workspace/coverage/default/25.edn_alert_test.3006054445 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 14171722 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:38:05 PM PST 24 |
| Finished | Jan 17 01:38:08 PM PST 24 |
| Peak memory | 204092 kb |
| Host | smart-f376ade5-9220-47c3-899f-aea63b297ffb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006054445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3006054445 |
| Directory | /workspace/25.edn_alert_test/latest |
| Test location | /workspace/coverage/default/25.edn_disable.715961980 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 19628794 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:38:07 PM PST 24 |
| Finished | Jan 17 01:38:09 PM PST 24 |
| Peak memory | 214408 kb |
| Host | smart-844c5e22-5f3a-4e6f-9e08-01e2c8f4b2c1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715961980 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.715961980 |
| Directory | /workspace/25.edn_disable/latest |
| Test location | /workspace/coverage/default/25.edn_disable_auto_req_mode.126256127 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 101582451 ps |
| CPU time | 1.14 seconds |
| Started | Jan 17 01:38:10 PM PST 24 |
| Finished | Jan 17 01:38:12 PM PST 24 |
| Peak memory | 214360 kb |
| Host | smart-c7c92269-1db3-489c-8c91-3d8ca610ab50 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126256127 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di sable_auto_req_mode.126256127 |
| Directory | /workspace/25.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/25.edn_err.4223895902 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 49626708 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 01:38:05 PM PST 24 |
| Finished | Jan 17 01:38:08 PM PST 24 |
| Peak memory | 221976 kb |
| Host | smart-aaf974d6-20ab-4897-9a03-67d07d3716a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4223895902 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.4223895902 |
| Directory | /workspace/25.edn_err/latest |
| Test location | /workspace/coverage/default/25.edn_genbits.3831140115 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 35353259 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:38:00 PM PST 24 |
| Finished | Jan 17 01:38:02 PM PST 24 |
| Peak memory | 205536 kb |
| Host | smart-6fbfcfc0-ac7d-4498-8718-b51928a5e796 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3831140115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3831140115 |
| Directory | /workspace/25.edn_genbits/latest |
| Test location | /workspace/coverage/default/25.edn_intr.1519705990 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 25620311 ps |
| CPU time | 1.04 seconds |
| Started | Jan 17 01:38:07 PM PST 24 |
| Finished | Jan 17 01:38:09 PM PST 24 |
| Peak memory | 221476 kb |
| Host | smart-bb0d655e-b091-45ec-8d6e-c47a0bd5c913 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1519705990 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1519705990 |
| Directory | /workspace/25.edn_intr/latest |
| Test location | /workspace/coverage/default/25.edn_smoke.4108480783 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 45959135 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:38:00 PM PST 24 |
| Finished | Jan 17 01:38:02 PM PST 24 |
| Peak memory | 204692 kb |
| Host | smart-503ba9d7-a177-476d-bcc0-7dca3be73920 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4108480783 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.4108480783 |
| Directory | /workspace/25.edn_smoke/latest |
| Test location | /workspace/coverage/default/25.edn_stress_all.3871429931 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 54927863 ps |
| CPU time | 1.53 seconds |
| Started | Jan 17 01:37:55 PM PST 24 |
| Finished | Jan 17 01:37:57 PM PST 24 |
| Peak memory | 205476 kb |
| Host | smart-a1b8018d-676d-4b30-91a0-f40c2ae0a5ba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871429931 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3871429931 |
| Directory | /workspace/25.edn_stress_all/latest |
| Test location | /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2383590630 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 103551358794 ps |
| CPU time | 1153.06 seconds |
| Started | Jan 17 01:37:57 PM PST 24 |
| Finished | Jan 17 01:57:11 PM PST 24 |
| Peak memory | 217256 kb |
| Host | smart-1f16246f-c747-43cd-8e2d-37d249bbb717 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383590630 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2383590630 |
| Directory | /workspace/25.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/251.edn_genbits.1646248295 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 16528421 ps |
| CPU time | 1.02 seconds |
| Started | Jan 17 01:41:09 PM PST 24 |
| Finished | Jan 17 01:41:11 PM PST 24 |
| Peak memory | 205052 kb |
| Host | smart-a176e8e5-2ca9-4edc-ab3f-fe009f486ff0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1646248295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1646248295 |
| Directory | /workspace/251.edn_genbits/latest |
| Test location | /workspace/coverage/default/252.edn_genbits.2322464917 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 42231766 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:41:08 PM PST 24 |
| Finished | Jan 17 01:41:09 PM PST 24 |
| Peak memory | 204896 kb |
| Host | smart-283ea4a1-6c8a-4ea0-b1e4-11d3477fcf37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2322464917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2322464917 |
| Directory | /workspace/252.edn_genbits/latest |
| Test location | /workspace/coverage/default/253.edn_genbits.2842153758 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 19826337 ps |
| CPU time | 1.19 seconds |
| Started | Jan 17 01:41:09 PM PST 24 |
| Finished | Jan 17 01:41:11 PM PST 24 |
| Peak memory | 205564 kb |
| Host | smart-919ad3f7-cf0f-49eb-92c6-26bab41e00fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2842153758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2842153758 |
| Directory | /workspace/253.edn_genbits/latest |
| Test location | /workspace/coverage/default/254.edn_genbits.2660001178 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 231587749 ps |
| CPU time | 3.41 seconds |
| Started | Jan 17 01:41:14 PM PST 24 |
| Finished | Jan 17 01:41:21 PM PST 24 |
| Peak memory | 213968 kb |
| Host | smart-f6348cdc-4d67-4fad-8bfd-a373a1829d14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2660001178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2660001178 |
| Directory | /workspace/254.edn_genbits/latest |
| Test location | /workspace/coverage/default/255.edn_genbits.1765552664 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 25629666 ps |
| CPU time | 1.17 seconds |
| Started | Jan 17 01:41:11 PM PST 24 |
| Finished | Jan 17 01:41:14 PM PST 24 |
| Peak memory | 214172 kb |
| Host | smart-58d74686-60e3-4623-b226-70867d806d6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1765552664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1765552664 |
| Directory | /workspace/255.edn_genbits/latest |
| Test location | /workspace/coverage/default/256.edn_genbits.3875081020 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 38478056 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 01:41:14 PM PST 24 |
| Finished | Jan 17 01:41:18 PM PST 24 |
| Peak memory | 214004 kb |
| Host | smart-32de239e-92ef-42c6-8462-277f2f19017a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3875081020 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3875081020 |
| Directory | /workspace/256.edn_genbits/latest |
| Test location | /workspace/coverage/default/257.edn_genbits.3014744071 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 49414099 ps |
| CPU time | 0.91 seconds |
| Started | Jan 17 01:41:14 PM PST 24 |
| Finished | Jan 17 01:41:18 PM PST 24 |
| Peak memory | 204932 kb |
| Host | smart-e567ca72-a352-41ba-8391-5d882d63f977 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3014744071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3014744071 |
| Directory | /workspace/257.edn_genbits/latest |
| Test location | /workspace/coverage/default/258.edn_genbits.365500794 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 127710167 ps |
| CPU time | 0.91 seconds |
| Started | Jan 17 01:41:14 PM PST 24 |
| Finished | Jan 17 01:41:18 PM PST 24 |
| Peak memory | 205368 kb |
| Host | smart-014b503c-8c6b-41ab-b025-11b4ac29278c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=365500794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.365500794 |
| Directory | /workspace/258.edn_genbits/latest |
| Test location | /workspace/coverage/default/26.edn_alert.3978074574 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 35030007 ps |
| CPU time | 1.02 seconds |
| Started | Jan 17 01:38:07 PM PST 24 |
| Finished | Jan 17 01:38:09 PM PST 24 |
| Peak memory | 205220 kb |
| Host | smart-2b6b214c-cb95-4ad1-aaf0-4e49ae9eb5a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3978074574 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3978074574 |
| Directory | /workspace/26.edn_alert/latest |
| Test location | /workspace/coverage/default/26.edn_alert_test.1049911124 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 22485891 ps |
| CPU time | 0.91 seconds |
| Started | Jan 17 01:38:07 PM PST 24 |
| Finished | Jan 17 01:38:09 PM PST 24 |
| Peak memory | 204432 kb |
| Host | smart-408e1be3-59ee-41d4-8bcc-89bb139e7790 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049911124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1049911124 |
| Directory | /workspace/26.edn_alert_test/latest |
| Test location | /workspace/coverage/default/26.edn_disable.879057441 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 36133293 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:38:07 PM PST 24 |
| Finished | Jan 17 01:38:10 PM PST 24 |
| Peak memory | 214372 kb |
| Host | smart-d24f929a-b12a-4a64-a159-d462f0f02cff |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879057441 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.879057441 |
| Directory | /workspace/26.edn_disable/latest |
| Test location | /workspace/coverage/default/26.edn_disable_auto_req_mode.3783840360 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 31428191 ps |
| CPU time | 1.1 seconds |
| Started | Jan 17 01:38:08 PM PST 24 |
| Finished | Jan 17 01:38:10 PM PST 24 |
| Peak memory | 214512 kb |
| Host | smart-00c1b9e6-b497-425c-854e-56d144176aa9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783840360 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d isable_auto_req_mode.3783840360 |
| Directory | /workspace/26.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/26.edn_err.4221250397 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 40298316 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 01:38:10 PM PST 24 |
| Finished | Jan 17 01:38:11 PM PST 24 |
| Peak memory | 215568 kb |
| Host | smart-1e165b5f-f98e-4033-8078-c291aece6174 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4221250397 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.4221250397 |
| Directory | /workspace/26.edn_err/latest |
| Test location | /workspace/coverage/default/26.edn_genbits.3669108712 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 13867623 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:38:05 PM PST 24 |
| Finished | Jan 17 01:38:08 PM PST 24 |
| Peak memory | 205248 kb |
| Host | smart-44a29e57-45ec-44be-a439-30d244024ea8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3669108712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3669108712 |
| Directory | /workspace/26.edn_genbits/latest |
| Test location | /workspace/coverage/default/26.edn_intr.3723283909 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 31606268 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 01:38:07 PM PST 24 |
| Finished | Jan 17 01:38:10 PM PST 24 |
| Peak memory | 214436 kb |
| Host | smart-ee9fca1a-8715-4d09-b154-7f8c6a952d19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3723283909 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3723283909 |
| Directory | /workspace/26.edn_intr/latest |
| Test location | /workspace/coverage/default/26.edn_smoke.628221202 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 30532424 ps |
| CPU time | 0.91 seconds |
| Started | Jan 17 01:38:06 PM PST 24 |
| Finished | Jan 17 01:38:08 PM PST 24 |
| Peak memory | 204900 kb |
| Host | smart-d2307944-ba61-48d7-a219-e97e40676c66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=628221202 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.628221202 |
| Directory | /workspace/26.edn_smoke/latest |
| Test location | /workspace/coverage/default/26.edn_stress_all.3312867002 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 77530742 ps |
| CPU time | 2.08 seconds |
| Started | Jan 17 01:38:05 PM PST 24 |
| Finished | Jan 17 01:38:09 PM PST 24 |
| Peak memory | 205904 kb |
| Host | smart-dd442924-2f15-486e-809a-2a20993f974c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312867002 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3312867002 |
| Directory | /workspace/26.edn_stress_all/latest |
| Test location | /workspace/coverage/default/26.edn_stress_all_with_rand_reset.577639787 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 36973850018 ps |
| CPU time | 401.49 seconds |
| Started | Jan 17 01:38:06 PM PST 24 |
| Finished | Jan 17 01:44:49 PM PST 24 |
| Peak memory | 214420 kb |
| Host | smart-aed96d1c-125d-41bd-b9dc-73eaa39f45d5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577639787 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.577639787 |
| Directory | /workspace/26.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/260.edn_genbits.23207218 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 72644616 ps |
| CPU time | 1.11 seconds |
| Started | Jan 17 01:41:16 PM PST 24 |
| Finished | Jan 17 01:41:19 PM PST 24 |
| Peak memory | 205388 kb |
| Host | smart-4cc05932-1895-44e7-a8be-771c8eb2b9cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=23207218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.23207218 |
| Directory | /workspace/260.edn_genbits/latest |
| Test location | /workspace/coverage/default/261.edn_genbits.2833131268 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 16465096 ps |
| CPU time | 1.09 seconds |
| Started | Jan 17 01:41:08 PM PST 24 |
| Finished | Jan 17 01:41:10 PM PST 24 |
| Peak memory | 205448 kb |
| Host | smart-7d5476d6-ef30-4615-bc23-c98760e7ddae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2833131268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2833131268 |
| Directory | /workspace/261.edn_genbits/latest |
| Test location | /workspace/coverage/default/262.edn_genbits.3362239795 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 37436845 ps |
| CPU time | 1.18 seconds |
| Started | Jan 17 01:41:18 PM PST 24 |
| Finished | Jan 17 01:41:28 PM PST 24 |
| Peak memory | 214068 kb |
| Host | smart-b64f3b79-4e2b-4ffa-aa2f-af23d385f3d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3362239795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3362239795 |
| Directory | /workspace/262.edn_genbits/latest |
| Test location | /workspace/coverage/default/263.edn_genbits.2166980958 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 54080471 ps |
| CPU time | 1.04 seconds |
| Started | Jan 17 01:41:18 PM PST 24 |
| Finished | Jan 17 01:41:28 PM PST 24 |
| Peak memory | 214264 kb |
| Host | smart-84571606-1f29-4e83-b3d5-02a9177c5dfe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2166980958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2166980958 |
| Directory | /workspace/263.edn_genbits/latest |
| Test location | /workspace/coverage/default/264.edn_genbits.1852925486 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 19705433 ps |
| CPU time | 1.28 seconds |
| Started | Jan 17 01:41:16 PM PST 24 |
| Finished | Jan 17 01:41:20 PM PST 24 |
| Peak memory | 205760 kb |
| Host | smart-40c8ed4f-0b11-4b76-80f4-f0b74df7e45e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1852925486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1852925486 |
| Directory | /workspace/264.edn_genbits/latest |
| Test location | /workspace/coverage/default/265.edn_genbits.1452437418 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 70086377 ps |
| CPU time | 1.06 seconds |
| Started | Jan 17 01:41:15 PM PST 24 |
| Finished | Jan 17 01:41:19 PM PST 24 |
| Peak memory | 205488 kb |
| Host | smart-ab1bfeb3-89e2-47da-85ac-5ee1a91b88f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452437418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1452437418 |
| Directory | /workspace/265.edn_genbits/latest |
| Test location | /workspace/coverage/default/266.edn_genbits.301640543 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 82220671 ps |
| CPU time | 0.91 seconds |
| Started | Jan 17 01:41:16 PM PST 24 |
| Finished | Jan 17 01:41:19 PM PST 24 |
| Peak memory | 205284 kb |
| Host | smart-fb2296e1-8edd-494a-9d40-f46799520b7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=301640543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.301640543 |
| Directory | /workspace/266.edn_genbits/latest |
| Test location | /workspace/coverage/default/267.edn_genbits.1180161188 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 29839315 ps |
| CPU time | 1.09 seconds |
| Started | Jan 17 01:41:18 PM PST 24 |
| Finished | Jan 17 01:41:28 PM PST 24 |
| Peak memory | 205660 kb |
| Host | smart-f88b628d-91ed-4a8a-976b-af4cd0ead62e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1180161188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1180161188 |
| Directory | /workspace/267.edn_genbits/latest |
| Test location | /workspace/coverage/default/268.edn_genbits.1877645990 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 60957051 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:41:20 PM PST 24 |
| Finished | Jan 17 01:41:28 PM PST 24 |
| Peak memory | 214196 kb |
| Host | smart-eb0c5948-80c0-4a70-866c-6b2cb72cdc01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1877645990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1877645990 |
| Directory | /workspace/268.edn_genbits/latest |
| Test location | /workspace/coverage/default/269.edn_genbits.1579835549 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 87844349 ps |
| CPU time | 1.21 seconds |
| Started | Jan 17 01:41:20 PM PST 24 |
| Finished | Jan 17 01:41:28 PM PST 24 |
| Peak memory | 214168 kb |
| Host | smart-7e640cf4-509c-401d-b00d-1c23e392dc1a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1579835549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1579835549 |
| Directory | /workspace/269.edn_genbits/latest |
| Test location | /workspace/coverage/default/27.edn_alert.3725024388 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 25205657 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:38:08 PM PST 24 |
| Finished | Jan 17 01:38:10 PM PST 24 |
| Peak memory | 205364 kb |
| Host | smart-1107143f-c703-4787-aa24-7e9378f20b18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3725024388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.3725024388 |
| Directory | /workspace/27.edn_alert/latest |
| Test location | /workspace/coverage/default/27.edn_alert_test.3274321987 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 22960242 ps |
| CPU time | 0.8 seconds |
| Started | Jan 17 01:38:33 PM PST 24 |
| Finished | Jan 17 01:38:34 PM PST 24 |
| Peak memory | 205012 kb |
| Host | smart-f68ac1e8-6218-4ae1-9570-8c65209b141c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274321987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3274321987 |
| Directory | /workspace/27.edn_alert_test/latest |
| Test location | /workspace/coverage/default/27.edn_disable.3396257986 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 13358508 ps |
| CPU time | 0.91 seconds |
| Started | Jan 17 01:38:08 PM PST 24 |
| Finished | Jan 17 01:38:10 PM PST 24 |
| Peak memory | 214424 kb |
| Host | smart-cebf546a-e1e5-4af2-9c8c-116c0f32d1db |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396257986 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3396257986 |
| Directory | /workspace/27.edn_disable/latest |
| Test location | /workspace/coverage/default/27.edn_disable_auto_req_mode.2466489383 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 38769713 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:38:36 PM PST 24 |
| Finished | Jan 17 01:38:38 PM PST 24 |
| Peak memory | 214432 kb |
| Host | smart-bc58a825-759f-40e3-ad21-c533ee55ef0f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466489383 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d isable_auto_req_mode.2466489383 |
| Directory | /workspace/27.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/27.edn_err.1246312693 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 70255242 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:38:07 PM PST 24 |
| Finished | Jan 17 01:38:09 PM PST 24 |
| Peak memory | 216716 kb |
| Host | smart-f9d12d3a-26bf-4fee-a144-05bc201fc9b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1246312693 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1246312693 |
| Directory | /workspace/27.edn_err/latest |
| Test location | /workspace/coverage/default/27.edn_genbits.425682843 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 27284016 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:38:07 PM PST 24 |
| Finished | Jan 17 01:38:09 PM PST 24 |
| Peak memory | 205116 kb |
| Host | smart-ef337298-ede5-4930-9c26-24786537e0a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=425682843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.425682843 |
| Directory | /workspace/27.edn_genbits/latest |
| Test location | /workspace/coverage/default/27.edn_intr.1481643607 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 21276732 ps |
| CPU time | 1.2 seconds |
| Started | Jan 17 01:38:06 PM PST 24 |
| Finished | Jan 17 01:38:09 PM PST 24 |
| Peak memory | 221508 kb |
| Host | smart-e6f4169a-7a08-42c8-b471-6d2daa547529 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1481643607 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1481643607 |
| Directory | /workspace/27.edn_intr/latest |
| Test location | /workspace/coverage/default/27.edn_smoke.1785476717 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 26275680 ps |
| CPU time | 0.9 seconds |
| Started | Jan 17 01:38:08 PM PST 24 |
| Finished | Jan 17 01:38:10 PM PST 24 |
| Peak memory | 204672 kb |
| Host | smart-3460ec58-6f69-477c-a64e-ac21f5cdfb4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1785476717 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1785476717 |
| Directory | /workspace/27.edn_smoke/latest |
| Test location | /workspace/coverage/default/27.edn_stress_all.2499690396 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 53238213 ps |
| CPU time | 1.61 seconds |
| Started | Jan 17 01:38:06 PM PST 24 |
| Finished | Jan 17 01:38:09 PM PST 24 |
| Peak memory | 204924 kb |
| Host | smart-7e09b994-82a4-4f44-8b4a-610c29cc788e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499690396 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2499690396 |
| Directory | /workspace/27.edn_stress_all/latest |
| Test location | /workspace/coverage/default/27.edn_stress_all_with_rand_reset.889546717 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 9629782769 ps |
| CPU time | 107.79 seconds |
| Started | Jan 17 01:38:05 PM PST 24 |
| Finished | Jan 17 01:39:55 PM PST 24 |
| Peak memory | 215320 kb |
| Host | smart-c73bb6b3-d3ec-4bea-979b-0e04c6636955 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889546717 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.889546717 |
| Directory | /workspace/27.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/270.edn_genbits.4046233118 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 18203932 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:41:19 PM PST 24 |
| Finished | Jan 17 01:41:28 PM PST 24 |
| Peak memory | 205788 kb |
| Host | smart-afa5b771-bcd9-4d82-a1e7-d912421927cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4046233118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.4046233118 |
| Directory | /workspace/270.edn_genbits/latest |
| Test location | /workspace/coverage/default/271.edn_genbits.2550302085 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 128284293 ps |
| CPU time | 3.01 seconds |
| Started | Jan 17 01:41:19 PM PST 24 |
| Finished | Jan 17 01:41:30 PM PST 24 |
| Peak memory | 214388 kb |
| Host | smart-dc952c26-83fe-4581-8813-0bbab294af4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2550302085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2550302085 |
| Directory | /workspace/271.edn_genbits/latest |
| Test location | /workspace/coverage/default/272.edn_genbits.2168202774 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 34936763 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:41:13 PM PST 24 |
| Finished | Jan 17 01:41:18 PM PST 24 |
| Peak memory | 205480 kb |
| Host | smart-7f63dc3e-0795-4d43-bdb8-9973bb66a87a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2168202774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2168202774 |
| Directory | /workspace/272.edn_genbits/latest |
| Test location | /workspace/coverage/default/273.edn_genbits.44664996 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 21987237 ps |
| CPU time | 1.16 seconds |
| Started | Jan 17 01:41:15 PM PST 24 |
| Finished | Jan 17 01:41:19 PM PST 24 |
| Peak memory | 214068 kb |
| Host | smart-f10f0a01-9e91-4bca-8ea9-543d2e10853e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=44664996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.44664996 |
| Directory | /workspace/273.edn_genbits/latest |
| Test location | /workspace/coverage/default/274.edn_genbits.3966889404 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 17762433 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:41:16 PM PST 24 |
| Finished | Jan 17 01:41:19 PM PST 24 |
| Peak memory | 205044 kb |
| Host | smart-3dd07930-87df-47f7-9bd8-51534001e1a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3966889404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3966889404 |
| Directory | /workspace/274.edn_genbits/latest |
| Test location | /workspace/coverage/default/275.edn_genbits.3558882339 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 35573334 ps |
| CPU time | 1.22 seconds |
| Started | Jan 17 01:41:20 PM PST 24 |
| Finished | Jan 17 01:41:28 PM PST 24 |
| Peak memory | 214192 kb |
| Host | smart-d12846ed-37ad-42da-9b43-f1f65ea6e891 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3558882339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3558882339 |
| Directory | /workspace/275.edn_genbits/latest |
| Test location | /workspace/coverage/default/277.edn_genbits.1705917621 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 58102607 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 01:41:19 PM PST 24 |
| Finished | Jan 17 01:41:28 PM PST 24 |
| Peak memory | 204800 kb |
| Host | smart-91ad7f51-bde0-4031-92a1-9aa01aade20b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1705917621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1705917621 |
| Directory | /workspace/277.edn_genbits/latest |
| Test location | /workspace/coverage/default/278.edn_genbits.1016350226 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 20461028 ps |
| CPU time | 1.02 seconds |
| Started | Jan 17 01:41:17 PM PST 24 |
| Finished | Jan 17 01:41:27 PM PST 24 |
| Peak memory | 205368 kb |
| Host | smart-9bb97b33-135e-442c-b2ce-30c144db7f1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1016350226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1016350226 |
| Directory | /workspace/278.edn_genbits/latest |
| Test location | /workspace/coverage/default/28.edn_alert.2165477878 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 20400508 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:38:23 PM PST 24 |
| Finished | Jan 17 01:38:25 PM PST 24 |
| Peak memory | 205904 kb |
| Host | smart-c1a6b44c-45e8-4c46-8b9e-9c3ddcfcbe74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2165477878 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2165477878 |
| Directory | /workspace/28.edn_alert/latest |
| Test location | /workspace/coverage/default/28.edn_alert_test.3221683116 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 19089382 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:38:22 PM PST 24 |
| Finished | Jan 17 01:38:24 PM PST 24 |
| Peak memory | 204516 kb |
| Host | smart-4fff2730-415f-46ef-a7e5-40e6f1af2de5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221683116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3221683116 |
| Directory | /workspace/28.edn_alert_test/latest |
| Test location | /workspace/coverage/default/28.edn_disable.1259571920 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 10777142 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 01:38:21 PM PST 24 |
| Finished | Jan 17 01:38:24 PM PST 24 |
| Peak memory | 214376 kb |
| Host | smart-ba533dfd-c032-4c78-adc9-2c4b0fd8f77f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259571920 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1259571920 |
| Directory | /workspace/28.edn_disable/latest |
| Test location | /workspace/coverage/default/28.edn_disable_auto_req_mode.34780094 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 21795288 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:38:35 PM PST 24 |
| Finished | Jan 17 01:38:37 PM PST 24 |
| Peak memory | 214420 kb |
| Host | smart-eaa54986-5d0f-40e2-bbd9-b3b603d0307d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34780094 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_dis able_auto_req_mode.34780094 |
| Directory | /workspace/28.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/28.edn_err.1161775567 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 73242064 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:38:33 PM PST 24 |
| Finished | Jan 17 01:38:35 PM PST 24 |
| Peak memory | 221472 kb |
| Host | smart-e2322fbe-c951-4247-bbff-ffaa4bf4c3cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1161775567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.1161775567 |
| Directory | /workspace/28.edn_err/latest |
| Test location | /workspace/coverage/default/28.edn_genbits.2206540542 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 14339769 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:38:31 PM PST 24 |
| Finished | Jan 17 01:38:32 PM PST 24 |
| Peak memory | 205308 kb |
| Host | smart-6836694b-ce34-4066-81ae-e99486a90471 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2206540542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2206540542 |
| Directory | /workspace/28.edn_genbits/latest |
| Test location | /workspace/coverage/default/28.edn_intr.863586589 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 34274177 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:38:34 PM PST 24 |
| Finished | Jan 17 01:38:35 PM PST 24 |
| Peak memory | 214384 kb |
| Host | smart-c2e3adee-ecd9-4404-ba49-2e7cb4a55d62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=863586589 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.863586589 |
| Directory | /workspace/28.edn_intr/latest |
| Test location | /workspace/coverage/default/28.edn_smoke.1457829458 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 31446196 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:38:22 PM PST 24 |
| Finished | Jan 17 01:38:24 PM PST 24 |
| Peak memory | 204576 kb |
| Host | smart-d8b7a2e7-0749-4aa8-a7ca-2651942c5b19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1457829458 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1457829458 |
| Directory | /workspace/28.edn_smoke/latest |
| Test location | /workspace/coverage/default/28.edn_stress_all.507480730 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 508787308 ps |
| CPU time | 2.95 seconds |
| Started | Jan 17 01:38:21 PM PST 24 |
| Finished | Jan 17 01:38:26 PM PST 24 |
| Peak memory | 205944 kb |
| Host | smart-c53d5d23-cdce-4d97-a8aa-77cf3dcd6049 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507480730 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.507480730 |
| Directory | /workspace/28.edn_stress_all/latest |
| Test location | /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1937509076 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 321804171761 ps |
| CPU time | 1763.3 seconds |
| Started | Jan 17 01:38:21 PM PST 24 |
| Finished | Jan 17 02:07:47 PM PST 24 |
| Peak memory | 219692 kb |
| Host | smart-d166e7a4-9d12-44d8-afdd-1499238e8898 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937509076 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1937509076 |
| Directory | /workspace/28.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/280.edn_genbits.207892860 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 52584378 ps |
| CPU time | 1.23 seconds |
| Started | Jan 17 01:41:16 PM PST 24 |
| Finished | Jan 17 01:41:19 PM PST 24 |
| Peak memory | 205508 kb |
| Host | smart-77e64dc1-797c-4fb5-bd3a-459a971881a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=207892860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.207892860 |
| Directory | /workspace/280.edn_genbits/latest |
| Test location | /workspace/coverage/default/281.edn_genbits.1445695277 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 57590489 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 01:41:20 PM PST 24 |
| Finished | Jan 17 01:41:28 PM PST 24 |
| Peak memory | 204784 kb |
| Host | smart-e9dea369-2c3b-400c-8391-9aeb68408db6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1445695277 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1445695277 |
| Directory | /workspace/281.edn_genbits/latest |
| Test location | /workspace/coverage/default/282.edn_genbits.1483283522 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 13110769 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:41:16 PM PST 24 |
| Finished | Jan 17 01:41:20 PM PST 24 |
| Peak memory | 205112 kb |
| Host | smart-e83aba2e-e0e8-4104-885d-484cf350dd5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1483283522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1483283522 |
| Directory | /workspace/282.edn_genbits/latest |
| Test location | /workspace/coverage/default/283.edn_genbits.2579875392 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 47330201 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:41:20 PM PST 24 |
| Finished | Jan 17 01:41:28 PM PST 24 |
| Peak memory | 205204 kb |
| Host | smart-8d28f83c-c912-475a-8971-896e4d4f71fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2579875392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2579875392 |
| Directory | /workspace/283.edn_genbits/latest |
| Test location | /workspace/coverage/default/284.edn_genbits.3824584004 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 50055549 ps |
| CPU time | 1.2 seconds |
| Started | Jan 17 01:41:19 PM PST 24 |
| Finished | Jan 17 01:41:28 PM PST 24 |
| Peak memory | 214172 kb |
| Host | smart-a42285c9-b586-45c5-afa0-bb0ba4e873e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3824584004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3824584004 |
| Directory | /workspace/284.edn_genbits/latest |
| Test location | /workspace/coverage/default/285.edn_genbits.3431340572 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 18180733 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:41:14 PM PST 24 |
| Finished | Jan 17 01:41:18 PM PST 24 |
| Peak memory | 204888 kb |
| Host | smart-4372cabe-4e49-47f8-92ec-37abcb5259d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3431340572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3431340572 |
| Directory | /workspace/285.edn_genbits/latest |
| Test location | /workspace/coverage/default/286.edn_genbits.3504739770 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 20499384 ps |
| CPU time | 1.17 seconds |
| Started | Jan 17 01:41:17 PM PST 24 |
| Finished | Jan 17 01:41:20 PM PST 24 |
| Peak memory | 214216 kb |
| Host | smart-4e417075-643a-456b-9d9f-cf3094909b95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3504739770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.3504739770 |
| Directory | /workspace/286.edn_genbits/latest |
| Test location | /workspace/coverage/default/287.edn_genbits.3593689735 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 118742143 ps |
| CPU time | 2.88 seconds |
| Started | Jan 17 01:41:19 PM PST 24 |
| Finished | Jan 17 01:41:30 PM PST 24 |
| Peak memory | 214436 kb |
| Host | smart-a2563d35-4de1-497a-be97-6c2cac975582 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3593689735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3593689735 |
| Directory | /workspace/287.edn_genbits/latest |
| Test location | /workspace/coverage/default/288.edn_genbits.1265965651 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 28233248 ps |
| CPU time | 1.27 seconds |
| Started | Jan 17 01:41:17 PM PST 24 |
| Finished | Jan 17 01:41:20 PM PST 24 |
| Peak memory | 214184 kb |
| Host | smart-5e890e95-aec5-4649-a5e3-6d724c1ede87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1265965651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1265965651 |
| Directory | /workspace/288.edn_genbits/latest |
| Test location | /workspace/coverage/default/289.edn_genbits.475963047 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 32560824 ps |
| CPU time | 1.09 seconds |
| Started | Jan 17 01:41:17 PM PST 24 |
| Finished | Jan 17 01:41:20 PM PST 24 |
| Peak memory | 205484 kb |
| Host | smart-d0b8f52c-eead-41b8-8241-9f66e3906f74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=475963047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.475963047 |
| Directory | /workspace/289.edn_genbits/latest |
| Test location | /workspace/coverage/default/29.edn_alert.23673282 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 30517297 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:38:33 PM PST 24 |
| Finished | Jan 17 01:38:34 PM PST 24 |
| Peak memory | 205024 kb |
| Host | smart-34fac338-ce2b-492d-b67d-e6ecd5ec77f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=23673282 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.23673282 |
| Directory | /workspace/29.edn_alert/latest |
| Test location | /workspace/coverage/default/29.edn_alert_test.2075450955 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 29730545 ps |
| CPU time | 0.84 seconds |
| Started | Jan 17 01:38:22 PM PST 24 |
| Finished | Jan 17 01:38:24 PM PST 24 |
| Peak memory | 204256 kb |
| Host | smart-2b362d66-5a04-4404-b4f5-249d67d1be19 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075450955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2075450955 |
| Directory | /workspace/29.edn_alert_test/latest |
| Test location | /workspace/coverage/default/29.edn_disable.1715251281 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 14505291 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:38:25 PM PST 24 |
| Finished | Jan 17 01:38:31 PM PST 24 |
| Peak memory | 214472 kb |
| Host | smart-6b54763b-8e69-4a98-ada6-722c593cab37 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715251281 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1715251281 |
| Directory | /workspace/29.edn_disable/latest |
| Test location | /workspace/coverage/default/29.edn_disable_auto_req_mode.936662354 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 69341381 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:38:34 PM PST 24 |
| Finished | Jan 17 01:38:36 PM PST 24 |
| Peak memory | 206232 kb |
| Host | smart-f2af985c-f9b8-4559-9efa-71e40bf4bc99 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936662354 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di sable_auto_req_mode.936662354 |
| Directory | /workspace/29.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/29.edn_err.948095566 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 31329534 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:38:36 PM PST 24 |
| Finished | Jan 17 01:38:37 PM PST 24 |
| Peak memory | 215812 kb |
| Host | smart-a7ed46a2-3198-4899-976f-5541cc5eb87f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=948095566 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.948095566 |
| Directory | /workspace/29.edn_err/latest |
| Test location | /workspace/coverage/default/29.edn_genbits.1341861943 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 36012716 ps |
| CPU time | 1.45 seconds |
| Started | Jan 17 01:38:25 PM PST 24 |
| Finished | Jan 17 01:38:32 PM PST 24 |
| Peak memory | 214160 kb |
| Host | smart-0154a54d-10f8-496b-bc43-670bcb5fd3b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1341861943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1341861943 |
| Directory | /workspace/29.edn_genbits/latest |
| Test location | /workspace/coverage/default/29.edn_intr.4226889493 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 28566742 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:38:24 PM PST 24 |
| Finished | Jan 17 01:38:31 PM PST 24 |
| Peak memory | 214424 kb |
| Host | smart-1715d7ea-40d2-43f9-bb14-bfd1dc21e83b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4226889493 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.4226889493 |
| Directory | /workspace/29.edn_intr/latest |
| Test location | /workspace/coverage/default/29.edn_smoke.62758218 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 34922887 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 01:38:25 PM PST 24 |
| Finished | Jan 17 01:38:31 PM PST 24 |
| Peak memory | 204584 kb |
| Host | smart-f7076322-06b8-4449-9b4b-ba90c87776c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62758218 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.62758218 |
| Directory | /workspace/29.edn_smoke/latest |
| Test location | /workspace/coverage/default/29.edn_stress_all.1642519169 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 379165794 ps |
| CPU time | 3.01 seconds |
| Started | Jan 17 01:38:34 PM PST 24 |
| Finished | Jan 17 01:38:38 PM PST 24 |
| Peak memory | 205508 kb |
| Host | smart-c6add784-38f9-42ad-b2f1-50cf1cfdff69 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642519169 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1642519169 |
| Directory | /workspace/29.edn_stress_all/latest |
| Test location | /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1268861066 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 68320685064 ps |
| CPU time | 1562.36 seconds |
| Started | Jan 17 01:38:33 PM PST 24 |
| Finished | Jan 17 02:04:36 PM PST 24 |
| Peak memory | 221080 kb |
| Host | smart-cf815b49-74d0-46ec-8cc1-5475cb11565c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268861066 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1268861066 |
| Directory | /workspace/29.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/290.edn_genbits.1284640077 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 96772572 ps |
| CPU time | 1.32 seconds |
| Started | Jan 17 01:41:17 PM PST 24 |
| Finished | Jan 17 01:41:20 PM PST 24 |
| Peak memory | 205668 kb |
| Host | smart-e6eee6fd-2567-438b-b885-600524bcd34d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1284640077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1284640077 |
| Directory | /workspace/290.edn_genbits/latest |
| Test location | /workspace/coverage/default/291.edn_genbits.233260842 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 42024274 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 01:41:18 PM PST 24 |
| Finished | Jan 17 01:41:28 PM PST 24 |
| Peak memory | 214176 kb |
| Host | smart-e5c92c35-dfba-4ada-8378-95c222897f9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=233260842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.233260842 |
| Directory | /workspace/291.edn_genbits/latest |
| Test location | /workspace/coverage/default/292.edn_genbits.738836230 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 25764040 ps |
| CPU time | 1.31 seconds |
| Started | Jan 17 01:41:20 PM PST 24 |
| Finished | Jan 17 01:41:28 PM PST 24 |
| Peak memory | 214176 kb |
| Host | smart-3bda7037-8c06-434d-bdbe-eef5398b9b3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=738836230 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.738836230 |
| Directory | /workspace/292.edn_genbits/latest |
| Test location | /workspace/coverage/default/293.edn_genbits.756479744 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 29047931 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 01:41:16 PM PST 24 |
| Finished | Jan 17 01:41:19 PM PST 24 |
| Peak memory | 205632 kb |
| Host | smart-f3612606-7872-4986-a37a-a1d12f30e4a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=756479744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.756479744 |
| Directory | /workspace/293.edn_genbits/latest |
| Test location | /workspace/coverage/default/294.edn_genbits.902197771 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 27369575 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:41:18 PM PST 24 |
| Finished | Jan 17 01:41:27 PM PST 24 |
| Peak memory | 205660 kb |
| Host | smart-6be826af-2044-49a3-b8fa-15cd79f2864a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=902197771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.902197771 |
| Directory | /workspace/294.edn_genbits/latest |
| Test location | /workspace/coverage/default/295.edn_genbits.3813716547 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 72070106 ps |
| CPU time | 2.87 seconds |
| Started | Jan 17 01:41:19 PM PST 24 |
| Finished | Jan 17 01:41:30 PM PST 24 |
| Peak memory | 214160 kb |
| Host | smart-bfb89580-c6cf-410c-a2e8-4950a89f3b48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3813716547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3813716547 |
| Directory | /workspace/295.edn_genbits/latest |
| Test location | /workspace/coverage/default/296.edn_genbits.2936837094 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 56903423 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:41:25 PM PST 24 |
| Finished | Jan 17 01:41:28 PM PST 24 |
| Peak memory | 205388 kb |
| Host | smart-b87522db-45d0-4d5c-a1e4-03b2a5697221 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2936837094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2936837094 |
| Directory | /workspace/296.edn_genbits/latest |
| Test location | /workspace/coverage/default/297.edn_genbits.3276354563 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 372117129 ps |
| CPU time | 4.68 seconds |
| Started | Jan 17 01:41:28 PM PST 24 |
| Finished | Jan 17 01:41:34 PM PST 24 |
| Peak memory | 214172 kb |
| Host | smart-079c0421-fba8-4e65-aab7-77a52abeedae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3276354563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3276354563 |
| Directory | /workspace/297.edn_genbits/latest |
| Test location | /workspace/coverage/default/298.edn_genbits.3091160918 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 17456952 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:41:23 PM PST 24 |
| Finished | Jan 17 01:41:28 PM PST 24 |
| Peak memory | 205184 kb |
| Host | smart-099acd1e-5630-406f-a07d-328f3386b283 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091160918 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3091160918 |
| Directory | /workspace/298.edn_genbits/latest |
| Test location | /workspace/coverage/default/299.edn_genbits.1216264157 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 67287505 ps |
| CPU time | 1.14 seconds |
| Started | Jan 17 01:41:26 PM PST 24 |
| Finished | Jan 17 01:41:28 PM PST 24 |
| Peak memory | 214100 kb |
| Host | smart-0e32ea8b-b9d4-4657-be35-83fa6cc3e157 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1216264157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1216264157 |
| Directory | /workspace/299.edn_genbits/latest |
| Test location | /workspace/coverage/default/3.edn_alert.1335863845 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 27918371 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:36:04 PM PST 24 |
| Finished | Jan 17 01:36:05 PM PST 24 |
| Peak memory | 205792 kb |
| Host | smart-cc3e5546-0c44-48e9-9af9-716f16fae634 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1335863845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1335863845 |
| Directory | /workspace/3.edn_alert/latest |
| Test location | /workspace/coverage/default/3.edn_alert_test.2371488464 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 25607916 ps |
| CPU time | 0.9 seconds |
| Started | Jan 17 01:36:02 PM PST 24 |
| Finished | Jan 17 01:36:04 PM PST 24 |
| Peak memory | 204972 kb |
| Host | smart-b06b9478-b649-4944-8e98-cfcff32493a3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371488464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2371488464 |
| Directory | /workspace/3.edn_alert_test/latest |
| Test location | /workspace/coverage/default/3.edn_disable.1052439512 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 12434921 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 01:36:01 PM PST 24 |
| Finished | Jan 17 01:36:03 PM PST 24 |
| Peak memory | 214388 kb |
| Host | smart-10b258c6-ad3d-4078-9f47-cf1edecd73b7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052439512 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1052439512 |
| Directory | /workspace/3.edn_disable/latest |
| Test location | /workspace/coverage/default/3.edn_disable_auto_req_mode.3723663407 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 13617023 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 01:36:04 PM PST 24 |
| Finished | Jan 17 01:36:05 PM PST 24 |
| Peak memory | 214360 kb |
| Host | smart-878b6773-13a0-4a19-8548-f29dcf400b9e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723663407 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di sable_auto_req_mode.3723663407 |
| Directory | /workspace/3.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/3.edn_err.2105614862 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 30455005 ps |
| CPU time | 1.19 seconds |
| Started | Jan 17 01:36:00 PM PST 24 |
| Finished | Jan 17 01:36:02 PM PST 24 |
| Peak memory | 216680 kb |
| Host | smart-1ee5691a-becb-4872-a651-a325cf5aaa28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2105614862 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2105614862 |
| Directory | /workspace/3.edn_err/latest |
| Test location | /workspace/coverage/default/3.edn_genbits.2241500623 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 15762149 ps |
| CPU time | 1.02 seconds |
| Started | Jan 17 01:35:53 PM PST 24 |
| Finished | Jan 17 01:35:55 PM PST 24 |
| Peak memory | 205560 kb |
| Host | smart-ed4ac2b1-e12f-4804-96c4-75fa2c3fc45d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2241500623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2241500623 |
| Directory | /workspace/3.edn_genbits/latest |
| Test location | /workspace/coverage/default/3.edn_intr.3115791769 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 23604940 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:35:54 PM PST 24 |
| Finished | Jan 17 01:35:55 PM PST 24 |
| Peak memory | 214720 kb |
| Host | smart-550e7d6a-a505-43b4-bcd4-92f0bb79cbd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3115791769 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3115791769 |
| Directory | /workspace/3.edn_intr/latest |
| Test location | /workspace/coverage/default/3.edn_regwen.4224192548 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 44763489 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 01:35:52 PM PST 24 |
| Finished | Jan 17 01:35:53 PM PST 24 |
| Peak memory | 204856 kb |
| Host | smart-91b573c7-940c-47a8-9f12-1f20d3ff4374 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4224192548 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.4224192548 |
| Directory | /workspace/3.edn_regwen/latest |
| Test location | /workspace/coverage/default/3.edn_sec_cm.1404509890 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 370147721 ps |
| CPU time | 3.52 seconds |
| Started | Jan 17 01:36:00 PM PST 24 |
| Finished | Jan 17 01:36:04 PM PST 24 |
| Peak memory | 233316 kb |
| Host | smart-438fce62-4357-41bb-8f36-de89c332f439 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404509890 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1404509890 |
| Directory | /workspace/3.edn_sec_cm/latest |
| Test location | /workspace/coverage/default/3.edn_smoke.2522350187 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 13583535 ps |
| CPU time | 0.84 seconds |
| Started | Jan 17 01:35:59 PM PST 24 |
| Finished | Jan 17 01:36:01 PM PST 24 |
| Peak memory | 204804 kb |
| Host | smart-1b1237fe-a72f-499a-ac25-3ecdc8764122 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2522350187 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2522350187 |
| Directory | /workspace/3.edn_smoke/latest |
| Test location | /workspace/coverage/default/3.edn_stress_all.3313543324 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 249102001 ps |
| CPU time | 2.85 seconds |
| Started | Jan 17 01:35:52 PM PST 24 |
| Finished | Jan 17 01:35:56 PM PST 24 |
| Peak memory | 205572 kb |
| Host | smart-a6d1d1a3-7915-4952-9326-bee4c6932df1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313543324 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3313543324 |
| Directory | /workspace/3.edn_stress_all/latest |
| Test location | /workspace/coverage/default/3.edn_stress_all_with_rand_reset.2346606757 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 120236066035 ps |
| CPU time | 675.84 seconds |
| Started | Jan 17 01:35:59 PM PST 24 |
| Finished | Jan 17 01:47:15 PM PST 24 |
| Peak memory | 214840 kb |
| Host | smart-b124b23b-de41-4753-a1bb-59b9df32a66a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346606757 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.2346606757 |
| Directory | /workspace/3.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.edn_alert.578406009 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 22219191 ps |
| CPU time | 1.04 seconds |
| Started | Jan 17 01:38:33 PM PST 24 |
| Finished | Jan 17 01:38:35 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-c94deb94-803b-4483-bf8b-0988c3e1b7aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=578406009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.578406009 |
| Directory | /workspace/30.edn_alert/latest |
| Test location | /workspace/coverage/default/30.edn_alert_test.1400426399 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 17215270 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:38:31 PM PST 24 |
| Finished | Jan 17 01:38:32 PM PST 24 |
| Peak memory | 204788 kb |
| Host | smart-5dbdeb45-2711-4386-8cff-ea582189b14d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400426399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1400426399 |
| Directory | /workspace/30.edn_alert_test/latest |
| Test location | /workspace/coverage/default/30.edn_disable_auto_req_mode.3234925798 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 32970382 ps |
| CPU time | 1.12 seconds |
| Started | Jan 17 01:38:27 PM PST 24 |
| Finished | Jan 17 01:38:31 PM PST 24 |
| Peak memory | 214504 kb |
| Host | smart-4497e803-5bea-4fab-8e2f-e6be887198d3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234925798 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d isable_auto_req_mode.3234925798 |
| Directory | /workspace/30.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/30.edn_err.2559417494 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 22823954 ps |
| CPU time | 1.1 seconds |
| Started | Jan 17 01:38:21 PM PST 24 |
| Finished | Jan 17 01:38:24 PM PST 24 |
| Peak memory | 216148 kb |
| Host | smart-085376ad-6736-4784-878f-1eaacc81ddb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2559417494 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.2559417494 |
| Directory | /workspace/30.edn_err/latest |
| Test location | /workspace/coverage/default/30.edn_genbits.1220669766 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 82393204 ps |
| CPU time | 1.06 seconds |
| Started | Jan 17 01:38:34 PM PST 24 |
| Finished | Jan 17 01:38:36 PM PST 24 |
| Peak memory | 205484 kb |
| Host | smart-ad98bce6-ffbf-460b-b65d-b94d9c4ee6dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1220669766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1220669766 |
| Directory | /workspace/30.edn_genbits/latest |
| Test location | /workspace/coverage/default/30.edn_intr.3172483548 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 32041868 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:38:31 PM PST 24 |
| Finished | Jan 17 01:38:33 PM PST 24 |
| Peak memory | 214612 kb |
| Host | smart-c3e5bc3f-b143-4cfc-b0a3-77f9ba5b712e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172483548 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3172483548 |
| Directory | /workspace/30.edn_intr/latest |
| Test location | /workspace/coverage/default/30.edn_smoke.3874760508 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 17910940 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 01:38:34 PM PST 24 |
| Finished | Jan 17 01:38:35 PM PST 24 |
| Peak memory | 204748 kb |
| Host | smart-8aff8629-2d44-4679-b010-55c2f76c2477 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3874760508 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3874760508 |
| Directory | /workspace/30.edn_smoke/latest |
| Test location | /workspace/coverage/default/30.edn_stress_all.2301475082 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 318017844 ps |
| CPU time | 2.9 seconds |
| Started | Jan 17 01:38:37 PM PST 24 |
| Finished | Jan 17 01:38:40 PM PST 24 |
| Peak memory | 205996 kb |
| Host | smart-0e76f78c-e4ac-4bfa-bd22-6d2eb3110812 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301475082 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.2301475082 |
| Directory | /workspace/30.edn_stress_all/latest |
| Test location | /workspace/coverage/default/30.edn_stress_all_with_rand_reset.2752725128 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 110559860799 ps |
| CPU time | 1637.26 seconds |
| Started | Jan 17 01:38:36 PM PST 24 |
| Finished | Jan 17 02:05:54 PM PST 24 |
| Peak memory | 221452 kb |
| Host | smart-7107c95b-babc-457e-9434-a1babcd78807 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752725128 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.2752725128 |
| Directory | /workspace/30.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.edn_alert.1396818367 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 176221064 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:38:38 PM PST 24 |
| Finished | Jan 17 01:38:41 PM PST 24 |
| Peak memory | 205944 kb |
| Host | smart-00770482-bc6b-4901-a184-fd0e42d78395 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1396818367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1396818367 |
| Directory | /workspace/31.edn_alert/latest |
| Test location | /workspace/coverage/default/31.edn_alert_test.539482522 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 32000152 ps |
| CPU time | 0.79 seconds |
| Started | Jan 17 01:38:32 PM PST 24 |
| Finished | Jan 17 01:38:34 PM PST 24 |
| Peak memory | 204208 kb |
| Host | smart-557a8ba4-c871-420a-a29b-582931ff7365 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539482522 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.539482522 |
| Directory | /workspace/31.edn_alert_test/latest |
| Test location | /workspace/coverage/default/31.edn_disable_auto_req_mode.679054851 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 53810188 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 01:38:37 PM PST 24 |
| Finished | Jan 17 01:38:39 PM PST 24 |
| Peak memory | 214480 kb |
| Host | smart-64da5f75-a6b9-45d1-b8da-a90f21697573 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679054851 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di sable_auto_req_mode.679054851 |
| Directory | /workspace/31.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/31.edn_err.381254148 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 18922783 ps |
| CPU time | 1.16 seconds |
| Started | Jan 17 01:38:34 PM PST 24 |
| Finished | Jan 17 01:38:36 PM PST 24 |
| Peak memory | 221864 kb |
| Host | smart-a73eb8ef-5def-49c8-b792-6d656ff9051e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=381254148 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.381254148 |
| Directory | /workspace/31.edn_err/latest |
| Test location | /workspace/coverage/default/31.edn_genbits.656614681 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 46589503 ps |
| CPU time | 1.91 seconds |
| Started | Jan 17 01:38:35 PM PST 24 |
| Finished | Jan 17 01:38:37 PM PST 24 |
| Peak memory | 214176 kb |
| Host | smart-cc307dd9-61a2-4355-9a3e-6f1652fe4851 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=656614681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.656614681 |
| Directory | /workspace/31.edn_genbits/latest |
| Test location | /workspace/coverage/default/31.edn_intr.967198551 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 19892641 ps |
| CPU time | 1.02 seconds |
| Started | Jan 17 01:38:36 PM PST 24 |
| Finished | Jan 17 01:38:38 PM PST 24 |
| Peak memory | 214324 kb |
| Host | smart-d25d4685-aaa6-4ef4-9be0-81f47f0b38dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=967198551 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.967198551 |
| Directory | /workspace/31.edn_intr/latest |
| Test location | /workspace/coverage/default/31.edn_smoke.3968146207 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 18875273 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:38:34 PM PST 24 |
| Finished | Jan 17 01:38:36 PM PST 24 |
| Peak memory | 204916 kb |
| Host | smart-740aa834-da24-4115-9308-950387cbb2f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968146207 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.3968146207 |
| Directory | /workspace/31.edn_smoke/latest |
| Test location | /workspace/coverage/default/31.edn_stress_all.929407187 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 189988934 ps |
| CPU time | 2.23 seconds |
| Started | Jan 17 01:38:33 PM PST 24 |
| Finished | Jan 17 01:38:35 PM PST 24 |
| Peak memory | 205544 kb |
| Host | smart-b96f574d-08f5-4ed4-9373-20c391f71289 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929407187 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.929407187 |
| Directory | /workspace/31.edn_stress_all/latest |
| Test location | /workspace/coverage/default/31.edn_stress_all_with_rand_reset.348849849 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 158039809950 ps |
| CPU time | 560.29 seconds |
| Started | Jan 17 01:38:34 PM PST 24 |
| Finished | Jan 17 01:47:55 PM PST 24 |
| Peak memory | 215996 kb |
| Host | smart-69bf80bb-8c6e-4cda-b7ec-ae421a223471 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348849849 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.348849849 |
| Directory | /workspace/31.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.edn_alert.2630362990 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 58595973 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:38:35 PM PST 24 |
| Finished | Jan 17 01:38:36 PM PST 24 |
| Peak memory | 206036 kb |
| Host | smart-2e48a772-cad5-4736-8bbc-b4978e22f00c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2630362990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2630362990 |
| Directory | /workspace/32.edn_alert/latest |
| Test location | /workspace/coverage/default/32.edn_alert_test.3794716769 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 55529709 ps |
| CPU time | 1.12 seconds |
| Started | Jan 17 01:38:36 PM PST 24 |
| Finished | Jan 17 01:38:38 PM PST 24 |
| Peak memory | 204604 kb |
| Host | smart-569af9c0-a153-4753-a466-2d949adbce00 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794716769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3794716769 |
| Directory | /workspace/32.edn_alert_test/latest |
| Test location | /workspace/coverage/default/32.edn_disable.2915448643 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 14906639 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:38:43 PM PST 24 |
| Finished | Jan 17 01:38:45 PM PST 24 |
| Peak memory | 214424 kb |
| Host | smart-4c2d4d32-81bc-4b95-9c1e-6adb8b089b25 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915448643 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2915448643 |
| Directory | /workspace/32.edn_disable/latest |
| Test location | /workspace/coverage/default/32.edn_disable_auto_req_mode.2644997059 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 126755450 ps |
| CPU time | 1.21 seconds |
| Started | Jan 17 01:38:35 PM PST 24 |
| Finished | Jan 17 01:38:37 PM PST 24 |
| Peak memory | 214692 kb |
| Host | smart-8d4bff28-8933-4eaf-8a2f-e969cb4ee194 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644997059 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d isable_auto_req_mode.2644997059 |
| Directory | /workspace/32.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/32.edn_err.2846384781 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 28342716 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:38:37 PM PST 24 |
| Finished | Jan 17 01:38:39 PM PST 24 |
| Peak memory | 221460 kb |
| Host | smart-aa882da2-1d9c-43b7-8f12-ea6ca14afa23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2846384781 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2846384781 |
| Directory | /workspace/32.edn_err/latest |
| Test location | /workspace/coverage/default/32.edn_genbits.2869970840 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 58237885 ps |
| CPU time | 1.09 seconds |
| Started | Jan 17 01:38:38 PM PST 24 |
| Finished | Jan 17 01:38:41 PM PST 24 |
| Peak memory | 205476 kb |
| Host | smart-dd16d767-f1e6-4501-9341-671ab8b3b8f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2869970840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2869970840 |
| Directory | /workspace/32.edn_genbits/latest |
| Test location | /workspace/coverage/default/32.edn_intr.3629726468 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 19691408 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 01:38:32 PM PST 24 |
| Finished | Jan 17 01:38:34 PM PST 24 |
| Peak memory | 214556 kb |
| Host | smart-e3cc746e-3448-4fa1-94ec-bab889e1f950 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3629726468 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3629726468 |
| Directory | /workspace/32.edn_intr/latest |
| Test location | /workspace/coverage/default/32.edn_smoke.4288469507 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 27404964 ps |
| CPU time | 0.84 seconds |
| Started | Jan 17 01:38:32 PM PST 24 |
| Finished | Jan 17 01:38:33 PM PST 24 |
| Peak memory | 204684 kb |
| Host | smart-ef1291f3-c26c-4f78-94e9-38aac5bb18a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4288469507 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.4288469507 |
| Directory | /workspace/32.edn_smoke/latest |
| Test location | /workspace/coverage/default/32.edn_stress_all.210804030 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 342614017 ps |
| CPU time | 4.25 seconds |
| Started | Jan 17 01:38:37 PM PST 24 |
| Finished | Jan 17 01:38:43 PM PST 24 |
| Peak memory | 206012 kb |
| Host | smart-1a8cc919-dce1-4231-b1da-a58a57c4a69a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210804030 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.210804030 |
| Directory | /workspace/32.edn_stress_all/latest |
| Test location | /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1517519451 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 84976157235 ps |
| CPU time | 926.65 seconds |
| Started | Jan 17 01:38:37 PM PST 24 |
| Finished | Jan 17 01:54:05 PM PST 24 |
| Peak memory | 215476 kb |
| Host | smart-0747cdb3-2208-4a43-8d24-b308e74cb999 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517519451 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1517519451 |
| Directory | /workspace/32.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.edn_alert.1571342929 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 65407210 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:38:44 PM PST 24 |
| Finished | Jan 17 01:38:46 PM PST 24 |
| Peak memory | 205048 kb |
| Host | smart-721cfda6-3aae-4039-bee0-2a6813d62cb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1571342929 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1571342929 |
| Directory | /workspace/33.edn_alert/latest |
| Test location | /workspace/coverage/default/33.edn_alert_test.2352854533 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 50356231 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:38:43 PM PST 24 |
| Finished | Jan 17 01:38:45 PM PST 24 |
| Peak memory | 205124 kb |
| Host | smart-c11d5b82-1831-4bbb-973d-8c8172bb1dda |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352854533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2352854533 |
| Directory | /workspace/33.edn_alert_test/latest |
| Test location | /workspace/coverage/default/33.edn_disable.4025592532 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 37479158 ps |
| CPU time | 0.8 seconds |
| Started | Jan 17 01:38:43 PM PST 24 |
| Finished | Jan 17 01:38:45 PM PST 24 |
| Peak memory | 214384 kb |
| Host | smart-2bf2e373-9936-4163-9640-0d64a5ae5404 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025592532 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.4025592532 |
| Directory | /workspace/33.edn_disable/latest |
| Test location | /workspace/coverage/default/33.edn_disable_auto_req_mode.1974340129 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 122020411 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:38:41 PM PST 24 |
| Finished | Jan 17 01:38:44 PM PST 24 |
| Peak memory | 214444 kb |
| Host | smart-4f1d5eeb-247e-44fc-93c0-f4e48853d8ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974340129 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d isable_auto_req_mode.1974340129 |
| Directory | /workspace/33.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/33.edn_err.2956605721 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 22644315 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:38:42 PM PST 24 |
| Finished | Jan 17 01:38:45 PM PST 24 |
| Peak memory | 216244 kb |
| Host | smart-f4702867-94ab-47f8-91f8-d326d73a53b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2956605721 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2956605721 |
| Directory | /workspace/33.edn_err/latest |
| Test location | /workspace/coverage/default/33.edn_intr.3553384352 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 19499923 ps |
| CPU time | 1.05 seconds |
| Started | Jan 17 01:38:49 PM PST 24 |
| Finished | Jan 17 01:38:51 PM PST 24 |
| Peak memory | 214408 kb |
| Host | smart-b73f7d47-aa6f-4026-b8cd-477e7c355b7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3553384352 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3553384352 |
| Directory | /workspace/33.edn_intr/latest |
| Test location | /workspace/coverage/default/33.edn_smoke.240405416 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 53326309 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 01:38:34 PM PST 24 |
| Finished | Jan 17 01:38:36 PM PST 24 |
| Peak memory | 204600 kb |
| Host | smart-94e57787-1f52-486a-a378-9a4b1f6b37c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240405416 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.240405416 |
| Directory | /workspace/33.edn_smoke/latest |
| Test location | /workspace/coverage/default/33.edn_stress_all.2829852497 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 328359503 ps |
| CPU time | 2.17 seconds |
| Started | Jan 17 01:38:35 PM PST 24 |
| Finished | Jan 17 01:38:38 PM PST 24 |
| Peak memory | 205944 kb |
| Host | smart-5b83ac02-9809-4d4b-98e1-2a1b4e0678ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829852497 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2829852497 |
| Directory | /workspace/33.edn_stress_all/latest |
| Test location | /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1263319512 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 378811566874 ps |
| CPU time | 716.21 seconds |
| Started | Jan 17 01:38:44 PM PST 24 |
| Finished | Jan 17 01:50:41 PM PST 24 |
| Peak memory | 220324 kb |
| Host | smart-84ea403b-8a09-4efc-a830-4d9080f7b083 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263319512 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1263319512 |
| Directory | /workspace/33.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.edn_alert_test.3560621388 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 37790250 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 01:38:44 PM PST 24 |
| Finished | Jan 17 01:38:46 PM PST 24 |
| Peak memory | 205084 kb |
| Host | smart-bd1f78a5-e6c0-4696-8dea-5aaf56f90f9a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560621388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3560621388 |
| Directory | /workspace/34.edn_alert_test/latest |
| Test location | /workspace/coverage/default/34.edn_disable.3910464359 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 24519998 ps |
| CPU time | 0.84 seconds |
| Started | Jan 17 01:38:44 PM PST 24 |
| Finished | Jan 17 01:38:46 PM PST 24 |
| Peak memory | 214356 kb |
| Host | smart-43f916b0-532a-4bc7-a963-3c384f6bbab0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910464359 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3910464359 |
| Directory | /workspace/34.edn_disable/latest |
| Test location | /workspace/coverage/default/34.edn_disable_auto_req_mode.1233558064 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 51734679 ps |
| CPU time | 1.05 seconds |
| Started | Jan 17 01:38:48 PM PST 24 |
| Finished | Jan 17 01:38:49 PM PST 24 |
| Peak memory | 214416 kb |
| Host | smart-481aec63-092c-4555-b94f-cd147fbfd41b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233558064 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d isable_auto_req_mode.1233558064 |
| Directory | /workspace/34.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/34.edn_err.1340237791 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 35625138 ps |
| CPU time | 0.79 seconds |
| Started | Jan 17 01:38:43 PM PST 24 |
| Finished | Jan 17 01:38:45 PM PST 24 |
| Peak memory | 215280 kb |
| Host | smart-ff3a992c-c9a6-4396-9541-c6422cbc6cb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1340237791 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.1340237791 |
| Directory | /workspace/34.edn_err/latest |
| Test location | /workspace/coverage/default/34.edn_genbits.1097593216 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 59659194 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:38:42 PM PST 24 |
| Finished | Jan 17 01:38:45 PM PST 24 |
| Peak memory | 204884 kb |
| Host | smart-a0aaba80-399f-4dfb-8a86-1759c423d95d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1097593216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1097593216 |
| Directory | /workspace/34.edn_genbits/latest |
| Test location | /workspace/coverage/default/34.edn_intr.1500205275 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 18473520 ps |
| CPU time | 1.05 seconds |
| Started | Jan 17 01:38:44 PM PST 24 |
| Finished | Jan 17 01:38:46 PM PST 24 |
| Peak memory | 214512 kb |
| Host | smart-a4968afe-f4f1-4382-aec3-f63e4a4c61dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1500205275 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1500205275 |
| Directory | /workspace/34.edn_intr/latest |
| Test location | /workspace/coverage/default/34.edn_smoke.3686915515 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 140556492 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:38:43 PM PST 24 |
| Finished | Jan 17 01:38:45 PM PST 24 |
| Peak memory | 204584 kb |
| Host | smart-7a8c9693-67b9-49aa-824f-cf26895effba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3686915515 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3686915515 |
| Directory | /workspace/34.edn_smoke/latest |
| Test location | /workspace/coverage/default/34.edn_stress_all.3271145118 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 139845520 ps |
| CPU time | 3.43 seconds |
| Started | Jan 17 01:38:41 PM PST 24 |
| Finished | Jan 17 01:38:47 PM PST 24 |
| Peak memory | 205696 kb |
| Host | smart-80ea0318-7298-43f9-a68a-120eee5cadd2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271145118 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3271145118 |
| Directory | /workspace/34.edn_stress_all/latest |
| Test location | /workspace/coverage/default/35.edn_alert.2492926591 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 17680067 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:38:50 PM PST 24 |
| Finished | Jan 17 01:38:51 PM PST 24 |
| Peak memory | 205180 kb |
| Host | smart-dc693c81-8688-44fa-8886-ea1d8ef62962 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2492926591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.2492926591 |
| Directory | /workspace/35.edn_alert/latest |
| Test location | /workspace/coverage/default/35.edn_alert_test.2058250552 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 18430758 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:38:49 PM PST 24 |
| Finished | Jan 17 01:38:50 PM PST 24 |
| Peak memory | 204540 kb |
| Host | smart-7ba12d8c-ae4e-41fd-8ed0-efa8ae4687d9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058250552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2058250552 |
| Directory | /workspace/35.edn_alert_test/latest |
| Test location | /workspace/coverage/default/35.edn_disable.2337719894 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 38135308 ps |
| CPU time | 0.84 seconds |
| Started | Jan 17 01:38:50 PM PST 24 |
| Finished | Jan 17 01:38:51 PM PST 24 |
| Peak memory | 214320 kb |
| Host | smart-d202f32d-1197-4ca6-b1e8-2d87329328a6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337719894 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2337719894 |
| Directory | /workspace/35.edn_disable/latest |
| Test location | /workspace/coverage/default/35.edn_disable_auto_req_mode.2810653491 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 15384633 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 01:38:50 PM PST 24 |
| Finished | Jan 17 01:38:52 PM PST 24 |
| Peak memory | 214452 kb |
| Host | smart-05e600ac-19b3-4a27-9936-d4423b48fc79 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810653491 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d isable_auto_req_mode.2810653491 |
| Directory | /workspace/35.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/35.edn_err.1833863733 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 32518504 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:38:51 PM PST 24 |
| Finished | Jan 17 01:38:52 PM PST 24 |
| Peak memory | 215884 kb |
| Host | smart-bc8853a0-2555-491b-8396-76f7be1642bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1833863733 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1833863733 |
| Directory | /workspace/35.edn_err/latest |
| Test location | /workspace/coverage/default/35.edn_genbits.2340606333 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 31391224 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 01:38:49 PM PST 24 |
| Finished | Jan 17 01:38:51 PM PST 24 |
| Peak memory | 214152 kb |
| Host | smart-2b674bb5-2c26-4716-abb9-0eeb16cf3d88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2340606333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.2340606333 |
| Directory | /workspace/35.edn_genbits/latest |
| Test location | /workspace/coverage/default/35.edn_intr.1578026328 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 24820353 ps |
| CPU time | 1.02 seconds |
| Started | Jan 17 01:38:46 PM PST 24 |
| Finished | Jan 17 01:38:48 PM PST 24 |
| Peak memory | 222016 kb |
| Host | smart-2dfa3767-0677-4679-a5c3-076c8db62c31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1578026328 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1578026328 |
| Directory | /workspace/35.edn_intr/latest |
| Test location | /workspace/coverage/default/35.edn_smoke.3663502195 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 35166075 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:38:41 PM PST 24 |
| Finished | Jan 17 01:38:44 PM PST 24 |
| Peak memory | 204552 kb |
| Host | smart-d865d79d-0081-48f3-83c3-27decb7aee8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3663502195 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3663502195 |
| Directory | /workspace/35.edn_smoke/latest |
| Test location | /workspace/coverage/default/35.edn_stress_all.3353371242 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 250754141 ps |
| CPU time | 4.28 seconds |
| Started | Jan 17 01:38:44 PM PST 24 |
| Finished | Jan 17 01:38:50 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-f401e882-ddc6-471c-85ff-51609b16c789 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353371242 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.3353371242 |
| Directory | /workspace/35.edn_stress_all/latest |
| Test location | /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3114986570 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 102443406182 ps |
| CPU time | 178.84 seconds |
| Started | Jan 17 01:38:52 PM PST 24 |
| Finished | Jan 17 01:41:52 PM PST 24 |
| Peak memory | 215736 kb |
| Host | smart-929ac4f9-71f9-4f48-bdb0-9bedcadfb4f0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114986570 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3114986570 |
| Directory | /workspace/35.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.edn_alert.3077996993 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 47413026 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:38:50 PM PST 24 |
| Finished | Jan 17 01:38:52 PM PST 24 |
| Peak memory | 205964 kb |
| Host | smart-5a3b6c29-f3b4-4b3d-b7cd-fd8a9ef25c74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3077996993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3077996993 |
| Directory | /workspace/36.edn_alert/latest |
| Test location | /workspace/coverage/default/36.edn_alert_test.594479403 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 76164269 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 01:38:49 PM PST 24 |
| Finished | Jan 17 01:38:51 PM PST 24 |
| Peak memory | 204556 kb |
| Host | smart-0321cfa4-4c3f-4f67-934c-ce714ff4de17 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594479403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.594479403 |
| Directory | /workspace/36.edn_alert_test/latest |
| Test location | /workspace/coverage/default/36.edn_disable.1202537203 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 19811414 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:38:48 PM PST 24 |
| Finished | Jan 17 01:38:49 PM PST 24 |
| Peak memory | 214396 kb |
| Host | smart-41c806b0-4a1d-4fa0-96ff-2d784241ac7a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202537203 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1202537203 |
| Directory | /workspace/36.edn_disable/latest |
| Test location | /workspace/coverage/default/36.edn_disable_auto_req_mode.1070996698 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 199749218 ps |
| CPU time | 1.06 seconds |
| Started | Jan 17 01:38:48 PM PST 24 |
| Finished | Jan 17 01:38:49 PM PST 24 |
| Peak memory | 214468 kb |
| Host | smart-b174a652-c974-4139-8fe7-8e9f6a1e5502 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070996698 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d isable_auto_req_mode.1070996698 |
| Directory | /workspace/36.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/36.edn_err.1172076226 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 88785397 ps |
| CPU time | 1.1 seconds |
| Started | Jan 17 01:38:44 PM PST 24 |
| Finished | Jan 17 01:38:46 PM PST 24 |
| Peak memory | 216788 kb |
| Host | smart-1d31cc38-dc63-4c53-a0c8-662dc89e2934 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1172076226 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1172076226 |
| Directory | /workspace/36.edn_err/latest |
| Test location | /workspace/coverage/default/36.edn_genbits.2848770928 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 49393935 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:38:48 PM PST 24 |
| Finished | Jan 17 01:38:49 PM PST 24 |
| Peak memory | 205164 kb |
| Host | smart-6db06f43-3911-455c-b028-0fcd2f19f6c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2848770928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2848770928 |
| Directory | /workspace/36.edn_genbits/latest |
| Test location | /workspace/coverage/default/36.edn_smoke.2765721310 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 20397130 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 01:38:51 PM PST 24 |
| Finished | Jan 17 01:38:52 PM PST 24 |
| Peak memory | 204944 kb |
| Host | smart-35f8ca6a-aaa9-4992-9d95-8168d2b25aca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2765721310 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2765721310 |
| Directory | /workspace/36.edn_smoke/latest |
| Test location | /workspace/coverage/default/36.edn_stress_all.1940362861 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 366793792 ps |
| CPU time | 2.23 seconds |
| Started | Jan 17 01:38:47 PM PST 24 |
| Finished | Jan 17 01:38:50 PM PST 24 |
| Peak memory | 205896 kb |
| Host | smart-ff96ceaa-62f5-4863-a8fc-099f0d8e267d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940362861 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1940362861 |
| Directory | /workspace/36.edn_stress_all/latest |
| Test location | /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3673116116 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 25833133506 ps |
| CPU time | 605.72 seconds |
| Started | Jan 17 01:38:50 PM PST 24 |
| Finished | Jan 17 01:48:57 PM PST 24 |
| Peak memory | 214548 kb |
| Host | smart-2c781b17-e3d4-4dc8-8f35-b2d354e98b34 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673116116 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3673116116 |
| Directory | /workspace/36.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.edn_alert.32795302 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 18651624 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:38:56 PM PST 24 |
| Finished | Jan 17 01:38:59 PM PST 24 |
| Peak memory | 205864 kb |
| Host | smart-a12b1ff0-021f-4324-9eec-69ff5aeccd6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32795302 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.32795302 |
| Directory | /workspace/37.edn_alert/latest |
| Test location | /workspace/coverage/default/37.edn_alert_test.708305382 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 28918747 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 01:38:54 PM PST 24 |
| Finished | Jan 17 01:38:55 PM PST 24 |
| Peak memory | 204480 kb |
| Host | smart-a15e9fab-2897-46a1-9c54-e7ffebb6aa41 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708305382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.708305382 |
| Directory | /workspace/37.edn_alert_test/latest |
| Test location | /workspace/coverage/default/37.edn_disable.81318059 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 23532178 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 01:38:57 PM PST 24 |
| Finished | Jan 17 01:39:00 PM PST 24 |
| Peak memory | 214328 kb |
| Host | smart-ee4ce3e6-1eea-44fb-aeaa-114d45a4f2ef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81318059 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.81318059 |
| Directory | /workspace/37.edn_disable/latest |
| Test location | /workspace/coverage/default/37.edn_disable_auto_req_mode.3351263688 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 25053868 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 01:38:53 PM PST 24 |
| Finished | Jan 17 01:38:55 PM PST 24 |
| Peak memory | 214468 kb |
| Host | smart-ad9f0575-0c3d-45ce-a0ed-f394dd4eb6c7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351263688 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d isable_auto_req_mode.3351263688 |
| Directory | /workspace/37.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/37.edn_err.319488254 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 47608392 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:38:55 PM PST 24 |
| Finished | Jan 17 01:38:59 PM PST 24 |
| Peak memory | 215644 kb |
| Host | smart-61ff047f-4e97-4349-b0d5-dae91b8f18a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=319488254 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.319488254 |
| Directory | /workspace/37.edn_err/latest |
| Test location | /workspace/coverage/default/37.edn_genbits.2147288124 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 48129082 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:38:54 PM PST 24 |
| Finished | Jan 17 01:38:56 PM PST 24 |
| Peak memory | 205048 kb |
| Host | smart-15f2c176-0b3e-4f24-9e81-4127bdbac876 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2147288124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2147288124 |
| Directory | /workspace/37.edn_genbits/latest |
| Test location | /workspace/coverage/default/37.edn_intr.4173961607 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 19186403 ps |
| CPU time | 1.07 seconds |
| Started | Jan 17 01:38:58 PM PST 24 |
| Finished | Jan 17 01:39:01 PM PST 24 |
| Peak memory | 214448 kb |
| Host | smart-165900e8-b8f2-4bb1-a127-8f92cebd938c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4173961607 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.4173961607 |
| Directory | /workspace/37.edn_intr/latest |
| Test location | /workspace/coverage/default/37.edn_smoke.3869981111 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 20855053 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 01:38:47 PM PST 24 |
| Finished | Jan 17 01:38:48 PM PST 24 |
| Peak memory | 204780 kb |
| Host | smart-18af9c76-fa2d-462c-888f-ddaf94b88f48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3869981111 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3869981111 |
| Directory | /workspace/37.edn_smoke/latest |
| Test location | /workspace/coverage/default/37.edn_stress_all.3783461950 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 234882733 ps |
| CPU time | 3.09 seconds |
| Started | Jan 17 01:38:51 PM PST 24 |
| Finished | Jan 17 01:38:55 PM PST 24 |
| Peak memory | 205776 kb |
| Host | smart-016f342f-04f4-48a5-861e-6eaf789e9c77 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783461950 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3783461950 |
| Directory | /workspace/37.edn_stress_all/latest |
| Test location | /workspace/coverage/default/37.edn_stress_all_with_rand_reset.329819732 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 204698829166 ps |
| CPU time | 1780.52 seconds |
| Started | Jan 17 01:38:54 PM PST 24 |
| Finished | Jan 17 02:08:35 PM PST 24 |
| Peak memory | 219680 kb |
| Host | smart-19913359-1795-4221-a352-99f50eb442ab |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329819732 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.329819732 |
| Directory | /workspace/37.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.edn_alert.3550857538 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 21110973 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 01:38:55 PM PST 24 |
| Finished | Jan 17 01:38:57 PM PST 24 |
| Peak memory | 205992 kb |
| Host | smart-fc090a1c-4538-4dc3-a051-3c7f38922884 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550857538 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3550857538 |
| Directory | /workspace/38.edn_alert/latest |
| Test location | /workspace/coverage/default/38.edn_alert_test.587143304 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 21941912 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:38:53 PM PST 24 |
| Finished | Jan 17 01:38:55 PM PST 24 |
| Peak memory | 204496 kb |
| Host | smart-c0ca1e35-c628-4d4e-b6ba-53d8aee222ab |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587143304 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.587143304 |
| Directory | /workspace/38.edn_alert_test/latest |
| Test location | /workspace/coverage/default/38.edn_disable.3527272651 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 16625433 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 01:38:53 PM PST 24 |
| Finished | Jan 17 01:38:54 PM PST 24 |
| Peak memory | 214324 kb |
| Host | smart-6cbd3fcb-12f8-4f77-8e44-b8337aa5a00a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527272651 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3527272651 |
| Directory | /workspace/38.edn_disable/latest |
| Test location | /workspace/coverage/default/38.edn_disable_auto_req_mode.2739929864 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 20696599 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:38:57 PM PST 24 |
| Finished | Jan 17 01:39:00 PM PST 24 |
| Peak memory | 214420 kb |
| Host | smart-b9d9b6fc-c458-4bc3-bb3b-2c2746cc57b7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739929864 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d isable_auto_req_mode.2739929864 |
| Directory | /workspace/38.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/38.edn_err.4013777687 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 34764454 ps |
| CPU time | 1.17 seconds |
| Started | Jan 17 01:38:55 PM PST 24 |
| Finished | Jan 17 01:38:58 PM PST 24 |
| Peak memory | 221900 kb |
| Host | smart-79edc8f9-69a2-4927-bc98-3b33a641af41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4013777687 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.4013777687 |
| Directory | /workspace/38.edn_err/latest |
| Test location | /workspace/coverage/default/38.edn_genbits.2480151769 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 2265363070 ps |
| CPU time | 71.03 seconds |
| Started | Jan 17 01:38:54 PM PST 24 |
| Finished | Jan 17 01:40:06 PM PST 24 |
| Peak memory | 214232 kb |
| Host | smart-af1dc2be-8a27-488d-885b-36e721c81945 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2480151769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2480151769 |
| Directory | /workspace/38.edn_genbits/latest |
| Test location | /workspace/coverage/default/38.edn_intr.374922933 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 41009972 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:38:55 PM PST 24 |
| Finished | Jan 17 01:38:58 PM PST 24 |
| Peak memory | 214296 kb |
| Host | smart-57bfe0d2-f72d-4a63-a01f-73954e26470d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=374922933 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.374922933 |
| Directory | /workspace/38.edn_intr/latest |
| Test location | /workspace/coverage/default/38.edn_smoke.1674071866 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 21066842 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 01:38:55 PM PST 24 |
| Finished | Jan 17 01:38:58 PM PST 24 |
| Peak memory | 204596 kb |
| Host | smart-acc754ce-e8b6-479a-9206-70d93dd18396 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1674071866 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1674071866 |
| Directory | /workspace/38.edn_smoke/latest |
| Test location | /workspace/coverage/default/38.edn_stress_all.1306506731 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 123771433 ps |
| CPU time | 2.62 seconds |
| Started | Jan 17 01:38:56 PM PST 24 |
| Finished | Jan 17 01:39:01 PM PST 24 |
| Peak memory | 205892 kb |
| Host | smart-da0c9676-7ebc-471a-88b6-d41752c6b61a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306506731 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1306506731 |
| Directory | /workspace/38.edn_stress_all/latest |
| Test location | /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1278043458 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 378242449548 ps |
| CPU time | 1995.56 seconds |
| Started | Jan 17 01:38:54 PM PST 24 |
| Finished | Jan 17 02:12:10 PM PST 24 |
| Peak memory | 220356 kb |
| Host | smart-2745211f-646d-4339-a5db-284ac304004b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278043458 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1278043458 |
| Directory | /workspace/38.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.edn_alert.3696375320 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 35051739 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:38:58 PM PST 24 |
| Finished | Jan 17 01:39:01 PM PST 24 |
| Peak memory | 205072 kb |
| Host | smart-af69eaee-8884-4e86-9faf-1bcdf7f8e85c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3696375320 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3696375320 |
| Directory | /workspace/39.edn_alert/latest |
| Test location | /workspace/coverage/default/39.edn_alert_test.3211521305 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 16946075 ps |
| CPU time | 0.81 seconds |
| Started | Jan 17 01:39:07 PM PST 24 |
| Finished | Jan 17 01:39:09 PM PST 24 |
| Peak memory | 204540 kb |
| Host | smart-551fd10b-0fcd-49b5-9013-31fc371429c5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211521305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3211521305 |
| Directory | /workspace/39.edn_alert_test/latest |
| Test location | /workspace/coverage/default/39.edn_disable_auto_req_mode.1685484570 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 26649200 ps |
| CPU time | 1.12 seconds |
| Started | Jan 17 01:39:12 PM PST 24 |
| Finished | Jan 17 01:39:14 PM PST 24 |
| Peak memory | 214452 kb |
| Host | smart-f513da17-e4ab-4ffb-a7db-705b456aebc2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685484570 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d isable_auto_req_mode.1685484570 |
| Directory | /workspace/39.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/39.edn_err.3891733807 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 33640786 ps |
| CPU time | 1.35 seconds |
| Started | Jan 17 01:38:55 PM PST 24 |
| Finished | Jan 17 01:38:58 PM PST 24 |
| Peak memory | 217404 kb |
| Host | smart-ef55d1ae-dbf1-483b-a6c4-b24b1a39fb06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3891733807 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3891733807 |
| Directory | /workspace/39.edn_err/latest |
| Test location | /workspace/coverage/default/39.edn_genbits.3418643559 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 34231018 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:38:53 PM PST 24 |
| Finished | Jan 17 01:38:55 PM PST 24 |
| Peak memory | 205032 kb |
| Host | smart-63fb44fd-419a-43a7-ac5c-d105cb4726c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3418643559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3418643559 |
| Directory | /workspace/39.edn_genbits/latest |
| Test location | /workspace/coverage/default/39.edn_intr.1055864060 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 26212518 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:38:55 PM PST 24 |
| Finished | Jan 17 01:38:58 PM PST 24 |
| Peak memory | 221552 kb |
| Host | smart-a75334f1-d43a-4c2f-adb4-f1b014bf8bde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1055864060 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1055864060 |
| Directory | /workspace/39.edn_intr/latest |
| Test location | /workspace/coverage/default/39.edn_smoke.3444284968 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 50446730 ps |
| CPU time | 0.82 seconds |
| Started | Jan 17 01:38:57 PM PST 24 |
| Finished | Jan 17 01:39:00 PM PST 24 |
| Peak memory | 204768 kb |
| Host | smart-bb455e7d-be17-4f59-b6e7-d02f1799c665 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3444284968 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3444284968 |
| Directory | /workspace/39.edn_smoke/latest |
| Test location | /workspace/coverage/default/39.edn_stress_all.3653662677 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 450135515 ps |
| CPU time | 3.22 seconds |
| Started | Jan 17 01:38:55 PM PST 24 |
| Finished | Jan 17 01:39:00 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-f6608ba2-4dc0-4bce-9d01-651078f274ee |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653662677 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3653662677 |
| Directory | /workspace/39.edn_stress_all/latest |
| Test location | /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3531161759 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 25936057052 ps |
| CPU time | 581.14 seconds |
| Started | Jan 17 01:38:58 PM PST 24 |
| Finished | Jan 17 01:48:42 PM PST 24 |
| Peak memory | 214496 kb |
| Host | smart-49d69c06-e040-4bb0-9685-5a0debd81c8a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531161759 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3531161759 |
| Directory | /workspace/39.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.edn_alert.2352358642 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 30603341 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:36:08 PM PST 24 |
| Finished | Jan 17 01:36:10 PM PST 24 |
| Peak memory | 205380 kb |
| Host | smart-899dff85-aa3f-4c41-96b5-af98059a2c22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2352358642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2352358642 |
| Directory | /workspace/4.edn_alert/latest |
| Test location | /workspace/coverage/default/4.edn_alert_test.1951770350 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 53602149 ps |
| CPU time | 0.9 seconds |
| Started | Jan 17 01:36:09 PM PST 24 |
| Finished | Jan 17 01:36:10 PM PST 24 |
| Peak memory | 204528 kb |
| Host | smart-aeb3fe17-db36-4faa-b8f9-fd07f12b16f8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951770350 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1951770350 |
| Directory | /workspace/4.edn_alert_test/latest |
| Test location | /workspace/coverage/default/4.edn_disable.2111407096 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 18450340 ps |
| CPU time | 0.9 seconds |
| Started | Jan 17 01:36:08 PM PST 24 |
| Finished | Jan 17 01:36:10 PM PST 24 |
| Peak memory | 214400 kb |
| Host | smart-537d8867-07bd-46e3-a51e-60ce1c8cf5ff |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111407096 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2111407096 |
| Directory | /workspace/4.edn_disable/latest |
| Test location | /workspace/coverage/default/4.edn_disable_auto_req_mode.3507610313 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 96237324 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:36:10 PM PST 24 |
| Finished | Jan 17 01:36:17 PM PST 24 |
| Peak memory | 214448 kb |
| Host | smart-f7b7aae7-dac9-438a-96ba-11b434f6b9de |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507610313 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di sable_auto_req_mode.3507610313 |
| Directory | /workspace/4.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/4.edn_err.885480833 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 24376928 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:36:05 PM PST 24 |
| Finished | Jan 17 01:36:07 PM PST 24 |
| Peak memory | 215996 kb |
| Host | smart-764862eb-c65e-4c54-8c9f-0d8e8424e5da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=885480833 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.885480833 |
| Directory | /workspace/4.edn_err/latest |
| Test location | /workspace/coverage/default/4.edn_genbits.2550125734 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 280037620 ps |
| CPU time | 2.56 seconds |
| Started | Jan 17 01:35:59 PM PST 24 |
| Finished | Jan 17 01:36:02 PM PST 24 |
| Peak memory | 214116 kb |
| Host | smart-09a02c73-7ddc-40c0-b9ec-ec0770cc0b39 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2550125734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2550125734 |
| Directory | /workspace/4.edn_genbits/latest |
| Test location | /workspace/coverage/default/4.edn_intr.561026468 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 22956753 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:36:01 PM PST 24 |
| Finished | Jan 17 01:36:02 PM PST 24 |
| Peak memory | 225804 kb |
| Host | smart-1e97b93a-06d2-4493-95b6-e69575d3af42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=561026468 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.561026468 |
| Directory | /workspace/4.edn_intr/latest |
| Test location | /workspace/coverage/default/4.edn_regwen.1955866541 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 38372971 ps |
| CPU time | 0.84 seconds |
| Started | Jan 17 01:35:59 PM PST 24 |
| Finished | Jan 17 01:36:01 PM PST 24 |
| Peak memory | 204828 kb |
| Host | smart-6560721c-ea8f-4fc3-a6af-0557da2325b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1955866541 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1955866541 |
| Directory | /workspace/4.edn_regwen/latest |
| Test location | /workspace/coverage/default/4.edn_sec_cm.1697805399 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 1036136609 ps |
| CPU time | 7 seconds |
| Started | Jan 17 01:36:09 PM PST 24 |
| Finished | Jan 17 01:36:23 PM PST 24 |
| Peak memory | 232936 kb |
| Host | smart-1ce7e215-14d2-4863-8f96-14963fdcdefa |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697805399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1697805399 |
| Directory | /workspace/4.edn_sec_cm/latest |
| Test location | /workspace/coverage/default/4.edn_smoke.3661948753 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 20058847 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:35:59 PM PST 24 |
| Finished | Jan 17 01:36:01 PM PST 24 |
| Peak memory | 204684 kb |
| Host | smart-f349cdad-0968-4e62-9fa2-3eb3a24a17b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3661948753 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3661948753 |
| Directory | /workspace/4.edn_smoke/latest |
| Test location | /workspace/coverage/default/4.edn_stress_all.2173474592 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 108603435 ps |
| CPU time | 2.69 seconds |
| Started | Jan 17 01:36:00 PM PST 24 |
| Finished | Jan 17 01:36:04 PM PST 24 |
| Peak memory | 205680 kb |
| Host | smart-74712382-1188-4b0d-9880-2501cf0db76b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173474592 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2173474592 |
| Directory | /workspace/4.edn_stress_all/latest |
| Test location | /workspace/coverage/default/4.edn_stress_all_with_rand_reset.125280514 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 248709961529 ps |
| CPU time | 2755.52 seconds |
| Started | Jan 17 01:36:02 PM PST 24 |
| Finished | Jan 17 02:21:59 PM PST 24 |
| Peak memory | 224896 kb |
| Host | smart-34ed0386-78cc-49df-9368-60d2e1bd3856 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125280514 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.125280514 |
| Directory | /workspace/4.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.edn_alert.2575457754 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 28377701 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:39:07 PM PST 24 |
| Finished | Jan 17 01:39:09 PM PST 24 |
| Peak memory | 206016 kb |
| Host | smart-e5bbc6a3-2afc-4fa0-bdb2-2ecd4dd4a42c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2575457754 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2575457754 |
| Directory | /workspace/40.edn_alert/latest |
| Test location | /workspace/coverage/default/40.edn_alert_test.1881308031 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 16107047 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:39:17 PM PST 24 |
| Finished | Jan 17 01:39:20 PM PST 24 |
| Peak memory | 205288 kb |
| Host | smart-e3d8f383-f7ac-43c6-b586-13de927bbc8b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881308031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1881308031 |
| Directory | /workspace/40.edn_alert_test/latest |
| Test location | /workspace/coverage/default/40.edn_disable.2104269327 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 18985784 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:39:09 PM PST 24 |
| Finished | Jan 17 01:39:10 PM PST 24 |
| Peak memory | 214344 kb |
| Host | smart-9e7565ae-54a8-4aa2-9400-a05db14937f2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104269327 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2104269327 |
| Directory | /workspace/40.edn_disable/latest |
| Test location | /workspace/coverage/default/40.edn_disable_auto_req_mode.119221412 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 79372634 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:39:17 PM PST 24 |
| Finished | Jan 17 01:39:20 PM PST 24 |
| Peak memory | 214420 kb |
| Host | smart-d98aff84-0ff9-4924-94c4-58109893addb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119221412 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di sable_auto_req_mode.119221412 |
| Directory | /workspace/40.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/40.edn_err.2188356566 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 24344605 ps |
| CPU time | 1.17 seconds |
| Started | Jan 17 01:39:08 PM PST 24 |
| Finished | Jan 17 01:39:10 PM PST 24 |
| Peak memory | 216156 kb |
| Host | smart-f94330a4-c5e5-4158-8823-b9f732275135 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2188356566 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2188356566 |
| Directory | /workspace/40.edn_err/latest |
| Test location | /workspace/coverage/default/40.edn_genbits.4130610718 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 44619638 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:39:16 PM PST 24 |
| Finished | Jan 17 01:39:20 PM PST 24 |
| Peak memory | 205468 kb |
| Host | smart-4360ca68-5c69-4f6d-94aa-f885fa9de4d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4130610718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.4130610718 |
| Directory | /workspace/40.edn_genbits/latest |
| Test location | /workspace/coverage/default/40.edn_intr.649634546 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 34120833 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 01:39:11 PM PST 24 |
| Finished | Jan 17 01:39:13 PM PST 24 |
| Peak memory | 214448 kb |
| Host | smart-486959ff-524c-4db3-b5f1-2faa7bbc87a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=649634546 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.649634546 |
| Directory | /workspace/40.edn_intr/latest |
| Test location | /workspace/coverage/default/40.edn_smoke.317784442 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 26416075 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:39:12 PM PST 24 |
| Finished | Jan 17 01:39:13 PM PST 24 |
| Peak memory | 204856 kb |
| Host | smart-27aefe74-3d8c-4ded-aca7-96eba7d8e52d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=317784442 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.317784442 |
| Directory | /workspace/40.edn_smoke/latest |
| Test location | /workspace/coverage/default/40.edn_stress_all.3668212397 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 142432497 ps |
| CPU time | 1.34 seconds |
| Started | Jan 17 01:39:08 PM PST 24 |
| Finished | Jan 17 01:39:09 PM PST 24 |
| Peak memory | 205868 kb |
| Host | smart-c7f13978-2530-45cc-ad7a-11c239e49717 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668212397 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3668212397 |
| Directory | /workspace/40.edn_stress_all/latest |
| Test location | /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1440899282 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 215305015721 ps |
| CPU time | 2825.14 seconds |
| Started | Jan 17 01:39:12 PM PST 24 |
| Finished | Jan 17 02:26:18 PM PST 24 |
| Peak memory | 228128 kb |
| Host | smart-22d049f5-52c8-45b6-b1f4-299e9c18648f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440899282 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1440899282 |
| Directory | /workspace/40.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.edn_alert.2952628998 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 46271209 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:39:32 PM PST 24 |
| Finished | Jan 17 01:39:35 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-2175c5c2-62ba-4e2a-b224-d5368c24d037 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2952628998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2952628998 |
| Directory | /workspace/41.edn_alert/latest |
| Test location | /workspace/coverage/default/41.edn_alert_test.2736753305 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 54790182 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 01:39:28 PM PST 24 |
| Finished | Jan 17 01:39:30 PM PST 24 |
| Peak memory | 204476 kb |
| Host | smart-daf07716-dd18-4296-99bb-39bfb1dbabfb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736753305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2736753305 |
| Directory | /workspace/41.edn_alert_test/latest |
| Test location | /workspace/coverage/default/41.edn_disable.1655477114 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 21553395 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:39:34 PM PST 24 |
| Finished | Jan 17 01:39:40 PM PST 24 |
| Peak memory | 214352 kb |
| Host | smart-8565df99-96c6-42fb-b4d1-658f678c46bf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655477114 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1655477114 |
| Directory | /workspace/41.edn_disable/latest |
| Test location | /workspace/coverage/default/41.edn_disable_auto_req_mode.2590083879 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 208239314 ps |
| CPU time | 1.16 seconds |
| Started | Jan 17 01:39:28 PM PST 24 |
| Finished | Jan 17 01:39:29 PM PST 24 |
| Peak memory | 214452 kb |
| Host | smart-118f6f77-49f5-457e-86e6-4dc801556a05 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590083879 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d isable_auto_req_mode.2590083879 |
| Directory | /workspace/41.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/41.edn_err.3683741504 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 36539202 ps |
| CPU time | 1.04 seconds |
| Started | Jan 17 01:39:34 PM PST 24 |
| Finished | Jan 17 01:39:40 PM PST 24 |
| Peak memory | 221900 kb |
| Host | smart-00e990b6-397b-494f-ac10-7c4983189aa5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3683741504 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3683741504 |
| Directory | /workspace/41.edn_err/latest |
| Test location | /workspace/coverage/default/41.edn_genbits.1500160818 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 100688406 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 01:39:13 PM PST 24 |
| Finished | Jan 17 01:39:14 PM PST 24 |
| Peak memory | 204900 kb |
| Host | smart-606d0905-945d-4c96-bf2b-52c3492a4260 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1500160818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1500160818 |
| Directory | /workspace/41.edn_genbits/latest |
| Test location | /workspace/coverage/default/41.edn_intr.1517046862 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 24941102 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 01:39:31 PM PST 24 |
| Finished | Jan 17 01:39:33 PM PST 24 |
| Peak memory | 225752 kb |
| Host | smart-1e0da058-dccd-4473-8b58-a5e7fd15cf4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1517046862 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1517046862 |
| Directory | /workspace/41.edn_intr/latest |
| Test location | /workspace/coverage/default/41.edn_smoke.1927656220 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 22382231 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 01:39:11 PM PST 24 |
| Finished | Jan 17 01:39:13 PM PST 24 |
| Peak memory | 204848 kb |
| Host | smart-fc0bc282-aaa5-438a-a94e-a4cc42f69299 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1927656220 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1927656220 |
| Directory | /workspace/41.edn_smoke/latest |
| Test location | /workspace/coverage/default/41.edn_stress_all.2760845027 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 276425604 ps |
| CPU time | 3.11 seconds |
| Started | Jan 17 01:39:13 PM PST 24 |
| Finished | Jan 17 01:39:17 PM PST 24 |
| Peak memory | 205704 kb |
| Host | smart-09cc8478-bbe3-493d-ab76-537dd8356ca8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760845027 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2760845027 |
| Directory | /workspace/41.edn_stress_all/latest |
| Test location | /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2892978276 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 98793705880 ps |
| CPU time | 1484.55 seconds |
| Started | Jan 17 01:39:32 PM PST 24 |
| Finished | Jan 17 02:04:20 PM PST 24 |
| Peak memory | 217776 kb |
| Host | smart-f9bcb35c-6b41-4add-9ba6-ded1f9eb1fb9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892978276 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2892978276 |
| Directory | /workspace/41.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.edn_alert.1676365113 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 63413862 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:39:31 PM PST 24 |
| Finished | Jan 17 01:39:33 PM PST 24 |
| Peak memory | 205680 kb |
| Host | smart-f4afd5ed-a904-439c-8db5-dd78691e6684 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1676365113 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1676365113 |
| Directory | /workspace/42.edn_alert/latest |
| Test location | /workspace/coverage/default/42.edn_alert_test.2355923473 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 42882168 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:39:35 PM PST 24 |
| Finished | Jan 17 01:39:40 PM PST 24 |
| Peak memory | 204820 kb |
| Host | smart-ffa1f10e-de45-4ac6-b478-4a9a6012fb5f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355923473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2355923473 |
| Directory | /workspace/42.edn_alert_test/latest |
| Test location | /workspace/coverage/default/42.edn_disable.1334907502 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 37421115 ps |
| CPU time | 0.81 seconds |
| Started | Jan 17 01:39:34 PM PST 24 |
| Finished | Jan 17 01:39:39 PM PST 24 |
| Peak memory | 214316 kb |
| Host | smart-58c55743-f637-4a33-aa78-57dd842b19bd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334907502 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1334907502 |
| Directory | /workspace/42.edn_disable/latest |
| Test location | /workspace/coverage/default/42.edn_disable_auto_req_mode.234270509 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 22589420 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 01:39:28 PM PST 24 |
| Finished | Jan 17 01:39:30 PM PST 24 |
| Peak memory | 214408 kb |
| Host | smart-e5d455b2-0a88-4b92-b8d7-d6866d08b0ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234270509 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di sable_auto_req_mode.234270509 |
| Directory | /workspace/42.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/42.edn_err.1526126181 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 23738035 ps |
| CPU time | 0.9 seconds |
| Started | Jan 17 01:39:28 PM PST 24 |
| Finished | Jan 17 01:39:30 PM PST 24 |
| Peak memory | 215720 kb |
| Host | smart-861eb668-8aba-4bd5-ac3a-1da9d7d1ef2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1526126181 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1526126181 |
| Directory | /workspace/42.edn_err/latest |
| Test location | /workspace/coverage/default/42.edn_genbits.2403222859 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 47663366 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:39:27 PM PST 24 |
| Finished | Jan 17 01:39:28 PM PST 24 |
| Peak memory | 205120 kb |
| Host | smart-a824f277-d793-4d0e-aa9c-c002576eb7a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2403222859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2403222859 |
| Directory | /workspace/42.edn_genbits/latest |
| Test location | /workspace/coverage/default/42.edn_intr.1739197385 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 20757596 ps |
| CPU time | 1.15 seconds |
| Started | Jan 17 01:39:27 PM PST 24 |
| Finished | Jan 17 01:39:28 PM PST 24 |
| Peak memory | 221960 kb |
| Host | smart-6c6a04d9-b858-44bc-941b-ec61c2e13b6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1739197385 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1739197385 |
| Directory | /workspace/42.edn_intr/latest |
| Test location | /workspace/coverage/default/42.edn_smoke.3956529066 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 14201528 ps |
| CPU time | 0.91 seconds |
| Started | Jan 17 01:39:21 PM PST 24 |
| Finished | Jan 17 01:39:23 PM PST 24 |
| Peak memory | 204588 kb |
| Host | smart-3017d7c1-eda0-44a0-81bf-235616f09a13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3956529066 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3956529066 |
| Directory | /workspace/42.edn_smoke/latest |
| Test location | /workspace/coverage/default/42.edn_stress_all.1606387497 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 222898354 ps |
| CPU time | 2.47 seconds |
| Started | Jan 17 01:39:32 PM PST 24 |
| Finished | Jan 17 01:39:38 PM PST 24 |
| Peak memory | 205772 kb |
| Host | smart-614d23f6-abd2-4c32-bea8-d45ecc7c14ad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606387497 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1606387497 |
| Directory | /workspace/42.edn_stress_all/latest |
| Test location | /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3724795168 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 90057497536 ps |
| CPU time | 766.95 seconds |
| Started | Jan 17 01:39:35 PM PST 24 |
| Finished | Jan 17 01:52:26 PM PST 24 |
| Peak memory | 215836 kb |
| Host | smart-cc43dfa2-e9bf-49db-a3d9-80531b2d76a8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724795168 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3724795168 |
| Directory | /workspace/42.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.edn_alert.574731402 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 19342590 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:39:34 PM PST 24 |
| Finished | Jan 17 01:39:39 PM PST 24 |
| Peak memory | 205908 kb |
| Host | smart-56c7ed08-ff32-45a0-8522-875d352fbbb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=574731402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.574731402 |
| Directory | /workspace/43.edn_alert/latest |
| Test location | /workspace/coverage/default/43.edn_alert_test.2992431185 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 15759881 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 01:39:34 PM PST 24 |
| Finished | Jan 17 01:39:39 PM PST 24 |
| Peak memory | 205092 kb |
| Host | smart-c983e56a-7e9a-443d-8b4d-a3c4cd578552 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992431185 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2992431185 |
| Directory | /workspace/43.edn_alert_test/latest |
| Test location | /workspace/coverage/default/43.edn_disable.4084639331 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 22726397 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:39:32 PM PST 24 |
| Finished | Jan 17 01:39:35 PM PST 24 |
| Peak memory | 214256 kb |
| Host | smart-855eb8db-bf53-447d-a299-660d0d8120fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084639331 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.4084639331 |
| Directory | /workspace/43.edn_disable/latest |
| Test location | /workspace/coverage/default/43.edn_disable_auto_req_mode.1575586285 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 81721163 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 01:39:35 PM PST 24 |
| Finished | Jan 17 01:39:40 PM PST 24 |
| Peak memory | 214564 kb |
| Host | smart-fa6c601f-02bb-4186-8e5b-c284209d3d5f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575586285 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d isable_auto_req_mode.1575586285 |
| Directory | /workspace/43.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/43.edn_err.398531911 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 19133991 ps |
| CPU time | 1.15 seconds |
| Started | Jan 17 01:39:34 PM PST 24 |
| Finished | Jan 17 01:39:40 PM PST 24 |
| Peak memory | 221968 kb |
| Host | smart-ff432891-e723-41ee-b213-603e72463281 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=398531911 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.398531911 |
| Directory | /workspace/43.edn_err/latest |
| Test location | /workspace/coverage/default/43.edn_genbits.2087576082 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 105101464 ps |
| CPU time | 1.1 seconds |
| Started | Jan 17 01:39:41 PM PST 24 |
| Finished | Jan 17 01:39:50 PM PST 24 |
| Peak memory | 205504 kb |
| Host | smart-fd6c0b3e-1d40-4881-b03a-363c7410ee31 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2087576082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2087576082 |
| Directory | /workspace/43.edn_genbits/latest |
| Test location | /workspace/coverage/default/43.edn_intr.4166416163 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 61824943 ps |
| CPU time | 0.82 seconds |
| Started | Jan 17 01:39:35 PM PST 24 |
| Finished | Jan 17 01:39:40 PM PST 24 |
| Peak memory | 213948 kb |
| Host | smart-b3f35160-0994-4906-bafc-3d922c230359 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4166416163 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.4166416163 |
| Directory | /workspace/43.edn_intr/latest |
| Test location | /workspace/coverage/default/43.edn_smoke.3281736756 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 54510588 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:39:27 PM PST 24 |
| Finished | Jan 17 01:39:28 PM PST 24 |
| Peak memory | 204616 kb |
| Host | smart-b39213cb-29e1-49bc-a32a-e5bdfdfbb3f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3281736756 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3281736756 |
| Directory | /workspace/43.edn_smoke/latest |
| Test location | /workspace/coverage/default/43.edn_stress_all.3213751176 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 261391211 ps |
| CPU time | 3.51 seconds |
| Started | Jan 17 01:39:27 PM PST 24 |
| Finished | Jan 17 01:39:31 PM PST 24 |
| Peak memory | 205872 kb |
| Host | smart-b4b59767-d8ef-4c01-80e9-4e0e51f7961d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213751176 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3213751176 |
| Directory | /workspace/43.edn_stress_all/latest |
| Test location | /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2642315016 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 35775370691 ps |
| CPU time | 607.32 seconds |
| Started | Jan 17 01:39:39 PM PST 24 |
| Finished | Jan 17 01:49:55 PM PST 24 |
| Peak memory | 216012 kb |
| Host | smart-66190845-b1a5-4a29-bfb6-fe61fb3c45eb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642315016 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2642315016 |
| Directory | /workspace/43.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.edn_alert.3974235240 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 21204885 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:39:29 PM PST 24 |
| Finished | Jan 17 01:39:31 PM PST 24 |
| Peak memory | 205032 kb |
| Host | smart-3e0a8635-6797-40df-b7cb-d1bc5107e2af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3974235240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3974235240 |
| Directory | /workspace/44.edn_alert/latest |
| Test location | /workspace/coverage/default/44.edn_alert_test.2135142564 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 32829612 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 01:39:33 PM PST 24 |
| Finished | Jan 17 01:39:38 PM PST 24 |
| Peak memory | 205112 kb |
| Host | smart-9127506f-76c5-4ec5-822d-ee95f60d8c2c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135142564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2135142564 |
| Directory | /workspace/44.edn_alert_test/latest |
| Test location | /workspace/coverage/default/44.edn_disable.2577684729 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 65213849 ps |
| CPU time | 0.82 seconds |
| Started | Jan 17 01:39:43 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 214376 kb |
| Host | smart-ff3aeef4-df4c-4bfe-8a7c-b02466227172 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577684729 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2577684729 |
| Directory | /workspace/44.edn_disable/latest |
| Test location | /workspace/coverage/default/44.edn_disable_auto_req_mode.2177484188 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 96993222 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:39:39 PM PST 24 |
| Finished | Jan 17 01:39:49 PM PST 24 |
| Peak memory | 214524 kb |
| Host | smart-c74dfe99-0e5a-4999-a831-21c3d8cb32ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177484188 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d isable_auto_req_mode.2177484188 |
| Directory | /workspace/44.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/44.edn_err.797179162 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 29570983 ps |
| CPU time | 1.2 seconds |
| Started | Jan 17 01:39:34 PM PST 24 |
| Finished | Jan 17 01:39:40 PM PST 24 |
| Peak memory | 216968 kb |
| Host | smart-5b9fab48-d24e-47db-adf8-f13d62046b1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=797179162 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.797179162 |
| Directory | /workspace/44.edn_err/latest |
| Test location | /workspace/coverage/default/44.edn_genbits.1409224526 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 167635783 ps |
| CPU time | 2.86 seconds |
| Started | Jan 17 01:39:43 PM PST 24 |
| Finished | Jan 17 01:39:53 PM PST 24 |
| Peak memory | 214124 kb |
| Host | smart-320f1673-7872-49dd-9ffe-1b440694a26a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1409224526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1409224526 |
| Directory | /workspace/44.edn_genbits/latest |
| Test location | /workspace/coverage/default/44.edn_intr.1832028896 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 39995972 ps |
| CPU time | 0.84 seconds |
| Started | Jan 17 01:39:31 PM PST 24 |
| Finished | Jan 17 01:39:33 PM PST 24 |
| Peak memory | 214272 kb |
| Host | smart-de37dec2-20fc-45e8-931d-dde169ef300e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1832028896 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1832028896 |
| Directory | /workspace/44.edn_intr/latest |
| Test location | /workspace/coverage/default/44.edn_smoke.146985232 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 16601818 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:39:32 PM PST 24 |
| Finished | Jan 17 01:39:35 PM PST 24 |
| Peak memory | 204856 kb |
| Host | smart-b720c8ae-581e-4511-a361-ef8dedbd22e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=146985232 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.146985232 |
| Directory | /workspace/44.edn_smoke/latest |
| Test location | /workspace/coverage/default/44.edn_stress_all.911529373 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 391033605 ps |
| CPU time | 2.53 seconds |
| Started | Jan 17 01:39:43 PM PST 24 |
| Finished | Jan 17 01:39:52 PM PST 24 |
| Peak memory | 205928 kb |
| Host | smart-22106aba-026a-48e5-813c-4f163e154331 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911529373 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.911529373 |
| Directory | /workspace/44.edn_stress_all/latest |
| Test location | /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1655187329 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 202649544127 ps |
| CPU time | 1285.93 seconds |
| Started | Jan 17 01:39:29 PM PST 24 |
| Finished | Jan 17 02:00:56 PM PST 24 |
| Peak memory | 218828 kb |
| Host | smart-4a59504e-b176-429f-a673-5117701b796e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655187329 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1655187329 |
| Directory | /workspace/44.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.edn_alert.4215685154 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 29412270 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:39:40 PM PST 24 |
| Finished | Jan 17 01:39:49 PM PST 24 |
| Peak memory | 205136 kb |
| Host | smart-fa1aa6a3-5fd7-446c-986e-04dacc409178 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4215685154 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.4215685154 |
| Directory | /workspace/45.edn_alert/latest |
| Test location | /workspace/coverage/default/45.edn_alert_test.80425203 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 59098892 ps |
| CPU time | 1.14 seconds |
| Started | Jan 17 01:39:30 PM PST 24 |
| Finished | Jan 17 01:39:32 PM PST 24 |
| Peak memory | 204652 kb |
| Host | smart-e55f9c16-eb64-40e0-8f4e-535961ca069c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80425203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.80425203 |
| Directory | /workspace/45.edn_alert_test/latest |
| Test location | /workspace/coverage/default/45.edn_disable.3664384898 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 34376195 ps |
| CPU time | 0.8 seconds |
| Started | Jan 17 01:39:43 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 214324 kb |
| Host | smart-bdec606d-e741-4005-bb5e-a9e0437f446a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664384898 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.3664384898 |
| Directory | /workspace/45.edn_disable/latest |
| Test location | /workspace/coverage/default/45.edn_disable_auto_req_mode.1321051704 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 57756328 ps |
| CPU time | 1.07 seconds |
| Started | Jan 17 01:39:32 PM PST 24 |
| Finished | Jan 17 01:39:34 PM PST 24 |
| Peak memory | 214468 kb |
| Host | smart-ed74db42-3607-4fe6-a2f4-3195a311bc3c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321051704 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d isable_auto_req_mode.1321051704 |
| Directory | /workspace/45.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/45.edn_err.547121789 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 19950099 ps |
| CPU time | 1.21 seconds |
| Started | Jan 17 01:39:42 PM PST 24 |
| Finished | Jan 17 01:39:50 PM PST 24 |
| Peak memory | 221928 kb |
| Host | smart-75583a2a-b466-4572-851f-4560fdbef3fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=547121789 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.547121789 |
| Directory | /workspace/45.edn_err/latest |
| Test location | /workspace/coverage/default/45.edn_genbits.1332408997 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 33711733 ps |
| CPU time | 1.02 seconds |
| Started | Jan 17 01:39:32 PM PST 24 |
| Finished | Jan 17 01:39:35 PM PST 24 |
| Peak memory | 205456 kb |
| Host | smart-17e13c82-d033-4642-91d3-3569f14e851f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1332408997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1332408997 |
| Directory | /workspace/45.edn_genbits/latest |
| Test location | /workspace/coverage/default/45.edn_intr.1768852619 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 24634092 ps |
| CPU time | 1.04 seconds |
| Started | Jan 17 01:39:44 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 222064 kb |
| Host | smart-c4ca9e9c-e29a-4ef1-8f09-c5baef4c9a44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1768852619 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.1768852619 |
| Directory | /workspace/45.edn_intr/latest |
| Test location | /workspace/coverage/default/45.edn_smoke.273845873 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 25260571 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:39:30 PM PST 24 |
| Finished | Jan 17 01:39:32 PM PST 24 |
| Peak memory | 204916 kb |
| Host | smart-2c2bb679-ad30-4c82-9eaf-b909e133cd83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=273845873 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.273845873 |
| Directory | /workspace/45.edn_smoke/latest |
| Test location | /workspace/coverage/default/45.edn_stress_all.1462590591 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 1767609094 ps |
| CPU time | 3.97 seconds |
| Started | Jan 17 01:39:41 PM PST 24 |
| Finished | Jan 17 01:39:53 PM PST 24 |
| Peak memory | 205956 kb |
| Host | smart-1ba01bb5-1845-4127-95e7-f18a68ec8e14 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462590591 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1462590591 |
| Directory | /workspace/45.edn_stress_all/latest |
| Test location | /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3111814584 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 42566173127 ps |
| CPU time | 999.48 seconds |
| Started | Jan 17 01:39:27 PM PST 24 |
| Finished | Jan 17 01:56:08 PM PST 24 |
| Peak memory | 216108 kb |
| Host | smart-a0da175f-7490-4f9e-a036-d4f418c3ff4c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111814584 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3111814584 |
| Directory | /workspace/45.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.edn_alert.3405128436 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 34918106 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:39:27 PM PST 24 |
| Finished | Jan 17 01:39:29 PM PST 24 |
| Peak memory | 205048 kb |
| Host | smart-ae47d72b-6d0b-4816-96aa-c674f9a26ee1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3405128436 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.3405128436 |
| Directory | /workspace/46.edn_alert/latest |
| Test location | /workspace/coverage/default/46.edn_alert_test.228759779 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 19566980 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:39:34 PM PST 24 |
| Finished | Jan 17 01:39:39 PM PST 24 |
| Peak memory | 205112 kb |
| Host | smart-4b197dec-663c-4383-83ea-8445f9d5a958 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228759779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.228759779 |
| Directory | /workspace/46.edn_alert_test/latest |
| Test location | /workspace/coverage/default/46.edn_disable_auto_req_mode.2873380223 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 84488210 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:39:34 PM PST 24 |
| Finished | Jan 17 01:39:39 PM PST 24 |
| Peak memory | 214420 kb |
| Host | smart-acfbf96e-d7ae-43fc-ae96-a344ad6c491f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873380223 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d isable_auto_req_mode.2873380223 |
| Directory | /workspace/46.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/46.edn_err.1146661059 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 27893054 ps |
| CPU time | 0.8 seconds |
| Started | Jan 17 01:39:31 PM PST 24 |
| Finished | Jan 17 01:39:32 PM PST 24 |
| Peak memory | 215468 kb |
| Host | smart-6c287d6a-1a3d-42eb-8757-cbfd43ed87c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1146661059 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1146661059 |
| Directory | /workspace/46.edn_err/latest |
| Test location | /workspace/coverage/default/46.edn_genbits.3619692177 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 332104005 ps |
| CPU time | 3.64 seconds |
| Started | Jan 17 01:39:33 PM PST 24 |
| Finished | Jan 17 01:39:39 PM PST 24 |
| Peak memory | 214060 kb |
| Host | smart-d6025a24-d837-4642-a07f-9ebb6b1f9ed9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3619692177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3619692177 |
| Directory | /workspace/46.edn_genbits/latest |
| Test location | /workspace/coverage/default/46.edn_intr.2545710292 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 33351311 ps |
| CPU time | 0.9 seconds |
| Started | Jan 17 01:39:29 PM PST 24 |
| Finished | Jan 17 01:39:30 PM PST 24 |
| Peak memory | 214376 kb |
| Host | smart-6cfbf485-336c-4b73-bb0f-5824639a49ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2545710292 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2545710292 |
| Directory | /workspace/46.edn_intr/latest |
| Test location | /workspace/coverage/default/46.edn_smoke.970785876 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 38957763 ps |
| CPU time | 0.81 seconds |
| Started | Jan 17 01:39:30 PM PST 24 |
| Finished | Jan 17 01:39:31 PM PST 24 |
| Peak memory | 204768 kb |
| Host | smart-d55c0919-6a29-4fbc-a390-2734b1552d7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=970785876 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.970785876 |
| Directory | /workspace/46.edn_smoke/latest |
| Test location | /workspace/coverage/default/46.edn_stress_all.70577112 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 714833005 ps |
| CPU time | 3.89 seconds |
| Started | Jan 17 01:39:33 PM PST 24 |
| Finished | Jan 17 01:39:42 PM PST 24 |
| Peak memory | 206032 kb |
| Host | smart-eceeff1f-7dab-4b02-943f-11ead974a3c9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70577112 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.70577112 |
| Directory | /workspace/46.edn_stress_all/latest |
| Test location | /workspace/coverage/default/46.edn_stress_all_with_rand_reset.487258556 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 131710461524 ps |
| CPU time | 1585.56 seconds |
| Started | Jan 17 01:39:29 PM PST 24 |
| Finished | Jan 17 02:05:55 PM PST 24 |
| Peak memory | 221304 kb |
| Host | smart-190c4cc6-575a-41e6-92ea-0c9e5c90a997 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487258556 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.487258556 |
| Directory | /workspace/46.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.edn_alert.1833686618 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 26023404 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:39:34 PM PST 24 |
| Finished | Jan 17 01:39:40 PM PST 24 |
| Peak memory | 205132 kb |
| Host | smart-bcf50128-e594-4c53-bab1-40559078c0fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1833686618 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1833686618 |
| Directory | /workspace/47.edn_alert/latest |
| Test location | /workspace/coverage/default/47.edn_alert_test.3559090075 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 38183816 ps |
| CPU time | 1.1 seconds |
| Started | Jan 17 01:39:43 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 205048 kb |
| Host | smart-8e7bc657-96e1-4bd5-b131-a65d8b50b9e8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559090075 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3559090075 |
| Directory | /workspace/47.edn_alert_test/latest |
| Test location | /workspace/coverage/default/47.edn_disable.849103398 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 45479625 ps |
| CPU time | 0.84 seconds |
| Started | Jan 17 01:39:43 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 213936 kb |
| Host | smart-44219559-b0d0-4f05-9b5a-827e9a9d381d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849103398 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.849103398 |
| Directory | /workspace/47.edn_disable/latest |
| Test location | /workspace/coverage/default/47.edn_disable_auto_req_mode.3903040178 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 21383029 ps |
| CPU time | 1.02 seconds |
| Started | Jan 17 01:39:39 PM PST 24 |
| Finished | Jan 17 01:39:49 PM PST 24 |
| Peak memory | 214348 kb |
| Host | smart-4923d015-6423-45cf-bb2a-9a4fd0a8b72e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903040178 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d isable_auto_req_mode.3903040178 |
| Directory | /workspace/47.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/47.edn_err.2658507743 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 70477692 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 01:39:34 PM PST 24 |
| Finished | Jan 17 01:39:39 PM PST 24 |
| Peak memory | 217104 kb |
| Host | smart-6e4fa21f-b3ec-4c74-b439-2ce1883af2c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2658507743 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2658507743 |
| Directory | /workspace/47.edn_err/latest |
| Test location | /workspace/coverage/default/47.edn_genbits.1108369325 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 29241825 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 01:39:41 PM PST 24 |
| Finished | Jan 17 01:39:50 PM PST 24 |
| Peak memory | 205476 kb |
| Host | smart-5f84784e-375d-4bab-ae6f-30fe2afd9b63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1108369325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1108369325 |
| Directory | /workspace/47.edn_genbits/latest |
| Test location | /workspace/coverage/default/47.edn_intr.2469205538 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 21806610 ps |
| CPU time | 1.15 seconds |
| Started | Jan 17 01:39:42 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 221972 kb |
| Host | smart-ddac18f1-cab0-42bc-9199-c49177ad1f4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2469205538 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2469205538 |
| Directory | /workspace/47.edn_intr/latest |
| Test location | /workspace/coverage/default/47.edn_smoke.1963005264 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 44218857 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:39:31 PM PST 24 |
| Finished | Jan 17 01:39:33 PM PST 24 |
| Peak memory | 204848 kb |
| Host | smart-e065c3ef-7e4a-403f-86ea-f9008508d6b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1963005264 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1963005264 |
| Directory | /workspace/47.edn_smoke/latest |
| Test location | /workspace/coverage/default/47.edn_stress_all.26417974 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 307038535 ps |
| CPU time | 3.6 seconds |
| Started | Jan 17 01:39:45 PM PST 24 |
| Finished | Jan 17 01:39:53 PM PST 24 |
| Peak memory | 205992 kb |
| Host | smart-3d22ed20-2b3e-4849-97f0-b98cdaef0783 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26417974 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.26417974 |
| Directory | /workspace/47.edn_stress_all/latest |
| Test location | /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2517025229 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 299723182364 ps |
| CPU time | 1849.44 seconds |
| Started | Jan 17 01:39:34 PM PST 24 |
| Finished | Jan 17 02:10:28 PM PST 24 |
| Peak memory | 222636 kb |
| Host | smart-6db1cbb2-dce1-4327-8ed7-8888bf05870f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517025229 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2517025229 |
| Directory | /workspace/47.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.edn_alert.1204836251 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 21163879 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:39:34 PM PST 24 |
| Finished | Jan 17 01:39:40 PM PST 24 |
| Peak memory | 205932 kb |
| Host | smart-8fbe5d8e-f6ce-481f-b139-fc8ed9b40e63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1204836251 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1204836251 |
| Directory | /workspace/48.edn_alert/latest |
| Test location | /workspace/coverage/default/48.edn_alert_test.3940266139 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 46259070 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:39:34 PM PST 24 |
| Finished | Jan 17 01:39:39 PM PST 24 |
| Peak memory | 205364 kb |
| Host | smart-81f20355-fe2f-4223-8764-c54f2e714c97 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940266139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3940266139 |
| Directory | /workspace/48.edn_alert_test/latest |
| Test location | /workspace/coverage/default/48.edn_disable.90925046 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 21792466 ps |
| CPU time | 0.91 seconds |
| Started | Jan 17 01:39:43 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 214420 kb |
| Host | smart-5849ce30-17d7-4361-9c76-bafb992ae38e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90925046 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.90925046 |
| Directory | /workspace/48.edn_disable/latest |
| Test location | /workspace/coverage/default/48.edn_disable_auto_req_mode.565878479 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 23448202 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:39:37 PM PST 24 |
| Finished | Jan 17 01:39:40 PM PST 24 |
| Peak memory | 214464 kb |
| Host | smart-32d61bb8-3a01-49ed-8ca6-eac943e66fd6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565878479 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di sable_auto_req_mode.565878479 |
| Directory | /workspace/48.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/48.edn_err.1284676253 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 37370393 ps |
| CPU time | 1.14 seconds |
| Started | Jan 17 01:39:41 PM PST 24 |
| Finished | Jan 17 01:39:50 PM PST 24 |
| Peak memory | 221888 kb |
| Host | smart-1e62f914-dcc5-4458-930c-bcbd61d1409c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1284676253 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1284676253 |
| Directory | /workspace/48.edn_err/latest |
| Test location | /workspace/coverage/default/48.edn_intr.2160458145 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 26008294 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:39:32 PM PST 24 |
| Finished | Jan 17 01:39:36 PM PST 24 |
| Peak memory | 221996 kb |
| Host | smart-453bc2b3-c65e-4dcd-b05b-329681aebbfc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2160458145 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2160458145 |
| Directory | /workspace/48.edn_intr/latest |
| Test location | /workspace/coverage/default/48.edn_smoke.4090579489 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 37155421 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:39:43 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 204776 kb |
| Host | smart-9c766e8b-c6fb-414f-a7a1-618dc2acf975 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4090579489 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.4090579489 |
| Directory | /workspace/48.edn_smoke/latest |
| Test location | /workspace/coverage/default/48.edn_stress_all.3885426543 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 750413269 ps |
| CPU time | 3.33 seconds |
| Started | Jan 17 01:39:39 PM PST 24 |
| Finished | Jan 17 01:39:52 PM PST 24 |
| Peak memory | 206116 kb |
| Host | smart-1c771c83-1b1a-491f-b30e-36b0a4f90fea |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885426543 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3885426543 |
| Directory | /workspace/48.edn_stress_all/latest |
| Test location | /workspace/coverage/default/48.edn_stress_all_with_rand_reset.4037061094 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 75782874998 ps |
| CPU time | 895.32 seconds |
| Started | Jan 17 01:39:32 PM PST 24 |
| Finished | Jan 17 01:54:31 PM PST 24 |
| Peak memory | 214560 kb |
| Host | smart-8e2e22d4-31b2-42bd-b32c-ffedd36ac4fd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037061094 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.4037061094 |
| Directory | /workspace/48.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.edn_alert.3867157561 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 27646396 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:39:36 PM PST 24 |
| Finished | Jan 17 01:39:40 PM PST 24 |
| Peak memory | 205068 kb |
| Host | smart-c8a37f57-3d6b-4cf5-9bad-701869a1f3ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3867157561 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3867157561 |
| Directory | /workspace/49.edn_alert/latest |
| Test location | /workspace/coverage/default/49.edn_alert_test.2682854772 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 16483637 ps |
| CPU time | 0.78 seconds |
| Started | Jan 17 01:39:46 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 204212 kb |
| Host | smart-6068f778-c39b-41ad-9bc8-208863c99d9e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682854772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2682854772 |
| Directory | /workspace/49.edn_alert_test/latest |
| Test location | /workspace/coverage/default/49.edn_disable_auto_req_mode.1553138047 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 96147372 ps |
| CPU time | 1.05 seconds |
| Started | Jan 17 01:39:43 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 213952 kb |
| Host | smart-c0fbc41b-6a62-4704-a69f-03c27a4baee8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553138047 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d isable_auto_req_mode.1553138047 |
| Directory | /workspace/49.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/49.edn_err.1721712220 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 36069163 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:39:42 PM PST 24 |
| Finished | Jan 17 01:39:50 PM PST 24 |
| Peak memory | 216036 kb |
| Host | smart-7a2b1cf8-bd0e-4db0-8f24-2c484409bea2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1721712220 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1721712220 |
| Directory | /workspace/49.edn_err/latest |
| Test location | /workspace/coverage/default/49.edn_genbits.2253317915 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 39849363 ps |
| CPU time | 1.11 seconds |
| Started | Jan 17 01:39:34 PM PST 24 |
| Finished | Jan 17 01:39:40 PM PST 24 |
| Peak memory | 205928 kb |
| Host | smart-91a2a22a-2fc2-499c-a0f9-770bc2fbcbf3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2253317915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2253317915 |
| Directory | /workspace/49.edn_genbits/latest |
| Test location | /workspace/coverage/default/49.edn_intr.1849011058 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 63642581 ps |
| CPU time | 0.91 seconds |
| Started | Jan 17 01:39:43 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 225224 kb |
| Host | smart-ac0c563e-e562-458c-a52e-ed1265b3901e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1849011058 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1849011058 |
| Directory | /workspace/49.edn_intr/latest |
| Test location | /workspace/coverage/default/49.edn_smoke.2600453375 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 47638670 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 01:39:39 PM PST 24 |
| Finished | Jan 17 01:39:49 PM PST 24 |
| Peak memory | 204708 kb |
| Host | smart-e21f9aec-844a-470a-a9e0-dec830414a58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2600453375 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2600453375 |
| Directory | /workspace/49.edn_smoke/latest |
| Test location | /workspace/coverage/default/49.edn_stress_all.3486006530 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 181879578 ps |
| CPU time | 3.29 seconds |
| Started | Jan 17 01:39:35 PM PST 24 |
| Finished | Jan 17 01:39:42 PM PST 24 |
| Peak memory | 205840 kb |
| Host | smart-069b80e2-d3d0-4927-b647-848ea9b37d34 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486006530 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3486006530 |
| Directory | /workspace/49.edn_stress_all/latest |
| Test location | /workspace/coverage/default/49.edn_stress_all_with_rand_reset.193497937 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 27807788890 ps |
| CPU time | 648.22 seconds |
| Started | Jan 17 01:39:40 PM PST 24 |
| Finished | Jan 17 01:50:37 PM PST 24 |
| Peak memory | 215484 kb |
| Host | smart-f2f90071-3b61-4322-abbd-938072616491 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193497937 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.193497937 |
| Directory | /workspace/49.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.edn_alert.381748958 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 20319049 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:36:07 PM PST 24 |
| Finished | Jan 17 01:36:10 PM PST 24 |
| Peak memory | 205576 kb |
| Host | smart-07961ac3-c004-4cb3-8a68-ca9f83d230ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=381748958 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.381748958 |
| Directory | /workspace/5.edn_alert/latest |
| Test location | /workspace/coverage/default/5.edn_alert_test.3405445428 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 12418325 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:36:07 PM PST 24 |
| Finished | Jan 17 01:36:09 PM PST 24 |
| Peak memory | 204384 kb |
| Host | smart-25aba066-ebb0-4fe9-b794-caf4243c8aa8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405445428 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3405445428 |
| Directory | /workspace/5.edn_alert_test/latest |
| Test location | /workspace/coverage/default/5.edn_disable.887878805 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 88616991 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:36:08 PM PST 24 |
| Finished | Jan 17 01:36:10 PM PST 24 |
| Peak memory | 214328 kb |
| Host | smart-dcd8c319-4101-4170-bd44-5bb2643fcacf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887878805 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.887878805 |
| Directory | /workspace/5.edn_disable/latest |
| Test location | /workspace/coverage/default/5.edn_disable_auto_req_mode.3539913402 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 73314226 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:36:08 PM PST 24 |
| Finished | Jan 17 01:36:10 PM PST 24 |
| Peak memory | 214488 kb |
| Host | smart-69acca55-1150-4d3f-b369-6d7f78e99929 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539913402 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di sable_auto_req_mode.3539913402 |
| Directory | /workspace/5.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/5.edn_err.3862292928 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 36903372 ps |
| CPU time | 0.8 seconds |
| Started | Jan 17 01:36:07 PM PST 24 |
| Finished | Jan 17 01:36:09 PM PST 24 |
| Peak memory | 215676 kb |
| Host | smart-87ac45cd-8813-41e3-a32a-3e68befe4204 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3862292928 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3862292928 |
| Directory | /workspace/5.edn_err/latest |
| Test location | /workspace/coverage/default/5.edn_genbits.448968952 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 260027043 ps |
| CPU time | 3.84 seconds |
| Started | Jan 17 01:36:07 PM PST 24 |
| Finished | Jan 17 01:36:12 PM PST 24 |
| Peak memory | 214172 kb |
| Host | smart-b8372bf6-9503-40ac-8aaa-bc3264b04e1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=448968952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.448968952 |
| Directory | /workspace/5.edn_genbits/latest |
| Test location | /workspace/coverage/default/5.edn_regwen.92213278 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 15241032 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:36:09 PM PST 24 |
| Finished | Jan 17 01:36:17 PM PST 24 |
| Peak memory | 204932 kb |
| Host | smart-c15f3ce3-a950-4368-9f59-844945a9a418 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92213278 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.92213278 |
| Directory | /workspace/5.edn_regwen/latest |
| Test location | /workspace/coverage/default/5.edn_smoke.687958604 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 11455527 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:36:07 PM PST 24 |
| Finished | Jan 17 01:36:10 PM PST 24 |
| Peak memory | 204804 kb |
| Host | smart-48947d8e-3058-4475-a613-8f960c970cf7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=687958604 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.687958604 |
| Directory | /workspace/5.edn_smoke/latest |
| Test location | /workspace/coverage/default/5.edn_stress_all.1555079347 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 551513770 ps |
| CPU time | 3.12 seconds |
| Started | Jan 17 01:36:08 PM PST 24 |
| Finished | Jan 17 01:36:12 PM PST 24 |
| Peak memory | 206084 kb |
| Host | smart-8587ac2b-7da0-4903-abc0-277f43989fc3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555079347 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1555079347 |
| Directory | /workspace/5.edn_stress_all/latest |
| Test location | /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1857343371 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 101469854193 ps |
| CPU time | 704.04 seconds |
| Started | Jan 17 01:36:06 PM PST 24 |
| Finished | Jan 17 01:47:52 PM PST 24 |
| Peak memory | 215156 kb |
| Host | smart-6a47af9d-166c-4819-8546-41292d4aecfb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857343371 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1857343371 |
| Directory | /workspace/5.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/50.edn_genbits.3352598597 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 81715377 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 01:39:42 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 204848 kb |
| Host | smart-e54f6b72-148e-4233-a7a2-a44248df5b7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3352598597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3352598597 |
| Directory | /workspace/50.edn_genbits/latest |
| Test location | /workspace/coverage/default/51.edn_err.350155600 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 24433106 ps |
| CPU time | 0.88 seconds |
| Started | Jan 17 01:39:43 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 215900 kb |
| Host | smart-3a257210-8209-4c1c-a7b9-296dde4b04d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=350155600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.350155600 |
| Directory | /workspace/51.edn_err/latest |
| Test location | /workspace/coverage/default/51.edn_genbits.3596613046 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 24406739 ps |
| CPU time | 1.16 seconds |
| Started | Jan 17 01:39:42 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 205568 kb |
| Host | smart-64c38a31-ed1e-4034-9709-23d961787b9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3596613046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3596613046 |
| Directory | /workspace/51.edn_genbits/latest |
| Test location | /workspace/coverage/default/52.edn_err.1702132397 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 33001524 ps |
| CPU time | 0.91 seconds |
| Started | Jan 17 01:39:43 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 221352 kb |
| Host | smart-b876bff8-3dba-4cd7-ad8a-96214aecd5e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1702132397 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1702132397 |
| Directory | /workspace/52.edn_err/latest |
| Test location | /workspace/coverage/default/52.edn_genbits.847449585 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 114629708 ps |
| CPU time | 2.39 seconds |
| Started | Jan 17 01:39:46 PM PST 24 |
| Finished | Jan 17 01:39:52 PM PST 24 |
| Peak memory | 214148 kb |
| Host | smart-bd099106-75de-4791-aed1-93a01e0aa03a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=847449585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.847449585 |
| Directory | /workspace/52.edn_genbits/latest |
| Test location | /workspace/coverage/default/53.edn_err.1005917985 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 32626634 ps |
| CPU time | 0.8 seconds |
| Started | Jan 17 01:39:41 PM PST 24 |
| Finished | Jan 17 01:39:50 PM PST 24 |
| Peak memory | 215304 kb |
| Host | smart-cc5961ae-077c-468e-9c1a-3192599d9f99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1005917985 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1005917985 |
| Directory | /workspace/53.edn_err/latest |
| Test location | /workspace/coverage/default/53.edn_genbits.789832171 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 17234004 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:39:42 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 204852 kb |
| Host | smart-ada4db27-cc91-446d-aadf-fde0f5ff72f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=789832171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.789832171 |
| Directory | /workspace/53.edn_genbits/latest |
| Test location | /workspace/coverage/default/54.edn_err.3708906602 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 26641201 ps |
| CPU time | 0.78 seconds |
| Started | Jan 17 01:39:41 PM PST 24 |
| Finished | Jan 17 01:39:50 PM PST 24 |
| Peak memory | 215268 kb |
| Host | smart-5aad531f-8501-4c78-ab36-9175270087b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3708906602 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3708906602 |
| Directory | /workspace/54.edn_err/latest |
| Test location | /workspace/coverage/default/54.edn_genbits.137920022 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 30876766 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:39:44 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 214104 kb |
| Host | smart-713a1a06-d6b6-4c62-86f7-6b0e0e82d526 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=137920022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.137920022 |
| Directory | /workspace/54.edn_genbits/latest |
| Test location | /workspace/coverage/default/55.edn_err.2063667525 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 19884891 ps |
| CPU time | 1.17 seconds |
| Started | Jan 17 01:39:45 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 216476 kb |
| Host | smart-3d90710c-7cfc-4537-89b7-b93655040aaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2063667525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2063667525 |
| Directory | /workspace/55.edn_err/latest |
| Test location | /workspace/coverage/default/55.edn_genbits.1069036223 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 42288859 ps |
| CPU time | 1.25 seconds |
| Started | Jan 17 01:39:43 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 205584 kb |
| Host | smart-9abb39f9-2eb4-4399-8ca6-dd217e02b687 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1069036223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1069036223 |
| Directory | /workspace/55.edn_genbits/latest |
| Test location | /workspace/coverage/default/56.edn_err.3253685458 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 168468082 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:39:41 PM PST 24 |
| Finished | Jan 17 01:39:50 PM PST 24 |
| Peak memory | 221920 kb |
| Host | smart-ad74337a-2a0d-429d-9abf-796414e8f0ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3253685458 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3253685458 |
| Directory | /workspace/56.edn_err/latest |
| Test location | /workspace/coverage/default/56.edn_genbits.471223886 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 31559072 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:39:43 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 204724 kb |
| Host | smart-ac5d9956-b662-4225-8fd9-3921da5e6437 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=471223886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.471223886 |
| Directory | /workspace/56.edn_genbits/latest |
| Test location | /workspace/coverage/default/57.edn_err.2086147316 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 84563346 ps |
| CPU time | 1.09 seconds |
| Started | Jan 17 01:39:41 PM PST 24 |
| Finished | Jan 17 01:39:50 PM PST 24 |
| Peak memory | 216936 kb |
| Host | smart-4466778e-c2d4-462f-b72a-ee9e6172bd10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2086147316 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2086147316 |
| Directory | /workspace/57.edn_err/latest |
| Test location | /workspace/coverage/default/57.edn_genbits.2707353082 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 31987789 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:39:43 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 205520 kb |
| Host | smart-d7988776-c116-44e9-9e58-1d7228ca47d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2707353082 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2707353082 |
| Directory | /workspace/57.edn_genbits/latest |
| Test location | /workspace/coverage/default/58.edn_err.1596603294 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 20209103 ps |
| CPU time | 1.13 seconds |
| Started | Jan 17 01:39:45 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 216180 kb |
| Host | smart-cb433304-b44c-4d2a-a1f0-f5017cd02032 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1596603294 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1596603294 |
| Directory | /workspace/58.edn_err/latest |
| Test location | /workspace/coverage/default/58.edn_genbits.1252723199 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 44056534 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:39:44 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 205176 kb |
| Host | smart-81e122f1-b297-4ef1-aa01-8fd65e368e36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252723199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1252723199 |
| Directory | /workspace/58.edn_genbits/latest |
| Test location | /workspace/coverage/default/59.edn_err.1718790133 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 22632197 ps |
| CPU time | 1.14 seconds |
| Started | Jan 17 01:39:45 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 215708 kb |
| Host | smart-2870322a-224a-4d2f-99ad-645cd4a3d9fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1718790133 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1718790133 |
| Directory | /workspace/59.edn_err/latest |
| Test location | /workspace/coverage/default/59.edn_genbits.902071827 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 14949448 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:39:42 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 205392 kb |
| Host | smart-fb3bcbfe-bf29-4335-8565-122e1ee983df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=902071827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.902071827 |
| Directory | /workspace/59.edn_genbits/latest |
| Test location | /workspace/coverage/default/6.edn_alert.1396205493 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 21030863 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:36:26 PM PST 24 |
| Finished | Jan 17 01:36:29 PM PST 24 |
| Peak memory | 205876 kb |
| Host | smart-c56def09-cf27-45d1-931f-05e8e48fb09a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1396205493 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1396205493 |
| Directory | /workspace/6.edn_alert/latest |
| Test location | /workspace/coverage/default/6.edn_alert_test.4056743864 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 15625319 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:36:28 PM PST 24 |
| Finished | Jan 17 01:36:31 PM PST 24 |
| Peak memory | 205096 kb |
| Host | smart-a961b1ca-7364-4eb2-9ff0-e3f0a43bd3f0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056743864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.4056743864 |
| Directory | /workspace/6.edn_alert_test/latest |
| Test location | /workspace/coverage/default/6.edn_disable.4283263111 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 40427490 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:36:25 PM PST 24 |
| Finished | Jan 17 01:36:28 PM PST 24 |
| Peak memory | 214364 kb |
| Host | smart-4ffce722-e9e8-4ba3-befc-3e4dcc541c1c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283263111 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.4283263111 |
| Directory | /workspace/6.edn_disable/latest |
| Test location | /workspace/coverage/default/6.edn_genbits.2169020536 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 33069784 ps |
| CPU time | 1.45 seconds |
| Started | Jan 17 01:36:09 PM PST 24 |
| Finished | Jan 17 01:36:17 PM PST 24 |
| Peak memory | 214168 kb |
| Host | smart-fed34abb-b9fe-45f9-9f3a-203e2efc7645 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2169020536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2169020536 |
| Directory | /workspace/6.edn_genbits/latest |
| Test location | /workspace/coverage/default/6.edn_intr.2219843174 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 19917558 ps |
| CPU time | 1.06 seconds |
| Started | Jan 17 01:36:22 PM PST 24 |
| Finished | Jan 17 01:36:23 PM PST 24 |
| Peak memory | 214512 kb |
| Host | smart-4d5bbae5-4339-4e03-8aae-79df5f48f4a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2219843174 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2219843174 |
| Directory | /workspace/6.edn_intr/latest |
| Test location | /workspace/coverage/default/6.edn_regwen.3535686843 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 16255493 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:36:08 PM PST 24 |
| Finished | Jan 17 01:36:10 PM PST 24 |
| Peak memory | 204784 kb |
| Host | smart-80028240-5573-44cc-a950-7d332942a4a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3535686843 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3535686843 |
| Directory | /workspace/6.edn_regwen/latest |
| Test location | /workspace/coverage/default/6.edn_smoke.2264271953 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 14596350 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:36:08 PM PST 24 |
| Finished | Jan 17 01:36:10 PM PST 24 |
| Peak memory | 204852 kb |
| Host | smart-9a4e4d38-d3c2-4192-8a70-d91366206ef8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2264271953 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2264271953 |
| Directory | /workspace/6.edn_smoke/latest |
| Test location | /workspace/coverage/default/6.edn_stress_all.2100162241 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 263765937 ps |
| CPU time | 1.29 seconds |
| Started | Jan 17 01:36:23 PM PST 24 |
| Finished | Jan 17 01:36:25 PM PST 24 |
| Peak memory | 204960 kb |
| Host | smart-038e1219-e12c-44f5-b952-04b615083233 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100162241 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2100162241 |
| Directory | /workspace/6.edn_stress_all/latest |
| Test location | /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2650928441 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 60979316363 ps |
| CPU time | 773.34 seconds |
| Started | Jan 17 01:36:25 PM PST 24 |
| Finished | Jan 17 01:49:21 PM PST 24 |
| Peak memory | 215600 kb |
| Host | smart-a84b9118-05bd-4ab1-a5e4-860aee019244 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650928441 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2650928441 |
| Directory | /workspace/6.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/60.edn_err.1645760308 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 28693708 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 01:39:52 PM PST 24 |
| Finished | Jan 17 01:39:54 PM PST 24 |
| Peak memory | 216264 kb |
| Host | smart-279f6661-49c6-4e1c-8a4c-41ad8bd3b554 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1645760308 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1645760308 |
| Directory | /workspace/60.edn_err/latest |
| Test location | /workspace/coverage/default/60.edn_genbits.391761048 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 22729947 ps |
| CPU time | 1.06 seconds |
| Started | Jan 17 01:39:52 PM PST 24 |
| Finished | Jan 17 01:39:54 PM PST 24 |
| Peak memory | 205320 kb |
| Host | smart-1aeabeaa-13a9-4197-ab61-3b117218f798 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=391761048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.391761048 |
| Directory | /workspace/60.edn_genbits/latest |
| Test location | /workspace/coverage/default/61.edn_err.2912332412 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 26921904 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:39:46 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 215676 kb |
| Host | smart-a506d54f-0206-4708-ae2c-d67d06380b6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2912332412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2912332412 |
| Directory | /workspace/61.edn_err/latest |
| Test location | /workspace/coverage/default/61.edn_genbits.295555426 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 76539984 ps |
| CPU time | 1.28 seconds |
| Started | Jan 17 01:39:48 PM PST 24 |
| Finished | Jan 17 01:39:52 PM PST 24 |
| Peak memory | 214152 kb |
| Host | smart-a6b46e35-a0dd-448f-8041-a8b590ae4631 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=295555426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.295555426 |
| Directory | /workspace/61.edn_genbits/latest |
| Test location | /workspace/coverage/default/62.edn_err.3932897063 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 20966844 ps |
| CPU time | 1.02 seconds |
| Started | Jan 17 01:39:47 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 221924 kb |
| Host | smart-79dd1aad-c837-43cb-b176-a485f119050f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3932897063 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3932897063 |
| Directory | /workspace/62.edn_err/latest |
| Test location | /workspace/coverage/default/62.edn_genbits.3685635190 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 22490369 ps |
| CPU time | 1.07 seconds |
| Started | Jan 17 01:39:47 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 205168 kb |
| Host | smart-d71a7796-ec72-42e7-b257-8defb9fb1653 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3685635190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3685635190 |
| Directory | /workspace/62.edn_genbits/latest |
| Test location | /workspace/coverage/default/63.edn_err.1523530348 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 43793470 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:39:47 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 215564 kb |
| Host | smart-f34c3c0e-40f1-4568-a5cc-709f3d027cbd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1523530348 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1523530348 |
| Directory | /workspace/63.edn_err/latest |
| Test location | /workspace/coverage/default/63.edn_genbits.1950312783 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 17820774 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:39:48 PM PST 24 |
| Finished | Jan 17 01:39:52 PM PST 24 |
| Peak memory | 205136 kb |
| Host | smart-600b87be-5d2a-4816-b918-3f59f7190d20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1950312783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1950312783 |
| Directory | /workspace/63.edn_genbits/latest |
| Test location | /workspace/coverage/default/64.edn_err.3872884708 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 29133783 ps |
| CPU time | 1.28 seconds |
| Started | Jan 17 01:39:52 PM PST 24 |
| Finished | Jan 17 01:39:54 PM PST 24 |
| Peak memory | 221940 kb |
| Host | smart-8145465c-4640-4690-a31f-c32e9b0bf677 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3872884708 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3872884708 |
| Directory | /workspace/64.edn_err/latest |
| Test location | /workspace/coverage/default/64.edn_genbits.3024882826 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 99179070 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 01:39:47 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 214216 kb |
| Host | smart-02d53e89-dca7-4c5d-a282-8657ca81ecaa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3024882826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3024882826 |
| Directory | /workspace/64.edn_genbits/latest |
| Test location | /workspace/coverage/default/65.edn_err.1338670498 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 43513880 ps |
| CPU time | 0.91 seconds |
| Started | Jan 17 01:39:52 PM PST 24 |
| Finished | Jan 17 01:39:54 PM PST 24 |
| Peak memory | 215728 kb |
| Host | smart-7f6ecf28-9249-450d-afc6-b5f8fdccc886 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1338670498 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1338670498 |
| Directory | /workspace/65.edn_err/latest |
| Test location | /workspace/coverage/default/65.edn_genbits.623508581 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 29973082 ps |
| CPU time | 1.04 seconds |
| Started | Jan 17 01:39:47 PM PST 24 |
| Finished | Jan 17 01:39:51 PM PST 24 |
| Peak memory | 205608 kb |
| Host | smart-2d3dc0a4-d2b6-4478-9c4d-4a9ab946f3dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=623508581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.623508581 |
| Directory | /workspace/65.edn_genbits/latest |
| Test location | /workspace/coverage/default/66.edn_err.3843931283 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 19435189 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 01:39:52 PM PST 24 |
| Finished | Jan 17 01:39:54 PM PST 24 |
| Peak memory | 216252 kb |
| Host | smart-e906283f-32bb-48cc-b179-bb3de6255d8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3843931283 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3843931283 |
| Directory | /workspace/66.edn_err/latest |
| Test location | /workspace/coverage/default/66.edn_genbits.2495037917 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 22762645 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:39:49 PM PST 24 |
| Finished | Jan 17 01:39:54 PM PST 24 |
| Peak memory | 205412 kb |
| Host | smart-7f311900-27bb-46c3-9c14-1b25d93c7629 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2495037917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2495037917 |
| Directory | /workspace/66.edn_genbits/latest |
| Test location | /workspace/coverage/default/67.edn_err.1012765678 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 60351993 ps |
| CPU time | 1.05 seconds |
| Started | Jan 17 01:39:48 PM PST 24 |
| Finished | Jan 17 01:39:53 PM PST 24 |
| Peak memory | 216556 kb |
| Host | smart-168fcc8b-73e1-4d11-945a-9764245f863f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1012765678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1012765678 |
| Directory | /workspace/67.edn_err/latest |
| Test location | /workspace/coverage/default/67.edn_genbits.3921747450 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 121473958 ps |
| CPU time | 1.06 seconds |
| Started | Jan 17 01:39:52 PM PST 24 |
| Finished | Jan 17 01:39:54 PM PST 24 |
| Peak memory | 214180 kb |
| Host | smart-b27a0a09-cc18-41d3-a212-8b63f095dc2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3921747450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.3921747450 |
| Directory | /workspace/67.edn_genbits/latest |
| Test location | /workspace/coverage/default/68.edn_err.2558777807 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 29523642 ps |
| CPU time | 0.87 seconds |
| Started | Jan 17 01:39:49 PM PST 24 |
| Finished | Jan 17 01:39:53 PM PST 24 |
| Peak memory | 215512 kb |
| Host | smart-18d15fd4-e398-4c70-909b-38d8b9047c0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2558777807 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2558777807 |
| Directory | /workspace/68.edn_err/latest |
| Test location | /workspace/coverage/default/68.edn_genbits.1320433091 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 16028947 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:39:48 PM PST 24 |
| Finished | Jan 17 01:39:53 PM PST 24 |
| Peak memory | 205272 kb |
| Host | smart-216ec61d-8dc9-4106-8f0b-209ddfe3a3b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1320433091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1320433091 |
| Directory | /workspace/68.edn_genbits/latest |
| Test location | /workspace/coverage/default/69.edn_err.3996118096 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 24550974 ps |
| CPU time | 1.14 seconds |
| Started | Jan 17 01:39:48 PM PST 24 |
| Finished | Jan 17 01:39:53 PM PST 24 |
| Peak memory | 216016 kb |
| Host | smart-d36d8f59-6824-46be-878f-45f8cbbc774c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3996118096 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3996118096 |
| Directory | /workspace/69.edn_err/latest |
| Test location | /workspace/coverage/default/69.edn_genbits.3916696671 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 36618875 ps |
| CPU time | 1.58 seconds |
| Started | Jan 17 01:39:48 PM PST 24 |
| Finished | Jan 17 01:39:54 PM PST 24 |
| Peak memory | 214144 kb |
| Host | smart-19256493-bd64-4f39-9f96-8eb4b67f61b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3916696671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3916696671 |
| Directory | /workspace/69.edn_genbits/latest |
| Test location | /workspace/coverage/default/7.edn_alert.1932133935 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 131237239 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 01:36:25 PM PST 24 |
| Finished | Jan 17 01:36:28 PM PST 24 |
| Peak memory | 205912 kb |
| Host | smart-64764f13-689a-41fc-bd32-7bff6eeeacdb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1932133935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1932133935 |
| Directory | /workspace/7.edn_alert/latest |
| Test location | /workspace/coverage/default/7.edn_alert_test.3253671968 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 30756753 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 01:36:28 PM PST 24 |
| Finished | Jan 17 01:36:31 PM PST 24 |
| Peak memory | 205108 kb |
| Host | smart-5a6da10f-e6b4-44da-9afb-263e1730f90b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253671968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.3253671968 |
| Directory | /workspace/7.edn_alert_test/latest |
| Test location | /workspace/coverage/default/7.edn_disable.4290626833 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 17364944 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:36:27 PM PST 24 |
| Finished | Jan 17 01:36:31 PM PST 24 |
| Peak memory | 214584 kb |
| Host | smart-86deb9b5-5be7-4b6d-a58b-c8a9f9ed8ff6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290626833 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.4290626833 |
| Directory | /workspace/7.edn_disable/latest |
| Test location | /workspace/coverage/default/7.edn_disable_auto_req_mode.1613316411 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 18081681 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:36:21 PM PST 24 |
| Finished | Jan 17 01:36:23 PM PST 24 |
| Peak memory | 214408 kb |
| Host | smart-95486bdc-6c60-4557-a8d7-ee2cbbaa3091 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613316411 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di sable_auto_req_mode.1613316411 |
| Directory | /workspace/7.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/7.edn_err.3534094881 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 24632218 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:36:20 PM PST 24 |
| Finished | Jan 17 01:36:22 PM PST 24 |
| Peak memory | 216048 kb |
| Host | smart-be0458db-115c-453c-a2d7-caa3490e054f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3534094881 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3534094881 |
| Directory | /workspace/7.edn_err/latest |
| Test location | /workspace/coverage/default/7.edn_genbits.2059024736 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 29632912 ps |
| CPU time | 1.38 seconds |
| Started | Jan 17 01:36:23 PM PST 24 |
| Finished | Jan 17 01:36:25 PM PST 24 |
| Peak memory | 214244 kb |
| Host | smart-13ebe74c-c9a3-4bc4-90f5-5196cce6e26f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2059024736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2059024736 |
| Directory | /workspace/7.edn_genbits/latest |
| Test location | /workspace/coverage/default/7.edn_intr.2859525151 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 26802233 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 01:36:20 PM PST 24 |
| Finished | Jan 17 01:36:21 PM PST 24 |
| Peak memory | 222016 kb |
| Host | smart-5cfaa08a-fddf-4781-ba7b-13625c78fde1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2859525151 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2859525151 |
| Directory | /workspace/7.edn_intr/latest |
| Test location | /workspace/coverage/default/7.edn_smoke.1214789556 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 13587770 ps |
| CPU time | 0.91 seconds |
| Started | Jan 17 01:36:29 PM PST 24 |
| Finished | Jan 17 01:36:31 PM PST 24 |
| Peak memory | 204852 kb |
| Host | smart-929323b6-05f4-4864-aa02-802e8325c730 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1214789556 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1214789556 |
| Directory | /workspace/7.edn_smoke/latest |
| Test location | /workspace/coverage/default/7.edn_stress_all.3887670762 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 190319074 ps |
| CPU time | 1.75 seconds |
| Started | Jan 17 01:36:28 PM PST 24 |
| Finished | Jan 17 01:36:32 PM PST 24 |
| Peak memory | 205480 kb |
| Host | smart-58dfa94e-acd9-4ff6-aa96-65fd6e0d6295 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887670762 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.3887670762 |
| Directory | /workspace/7.edn_stress_all/latest |
| Test location | /workspace/coverage/default/7.edn_stress_all_with_rand_reset.533642607 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 701017224989 ps |
| CPU time | 2189.84 seconds |
| Started | Jan 17 01:36:26 PM PST 24 |
| Finished | Jan 17 02:12:58 PM PST 24 |
| Peak memory | 224416 kb |
| Host | smart-cf44295e-29b9-45f2-ab6b-1b543d68221e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533642607 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.533642607 |
| Directory | /workspace/7.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/70.edn_err.3405789378 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 30323590 ps |
| CPU time | 0.93 seconds |
| Started | Jan 17 01:39:59 PM PST 24 |
| Finished | Jan 17 01:40:00 PM PST 24 |
| Peak memory | 215780 kb |
| Host | smart-3d878791-907b-4575-9dc3-fd40828837d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3405789378 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3405789378 |
| Directory | /workspace/70.edn_err/latest |
| Test location | /workspace/coverage/default/70.edn_genbits.1238203402 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 51491828 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 01:39:57 PM PST 24 |
| Finished | Jan 17 01:39:59 PM PST 24 |
| Peak memory | 205484 kb |
| Host | smart-9a37beac-a42d-4aaf-8370-ec0964b638b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1238203402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1238203402 |
| Directory | /workspace/70.edn_genbits/latest |
| Test location | /workspace/coverage/default/71.edn_err.2162821742 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 37019810 ps |
| CPU time | 0.81 seconds |
| Started | Jan 17 01:39:57 PM PST 24 |
| Finished | Jan 17 01:39:59 PM PST 24 |
| Peak memory | 215360 kb |
| Host | smart-7dce8f2b-06f7-488b-bbdc-d6bc1c4c551c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2162821742 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2162821742 |
| Directory | /workspace/71.edn_err/latest |
| Test location | /workspace/coverage/default/71.edn_genbits.2896067055 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 66862316 ps |
| CPU time | 1.02 seconds |
| Started | Jan 17 01:39:55 PM PST 24 |
| Finished | Jan 17 01:39:57 PM PST 24 |
| Peak memory | 214124 kb |
| Host | smart-1ebf3ca1-89d7-4a26-b7e1-42b9e611c949 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896067055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2896067055 |
| Directory | /workspace/71.edn_genbits/latest |
| Test location | /workspace/coverage/default/72.edn_err.411977001 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 23524634 ps |
| CPU time | 0.89 seconds |
| Started | Jan 17 01:39:59 PM PST 24 |
| Finished | Jan 17 01:40:00 PM PST 24 |
| Peak memory | 215624 kb |
| Host | smart-6e630c6f-8768-4b9b-82c8-413c025d3054 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=411977001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.411977001 |
| Directory | /workspace/72.edn_err/latest |
| Test location | /workspace/coverage/default/72.edn_genbits.1855481500 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 22977391 ps |
| CPU time | 1.17 seconds |
| Started | Jan 17 01:39:56 PM PST 24 |
| Finished | Jan 17 01:39:58 PM PST 24 |
| Peak memory | 214168 kb |
| Host | smart-26ec8166-2e51-48c8-92ca-62f3ad150f84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1855481500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1855481500 |
| Directory | /workspace/72.edn_genbits/latest |
| Test location | /workspace/coverage/default/73.edn_err.259751797 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 46716503 ps |
| CPU time | 1.05 seconds |
| Started | Jan 17 01:40:00 PM PST 24 |
| Finished | Jan 17 01:40:02 PM PST 24 |
| Peak memory | 222200 kb |
| Host | smart-39e35a29-1d74-4cc6-874e-029999c5ff86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=259751797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.259751797 |
| Directory | /workspace/73.edn_err/latest |
| Test location | /workspace/coverage/default/73.edn_genbits.437762834 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 195418725 ps |
| CPU time | 2.94 seconds |
| Started | Jan 17 01:39:56 PM PST 24 |
| Finished | Jan 17 01:39:59 PM PST 24 |
| Peak memory | 214032 kb |
| Host | smart-6c95c639-2c3f-45ed-ae90-2bc8b47c67e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=437762834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.437762834 |
| Directory | /workspace/73.edn_genbits/latest |
| Test location | /workspace/coverage/default/74.edn_err.3031616058 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 19217346 ps |
| CPU time | 1.05 seconds |
| Started | Jan 17 01:40:07 PM PST 24 |
| Finished | Jan 17 01:40:09 PM PST 24 |
| Peak memory | 215636 kb |
| Host | smart-07442e5c-1165-44ab-9fe8-33c9d6e78029 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3031616058 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.3031616058 |
| Directory | /workspace/74.edn_err/latest |
| Test location | /workspace/coverage/default/74.edn_genbits.3654307437 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 29529255 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:39:58 PM PST 24 |
| Finished | Jan 17 01:39:59 PM PST 24 |
| Peak memory | 205348 kb |
| Host | smart-dac188a9-e8de-4661-ad35-f43c8cb0a960 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3654307437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.3654307437 |
| Directory | /workspace/74.edn_genbits/latest |
| Test location | /workspace/coverage/default/75.edn_err.1635817643 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 20347080 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 01:40:06 PM PST 24 |
| Finished | Jan 17 01:40:08 PM PST 24 |
| Peak memory | 216008 kb |
| Host | smart-b5333112-ca71-4e00-a170-4e0444c1d5e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1635817643 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.1635817643 |
| Directory | /workspace/75.edn_err/latest |
| Test location | /workspace/coverage/default/75.edn_genbits.3104128880 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 98617180 ps |
| CPU time | 2.02 seconds |
| Started | Jan 17 01:40:07 PM PST 24 |
| Finished | Jan 17 01:40:10 PM PST 24 |
| Peak memory | 214172 kb |
| Host | smart-b944d156-f205-4249-911f-0f4de68fd1ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3104128880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3104128880 |
| Directory | /workspace/75.edn_genbits/latest |
| Test location | /workspace/coverage/default/76.edn_err.3678233509 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 32517863 ps |
| CPU time | 1 seconds |
| Started | Jan 17 01:40:08 PM PST 24 |
| Finished | Jan 17 01:40:10 PM PST 24 |
| Peak memory | 221392 kb |
| Host | smart-fe5cf176-8fc1-43b7-b1da-0baaac0be172 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3678233509 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3678233509 |
| Directory | /workspace/76.edn_err/latest |
| Test location | /workspace/coverage/default/76.edn_genbits.2658116513 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 120097067 ps |
| CPU time | 2.71 seconds |
| Started | Jan 17 01:40:09 PM PST 24 |
| Finished | Jan 17 01:40:13 PM PST 24 |
| Peak memory | 214216 kb |
| Host | smart-969e21b0-781a-4a89-b4fc-1f2a6bddfe78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2658116513 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2658116513 |
| Directory | /workspace/76.edn_genbits/latest |
| Test location | /workspace/coverage/default/77.edn_err.2895141480 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 19820035 ps |
| CPU time | 1.14 seconds |
| Started | Jan 17 01:40:13 PM PST 24 |
| Finished | Jan 17 01:40:16 PM PST 24 |
| Peak memory | 221972 kb |
| Host | smart-7f497f88-45ce-42a2-a571-b90a6fc51f29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2895141480 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2895141480 |
| Directory | /workspace/77.edn_err/latest |
| Test location | /workspace/coverage/default/78.edn_err.306843453 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 80627672 ps |
| CPU time | 1.04 seconds |
| Started | Jan 17 01:40:07 PM PST 24 |
| Finished | Jan 17 01:40:09 PM PST 24 |
| Peak memory | 216824 kb |
| Host | smart-efc7ff0e-4f0f-4e17-9aaa-0458d1308d73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=306843453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.306843453 |
| Directory | /workspace/78.edn_err/latest |
| Test location | /workspace/coverage/default/78.edn_genbits.1683334041 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 21554373 ps |
| CPU time | 1.15 seconds |
| Started | Jan 17 01:40:06 PM PST 24 |
| Finished | Jan 17 01:40:07 PM PST 24 |
| Peak memory | 205520 kb |
| Host | smart-dfdb618c-b2d4-4c72-81ed-4aa83966cb89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1683334041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1683334041 |
| Directory | /workspace/78.edn_genbits/latest |
| Test location | /workspace/coverage/default/79.edn_err.2493940296 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 35432425 ps |
| CPU time | 1.33 seconds |
| Started | Jan 17 01:40:17 PM PST 24 |
| Finished | Jan 17 01:40:24 PM PST 24 |
| Peak memory | 217264 kb |
| Host | smart-3b58b867-1bd7-433b-b24c-54002c569542 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2493940296 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2493940296 |
| Directory | /workspace/79.edn_err/latest |
| Test location | /workspace/coverage/default/79.edn_genbits.3523142191 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 47744559 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 01:40:20 PM PST 24 |
| Finished | Jan 17 01:40:24 PM PST 24 |
| Peak memory | 205460 kb |
| Host | smart-30c255d2-790d-467f-81a6-a526f4b09e78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3523142191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3523142191 |
| Directory | /workspace/79.edn_genbits/latest |
| Test location | /workspace/coverage/default/8.edn_alert_test.2813553359 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 143214030 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:36:37 PM PST 24 |
| Finished | Jan 17 01:36:39 PM PST 24 |
| Peak memory | 204440 kb |
| Host | smart-cfd97eb8-edba-468f-b195-b5e0045985d1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813553359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2813553359 |
| Directory | /workspace/8.edn_alert_test/latest |
| Test location | /workspace/coverage/default/8.edn_disable.3242622273 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 11044117 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:36:36 PM PST 24 |
| Finished | Jan 17 01:36:37 PM PST 24 |
| Peak memory | 214352 kb |
| Host | smart-ce3f675f-1b29-479d-bbc6-7e1b23bf1bcc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242622273 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3242622273 |
| Directory | /workspace/8.edn_disable/latest |
| Test location | /workspace/coverage/default/8.edn_disable_auto_req_mode.2389152529 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 21609374 ps |
| CPU time | 1.11 seconds |
| Started | Jan 17 01:36:39 PM PST 24 |
| Finished | Jan 17 01:36:41 PM PST 24 |
| Peak memory | 214764 kb |
| Host | smart-3f39d9fa-634a-43d2-8806-b47c7d6f1468 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389152529 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di sable_auto_req_mode.2389152529 |
| Directory | /workspace/8.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/8.edn_err.2095439891 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 26329832 ps |
| CPU time | 0.81 seconds |
| Started | Jan 17 01:36:36 PM PST 24 |
| Finished | Jan 17 01:36:37 PM PST 24 |
| Peak memory | 215444 kb |
| Host | smart-0f031eec-40d8-4cf2-a49d-ea94f7f319c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2095439891 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2095439891 |
| Directory | /workspace/8.edn_err/latest |
| Test location | /workspace/coverage/default/8.edn_genbits.2487778510 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 68954102 ps |
| CPU time | 2.62 seconds |
| Started | Jan 17 01:36:28 PM PST 24 |
| Finished | Jan 17 01:36:33 PM PST 24 |
| Peak memory | 214192 kb |
| Host | smart-86113db6-c4f0-4da7-9a7e-c3656b1b4a0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2487778510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2487778510 |
| Directory | /workspace/8.edn_genbits/latest |
| Test location | /workspace/coverage/default/8.edn_intr.3795210865 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 18865232 ps |
| CPU time | 1.17 seconds |
| Started | Jan 17 01:36:28 PM PST 24 |
| Finished | Jan 17 01:36:31 PM PST 24 |
| Peak memory | 221940 kb |
| Host | smart-962a909a-bb53-4fe6-a349-38f2b32f6b44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3795210865 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3795210865 |
| Directory | /workspace/8.edn_intr/latest |
| Test location | /workspace/coverage/default/8.edn_regwen.1829310854 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 15612690 ps |
| CPU time | 0.92 seconds |
| Started | Jan 17 01:36:27 PM PST 24 |
| Finished | Jan 17 01:36:31 PM PST 24 |
| Peak memory | 204996 kb |
| Host | smart-4dc060f9-7c2b-483f-ad4b-aac4cea2c4b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1829310854 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1829310854 |
| Directory | /workspace/8.edn_regwen/latest |
| Test location | /workspace/coverage/default/8.edn_smoke.2574530253 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 13483059 ps |
| CPU time | 0.9 seconds |
| Started | Jan 17 01:36:22 PM PST 24 |
| Finished | Jan 17 01:36:23 PM PST 24 |
| Peak memory | 204864 kb |
| Host | smart-3cf742f3-078a-4cdd-8ee0-1ba02e65e7ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2574530253 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2574530253 |
| Directory | /workspace/8.edn_smoke/latest |
| Test location | /workspace/coverage/default/8.edn_stress_all.3960641050 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 426735241 ps |
| CPU time | 2.73 seconds |
| Started | Jan 17 01:36:28 PM PST 24 |
| Finished | Jan 17 01:36:33 PM PST 24 |
| Peak memory | 205940 kb |
| Host | smart-d3e4e6c5-4ebf-4dea-92f2-28501a87f5c5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960641050 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3960641050 |
| Directory | /workspace/8.edn_stress_all/latest |
| Test location | /workspace/coverage/default/8.edn_stress_all_with_rand_reset.796727100 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 68931509889 ps |
| CPU time | 427.89 seconds |
| Started | Jan 17 01:36:29 PM PST 24 |
| Finished | Jan 17 01:43:38 PM PST 24 |
| Peak memory | 214496 kb |
| Host | smart-75f0db6b-6481-4d1b-b466-683f0049bbda |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796727100 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.796727100 |
| Directory | /workspace/8.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/80.edn_err.3874139432 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 43870805 ps |
| CPU time | 0.82 seconds |
| Started | Jan 17 01:40:18 PM PST 24 |
| Finished | Jan 17 01:40:24 PM PST 24 |
| Peak memory | 215832 kb |
| Host | smart-a3294382-8fc9-4e11-8688-204cd82bb26e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3874139432 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3874139432 |
| Directory | /workspace/80.edn_err/latest |
| Test location | /workspace/coverage/default/80.edn_genbits.1407946306 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 19804838 ps |
| CPU time | 1.03 seconds |
| Started | Jan 17 01:40:16 PM PST 24 |
| Finished | Jan 17 01:40:24 PM PST 24 |
| Peak memory | 205120 kb |
| Host | smart-6011634e-6fac-44fb-9ce9-3d51f8995d6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1407946306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1407946306 |
| Directory | /workspace/80.edn_genbits/latest |
| Test location | /workspace/coverage/default/81.edn_err.3553228612 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 62053616 ps |
| CPU time | 1.11 seconds |
| Started | Jan 17 01:40:16 PM PST 24 |
| Finished | Jan 17 01:40:24 PM PST 24 |
| Peak memory | 216988 kb |
| Host | smart-639dde38-efdd-4609-b509-f34151594a46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3553228612 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3553228612 |
| Directory | /workspace/81.edn_err/latest |
| Test location | /workspace/coverage/default/81.edn_genbits.2526853553 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 205527178 ps |
| CPU time | 1.73 seconds |
| Started | Jan 17 01:40:17 PM PST 24 |
| Finished | Jan 17 01:40:25 PM PST 24 |
| Peak memory | 214100 kb |
| Host | smart-7d200aff-cae8-4b51-af76-6727568ee277 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2526853553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2526853553 |
| Directory | /workspace/81.edn_genbits/latest |
| Test location | /workspace/coverage/default/82.edn_err.878465088 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 26427395 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:40:16 PM PST 24 |
| Finished | Jan 17 01:40:24 PM PST 24 |
| Peak memory | 215248 kb |
| Host | smart-071e438f-0653-4043-8a77-d9d7a278551d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=878465088 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.878465088 |
| Directory | /workspace/82.edn_err/latest |
| Test location | /workspace/coverage/default/82.edn_genbits.1147285453 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 30902241 ps |
| CPU time | 0.98 seconds |
| Started | Jan 17 01:40:15 PM PST 24 |
| Finished | Jan 17 01:40:16 PM PST 24 |
| Peak memory | 205400 kb |
| Host | smart-5ab6b53d-fa8a-47f4-91aa-ea558c858113 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1147285453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1147285453 |
| Directory | /workspace/82.edn_genbits/latest |
| Test location | /workspace/coverage/default/83.edn_err.340474512 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 20910633 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:40:24 PM PST 24 |
| Finished | Jan 17 01:40:26 PM PST 24 |
| Peak memory | 221936 kb |
| Host | smart-f3c7a514-bb6f-4cf9-84bf-77a69f9368f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=340474512 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.340474512 |
| Directory | /workspace/83.edn_err/latest |
| Test location | /workspace/coverage/default/83.edn_genbits.3309956468 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 70597409 ps |
| CPU time | 2.06 seconds |
| Started | Jan 17 01:40:20 PM PST 24 |
| Finished | Jan 17 01:40:25 PM PST 24 |
| Peak memory | 214156 kb |
| Host | smart-8daaa4ab-009b-44c6-b7c1-b6265b92102e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3309956468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3309956468 |
| Directory | /workspace/83.edn_genbits/latest |
| Test location | /workspace/coverage/default/84.edn_err.826314018 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 23899750 ps |
| CPU time | 1.12 seconds |
| Started | Jan 17 01:40:27 PM PST 24 |
| Finished | Jan 17 01:40:29 PM PST 24 |
| Peak memory | 216048 kb |
| Host | smart-6bb5d508-13a2-475f-bc96-913d685bf33e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=826314018 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.826314018 |
| Directory | /workspace/84.edn_err/latest |
| Test location | /workspace/coverage/default/84.edn_genbits.2089631384 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 93856817 ps |
| CPU time | 0.91 seconds |
| Started | Jan 17 01:40:23 PM PST 24 |
| Finished | Jan 17 01:40:26 PM PST 24 |
| Peak memory | 204708 kb |
| Host | smart-1a2954b7-3ccc-4909-8a1b-0b5a79660ac8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2089631384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2089631384 |
| Directory | /workspace/84.edn_genbits/latest |
| Test location | /workspace/coverage/default/85.edn_err.2851040550 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 18138047 ps |
| CPU time | 1.12 seconds |
| Started | Jan 17 01:40:19 PM PST 24 |
| Finished | Jan 17 01:40:24 PM PST 24 |
| Peak memory | 221924 kb |
| Host | smart-6fd69d69-7c28-4cbd-932c-31f3ebfc8c1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2851040550 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2851040550 |
| Directory | /workspace/85.edn_err/latest |
| Test location | /workspace/coverage/default/85.edn_genbits.1664605178 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 80627159 ps |
| CPU time | 1.11 seconds |
| Started | Jan 17 01:40:28 PM PST 24 |
| Finished | Jan 17 01:40:30 PM PST 24 |
| Peak memory | 214180 kb |
| Host | smart-66aa5ea6-873c-4de1-947d-356248c3dd13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1664605178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1664605178 |
| Directory | /workspace/85.edn_genbits/latest |
| Test location | /workspace/coverage/default/86.edn_err.2556284987 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 32872625 ps |
| CPU time | 1.33 seconds |
| Started | Jan 17 01:40:23 PM PST 24 |
| Finished | Jan 17 01:40:26 PM PST 24 |
| Peak memory | 221572 kb |
| Host | smart-37636616-13ef-4ce2-902a-6398e67928b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2556284987 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2556284987 |
| Directory | /workspace/86.edn_err/latest |
| Test location | /workspace/coverage/default/86.edn_genbits.1304809518 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 67783804 ps |
| CPU time | 1.02 seconds |
| Started | Jan 17 01:40:18 PM PST 24 |
| Finished | Jan 17 01:40:24 PM PST 24 |
| Peak memory | 214168 kb |
| Host | smart-f23216ab-2489-4bda-a717-07a32da9fa79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1304809518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1304809518 |
| Directory | /workspace/86.edn_genbits/latest |
| Test location | /workspace/coverage/default/87.edn_err.2925473008 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 187097291 ps |
| CPU time | 1.26 seconds |
| Started | Jan 17 01:40:20 PM PST 24 |
| Finished | Jan 17 01:40:24 PM PST 24 |
| Peak memory | 221964 kb |
| Host | smart-182884ba-2b75-49b4-8325-723d6f52c4e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2925473008 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2925473008 |
| Directory | /workspace/87.edn_err/latest |
| Test location | /workspace/coverage/default/87.edn_genbits.1155309495 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 59760039 ps |
| CPU time | 1.34 seconds |
| Started | Jan 17 01:40:22 PM PST 24 |
| Finished | Jan 17 01:40:25 PM PST 24 |
| Peak memory | 205740 kb |
| Host | smart-da77c745-a3c8-48e4-8831-ceb32732e9f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1155309495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1155309495 |
| Directory | /workspace/87.edn_genbits/latest |
| Test location | /workspace/coverage/default/88.edn_err.884126453 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 20363063 ps |
| CPU time | 1.14 seconds |
| Started | Jan 17 01:40:21 PM PST 24 |
| Finished | Jan 17 01:40:24 PM PST 24 |
| Peak memory | 221852 kb |
| Host | smart-84fece45-bdce-44ca-8f9c-d3e7130adf7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=884126453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.884126453 |
| Directory | /workspace/88.edn_err/latest |
| Test location | /workspace/coverage/default/88.edn_genbits.2495852920 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 46660245 ps |
| CPU time | 1.13 seconds |
| Started | Jan 17 01:40:18 PM PST 24 |
| Finished | Jan 17 01:40:24 PM PST 24 |
| Peak memory | 205232 kb |
| Host | smart-f33869ae-bfb1-4e46-b4c2-f8aaf33e756e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2495852920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2495852920 |
| Directory | /workspace/88.edn_genbits/latest |
| Test location | /workspace/coverage/default/89.edn_err.2223485908 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 22731146 ps |
| CPU time | 1.24 seconds |
| Started | Jan 17 01:40:28 PM PST 24 |
| Finished | Jan 17 01:40:30 PM PST 24 |
| Peak memory | 222088 kb |
| Host | smart-e423c4e5-356e-4916-bacc-fbfafad827a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223485908 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2223485908 |
| Directory | /workspace/89.edn_err/latest |
| Test location | /workspace/coverage/default/89.edn_genbits.2221287060 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 27333328 ps |
| CPU time | 1.07 seconds |
| Started | Jan 17 01:40:20 PM PST 24 |
| Finished | Jan 17 01:40:24 PM PST 24 |
| Peak memory | 205200 kb |
| Host | smart-4fd0e22c-1a69-4861-93d2-19ad8f8fef8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2221287060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2221287060 |
| Directory | /workspace/89.edn_genbits/latest |
| Test location | /workspace/coverage/default/9.edn_alert.2304553397 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 43363177 ps |
| CPU time | 0.94 seconds |
| Started | Jan 17 01:36:44 PM PST 24 |
| Finished | Jan 17 01:36:51 PM PST 24 |
| Peak memory | 205664 kb |
| Host | smart-778ba7d5-c158-4eda-aaf7-b18294b55e7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2304553397 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2304553397 |
| Directory | /workspace/9.edn_alert/latest |
| Test location | /workspace/coverage/default/9.edn_alert_test.1913595081 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 11934135 ps |
| CPU time | 0.86 seconds |
| Started | Jan 17 01:36:47 PM PST 24 |
| Finished | Jan 17 01:36:51 PM PST 24 |
| Peak memory | 204440 kb |
| Host | smart-d6ef3062-0e02-4285-a848-c697b149a878 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913595081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1913595081 |
| Directory | /workspace/9.edn_alert_test/latest |
| Test location | /workspace/coverage/default/9.edn_disable.470564720 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 73667539 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:36:44 PM PST 24 |
| Finished | Jan 17 01:36:51 PM PST 24 |
| Peak memory | 214380 kb |
| Host | smart-638d03d0-a7a4-4c1c-93aa-352b0773800f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470564720 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.470564720 |
| Directory | /workspace/9.edn_disable/latest |
| Test location | /workspace/coverage/default/9.edn_disable_auto_req_mode.630027718 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 29409231 ps |
| CPU time | 1.02 seconds |
| Started | Jan 17 01:36:45 PM PST 24 |
| Finished | Jan 17 01:36:51 PM PST 24 |
| Peak memory | 214412 kb |
| Host | smart-7beea3fd-a695-499c-b9c8-00f513900599 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630027718 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_dis able_auto_req_mode.630027718 |
| Directory | /workspace/9.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/9.edn_err.3328038378 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 28251990 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:36:47 PM PST 24 |
| Finished | Jan 17 01:36:51 PM PST 24 |
| Peak memory | 215512 kb |
| Host | smart-c6f137d7-1577-4bc5-b2e7-4ec3a34944c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3328038378 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3328038378 |
| Directory | /workspace/9.edn_err/latest |
| Test location | /workspace/coverage/default/9.edn_genbits.1273416888 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 145636801 ps |
| CPU time | 2.31 seconds |
| Started | Jan 17 01:36:45 PM PST 24 |
| Finished | Jan 17 01:36:52 PM PST 24 |
| Peak memory | 214240 kb |
| Host | smart-dfd000af-21e0-4e36-bba6-4a84a1e7bea7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1273416888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1273416888 |
| Directory | /workspace/9.edn_genbits/latest |
| Test location | /workspace/coverage/default/9.edn_intr.1148207764 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 30198506 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:36:44 PM PST 24 |
| Finished | Jan 17 01:36:51 PM PST 24 |
| Peak memory | 214428 kb |
| Host | smart-175ed599-ab58-4d35-a037-5040da34b0a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1148207764 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1148207764 |
| Directory | /workspace/9.edn_intr/latest |
| Test location | /workspace/coverage/default/9.edn_regwen.1029227820 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 40753774 ps |
| CPU time | 0.9 seconds |
| Started | Jan 17 01:36:44 PM PST 24 |
| Finished | Jan 17 01:36:51 PM PST 24 |
| Peak memory | 204792 kb |
| Host | smart-e8dfcdd3-a7f2-49ff-bd9b-2a18fde12ed0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1029227820 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1029227820 |
| Directory | /workspace/9.edn_regwen/latest |
| Test location | /workspace/coverage/default/9.edn_smoke.2424191930 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 17920077 ps |
| CPU time | 0.84 seconds |
| Started | Jan 17 01:36:47 PM PST 24 |
| Finished | Jan 17 01:36:51 PM PST 24 |
| Peak memory | 204780 kb |
| Host | smart-bc17ad5c-33ac-45ca-bbc7-e52d947f3490 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2424191930 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.2424191930 |
| Directory | /workspace/9.edn_smoke/latest |
| Test location | /workspace/coverage/default/9.edn_stress_all.3368727289 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 172314667 ps |
| CPU time | 3.79 seconds |
| Started | Jan 17 01:36:47 PM PST 24 |
| Finished | Jan 17 01:36:54 PM PST 24 |
| Peak memory | 206072 kb |
| Host | smart-b75d350c-17be-475f-aa64-4031d0ae672d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368727289 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3368727289 |
| Directory | /workspace/9.edn_stress_all/latest |
| Test location | /workspace/coverage/default/9.edn_stress_all_with_rand_reset.982248699 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 3153451543 ps |
| CPU time | 66.27 seconds |
| Started | Jan 17 01:36:45 PM PST 24 |
| Finished | Jan 17 01:37:56 PM PST 24 |
| Peak memory | 214548 kb |
| Host | smart-4df9cad2-bae6-4d34-bbb8-3389f7d6e317 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982248699 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.982248699 |
| Directory | /workspace/9.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/90.edn_err.2595217856 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 28837335 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:40:20 PM PST 24 |
| Finished | Jan 17 01:40:24 PM PST 24 |
| Peak memory | 221892 kb |
| Host | smart-c0812665-c16b-4574-9b96-1faef3b02589 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2595217856 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2595217856 |
| Directory | /workspace/90.edn_err/latest |
| Test location | /workspace/coverage/default/90.edn_genbits.1639093474 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 49548553 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:40:22 PM PST 24 |
| Finished | Jan 17 01:40:24 PM PST 24 |
| Peak memory | 205404 kb |
| Host | smart-baf27efa-a74f-4d17-8141-4ba283c84f1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1639093474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1639093474 |
| Directory | /workspace/90.edn_genbits/latest |
| Test location | /workspace/coverage/default/91.edn_err.3396552065 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 21362844 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:40:19 PM PST 24 |
| Finished | Jan 17 01:40:24 PM PST 24 |
| Peak memory | 221496 kb |
| Host | smart-c3a18842-15f5-46e8-a452-df041fed24e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3396552065 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3396552065 |
| Directory | /workspace/91.edn_err/latest |
| Test location | /workspace/coverage/default/91.edn_genbits.3683965246 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 70970679 ps |
| CPU time | 0.95 seconds |
| Started | Jan 17 01:40:23 PM PST 24 |
| Finished | Jan 17 01:40:25 PM PST 24 |
| Peak memory | 205216 kb |
| Host | smart-fc678e56-44d6-4acb-beaf-23af35abed70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3683965246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3683965246 |
| Directory | /workspace/91.edn_genbits/latest |
| Test location | /workspace/coverage/default/92.edn_err.1671605697 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 58412634 ps |
| CPU time | 1.24 seconds |
| Started | Jan 17 01:40:20 PM PST 24 |
| Finished | Jan 17 01:40:24 PM PST 24 |
| Peak memory | 217020 kb |
| Host | smart-7d7d1695-5957-49b3-a713-e100485f546e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1671605697 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1671605697 |
| Directory | /workspace/92.edn_err/latest |
| Test location | /workspace/coverage/default/92.edn_genbits.1735177309 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 19658386 ps |
| CPU time | 0.97 seconds |
| Started | Jan 17 01:40:23 PM PST 24 |
| Finished | Jan 17 01:40:26 PM PST 24 |
| Peak memory | 204944 kb |
| Host | smart-8e09bf07-1588-4088-b40e-df12015f43c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1735177309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1735177309 |
| Directory | /workspace/92.edn_genbits/latest |
| Test location | /workspace/coverage/default/93.edn_err.492369443 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 18420190 ps |
| CPU time | 1.13 seconds |
| Started | Jan 17 01:40:21 PM PST 24 |
| Finished | Jan 17 01:40:24 PM PST 24 |
| Peak memory | 221860 kb |
| Host | smart-27a94163-6b83-4c11-a257-34890bf354f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=492369443 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.492369443 |
| Directory | /workspace/93.edn_err/latest |
| Test location | /workspace/coverage/default/93.edn_genbits.4084786105 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 57097119 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:40:20 PM PST 24 |
| Finished | Jan 17 01:40:24 PM PST 24 |
| Peak memory | 205112 kb |
| Host | smart-f8c53b8e-cdde-42e3-a342-67a09d0aab5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4084786105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.4084786105 |
| Directory | /workspace/93.edn_genbits/latest |
| Test location | /workspace/coverage/default/94.edn_err.2903297219 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 19750258 ps |
| CPU time | 1.14 seconds |
| Started | Jan 17 01:40:26 PM PST 24 |
| Finished | Jan 17 01:40:28 PM PST 24 |
| Peak memory | 221864 kb |
| Host | smart-1525fefe-70e1-4669-bdf1-01fcc5b2c06d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2903297219 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2903297219 |
| Directory | /workspace/94.edn_err/latest |
| Test location | /workspace/coverage/default/94.edn_genbits.785910675 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 13724025 ps |
| CPU time | 0.96 seconds |
| Started | Jan 17 01:40:20 PM PST 24 |
| Finished | Jan 17 01:40:24 PM PST 24 |
| Peak memory | 204768 kb |
| Host | smart-20b709c3-49b7-49f6-9bc7-f9a894f3889c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=785910675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.785910675 |
| Directory | /workspace/94.edn_genbits/latest |
| Test location | /workspace/coverage/default/95.edn_err.3527037330 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 21790177 ps |
| CPU time | 0.85 seconds |
| Started | Jan 17 01:40:26 PM PST 24 |
| Finished | Jan 17 01:40:28 PM PST 24 |
| Peak memory | 215408 kb |
| Host | smart-6587bc43-0b82-4ab6-9620-269913a7c688 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3527037330 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3527037330 |
| Directory | /workspace/95.edn_err/latest |
| Test location | /workspace/coverage/default/95.edn_genbits.1430386700 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 18803222 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:40:24 PM PST 24 |
| Finished | Jan 17 01:40:26 PM PST 24 |
| Peak memory | 205572 kb |
| Host | smart-654ded15-8c2d-4a2b-914e-aa14fa13ebaa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1430386700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1430386700 |
| Directory | /workspace/95.edn_genbits/latest |
| Test location | /workspace/coverage/default/96.edn_err.669772567 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 47074225 ps |
| CPU time | 0.83 seconds |
| Started | Jan 17 01:40:23 PM PST 24 |
| Finished | Jan 17 01:40:26 PM PST 24 |
| Peak memory | 215488 kb |
| Host | smart-339454e4-107e-4656-806d-243bdbb2b8e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=669772567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.669772567 |
| Directory | /workspace/96.edn_err/latest |
| Test location | /workspace/coverage/default/96.edn_genbits.1656761700 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 17051175 ps |
| CPU time | 1.12 seconds |
| Started | Jan 17 01:40:26 PM PST 24 |
| Finished | Jan 17 01:40:28 PM PST 24 |
| Peak memory | 205552 kb |
| Host | smart-a45c6501-7b47-4f29-840c-051f8cb914b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1656761700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1656761700 |
| Directory | /workspace/96.edn_genbits/latest |
| Test location | /workspace/coverage/default/97.edn_err.2257860814 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 43232113 ps |
| CPU time | 1.07 seconds |
| Started | Jan 17 01:40:25 PM PST 24 |
| Finished | Jan 17 01:40:27 PM PST 24 |
| Peak memory | 216900 kb |
| Host | smart-488a0e43-c77d-4b85-be18-0a1642b829f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2257860814 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2257860814 |
| Directory | /workspace/97.edn_err/latest |
| Test location | /workspace/coverage/default/97.edn_genbits.28127849 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 26383090 ps |
| CPU time | 1.08 seconds |
| Started | Jan 17 01:40:27 PM PST 24 |
| Finished | Jan 17 01:40:30 PM PST 24 |
| Peak memory | 214240 kb |
| Host | smart-b0fcaa6d-0668-4772-b026-22d4856fafb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=28127849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.28127849 |
| Directory | /workspace/97.edn_genbits/latest |
| Test location | /workspace/coverage/default/98.edn_err.592249573 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 21204934 ps |
| CPU time | 1.06 seconds |
| Started | Jan 17 01:40:26 PM PST 24 |
| Finished | Jan 17 01:40:28 PM PST 24 |
| Peak memory | 221940 kb |
| Host | smart-5384ff76-c54c-4ec0-859b-3723c61aa7ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=592249573 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.592249573 |
| Directory | /workspace/98.edn_err/latest |
| Test location | /workspace/coverage/default/98.edn_genbits.1458865758 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 34074721 ps |
| CPU time | 1.01 seconds |
| Started | Jan 17 01:40:32 PM PST 24 |
| Finished | Jan 17 01:40:33 PM PST 24 |
| Peak memory | 205436 kb |
| Host | smart-aad4747b-5931-4a0e-863d-d1064e8f2e3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1458865758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1458865758 |
| Directory | /workspace/98.edn_genbits/latest |
| Test location | /workspace/coverage/default/99.edn_err.2231923985 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 26054083 ps |
| CPU time | 0.81 seconds |
| Started | Jan 17 01:40:24 PM PST 24 |
| Finished | Jan 17 01:40:26 PM PST 24 |
| Peak memory | 215448 kb |
| Host | smart-3c0a8611-fcf4-409a-87f2-3eaf56df013d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2231923985 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2231923985 |
| Directory | /workspace/99.edn_err/latest |
| Test location | /workspace/coverage/default/99.edn_genbits.2687829861 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 19245726 ps |
| CPU time | 0.99 seconds |
| Started | Jan 17 01:40:25 PM PST 24 |
| Finished | Jan 17 01:40:27 PM PST 24 |
| Peak memory | 205020 kb |
| Host | smart-5a7324b4-1562-4903-99c0-e5ce5856e01d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2687829861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2687829861 |
| Directory | /workspace/99.edn_genbits/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |