| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.00 | 99.02 | 92.31 | 96.74 | 87.34 | 98.48 | 99.77 | 98.34 |
| T766 | /workspace/coverage/default/37.edn_smoke.2183397143 | Jan 21 12:56:13 PM PST 24 | Jan 21 12:56:21 PM PST 24 | 16149679 ps | ||
| T767 | /workspace/coverage/default/74.edn_genbits.1553470925 | Jan 21 12:58:21 PM PST 24 | Jan 21 12:58:23 PM PST 24 | 19657826 ps | ||
| T768 | /workspace/coverage/default/195.edn_genbits.1606685140 | Jan 21 12:59:56 PM PST 24 | Jan 21 12:59:58 PM PST 24 | 52655450 ps | ||
| T769 | /workspace/coverage/default/121.edn_genbits.1023274199 | Jan 21 01:09:35 PM PST 24 | Jan 21 01:09:37 PM PST 24 | 45237019 ps | ||
| T770 | /workspace/coverage/default/15.edn_disable.1918249823 | Jan 21 12:53:37 PM PST 24 | Jan 21 12:53:43 PM PST 24 | 29176160 ps | ||
| T771 | /workspace/coverage/default/22.edn_smoke.2057570993 | Jan 21 12:54:27 PM PST 24 | Jan 21 12:54:29 PM PST 24 | 71631888 ps | ||
| T124 | /workspace/coverage/default/16.edn_disable.2102536035 | Jan 21 12:53:42 PM PST 24 | Jan 21 12:53:46 PM PST 24 | 24129065 ps | ||
| T772 | /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3940083885 | Jan 21 12:56:03 PM PST 24 | Jan 21 01:02:31 PM PST 24 | 30902108200 ps | ||
| T773 | /workspace/coverage/default/32.edn_alert.1695467349 | Jan 21 12:55:38 PM PST 24 | Jan 21 12:55:40 PM PST 24 | 22046616 ps | ||
| T774 | /workspace/coverage/default/26.edn_genbits.1136685816 | Jan 21 01:09:34 PM PST 24 | Jan 21 01:09:36 PM PST 24 | 21783312 ps | ||
| T775 | /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2056404987 | Jan 21 12:53:48 PM PST 24 | Jan 21 12:57:49 PM PST 24 | 18221704908 ps | ||
| T776 | /workspace/coverage/default/17.edn_err.2102001466 | Jan 21 12:53:51 PM PST 24 | Jan 21 12:53:53 PM PST 24 | 63239870 ps | ||
| T777 | /workspace/coverage/default/67.edn_genbits.2344932151 | Jan 21 12:58:12 PM PST 24 | Jan 21 12:58:13 PM PST 24 | 22160005 ps | ||
| T778 | /workspace/coverage/default/35.edn_disable_auto_req_mode.2507849887 | Jan 21 12:56:03 PM PST 24 | Jan 21 12:56:05 PM PST 24 | 30789252 ps | ||
| T779 | /workspace/coverage/default/30.edn_alert.2103974250 | Jan 21 12:55:25 PM PST 24 | Jan 21 12:55:27 PM PST 24 | 31836525 ps | ||
| T780 | /workspace/coverage/default/40.edn_smoke.1590729080 | Jan 21 12:56:39 PM PST 24 | Jan 21 12:56:41 PM PST 24 | 23358766 ps | ||
| T781 | /workspace/coverage/default/215.edn_genbits.402044763 | Jan 21 01:00:02 PM PST 24 | Jan 21 01:00:05 PM PST 24 | 32097864 ps | ||
| T782 | /workspace/coverage/default/57.edn_err.3243288351 | Jan 21 12:58:02 PM PST 24 | Jan 21 12:58:04 PM PST 24 | 25532921 ps | ||
| T783 | /workspace/coverage/default/40.edn_alert_test.748298984 | Jan 21 12:56:38 PM PST 24 | Jan 21 12:56:40 PM PST 24 | 158436110 ps | ||
| T784 | /workspace/coverage/default/41.edn_stress_all.1484418513 | Jan 21 12:56:48 PM PST 24 | Jan 21 12:56:52 PM PST 24 | 131808592 ps | ||
| T785 | /workspace/coverage/default/63.edn_genbits.249574611 | Jan 21 01:52:00 PM PST 24 | Jan 21 01:52:01 PM PST 24 | 184899993 ps | ||
| T786 | /workspace/coverage/default/206.edn_genbits.496493850 | Jan 21 01:00:03 PM PST 24 | Jan 21 01:00:07 PM PST 24 | 74619176 ps | ||
| T787 | /workspace/coverage/default/17.edn_alert.4198662266 | Jan 21 12:53:55 PM PST 24 | Jan 21 12:53:56 PM PST 24 | 240217803 ps | ||
| T788 | /workspace/coverage/default/1.edn_alert.1878281526 | Jan 21 01:13:31 PM PST 24 | Jan 21 01:13:34 PM PST 24 | 31215457 ps | ||
| T789 | /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2978315692 | Jan 21 12:53:02 PM PST 24 | Jan 21 12:57:37 PM PST 24 | 23621308746 ps | ||
| T790 | /workspace/coverage/default/9.edn_smoke.1333007450 | Jan 21 12:52:30 PM PST 24 | Jan 21 12:52:31 PM PST 24 | 33558786 ps | ||
| T791 | /workspace/coverage/default/22.edn_disable.304984922 | Jan 21 12:54:30 PM PST 24 | Jan 21 12:54:32 PM PST 24 | 28852881 ps | ||
| T792 | /workspace/coverage/default/25.edn_err.1867386035 | Jan 21 01:47:04 PM PST 24 | Jan 21 01:47:11 PM PST 24 | 20869497 ps | ||
| T793 | /workspace/coverage/default/15.edn_intr.3173253867 | Jan 21 12:53:39 PM PST 24 | Jan 21 12:53:45 PM PST 24 | 35156085 ps | ||
| T794 | /workspace/coverage/default/26.edn_disable.1286068877 | Jan 21 12:54:55 PM PST 24 | Jan 21 12:54:56 PM PST 24 | 28478379 ps | ||
| T795 | /workspace/coverage/default/139.edn_genbits.3824538378 | Jan 21 12:59:22 PM PST 24 | Jan 21 12:59:27 PM PST 24 | 72860325 ps | ||
| T266 | /workspace/coverage/default/37.edn_alert.1941405566 | Jan 21 01:08:03 PM PST 24 | Jan 21 01:08:06 PM PST 24 | 36541927 ps | ||
| T796 | /workspace/coverage/default/45.edn_stress_all.2111379283 | Jan 21 12:57:19 PM PST 24 | Jan 21 12:57:21 PM PST 24 | 45543907 ps | ||
| T797 | /workspace/coverage/default/30.edn_genbits.4157393223 | Jan 21 02:35:43 PM PST 24 | Jan 21 02:35:45 PM PST 24 | 29359357 ps | ||
| T798 | /workspace/coverage/default/79.edn_err.29934821 | Jan 21 12:58:29 PM PST 24 | Jan 21 12:58:30 PM PST 24 | 36638279 ps | ||
| T799 | /workspace/coverage/default/8.edn_disable.1620854495 | Jan 21 12:52:31 PM PST 24 | Jan 21 12:52:32 PM PST 24 | 28123984 ps | ||
| T800 | /workspace/coverage/default/52.edn_err.2616345625 | Jan 21 12:57:45 PM PST 24 | Jan 21 12:57:47 PM PST 24 | 35403065 ps | ||
| T801 | /workspace/coverage/default/21.edn_disable_auto_req_mode.3462836820 | Jan 21 12:54:27 PM PST 24 | Jan 21 12:54:29 PM PST 24 | 20955989 ps | ||
| T802 | /workspace/coverage/default/16.edn_genbits.482700218 | Jan 21 12:53:40 PM PST 24 | Jan 21 12:53:46 PM PST 24 | 24712635 ps | ||
| T803 | /workspace/coverage/default/36.edn_stress_all.3237866230 | Jan 21 12:56:06 PM PST 24 | Jan 21 12:56:10 PM PST 24 | 1068015581 ps | ||
| T258 | /workspace/coverage/default/7.edn_regwen.285427040 | Jan 21 12:52:17 PM PST 24 | Jan 21 12:52:18 PM PST 24 | 18477061 ps | ||
| T804 | /workspace/coverage/default/43.edn_alert.1957414247 | Jan 21 12:56:58 PM PST 24 | Jan 21 12:57:05 PM PST 24 | 72844821 ps | ||
| T805 | /workspace/coverage/default/1.edn_regwen.2703508111 | Jan 21 12:50:51 PM PST 24 | Jan 21 12:50:58 PM PST 24 | 20812355 ps | ||
| T806 | /workspace/coverage/default/27.edn_intr.1890664102 | Jan 21 12:55:00 PM PST 24 | Jan 21 12:55:02 PM PST 24 | 18210035 ps | ||
| T807 | /workspace/coverage/default/48.edn_intr.2216566039 | Jan 21 12:57:38 PM PST 24 | Jan 21 12:57:40 PM PST 24 | 19787085 ps | ||
| T808 | /workspace/coverage/default/71.edn_genbits.1629881509 | Jan 21 12:58:24 PM PST 24 | Jan 21 12:58:25 PM PST 24 | 41814237 ps | ||
| T809 | /workspace/coverage/default/35.edn_intr.883293524 | Jan 21 12:56:07 PM PST 24 | Jan 21 12:56:09 PM PST 24 | 19397795 ps | ||
| T810 | /workspace/coverage/default/42.edn_err.2471594540 | Jan 21 12:56:56 PM PST 24 | Jan 21 12:57:00 PM PST 24 | 24371698 ps | ||
| T811 | /workspace/coverage/default/5.edn_alert_test.209426624 | Jan 21 12:52:07 PM PST 24 | Jan 21 12:52:08 PM PST 24 | 154707619 ps | ||
| T812 | /workspace/coverage/default/30.edn_smoke.520064007 | Jan 21 12:55:26 PM PST 24 | Jan 21 12:55:27 PM PST 24 | 172592653 ps | ||
| T813 | /workspace/coverage/default/276.edn_genbits.1581146174 | Jan 21 01:00:35 PM PST 24 | Jan 21 01:00:37 PM PST 24 | 26088948 ps | ||
| T814 | /workspace/coverage/default/213.edn_genbits.1479500361 | Jan 21 01:00:02 PM PST 24 | Jan 21 01:00:05 PM PST 24 | 20818400 ps | ||
| T815 | /workspace/coverage/default/34.edn_genbits.3954326939 | Jan 21 12:55:54 PM PST 24 | Jan 21 12:55:58 PM PST 24 | 116857854 ps | ||
| T816 | /workspace/coverage/default/26.edn_alert_test.1558748122 | Jan 21 12:55:00 PM PST 24 | Jan 21 12:55:02 PM PST 24 | 19763526 ps | ||
| T817 | /workspace/coverage/default/217.edn_genbits.876547841 | Jan 21 01:00:01 PM PST 24 | Jan 21 01:00:05 PM PST 24 | 32191041 ps | ||
| T818 | /workspace/coverage/default/73.edn_err.525545709 | Jan 21 12:58:21 PM PST 24 | Jan 21 12:58:23 PM PST 24 | 18004080 ps | ||
| T819 | /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2765584213 | Jan 21 12:55:06 PM PST 24 | Jan 21 01:23:23 PM PST 24 | 823621600026 ps | ||
| T820 | /workspace/coverage/default/77.edn_err.4219993075 | Jan 21 12:58:30 PM PST 24 | Jan 21 12:58:32 PM PST 24 | 36404646 ps | ||
| T821 | /workspace/coverage/default/31.edn_alert.3351391454 | Jan 21 12:55:38 PM PST 24 | Jan 21 12:55:40 PM PST 24 | 66346211 ps | ||
| T822 | /workspace/coverage/default/75.edn_err.3387367523 | Jan 21 12:58:26 PM PST 24 | Jan 21 12:58:28 PM PST 24 | 26929482 ps | ||
| T251 | /workspace/coverage/default/27.edn_alert.418933235 | Jan 21 12:55:03 PM PST 24 | Jan 21 12:55:05 PM PST 24 | 84336817 ps | ||
| T823 | /workspace/coverage/default/47.edn_stress_all.3433584630 | Jan 21 12:57:30 PM PST 24 | Jan 21 12:57:33 PM PST 24 | 76822339 ps | ||
| T824 | /workspace/coverage/default/12.edn_disable_auto_req_mode.2704417914 | Jan 21 01:39:32 PM PST 24 | Jan 21 01:39:36 PM PST 24 | 19351009 ps | ||
| T825 | /workspace/coverage/default/22.edn_err.68057111 | Jan 21 12:54:25 PM PST 24 | Jan 21 12:54:27 PM PST 24 | 189919453 ps | ||
| T826 | /workspace/coverage/default/16.edn_smoke.1482973404 | Jan 21 12:53:42 PM PST 24 | Jan 21 12:53:46 PM PST 24 | 12188949 ps | ||
| T827 | /workspace/coverage/default/17.edn_stress_all.1190242353 | Jan 21 12:53:48 PM PST 24 | Jan 21 12:53:52 PM PST 24 | 275407348 ps | ||
| T828 | /workspace/coverage/default/149.edn_genbits.52078634 | Jan 21 01:32:09 PM PST 24 | Jan 21 01:32:12 PM PST 24 | 281396041 ps | ||
| T829 | /workspace/coverage/default/20.edn_disable.3346177325 | Jan 21 12:54:16 PM PST 24 | Jan 21 12:54:17 PM PST 24 | 18282234 ps | ||
| T102 | /workspace/coverage/default/43.edn_intr.4134461851 | Jan 21 12:56:57 PM PST 24 | Jan 21 12:57:01 PM PST 24 | 53374263 ps | ||
| T252 | /workspace/coverage/default/44.edn_alert.2039683220 | Jan 21 12:57:11 PM PST 24 | Jan 21 12:57:13 PM PST 24 | 31284165 ps | ||
| T830 | /workspace/coverage/default/123.edn_genbits.2290683366 | Jan 21 12:59:20 PM PST 24 | Jan 21 12:59:26 PM PST 24 | 50542497 ps | ||
| T831 | /workspace/coverage/default/155.edn_genbits.2323065732 | Jan 21 12:59:17 PM PST 24 | Jan 21 12:59:20 PM PST 24 | 21201111 ps | ||
| T832 | /workspace/coverage/default/189.edn_genbits.3276559739 | Jan 21 12:59:43 PM PST 24 | Jan 21 12:59:45 PM PST 24 | 18133987 ps | ||
| T833 | /workspace/coverage/default/193.edn_genbits.1582176549 | Jan 21 12:59:53 PM PST 24 | Jan 21 12:59:56 PM PST 24 | 122319650 ps | ||
| T834 | /workspace/coverage/default/31.edn_disable.523773126 | Jan 21 12:55:38 PM PST 24 | Jan 21 12:55:40 PM PST 24 | 33897050 ps | ||
| T835 | /workspace/coverage/default/6.edn_intr.1440417039 | Jan 21 12:52:10 PM PST 24 | Jan 21 12:52:12 PM PST 24 | 24981329 ps | ||
| T836 | /workspace/coverage/default/18.edn_alert.2987888068 | Jan 21 01:21:10 PM PST 24 | Jan 21 01:21:12 PM PST 24 | 123337206 ps | ||
| T837 | /workspace/coverage/default/19.edn_genbits.2012701806 | Jan 21 01:08:04 PM PST 24 | Jan 21 01:08:06 PM PST 24 | 25490153 ps | ||
| T838 | /workspace/coverage/default/99.edn_err.1708647357 | Jan 21 12:58:57 PM PST 24 | Jan 21 12:58:59 PM PST 24 | 41918533 ps | ||
| T839 | /workspace/coverage/default/39.edn_stress_all_with_rand_reset.848071984 | Jan 21 12:56:29 PM PST 24 | Jan 21 01:40:01 PM PST 24 | 1261018286031 ps | ||
| T840 | /workspace/coverage/default/262.edn_genbits.1486339520 | Jan 21 01:56:22 PM PST 24 | Jan 21 01:56:24 PM PST 24 | 26824365 ps | ||
| T841 | /workspace/coverage/default/19.edn_stress_all_with_rand_reset.378492345 | Jan 21 02:22:55 PM PST 24 | Jan 21 02:38:29 PM PST 24 | 203362045181 ps | ||
| T842 | /workspace/coverage/default/19.edn_disable.2819677168 | Jan 21 01:23:48 PM PST 24 | Jan 21 01:23:49 PM PST 24 | 11893262 ps | ||
| T843 | /workspace/coverage/default/129.edn_genbits.4275457691 | Jan 21 12:59:16 PM PST 24 | Jan 21 12:59:19 PM PST 24 | 14621524 ps | ||
| T844 | /workspace/coverage/default/202.edn_genbits.2168100940 | Jan 21 12:59:57 PM PST 24 | Jan 21 12:59:59 PM PST 24 | 36804128 ps | ||
| T845 | /workspace/coverage/default/2.edn_disable.3864777080 | Jan 21 12:51:28 PM PST 24 | Jan 21 12:51:32 PM PST 24 | 14310110 ps | ||
| T846 | /workspace/coverage/default/2.edn_stress_all_with_rand_reset.4165662999 | Jan 21 12:51:20 PM PST 24 | Jan 21 01:00:12 PM PST 24 | 40628242906 ps | ||
| T847 | /workspace/coverage/default/101.edn_genbits.2093910696 | Jan 21 12:58:57 PM PST 24 | Jan 21 12:58:59 PM PST 24 | 166242065 ps | ||
| T848 | /workspace/coverage/default/183.edn_genbits.1776828435 | Jan 21 12:59:33 PM PST 24 | Jan 21 12:59:39 PM PST 24 | 39748136 ps | ||
| T849 | /workspace/coverage/default/236.edn_genbits.2520233653 | Jan 21 01:00:18 PM PST 24 | Jan 21 01:00:20 PM PST 24 | 28959184 ps | ||
| T850 | /workspace/coverage/default/180.edn_genbits.3897429489 | Jan 21 12:59:43 PM PST 24 | Jan 21 12:59:45 PM PST 24 | 15977716 ps | ||
| T851 | /workspace/coverage/default/9.edn_regwen.1426869993 | Jan 21 12:52:40 PM PST 24 | Jan 21 12:52:42 PM PST 24 | 47852027 ps | ||
| T852 | /workspace/coverage/default/216.edn_genbits.1598728498 | Jan 21 01:00:03 PM PST 24 | Jan 21 01:00:13 PM PST 24 | 748234527 ps | ||
| T853 | /workspace/coverage/default/3.edn_regwen.1271015957 | Jan 21 12:51:40 PM PST 24 | Jan 21 12:51:42 PM PST 24 | 23988000 ps | ||
| T854 | /workspace/coverage/default/8.edn_genbits.1636134831 | Jan 21 12:52:32 PM PST 24 | Jan 21 12:52:33 PM PST 24 | 20877617 ps | ||
| T855 | /workspace/coverage/default/98.edn_err.4113225147 | Jan 21 12:58:57 PM PST 24 | Jan 21 12:58:59 PM PST 24 | 20375078 ps | ||
| T856 | /workspace/coverage/default/143.edn_genbits.1740889635 | Jan 21 12:59:23 PM PST 24 | Jan 21 12:59:26 PM PST 24 | 30839002 ps | ||
| T857 | /workspace/coverage/default/38.edn_err.1712958001 | Jan 21 12:56:27 PM PST 24 | Jan 21 12:56:34 PM PST 24 | 47098904 ps | ||
| T60 | /workspace/coverage/default/0.edn_sec_cm.231832673 | Jan 21 12:50:53 PM PST 24 | Jan 21 12:51:07 PM PST 24 | 1868182461 ps | ||
| T858 | /workspace/coverage/default/30.edn_alert_test.2228365141 | Jan 21 12:55:26 PM PST 24 | Jan 21 12:55:28 PM PST 24 | 42196001 ps | ||
| T859 | /workspace/coverage/default/23.edn_disable.3260335417 | Jan 21 12:54:32 PM PST 24 | Jan 21 12:54:34 PM PST 24 | 16151451 ps | ||
| T860 | /workspace/coverage/default/46.edn_alert_test.191603136 | Jan 21 12:57:31 PM PST 24 | Jan 21 12:57:32 PM PST 24 | 11727380 ps | ||
| T105 | /workspace/coverage/default/1.edn_intr.1700998372 | Jan 21 01:44:04 PM PST 24 | Jan 21 01:44:06 PM PST 24 | 25149776 ps | ||
| T861 | /workspace/coverage/default/42.edn_alert.1650208096 | Jan 21 12:57:07 PM PST 24 | Jan 21 12:57:09 PM PST 24 | 73739580 ps | ||
| T262 | /workspace/coverage/default/49.edn_alert.2010232175 | Jan 21 12:57:45 PM PST 24 | Jan 21 12:57:46 PM PST 24 | 66035551 ps | ||
| T862 | /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1846262852 | Jan 21 12:56:48 PM PST 24 | Jan 21 01:01:40 PM PST 24 | 24658072888 ps | ||
| T863 | /workspace/coverage/default/122.edn_genbits.1796299186 | Jan 21 12:59:16 PM PST 24 | Jan 21 12:59:20 PM PST 24 | 34317367 ps | ||
| T864 | /workspace/coverage/default/34.edn_disable.692648473 | Jan 21 01:21:26 PM PST 24 | Jan 21 01:21:27 PM PST 24 | 12106939 ps | ||
| T865 | /workspace/coverage/default/13.edn_smoke.3045689303 | Jan 21 12:53:06 PM PST 24 | Jan 21 12:53:08 PM PST 24 | 97337863 ps | ||
| T866 | /workspace/coverage/default/1.edn_stress_all_with_rand_reset.902650874 | Jan 21 12:50:50 PM PST 24 | Jan 21 01:03:44 PM PST 24 | 34759559500 ps | ||
| T867 | /workspace/coverage/default/233.edn_genbits.3641954312 | Jan 21 01:00:14 PM PST 24 | Jan 21 01:00:17 PM PST 24 | 69614898 ps | ||
| T868 | /workspace/coverage/default/36.edn_alert.848324942 | Jan 21 12:56:12 PM PST 24 | Jan 21 12:56:19 PM PST 24 | 18888543 ps | ||
| T869 | /workspace/coverage/default/38.edn_alert.2199532675 | Jan 21 12:56:26 PM PST 24 | Jan 21 12:56:28 PM PST 24 | 55758183 ps | ||
| T870 | /workspace/coverage/default/158.edn_genbits.884781386 | Jan 21 12:59:27 PM PST 24 | Jan 21 12:59:30 PM PST 24 | 22143881 ps | ||
| T871 | /workspace/coverage/default/24.edn_disable_auto_req_mode.2856950283 | Jan 21 12:54:49 PM PST 24 | Jan 21 12:54:52 PM PST 24 | 34994126 ps | ||
| T872 | /workspace/coverage/default/17.edn_smoke.1112007957 | Jan 21 12:53:45 PM PST 24 | Jan 21 12:53:50 PM PST 24 | 28340909 ps | ||
| T873 | /workspace/coverage/default/126.edn_genbits.4214342533 | Jan 21 12:59:10 PM PST 24 | Jan 21 12:59:13 PM PST 24 | 12783396 ps | ||
| T874 | /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2106354947 | Jan 21 12:54:45 PM PST 24 | Jan 21 01:02:56 PM PST 24 | 22707711631 ps | ||
| T875 | /workspace/coverage/default/4.edn_intr.3918254411 | Jan 21 12:51:52 PM PST 24 | Jan 21 12:51:56 PM PST 24 | 31828003 ps | ||
| T876 | /workspace/coverage/default/135.edn_genbits.3025612353 | Jan 21 12:59:11 PM PST 24 | Jan 21 12:59:15 PM PST 24 | 97164790 ps | ||
| T877 | /workspace/coverage/default/249.edn_genbits.677847342 | Jan 21 01:00:18 PM PST 24 | Jan 21 01:00:21 PM PST 24 | 116048607 ps | ||
| T878 | /workspace/coverage/default/278.edn_genbits.3482864727 | Jan 21 01:00:36 PM PST 24 | Jan 21 01:00:39 PM PST 24 | 78598414 ps | ||
| T879 | /workspace/coverage/default/29.edn_alert.887472161 | Jan 21 12:55:17 PM PST 24 | Jan 21 12:55:19 PM PST 24 | 64493253 ps | ||
| T880 | /workspace/coverage/default/42.edn_smoke.707934039 | Jan 21 12:56:47 PM PST 24 | Jan 21 12:56:50 PM PST 24 | 26078489 ps | ||
| T881 | /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1671827011 | Jan 21 12:57:08 PM PST 24 | Jan 21 01:03:20 PM PST 24 | 28279144955 ps | ||
| T882 | /workspace/coverage/default/9.edn_genbits.2079976646 | Jan 21 12:52:41 PM PST 24 | Jan 21 12:52:43 PM PST 24 | 33568330 ps | ||
| T883 | /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2932555108 | Jan 21 12:52:48 PM PST 24 | Jan 21 01:27:30 PM PST 24 | 85752641986 ps | ||
| T884 | /workspace/coverage/default/27.edn_err.2309680367 | Jan 21 12:55:07 PM PST 24 | Jan 21 12:55:08 PM PST 24 | 42599528 ps | ||
| T885 | /workspace/coverage/default/3.edn_alert_test.3453244615 | Jan 21 12:51:48 PM PST 24 | Jan 21 12:51:53 PM PST 24 | 79968692 ps | ||
| T886 | /workspace/coverage/cover_reg_top/33.edn_intr_test.3093540630 | Jan 21 12:25:30 PM PST 24 | Jan 21 12:25:32 PM PST 24 | 19136034 ps | ||
| T887 | /workspace/coverage/cover_reg_top/17.edn_tl_errors.510555678 | Jan 21 12:25:27 PM PST 24 | Jan 21 12:25:31 PM PST 24 | 58529325 ps | ||
| T178 | /workspace/coverage/cover_reg_top/7.edn_csr_rw.67668837 | Jan 21 12:23:02 PM PST 24 | Jan 21 12:23:03 PM PST 24 | 16359444 ps | ||
| T888 | /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3069236366 | Jan 21 12:25:30 PM PST 24 | Jan 21 12:25:32 PM PST 24 | 54310697 ps | ||
| T889 | /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2383257948 | Jan 21 12:25:27 PM PST 24 | Jan 21 12:25:29 PM PST 24 | 29011098 ps | ||
| T890 | /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3476179753 | Jan 21 12:47:30 PM PST 24 | Jan 21 12:47:32 PM PST 24 | 63414201 ps | ||
| T891 | /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3294368121 | Jan 21 12:25:29 PM PST 24 | Jan 21 12:25:31 PM PST 24 | 32344130 ps | ||
| T180 | /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.475150252 | Jan 21 01:26:01 PM PST 24 | Jan 21 01:26:03 PM PST 24 | 13283363 ps | ||
| T892 | /workspace/coverage/cover_reg_top/4.edn_tl_errors.549905719 | Jan 21 12:25:08 PM PST 24 | Jan 21 12:25:10 PM PST 24 | 30823724 ps | ||
| T893 | /workspace/coverage/cover_reg_top/11.edn_csr_rw.3508480495 | Jan 21 12:25:01 PM PST 24 | Jan 21 12:25:04 PM PST 24 | 27865793 ps | ||
| T894 | /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3183546416 | Jan 21 12:25:29 PM PST 24 | Jan 21 12:25:31 PM PST 24 | 40682455 ps | ||
| T895 | /workspace/coverage/cover_reg_top/0.edn_csr_rw.459063731 | Jan 21 12:39:19 PM PST 24 | Jan 21 12:39:21 PM PST 24 | 23330795 ps | ||
| T896 | /workspace/coverage/cover_reg_top/13.edn_csr_rw.1491557924 | Jan 21 12:46:45 PM PST 24 | Jan 21 12:46:47 PM PST 24 | 15014464 ps | ||
| T897 | /workspace/coverage/cover_reg_top/25.edn_intr_test.3963176852 | Jan 21 12:25:20 PM PST 24 | Jan 21 12:25:22 PM PST 24 | 14382535 ps | ||
| T181 | /workspace/coverage/cover_reg_top/17.edn_csr_rw.2023903041 | Jan 21 12:25:27 PM PST 24 | Jan 21 12:25:29 PM PST 24 | 31366689 ps | ||
| T182 | /workspace/coverage/cover_reg_top/12.edn_csr_rw.3634110392 | Jan 21 12:25:01 PM PST 24 | Jan 21 12:25:05 PM PST 24 | 26427033 ps | ||
| T898 | /workspace/coverage/cover_reg_top/10.edn_tl_errors.2036529604 | Jan 21 12:24:33 PM PST 24 | Jan 21 12:24:35 PM PST 24 | 43825994 ps | ||
| T899 | /workspace/coverage/cover_reg_top/5.edn_csr_rw.928078330 | Jan 21 12:29:31 PM PST 24 | Jan 21 12:29:33 PM PST 24 | 34000691 ps | ||
| T900 | /workspace/coverage/cover_reg_top/3.edn_tl_errors.210932285 | Jan 21 01:54:55 PM PST 24 | Jan 21 01:54:59 PM PST 24 | 567697996 ps | ||
| T901 | /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3796976581 | Jan 21 12:25:17 PM PST 24 | Jan 21 12:25:19 PM PST 24 | 18624657 ps | ||
| T198 | /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2901365914 | Jan 21 12:25:01 PM PST 24 | Jan 21 12:25:05 PM PST 24 | 81009764 ps | ||
| T902 | /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1907620848 | Jan 21 12:25:07 PM PST 24 | Jan 21 12:25:09 PM PST 24 | 147189916 ps | ||
| T903 | /workspace/coverage/cover_reg_top/5.edn_intr_test.2169478744 | Jan 21 12:25:00 PM PST 24 | Jan 21 12:25:03 PM PST 24 | 21855540 ps | ||
| T904 | /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3480380100 | Jan 21 12:24:54 PM PST 24 | Jan 21 12:24:57 PM PST 24 | 43943364 ps | ||
| T905 | /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.291012131 | Jan 21 12:24:50 PM PST 24 | Jan 21 12:24:53 PM PST 24 | 68102514 ps | ||
| T906 | /workspace/coverage/cover_reg_top/23.edn_intr_test.2007657926 | Jan 21 12:25:17 PM PST 24 | Jan 21 12:25:19 PM PST 24 | 36474408 ps | ||
| T907 | /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1770426532 | Jan 21 12:25:30 PM PST 24 | Jan 21 12:25:31 PM PST 24 | 65111541 ps | ||
| T908 | /workspace/coverage/cover_reg_top/45.edn_intr_test.1484063338 | Jan 21 12:25:33 PM PST 24 | Jan 21 12:25:35 PM PST 24 | 127420110 ps | ||
| T909 | /workspace/coverage/cover_reg_top/18.edn_tl_errors.3999197453 | Jan 21 12:25:30 PM PST 24 | Jan 21 12:25:33 PM PST 24 | 121963355 ps | ||
| T910 | /workspace/coverage/cover_reg_top/7.edn_intr_test.3569074751 | Jan 21 12:39:36 PM PST 24 | Jan 21 12:39:37 PM PST 24 | 27926660 ps | ||
| T911 | /workspace/coverage/cover_reg_top/47.edn_intr_test.2451594910 | Jan 21 12:25:37 PM PST 24 | Jan 21 12:25:39 PM PST 24 | 15588880 ps | ||
| T912 | /workspace/coverage/cover_reg_top/41.edn_intr_test.3872249942 | Jan 21 12:25:36 PM PST 24 | Jan 21 12:25:37 PM PST 24 | 13562287 ps | ||
| T913 | /workspace/coverage/cover_reg_top/4.edn_csr_rw.979204511 | Jan 21 12:22:58 PM PST 24 | Jan 21 12:22:59 PM PST 24 | 51278954 ps | ||
| T914 | /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3077213958 | Jan 21 12:25:01 PM PST 24 | Jan 21 12:25:06 PM PST 24 | 28213391 ps | ||
| T915 | /workspace/coverage/cover_reg_top/34.edn_intr_test.1119078611 | Jan 21 12:25:38 PM PST 24 | Jan 21 12:25:39 PM PST 24 | 17732750 ps | ||
| T916 | /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1637028056 | Jan 21 12:25:01 PM PST 24 | Jan 21 12:25:05 PM PST 24 | 24707289 ps | ||
| T917 | /workspace/coverage/cover_reg_top/35.edn_intr_test.3393907384 | Jan 21 12:25:38 PM PST 24 | Jan 21 12:25:39 PM PST 24 | 16975613 ps | ||
| T918 | /workspace/coverage/cover_reg_top/42.edn_intr_test.1007319847 | Jan 21 12:25:36 PM PST 24 | Jan 21 12:25:38 PM PST 24 | 49862529 ps | ||
| T919 | /workspace/coverage/cover_reg_top/17.edn_intr_test.160401221 | Jan 21 12:25:27 PM PST 24 | Jan 21 12:25:29 PM PST 24 | 25998159 ps | ||
| T920 | /workspace/coverage/cover_reg_top/14.edn_tl_errors.1394110227 | Jan 21 12:25:06 PM PST 24 | Jan 21 12:25:11 PM PST 24 | 1077247666 ps | ||
| T921 | /workspace/coverage/cover_reg_top/11.edn_intr_test.182065365 | Jan 21 12:25:01 PM PST 24 | Jan 21 12:25:05 PM PST 24 | 34791224 ps | ||
| T184 | /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.4140022192 | Jan 21 12:50:20 PM PST 24 | Jan 21 12:50:21 PM PST 24 | 31953402 ps | ||
| T922 | /workspace/coverage/cover_reg_top/16.edn_intr_test.2185026410 | Jan 21 12:40:04 PM PST 24 | Jan 21 12:40:06 PM PST 24 | 10343749 ps |
| Test location | /workspace/coverage/cover_reg_top/20.edn_intr_test.4142866043 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 49743207 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 12:25:19 PM PST 24 |
| Finished | Jan 21 12:25:20 PM PST 24 |
| Peak memory | 205804 kb |
| Host | smart-cb22a42a-d41b-4f55-8dbb-eba79444befd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142866043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.4142866043 |
| Directory | /workspace/20.edn_intr_test/latest |
| Test location | /workspace/coverage/default/116.edn_genbits.675377420 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 67233553 ps |
| CPU time | 1.19 seconds |
| Started | Jan 21 12:59:01 PM PST 24 |
| Finished | Jan 21 12:59:04 PM PST 24 |
| Peak memory | 213736 kb |
| Host | smart-c1ed2dfe-2291-4fa4-953e-16a2501c3824 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=675377420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.675377420 |
| Directory | /workspace/116.edn_genbits/latest |
| Test location | /workspace/coverage/default/198.edn_genbits.1949235819 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 44588613 ps |
| CPU time | 1.24 seconds |
| Started | Jan 21 12:59:55 PM PST 24 |
| Finished | Jan 21 12:59:57 PM PST 24 |
| Peak memory | 205168 kb |
| Host | smart-ccace56e-a615-4b5b-8fe0-f2147312b36b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1949235819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1949235819 |
| Directory | /workspace/198.edn_genbits/latest |
| Test location | /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2452144652 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 151241267 ps |
| CPU time | 3.22 seconds |
| Started | Jan 21 12:46:49 PM PST 24 |
| Finished | Jan 21 12:46:53 PM PST 24 |
| Peak memory | 206112 kb |
| Host | smart-b06c113b-f1b3-4298-8a89-c422ad4b8dcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452144652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2452144652 |
| Directory | /workspace/7.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/default/28.edn_err.2257235276 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 53323990 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 01:12:25 PM PST 24 |
| Finished | Jan 21 01:12:26 PM PST 24 |
| Peak memory | 215424 kb |
| Host | smart-5fec4904-e47a-4c12-ac92-5243bab73db1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2257235276 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2257235276 |
| Directory | /workspace/28.edn_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1849285785 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 165380365 ps |
| CPU time | 1.2 seconds |
| Started | Jan 21 12:25:30 PM PST 24 |
| Finished | Jan 21 12:25:32 PM PST 24 |
| Peak memory | 214276 kb |
| Host | smart-dad6db54-fde8-4eab-aa46-c6b05fa88753 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849285785 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1849285785 |
| Directory | /workspace/15.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.edn_stress_all_with_rand_reset.4070319452 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 79193197238 ps |
| CPU time | 511.72 seconds |
| Started | Jan 21 12:57:28 PM PST 24 |
| Finished | Jan 21 01:06:01 PM PST 24 |
| Peak memory | 214988 kb |
| Host | smart-66d0feb9-b668-41fc-8309-8edad4308ef0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070319452 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.4070319452 |
| Directory | /workspace/47.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.edn_sec_cm.4017882835 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 612289390 ps |
| CPU time | 3.09 seconds |
| Started | Jan 21 02:51:49 PM PST 24 |
| Finished | Jan 21 02:51:53 PM PST 24 |
| Peak memory | 232756 kb |
| Host | smart-9630e29b-16b2-4505-a291-5d31ed878b17 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017882835 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.4017882835 |
| Directory | /workspace/2.edn_sec_cm/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2069448471 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 160057713 ps |
| CPU time | 1.97 seconds |
| Started | Jan 21 12:25:08 PM PST 24 |
| Finished | Jan 21 12:25:10 PM PST 24 |
| Peak memory | 205900 kb |
| Host | smart-71dcfdb6-16a8-4a1b-ba34-53bb0bcdc4d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069448471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2069448471 |
| Directory | /workspace/4.edn_csr_bit_bash/latest |
| Test location | /workspace/coverage/default/87.edn_genbits.2689875679 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 17914834 ps |
| CPU time | 1.15 seconds |
| Started | Jan 21 12:58:35 PM PST 24 |
| Finished | Jan 21 12:58:37 PM PST 24 |
| Peak memory | 205116 kb |
| Host | smart-612c1122-5814-4b0a-bc47-e48d4b4f9d7f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2689875679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2689875679 |
| Directory | /workspace/87.edn_genbits/latest |
| Test location | /workspace/coverage/cover_reg_top/38.edn_intr_test.2403558820 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 49016371 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:25:36 PM PST 24 |
| Finished | Jan 21 12:25:37 PM PST 24 |
| Peak memory | 205732 kb |
| Host | smart-51dc6a18-e225-41dc-a29c-207616b16428 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403558820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2403558820 |
| Directory | /workspace/38.edn_intr_test/latest |
| Test location | /workspace/coverage/default/13.edn_alert.1376450902 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 32416439 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:53:02 PM PST 24 |
| Finished | Jan 21 12:53:05 PM PST 24 |
| Peak memory | 204848 kb |
| Host | smart-c7cc42e9-9e9f-4946-9b10-6c057218a541 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1376450902 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1376450902 |
| Directory | /workspace/13.edn_alert/latest |
| Test location | /workspace/coverage/default/22.edn_intr.1299874429 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 34157559 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 01:12:15 PM PST 24 |
| Finished | Jan 21 01:12:16 PM PST 24 |
| Peak memory | 214032 kb |
| Host | smart-c3433af5-e290-4039-9669-3f3919f75513 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1299874429 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1299874429 |
| Directory | /workspace/22.edn_intr/latest |
| Test location | /workspace/coverage/default/222.edn_genbits.2209839464 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 38425625 ps |
| CPU time | 1.07 seconds |
| Started | Jan 21 01:00:10 PM PST 24 |
| Finished | Jan 21 01:00:13 PM PST 24 |
| Peak memory | 213816 kb |
| Host | smart-e93bae4f-2f55-418f-bc6c-99016bacf775 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2209839464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2209839464 |
| Directory | /workspace/222.edn_genbits/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1927730121 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 62083202 ps |
| CPU time | 1.96 seconds |
| Started | Jan 21 12:24:56 PM PST 24 |
| Finished | Jan 21 12:24:59 PM PST 24 |
| Peak memory | 205916 kb |
| Host | smart-9cea4919-3869-4e2b-aba3-8256e70c336c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927730121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1927730121 |
| Directory | /workspace/0.edn_csr_bit_bash/latest |
| Test location | /workspace/coverage/default/88.edn_genbits.1516050694 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 23937512 ps |
| CPU time | 1.25 seconds |
| Started | Jan 21 12:58:37 PM PST 24 |
| Finished | Jan 21 12:58:39 PM PST 24 |
| Peak memory | 213780 kb |
| Host | smart-70bf9cf3-ef7d-454e-b188-118c3b18a188 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1516050694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1516050694 |
| Directory | /workspace/88.edn_genbits/latest |
| Test location | /workspace/coverage/default/0.edn_regwen.2950206270 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 20599184 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 12:50:43 PM PST 24 |
| Finished | Jan 21 12:50:53 PM PST 24 |
| Peak memory | 204344 kb |
| Host | smart-60b78b30-77fe-4d92-9170-b69cbc1532fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2950206270 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2950206270 |
| Directory | /workspace/0.edn_regwen/latest |
| Test location | /workspace/coverage/default/1.edn_intr.1700998372 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 25149776 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 01:44:04 PM PST 24 |
| Finished | Jan 21 01:44:06 PM PST 24 |
| Peak memory | 225212 kb |
| Host | smart-15440eca-6981-4e9f-9e64-358669b99793 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1700998372 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1700998372 |
| Directory | /workspace/1.edn_intr/latest |
| Test location | /workspace/coverage/default/7.edn_stress_all_with_rand_reset.528343008 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 26466040491 ps |
| CPU time | 223.7 seconds |
| Started | Jan 21 01:36:50 PM PST 24 |
| Finished | Jan 21 01:40:37 PM PST 24 |
| Peak memory | 215640 kb |
| Host | smart-c12b6fc8-8a4e-454e-aab4-d408f529f3a0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528343008 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.528343008 |
| Directory | /workspace/7.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/86.edn_err.638315861 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 19649556 ps |
| CPU time | 1.05 seconds |
| Started | Jan 21 12:58:36 PM PST 24 |
| Finished | Jan 21 12:58:38 PM PST 24 |
| Peak memory | 215436 kb |
| Host | smart-21083f46-6412-46fd-a43d-0eb70bf5f415 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=638315861 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.638315861 |
| Directory | /workspace/86.edn_err/latest |
| Test location | /workspace/coverage/default/220.edn_genbits.637699994 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 38656655 ps |
| CPU time | 1.15 seconds |
| Started | Jan 21 01:00:10 PM PST 24 |
| Finished | Jan 21 01:00:12 PM PST 24 |
| Peak memory | 213728 kb |
| Host | smart-d16b17d6-45b1-4c69-83ef-a746523c6f1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=637699994 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.637699994 |
| Directory | /workspace/220.edn_genbits/latest |
| Test location | /workspace/coverage/cover_reg_top/9.edn_tl_errors.1765800106 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 40935666 ps |
| CPU time | 2.63 seconds |
| Started | Jan 21 12:28:48 PM PST 24 |
| Finished | Jan 21 12:28:52 PM PST 24 |
| Peak memory | 214280 kb |
| Host | smart-674de2db-02b2-406b-bf12-f514690f8b06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765800106 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1765800106 |
| Directory | /workspace/9.edn_tl_errors/latest |
| Test location | /workspace/coverage/default/8.edn_alert.3979439305 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 38779973 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 12:52:32 PM PST 24 |
| Finished | Jan 21 12:52:33 PM PST 24 |
| Peak memory | 204616 kb |
| Host | smart-0f2a2e3b-63cb-4a47-917d-4a0b8ff9a805 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3979439305 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3979439305 |
| Directory | /workspace/8.edn_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_intr_test.1458198038 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 15644823 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:25:00 PM PST 24 |
| Finished | Jan 21 12:25:02 PM PST 24 |
| Peak memory | 205756 kb |
| Host | smart-e8e39255-e6b8-413c-ad7a-cf4a5aa3d032 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458198038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1458198038 |
| Directory | /workspace/0.edn_intr_test/latest |
| Test location | /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2976451290 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 159748598203 ps |
| CPU time | 966.12 seconds |
| Started | Jan 21 12:54:07 PM PST 24 |
| Finished | Jan 21 01:10:14 PM PST 24 |
| Peak memory | 215672 kb |
| Host | smart-0dea5e24-8b70-4836-84fd-5e5dfd38b7c9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976451290 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2976451290 |
| Directory | /workspace/20.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.edn_alert.394289019 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 15987500 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:50:45 PM PST 24 |
| Finished | Jan 21 12:50:53 PM PST 24 |
| Peak memory | 205404 kb |
| Host | smart-fa08fcea-8516-4dda-913e-532c6e89b3b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=394289019 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.394289019 |
| Directory | /workspace/0.edn_alert/latest |
| Test location | /workspace/coverage/default/16.edn_alert.4188115863 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 18316775 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 12:53:40 PM PST 24 |
| Finished | Jan 21 12:53:46 PM PST 24 |
| Peak memory | 205280 kb |
| Host | smart-bc31f2fa-0de8-4169-bcdb-5e68f9e7dda9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4188115863 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.4188115863 |
| Directory | /workspace/16.edn_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.2305240086 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 62541926 ps |
| CPU time | 1.11 seconds |
| Started | Jan 21 12:47:47 PM PST 24 |
| Finished | Jan 21 12:47:49 PM PST 24 |
| Peak memory | 205920 kb |
| Host | smart-f8767647-a808-4b01-b4de-c22c64dcc862 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305240086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou tstanding.2305240086 |
| Directory | /workspace/2.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/1.edn_regwen.2703508111 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 20812355 ps |
| CPU time | 0.94 seconds |
| Started | Jan 21 12:50:51 PM PST 24 |
| Finished | Jan 21 12:50:58 PM PST 24 |
| Peak memory | 204516 kb |
| Host | smart-796fc6b9-501e-47ce-91d8-aa3837e8d43d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2703508111 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2703508111 |
| Directory | /workspace/1.edn_regwen/latest |
| Test location | /workspace/coverage/default/277.edn_genbits.3915846340 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 64239869 ps |
| CPU time | 1.09 seconds |
| Started | Jan 21 01:00:35 PM PST 24 |
| Finished | Jan 21 01:00:37 PM PST 24 |
| Peak memory | 213764 kb |
| Host | smart-af711ddf-b0d9-496c-b5ef-966637eb7675 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3915846340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3915846340 |
| Directory | /workspace/277.edn_genbits/latest |
| Test location | /workspace/coverage/default/6.edn_regwen.2050130720 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 24796448 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:52:05 PM PST 24 |
| Finished | Jan 21 12:52:06 PM PST 24 |
| Peak memory | 204512 kb |
| Host | smart-0da940a1-ced1-4bec-9e19-103063dbe746 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2050130720 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2050130720 |
| Directory | /workspace/6.edn_regwen/latest |
| Test location | /workspace/coverage/default/86.edn_genbits.1595179840 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 88569529 ps |
| CPU time | 1.61 seconds |
| Started | Jan 21 12:58:36 PM PST 24 |
| Finished | Jan 21 12:58:38 PM PST 24 |
| Peak memory | 213748 kb |
| Host | smart-5b500cc6-75a5-47b1-b649-804785c3b371 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1595179840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1595179840 |
| Directory | /workspace/86.edn_genbits/latest |
| Test location | /workspace/coverage/default/5.edn_disable.1913954752 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 19952012 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 12:51:58 PM PST 24 |
| Finished | Jan 21 12:52:00 PM PST 24 |
| Peak memory | 213888 kb |
| Host | smart-b72a412c-1f07-46f0-ad34-5af4019647cf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913954752 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1913954752 |
| Directory | /workspace/5.edn_disable/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.767611574 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 406640917 ps |
| CPU time | 1.55 seconds |
| Started | Jan 21 12:54:45 PM PST 24 |
| Finished | Jan 21 12:54:47 PM PST 24 |
| Peak memory | 205932 kb |
| Host | smart-009bfb61-2cd5-4d7e-9eb0-436084f46026 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767611574 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.767611574 |
| Directory | /workspace/4.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/default/114.edn_genbits.1917724789 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 69284021 ps |
| CPU time | 2.76 seconds |
| Started | Jan 21 12:59:05 PM PST 24 |
| Finished | Jan 21 12:59:11 PM PST 24 |
| Peak memory | 213776 kb |
| Host | smart-e1e11d81-b701-470f-8483-bec0548de4db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1917724789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1917724789 |
| Directory | /workspace/114.edn_genbits/latest |
| Test location | /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1583040260 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 171130219411 ps |
| CPU time | 2216.6 seconds |
| Started | Jan 21 01:35:06 PM PST 24 |
| Finished | Jan 21 02:12:03 PM PST 24 |
| Peak memory | 224572 kb |
| Host | smart-8212cd83-5a4d-4637-8b6b-3f27d1a07799 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583040260 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1583040260 |
| Directory | /workspace/14.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/179.edn_genbits.3961255720 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 24331366 ps |
| CPU time | 1.01 seconds |
| Started | Jan 21 12:59:34 PM PST 24 |
| Finished | Jan 21 12:59:40 PM PST 24 |
| Peak memory | 204776 kb |
| Host | smart-3b70a79d-54df-4e9a-a1ae-3b951579c481 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3961255720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3961255720 |
| Directory | /workspace/179.edn_genbits/latest |
| Test location | /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1383785388 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 312049621621 ps |
| CPU time | 354.5 seconds |
| Started | Jan 21 12:55:03 PM PST 24 |
| Finished | Jan 21 01:00:59 PM PST 24 |
| Peak memory | 214320 kb |
| Host | smart-d818412f-ea98-4cf1-bf85-04df044bfca2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383785388 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1383785388 |
| Directory | /workspace/27.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.edn_err.2523111216 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 96885532 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:55:49 PM PST 24 |
| Finished | Jan 21 12:55:50 PM PST 24 |
| Peak memory | 220848 kb |
| Host | smart-b1d1a252-2aa5-4e30-bf6d-8f70dc14a017 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2523111216 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2523111216 |
| Directory | /workspace/33.edn_err/latest |
| Test location | /workspace/coverage/default/43.edn_intr.4134461851 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 53374263 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 12:56:57 PM PST 24 |
| Finished | Jan 21 12:57:01 PM PST 24 |
| Peak memory | 213932 kb |
| Host | smart-1daad7b1-2e4e-4576-a1c9-adf098faed6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134461851 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.4134461851 |
| Directory | /workspace/43.edn_intr/latest |
| Test location | /workspace/coverage/default/1.edn_alert_test.3371760126 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 43177245 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:51:14 PM PST 24 |
| Finished | Jan 21 12:51:16 PM PST 24 |
| Peak memory | 203800 kb |
| Host | smart-144df2e1-ce52-4dab-9c16-5ee8ad03342d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371760126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3371760126 |
| Directory | /workspace/1.edn_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.122818995 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 89902100 ps |
| CPU time | 1.51 seconds |
| Started | Jan 21 12:38:57 PM PST 24 |
| Finished | Jan 21 12:38:59 PM PST 24 |
| Peak memory | 206004 kb |
| Host | smart-698b07cd-b24b-4450-913d-49365723017d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122818995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.122818995 |
| Directory | /workspace/0.edn_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2901365914 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 81009764 ps |
| CPU time | 1.56 seconds |
| Started | Jan 21 12:25:01 PM PST 24 |
| Finished | Jan 21 12:25:05 PM PST 24 |
| Peak memory | 205008 kb |
| Host | smart-a5ceea4b-a547-4c58-92c8-df2e2657d301 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901365914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2901365914 |
| Directory | /workspace/11.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/default/136.edn_genbits.768418417 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 272835524 ps |
| CPU time | 4.32 seconds |
| Started | Jan 21 12:59:16 PM PST 24 |
| Finished | Jan 21 12:59:23 PM PST 24 |
| Peak memory | 213272 kb |
| Host | smart-515be79c-e7f3-470a-83e1-b7c36e70b4d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=768418417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.768418417 |
| Directory | /workspace/136.edn_genbits/latest |
| Test location | /workspace/coverage/default/14.edn_stress_all.2170863259 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 633965980 ps |
| CPU time | 4.04 seconds |
| Started | Jan 21 12:53:26 PM PST 24 |
| Finished | Jan 21 12:53:33 PM PST 24 |
| Peak memory | 205588 kb |
| Host | smart-e9985a84-1457-489f-ae5e-4055c2f64809 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170863259 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2170863259 |
| Directory | /workspace/14.edn_stress_all/latest |
| Test location | /workspace/coverage/default/175.edn_genbits.4048059006 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 41634761 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 12:59:27 PM PST 24 |
| Finished | Jan 21 12:59:30 PM PST 24 |
| Peak memory | 204596 kb |
| Host | smart-a5b20412-1a9c-4917-b75a-c64cf54ebb94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4048059006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.4048059006 |
| Directory | /workspace/175.edn_genbits/latest |
| Test location | /workspace/coverage/default/178.edn_genbits.3345646501 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 21517277 ps |
| CPU time | 1.11 seconds |
| Started | Jan 21 12:59:35 PM PST 24 |
| Finished | Jan 21 12:59:40 PM PST 24 |
| Peak memory | 205252 kb |
| Host | smart-d1353177-5a1e-439a-bb18-ab71e566fd8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3345646501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3345646501 |
| Directory | /workspace/178.edn_genbits/latest |
| Test location | /workspace/coverage/default/199.edn_genbits.347538853 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 55085361 ps |
| CPU time | 1.04 seconds |
| Started | Jan 21 12:59:57 PM PST 24 |
| Finished | Jan 21 12:59:59 PM PST 24 |
| Peak memory | 205184 kb |
| Host | smart-23046da9-e70a-4a7e-9d36-d3af3d591f80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=347538853 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.347538853 |
| Directory | /workspace/199.edn_genbits/latest |
| Test location | /workspace/coverage/default/24.edn_alert.2116119341 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 22670385 ps |
| CPU time | 1.05 seconds |
| Started | Jan 21 12:54:42 PM PST 24 |
| Finished | Jan 21 12:54:44 PM PST 24 |
| Peak memory | 204592 kb |
| Host | smart-53937a11-41fb-4d41-8d90-b82a8890d799 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2116119341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.2116119341 |
| Directory | /workspace/24.edn_alert/latest |
| Test location | /workspace/coverage/default/267.edn_genbits.2283329905 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 19133551 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 01:00:40 PM PST 24 |
| Finished | Jan 21 01:00:42 PM PST 24 |
| Peak memory | 204912 kb |
| Host | smart-8e321de2-e4e8-479b-bc6f-2fc9da8cecd2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2283329905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2283329905 |
| Directory | /workspace/267.edn_genbits/latest |
| Test location | /workspace/coverage/default/28.edn_alert.835619476 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 47293591 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 12:55:07 PM PST 24 |
| Finished | Jan 21 12:55:08 PM PST 24 |
| Peak memory | 204736 kb |
| Host | smart-357215c9-f739-44c6-be25-5bf613732aaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=835619476 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.835619476 |
| Directory | /workspace/28.edn_alert/latest |
| Test location | /workspace/coverage/default/15.edn_intr.3173253867 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 35156085 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 12:53:39 PM PST 24 |
| Finished | Jan 21 12:53:45 PM PST 24 |
| Peak memory | 213880 kb |
| Host | smart-ff48f038-ea5f-47ef-b93a-240cf4503d63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3173253867 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3173253867 |
| Directory | /workspace/15.edn_intr/latest |
| Test location | /workspace/coverage/default/11.edn_disable_auto_req_mode.1580634349 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 28707715 ps |
| CPU time | 1.05 seconds |
| Started | Jan 21 12:53:01 PM PST 24 |
| Finished | Jan 21 12:53:03 PM PST 24 |
| Peak memory | 214144 kb |
| Host | smart-a74d76f8-c164-48e2-961e-ee7acc283290 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580634349 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d isable_auto_req_mode.1580634349 |
| Directory | /workspace/11.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_tl_errors.3085775332 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 70013546 ps |
| CPU time | 2.43 seconds |
| Started | Jan 21 12:25:08 PM PST 24 |
| Finished | Jan 21 12:25:11 PM PST 24 |
| Peak memory | 213648 kb |
| Host | smart-c2bdfb58-ac19-45f6-b4c2-a64315b7c58b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085775332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3085775332 |
| Directory | /workspace/0.edn_tl_errors/latest |
| Test location | /workspace/coverage/default/0.edn_disable.337141383 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 30855074 ps |
| CPU time | 0.87 seconds |
| Started | Jan 21 12:50:54 PM PST 24 |
| Finished | Jan 21 12:51:03 PM PST 24 |
| Peak memory | 213792 kb |
| Host | smart-123c9b83-eb3e-4846-84cb-b287e49fd362 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337141383 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.337141383 |
| Directory | /workspace/0.edn_disable/latest |
| Test location | /workspace/coverage/default/1.edn_disable.3254660647 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 30446792 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 12:51:14 PM PST 24 |
| Finished | Jan 21 12:51:16 PM PST 24 |
| Peak memory | 213572 kb |
| Host | smart-1c558b53-2133-4ac1-91cf-4ecbdbd2ec33 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254660647 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3254660647 |
| Directory | /workspace/1.edn_disable/latest |
| Test location | /workspace/coverage/default/11.edn_disable.2891145742 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 76258103 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 12:53:02 PM PST 24 |
| Finished | Jan 21 12:53:04 PM PST 24 |
| Peak memory | 213844 kb |
| Host | smart-a5750d13-2b94-42d2-8d2b-699f271b7abf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891145742 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2891145742 |
| Directory | /workspace/11.edn_disable/latest |
| Test location | /workspace/coverage/default/20.edn_disable_auto_req_mode.2644996325 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 16531134 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:54:15 PM PST 24 |
| Finished | Jan 21 12:54:16 PM PST 24 |
| Peak memory | 206000 kb |
| Host | smart-3be1c091-5cd8-4bc7-8427-3fb50e6d7457 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644996325 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d isable_auto_req_mode.2644996325 |
| Directory | /workspace/20.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/23.edn_disable.3260335417 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 16151451 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 12:54:32 PM PST 24 |
| Finished | Jan 21 12:54:34 PM PST 24 |
| Peak memory | 213936 kb |
| Host | smart-993c49ba-5755-453b-ab18-39af40d91c6d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260335417 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3260335417 |
| Directory | /workspace/23.edn_disable/latest |
| Test location | /workspace/coverage/default/33.edn_disable.3563187233 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 13119487 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:55:49 PM PST 24 |
| Finished | Jan 21 12:55:51 PM PST 24 |
| Peak memory | 214104 kb |
| Host | smart-3d9ab9c0-c7c8-491a-a752-c79ca88cd202 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563187233 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3563187233 |
| Directory | /workspace/33.edn_disable/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1733840171 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 21646059 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 12:23:01 PM PST 24 |
| Finished | Jan 21 12:23:03 PM PST 24 |
| Peak memory | 205776 kb |
| Host | smart-f8f4701c-ab3e-4075-9e7a-f6b707eef214 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733840171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1733840171 |
| Directory | /workspace/0.edn_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3017095955 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 54850312 ps |
| CPU time | 1.83 seconds |
| Started | Jan 21 12:24:50 PM PST 24 |
| Finished | Jan 21 12:24:53 PM PST 24 |
| Peak memory | 214212 kb |
| Host | smart-7a6dc7ef-3aad-4c93-a9ac-4f10fcbb5808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017095955 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3017095955 |
| Directory | /workspace/0.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_csr_rw.459063731 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 23330795 ps |
| CPU time | 0.87 seconds |
| Started | Jan 21 12:39:19 PM PST 24 |
| Finished | Jan 21 12:39:21 PM PST 24 |
| Peak memory | 205872 kb |
| Host | smart-85c1d393-4527-4160-bed3-4243dc2a8da9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459063731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.459063731 |
| Directory | /workspace/0.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.4000221770 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 32581026 ps |
| CPU time | 1.1 seconds |
| Started | Jan 21 12:24:31 PM PST 24 |
| Finished | Jan 21 12:24:34 PM PST 24 |
| Peak memory | 205224 kb |
| Host | smart-03bae7b0-7e8d-4b84-a468-d19b1224a89a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000221770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou tstanding.4000221770 |
| Directory | /workspace/0.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1907620848 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 147189916 ps |
| CPU time | 1.37 seconds |
| Started | Jan 21 12:25:07 PM PST 24 |
| Finished | Jan 21 12:25:09 PM PST 24 |
| Peak memory | 205960 kb |
| Host | smart-921edb0a-ea20-47f8-be4b-17d1ef1785e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907620848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1907620848 |
| Directory | /workspace/0.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.600861889 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 27354259 ps |
| CPU time | 1.03 seconds |
| Started | Jan 21 12:24:28 PM PST 24 |
| Finished | Jan 21 12:24:32 PM PST 24 |
| Peak memory | 205040 kb |
| Host | smart-e9fc16a3-aaa6-4f76-8968-8ca20dc64397 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600861889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.600861889 |
| Directory | /workspace/1.edn_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.349210782 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 2169942899 ps |
| CPU time | 3.84 seconds |
| Started | Jan 21 12:21:48 PM PST 24 |
| Finished | Jan 21 12:21:57 PM PST 24 |
| Peak memory | 206304 kb |
| Host | smart-7f3c55db-d3ec-4c37-935b-794b3309c66a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349210782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.349210782 |
| Directory | /workspace/1.edn_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.858909232 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 35320762 ps |
| CPU time | 0.78 seconds |
| Started | Jan 21 12:24:52 PM PST 24 |
| Finished | Jan 21 12:24:55 PM PST 24 |
| Peak memory | 205472 kb |
| Host | smart-d39bc3ef-b0de-4844-b7c4-89e152cd13a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858909232 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.858909232 |
| Directory | /workspace/1.edn_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3237861459 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 52720321 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 01:13:29 PM PST 24 |
| Finished | Jan 21 01:13:32 PM PST 24 |
| Peak memory | 213864 kb |
| Host | smart-f811fe68-cb94-49ac-a675-34dfb14e7e79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237861459 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3237861459 |
| Directory | /workspace/1.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_csr_rw.3781221496 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 25206035 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 12:24:26 PM PST 24 |
| Finished | Jan 21 12:24:28 PM PST 24 |
| Peak memory | 204640 kb |
| Host | smart-8e2c5099-ef8c-4d8f-9b2e-e5b2b74110d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781221496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3781221496 |
| Directory | /workspace/1.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_intr_test.52081706 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 18776568 ps |
| CPU time | 0.94 seconds |
| Started | Jan 21 12:24:26 PM PST 24 |
| Finished | Jan 21 12:24:28 PM PST 24 |
| Peak memory | 204728 kb |
| Host | smart-1fe3a3d2-3276-47e5-a962-03517e5f24d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52081706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.52081706 |
| Directory | /workspace/1.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.4193318025 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 16552938 ps |
| CPU time | 1.03 seconds |
| Started | Jan 21 01:00:28 PM PST 24 |
| Finished | Jan 21 01:00:30 PM PST 24 |
| Peak memory | 206040 kb |
| Host | smart-131223d3-e8b0-4a61-84d4-96413df21873 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193318025 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou tstanding.4193318025 |
| Directory | /workspace/1.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_tl_errors.4227674822 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 731402125 ps |
| CPU time | 1.87 seconds |
| Started | Jan 21 12:24:50 PM PST 24 |
| Finished | Jan 21 12:24:54 PM PST 24 |
| Peak memory | 214148 kb |
| Host | smart-fdba20ae-57c9-450f-bf9c-f421ce5bd498 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227674822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.4227674822 |
| Directory | /workspace/1.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1699681983 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 44239180 ps |
| CPU time | 1.56 seconds |
| Started | Jan 21 12:24:26 PM PST 24 |
| Finished | Jan 21 12:24:29 PM PST 24 |
| Peak memory | 205544 kb |
| Host | smart-e02835fc-7d2d-4ca9-9f64-44d893e0d09a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699681983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1699681983 |
| Directory | /workspace/1.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3480380100 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 43943364 ps |
| CPU time | 1.39 seconds |
| Started | Jan 21 12:24:54 PM PST 24 |
| Finished | Jan 21 12:24:57 PM PST 24 |
| Peak memory | 213968 kb |
| Host | smart-51c0f36a-ef95-4a66-986c-2b0ecf3471e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480380100 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3480380100 |
| Directory | /workspace/10.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.edn_csr_rw.1999699076 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 18509594 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:24:54 PM PST 24 |
| Finished | Jan 21 12:24:57 PM PST 24 |
| Peak memory | 205524 kb |
| Host | smart-c3f2f8d7-b5a3-4e51-8075-d725429c20b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999699076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1999699076 |
| Directory | /workspace/10.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.edn_intr_test.1278826439 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 16574308 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:24:40 PM PST 24 |
| Finished | Jan 21 12:24:42 PM PST 24 |
| Peak memory | 205232 kb |
| Host | smart-e4b00eec-00b3-4095-98d1-36e07723f8a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278826439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1278826439 |
| Directory | /workspace/10.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.1916134794 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 30114255 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 12:25:01 PM PST 24 |
| Finished | Jan 21 12:25:04 PM PST 24 |
| Peak memory | 205888 kb |
| Host | smart-fc929c14-af9f-43e8-b2d9-81cb7c214385 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916134794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o utstanding.1916134794 |
| Directory | /workspace/10.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.edn_tl_errors.2036529604 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 43825994 ps |
| CPU time | 1.71 seconds |
| Started | Jan 21 12:24:33 PM PST 24 |
| Finished | Jan 21 12:24:35 PM PST 24 |
| Peak memory | 214096 kb |
| Host | smart-ab7f62c0-7e72-408f-8893-bcade510229d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036529604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2036529604 |
| Directory | /workspace/10.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1222995886 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 517599341 ps |
| CPU time | 4.29 seconds |
| Started | Jan 21 12:24:40 PM PST 24 |
| Finished | Jan 21 12:24:46 PM PST 24 |
| Peak memory | 205464 kb |
| Host | smart-beea0d06-cc74-4412-b1ca-95080bfc9c87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222995886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1222995886 |
| Directory | /workspace/10.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3077213958 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 28213391 ps |
| CPU time | 1.78 seconds |
| Started | Jan 21 12:25:01 PM PST 24 |
| Finished | Jan 21 12:25:06 PM PST 24 |
| Peak memory | 214164 kb |
| Host | smart-379a77f7-bb3f-4d32-af6b-46b81125c06f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077213958 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3077213958 |
| Directory | /workspace/11.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.edn_csr_rw.3508480495 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 27865793 ps |
| CPU time | 0.87 seconds |
| Started | Jan 21 12:25:01 PM PST 24 |
| Finished | Jan 21 12:25:04 PM PST 24 |
| Peak memory | 205812 kb |
| Host | smart-13a9cb1f-9447-4dc4-82c9-6dbe2c8e4a66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508480495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3508480495 |
| Directory | /workspace/11.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.edn_intr_test.182065365 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 34791224 ps |
| CPU time | 0.87 seconds |
| Started | Jan 21 12:25:01 PM PST 24 |
| Finished | Jan 21 12:25:05 PM PST 24 |
| Peak memory | 205100 kb |
| Host | smart-e856b2c4-e976-4f2f-b58c-040c92604e97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182065365 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.182065365 |
| Directory | /workspace/11.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1553348820 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 54097448 ps |
| CPU time | 1.01 seconds |
| Started | Jan 21 12:24:54 PM PST 24 |
| Finished | Jan 21 12:24:57 PM PST 24 |
| Peak memory | 206296 kb |
| Host | smart-b939c783-d6ac-41e0-be5b-d82d5f30e570 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553348820 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o utstanding.1553348820 |
| Directory | /workspace/11.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.edn_tl_errors.3221948271 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 107356321 ps |
| CPU time | 3.65 seconds |
| Started | Jan 21 12:24:57 PM PST 24 |
| Finished | Jan 21 12:25:03 PM PST 24 |
| Peak memory | 214032 kb |
| Host | smart-8db0a42f-5b25-4d96-94e2-6c2bafa8f410 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221948271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3221948271 |
| Directory | /workspace/11.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.112337957 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 38554051 ps |
| CPU time | 1.45 seconds |
| Started | Jan 21 12:24:57 PM PST 24 |
| Finished | Jan 21 12:25:00 PM PST 24 |
| Peak memory | 214172 kb |
| Host | smart-4f559f8a-24c3-422a-b8fd-bd16ac3f7909 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112337957 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.112337957 |
| Directory | /workspace/12.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.edn_csr_rw.3634110392 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 26427033 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:25:01 PM PST 24 |
| Finished | Jan 21 12:25:05 PM PST 24 |
| Peak memory | 205392 kb |
| Host | smart-5a2f5a18-dfc3-443b-a23c-9c00d739c46b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634110392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3634110392 |
| Directory | /workspace/12.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.edn_intr_test.4204598314 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 11079878 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:25:01 PM PST 24 |
| Finished | Jan 21 12:25:04 PM PST 24 |
| Peak memory | 205744 kb |
| Host | smart-855bba24-aaf9-43c9-9d44-486e8691991e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204598314 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.4204598314 |
| Directory | /workspace/12.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.4181154661 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 19689692 ps |
| CPU time | 1.17 seconds |
| Started | Jan 21 12:25:01 PM PST 24 |
| Finished | Jan 21 12:25:05 PM PST 24 |
| Peak memory | 205272 kb |
| Host | smart-bfe1390a-f2be-4fa6-ac99-cd474831160a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181154661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o utstanding.4181154661 |
| Directory | /workspace/12.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.edn_tl_errors.2585843972 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 162033716 ps |
| CPU time | 2.98 seconds |
| Started | Jan 21 12:24:54 PM PST 24 |
| Finished | Jan 21 12:24:59 PM PST 24 |
| Peak memory | 214576 kb |
| Host | smart-cba78cdd-4afd-48d8-8c3b-1bd69fe7ea89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585843972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2585843972 |
| Directory | /workspace/12.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3374599750 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 300086007 ps |
| CPU time | 1.64 seconds |
| Started | Jan 21 12:24:57 PM PST 24 |
| Finished | Jan 21 12:25:01 PM PST 24 |
| Peak memory | 205840 kb |
| Host | smart-c1e49147-748e-4c22-a7e1-7c4a5e171162 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374599750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3374599750 |
| Directory | /workspace/12.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.671722206 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 415378853 ps |
| CPU time | 1.31 seconds |
| Started | Jan 21 12:38:36 PM PST 24 |
| Finished | Jan 21 12:38:38 PM PST 24 |
| Peak memory | 214204 kb |
| Host | smart-075a4a69-e7ec-4f6a-9e61-ad1d52e967af |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671722206 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.671722206 |
| Directory | /workspace/13.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.edn_csr_rw.1491557924 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 15014464 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:46:45 PM PST 24 |
| Finished | Jan 21 12:46:47 PM PST 24 |
| Peak memory | 204772 kb |
| Host | smart-ca5f0882-b0ee-4088-bda2-0e10840fcdd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491557924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1491557924 |
| Directory | /workspace/13.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.edn_intr_test.2586745253 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 12429161 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 01:00:55 PM PST 24 |
| Finished | Jan 21 01:00:57 PM PST 24 |
| Peak memory | 205764 kb |
| Host | smart-7e4bee62-fb5e-445d-b594-828de0376927 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586745253 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2586745253 |
| Directory | /workspace/13.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1637028056 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 24707289 ps |
| CPU time | 1.11 seconds |
| Started | Jan 21 12:25:01 PM PST 24 |
| Finished | Jan 21 12:25:05 PM PST 24 |
| Peak memory | 205952 kb |
| Host | smart-d1a2efb1-3881-4483-8ce9-a6c042405dc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637028056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o utstanding.1637028056 |
| Directory | /workspace/13.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.edn_tl_errors.1609180146 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 98844253 ps |
| CPU time | 2 seconds |
| Started | Jan 21 01:06:31 PM PST 24 |
| Finished | Jan 21 01:06:34 PM PST 24 |
| Peak memory | 214260 kb |
| Host | smart-b4e1563b-0238-4d1f-9d40-978995d3aa6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609180146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1609180146 |
| Directory | /workspace/13.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2336488007 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 56067473 ps |
| CPU time | 1.7 seconds |
| Started | Jan 21 12:24:57 PM PST 24 |
| Finished | Jan 21 12:25:01 PM PST 24 |
| Peak memory | 205832 kb |
| Host | smart-cefe98dc-741a-4f61-9263-674b6c8a00ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336488007 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2336488007 |
| Directory | /workspace/13.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2344981803 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 15936270 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:46:01 PM PST 24 |
| Finished | Jan 21 12:46:03 PM PST 24 |
| Peak memory | 206400 kb |
| Host | smart-3a8c7772-acb4-4575-982a-08970095b600 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344981803 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2344981803 |
| Directory | /workspace/14.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.edn_csr_rw.890726255 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 30067068 ps |
| CPU time | 0.8 seconds |
| Started | Jan 21 12:25:06 PM PST 24 |
| Finished | Jan 21 12:25:07 PM PST 24 |
| Peak memory | 205504 kb |
| Host | smart-0556d412-7db3-4550-92e5-e6e31272f666 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890726255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.890726255 |
| Directory | /workspace/14.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.edn_intr_test.1537721644 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 35693529 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 12:25:17 PM PST 24 |
| Finished | Jan 21 12:25:18 PM PST 24 |
| Peak memory | 205968 kb |
| Host | smart-35c57819-6331-4e23-86d5-8e410c8df572 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537721644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1537721644 |
| Directory | /workspace/14.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3796976581 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 18624657 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:25:17 PM PST 24 |
| Finished | Jan 21 12:25:19 PM PST 24 |
| Peak memory | 206360 kb |
| Host | smart-f880f2ef-155e-4430-84dc-1354fa93e0ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796976581 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o utstanding.3796976581 |
| Directory | /workspace/14.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.edn_tl_errors.1394110227 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 1077247666 ps |
| CPU time | 4.39 seconds |
| Started | Jan 21 12:25:06 PM PST 24 |
| Finished | Jan 21 12:25:11 PM PST 24 |
| Peak memory | 213968 kb |
| Host | smart-91f77797-0892-4bb9-8486-7a6cd919e332 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394110227 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1394110227 |
| Directory | /workspace/14.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1512048306 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 175053142 ps |
| CPU time | 1.54 seconds |
| Started | Jan 21 12:25:21 PM PST 24 |
| Finished | Jan 21 12:25:23 PM PST 24 |
| Peak memory | 206296 kb |
| Host | smart-906cbcea-4cc8-44ff-bd41-1452361738a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512048306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1512048306 |
| Directory | /workspace/14.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.edn_csr_rw.598055725 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 10930288 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 12:25:30 PM PST 24 |
| Finished | Jan 21 12:25:32 PM PST 24 |
| Peak memory | 205760 kb |
| Host | smart-441e069f-a760-42a8-a8d1-23b713c54738 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598055725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.598055725 |
| Directory | /workspace/15.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.edn_intr_test.1203580794 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 19774446 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 01:45:32 PM PST 24 |
| Finished | Jan 21 01:45:34 PM PST 24 |
| Peak memory | 205900 kb |
| Host | smart-9f7a027b-ee12-43de-b06c-d6cb69b3f80b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203580794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1203580794 |
| Directory | /workspace/15.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3183546416 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 40682455 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 12:25:29 PM PST 24 |
| Finished | Jan 21 12:25:31 PM PST 24 |
| Peak memory | 206060 kb |
| Host | smart-fc19abd3-10f1-4275-bb90-54d67427660c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183546416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o utstanding.3183546416 |
| Directory | /workspace/15.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.edn_tl_errors.1964568286 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 35002157 ps |
| CPU time | 2.18 seconds |
| Started | Jan 21 12:54:48 PM PST 24 |
| Finished | Jan 21 12:54:51 PM PST 24 |
| Peak memory | 214304 kb |
| Host | smart-c8f0cf8b-c3f4-464b-a445-f58830a5d67a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964568286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1964568286 |
| Directory | /workspace/15.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2284065847 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 162471003 ps |
| CPU time | 2.27 seconds |
| Started | Jan 21 12:53:51 PM PST 24 |
| Finished | Jan 21 12:53:54 PM PST 24 |
| Peak memory | 206112 kb |
| Host | smart-6af46845-67d9-4d8f-98d2-16340db19ba4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284065847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2284065847 |
| Directory | /workspace/15.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2383257948 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 29011098 ps |
| CPU time | 1.24 seconds |
| Started | Jan 21 12:25:27 PM PST 24 |
| Finished | Jan 21 12:25:29 PM PST 24 |
| Peak memory | 213868 kb |
| Host | smart-e66d3810-ce08-42b0-bd56-e78cfaf52c3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383257948 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2383257948 |
| Directory | /workspace/16.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.edn_csr_rw.1181479300 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 22862336 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 01:21:43 PM PST 24 |
| Finished | Jan 21 01:21:45 PM PST 24 |
| Peak memory | 206012 kb |
| Host | smart-5faab65d-c8a7-498c-b7ea-6c304b272626 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181479300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1181479300 |
| Directory | /workspace/16.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.edn_intr_test.2185026410 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 10343749 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:40:04 PM PST 24 |
| Finished | Jan 21 12:40:06 PM PST 24 |
| Peak memory | 205704 kb |
| Host | smart-e6ab7212-53aa-4bf3-b4d7-043f94c44b20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185026410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2185026410 |
| Directory | /workspace/16.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3294368121 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 32344130 ps |
| CPU time | 1.46 seconds |
| Started | Jan 21 12:25:29 PM PST 24 |
| Finished | Jan 21 12:25:31 PM PST 24 |
| Peak memory | 206088 kb |
| Host | smart-4f6f4fff-4640-4781-9a5e-d0489a38c904 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294368121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o utstanding.3294368121 |
| Directory | /workspace/16.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.edn_tl_errors.872143372 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 267290818 ps |
| CPU time | 3.39 seconds |
| Started | Jan 21 12:25:25 PM PST 24 |
| Finished | Jan 21 12:25:29 PM PST 24 |
| Peak memory | 214532 kb |
| Host | smart-79e382ba-e811-4030-8208-c580af80832e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872143372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.872143372 |
| Directory | /workspace/16.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1060515247 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 44032921 ps |
| CPU time | 1.52 seconds |
| Started | Jan 21 12:25:29 PM PST 24 |
| Finished | Jan 21 12:25:31 PM PST 24 |
| Peak memory | 206084 kb |
| Host | smart-646950f7-d6e1-4c4b-9a07-d533d3799e70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060515247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1060515247 |
| Directory | /workspace/16.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3728986381 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 28043254 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 12:25:28 PM PST 24 |
| Finished | Jan 21 12:25:30 PM PST 24 |
| Peak memory | 214340 kb |
| Host | smart-dc02091e-425e-4ed9-a788-6f52a192b303 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728986381 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3728986381 |
| Directory | /workspace/17.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.edn_csr_rw.2023903041 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 31366689 ps |
| CPU time | 0.8 seconds |
| Started | Jan 21 12:25:27 PM PST 24 |
| Finished | Jan 21 12:25:29 PM PST 24 |
| Peak memory | 205380 kb |
| Host | smart-02b7bbb1-83e6-4609-bfda-f56aba4a59f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023903041 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2023903041 |
| Directory | /workspace/17.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.edn_intr_test.160401221 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 25998159 ps |
| CPU time | 0.73 seconds |
| Started | Jan 21 12:25:27 PM PST 24 |
| Finished | Jan 21 12:25:29 PM PST 24 |
| Peak memory | 205512 kb |
| Host | smart-58ffb611-87d8-4342-9f34-bfc3f5e6353d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160401221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.160401221 |
| Directory | /workspace/17.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.520128661 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 66581191 ps |
| CPU time | 1.03 seconds |
| Started | Jan 21 12:25:29 PM PST 24 |
| Finished | Jan 21 12:25:31 PM PST 24 |
| Peak memory | 206012 kb |
| Host | smart-0bbcabb5-257b-4b63-8dce-797ceb3504ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520128661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou tstanding.520128661 |
| Directory | /workspace/17.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.edn_tl_errors.510555678 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 58529325 ps |
| CPU time | 3.08 seconds |
| Started | Jan 21 12:25:27 PM PST 24 |
| Finished | Jan 21 12:25:31 PM PST 24 |
| Peak memory | 214032 kb |
| Host | smart-08f9da22-73ce-45c7-8827-1812cb257bb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510555678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.510555678 |
| Directory | /workspace/17.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2802835445 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 134096099 ps |
| CPU time | 2.98 seconds |
| Started | Jan 21 12:25:28 PM PST 24 |
| Finished | Jan 21 12:25:32 PM PST 24 |
| Peak memory | 206020 kb |
| Host | smart-5accb8f4-19ff-4f63-a349-3b54cefc9b04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802835445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2802835445 |
| Directory | /workspace/17.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3057459239 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 66680154 ps |
| CPU time | 1.16 seconds |
| Started | Jan 21 12:25:31 PM PST 24 |
| Finished | Jan 21 12:25:34 PM PST 24 |
| Peak memory | 214208 kb |
| Host | smart-bd5d94a2-94ed-4862-86fd-fafe4619380c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057459239 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3057459239 |
| Directory | /workspace/18.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.edn_csr_rw.1194511070 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 33307706 ps |
| CPU time | 0.79 seconds |
| Started | Jan 21 12:25:27 PM PST 24 |
| Finished | Jan 21 12:25:28 PM PST 24 |
| Peak memory | 205516 kb |
| Host | smart-7917ac98-29ed-4d41-884e-049ceeadbbd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194511070 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1194511070 |
| Directory | /workspace/18.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.edn_intr_test.1264430816 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 85775910 ps |
| CPU time | 0.79 seconds |
| Started | Jan 21 01:08:48 PM PST 24 |
| Finished | Jan 21 01:08:49 PM PST 24 |
| Peak memory | 205736 kb |
| Host | smart-35c47415-6203-41bd-ba4b-2404f5418faa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264430816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1264430816 |
| Directory | /workspace/18.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3069236366 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 54310697 ps |
| CPU time | 0.94 seconds |
| Started | Jan 21 12:25:30 PM PST 24 |
| Finished | Jan 21 12:25:32 PM PST 24 |
| Peak memory | 206080 kb |
| Host | smart-3af71a45-dc8f-439c-b839-0f975f011e1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069236366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o utstanding.3069236366 |
| Directory | /workspace/18.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.edn_tl_errors.3999197453 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 121963355 ps |
| CPU time | 2.38 seconds |
| Started | Jan 21 12:25:30 PM PST 24 |
| Finished | Jan 21 12:25:33 PM PST 24 |
| Peak memory | 214228 kb |
| Host | smart-e6db4bdf-8320-4607-beb5-cce6dd64a5e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999197453 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3999197453 |
| Directory | /workspace/18.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.552370643 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 67645145 ps |
| CPU time | 2.12 seconds |
| Started | Jan 21 12:25:29 PM PST 24 |
| Finished | Jan 21 12:25:32 PM PST 24 |
| Peak memory | 206016 kb |
| Host | smart-9dafbdba-f2ab-424d-a4ed-dacfc493a855 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552370643 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.552370643 |
| Directory | /workspace/18.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1770426532 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 65111541 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:25:30 PM PST 24 |
| Finished | Jan 21 12:25:31 PM PST 24 |
| Peak memory | 205796 kb |
| Host | smart-f043228c-3a35-40e4-99a8-3df3950bafe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770426532 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1770426532 |
| Directory | /workspace/19.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.edn_csr_rw.3989847410 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 21567112 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:25:31 PM PST 24 |
| Finished | Jan 21 12:25:33 PM PST 24 |
| Peak memory | 205816 kb |
| Host | smart-9995ee91-3785-4d7e-bff2-0478a16bb75c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989847410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3989847410 |
| Directory | /workspace/19.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.edn_intr_test.3901824955 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 12683202 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 12:46:51 PM PST 24 |
| Finished | Jan 21 12:46:52 PM PST 24 |
| Peak memory | 205716 kb |
| Host | smart-5df4d42f-05f4-4b79-b71e-cfd8c11415d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901824955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3901824955 |
| Directory | /workspace/19.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.117436769 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 27400694 ps |
| CPU time | 1.2 seconds |
| Started | Jan 21 12:25:20 PM PST 24 |
| Finished | Jan 21 12:25:22 PM PST 24 |
| Peak memory | 205960 kb |
| Host | smart-69b3059f-5b31-494a-ae17-e14d4627d42a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117436769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou tstanding.117436769 |
| Directory | /workspace/19.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.edn_tl_errors.3438861644 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 152011778 ps |
| CPU time | 2.94 seconds |
| Started | Jan 21 12:25:20 PM PST 24 |
| Finished | Jan 21 12:25:24 PM PST 24 |
| Peak memory | 214120 kb |
| Host | smart-b8aaccf7-962c-40b1-98cc-28ef6f65b24b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438861644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3438861644 |
| Directory | /workspace/19.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2962194237 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1140026453 ps |
| CPU time | 2.17 seconds |
| Started | Jan 21 12:25:18 PM PST 24 |
| Finished | Jan 21 12:25:22 PM PST 24 |
| Peak memory | 205952 kb |
| Host | smart-63d5e58d-0e48-4f3f-8cba-97f6c5671012 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962194237 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2962194237 |
| Directory | /workspace/19.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.322210228 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 91809164 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:22:55 PM PST 24 |
| Finished | Jan 21 12:22:56 PM PST 24 |
| Peak memory | 206308 kb |
| Host | smart-da7044fb-1351-4be2-a7bf-5f4c3efbd79c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322210228 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.322210228 |
| Directory | /workspace/2.edn_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.3106695697 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 1553387127 ps |
| CPU time | 5.93 seconds |
| Started | Jan 21 12:24:52 PM PST 24 |
| Finished | Jan 21 12:25:00 PM PST 24 |
| Peak memory | 205448 kb |
| Host | smart-a60dda78-1667-423e-a2b2-8d8ac4bc5130 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106695697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.3106695697 |
| Directory | /workspace/2.edn_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.4140022192 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 31953402 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 12:50:20 PM PST 24 |
| Finished | Jan 21 12:50:21 PM PST 24 |
| Peak memory | 205780 kb |
| Host | smart-9571e5f7-8410-49a1-a805-8e8c4671317f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140022192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.4140022192 |
| Directory | /workspace/2.edn_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.403237517 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 46828005 ps |
| CPU time | 0.94 seconds |
| Started | Jan 21 12:20:15 PM PST 24 |
| Finished | Jan 21 12:20:17 PM PST 24 |
| Peak memory | 206300 kb |
| Host | smart-cbb2134d-f32b-4bfe-97b9-f1071be31749 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403237517 -assert nopostproc +UVM_TESTNAME= edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.403237517 |
| Directory | /workspace/2.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_csr_rw.2283137774 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 14598083 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 01:00:21 PM PST 24 |
| Finished | Jan 21 01:00:24 PM PST 24 |
| Peak memory | 205820 kb |
| Host | smart-0af6e62c-bbbb-474f-bc18-a32e0eda05d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283137774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2283137774 |
| Directory | /workspace/2.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_intr_test.2712365246 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 18649082 ps |
| CPU time | 0.79 seconds |
| Started | Jan 21 12:24:28 PM PST 24 |
| Finished | Jan 21 12:24:32 PM PST 24 |
| Peak memory | 204896 kb |
| Host | smart-33e128be-c79e-4673-950f-21965aa77876 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712365246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2712365246 |
| Directory | /workspace/2.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_tl_errors.279113116 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 176106531 ps |
| CPU time | 1.84 seconds |
| Started | Jan 21 12:24:33 PM PST 24 |
| Finished | Jan 21 12:24:36 PM PST 24 |
| Peak memory | 212692 kb |
| Host | smart-5a60d210-4d95-4528-bf65-ed757f7f3021 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279113116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.279113116 |
| Directory | /workspace/2.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2550882531 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 178134839 ps |
| CPU time | 1.48 seconds |
| Started | Jan 21 12:24:52 PM PST 24 |
| Finished | Jan 21 12:24:56 PM PST 24 |
| Peak memory | 205936 kb |
| Host | smart-9ddd7ca1-140f-4a5f-9811-96632e3e6473 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550882531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2550882531 |
| Directory | /workspace/2.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/21.edn_intr_test.122337042 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 53295875 ps |
| CPU time | 0.75 seconds |
| Started | Jan 21 12:25:29 PM PST 24 |
| Finished | Jan 21 12:25:31 PM PST 24 |
| Peak memory | 205620 kb |
| Host | smart-908c21fc-8e21-405b-8544-2261489707c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122337042 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.122337042 |
| Directory | /workspace/21.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.edn_intr_test.3116802004 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 24647576 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 12:25:31 PM PST 24 |
| Finished | Jan 21 12:25:33 PM PST 24 |
| Peak memory | 205808 kb |
| Host | smart-23c938c9-bc0f-41a7-ba3f-b359a3cc9fb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116802004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3116802004 |
| Directory | /workspace/22.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.edn_intr_test.2007657926 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 36474408 ps |
| CPU time | 0.81 seconds |
| Started | Jan 21 12:25:17 PM PST 24 |
| Finished | Jan 21 12:25:19 PM PST 24 |
| Peak memory | 205576 kb |
| Host | smart-71394189-7b3a-497a-a040-fcc13e41817f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007657926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2007657926 |
| Directory | /workspace/23.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.edn_intr_test.1352841455 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 81447054 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 12:25:30 PM PST 24 |
| Finished | Jan 21 12:25:32 PM PST 24 |
| Peak memory | 205756 kb |
| Host | smart-516bfee4-375d-49e1-9f77-5fc12f3f132b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352841455 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1352841455 |
| Directory | /workspace/24.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.edn_intr_test.3963176852 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 14382535 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:25:20 PM PST 24 |
| Finished | Jan 21 12:25:22 PM PST 24 |
| Peak memory | 205768 kb |
| Host | smart-21f71236-493a-457d-8e33-736c5386f6ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963176852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3963176852 |
| Directory | /workspace/25.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.edn_intr_test.3078176438 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 17963186 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:25:30 PM PST 24 |
| Finished | Jan 21 12:25:31 PM PST 24 |
| Peak memory | 205644 kb |
| Host | smart-fdc9d964-5e83-40d0-9f88-6a83ee4d4102 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078176438 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3078176438 |
| Directory | /workspace/26.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.edn_intr_test.4172228895 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 46669421 ps |
| CPU time | 0.78 seconds |
| Started | Jan 21 12:25:18 PM PST 24 |
| Finished | Jan 21 12:25:19 PM PST 24 |
| Peak memory | 205756 kb |
| Host | smart-dea4c0e5-8436-45ae-baca-3c89b1490fa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172228895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.4172228895 |
| Directory | /workspace/27.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.edn_intr_test.21410461 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 103505423 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 12:25:30 PM PST 24 |
| Finished | Jan 21 12:25:33 PM PST 24 |
| Peak memory | 205816 kb |
| Host | smart-0dcb7c96-1517-49e8-a6c8-fc3b56cf3db5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21410461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.21410461 |
| Directory | /workspace/28.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.edn_intr_test.230120940 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 38041908 ps |
| CPU time | 0.79 seconds |
| Started | Jan 21 12:25:27 PM PST 24 |
| Finished | Jan 21 12:25:29 PM PST 24 |
| Peak memory | 205512 kb |
| Host | smart-27819fc1-b24f-4ecb-8c29-568c4bc6e608 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230120940 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.230120940 |
| Directory | /workspace/29.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.291012131 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 68102514 ps |
| CPU time | 1.15 seconds |
| Started | Jan 21 12:24:50 PM PST 24 |
| Finished | Jan 21 12:24:53 PM PST 24 |
| Peak memory | 205912 kb |
| Host | smart-49cbdf22-eef8-4a72-9653-2e91717e8805 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291012131 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.291012131 |
| Directory | /workspace/3.edn_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.137959303 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 67395896 ps |
| CPU time | 1.9 seconds |
| Started | Jan 21 12:24:50 PM PST 24 |
| Finished | Jan 21 12:24:54 PM PST 24 |
| Peak memory | 205820 kb |
| Host | smart-79a2e71f-0e1a-41c7-8c43-d465668545b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137959303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.137959303 |
| Directory | /workspace/3.edn_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2682856648 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 102032466 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:29:58 PM PST 24 |
| Finished | Jan 21 12:30:00 PM PST 24 |
| Peak memory | 205872 kb |
| Host | smart-0ff3887d-5f87-48af-9ffb-dee11cedece4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682856648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2682856648 |
| Directory | /workspace/3.edn_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.4222283589 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 16382089 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:24:50 PM PST 24 |
| Finished | Jan 21 12:24:52 PM PST 24 |
| Peak memory | 205888 kb |
| Host | smart-ddee6aea-708f-4070-a94a-1ae97695ca77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222283589 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.4222283589 |
| Directory | /workspace/3.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_csr_rw.962535914 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 25725729 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 12:23:09 PM PST 24 |
| Finished | Jan 21 12:23:10 PM PST 24 |
| Peak memory | 206160 kb |
| Host | smart-b880cb83-df07-4c12-9750-48b4ec924411 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962535914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.962535914 |
| Directory | /workspace/3.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_intr_test.1110448446 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 11470486 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:20:15 PM PST 24 |
| Finished | Jan 21 12:20:17 PM PST 24 |
| Peak memory | 206164 kb |
| Host | smart-49463f4a-0b0f-4a0c-8f01-99bf49e371ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110448446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1110448446 |
| Directory | /workspace/3.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3476179753 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 63414201 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 12:47:30 PM PST 24 |
| Finished | Jan 21 12:47:32 PM PST 24 |
| Peak memory | 205820 kb |
| Host | smart-6ad68559-7855-45d1-a18d-cdc15c2c0f22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476179753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou tstanding.3476179753 |
| Directory | /workspace/3.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_tl_errors.210932285 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 567697996 ps |
| CPU time | 4.12 seconds |
| Started | Jan 21 01:54:55 PM PST 24 |
| Finished | Jan 21 01:54:59 PM PST 24 |
| Peak memory | 214108 kb |
| Host | smart-03bdb294-1f23-49ba-ae1a-deaddcb08e38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210932285 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.210932285 |
| Directory | /workspace/3.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1680461348 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 304893207 ps |
| CPU time | 2.19 seconds |
| Started | Jan 21 12:23:02 PM PST 24 |
| Finished | Jan 21 12:23:05 PM PST 24 |
| Peak memory | 205904 kb |
| Host | smart-b878e987-8fe7-4b28-a64a-ea949ecd2944 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680461348 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1680461348 |
| Directory | /workspace/3.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.edn_intr_test.705302928 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 19230384 ps |
| CPU time | 0.77 seconds |
| Started | Jan 21 12:50:34 PM PST 24 |
| Finished | Jan 21 12:50:36 PM PST 24 |
| Peak memory | 205760 kb |
| Host | smart-f60ff9ed-29dc-4842-8955-01bebfe42745 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705302928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.705302928 |
| Directory | /workspace/30.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.edn_intr_test.190776119 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 18653920 ps |
| CPU time | 0.79 seconds |
| Started | Jan 21 12:25:30 PM PST 24 |
| Finished | Jan 21 12:25:32 PM PST 24 |
| Peak memory | 205212 kb |
| Host | smart-579e4184-eceb-445e-be25-ecbf6cdb0677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190776119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.190776119 |
| Directory | /workspace/31.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.edn_intr_test.2286767267 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 28742273 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 01:03:50 PM PST 24 |
| Finished | Jan 21 01:03:52 PM PST 24 |
| Peak memory | 205848 kb |
| Host | smart-65593711-8489-404d-9e2b-7c5ba5ad463f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286767267 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.2286767267 |
| Directory | /workspace/32.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.edn_intr_test.3093540630 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 19136034 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 12:25:30 PM PST 24 |
| Finished | Jan 21 12:25:32 PM PST 24 |
| Peak memory | 205420 kb |
| Host | smart-03b439e1-282e-4e15-9788-68308c088fd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093540630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3093540630 |
| Directory | /workspace/33.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.edn_intr_test.1119078611 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 17732750 ps |
| CPU time | 0.94 seconds |
| Started | Jan 21 12:25:38 PM PST 24 |
| Finished | Jan 21 12:25:39 PM PST 24 |
| Peak memory | 205708 kb |
| Host | smart-a43c4a27-12a6-43f9-9a4d-1d8bc6be88ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119078611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.1119078611 |
| Directory | /workspace/34.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.edn_intr_test.3393907384 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 16975613 ps |
| CPU time | 0.79 seconds |
| Started | Jan 21 12:25:38 PM PST 24 |
| Finished | Jan 21 12:25:39 PM PST 24 |
| Peak memory | 205512 kb |
| Host | smart-2e32922d-c404-4442-bcfc-7f4cfd795113 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393907384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3393907384 |
| Directory | /workspace/35.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.edn_intr_test.900973658 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 22718784 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:25:38 PM PST 24 |
| Finished | Jan 21 12:25:39 PM PST 24 |
| Peak memory | 205732 kb |
| Host | smart-21ee299e-38e3-4a79-8a3e-42439cc57d74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900973658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.900973658 |
| Directory | /workspace/36.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.edn_intr_test.3987633389 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 12497578 ps |
| CPU time | 0.79 seconds |
| Started | Jan 21 12:25:39 PM PST 24 |
| Finished | Jan 21 12:25:41 PM PST 24 |
| Peak memory | 205812 kb |
| Host | smart-dd15ed40-077e-4b65-b1ee-541e187f5be6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987633389 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3987633389 |
| Directory | /workspace/37.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.edn_intr_test.3798159781 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 30351491 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:25:32 PM PST 24 |
| Finished | Jan 21 12:25:34 PM PST 24 |
| Peak memory | 206164 kb |
| Host | smart-d6eb4e3f-9e8b-4dc9-82a0-f12d54012f5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798159781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3798159781 |
| Directory | /workspace/39.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.167119430 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 140776355 ps |
| CPU time | 1.47 seconds |
| Started | Jan 21 12:19:30 PM PST 24 |
| Finished | Jan 21 12:19:32 PM PST 24 |
| Peak memory | 205948 kb |
| Host | smart-4829dc7d-8f3a-4829-ab73-32ce15d3da25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167119430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.167119430 |
| Directory | /workspace/4.edn_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.475150252 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 13283363 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 01:26:01 PM PST 24 |
| Finished | Jan 21 01:26:03 PM PST 24 |
| Peak memory | 206040 kb |
| Host | smart-dbab179c-010d-4f1e-8245-08c2d4e16d0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475150252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.475150252 |
| Directory | /workspace/4.edn_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3485507656 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 23979904 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 12:25:00 PM PST 24 |
| Finished | Jan 21 12:25:03 PM PST 24 |
| Peak memory | 214152 kb |
| Host | smart-cdb8d62e-0b7b-4200-919a-b755d225a5ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485507656 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3485507656 |
| Directory | /workspace/4.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_csr_rw.979204511 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 51278954 ps |
| CPU time | 0.75 seconds |
| Started | Jan 21 12:22:58 PM PST 24 |
| Finished | Jan 21 12:22:59 PM PST 24 |
| Peak memory | 205608 kb |
| Host | smart-87763515-d5fb-457b-a6ee-2963e349145e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979204511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.979204511 |
| Directory | /workspace/4.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_intr_test.1858718753 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 12827522 ps |
| CPU time | 0.79 seconds |
| Started | Jan 21 12:25:08 PM PST 24 |
| Finished | Jan 21 12:25:09 PM PST 24 |
| Peak memory | 205764 kb |
| Host | smart-d7af72a1-07b0-408b-8623-94237b92495b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858718753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1858718753 |
| Directory | /workspace/4.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1557234033 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 27681453 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 01:04:11 PM PST 24 |
| Finished | Jan 21 01:04:13 PM PST 24 |
| Peak memory | 205832 kb |
| Host | smart-52780802-5c17-4186-9033-8e65f8decee9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557234033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou tstanding.1557234033 |
| Directory | /workspace/4.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.edn_tl_errors.549905719 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 30823724 ps |
| CPU time | 2.08 seconds |
| Started | Jan 21 12:25:08 PM PST 24 |
| Finished | Jan 21 12:25:10 PM PST 24 |
| Peak memory | 214160 kb |
| Host | smart-0fbdf76d-f27e-4cd4-b7f2-4ba0b6605e8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549905719 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.549905719 |
| Directory | /workspace/4.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/40.edn_intr_test.1627863840 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 13065526 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 12:25:28 PM PST 24 |
| Finished | Jan 21 12:25:29 PM PST 24 |
| Peak memory | 205756 kb |
| Host | smart-c26708da-e74c-40f6-a692-26c6ac0b1157 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627863840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1627863840 |
| Directory | /workspace/40.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.edn_intr_test.3872249942 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 13562287 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 12:25:36 PM PST 24 |
| Finished | Jan 21 12:25:37 PM PST 24 |
| Peak memory | 205760 kb |
| Host | smart-56127085-8a24-4dce-a40c-ba784645f60f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872249942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3872249942 |
| Directory | /workspace/41.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.edn_intr_test.1007319847 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 49862529 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:25:36 PM PST 24 |
| Finished | Jan 21 12:25:38 PM PST 24 |
| Peak memory | 205732 kb |
| Host | smart-ebf7d8f8-b139-43ed-af1c-f21c73f7bddb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007319847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1007319847 |
| Directory | /workspace/42.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.edn_intr_test.1863509765 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 47339825 ps |
| CPU time | 0.8 seconds |
| Started | Jan 21 12:25:38 PM PST 24 |
| Finished | Jan 21 12:25:39 PM PST 24 |
| Peak memory | 205732 kb |
| Host | smart-b0f9291a-ac7f-4204-94ac-97bbf630ddc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863509765 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1863509765 |
| Directory | /workspace/43.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.edn_intr_test.3567394276 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 52272872 ps |
| CPU time | 0.78 seconds |
| Started | Jan 21 12:25:25 PM PST 24 |
| Finished | Jan 21 12:25:26 PM PST 24 |
| Peak memory | 205760 kb |
| Host | smart-65b98be8-733f-42d1-a395-ae5e74866faf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567394276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3567394276 |
| Directory | /workspace/44.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.edn_intr_test.1484063338 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 127420110 ps |
| CPU time | 0.8 seconds |
| Started | Jan 21 12:25:33 PM PST 24 |
| Finished | Jan 21 12:25:35 PM PST 24 |
| Peak memory | 205708 kb |
| Host | smart-200b1dc1-9215-4018-97b4-36505a6da6a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484063338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1484063338 |
| Directory | /workspace/45.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.edn_intr_test.2557247254 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 38859471 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 12:25:38 PM PST 24 |
| Finished | Jan 21 12:25:39 PM PST 24 |
| Peak memory | 205728 kb |
| Host | smart-b7a89e07-e356-449c-b2b6-04b5b7dc98f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557247254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2557247254 |
| Directory | /workspace/46.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.edn_intr_test.2451594910 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 15588880 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:25:37 PM PST 24 |
| Finished | Jan 21 12:25:39 PM PST 24 |
| Peak memory | 205796 kb |
| Host | smart-6a020062-03da-4515-9da6-ce7e52f18995 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451594910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2451594910 |
| Directory | /workspace/47.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.edn_intr_test.3698255975 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 29066560 ps |
| CPU time | 0.81 seconds |
| Started | Jan 21 12:25:36 PM PST 24 |
| Finished | Jan 21 12:25:37 PM PST 24 |
| Peak memory | 205720 kb |
| Host | smart-5feff475-61b6-4b84-a11b-c4c9a6f8c605 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698255975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3698255975 |
| Directory | /workspace/48.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.edn_intr_test.3080142762 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 22508194 ps |
| CPU time | 0.78 seconds |
| Started | Jan 21 12:25:28 PM PST 24 |
| Finished | Jan 21 12:25:29 PM PST 24 |
| Peak memory | 205756 kb |
| Host | smart-cc1a58ff-617c-4d64-b757-9ba747989dd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080142762 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3080142762 |
| Directory | /workspace/49.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3233365698 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 110355262 ps |
| CPU time | 1.11 seconds |
| Started | Jan 21 01:12:34 PM PST 24 |
| Finished | Jan 21 01:12:36 PM PST 24 |
| Peak memory | 214284 kb |
| Host | smart-1b0b6296-25ae-4374-951c-603faaa18d36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233365698 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3233365698 |
| Directory | /workspace/5.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.edn_csr_rw.928078330 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 34000691 ps |
| CPU time | 0.8 seconds |
| Started | Jan 21 12:29:31 PM PST 24 |
| Finished | Jan 21 12:29:33 PM PST 24 |
| Peak memory | 205564 kb |
| Host | smart-0d8ac8f6-4ddf-4367-ad4e-14091f19f2c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928078330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.928078330 |
| Directory | /workspace/5.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.edn_intr_test.2169478744 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 21855540 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 12:25:00 PM PST 24 |
| Finished | Jan 21 12:25:03 PM PST 24 |
| Peak memory | 205760 kb |
| Host | smart-9d007e45-5e5e-4541-ba39-6478bdb38a15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169478744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2169478744 |
| Directory | /workspace/5.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2278280979 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 74878061 ps |
| CPU time | 1.03 seconds |
| Started | Jan 21 12:22:50 PM PST 24 |
| Finished | Jan 21 12:22:52 PM PST 24 |
| Peak memory | 206092 kb |
| Host | smart-6b69267d-f6b3-4ec6-af9f-4016129989a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278280979 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou tstanding.2278280979 |
| Directory | /workspace/5.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.edn_tl_errors.3293099726 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 236450263 ps |
| CPU time | 1.4 seconds |
| Started | Jan 21 01:03:35 PM PST 24 |
| Finished | Jan 21 01:03:37 PM PST 24 |
| Peak memory | 217040 kb |
| Host | smart-04aa5866-3b3c-4d62-9830-095a6a302baf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293099726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3293099726 |
| Directory | /workspace/5.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3139161952 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 116681633 ps |
| CPU time | 1.85 seconds |
| Started | Jan 21 12:25:08 PM PST 24 |
| Finished | Jan 21 12:25:10 PM PST 24 |
| Peak memory | 205404 kb |
| Host | smart-38bf0e2e-a0b3-49ed-8151-65e1c3539e41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139161952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3139161952 |
| Directory | /workspace/5.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1355735400 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 70586786 ps |
| CPU time | 1.11 seconds |
| Started | Jan 21 12:24:28 PM PST 24 |
| Finished | Jan 21 12:24:33 PM PST 24 |
| Peak memory | 213784 kb |
| Host | smart-df097a4e-e9a1-4654-8ebf-4ab4e51c718d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355735400 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1355735400 |
| Directory | /workspace/6.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.edn_csr_rw.731674797 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 12802292 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 12:24:52 PM PST 24 |
| Finished | Jan 21 12:24:55 PM PST 24 |
| Peak memory | 205476 kb |
| Host | smart-83dce11c-4c58-426e-9929-7cee91d57526 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731674797 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.731674797 |
| Directory | /workspace/6.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.edn_intr_test.3383171056 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 12021626 ps |
| CPU time | 0.81 seconds |
| Started | Jan 21 12:24:52 PM PST 24 |
| Finished | Jan 21 12:24:55 PM PST 24 |
| Peak memory | 205588 kb |
| Host | smart-14ad1518-30cd-4fe5-b9ea-f48e8c7a48a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383171056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3383171056 |
| Directory | /workspace/6.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2626462644 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 21262656 ps |
| CPU time | 0.94 seconds |
| Started | Jan 21 01:14:04 PM PST 24 |
| Finished | Jan 21 01:14:10 PM PST 24 |
| Peak memory | 206120 kb |
| Host | smart-1b6110cb-b65a-41d9-9fd1-363f4de47f64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626462644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou tstanding.2626462644 |
| Directory | /workspace/6.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.edn_tl_errors.1709547788 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 42206458 ps |
| CPU time | 2.47 seconds |
| Started | Jan 21 12:49:49 PM PST 24 |
| Finished | Jan 21 12:49:52 PM PST 24 |
| Peak memory | 214112 kb |
| Host | smart-23d248e2-8d90-4536-b8c7-33788e243b5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709547788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1709547788 |
| Directory | /workspace/6.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3664296192 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 163962743 ps |
| CPU time | 1.53 seconds |
| Started | Jan 21 12:58:03 PM PST 24 |
| Finished | Jan 21 12:58:05 PM PST 24 |
| Peak memory | 205924 kb |
| Host | smart-25e0ee71-29cb-452d-9ae5-eac008e06203 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664296192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3664296192 |
| Directory | /workspace/6.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2631956896 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 85183294 ps |
| CPU time | 1.63 seconds |
| Started | Jan 21 01:25:15 PM PST 24 |
| Finished | Jan 21 01:25:17 PM PST 24 |
| Peak memory | 214300 kb |
| Host | smart-28c934b2-e189-4089-9875-6140e4e4d03f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631956896 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2631956896 |
| Directory | /workspace/7.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.edn_csr_rw.67668837 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 16359444 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 12:23:02 PM PST 24 |
| Finished | Jan 21 12:23:03 PM PST 24 |
| Peak memory | 205788 kb |
| Host | smart-7752c640-7f2b-41f1-b113-b188fb9e5c90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67668837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.67668837 |
| Directory | /workspace/7.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.edn_intr_test.3569074751 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 27926660 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:39:36 PM PST 24 |
| Finished | Jan 21 12:39:37 PM PST 24 |
| Peak memory | 205908 kb |
| Host | smart-2bd5194f-dffe-4704-8fc1-131eb7573be1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569074751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3569074751 |
| Directory | /workspace/7.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.37700446 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 13654221 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 12:24:33 PM PST 24 |
| Finished | Jan 21 12:24:35 PM PST 24 |
| Peak memory | 204280 kb |
| Host | smart-6b223ef6-7548-48cc-92e9-c4fe2a0f4ee0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37700446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_outs tanding.37700446 |
| Directory | /workspace/7.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.edn_tl_errors.2535013371 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 49251152 ps |
| CPU time | 1.92 seconds |
| Started | Jan 21 01:39:34 PM PST 24 |
| Finished | Jan 21 01:39:37 PM PST 24 |
| Peak memory | 222416 kb |
| Host | smart-b7433784-82e1-4c54-a252-8685a587d558 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535013371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2535013371 |
| Directory | /workspace/7.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3211808946 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 74140247 ps |
| CPU time | 1.11 seconds |
| Started | Jan 21 12:25:01 PM PST 24 |
| Finished | Jan 21 12:25:04 PM PST 24 |
| Peak memory | 214016 kb |
| Host | smart-5a26e74b-81a8-4ea0-939f-a8a73752a6eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211808946 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3211808946 |
| Directory | /workspace/8.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.edn_csr_rw.1787439093 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 19201089 ps |
| CPU time | 0.87 seconds |
| Started | Jan 21 12:25:01 PM PST 24 |
| Finished | Jan 21 12:25:04 PM PST 24 |
| Peak memory | 205756 kb |
| Host | smart-d4cb38cb-6999-4216-bbc7-63c9172200c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787439093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1787439093 |
| Directory | /workspace/8.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.edn_intr_test.2239108844 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 12596241 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 12:24:50 PM PST 24 |
| Finished | Jan 21 12:24:53 PM PST 24 |
| Peak memory | 205752 kb |
| Host | smart-2933a654-1c0a-41c2-9bf8-363164554e29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239108844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2239108844 |
| Directory | /workspace/8.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3072681697 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 475368013 ps |
| CPU time | 1.57 seconds |
| Started | Jan 21 12:25:01 PM PST 24 |
| Finished | Jan 21 12:25:05 PM PST 24 |
| Peak memory | 205852 kb |
| Host | smart-e62b4a01-54eb-4a0f-83e7-baba5726bfaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072681697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou tstanding.3072681697 |
| Directory | /workspace/8.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.edn_tl_errors.227518808 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 59154526 ps |
| CPU time | 1.99 seconds |
| Started | Jan 21 12:22:52 PM PST 24 |
| Finished | Jan 21 12:22:55 PM PST 24 |
| Peak memory | 214488 kb |
| Host | smart-739f9e5d-c4ac-4fce-bc7f-5fbacc789410 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227518808 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.227518808 |
| Directory | /workspace/8.edn_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1275694593 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 162875917 ps |
| CPU time | 1.49 seconds |
| Started | Jan 21 12:24:50 PM PST 24 |
| Finished | Jan 21 12:24:53 PM PST 24 |
| Peak memory | 205976 kb |
| Host | smart-8558d58f-2eff-44e1-a976-41c6d6e38ede |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275694593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1275694593 |
| Directory | /workspace/8.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1606003442 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 14942190 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 12:24:49 PM PST 24 |
| Finished | Jan 21 12:24:51 PM PST 24 |
| Peak memory | 214204 kb |
| Host | smart-8d6dd1d2-4d0d-43c2-8e1e-7a76607d42c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606003442 -assert nopostproc +UVM_TESTNAME =edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1606003442 |
| Directory | /workspace/9.edn_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.edn_csr_rw.1084564496 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 154161382 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:19:26 PM PST 24 |
| Finished | Jan 21 12:19:28 PM PST 24 |
| Peak memory | 206232 kb |
| Host | smart-2efe651f-71a0-4c86-9abd-0dbdd50fd920 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084564496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1084564496 |
| Directory | /workspace/9.edn_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.edn_intr_test.3970870635 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 28433114 ps |
| CPU time | 0.77 seconds |
| Started | Jan 21 01:01:30 PM PST 24 |
| Finished | Jan 21 01:01:32 PM PST 24 |
| Peak memory | 205672 kb |
| Host | smart-58a80f43-775e-4ada-b5e2-2651ca2521b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970870635 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3970870635 |
| Directory | /workspace/9.edn_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1942776562 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 78444335 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 01:34:24 PM PST 24 |
| Finished | Jan 21 01:34:25 PM PST 24 |
| Peak memory | 205908 kb |
| Host | smart-90c3b761-f78c-47f3-82d0-e1e59294c39e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942776562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou tstanding.1942776562 |
| Directory | /workspace/9.edn_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1187825812 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 187126568 ps |
| CPU time | 1.59 seconds |
| Started | Jan 21 02:25:33 PM PST 24 |
| Finished | Jan 21 02:25:35 PM PST 24 |
| Peak memory | 206020 kb |
| Host | smart-cd88f6f9-3f5a-4d12-91d1-51af095bf660 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187825812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1187825812 |
| Directory | /workspace/9.edn_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.edn_alert_test.2208600230 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 53716393 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:50:51 PM PST 24 |
| Finished | Jan 21 12:50:58 PM PST 24 |
| Peak memory | 204168 kb |
| Host | smart-7300cb5e-27f4-4430-939c-536e45170189 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208600230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.2208600230 |
| Directory | /workspace/0.edn_alert_test/latest |
| Test location | /workspace/coverage/default/0.edn_disable_auto_req_mode.472742573 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 38974303 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 12:50:51 PM PST 24 |
| Finished | Jan 21 12:50:58 PM PST 24 |
| Peak memory | 214132 kb |
| Host | smart-bcea6a38-d821-46f1-85a9-1e8ebe5ad275 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472742573 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis able_auto_req_mode.472742573 |
| Directory | /workspace/0.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/0.edn_err.4160800711 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 20228644 ps |
| CPU time | 1.18 seconds |
| Started | Jan 21 12:50:54 PM PST 24 |
| Finished | Jan 21 12:51:03 PM PST 24 |
| Peak memory | 215308 kb |
| Host | smart-0eb9ae0f-28c5-42c3-8c48-ed5c0c0464cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4160800711 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.4160800711 |
| Directory | /workspace/0.edn_err/latest |
| Test location | /workspace/coverage/default/0.edn_genbits.1914068071 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 20626424 ps |
| CPU time | 1.36 seconds |
| Started | Jan 21 12:50:43 PM PST 24 |
| Finished | Jan 21 12:50:54 PM PST 24 |
| Peak memory | 204888 kb |
| Host | smart-afd4faa3-fad7-4b96-be24-9f50623b9f56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1914068071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1914068071 |
| Directory | /workspace/0.edn_genbits/latest |
| Test location | /workspace/coverage/default/0.edn_intr.940089535 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 21281489 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 12:50:47 PM PST 24 |
| Finished | Jan 21 12:50:54 PM PST 24 |
| Peak memory | 213888 kb |
| Host | smart-3ad5f155-4b62-4bc0-a919-dd556376927b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=940089535 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.940089535 |
| Directory | /workspace/0.edn_intr/latest |
| Test location | /workspace/coverage/default/0.edn_sec_cm.231832673 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1868182461 ps |
| CPU time | 6.09 seconds |
| Started | Jan 21 12:50:53 PM PST 24 |
| Finished | Jan 21 12:51:07 PM PST 24 |
| Peak memory | 233668 kb |
| Host | smart-e2170d25-4108-421f-a5de-6460ad29d6d7 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231832673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.231832673 |
| Directory | /workspace/0.edn_sec_cm/latest |
| Test location | /workspace/coverage/default/0.edn_smoke.3194519911 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 24932018 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:50:44 PM PST 24 |
| Finished | Jan 21 12:50:53 PM PST 24 |
| Peak memory | 204196 kb |
| Host | smart-e29e5ccb-e914-4d69-813f-70f5e646b9f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3194519911 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3194519911 |
| Directory | /workspace/0.edn_smoke/latest |
| Test location | /workspace/coverage/default/0.edn_stress_all.3817999174 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 354747434 ps |
| CPU time | 2.22 seconds |
| Started | Jan 21 12:50:45 PM PST 24 |
| Finished | Jan 21 12:50:55 PM PST 24 |
| Peak memory | 205388 kb |
| Host | smart-4dd56c97-0ca7-40cb-bf06-2ee39c05ea39 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817999174 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3817999174 |
| Directory | /workspace/0.edn_stress_all/latest |
| Test location | /workspace/coverage/default/0.edn_stress_all_with_rand_reset.808053940 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 22750223325 ps |
| CPU time | 580.95 seconds |
| Started | Jan 21 12:50:45 PM PST 24 |
| Finished | Jan 21 01:00:33 PM PST 24 |
| Peak memory | 214396 kb |
| Host | smart-e6e3e511-d3f8-4842-a27d-d2ef7ad3e92c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808053940 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.808053940 |
| Directory | /workspace/0.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.edn_alert.1878281526 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 31215457 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 01:13:31 PM PST 24 |
| Finished | Jan 21 01:13:34 PM PST 24 |
| Peak memory | 204976 kb |
| Host | smart-67642c39-b8f6-4a48-b0fa-1f4e960356c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1878281526 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1878281526 |
| Directory | /workspace/1.edn_alert/latest |
| Test location | /workspace/coverage/default/1.edn_disable_auto_req_mode.4164204816 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 88339305 ps |
| CPU time | 1 seconds |
| Started | Jan 21 12:51:11 PM PST 24 |
| Finished | Jan 21 12:51:13 PM PST 24 |
| Peak memory | 213996 kb |
| Host | smart-a0368087-16ab-4c09-b38f-6308faab0325 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164204816 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di sable_auto_req_mode.4164204816 |
| Directory | /workspace/1.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/1.edn_err.2286788425 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 29716222 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 12:51:12 PM PST 24 |
| Finished | Jan 21 12:51:14 PM PST 24 |
| Peak memory | 214984 kb |
| Host | smart-d41c0dd0-1031-45a9-9b6a-e800942abed0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2286788425 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2286788425 |
| Directory | /workspace/1.edn_err/latest |
| Test location | /workspace/coverage/default/1.edn_genbits.1733168689 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 25280727 ps |
| CPU time | 1.12 seconds |
| Started | Jan 21 12:50:51 PM PST 24 |
| Finished | Jan 21 12:50:58 PM PST 24 |
| Peak memory | 204948 kb |
| Host | smart-1be471fb-21b7-48db-8432-97109319c2b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1733168689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1733168689 |
| Directory | /workspace/1.edn_genbits/latest |
| Test location | /workspace/coverage/default/1.edn_sec_cm.666687881 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1352645398 ps |
| CPU time | 3.79 seconds |
| Started | Jan 21 12:51:09 PM PST 24 |
| Finished | Jan 21 12:51:14 PM PST 24 |
| Peak memory | 232496 kb |
| Host | smart-472f37b6-f799-4df9-b82f-72ab81652f46 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666687881 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.666687881 |
| Directory | /workspace/1.edn_sec_cm/latest |
| Test location | /workspace/coverage/default/1.edn_smoke.3436086843 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 58915891 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:50:50 PM PST 24 |
| Finished | Jan 21 12:50:58 PM PST 24 |
| Peak memory | 204472 kb |
| Host | smart-d8d8944c-361f-4b57-ba64-6df2060813c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3436086843 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3436086843 |
| Directory | /workspace/1.edn_smoke/latest |
| Test location | /workspace/coverage/default/1.edn_stress_all.2373478810 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 43349112 ps |
| CPU time | 1.34 seconds |
| Started | Jan 21 12:50:50 PM PST 24 |
| Finished | Jan 21 12:50:59 PM PST 24 |
| Peak memory | 205524 kb |
| Host | smart-9aa60af9-2ea3-4b97-bb45-4326bbac1c4a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373478810 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2373478810 |
| Directory | /workspace/1.edn_stress_all/latest |
| Test location | /workspace/coverage/default/1.edn_stress_all_with_rand_reset.902650874 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 34759559500 ps |
| CPU time | 766.78 seconds |
| Started | Jan 21 12:50:50 PM PST 24 |
| Finished | Jan 21 01:03:44 PM PST 24 |
| Peak memory | 215012 kb |
| Host | smart-27e860ae-2b11-422c-8d16-a44d9ccc03ff |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902650874 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.902650874 |
| Directory | /workspace/1.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.edn_alert.3857911676 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 32636337 ps |
| CPU time | 1 seconds |
| Started | Jan 21 12:52:51 PM PST 24 |
| Finished | Jan 21 12:52:53 PM PST 24 |
| Peak memory | 205396 kb |
| Host | smart-d33152bc-0c40-4bd6-9bec-c60e3918cab0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3857911676 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3857911676 |
| Directory | /workspace/10.edn_alert/latest |
| Test location | /workspace/coverage/default/10.edn_alert_test.2329556584 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 26931244 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:52:47 PM PST 24 |
| Finished | Jan 21 12:52:49 PM PST 24 |
| Peak memory | 204156 kb |
| Host | smart-befc655b-baf6-40f7-b57e-d94bbd01ca9b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329556584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2329556584 |
| Directory | /workspace/10.edn_alert_test/latest |
| Test location | /workspace/coverage/default/10.edn_disable.3278573128 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 14193041 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:52:48 PM PST 24 |
| Finished | Jan 21 12:52:50 PM PST 24 |
| Peak memory | 214060 kb |
| Host | smart-1c238cca-d566-4d92-a6ef-8aa3ed120b30 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278573128 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3278573128 |
| Directory | /workspace/10.edn_disable/latest |
| Test location | /workspace/coverage/default/10.edn_disable_auto_req_mode.2229000078 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 24740165 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:52:51 PM PST 24 |
| Finished | Jan 21 12:52:52 PM PST 24 |
| Peak memory | 214120 kb |
| Host | smart-99fe46de-7928-44fa-9cfd-deefa420c870 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229000078 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d isable_auto_req_mode.2229000078 |
| Directory | /workspace/10.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/10.edn_err.1077997811 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 29934022 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 12:52:48 PM PST 24 |
| Finished | Jan 21 12:52:50 PM PST 24 |
| Peak memory | 215916 kb |
| Host | smart-9a18e7e7-4c23-4bec-b278-f8fad98992e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1077997811 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1077997811 |
| Directory | /workspace/10.edn_err/latest |
| Test location | /workspace/coverage/default/10.edn_genbits.465715211 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 37044559 ps |
| CPU time | 1.55 seconds |
| Started | Jan 21 12:52:42 PM PST 24 |
| Finished | Jan 21 12:52:44 PM PST 24 |
| Peak memory | 213720 kb |
| Host | smart-1fbe990c-86cb-4495-ad21-9575b076c637 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=465715211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.465715211 |
| Directory | /workspace/10.edn_genbits/latest |
| Test location | /workspace/coverage/default/10.edn_intr.4269052356 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 35400001 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:52:49 PM PST 24 |
| Finished | Jan 21 12:52:51 PM PST 24 |
| Peak memory | 213804 kb |
| Host | smart-9ab01216-72e0-406d-ad9b-268dd9bb9168 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4269052356 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.4269052356 |
| Directory | /workspace/10.edn_intr/latest |
| Test location | /workspace/coverage/default/10.edn_smoke.740209984 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 45810764 ps |
| CPU time | 0.81 seconds |
| Started | Jan 21 12:52:42 PM PST 24 |
| Finished | Jan 21 12:52:43 PM PST 24 |
| Peak memory | 204540 kb |
| Host | smart-3e5da773-d117-4249-a045-bc23df4c5ef9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=740209984 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.740209984 |
| Directory | /workspace/10.edn_smoke/latest |
| Test location | /workspace/coverage/default/10.edn_stress_all.2151667446 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 58832674 ps |
| CPU time | 1.81 seconds |
| Started | Jan 21 12:52:40 PM PST 24 |
| Finished | Jan 21 12:52:43 PM PST 24 |
| Peak memory | 205116 kb |
| Host | smart-66e1ed24-93a0-4ad3-bd71-d667a559576d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151667446 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.2151667446 |
| Directory | /workspace/10.edn_stress_all/latest |
| Test location | /workspace/coverage/default/10.edn_stress_all_with_rand_reset.2932555108 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 85752641986 ps |
| CPU time | 2080.88 seconds |
| Started | Jan 21 12:52:48 PM PST 24 |
| Finished | Jan 21 01:27:30 PM PST 24 |
| Peak memory | 223440 kb |
| Host | smart-967acaea-af3a-49a3-9e52-5c6724b75522 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932555108 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.2932555108 |
| Directory | /workspace/10.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/100.edn_genbits.240732078 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 19593288 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 12:58:55 PM PST 24 |
| Finished | Jan 21 12:58:57 PM PST 24 |
| Peak memory | 213676 kb |
| Host | smart-f5856958-bef4-492d-9322-5e0e420696e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240732078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.240732078 |
| Directory | /workspace/100.edn_genbits/latest |
| Test location | /workspace/coverage/default/101.edn_genbits.2093910696 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 166242065 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 12:58:57 PM PST 24 |
| Finished | Jan 21 12:58:59 PM PST 24 |
| Peak memory | 205304 kb |
| Host | smart-350f2a16-e7a0-4fcd-87db-69f7018e3eef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2093910696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2093910696 |
| Directory | /workspace/101.edn_genbits/latest |
| Test location | /workspace/coverage/default/102.edn_genbits.875647552 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 69775294 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 12:58:54 PM PST 24 |
| Finished | Jan 21 12:58:56 PM PST 24 |
| Peak memory | 213744 kb |
| Host | smart-f5d4e56b-9182-4016-b08e-7a9c545aea66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=875647552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.875647552 |
| Directory | /workspace/102.edn_genbits/latest |
| Test location | /workspace/coverage/default/103.edn_genbits.1897821150 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 65220673 ps |
| CPU time | 1.54 seconds |
| Started | Jan 21 12:58:59 PM PST 24 |
| Finished | Jan 21 12:59:02 PM PST 24 |
| Peak memory | 214084 kb |
| Host | smart-6b385e0f-393b-4a4a-8c5f-dba2a6fb8a02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1897821150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1897821150 |
| Directory | /workspace/103.edn_genbits/latest |
| Test location | /workspace/coverage/default/104.edn_genbits.2745715754 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 61588914 ps |
| CPU time | 1.15 seconds |
| Started | Jan 21 12:58:57 PM PST 24 |
| Finished | Jan 21 12:58:59 PM PST 24 |
| Peak memory | 213824 kb |
| Host | smart-85f2cd5e-fb5e-49c5-849f-1aaa75ec7eda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2745715754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2745715754 |
| Directory | /workspace/104.edn_genbits/latest |
| Test location | /workspace/coverage/default/106.edn_genbits.2797303329 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 136365227 ps |
| CPU time | 1.01 seconds |
| Started | Jan 21 12:58:55 PM PST 24 |
| Finished | Jan 21 12:58:57 PM PST 24 |
| Peak memory | 204776 kb |
| Host | smart-7ca87b05-2931-4f39-8a59-1f07fa3cf148 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2797303329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2797303329 |
| Directory | /workspace/106.edn_genbits/latest |
| Test location | /workspace/coverage/default/109.edn_genbits.3226684749 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 63128344 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 12:58:57 PM PST 24 |
| Finished | Jan 21 12:58:59 PM PST 24 |
| Peak memory | 205088 kb |
| Host | smart-2c60d915-5fb6-4633-a969-8c2dae9b0a42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226684749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3226684749 |
| Directory | /workspace/109.edn_genbits/latest |
| Test location | /workspace/coverage/default/11.edn_alert.1990637625 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 195469418 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:52:54 PM PST 24 |
| Finished | Jan 21 12:52:56 PM PST 24 |
| Peak memory | 204768 kb |
| Host | smart-7023339c-18ab-4b91-9b9a-2b1327131baf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1990637625 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1990637625 |
| Directory | /workspace/11.edn_alert/latest |
| Test location | /workspace/coverage/default/11.edn_alert_test.3632850836 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 16926800 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:53:01 PM PST 24 |
| Finished | Jan 21 12:53:03 PM PST 24 |
| Peak memory | 204032 kb |
| Host | smart-f934e848-6a02-4e36-940b-70b1641b1489 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632850836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3632850836 |
| Directory | /workspace/11.edn_alert_test/latest |
| Test location | /workspace/coverage/default/11.edn_err.3324393932 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 21229824 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:53:01 PM PST 24 |
| Finished | Jan 21 12:53:03 PM PST 24 |
| Peak memory | 220792 kb |
| Host | smart-b4bfcd15-67d4-471b-aa02-5bc361cdf71b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3324393932 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3324393932 |
| Directory | /workspace/11.edn_err/latest |
| Test location | /workspace/coverage/default/11.edn_intr.3744304057 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 29471440 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 12:53:01 PM PST 24 |
| Finished | Jan 21 12:53:03 PM PST 24 |
| Peak memory | 213852 kb |
| Host | smart-f81df7cc-9fb4-45a1-8adf-fdc0c80d4c2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744304057 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3744304057 |
| Directory | /workspace/11.edn_intr/latest |
| Test location | /workspace/coverage/default/11.edn_smoke.606507893 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 15038679 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:52:49 PM PST 24 |
| Finished | Jan 21 12:52:51 PM PST 24 |
| Peak memory | 204180 kb |
| Host | smart-8fc24074-9651-4033-88ed-6659ea613cc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=606507893 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.606507893 |
| Directory | /workspace/11.edn_smoke/latest |
| Test location | /workspace/coverage/default/11.edn_stress_all.1002868966 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 583105317 ps |
| CPU time | 3.8 seconds |
| Started | Jan 21 12:52:50 PM PST 24 |
| Finished | Jan 21 12:52:55 PM PST 24 |
| Peak memory | 205536 kb |
| Host | smart-6ef2c019-ce33-42b6-a644-d246a30e3c14 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002868966 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1002868966 |
| Directory | /workspace/11.edn_stress_all/latest |
| Test location | /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1612560558 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 29304415070 ps |
| CPU time | 770.47 seconds |
| Started | Jan 21 12:53:01 PM PST 24 |
| Finished | Jan 21 01:05:52 PM PST 24 |
| Peak memory | 215028 kb |
| Host | smart-2334cbda-9327-4564-9033-e8fd5c74f930 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612560558 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1612560558 |
| Directory | /workspace/11.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/110.edn_genbits.2612583876 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 59743431 ps |
| CPU time | 1 seconds |
| Started | Jan 21 12:58:59 PM PST 24 |
| Finished | Jan 21 12:59:02 PM PST 24 |
| Peak memory | 205020 kb |
| Host | smart-0c216d9b-928f-470d-8011-fd888e9f12fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2612583876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2612583876 |
| Directory | /workspace/110.edn_genbits/latest |
| Test location | /workspace/coverage/default/111.edn_genbits.848349588 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 36731530 ps |
| CPU time | 1.04 seconds |
| Started | Jan 21 12:58:59 PM PST 24 |
| Finished | Jan 21 12:59:02 PM PST 24 |
| Peak memory | 205120 kb |
| Host | smart-99f6a898-b4ee-484b-a05f-2bc4d15ce66a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=848349588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.848349588 |
| Directory | /workspace/111.edn_genbits/latest |
| Test location | /workspace/coverage/default/113.edn_genbits.1244070693 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 16888011 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 12:59:17 PM PST 24 |
| Finished | Jan 21 12:59:24 PM PST 24 |
| Peak memory | 204632 kb |
| Host | smart-19829cc1-697f-4d5f-af70-f8bb19b8929d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1244070693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1244070693 |
| Directory | /workspace/113.edn_genbits/latest |
| Test location | /workspace/coverage/default/118.edn_genbits.690357774 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 40971157 ps |
| CPU time | 1.04 seconds |
| Started | Jan 21 12:59:17 PM PST 24 |
| Finished | Jan 21 12:59:24 PM PST 24 |
| Peak memory | 205032 kb |
| Host | smart-7e3e6544-ff48-4535-bd13-a467bc115508 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=690357774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.690357774 |
| Directory | /workspace/118.edn_genbits/latest |
| Test location | /workspace/coverage/default/119.edn_genbits.3685292071 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 15638690 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:59:17 PM PST 24 |
| Finished | Jan 21 12:59:24 PM PST 24 |
| Peak memory | 204412 kb |
| Host | smart-052911e5-6da7-4327-ab89-37bff275acda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3685292071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3685292071 |
| Directory | /workspace/119.edn_genbits/latest |
| Test location | /workspace/coverage/default/12.edn_alert.285605867 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 33987780 ps |
| CPU time | 0.94 seconds |
| Started | Jan 21 12:53:02 PM PST 24 |
| Finished | Jan 21 12:53:05 PM PST 24 |
| Peak memory | 204672 kb |
| Host | smart-ebc8c47e-f552-4fa3-be91-d66c130f8e69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=285605867 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.285605867 |
| Directory | /workspace/12.edn_alert/latest |
| Test location | /workspace/coverage/default/12.edn_alert_test.3606604692 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 65877788 ps |
| CPU time | 1.58 seconds |
| Started | Jan 21 12:53:01 PM PST 24 |
| Finished | Jan 21 12:53:03 PM PST 24 |
| Peak memory | 204696 kb |
| Host | smart-f86a7c52-7495-4939-bcf9-1a6ca9325651 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606604692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3606604692 |
| Directory | /workspace/12.edn_alert_test/latest |
| Test location | /workspace/coverage/default/12.edn_disable.4018204017 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 39450350 ps |
| CPU time | 0.81 seconds |
| Started | Jan 21 12:53:06 PM PST 24 |
| Finished | Jan 21 12:53:08 PM PST 24 |
| Peak memory | 213956 kb |
| Host | smart-7c89d320-31f1-4c5f-b08c-36a86e8484b8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018204017 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.4018204017 |
| Directory | /workspace/12.edn_disable/latest |
| Test location | /workspace/coverage/default/12.edn_disable_auto_req_mode.2704417914 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 19351009 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 01:39:32 PM PST 24 |
| Finished | Jan 21 01:39:36 PM PST 24 |
| Peak memory | 214288 kb |
| Host | smart-a62166bc-a006-47ff-8fde-b888f06b0a30 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704417914 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d isable_auto_req_mode.2704417914 |
| Directory | /workspace/12.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/12.edn_err.1685076102 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 21930391 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:53:02 PM PST 24 |
| Finished | Jan 21 12:53:05 PM PST 24 |
| Peak memory | 215284 kb |
| Host | smart-00249e26-027d-4b58-a2d8-8b1cbecb491c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1685076102 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1685076102 |
| Directory | /workspace/12.edn_err/latest |
| Test location | /workspace/coverage/default/12.edn_genbits.2155190914 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 38789881 ps |
| CPU time | 1.68 seconds |
| Started | Jan 21 12:52:53 PM PST 24 |
| Finished | Jan 21 12:52:55 PM PST 24 |
| Peak memory | 213696 kb |
| Host | smart-eb0c139d-cb8a-4f05-bcfe-e46ba82ba7c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2155190914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2155190914 |
| Directory | /workspace/12.edn_genbits/latest |
| Test location | /workspace/coverage/default/12.edn_intr.4161187549 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 66215513 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 01:42:24 PM PST 24 |
| Finished | Jan 21 01:42:26 PM PST 24 |
| Peak memory | 214036 kb |
| Host | smart-867dbf06-9339-4c60-8b94-00da8ad27928 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4161187549 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.4161187549 |
| Directory | /workspace/12.edn_intr/latest |
| Test location | /workspace/coverage/default/12.edn_smoke.2479887749 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 14564315 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:53:01 PM PST 24 |
| Finished | Jan 21 12:53:03 PM PST 24 |
| Peak memory | 204308 kb |
| Host | smart-0af50fc4-6776-4197-8429-651986bccee7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2479887749 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2479887749 |
| Directory | /workspace/12.edn_smoke/latest |
| Test location | /workspace/coverage/default/12.edn_stress_all.1087632760 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 117611828 ps |
| CPU time | 1.83 seconds |
| Started | Jan 21 12:53:03 PM PST 24 |
| Finished | Jan 21 12:53:06 PM PST 24 |
| Peak memory | 205104 kb |
| Host | smart-7a1a0bde-3725-48d1-815e-8a8f0ca5a97a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087632760 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1087632760 |
| Directory | /workspace/12.edn_stress_all/latest |
| Test location | /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2978315692 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 23621308746 ps |
| CPU time | 272.98 seconds |
| Started | Jan 21 12:53:02 PM PST 24 |
| Finished | Jan 21 12:57:37 PM PST 24 |
| Peak memory | 215184 kb |
| Host | smart-ec06b996-7cab-47d3-bcc9-45636c9d3174 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978315692 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2978315692 |
| Directory | /workspace/12.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/121.edn_genbits.1023274199 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 45237019 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 01:09:35 PM PST 24 |
| Finished | Jan 21 01:09:37 PM PST 24 |
| Peak memory | 205336 kb |
| Host | smart-37c5c35d-0249-4460-bead-a35eee969a13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1023274199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1023274199 |
| Directory | /workspace/121.edn_genbits/latest |
| Test location | /workspace/coverage/default/122.edn_genbits.1796299186 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 34317367 ps |
| CPU time | 1.57 seconds |
| Started | Jan 21 12:59:16 PM PST 24 |
| Finished | Jan 21 12:59:20 PM PST 24 |
| Peak memory | 213684 kb |
| Host | smart-d2713b1d-afc3-4a61-8f99-e7114ef98aee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1796299186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1796299186 |
| Directory | /workspace/122.edn_genbits/latest |
| Test location | /workspace/coverage/default/123.edn_genbits.2290683366 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 50542497 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 12:59:20 PM PST 24 |
| Finished | Jan 21 12:59:26 PM PST 24 |
| Peak memory | 204556 kb |
| Host | smart-310b1a7b-9328-4661-823c-b5e892aa8434 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2290683366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2290683366 |
| Directory | /workspace/123.edn_genbits/latest |
| Test location | /workspace/coverage/default/124.edn_genbits.1066885458 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 204605255 ps |
| CPU time | 2.66 seconds |
| Started | Jan 21 12:59:11 PM PST 24 |
| Finished | Jan 21 12:59:15 PM PST 24 |
| Peak memory | 213756 kb |
| Host | smart-60a589d7-4be9-4c9d-a6df-38fa67841336 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1066885458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1066885458 |
| Directory | /workspace/124.edn_genbits/latest |
| Test location | /workspace/coverage/default/125.edn_genbits.1815912167 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 121285273 ps |
| CPU time | 1.18 seconds |
| Started | Jan 21 12:59:09 PM PST 24 |
| Finished | Jan 21 12:59:11 PM PST 24 |
| Peak memory | 213728 kb |
| Host | smart-39f6bd77-92a4-4d99-aca6-e6bd09788b08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1815912167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1815912167 |
| Directory | /workspace/125.edn_genbits/latest |
| Test location | /workspace/coverage/default/126.edn_genbits.4214342533 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 12783396 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:59:10 PM PST 24 |
| Finished | Jan 21 12:59:13 PM PST 24 |
| Peak memory | 204636 kb |
| Host | smart-4de22851-6f1e-431c-be66-ef767540bde9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4214342533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.4214342533 |
| Directory | /workspace/126.edn_genbits/latest |
| Test location | /workspace/coverage/default/128.edn_genbits.4231678142 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 28574501 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 12:59:10 PM PST 24 |
| Finished | Jan 21 12:59:13 PM PST 24 |
| Peak memory | 204644 kb |
| Host | smart-56f31546-a27f-449c-bdc6-efe353adf233 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4231678142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.4231678142 |
| Directory | /workspace/128.edn_genbits/latest |
| Test location | /workspace/coverage/default/129.edn_genbits.4275457691 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 14621524 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 12:59:16 PM PST 24 |
| Finished | Jan 21 12:59:19 PM PST 24 |
| Peak memory | 204076 kb |
| Host | smart-f369ba9e-6857-4bf0-b7e4-b3a093c9bf8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4275457691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.4275457691 |
| Directory | /workspace/129.edn_genbits/latest |
| Test location | /workspace/coverage/default/13.edn_alert_test.4072559164 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 54905982 ps |
| CPU time | 1.12 seconds |
| Started | Jan 21 12:53:26 PM PST 24 |
| Finished | Jan 21 12:53:30 PM PST 24 |
| Peak memory | 204244 kb |
| Host | smart-f2fd52ca-5edc-4936-ac34-9d59f6ffe9c3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072559164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.4072559164 |
| Directory | /workspace/13.edn_alert_test/latest |
| Test location | /workspace/coverage/default/13.edn_disable.2997034039 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 17684137 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 12:53:10 PM PST 24 |
| Finished | Jan 21 12:53:11 PM PST 24 |
| Peak memory | 213956 kb |
| Host | smart-be287c69-5330-4652-8e20-b0695a354fab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997034039 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2997034039 |
| Directory | /workspace/13.edn_disable/latest |
| Test location | /workspace/coverage/default/13.edn_disable_auto_req_mode.281465430 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 70496935 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 01:28:08 PM PST 24 |
| Finished | Jan 21 01:28:10 PM PST 24 |
| Peak memory | 214108 kb |
| Host | smart-73818dc5-db76-42fc-bf39-981efcdb9f5e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281465430 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di sable_auto_req_mode.281465430 |
| Directory | /workspace/13.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/13.edn_err.1305856974 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 31126508 ps |
| CPU time | 1.05 seconds |
| Started | Jan 21 12:53:03 PM PST 24 |
| Finished | Jan 21 12:53:05 PM PST 24 |
| Peak memory | 220912 kb |
| Host | smart-47ad1c4a-b0cb-4094-ac3e-64853a7b57aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1305856974 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1305856974 |
| Directory | /workspace/13.edn_err/latest |
| Test location | /workspace/coverage/default/13.edn_genbits.2315342678 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 58680383 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:53:03 PM PST 24 |
| Finished | Jan 21 12:53:05 PM PST 24 |
| Peak memory | 204404 kb |
| Host | smart-f01bf927-da6b-41a0-ae61-0d4ab4c91fc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2315342678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2315342678 |
| Directory | /workspace/13.edn_genbits/latest |
| Test location | /workspace/coverage/default/13.edn_intr.4026493276 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29301443 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:53:01 PM PST 24 |
| Finished | Jan 21 12:53:03 PM PST 24 |
| Peak memory | 214028 kb |
| Host | smart-8e8a4270-f567-40ae-9eb8-ee58f7cd11ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4026493276 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.4026493276 |
| Directory | /workspace/13.edn_intr/latest |
| Test location | /workspace/coverage/default/13.edn_smoke.3045689303 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 97337863 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:53:06 PM PST 24 |
| Finished | Jan 21 12:53:08 PM PST 24 |
| Peak memory | 204408 kb |
| Host | smart-3c834ee1-df68-43ad-8223-5a4077ec1c03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3045689303 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3045689303 |
| Directory | /workspace/13.edn_smoke/latest |
| Test location | /workspace/coverage/default/13.edn_stress_all.73119016 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 765481304 ps |
| CPU time | 4.1 seconds |
| Started | Jan 21 01:15:54 PM PST 24 |
| Finished | Jan 21 01:15:59 PM PST 24 |
| Peak memory | 205536 kb |
| Host | smart-87f29b90-4eeb-47cb-95a5-20c9e66262c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73119016 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.73119016 |
| Directory | /workspace/13.edn_stress_all/latest |
| Test location | /workspace/coverage/default/13.edn_stress_all_with_rand_reset.653949762 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 17853347804 ps |
| CPU time | 396.02 seconds |
| Started | Jan 21 01:45:21 PM PST 24 |
| Finished | Jan 21 01:51:59 PM PST 24 |
| Peak memory | 215248 kb |
| Host | smart-565e82ec-04eb-4372-a5ec-0d750263cd90 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653949762 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.653949762 |
| Directory | /workspace/13.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/131.edn_genbits.574392831 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 37134639 ps |
| CPU time | 1.14 seconds |
| Started | Jan 21 12:59:10 PM PST 24 |
| Finished | Jan 21 12:59:13 PM PST 24 |
| Peak memory | 213720 kb |
| Host | smart-588fc16f-3a4b-40bd-b137-6b6ff4842b66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=574392831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.574392831 |
| Directory | /workspace/131.edn_genbits/latest |
| Test location | /workspace/coverage/default/132.edn_genbits.366415811 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 56266489 ps |
| CPU time | 1.17 seconds |
| Started | Jan 21 12:59:10 PM PST 24 |
| Finished | Jan 21 12:59:14 PM PST 24 |
| Peak memory | 213796 kb |
| Host | smart-5f2157e5-fa92-4eb8-8112-4c00b76801a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=366415811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.366415811 |
| Directory | /workspace/132.edn_genbits/latest |
| Test location | /workspace/coverage/default/133.edn_genbits.3979540498 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 62184243 ps |
| CPU time | 1.62 seconds |
| Started | Jan 21 12:59:17 PM PST 24 |
| Finished | Jan 21 12:59:25 PM PST 24 |
| Peak memory | 213724 kb |
| Host | smart-d0940920-327b-4d44-bfd3-857f1a978209 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3979540498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3979540498 |
| Directory | /workspace/133.edn_genbits/latest |
| Test location | /workspace/coverage/default/134.edn_genbits.496408132 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 68936718 ps |
| CPU time | 2.73 seconds |
| Started | Jan 21 12:59:09 PM PST 24 |
| Finished | Jan 21 12:59:14 PM PST 24 |
| Peak memory | 213748 kb |
| Host | smart-6e91ee80-f4a3-449a-9358-4d3ed23db6c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=496408132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.496408132 |
| Directory | /workspace/134.edn_genbits/latest |
| Test location | /workspace/coverage/default/135.edn_genbits.3025612353 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 97164790 ps |
| CPU time | 2.17 seconds |
| Started | Jan 21 12:59:11 PM PST 24 |
| Finished | Jan 21 12:59:15 PM PST 24 |
| Peak memory | 213708 kb |
| Host | smart-1fa7aa37-a6a9-4cd6-bb23-57cd4a7e6485 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3025612353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.3025612353 |
| Directory | /workspace/135.edn_genbits/latest |
| Test location | /workspace/coverage/default/137.edn_genbits.2466475297 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 164925729 ps |
| CPU time | 2.04 seconds |
| Started | Jan 21 12:59:20 PM PST 24 |
| Finished | Jan 21 12:59:27 PM PST 24 |
| Peak memory | 213364 kb |
| Host | smart-d8352255-b9bf-4675-952d-3d5e8f7c17b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2466475297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2466475297 |
| Directory | /workspace/137.edn_genbits/latest |
| Test location | /workspace/coverage/default/138.edn_genbits.4265484618 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 25635539 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:59:20 PM PST 24 |
| Finished | Jan 21 12:59:26 PM PST 24 |
| Peak memory | 204920 kb |
| Host | smart-9e3c3329-361f-43cd-9d63-3ccf345f0d9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4265484618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.4265484618 |
| Directory | /workspace/138.edn_genbits/latest |
| Test location | /workspace/coverage/default/139.edn_genbits.3824538378 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 72860325 ps |
| CPU time | 1.84 seconds |
| Started | Jan 21 12:59:22 PM PST 24 |
| Finished | Jan 21 12:59:27 PM PST 24 |
| Peak memory | 213892 kb |
| Host | smart-2f7142b2-cef3-4c4b-8cc1-50eb519d69e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3824538378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3824538378 |
| Directory | /workspace/139.edn_genbits/latest |
| Test location | /workspace/coverage/default/14.edn_alert.2961406545 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 80054855 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 01:04:13 PM PST 24 |
| Finished | Jan 21 01:04:15 PM PST 24 |
| Peak memory | 204732 kb |
| Host | smart-6bd14c92-52e6-40ac-ba02-448d43621902 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961406545 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2961406545 |
| Directory | /workspace/14.edn_alert/latest |
| Test location | /workspace/coverage/default/14.edn_alert_test.2679911669 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 24370444 ps |
| CPU time | 0.8 seconds |
| Started | Jan 21 12:53:26 PM PST 24 |
| Finished | Jan 21 12:53:30 PM PST 24 |
| Peak memory | 203812 kb |
| Host | smart-224098ee-7079-47f0-95a2-3577d83edfbc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679911669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2679911669 |
| Directory | /workspace/14.edn_alert_test/latest |
| Test location | /workspace/coverage/default/14.edn_disable.3834880859 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 19578728 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 01:13:38 PM PST 24 |
| Finished | Jan 21 01:13:42 PM PST 24 |
| Peak memory | 214032 kb |
| Host | smart-2057e21a-dbf6-4efd-9439-ffd35319be97 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834880859 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3834880859 |
| Directory | /workspace/14.edn_disable/latest |
| Test location | /workspace/coverage/default/14.edn_disable_auto_req_mode.266516184 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 41175282 ps |
| CPU time | 1 seconds |
| Started | Jan 21 12:53:24 PM PST 24 |
| Finished | Jan 21 12:53:28 PM PST 24 |
| Peak memory | 214256 kb |
| Host | smart-6b41c1a3-e5df-473b-a105-f9ac64140139 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266516184 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di sable_auto_req_mode.266516184 |
| Directory | /workspace/14.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/14.edn_err.1500881537 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 36519559 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 12:53:28 PM PST 24 |
| Finished | Jan 21 12:53:32 PM PST 24 |
| Peak memory | 215044 kb |
| Host | smart-0ffc4556-5986-42a0-84f9-89d89876ad67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1500881537 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1500881537 |
| Directory | /workspace/14.edn_err/latest |
| Test location | /workspace/coverage/default/14.edn_genbits.3281929415 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 94567626 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 12:53:26 PM PST 24 |
| Finished | Jan 21 12:53:30 PM PST 24 |
| Peak memory | 213724 kb |
| Host | smart-ffea2faa-5e60-4cbf-9120-39a1710005d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3281929415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3281929415 |
| Directory | /workspace/14.edn_genbits/latest |
| Test location | /workspace/coverage/default/14.edn_intr.252978798 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 18580677 ps |
| CPU time | 1.03 seconds |
| Started | Jan 21 12:53:25 PM PST 24 |
| Finished | Jan 21 12:53:28 PM PST 24 |
| Peak memory | 214140 kb |
| Host | smart-e1a19df2-1a7b-4c5a-a6ae-f6c1e1524688 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=252978798 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.252978798 |
| Directory | /workspace/14.edn_intr/latest |
| Test location | /workspace/coverage/default/14.edn_smoke.1352135072 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 21522182 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:53:25 PM PST 24 |
| Finished | Jan 21 12:53:28 PM PST 24 |
| Peak memory | 204420 kb |
| Host | smart-1271474e-e28d-4266-864b-5f2e269015cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1352135072 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1352135072 |
| Directory | /workspace/14.edn_smoke/latest |
| Test location | /workspace/coverage/default/140.edn_genbits.2659774317 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 20530712 ps |
| CPU time | 1.21 seconds |
| Started | Jan 21 12:59:24 PM PST 24 |
| Finished | Jan 21 12:59:29 PM PST 24 |
| Peak memory | 205204 kb |
| Host | smart-146126d9-44f5-4c3e-8a64-4373420a226c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2659774317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2659774317 |
| Directory | /workspace/140.edn_genbits/latest |
| Test location | /workspace/coverage/default/141.edn_genbits.692960924 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 172211115 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:59:23 PM PST 24 |
| Finished | Jan 21 12:59:27 PM PST 24 |
| Peak memory | 204512 kb |
| Host | smart-0faca780-dc59-4e3d-8ec0-3a4222e273cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=692960924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.692960924 |
| Directory | /workspace/141.edn_genbits/latest |
| Test location | /workspace/coverage/default/142.edn_genbits.2732665093 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 20522523 ps |
| CPU time | 1.15 seconds |
| Started | Jan 21 12:59:19 PM PST 24 |
| Finished | Jan 21 12:59:26 PM PST 24 |
| Peak memory | 213784 kb |
| Host | smart-34820e8b-91ae-4af3-a680-6e85873fe3e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2732665093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2732665093 |
| Directory | /workspace/142.edn_genbits/latest |
| Test location | /workspace/coverage/default/143.edn_genbits.1740889635 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 30839002 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 12:59:23 PM PST 24 |
| Finished | Jan 21 12:59:26 PM PST 24 |
| Peak memory | 205428 kb |
| Host | smart-00902ead-f9f6-43e2-ad07-8bb5da362f10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1740889635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1740889635 |
| Directory | /workspace/143.edn_genbits/latest |
| Test location | /workspace/coverage/default/145.edn_genbits.1265309944 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 46149655 ps |
| CPU time | 1 seconds |
| Started | Jan 21 12:59:20 PM PST 24 |
| Finished | Jan 21 12:59:26 PM PST 24 |
| Peak memory | 213772 kb |
| Host | smart-24bb2973-51fc-48f4-8ec6-e615ec7e99de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1265309944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1265309944 |
| Directory | /workspace/145.edn_genbits/latest |
| Test location | /workspace/coverage/default/146.edn_genbits.1630595135 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 115706033 ps |
| CPU time | 1.1 seconds |
| Started | Jan 21 12:59:18 PM PST 24 |
| Finished | Jan 21 12:59:25 PM PST 24 |
| Peak memory | 205112 kb |
| Host | smart-a0f78b6c-1784-4353-b060-1836072b461d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1630595135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1630595135 |
| Directory | /workspace/146.edn_genbits/latest |
| Test location | /workspace/coverage/default/148.edn_genbits.2913885753 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 181167103 ps |
| CPU time | 2.61 seconds |
| Started | Jan 21 12:59:18 PM PST 24 |
| Finished | Jan 21 12:59:26 PM PST 24 |
| Peak memory | 213804 kb |
| Host | smart-51f96405-4c0a-4f6b-b7c3-be3165662073 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2913885753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2913885753 |
| Directory | /workspace/148.edn_genbits/latest |
| Test location | /workspace/coverage/default/149.edn_genbits.52078634 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 281396041 ps |
| CPU time | 1.3 seconds |
| Started | Jan 21 01:32:09 PM PST 24 |
| Finished | Jan 21 01:32:12 PM PST 24 |
| Peak memory | 213804 kb |
| Host | smart-f2db0df1-01bd-4c90-bc7a-a92ab9098891 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52078634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.52078634 |
| Directory | /workspace/149.edn_genbits/latest |
| Test location | /workspace/coverage/default/15.edn_alert.280690439 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 52483424 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:53:40 PM PST 24 |
| Finished | Jan 21 12:53:45 PM PST 24 |
| Peak memory | 204584 kb |
| Host | smart-c9330dec-770a-469f-b87a-a4ad4c95c673 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=280690439 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.280690439 |
| Directory | /workspace/15.edn_alert/latest |
| Test location | /workspace/coverage/default/15.edn_alert_test.1748994814 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 39546665 ps |
| CPU time | 0.81 seconds |
| Started | Jan 21 12:53:39 PM PST 24 |
| Finished | Jan 21 12:53:45 PM PST 24 |
| Peak memory | 203828 kb |
| Host | smart-dc7d3368-e509-4d72-90a3-6f8fd867ff19 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748994814 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1748994814 |
| Directory | /workspace/15.edn_alert_test/latest |
| Test location | /workspace/coverage/default/15.edn_disable.1918249823 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 29176160 ps |
| CPU time | 0.79 seconds |
| Started | Jan 21 12:53:37 PM PST 24 |
| Finished | Jan 21 12:53:43 PM PST 24 |
| Peak memory | 213804 kb |
| Host | smart-7afea183-8ce7-4f89-9ca7-ccb495ca56ff |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918249823 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.1918249823 |
| Directory | /workspace/15.edn_disable/latest |
| Test location | /workspace/coverage/default/15.edn_disable_auto_req_mode.4239373508 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 19908816 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 12:53:39 PM PST 24 |
| Finished | Jan 21 12:53:46 PM PST 24 |
| Peak memory | 214076 kb |
| Host | smart-26df5db1-0fe8-4f6c-be42-7f6204f17869 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239373508 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d isable_auto_req_mode.4239373508 |
| Directory | /workspace/15.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/15.edn_err.2234496738 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 25680107 ps |
| CPU time | 1.22 seconds |
| Started | Jan 21 12:53:38 PM PST 24 |
| Finished | Jan 21 12:53:46 PM PST 24 |
| Peak memory | 221260 kb |
| Host | smart-a0b4288d-0e6d-42ee-9c91-b83a602969f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2234496738 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2234496738 |
| Directory | /workspace/15.edn_err/latest |
| Test location | /workspace/coverage/default/15.edn_genbits.2388397754 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 23475640 ps |
| CPU time | 1.12 seconds |
| Started | Jan 21 12:53:25 PM PST 24 |
| Finished | Jan 21 12:53:28 PM PST 24 |
| Peak memory | 213688 kb |
| Host | smart-f8ea6fbe-70e7-470f-af3b-30e5c968c9eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2388397754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2388397754 |
| Directory | /workspace/15.edn_genbits/latest |
| Test location | /workspace/coverage/default/15.edn_smoke.1498545755 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 23337535 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:53:27 PM PST 24 |
| Finished | Jan 21 12:53:30 PM PST 24 |
| Peak memory | 204188 kb |
| Host | smart-1ef0c04d-9dc6-4991-883a-9ae2c57d47be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1498545755 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1498545755 |
| Directory | /workspace/15.edn_smoke/latest |
| Test location | /workspace/coverage/default/15.edn_stress_all.2786431757 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 183382111 ps |
| CPU time | 1.09 seconds |
| Started | Jan 21 12:53:26 PM PST 24 |
| Finished | Jan 21 12:53:30 PM PST 24 |
| Peak memory | 204736 kb |
| Host | smart-dbc6767c-1ac6-4115-af66-2a975c793651 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786431757 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2786431757 |
| Directory | /workspace/15.edn_stress_all/latest |
| Test location | /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3871683904 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 107258324537 ps |
| CPU time | 1154.24 seconds |
| Started | Jan 21 01:10:44 PM PST 24 |
| Finished | Jan 21 01:30:01 PM PST 24 |
| Peak memory | 216488 kb |
| Host | smart-c51ddfc3-b4b7-4526-a60d-7ca1961d3542 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871683904 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3871683904 |
| Directory | /workspace/15.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/151.edn_genbits.3863090892 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 130667472 ps |
| CPU time | 2.92 seconds |
| Started | Jan 21 12:59:23 PM PST 24 |
| Finished | Jan 21 12:59:28 PM PST 24 |
| Peak memory | 213804 kb |
| Host | smart-511e0854-3968-4a9f-807d-ca93f8bceb47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3863090892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3863090892 |
| Directory | /workspace/151.edn_genbits/latest |
| Test location | /workspace/coverage/default/153.edn_genbits.3500315791 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 72909087 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 12:59:24 PM PST 24 |
| Finished | Jan 21 12:59:29 PM PST 24 |
| Peak memory | 205276 kb |
| Host | smart-9c610636-94f6-4584-a0e9-5708e347bdf8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3500315791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3500315791 |
| Directory | /workspace/153.edn_genbits/latest |
| Test location | /workspace/coverage/default/154.edn_genbits.2294469652 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 75680201 ps |
| CPU time | 1.88 seconds |
| Started | Jan 21 01:03:27 PM PST 24 |
| Finished | Jan 21 01:03:30 PM PST 24 |
| Peak memory | 213828 kb |
| Host | smart-e1c27763-05e2-42b0-b2ff-f7a7391aff32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2294469652 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.2294469652 |
| Directory | /workspace/154.edn_genbits/latest |
| Test location | /workspace/coverage/default/155.edn_genbits.2323065732 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 21201111 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 12:59:17 PM PST 24 |
| Finished | Jan 21 12:59:20 PM PST 24 |
| Peak memory | 204868 kb |
| Host | smart-e7e62247-b88f-410c-82c2-1c7d9c4d18f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2323065732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2323065732 |
| Directory | /workspace/155.edn_genbits/latest |
| Test location | /workspace/coverage/default/157.edn_genbits.854610714 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 33812978 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:59:24 PM PST 24 |
| Finished | Jan 21 12:59:29 PM PST 24 |
| Peak memory | 205004 kb |
| Host | smart-8c629dea-3481-4f7b-ba1d-e2236edc79f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854610714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.854610714 |
| Directory | /workspace/157.edn_genbits/latest |
| Test location | /workspace/coverage/default/158.edn_genbits.884781386 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 22143881 ps |
| CPU time | 1.09 seconds |
| Started | Jan 21 12:59:27 PM PST 24 |
| Finished | Jan 21 12:59:30 PM PST 24 |
| Peak memory | 205140 kb |
| Host | smart-edf86448-1438-4e6d-a0d9-3e4c9d44666e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=884781386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.884781386 |
| Directory | /workspace/158.edn_genbits/latest |
| Test location | /workspace/coverage/default/159.edn_genbits.3091071985 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 49813450 ps |
| CPU time | 1 seconds |
| Started | Jan 21 12:59:31 PM PST 24 |
| Finished | Jan 21 12:59:33 PM PST 24 |
| Peak memory | 205208 kb |
| Host | smart-a058265b-4ec8-45f5-b156-9e251aa2e96b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091071985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3091071985 |
| Directory | /workspace/159.edn_genbits/latest |
| Test location | /workspace/coverage/default/16.edn_alert_test.3865464594 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 28310271 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 12:53:46 PM PST 24 |
| Finished | Jan 21 12:53:50 PM PST 24 |
| Peak memory | 204088 kb |
| Host | smart-788498f5-432b-4922-b595-1000e41e193b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865464594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3865464594 |
| Directory | /workspace/16.edn_alert_test/latest |
| Test location | /workspace/coverage/default/16.edn_disable.2102536035 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 24129065 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 12:53:42 PM PST 24 |
| Finished | Jan 21 12:53:46 PM PST 24 |
| Peak memory | 213972 kb |
| Host | smart-49eb3cca-8a63-4aab-a24b-092fc4c8dd8b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102536035 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2102536035 |
| Directory | /workspace/16.edn_disable/latest |
| Test location | /workspace/coverage/default/16.edn_disable_auto_req_mode.1571835642 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 16140111 ps |
| CPU time | 0.94 seconds |
| Started | Jan 21 12:53:39 PM PST 24 |
| Finished | Jan 21 12:53:45 PM PST 24 |
| Peak memory | 214092 kb |
| Host | smart-0716f5b3-beb4-4478-8658-2ee30e2ecad5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571835642 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d isable_auto_req_mode.1571835642 |
| Directory | /workspace/16.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/16.edn_err.1257519297 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 19653417 ps |
| CPU time | 1.04 seconds |
| Started | Jan 21 01:33:03 PM PST 24 |
| Finished | Jan 21 01:33:09 PM PST 24 |
| Peak memory | 215540 kb |
| Host | smart-67128fb4-50aa-4b70-8859-77f499d089dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1257519297 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1257519297 |
| Directory | /workspace/16.edn_err/latest |
| Test location | /workspace/coverage/default/16.edn_genbits.482700218 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 24712635 ps |
| CPU time | 1.17 seconds |
| Started | Jan 21 12:53:40 PM PST 24 |
| Finished | Jan 21 12:53:46 PM PST 24 |
| Peak memory | 213676 kb |
| Host | smart-b56a7628-57bf-4ddd-bb7e-6ddd90972da4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=482700218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.482700218 |
| Directory | /workspace/16.edn_genbits/latest |
| Test location | /workspace/coverage/default/16.edn_intr.3726292314 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 18881425 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:53:46 PM PST 24 |
| Finished | Jan 21 12:53:50 PM PST 24 |
| Peak memory | 213992 kb |
| Host | smart-5f8fe82f-4655-441b-8c04-d7be479b93e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3726292314 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3726292314 |
| Directory | /workspace/16.edn_intr/latest |
| Test location | /workspace/coverage/default/16.edn_smoke.1482973404 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 12188949 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:53:42 PM PST 24 |
| Finished | Jan 21 12:53:46 PM PST 24 |
| Peak memory | 204384 kb |
| Host | smart-f91032f5-ea7e-4e49-b53e-b2f1bc2b8a38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1482973404 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1482973404 |
| Directory | /workspace/16.edn_smoke/latest |
| Test location | /workspace/coverage/default/16.edn_stress_all.1368231535 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 57177444 ps |
| CPU time | 1.17 seconds |
| Started | Jan 21 01:08:05 PM PST 24 |
| Finished | Jan 21 01:08:08 PM PST 24 |
| Peak memory | 205220 kb |
| Host | smart-d0e1195e-9046-4424-9119-0cfd0f4610ef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368231535 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1368231535 |
| Directory | /workspace/16.edn_stress_all/latest |
| Test location | /workspace/coverage/default/16.edn_stress_all_with_rand_reset.633285843 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 48813416632 ps |
| CPU time | 564.71 seconds |
| Started | Jan 21 12:53:46 PM PST 24 |
| Finished | Jan 21 01:03:14 PM PST 24 |
| Peak memory | 214252 kb |
| Host | smart-d718a88d-800b-4d87-9025-5c75adad4b78 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633285843 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.633285843 |
| Directory | /workspace/16.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/160.edn_genbits.455553726 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 49556212 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 12:59:29 PM PST 24 |
| Finished | Jan 21 12:59:31 PM PST 24 |
| Peak memory | 204420 kb |
| Host | smart-774279e8-465b-4a47-b505-b56408be202d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=455553726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.455553726 |
| Directory | /workspace/160.edn_genbits/latest |
| Test location | /workspace/coverage/default/162.edn_genbits.2088649227 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 140731394 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 12:59:31 PM PST 24 |
| Finished | Jan 21 12:59:34 PM PST 24 |
| Peak memory | 205160 kb |
| Host | smart-cc89503a-2f6f-40ad-8ccd-71a93d896a9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2088649227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.2088649227 |
| Directory | /workspace/162.edn_genbits/latest |
| Test location | /workspace/coverage/default/164.edn_genbits.2996745601 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 19317028 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 12:59:27 PM PST 24 |
| Finished | Jan 21 12:59:30 PM PST 24 |
| Peak memory | 204812 kb |
| Host | smart-cc6ba663-0918-4355-96e9-4562c507cd97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2996745601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2996745601 |
| Directory | /workspace/164.edn_genbits/latest |
| Test location | /workspace/coverage/default/165.edn_genbits.852092207 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 19116819 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:59:26 PM PST 24 |
| Finished | Jan 21 12:59:30 PM PST 24 |
| Peak memory | 204796 kb |
| Host | smart-9b4a7e83-22a7-4d32-853c-d5406ea76a0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=852092207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.852092207 |
| Directory | /workspace/165.edn_genbits/latest |
| Test location | /workspace/coverage/default/166.edn_genbits.1200017263 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 32393368 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:59:32 PM PST 24 |
| Finished | Jan 21 12:59:35 PM PST 24 |
| Peak memory | 213796 kb |
| Host | smart-24f533fb-a646-4a5b-8330-776640d70f7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1200017263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1200017263 |
| Directory | /workspace/166.edn_genbits/latest |
| Test location | /workspace/coverage/default/168.edn_genbits.1923700448 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 19519051 ps |
| CPU time | 1.04 seconds |
| Started | Jan 21 12:59:28 PM PST 24 |
| Finished | Jan 21 12:59:30 PM PST 24 |
| Peak memory | 204700 kb |
| Host | smart-733449ba-4178-497d-8311-aec464b4ecd4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1923700448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1923700448 |
| Directory | /workspace/168.edn_genbits/latest |
| Test location | /workspace/coverage/default/169.edn_genbits.2047206136 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 63694638 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 12:59:32 PM PST 24 |
| Finished | Jan 21 12:59:35 PM PST 24 |
| Peak memory | 205160 kb |
| Host | smart-63f76f79-d0dc-42d4-8384-255e8b2e30c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2047206136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2047206136 |
| Directory | /workspace/169.edn_genbits/latest |
| Test location | /workspace/coverage/default/17.edn_alert.4198662266 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 240217803 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 12:53:55 PM PST 24 |
| Finished | Jan 21 12:53:56 PM PST 24 |
| Peak memory | 204508 kb |
| Host | smart-2cfecd51-4d73-4ea8-afd0-9df60e1edfa6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4198662266 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.4198662266 |
| Directory | /workspace/17.edn_alert/latest |
| Test location | /workspace/coverage/default/17.edn_alert_test.1629667689 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 179202458 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:53:55 PM PST 24 |
| Finished | Jan 21 12:53:57 PM PST 24 |
| Peak memory | 204388 kb |
| Host | smart-dbde462c-758e-47d2-afea-1acc19fb4be1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629667689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1629667689 |
| Directory | /workspace/17.edn_alert_test/latest |
| Test location | /workspace/coverage/default/17.edn_disable.1080951349 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 10681586 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:53:50 PM PST 24 |
| Finished | Jan 21 12:53:52 PM PST 24 |
| Peak memory | 214328 kb |
| Host | smart-7648b49e-885b-487c-878a-a39ed75119a6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080951349 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1080951349 |
| Directory | /workspace/17.edn_disable/latest |
| Test location | /workspace/coverage/default/17.edn_disable_auto_req_mode.781197074 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 36259267 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:53:55 PM PST 24 |
| Finished | Jan 21 12:53:57 PM PST 24 |
| Peak memory | 214216 kb |
| Host | smart-5e38f0ef-9f1e-4de6-a30e-edf445d0596d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781197074 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di sable_auto_req_mode.781197074 |
| Directory | /workspace/17.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/17.edn_err.2102001466 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 63239870 ps |
| CPU time | 1.01 seconds |
| Started | Jan 21 12:53:51 PM PST 24 |
| Finished | Jan 21 12:53:53 PM PST 24 |
| Peak memory | 215272 kb |
| Host | smart-b8ac174f-65d1-4e12-8102-4548cd4fe002 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2102001466 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.2102001466 |
| Directory | /workspace/17.edn_err/latest |
| Test location | /workspace/coverage/default/17.edn_genbits.4122383936 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 30239278 ps |
| CPU time | 1.37 seconds |
| Started | Jan 21 12:53:50 PM PST 24 |
| Finished | Jan 21 12:53:53 PM PST 24 |
| Peak memory | 213708 kb |
| Host | smart-d60728d7-53a9-4c63-a95b-6e64449f0fe6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4122383936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.4122383936 |
| Directory | /workspace/17.edn_genbits/latest |
| Test location | /workspace/coverage/default/17.edn_intr.1957656204 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 18223785 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:53:53 PM PST 24 |
| Finished | Jan 21 12:53:55 PM PST 24 |
| Peak memory | 214068 kb |
| Host | smart-c78402a6-2a5b-4d55-869a-82bade96aa8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1957656204 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1957656204 |
| Directory | /workspace/17.edn_intr/latest |
| Test location | /workspace/coverage/default/17.edn_smoke.1112007957 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 28340909 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:53:45 PM PST 24 |
| Finished | Jan 21 12:53:50 PM PST 24 |
| Peak memory | 204348 kb |
| Host | smart-2d2f62c9-cb31-4fa8-a726-f10eeb6f2404 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112007957 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1112007957 |
| Directory | /workspace/17.edn_smoke/latest |
| Test location | /workspace/coverage/default/17.edn_stress_all.1190242353 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 275407348 ps |
| CPU time | 2.06 seconds |
| Started | Jan 21 12:53:48 PM PST 24 |
| Finished | Jan 21 12:53:52 PM PST 24 |
| Peak memory | 205180 kb |
| Host | smart-fad3ea0a-bc20-474d-8675-2d08898584cf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190242353 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1190242353 |
| Directory | /workspace/17.edn_stress_all/latest |
| Test location | /workspace/coverage/default/17.edn_stress_all_with_rand_reset.466085942 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 249575677397 ps |
| CPU time | 406.88 seconds |
| Started | Jan 21 12:53:52 PM PST 24 |
| Finished | Jan 21 01:00:40 PM PST 24 |
| Peak memory | 215172 kb |
| Host | smart-80dabb35-d22d-4784-8c3f-818df00cebac |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466085942 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.466085942 |
| Directory | /workspace/17.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/170.edn_genbits.793937289 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 36833780 ps |
| CPU time | 1.01 seconds |
| Started | Jan 21 12:59:31 PM PST 24 |
| Finished | Jan 21 12:59:33 PM PST 24 |
| Peak memory | 204904 kb |
| Host | smart-3eaac5e1-7475-4072-94c6-5799c0845302 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=793937289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.793937289 |
| Directory | /workspace/170.edn_genbits/latest |
| Test location | /workspace/coverage/default/171.edn_genbits.4063888905 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 55013387 ps |
| CPU time | 0.94 seconds |
| Started | Jan 21 12:59:28 PM PST 24 |
| Finished | Jan 21 12:59:30 PM PST 24 |
| Peak memory | 204672 kb |
| Host | smart-367b8d4a-bbfc-4a33-bbe2-e83eccf62f4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4063888905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.4063888905 |
| Directory | /workspace/171.edn_genbits/latest |
| Test location | /workspace/coverage/default/172.edn_genbits.690794114 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 15663153 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 12:59:26 PM PST 24 |
| Finished | Jan 21 12:59:30 PM PST 24 |
| Peak memory | 204828 kb |
| Host | smart-3a02f220-249d-42a7-a71a-3f92d90f56c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=690794114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.690794114 |
| Directory | /workspace/172.edn_genbits/latest |
| Test location | /workspace/coverage/default/173.edn_genbits.505139771 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 64552695 ps |
| CPU time | 2.31 seconds |
| Started | Jan 21 12:59:40 PM PST 24 |
| Finished | Jan 21 12:59:46 PM PST 24 |
| Peak memory | 213056 kb |
| Host | smart-510fef40-ae49-4e38-ae56-ee9a6ad36d50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=505139771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.505139771 |
| Directory | /workspace/173.edn_genbits/latest |
| Test location | /workspace/coverage/default/174.edn_genbits.100620251 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 101207777 ps |
| CPU time | 1 seconds |
| Started | Jan 21 12:59:28 PM PST 24 |
| Finished | Jan 21 12:59:30 PM PST 24 |
| Peak memory | 204996 kb |
| Host | smart-7adce0aa-5615-4ae6-b2a5-4740397428e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=100620251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.100620251 |
| Directory | /workspace/174.edn_genbits/latest |
| Test location | /workspace/coverage/default/176.edn_genbits.3997694946 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 90962394 ps |
| CPU time | 1.31 seconds |
| Started | Jan 21 12:59:38 PM PST 24 |
| Finished | Jan 21 12:59:41 PM PST 24 |
| Peak memory | 213768 kb |
| Host | smart-b3744903-8500-4010-af4b-c79b439ef5df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3997694946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3997694946 |
| Directory | /workspace/176.edn_genbits/latest |
| Test location | /workspace/coverage/default/18.edn_alert.2987888068 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 123337206 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 01:21:10 PM PST 24 |
| Finished | Jan 21 01:21:12 PM PST 24 |
| Peak memory | 204780 kb |
| Host | smart-966c64af-2e6f-4fc0-b786-4240bd8232dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2987888068 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2987888068 |
| Directory | /workspace/18.edn_alert/latest |
| Test location | /workspace/coverage/default/18.edn_alert_test.261008679 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 15057055 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:53:59 PM PST 24 |
| Finished | Jan 21 12:54:01 PM PST 24 |
| Peak memory | 204084 kb |
| Host | smart-90729381-03ff-45e2-a4d1-506a13019021 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261008679 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.261008679 |
| Directory | /workspace/18.edn_alert_test/latest |
| Test location | /workspace/coverage/default/18.edn_disable.621087032 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 11548109 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:53:58 PM PST 24 |
| Finished | Jan 21 12:53:59 PM PST 24 |
| Peak memory | 213956 kb |
| Host | smart-03444862-e89f-4159-ba60-26fd4906d88b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621087032 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.621087032 |
| Directory | /workspace/18.edn_disable/latest |
| Test location | /workspace/coverage/default/18.edn_disable_auto_req_mode.3409006378 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 111787138 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 01:13:54 PM PST 24 |
| Finished | Jan 21 01:13:57 PM PST 24 |
| Peak memory | 214080 kb |
| Host | smart-9b7abf95-4727-4bb4-b705-f991d61f3d7d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409006378 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d isable_auto_req_mode.3409006378 |
| Directory | /workspace/18.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/18.edn_err.318264205 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 31510603 ps |
| CPU time | 0.8 seconds |
| Started | Jan 21 12:53:58 PM PST 24 |
| Finished | Jan 21 12:54:00 PM PST 24 |
| Peak memory | 214736 kb |
| Host | smart-bc75227d-c967-4dce-8a3f-b7b6698d0f50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=318264205 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.318264205 |
| Directory | /workspace/18.edn_err/latest |
| Test location | /workspace/coverage/default/18.edn_intr.3319687767 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 36635914 ps |
| CPU time | 0.78 seconds |
| Started | Jan 21 12:53:57 PM PST 24 |
| Finished | Jan 21 12:53:59 PM PST 24 |
| Peak memory | 213908 kb |
| Host | smart-e80755e2-2d08-4845-a700-00478134b8f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3319687767 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3319687767 |
| Directory | /workspace/18.edn_intr/latest |
| Test location | /workspace/coverage/default/18.edn_smoke.2610234345 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 22522972 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 12:53:55 PM PST 24 |
| Finished | Jan 21 12:53:58 PM PST 24 |
| Peak memory | 204424 kb |
| Host | smart-a3a06e07-9ec4-40ba-92f0-5e18bdf65800 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2610234345 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2610234345 |
| Directory | /workspace/18.edn_smoke/latest |
| Test location | /workspace/coverage/default/18.edn_stress_all.1868546461 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 451385673 ps |
| CPU time | 1.63 seconds |
| Started | Jan 21 12:53:49 PM PST 24 |
| Finished | Jan 21 12:53:52 PM PST 24 |
| Peak memory | 205444 kb |
| Host | smart-84b72cae-0829-42b3-85d5-f06bc691da1d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868546461 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.1868546461 |
| Directory | /workspace/18.edn_stress_all/latest |
| Test location | /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2056404987 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 18221704908 ps |
| CPU time | 239.68 seconds |
| Started | Jan 21 12:53:48 PM PST 24 |
| Finished | Jan 21 12:57:49 PM PST 24 |
| Peak memory | 214084 kb |
| Host | smart-d1b5298b-a15b-45c4-8ee6-3cf9ac1f6c6d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056404987 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2056404987 |
| Directory | /workspace/18.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/180.edn_genbits.3897429489 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 15977716 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:59:43 PM PST 24 |
| Finished | Jan 21 12:59:45 PM PST 24 |
| Peak memory | 204484 kb |
| Host | smart-9ae52fa6-3a20-436c-aaa7-238dd3393167 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3897429489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3897429489 |
| Directory | /workspace/180.edn_genbits/latest |
| Test location | /workspace/coverage/default/182.edn_genbits.864916239 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 19738162 ps |
| CPU time | 1.04 seconds |
| Started | Jan 21 12:59:37 PM PST 24 |
| Finished | Jan 21 12:59:40 PM PST 24 |
| Peak memory | 204444 kb |
| Host | smart-94cd6c42-b14e-4569-a583-f73e7c499eb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=864916239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.864916239 |
| Directory | /workspace/182.edn_genbits/latest |
| Test location | /workspace/coverage/default/183.edn_genbits.1776828435 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 39748136 ps |
| CPU time | 1.12 seconds |
| Started | Jan 21 12:59:33 PM PST 24 |
| Finished | Jan 21 12:59:39 PM PST 24 |
| Peak memory | 205280 kb |
| Host | smart-b33090cd-8ad1-4cec-ac6a-c5c1aac5cfcd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1776828435 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1776828435 |
| Directory | /workspace/183.edn_genbits/latest |
| Test location | /workspace/coverage/default/184.edn_genbits.3646795766 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 29665765 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 12:59:37 PM PST 24 |
| Finished | Jan 21 12:59:40 PM PST 24 |
| Peak memory | 204748 kb |
| Host | smart-36eb7131-90ed-41ea-a1e3-af50e7d4bb15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3646795766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3646795766 |
| Directory | /workspace/184.edn_genbits/latest |
| Test location | /workspace/coverage/default/185.edn_genbits.2793135136 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 50658236 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 12:59:37 PM PST 24 |
| Finished | Jan 21 12:59:40 PM PST 24 |
| Peak memory | 204596 kb |
| Host | smart-592681ff-f5b6-4e61-aac6-4e6c9616e139 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2793135136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2793135136 |
| Directory | /workspace/185.edn_genbits/latest |
| Test location | /workspace/coverage/default/186.edn_genbits.619695827 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 96276564 ps |
| CPU time | 1.19 seconds |
| Started | Jan 21 12:59:43 PM PST 24 |
| Finished | Jan 21 12:59:46 PM PST 24 |
| Peak memory | 213672 kb |
| Host | smart-ea009461-4c5f-4cd1-ab98-027cf3f8bd6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=619695827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.619695827 |
| Directory | /workspace/186.edn_genbits/latest |
| Test location | /workspace/coverage/default/187.edn_genbits.2024264170 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 20755360 ps |
| CPU time | 1.05 seconds |
| Started | Jan 21 12:59:43 PM PST 24 |
| Finished | Jan 21 12:59:45 PM PST 24 |
| Peak memory | 205240 kb |
| Host | smart-c0d8e8c9-e052-4d55-a130-bc032ce7ce3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2024264170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.2024264170 |
| Directory | /workspace/187.edn_genbits/latest |
| Test location | /workspace/coverage/default/188.edn_genbits.3548063550 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 31054184 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:59:44 PM PST 24 |
| Finished | Jan 21 12:59:47 PM PST 24 |
| Peak memory | 205108 kb |
| Host | smart-f8f6a671-1485-4854-9193-b3d8805ef3a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3548063550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3548063550 |
| Directory | /workspace/188.edn_genbits/latest |
| Test location | /workspace/coverage/default/189.edn_genbits.3276559739 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 18133987 ps |
| CPU time | 0.94 seconds |
| Started | Jan 21 12:59:43 PM PST 24 |
| Finished | Jan 21 12:59:45 PM PST 24 |
| Peak memory | 204884 kb |
| Host | smart-f6c2fac8-0616-4470-9967-82c0bb53ea13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3276559739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3276559739 |
| Directory | /workspace/189.edn_genbits/latest |
| Test location | /workspace/coverage/default/19.edn_alert.2452301280 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 291365021 ps |
| CPU time | 1.05 seconds |
| Started | Jan 21 01:47:10 PM PST 24 |
| Finished | Jan 21 01:47:14 PM PST 24 |
| Peak memory | 204696 kb |
| Host | smart-ffb45cd4-9216-4367-adbf-43c1f80a47b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2452301280 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2452301280 |
| Directory | /workspace/19.edn_alert/latest |
| Test location | /workspace/coverage/default/19.edn_alert_test.3707526063 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 42817728 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 01:49:41 PM PST 24 |
| Finished | Jan 21 01:49:43 PM PST 24 |
| Peak memory | 204072 kb |
| Host | smart-001a1945-1a3f-4803-9a71-1a10c49b2de1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707526063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3707526063 |
| Directory | /workspace/19.edn_alert_test/latest |
| Test location | /workspace/coverage/default/19.edn_disable.2819677168 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 11893262 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 01:23:48 PM PST 24 |
| Finished | Jan 21 01:23:49 PM PST 24 |
| Peak memory | 214096 kb |
| Host | smart-ca804385-858f-4e36-ada5-6d61dc105d9b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819677168 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2819677168 |
| Directory | /workspace/19.edn_disable/latest |
| Test location | /workspace/coverage/default/19.edn_disable_auto_req_mode.3163244767 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 92854633 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 01:11:50 PM PST 24 |
| Finished | Jan 21 01:11:51 PM PST 24 |
| Peak memory | 214236 kb |
| Host | smart-3dc949d2-18ba-4eef-8c85-65c36d6f6b34 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163244767 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d isable_auto_req_mode.3163244767 |
| Directory | /workspace/19.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/19.edn_err.443906845 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 35005857 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 01:19:59 PM PST 24 |
| Finished | Jan 21 01:20:01 PM PST 24 |
| Peak memory | 215128 kb |
| Host | smart-fba34696-6018-4d51-a1e1-7b7b5386a238 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=443906845 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.443906845 |
| Directory | /workspace/19.edn_err/latest |
| Test location | /workspace/coverage/default/19.edn_genbits.2012701806 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 25490153 ps |
| CPU time | 1.05 seconds |
| Started | Jan 21 01:08:04 PM PST 24 |
| Finished | Jan 21 01:08:06 PM PST 24 |
| Peak memory | 204896 kb |
| Host | smart-fe11d465-8717-4fca-b072-0b9bc5d85c73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2012701806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2012701806 |
| Directory | /workspace/19.edn_genbits/latest |
| Test location | /workspace/coverage/default/19.edn_intr.3194214216 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 29998618 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 01:25:34 PM PST 24 |
| Finished | Jan 21 01:25:36 PM PST 24 |
| Peak memory | 214188 kb |
| Host | smart-d36c5a7a-c109-43a3-b874-bb7d6b55ba41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3194214216 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3194214216 |
| Directory | /workspace/19.edn_intr/latest |
| Test location | /workspace/coverage/default/19.edn_smoke.805367517 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 21170750 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 01:22:20 PM PST 24 |
| Finished | Jan 21 01:22:24 PM PST 24 |
| Peak memory | 204432 kb |
| Host | smart-1033def3-a2c4-4413-9fec-2ec935bb3771 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=805367517 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.805367517 |
| Directory | /workspace/19.edn_smoke/latest |
| Test location | /workspace/coverage/default/19.edn_stress_all.3500822162 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 156778054 ps |
| CPU time | 3.31 seconds |
| Started | Jan 21 12:53:59 PM PST 24 |
| Finished | Jan 21 12:54:04 PM PST 24 |
| Peak memory | 205536 kb |
| Host | smart-3a9e5f81-f9b9-49ba-966b-3fd2110c5931 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500822162 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3500822162 |
| Directory | /workspace/19.edn_stress_all/latest |
| Test location | /workspace/coverage/default/19.edn_stress_all_with_rand_reset.378492345 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 203362045181 ps |
| CPU time | 933.11 seconds |
| Started | Jan 21 02:22:55 PM PST 24 |
| Finished | Jan 21 02:38:29 PM PST 24 |
| Peak memory | 216232 kb |
| Host | smart-8d599ff2-bb66-4602-8b0b-87be54349e1c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378492345 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.378492345 |
| Directory | /workspace/19.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/190.edn_genbits.3010459245 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 107415127 ps |
| CPU time | 2.76 seconds |
| Started | Jan 21 12:59:43 PM PST 24 |
| Finished | Jan 21 12:59:47 PM PST 24 |
| Peak memory | 213740 kb |
| Host | smart-54f42d97-3a73-4a47-ad88-ef1369e5d0fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3010459245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3010459245 |
| Directory | /workspace/190.edn_genbits/latest |
| Test location | /workspace/coverage/default/191.edn_genbits.2543330809 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 45647492 ps |
| CPU time | 1.36 seconds |
| Started | Jan 21 12:59:41 PM PST 24 |
| Finished | Jan 21 12:59:45 PM PST 24 |
| Peak memory | 205300 kb |
| Host | smart-f64b541c-4586-4c36-9064-47cc66affcd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2543330809 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2543330809 |
| Directory | /workspace/191.edn_genbits/latest |
| Test location | /workspace/coverage/default/193.edn_genbits.1582176549 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 122319650 ps |
| CPU time | 2.04 seconds |
| Started | Jan 21 12:59:53 PM PST 24 |
| Finished | Jan 21 12:59:56 PM PST 24 |
| Peak memory | 213748 kb |
| Host | smart-f01ca4c2-c262-4730-8b07-eaa6a660f0a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1582176549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1582176549 |
| Directory | /workspace/193.edn_genbits/latest |
| Test location | /workspace/coverage/default/194.edn_genbits.3944546272 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 116047170 ps |
| CPU time | 2.14 seconds |
| Started | Jan 21 12:59:53 PM PST 24 |
| Finished | Jan 21 12:59:56 PM PST 24 |
| Peak memory | 213752 kb |
| Host | smart-47fd1464-045c-4167-aabb-88cbc48add4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3944546272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3944546272 |
| Directory | /workspace/194.edn_genbits/latest |
| Test location | /workspace/coverage/default/195.edn_genbits.1606685140 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 52655450 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:59:56 PM PST 24 |
| Finished | Jan 21 12:59:58 PM PST 24 |
| Peak memory | 204736 kb |
| Host | smart-80e559e5-7421-413e-9280-71c41e80a6d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1606685140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1606685140 |
| Directory | /workspace/195.edn_genbits/latest |
| Test location | /workspace/coverage/default/197.edn_genbits.1845389205 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 171062028 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 12:59:56 PM PST 24 |
| Finished | Jan 21 12:59:58 PM PST 24 |
| Peak memory | 204904 kb |
| Host | smart-9347af4d-3daf-4242-9367-9d5bf0449d82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1845389205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1845389205 |
| Directory | /workspace/197.edn_genbits/latest |
| Test location | /workspace/coverage/default/2.edn_alert.4145852488 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 18299503 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 01:09:04 PM PST 24 |
| Finished | Jan 21 01:09:06 PM PST 24 |
| Peak memory | 205564 kb |
| Host | smart-5da9e612-6568-41a6-8e83-97f1c6974539 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4145852488 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.4145852488 |
| Directory | /workspace/2.edn_alert/latest |
| Test location | /workspace/coverage/default/2.edn_alert_test.3587927894 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 12979449 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 12:51:29 PM PST 24 |
| Finished | Jan 21 12:51:32 PM PST 24 |
| Peak memory | 203792 kb |
| Host | smart-9cbaafdd-5be9-4321-898d-377f20b18df8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587927894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3587927894 |
| Directory | /workspace/2.edn_alert_test/latest |
| Test location | /workspace/coverage/default/2.edn_disable.3864777080 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 14310110 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 12:51:28 PM PST 24 |
| Finished | Jan 21 12:51:32 PM PST 24 |
| Peak memory | 213924 kb |
| Host | smart-6b95d2ba-323c-4727-9a7f-4bb37010136f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864777080 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3864777080 |
| Directory | /workspace/2.edn_disable/latest |
| Test location | /workspace/coverage/default/2.edn_disable_auto_req_mode.2740669829 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 187483577 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 12:51:25 PM PST 24 |
| Finished | Jan 21 12:51:28 PM PST 24 |
| Peak memory | 214084 kb |
| Host | smart-a023bc01-26f5-4270-89e9-3bd9ff7d81db |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740669829 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di sable_auto_req_mode.2740669829 |
| Directory | /workspace/2.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/2.edn_err.4113641029 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 34938229 ps |
| CPU time | 1.46 seconds |
| Started | Jan 21 12:51:25 PM PST 24 |
| Finished | Jan 21 12:51:29 PM PST 24 |
| Peak memory | 221704 kb |
| Host | smart-a9e12a5c-b3b6-4c2b-a6ee-3888ecd54584 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4113641029 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.4113641029 |
| Directory | /workspace/2.edn_err/latest |
| Test location | /workspace/coverage/default/2.edn_genbits.1401057995 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 23797710 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:51:19 PM PST 24 |
| Finished | Jan 21 12:51:22 PM PST 24 |
| Peak memory | 204668 kb |
| Host | smart-f4b663de-6fd0-4060-a4d2-75d8afe15d46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1401057995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1401057995 |
| Directory | /workspace/2.edn_genbits/latest |
| Test location | /workspace/coverage/default/2.edn_intr.1639925096 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 28872742 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 01:53:51 PM PST 24 |
| Finished | Jan 21 01:53:53 PM PST 24 |
| Peak memory | 221212 kb |
| Host | smart-41042852-1a52-4e0e-ae19-34727c5ef9a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1639925096 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.1639925096 |
| Directory | /workspace/2.edn_intr/latest |
| Test location | /workspace/coverage/default/2.edn_regwen.2028239986 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 46842924 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:51:21 PM PST 24 |
| Finished | Jan 21 12:51:27 PM PST 24 |
| Peak memory | 204512 kb |
| Host | smart-3f62ab0c-5af4-4b3d-bebd-a2650abcc4fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2028239986 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.2028239986 |
| Directory | /workspace/2.edn_regwen/latest |
| Test location | /workspace/coverage/default/2.edn_smoke.564060356 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 50408279 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:51:17 PM PST 24 |
| Finished | Jan 21 12:51:20 PM PST 24 |
| Peak memory | 204392 kb |
| Host | smart-399bdf06-03b2-46fc-afea-3adb237982f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=564060356 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.564060356 |
| Directory | /workspace/2.edn_smoke/latest |
| Test location | /workspace/coverage/default/2.edn_stress_all.303971811 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 93292913 ps |
| CPU time | 2.64 seconds |
| Started | Jan 21 12:51:18 PM PST 24 |
| Finished | Jan 21 12:51:23 PM PST 24 |
| Peak memory | 205556 kb |
| Host | smart-13441ed3-2cd4-491a-ba6e-5d8ab2b1fd74 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303971811 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.303971811 |
| Directory | /workspace/2.edn_stress_all/latest |
| Test location | /workspace/coverage/default/2.edn_stress_all_with_rand_reset.4165662999 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 40628242906 ps |
| CPU time | 527.19 seconds |
| Started | Jan 21 12:51:20 PM PST 24 |
| Finished | Jan 21 01:00:12 PM PST 24 |
| Peak memory | 215484 kb |
| Host | smart-2f870d9f-afc6-46d1-b664-66579f79400a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165662999 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.4165662999 |
| Directory | /workspace/2.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.edn_alert.1420980195 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 16382521 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 12:54:15 PM PST 24 |
| Finished | Jan 21 12:54:16 PM PST 24 |
| Peak memory | 205468 kb |
| Host | smart-a6dc1469-1e93-4ec1-bdcd-59bce9e04fc7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1420980195 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1420980195 |
| Directory | /workspace/20.edn_alert/latest |
| Test location | /workspace/coverage/default/20.edn_alert_test.586093595 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 32278313 ps |
| CPU time | 0.75 seconds |
| Started | Jan 21 12:54:17 PM PST 24 |
| Finished | Jan 21 12:54:19 PM PST 24 |
| Peak memory | 203788 kb |
| Host | smart-78d86130-e3cf-4b87-b635-f176b1440ee3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586093595 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.586093595 |
| Directory | /workspace/20.edn_alert_test/latest |
| Test location | /workspace/coverage/default/20.edn_disable.3346177325 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 18282234 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 12:54:16 PM PST 24 |
| Finished | Jan 21 12:54:17 PM PST 24 |
| Peak memory | 213976 kb |
| Host | smart-f6cdfbc5-206f-4a85-999a-0f20e6301a82 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346177325 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3346177325 |
| Directory | /workspace/20.edn_disable/latest |
| Test location | /workspace/coverage/default/20.edn_err.2519493618 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 18407749 ps |
| CPU time | 1 seconds |
| Started | Jan 21 12:54:14 PM PST 24 |
| Finished | Jan 21 12:54:16 PM PST 24 |
| Peak memory | 215088 kb |
| Host | smart-b463afaf-584d-4f06-955e-b09f94d1eb1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2519493618 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2519493618 |
| Directory | /workspace/20.edn_err/latest |
| Test location | /workspace/coverage/default/20.edn_genbits.3994897928 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 189629435 ps |
| CPU time | 1.15 seconds |
| Started | Jan 21 12:54:07 PM PST 24 |
| Finished | Jan 21 12:54:10 PM PST 24 |
| Peak memory | 213780 kb |
| Host | smart-d4cb0495-9dac-46aa-87c2-32723f366e70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3994897928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3994897928 |
| Directory | /workspace/20.edn_genbits/latest |
| Test location | /workspace/coverage/default/20.edn_intr.2306154059 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 25231711 ps |
| CPU time | 0.94 seconds |
| Started | Jan 21 12:54:09 PM PST 24 |
| Finished | Jan 21 12:54:13 PM PST 24 |
| Peak memory | 213808 kb |
| Host | smart-ec5e9b64-4ff2-402a-8b29-991b6ff7ff51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2306154059 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2306154059 |
| Directory | /workspace/20.edn_intr/latest |
| Test location | /workspace/coverage/default/20.edn_smoke.60614481 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 23896531 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 01:22:29 PM PST 24 |
| Finished | Jan 21 01:22:33 PM PST 24 |
| Peak memory | 204632 kb |
| Host | smart-b767f2ff-02a6-4079-b457-02e1f25f48cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=60614481 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.60614481 |
| Directory | /workspace/20.edn_smoke/latest |
| Test location | /workspace/coverage/default/20.edn_stress_all.4243510694 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 61505199 ps |
| CPU time | 1.23 seconds |
| Started | Jan 21 12:54:09 PM PST 24 |
| Finished | Jan 21 12:54:13 PM PST 24 |
| Peak memory | 205052 kb |
| Host | smart-92a57983-68fb-47d5-aa06-b466033fdddb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243510694 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.4243510694 |
| Directory | /workspace/20.edn_stress_all/latest |
| Test location | /workspace/coverage/default/200.edn_genbits.4068128960 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 63533120 ps |
| CPU time | 1 seconds |
| Started | Jan 21 12:59:55 PM PST 24 |
| Finished | Jan 21 12:59:57 PM PST 24 |
| Peak memory | 205148 kb |
| Host | smart-e0db9272-290b-43d3-a17e-0cc0e1f18b83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4068128960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.4068128960 |
| Directory | /workspace/200.edn_genbits/latest |
| Test location | /workspace/coverage/default/201.edn_genbits.721302454 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 15458730 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 12:59:57 PM PST 24 |
| Finished | Jan 21 12:59:59 PM PST 24 |
| Peak memory | 205040 kb |
| Host | smart-83574fba-259c-49aa-b381-eaf88482df28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=721302454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.721302454 |
| Directory | /workspace/201.edn_genbits/latest |
| Test location | /workspace/coverage/default/202.edn_genbits.2168100940 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 36804128 ps |
| CPU time | 1.03 seconds |
| Started | Jan 21 12:59:57 PM PST 24 |
| Finished | Jan 21 12:59:59 PM PST 24 |
| Peak memory | 204520 kb |
| Host | smart-211f11ad-23f3-4bd0-81a1-c292a8358c37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2168100940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2168100940 |
| Directory | /workspace/202.edn_genbits/latest |
| Test location | /workspace/coverage/default/203.edn_genbits.863861934 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 87418895 ps |
| CPU time | 1.21 seconds |
| Started | Jan 21 01:00:01 PM PST 24 |
| Finished | Jan 21 01:00:05 PM PST 24 |
| Peak memory | 213740 kb |
| Host | smart-a1c3fd9e-f854-45d4-b2e3-47748e60e05f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=863861934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.863861934 |
| Directory | /workspace/203.edn_genbits/latest |
| Test location | /workspace/coverage/default/204.edn_genbits.1517144426 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 56487643 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 01:00:02 PM PST 24 |
| Finished | Jan 21 01:00:06 PM PST 24 |
| Peak memory | 213732 kb |
| Host | smart-e2789cc4-47e0-4f8b-999e-5667aa62c639 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1517144426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1517144426 |
| Directory | /workspace/204.edn_genbits/latest |
| Test location | /workspace/coverage/default/205.edn_genbits.1933241003 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 84331339 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 01:00:01 PM PST 24 |
| Finished | Jan 21 01:00:05 PM PST 24 |
| Peak memory | 204812 kb |
| Host | smart-66585acc-de1e-4fcb-a57a-e462bc7407a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1933241003 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1933241003 |
| Directory | /workspace/205.edn_genbits/latest |
| Test location | /workspace/coverage/default/206.edn_genbits.496493850 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 74619176 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 01:00:03 PM PST 24 |
| Finished | Jan 21 01:00:07 PM PST 24 |
| Peak memory | 204500 kb |
| Host | smart-cf7edc8c-d0b3-4082-8eac-d145932520b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=496493850 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.496493850 |
| Directory | /workspace/206.edn_genbits/latest |
| Test location | /workspace/coverage/default/207.edn_genbits.4226563385 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 52898268 ps |
| CPU time | 1.01 seconds |
| Started | Jan 21 01:00:02 PM PST 24 |
| Finished | Jan 21 01:00:05 PM PST 24 |
| Peak memory | 205196 kb |
| Host | smart-924c9114-95ea-4629-8c56-43971b6fd70b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4226563385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.4226563385 |
| Directory | /workspace/207.edn_genbits/latest |
| Test location | /workspace/coverage/default/208.edn_genbits.3803797695 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 240346930 ps |
| CPU time | 1.14 seconds |
| Started | Jan 21 01:00:03 PM PST 24 |
| Finished | Jan 21 01:00:08 PM PST 24 |
| Peak memory | 205104 kb |
| Host | smart-439ed339-4c02-4558-958a-3e5d3f2addb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3803797695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3803797695 |
| Directory | /workspace/208.edn_genbits/latest |
| Test location | /workspace/coverage/default/209.edn_genbits.3891890647 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 28299605 ps |
| CPU time | 1.28 seconds |
| Started | Jan 21 01:00:01 PM PST 24 |
| Finished | Jan 21 01:00:05 PM PST 24 |
| Peak memory | 205360 kb |
| Host | smart-cbf3c0b2-5445-42f7-86f3-53675e5a9bb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3891890647 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3891890647 |
| Directory | /workspace/209.edn_genbits/latest |
| Test location | /workspace/coverage/default/21.edn_alert.3584258222 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 56354539 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 01:18:34 PM PST 24 |
| Finished | Jan 21 01:18:35 PM PST 24 |
| Peak memory | 205584 kb |
| Host | smart-50b8d267-6249-4826-9b38-97c92bacb51a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584258222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3584258222 |
| Directory | /workspace/21.edn_alert/latest |
| Test location | /workspace/coverage/default/21.edn_alert_test.2329802499 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 24219308 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:54:30 PM PST 24 |
| Finished | Jan 21 12:54:32 PM PST 24 |
| Peak memory | 204652 kb |
| Host | smart-3a84b018-86c9-46be-af0a-17f1bc816990 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329802499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2329802499 |
| Directory | /workspace/21.edn_alert_test/latest |
| Test location | /workspace/coverage/default/21.edn_disable.4079475547 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 41219727 ps |
| CPU time | 0.81 seconds |
| Started | Jan 21 12:54:25 PM PST 24 |
| Finished | Jan 21 12:54:27 PM PST 24 |
| Peak memory | 213980 kb |
| Host | smart-4768dfaa-290b-4631-b21c-9e17bdfc75bf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079475547 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.4079475547 |
| Directory | /workspace/21.edn_disable/latest |
| Test location | /workspace/coverage/default/21.edn_disable_auto_req_mode.3462836820 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 20955989 ps |
| CPU time | 1 seconds |
| Started | Jan 21 12:54:27 PM PST 24 |
| Finished | Jan 21 12:54:29 PM PST 24 |
| Peak memory | 214112 kb |
| Host | smart-1c9b9fc3-8b4c-4eb1-a02c-12dd67c7f129 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462836820 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d isable_auto_req_mode.3462836820 |
| Directory | /workspace/21.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/21.edn_err.2042794125 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 34805085 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:54:27 PM PST 24 |
| Finished | Jan 21 12:54:29 PM PST 24 |
| Peak memory | 215408 kb |
| Host | smart-4487bda5-39fa-49ad-b170-ede32f40aad4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2042794125 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.2042794125 |
| Directory | /workspace/21.edn_err/latest |
| Test location | /workspace/coverage/default/21.edn_genbits.3026112063 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 186846038 ps |
| CPU time | 1.05 seconds |
| Started | Jan 21 12:54:24 PM PST 24 |
| Finished | Jan 21 12:54:26 PM PST 24 |
| Peak memory | 205288 kb |
| Host | smart-8b699ed2-d87d-44fc-be4a-ac38008a1689 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3026112063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3026112063 |
| Directory | /workspace/21.edn_genbits/latest |
| Test location | /workspace/coverage/default/21.edn_intr.171394392 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 17997398 ps |
| CPU time | 1.01 seconds |
| Started | Jan 21 12:54:25 PM PST 24 |
| Finished | Jan 21 12:54:27 PM PST 24 |
| Peak memory | 213952 kb |
| Host | smart-6573a977-ddd4-43b6-b4de-796584ef3ad3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=171394392 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.171394392 |
| Directory | /workspace/21.edn_intr/latest |
| Test location | /workspace/coverage/default/21.edn_smoke.1657560188 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 30721595 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 12:54:16 PM PST 24 |
| Finished | Jan 21 12:54:18 PM PST 24 |
| Peak memory | 204176 kb |
| Host | smart-311f8206-7182-4f15-abe3-1b24122e17f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657560188 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1657560188 |
| Directory | /workspace/21.edn_smoke/latest |
| Test location | /workspace/coverage/default/21.edn_stress_all.2784571190 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 41241067 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 01:13:32 PM PST 24 |
| Finished | Jan 21 01:13:34 PM PST 24 |
| Peak memory | 204272 kb |
| Host | smart-319b5d01-e153-4273-b6da-b1fd6b3e91fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784571190 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2784571190 |
| Directory | /workspace/21.edn_stress_all/latest |
| Test location | /workspace/coverage/default/21.edn_stress_all_with_rand_reset.258724670 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 96041777780 ps |
| CPU time | 1118.91 seconds |
| Started | Jan 21 12:54:24 PM PST 24 |
| Finished | Jan 21 01:13:04 PM PST 24 |
| Peak memory | 216276 kb |
| Host | smart-19837084-90b9-4814-b1dc-675f77fdc58d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258724670 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.258724670 |
| Directory | /workspace/21.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/211.edn_genbits.1353870464 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 26659002 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 01:00:03 PM PST 24 |
| Finished | Jan 21 01:00:08 PM PST 24 |
| Peak memory | 204644 kb |
| Host | smart-172104d3-4340-4c96-aee0-7c551cffa951 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1353870464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.1353870464 |
| Directory | /workspace/211.edn_genbits/latest |
| Test location | /workspace/coverage/default/212.edn_genbits.1072401726 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 44018495 ps |
| CPU time | 1.36 seconds |
| Started | Jan 21 01:00:04 PM PST 24 |
| Finished | Jan 21 01:00:09 PM PST 24 |
| Peak memory | 213772 kb |
| Host | smart-5903fe3e-ab09-43bd-b966-8cd0e62426c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1072401726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.1072401726 |
| Directory | /workspace/212.edn_genbits/latest |
| Test location | /workspace/coverage/default/213.edn_genbits.1479500361 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 20818400 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 01:00:02 PM PST 24 |
| Finished | Jan 21 01:00:05 PM PST 24 |
| Peak memory | 204708 kb |
| Host | smart-1fdd152a-0d30-4b9c-84c5-3a61f74a987b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1479500361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1479500361 |
| Directory | /workspace/213.edn_genbits/latest |
| Test location | /workspace/coverage/default/214.edn_genbits.2417042165 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 32563350 ps |
| CPU time | 1.05 seconds |
| Started | Jan 21 01:00:00 PM PST 24 |
| Finished | Jan 21 01:00:05 PM PST 24 |
| Peak memory | 213764 kb |
| Host | smart-e90dea99-4f5d-4fa5-bac4-fe1a33acad2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2417042165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2417042165 |
| Directory | /workspace/214.edn_genbits/latest |
| Test location | /workspace/coverage/default/215.edn_genbits.402044763 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 32097864 ps |
| CPU time | 1.18 seconds |
| Started | Jan 21 01:00:02 PM PST 24 |
| Finished | Jan 21 01:00:05 PM PST 24 |
| Peak memory | 213792 kb |
| Host | smart-c78453a3-30e0-42b8-8137-6c5ce5c9668c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=402044763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.402044763 |
| Directory | /workspace/215.edn_genbits/latest |
| Test location | /workspace/coverage/default/216.edn_genbits.1598728498 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 748234527 ps |
| CPU time | 5.75 seconds |
| Started | Jan 21 01:00:03 PM PST 24 |
| Finished | Jan 21 01:00:13 PM PST 24 |
| Peak memory | 213692 kb |
| Host | smart-804619ea-6995-42c0-8757-5244c3762cde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598728498 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1598728498 |
| Directory | /workspace/216.edn_genbits/latest |
| Test location | /workspace/coverage/default/217.edn_genbits.876547841 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 32191041 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 01:00:01 PM PST 24 |
| Finished | Jan 21 01:00:05 PM PST 24 |
| Peak memory | 204804 kb |
| Host | smart-5bb60edf-c9cd-4293-b8a6-ebdf044409ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=876547841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.876547841 |
| Directory | /workspace/217.edn_genbits/latest |
| Test location | /workspace/coverage/default/218.edn_genbits.1089084858 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 14608017 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 03:04:11 PM PST 24 |
| Finished | Jan 21 03:04:13 PM PST 24 |
| Peak memory | 205124 kb |
| Host | smart-1cec511d-4f6a-4ec8-9aaf-cd314b721635 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1089084858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1089084858 |
| Directory | /workspace/218.edn_genbits/latest |
| Test location | /workspace/coverage/default/22.edn_alert.133432603 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 28632967 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:54:27 PM PST 24 |
| Finished | Jan 21 12:54:28 PM PST 24 |
| Peak memory | 205516 kb |
| Host | smart-8052411c-6d6d-4b03-b33b-65f4f4b9ed9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=133432603 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.133432603 |
| Directory | /workspace/22.edn_alert/latest |
| Test location | /workspace/coverage/default/22.edn_alert_test.3160859043 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 76574626 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 12:54:36 PM PST 24 |
| Finished | Jan 21 12:54:38 PM PST 24 |
| Peak memory | 204984 kb |
| Host | smart-da09ddeb-8915-4aad-98c6-8db25a5777b7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160859043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3160859043 |
| Directory | /workspace/22.edn_alert_test/latest |
| Test location | /workspace/coverage/default/22.edn_disable.304984922 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 28852881 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:54:30 PM PST 24 |
| Finished | Jan 21 12:54:32 PM PST 24 |
| Peak memory | 213956 kb |
| Host | smart-9f5f307a-b3ab-48d3-aa94-53582e5ed624 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304984922 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.304984922 |
| Directory | /workspace/22.edn_disable/latest |
| Test location | /workspace/coverage/default/22.edn_disable_auto_req_mode.1756707816 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 81764323 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 12:54:32 PM PST 24 |
| Finished | Jan 21 12:54:34 PM PST 24 |
| Peak memory | 214244 kb |
| Host | smart-3d25c449-87dd-4928-b9af-05ed22cc4ec7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756707816 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d isable_auto_req_mode.1756707816 |
| Directory | /workspace/22.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/22.edn_err.68057111 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 189919453 ps |
| CPU time | 1.07 seconds |
| Started | Jan 21 12:54:25 PM PST 24 |
| Finished | Jan 21 12:54:27 PM PST 24 |
| Peak memory | 221292 kb |
| Host | smart-284466bd-ed63-4eed-bcaa-d5ddc1a38b71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=68057111 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.68057111 |
| Directory | /workspace/22.edn_err/latest |
| Test location | /workspace/coverage/default/22.edn_genbits.4275182417 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 74561356 ps |
| CPU time | 2.73 seconds |
| Started | Jan 21 12:54:22 PM PST 24 |
| Finished | Jan 21 12:54:26 PM PST 24 |
| Peak memory | 213704 kb |
| Host | smart-06d1403c-8d47-4e35-bd89-607c6329349e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4275182417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.4275182417 |
| Directory | /workspace/22.edn_genbits/latest |
| Test location | /workspace/coverage/default/22.edn_smoke.2057570993 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 71631888 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:54:27 PM PST 24 |
| Finished | Jan 21 12:54:29 PM PST 24 |
| Peak memory | 204408 kb |
| Host | smart-2923266d-1160-412c-9a0b-50a03116e2a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2057570993 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2057570993 |
| Directory | /workspace/22.edn_smoke/latest |
| Test location | /workspace/coverage/default/22.edn_stress_all.3647868837 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1493671044 ps |
| CPU time | 3.08 seconds |
| Started | Jan 21 12:54:23 PM PST 24 |
| Finished | Jan 21 12:54:27 PM PST 24 |
| Peak memory | 205260 kb |
| Host | smart-fd987d33-5569-461c-a640-af5580c896d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647868837 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3647868837 |
| Directory | /workspace/22.edn_stress_all/latest |
| Test location | /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1246998961 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 85072748987 ps |
| CPU time | 454.54 seconds |
| Started | Jan 21 12:54:24 PM PST 24 |
| Finished | Jan 21 01:02:00 PM PST 24 |
| Peak memory | 214040 kb |
| Host | smart-79e6d0fb-1f1f-44c2-a9c3-757d18a84306 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246998961 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1246998961 |
| Directory | /workspace/22.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/221.edn_genbits.3965671897 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 98162908 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 01:00:10 PM PST 24 |
| Finished | Jan 21 01:00:12 PM PST 24 |
| Peak memory | 204644 kb |
| Host | smart-fad43076-a5b5-4e75-9fac-50bbad20bc6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3965671897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3965671897 |
| Directory | /workspace/221.edn_genbits/latest |
| Test location | /workspace/coverage/default/223.edn_genbits.3330098032 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 23275415 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 01:00:15 PM PST 24 |
| Finished | Jan 21 01:00:17 PM PST 24 |
| Peak memory | 205060 kb |
| Host | smart-1a2ee8cf-ce06-4148-8f58-dcfeadb00877 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3330098032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3330098032 |
| Directory | /workspace/223.edn_genbits/latest |
| Test location | /workspace/coverage/default/224.edn_genbits.2007544392 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 16372503 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 01:00:12 PM PST 24 |
| Finished | Jan 21 01:00:15 PM PST 24 |
| Peak memory | 213692 kb |
| Host | smart-81c16091-853a-49b6-b92c-e2263c5c4958 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2007544392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2007544392 |
| Directory | /workspace/224.edn_genbits/latest |
| Test location | /workspace/coverage/default/225.edn_genbits.2872367079 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 338842932 ps |
| CPU time | 4.51 seconds |
| Started | Jan 21 01:00:11 PM PST 24 |
| Finished | Jan 21 01:00:18 PM PST 24 |
| Peak memory | 213772 kb |
| Host | smart-6ffab7fb-fbbc-4baf-8856-25e797583f2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2872367079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2872367079 |
| Directory | /workspace/225.edn_genbits/latest |
| Test location | /workspace/coverage/default/226.edn_genbits.519699061 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 276927293 ps |
| CPU time | 3.78 seconds |
| Started | Jan 21 01:00:13 PM PST 24 |
| Finished | Jan 21 01:00:18 PM PST 24 |
| Peak memory | 213680 kb |
| Host | smart-0acb96a8-0796-432b-9c9c-22da432219fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=519699061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.519699061 |
| Directory | /workspace/226.edn_genbits/latest |
| Test location | /workspace/coverage/default/227.edn_genbits.3768200703 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 19918937 ps |
| CPU time | 1.11 seconds |
| Started | Jan 21 01:00:11 PM PST 24 |
| Finished | Jan 21 01:00:14 PM PST 24 |
| Peak memory | 205400 kb |
| Host | smart-29c5ccc4-2cc6-463c-9e8d-6f982a103422 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3768200703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3768200703 |
| Directory | /workspace/227.edn_genbits/latest |
| Test location | /workspace/coverage/default/228.edn_genbits.2599710474 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 85352117 ps |
| CPU time | 1.1 seconds |
| Started | Jan 21 01:00:15 PM PST 24 |
| Finished | Jan 21 01:00:18 PM PST 24 |
| Peak memory | 205068 kb |
| Host | smart-75a1749d-2a8e-44fd-ae89-7356cfa99a17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2599710474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2599710474 |
| Directory | /workspace/228.edn_genbits/latest |
| Test location | /workspace/coverage/default/229.edn_genbits.2785955507 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 26092728 ps |
| CPU time | 0.87 seconds |
| Started | Jan 21 01:00:14 PM PST 24 |
| Finished | Jan 21 01:00:16 PM PST 24 |
| Peak memory | 204588 kb |
| Host | smart-d9cf76f1-297f-4ce0-9853-16f8a4d0b032 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2785955507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2785955507 |
| Directory | /workspace/229.edn_genbits/latest |
| Test location | /workspace/coverage/default/23.edn_alert.3431600005 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 62086671 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 01:28:53 PM PST 24 |
| Finished | Jan 21 01:28:55 PM PST 24 |
| Peak memory | 204688 kb |
| Host | smart-2175713b-d0be-4cc0-b561-24dc4eeff498 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3431600005 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3431600005 |
| Directory | /workspace/23.edn_alert/latest |
| Test location | /workspace/coverage/default/23.edn_alert_test.3075066268 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 65430619 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:54:33 PM PST 24 |
| Finished | Jan 21 12:54:35 PM PST 24 |
| Peak memory | 204644 kb |
| Host | smart-bf1fbe31-195d-4078-88e0-789149349b18 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075066268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.3075066268 |
| Directory | /workspace/23.edn_alert_test/latest |
| Test location | /workspace/coverage/default/23.edn_disable_auto_req_mode.1420964478 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 19494729 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 12:54:33 PM PST 24 |
| Finished | Jan 21 12:54:36 PM PST 24 |
| Peak memory | 214072 kb |
| Host | smart-d5841dc1-765d-4a55-b5fc-47a09f8ddf40 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420964478 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d isable_auto_req_mode.1420964478 |
| Directory | /workspace/23.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/23.edn_err.587217587 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 20094833 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:54:34 PM PST 24 |
| Finished | Jan 21 12:54:36 PM PST 24 |
| Peak memory | 215816 kb |
| Host | smart-d9571e14-b419-4e63-b389-3eab90466f15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=587217587 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.587217587 |
| Directory | /workspace/23.edn_err/latest |
| Test location | /workspace/coverage/default/23.edn_genbits.4142938892 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 19032472 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:54:31 PM PST 24 |
| Finished | Jan 21 12:54:33 PM PST 24 |
| Peak memory | 204752 kb |
| Host | smart-1726b15f-ae07-45f4-9b7b-afeb9d4c5e0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4142938892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.4142938892 |
| Directory | /workspace/23.edn_genbits/latest |
| Test location | /workspace/coverage/default/23.edn_intr.2908644180 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 23598610 ps |
| CPU time | 1.03 seconds |
| Started | Jan 21 12:54:31 PM PST 24 |
| Finished | Jan 21 12:54:33 PM PST 24 |
| Peak memory | 220948 kb |
| Host | smart-48d5c2e8-07bc-4d68-ba0f-d355880e5f46 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2908644180 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2908644180 |
| Directory | /workspace/23.edn_intr/latest |
| Test location | /workspace/coverage/default/23.edn_smoke.75383927 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 26509730 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 12:54:33 PM PST 24 |
| Finished | Jan 21 12:54:35 PM PST 24 |
| Peak memory | 204464 kb |
| Host | smart-749e2d74-20b1-4cbe-802c-7e6c6087dbdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75383927 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.75383927 |
| Directory | /workspace/23.edn_smoke/latest |
| Test location | /workspace/coverage/default/23.edn_stress_all.4136264385 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 91977584 ps |
| CPU time | 2.43 seconds |
| Started | Jan 21 01:13:04 PM PST 24 |
| Finished | Jan 21 01:13:07 PM PST 24 |
| Peak memory | 205680 kb |
| Host | smart-e3cbd064-4ca1-43be-9ff7-f7b851a2d493 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136264385 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.4136264385 |
| Directory | /workspace/23.edn_stress_all/latest |
| Test location | /workspace/coverage/default/23.edn_stress_all_with_rand_reset.3209334467 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 86519346672 ps |
| CPU time | 1132.76 seconds |
| Started | Jan 21 12:54:31 PM PST 24 |
| Finished | Jan 21 01:13:25 PM PST 24 |
| Peak memory | 215412 kb |
| Host | smart-78e6b9ff-7a96-480b-9256-916e814daf19 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209334467 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.3209334467 |
| Directory | /workspace/23.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/230.edn_genbits.517779399 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 58132710 ps |
| CPU time | 1 seconds |
| Started | Jan 21 01:00:11 PM PST 24 |
| Finished | Jan 21 01:00:14 PM PST 24 |
| Peak memory | 204780 kb |
| Host | smart-9483a27f-66f3-4e3e-a474-4e06c9ed2c70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=517779399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.517779399 |
| Directory | /workspace/230.edn_genbits/latest |
| Test location | /workspace/coverage/default/231.edn_genbits.825638774 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 105157609 ps |
| CPU time | 1.09 seconds |
| Started | Jan 21 01:00:10 PM PST 24 |
| Finished | Jan 21 01:00:13 PM PST 24 |
| Peak memory | 204984 kb |
| Host | smart-f8a5a728-ec42-416c-896a-5b4f17561329 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=825638774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.825638774 |
| Directory | /workspace/231.edn_genbits/latest |
| Test location | /workspace/coverage/default/232.edn_genbits.2461515706 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 18859035 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 01:00:12 PM PST 24 |
| Finished | Jan 21 01:00:15 PM PST 24 |
| Peak memory | 204588 kb |
| Host | smart-6c0b7c39-9c0d-4f53-b478-9ddac642e91f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2461515706 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2461515706 |
| Directory | /workspace/232.edn_genbits/latest |
| Test location | /workspace/coverage/default/233.edn_genbits.3641954312 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 69614898 ps |
| CPU time | 1.09 seconds |
| Started | Jan 21 01:00:14 PM PST 24 |
| Finished | Jan 21 01:00:17 PM PST 24 |
| Peak memory | 205024 kb |
| Host | smart-9ac7b6eb-21cd-4cf0-a79c-1827d7334f5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3641954312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3641954312 |
| Directory | /workspace/233.edn_genbits/latest |
| Test location | /workspace/coverage/default/234.edn_genbits.3885718293 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 89164980 ps |
| CPU time | 1.9 seconds |
| Started | Jan 21 01:00:08 PM PST 24 |
| Finished | Jan 21 01:00:12 PM PST 24 |
| Peak memory | 213768 kb |
| Host | smart-5e6b4474-12e8-4c9a-824d-020d23e82d6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3885718293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.3885718293 |
| Directory | /workspace/234.edn_genbits/latest |
| Test location | /workspace/coverage/default/235.edn_genbits.2824152627 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 72431013 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 01:00:18 PM PST 24 |
| Finished | Jan 21 01:00:21 PM PST 24 |
| Peak memory | 204928 kb |
| Host | smart-1de34f19-8cb1-44d5-8ac1-991a56807b59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2824152627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2824152627 |
| Directory | /workspace/235.edn_genbits/latest |
| Test location | /workspace/coverage/default/236.edn_genbits.2520233653 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 28959184 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 01:00:18 PM PST 24 |
| Finished | Jan 21 01:00:20 PM PST 24 |
| Peak memory | 205128 kb |
| Host | smart-f1347feb-f2d6-4799-a999-ee5de0393ef2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2520233653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2520233653 |
| Directory | /workspace/236.edn_genbits/latest |
| Test location | /workspace/coverage/default/237.edn_genbits.3089084609 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 46579577 ps |
| CPU time | 0.94 seconds |
| Started | Jan 21 01:00:20 PM PST 24 |
| Finished | Jan 21 01:00:24 PM PST 24 |
| Peak memory | 205116 kb |
| Host | smart-f12b8c1c-7f21-4a4e-973a-92474ed6d028 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3089084609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3089084609 |
| Directory | /workspace/237.edn_genbits/latest |
| Test location | /workspace/coverage/default/238.edn_genbits.3045869700 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 15038769 ps |
| CPU time | 1.01 seconds |
| Started | Jan 21 01:00:20 PM PST 24 |
| Finished | Jan 21 01:00:24 PM PST 24 |
| Peak memory | 205128 kb |
| Host | smart-ae58fa8d-8456-4e78-bf6b-9c06be5bc9d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3045869700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3045869700 |
| Directory | /workspace/238.edn_genbits/latest |
| Test location | /workspace/coverage/default/239.edn_genbits.3935851966 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 53848596 ps |
| CPU time | 1.26 seconds |
| Started | Jan 21 01:00:20 PM PST 24 |
| Finished | Jan 21 01:00:24 PM PST 24 |
| Peak memory | 205244 kb |
| Host | smart-5143a3c7-cf43-438c-a0e3-cc354259f501 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3935851966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3935851966 |
| Directory | /workspace/239.edn_genbits/latest |
| Test location | /workspace/coverage/default/24.edn_alert_test.3845623370 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 41353625 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:54:43 PM PST 24 |
| Finished | Jan 21 12:54:44 PM PST 24 |
| Peak memory | 204496 kb |
| Host | smart-53941810-a524-4860-ac9d-42ecdacec638 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845623370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.3845623370 |
| Directory | /workspace/24.edn_alert_test/latest |
| Test location | /workspace/coverage/default/24.edn_disable.3196562510 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 12780290 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 12:54:41 PM PST 24 |
| Finished | Jan 21 12:54:43 PM PST 24 |
| Peak memory | 214080 kb |
| Host | smart-0d1972cc-e3c7-4175-b08e-994057142791 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196562510 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3196562510 |
| Directory | /workspace/24.edn_disable/latest |
| Test location | /workspace/coverage/default/24.edn_disable_auto_req_mode.2856950283 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 34994126 ps |
| CPU time | 1 seconds |
| Started | Jan 21 12:54:49 PM PST 24 |
| Finished | Jan 21 12:54:52 PM PST 24 |
| Peak memory | 214024 kb |
| Host | smart-81e5cf24-4dc5-43ac-8e2c-3efa2bf52f38 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856950283 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d isable_auto_req_mode.2856950283 |
| Directory | /workspace/24.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/24.edn_genbits.2899009404 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 16994829 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:54:32 PM PST 24 |
| Finished | Jan 21 12:54:33 PM PST 24 |
| Peak memory | 204472 kb |
| Host | smart-e09127c0-5723-4ace-a0db-5bb970e7f791 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2899009404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2899009404 |
| Directory | /workspace/24.edn_genbits/latest |
| Test location | /workspace/coverage/default/24.edn_intr.1387556017 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 30972673 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:54:43 PM PST 24 |
| Finished | Jan 21 12:54:45 PM PST 24 |
| Peak memory | 213888 kb |
| Host | smart-13bbe14e-6530-4b4f-9c83-5bce024b71b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1387556017 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.1387556017 |
| Directory | /workspace/24.edn_intr/latest |
| Test location | /workspace/coverage/default/24.edn_smoke.3346576728 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 16345383 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:54:33 PM PST 24 |
| Finished | Jan 21 12:54:36 PM PST 24 |
| Peak memory | 204328 kb |
| Host | smart-509fe413-b01d-45a9-95f1-2ff76b63063d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3346576728 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3346576728 |
| Directory | /workspace/24.edn_smoke/latest |
| Test location | /workspace/coverage/default/24.edn_stress_all.4156948446 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 380598281 ps |
| CPU time | 3.96 seconds |
| Started | Jan 21 12:54:43 PM PST 24 |
| Finished | Jan 21 12:54:48 PM PST 24 |
| Peak memory | 205860 kb |
| Host | smart-9cc10581-1b52-4315-8223-02ab40c50753 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156948446 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.4156948446 |
| Directory | /workspace/24.edn_stress_all/latest |
| Test location | /workspace/coverage/default/24.edn_stress_all_with_rand_reset.2106354947 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 22707711631 ps |
| CPU time | 489.66 seconds |
| Started | Jan 21 12:54:45 PM PST 24 |
| Finished | Jan 21 01:02:56 PM PST 24 |
| Peak memory | 214036 kb |
| Host | smart-d39980db-8f39-4c2c-8a09-21ef3da91ff3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106354947 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.2106354947 |
| Directory | /workspace/24.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/240.edn_genbits.3075624444 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 13840880 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 01:00:19 PM PST 24 |
| Finished | Jan 21 01:00:22 PM PST 24 |
| Peak memory | 204736 kb |
| Host | smart-8dfa0543-eafd-4545-aeef-5ed251456788 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3075624444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3075624444 |
| Directory | /workspace/240.edn_genbits/latest |
| Test location | /workspace/coverage/default/241.edn_genbits.966228428 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 26730120 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 01:00:18 PM PST 24 |
| Finished | Jan 21 01:00:20 PM PST 24 |
| Peak memory | 204908 kb |
| Host | smart-af6a11a3-c4ca-44b5-b1d6-7ab930eb3bf1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=966228428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.966228428 |
| Directory | /workspace/241.edn_genbits/latest |
| Test location | /workspace/coverage/default/242.edn_genbits.3071450597 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 28636393 ps |
| CPU time | 1.11 seconds |
| Started | Jan 21 01:00:18 PM PST 24 |
| Finished | Jan 21 01:00:22 PM PST 24 |
| Peak memory | 205296 kb |
| Host | smart-7ba817c3-7a52-4f06-82bc-78e9ce9384de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3071450597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3071450597 |
| Directory | /workspace/242.edn_genbits/latest |
| Test location | /workspace/coverage/default/243.edn_genbits.1093591025 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 19082382 ps |
| CPU time | 1.12 seconds |
| Started | Jan 21 01:00:19 PM PST 24 |
| Finished | Jan 21 01:00:22 PM PST 24 |
| Peak memory | 213780 kb |
| Host | smart-31fe9ebe-afbf-4c96-94ed-4524ddab1088 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1093591025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1093591025 |
| Directory | /workspace/243.edn_genbits/latest |
| Test location | /workspace/coverage/default/244.edn_genbits.2879707941 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 96097451 ps |
| CPU time | 1.19 seconds |
| Started | Jan 21 01:00:19 PM PST 24 |
| Finished | Jan 21 01:00:23 PM PST 24 |
| Peak memory | 205256 kb |
| Host | smart-acd82593-c3da-4bf2-b82c-f2778d02c3c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2879707941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2879707941 |
| Directory | /workspace/244.edn_genbits/latest |
| Test location | /workspace/coverage/default/245.edn_genbits.2834742378 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 52307089 ps |
| CPU time | 1.98 seconds |
| Started | Jan 21 01:00:19 PM PST 24 |
| Finished | Jan 21 01:00:24 PM PST 24 |
| Peak memory | 213836 kb |
| Host | smart-8682bd0c-04a5-40d4-b3a5-64f140f3d9e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2834742378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2834742378 |
| Directory | /workspace/245.edn_genbits/latest |
| Test location | /workspace/coverage/default/246.edn_genbits.4243344615 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 196560598 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 01:00:21 PM PST 24 |
| Finished | Jan 21 01:00:24 PM PST 24 |
| Peak memory | 204648 kb |
| Host | smart-5bba6de2-978f-41cf-8fd1-696e5eeef46d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4243344615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.4243344615 |
| Directory | /workspace/246.edn_genbits/latest |
| Test location | /workspace/coverage/default/247.edn_genbits.2882616301 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 161560071 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 01:00:21 PM PST 24 |
| Finished | Jan 21 01:00:24 PM PST 24 |
| Peak memory | 205284 kb |
| Host | smart-94e80b33-8267-4e27-ad2f-1c2e3a0eb713 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2882616301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2882616301 |
| Directory | /workspace/247.edn_genbits/latest |
| Test location | /workspace/coverage/default/248.edn_genbits.2159916429 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 21303411 ps |
| CPU time | 1.14 seconds |
| Started | Jan 21 01:00:18 PM PST 24 |
| Finished | Jan 21 01:00:20 PM PST 24 |
| Peak memory | 213812 kb |
| Host | smart-e97827a7-c58b-4d5e-9231-6968fb90d9a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2159916429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2159916429 |
| Directory | /workspace/248.edn_genbits/latest |
| Test location | /workspace/coverage/default/249.edn_genbits.677847342 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 116048607 ps |
| CPU time | 1.17 seconds |
| Started | Jan 21 01:00:18 PM PST 24 |
| Finished | Jan 21 01:00:21 PM PST 24 |
| Peak memory | 213760 kb |
| Host | smart-43d71726-2ca5-4275-bf2c-a175199541c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=677847342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.677847342 |
| Directory | /workspace/249.edn_genbits/latest |
| Test location | /workspace/coverage/default/25.edn_alert.613497407 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 20116224 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 12:54:58 PM PST 24 |
| Finished | Jan 21 12:55:00 PM PST 24 |
| Peak memory | 205528 kb |
| Host | smart-3382093a-af13-4a8b-9c06-c64ecf1cafec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=613497407 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.613497407 |
| Directory | /workspace/25.edn_alert/latest |
| Test location | /workspace/coverage/default/25.edn_alert_test.1954369592 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 164047492 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 01:58:37 PM PST 24 |
| Finished | Jan 21 01:58:39 PM PST 24 |
| Peak memory | 204148 kb |
| Host | smart-c641e649-94ea-4196-b3aa-8bc35cd58fc6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954369592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1954369592 |
| Directory | /workspace/25.edn_alert_test/latest |
| Test location | /workspace/coverage/default/25.edn_disable.1452375632 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 11337627 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:54:54 PM PST 24 |
| Finished | Jan 21 12:54:55 PM PST 24 |
| Peak memory | 213928 kb |
| Host | smart-d5293fe8-6564-4ddb-97e9-4bb634cbb799 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452375632 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1452375632 |
| Directory | /workspace/25.edn_disable/latest |
| Test location | /workspace/coverage/default/25.edn_disable_auto_req_mode.1989804784 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 37800060 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:54:55 PM PST 24 |
| Finished | Jan 21 12:54:57 PM PST 24 |
| Peak memory | 214164 kb |
| Host | smart-91eac3ae-eea7-4c89-a85c-d132c900e1bf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989804784 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d isable_auto_req_mode.1989804784 |
| Directory | /workspace/25.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/25.edn_err.1867386035 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 20869497 ps |
| CPU time | 1 seconds |
| Started | Jan 21 01:47:04 PM PST 24 |
| Finished | Jan 21 01:47:11 PM PST 24 |
| Peak memory | 221080 kb |
| Host | smart-776e6dbe-d311-4e7d-8ff9-441a98257081 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1867386035 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1867386035 |
| Directory | /workspace/25.edn_err/latest |
| Test location | /workspace/coverage/default/25.edn_genbits.3905404546 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 61984246 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 12:54:43 PM PST 24 |
| Finished | Jan 21 12:54:45 PM PST 24 |
| Peak memory | 204904 kb |
| Host | smart-d873e930-9a0c-49d4-b092-6941640cd13a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3905404546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3905404546 |
| Directory | /workspace/25.edn_genbits/latest |
| Test location | /workspace/coverage/default/25.edn_intr.2056741585 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 19695084 ps |
| CPU time | 1.14 seconds |
| Started | Jan 21 01:04:11 PM PST 24 |
| Finished | Jan 21 01:04:13 PM PST 24 |
| Peak memory | 220948 kb |
| Host | smart-e372589e-3eda-47c1-aef8-d315ccbc958f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056741585 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2056741585 |
| Directory | /workspace/25.edn_intr/latest |
| Test location | /workspace/coverage/default/25.edn_smoke.2248550317 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 30718672 ps |
| CPU time | 0.87 seconds |
| Started | Jan 21 01:32:41 PM PST 24 |
| Finished | Jan 21 01:32:45 PM PST 24 |
| Peak memory | 204564 kb |
| Host | smart-6602120e-2a88-4786-bb3d-9d03760cffd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2248550317 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2248550317 |
| Directory | /workspace/25.edn_smoke/latest |
| Test location | /workspace/coverage/default/25.edn_stress_all.3602367136 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 183901958 ps |
| CPU time | 2.41 seconds |
| Started | Jan 21 12:54:45 PM PST 24 |
| Finished | Jan 21 12:54:48 PM PST 24 |
| Peak memory | 205544 kb |
| Host | smart-b4ecde4e-c7bb-4d4d-9451-65b40386178c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602367136 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3602367136 |
| Directory | /workspace/25.edn_stress_all/latest |
| Test location | /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2508060305 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 14835447529 ps |
| CPU time | 199.68 seconds |
| Started | Jan 21 12:54:41 PM PST 24 |
| Finished | Jan 21 12:58:02 PM PST 24 |
| Peak memory | 215032 kb |
| Host | smart-66662626-4651-4f86-af27-90aff0d6eadb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508060305 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2508060305 |
| Directory | /workspace/25.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/250.edn_genbits.857682257 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 42817190 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 01:00:17 PM PST 24 |
| Finished | Jan 21 01:00:19 PM PST 24 |
| Peak memory | 213716 kb |
| Host | smart-371c5eb5-193f-4373-9be2-a7eceb968a33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=857682257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.857682257 |
| Directory | /workspace/250.edn_genbits/latest |
| Test location | /workspace/coverage/default/252.edn_genbits.3016063347 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 231226445 ps |
| CPU time | 1.07 seconds |
| Started | Jan 21 01:00:19 PM PST 24 |
| Finished | Jan 21 01:00:22 PM PST 24 |
| Peak memory | 204456 kb |
| Host | smart-7db1caeb-5cb1-44ed-ad01-5dab92d9a38a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3016063347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3016063347 |
| Directory | /workspace/252.edn_genbits/latest |
| Test location | /workspace/coverage/default/253.edn_genbits.2620691628 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 23391720 ps |
| CPU time | 1.21 seconds |
| Started | Jan 21 01:00:19 PM PST 24 |
| Finished | Jan 21 01:00:23 PM PST 24 |
| Peak memory | 213788 kb |
| Host | smart-30b76154-59b6-49ec-9668-31990af04aa3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2620691628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.2620691628 |
| Directory | /workspace/253.edn_genbits/latest |
| Test location | /workspace/coverage/default/254.edn_genbits.1777978757 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 35674107 ps |
| CPU time | 1.04 seconds |
| Started | Jan 21 01:00:18 PM PST 24 |
| Finished | Jan 21 01:00:22 PM PST 24 |
| Peak memory | 213728 kb |
| Host | smart-4e9ccf39-1ac1-4cde-b276-f6d6e5e05793 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1777978757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1777978757 |
| Directory | /workspace/254.edn_genbits/latest |
| Test location | /workspace/coverage/default/256.edn_genbits.3027517789 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 19959985 ps |
| CPU time | 1.15 seconds |
| Started | Jan 21 01:00:19 PM PST 24 |
| Finished | Jan 21 01:00:22 PM PST 24 |
| Peak memory | 204896 kb |
| Host | smart-764c6dbd-83b0-487d-a14c-7dbc5efef94a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3027517789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3027517789 |
| Directory | /workspace/256.edn_genbits/latest |
| Test location | /workspace/coverage/default/257.edn_genbits.4195306255 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 23466352 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 01:00:23 PM PST 24 |
| Finished | Jan 21 01:00:26 PM PST 24 |
| Peak memory | 213644 kb |
| Host | smart-6e254e76-f729-4ec0-8987-a3a8f26ef73c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4195306255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.4195306255 |
| Directory | /workspace/257.edn_genbits/latest |
| Test location | /workspace/coverage/default/258.edn_genbits.3777753988 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 80892380 ps |
| CPU time | 1.11 seconds |
| Started | Jan 21 01:00:23 PM PST 24 |
| Finished | Jan 21 01:00:26 PM PST 24 |
| Peak memory | 213660 kb |
| Host | smart-c6e3b959-adee-46d1-bfda-05393bbaa0b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3777753988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3777753988 |
| Directory | /workspace/258.edn_genbits/latest |
| Test location | /workspace/coverage/default/26.edn_alert.2508638331 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 36804759 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 12:55:00 PM PST 24 |
| Finished | Jan 21 12:55:02 PM PST 24 |
| Peak memory | 205440 kb |
| Host | smart-10cd832a-e7db-41f8-828e-967d0b773ae4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2508638331 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2508638331 |
| Directory | /workspace/26.edn_alert/latest |
| Test location | /workspace/coverage/default/26.edn_alert_test.1558748122 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 19763526 ps |
| CPU time | 0.74 seconds |
| Started | Jan 21 12:55:00 PM PST 24 |
| Finished | Jan 21 12:55:02 PM PST 24 |
| Peak memory | 203512 kb |
| Host | smart-20f43bd4-0a95-4e02-9e87-e7961d84a358 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558748122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1558748122 |
| Directory | /workspace/26.edn_alert_test/latest |
| Test location | /workspace/coverage/default/26.edn_disable.1286068877 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 28478379 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 12:54:55 PM PST 24 |
| Finished | Jan 21 12:54:56 PM PST 24 |
| Peak memory | 213904 kb |
| Host | smart-0e10ccfa-b190-4aa8-92b5-f55434fef27b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286068877 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1286068877 |
| Directory | /workspace/26.edn_disable/latest |
| Test location | /workspace/coverage/default/26.edn_disable_auto_req_mode.2792617115 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 47145388 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:54:58 PM PST 24 |
| Finished | Jan 21 12:55:00 PM PST 24 |
| Peak memory | 214076 kb |
| Host | smart-832204bd-bf39-47a8-94d5-545797f155ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792617115 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d isable_auto_req_mode.2792617115 |
| Directory | /workspace/26.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/26.edn_err.2426774267 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 25031361 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 01:07:38 PM PST 24 |
| Finished | Jan 21 01:07:45 PM PST 24 |
| Peak memory | 220568 kb |
| Host | smart-52c6dc15-5e9c-45da-a1d6-40d8b55464d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2426774267 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2426774267 |
| Directory | /workspace/26.edn_err/latest |
| Test location | /workspace/coverage/default/26.edn_genbits.1136685816 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 21783312 ps |
| CPU time | 1.24 seconds |
| Started | Jan 21 01:09:34 PM PST 24 |
| Finished | Jan 21 01:09:36 PM PST 24 |
| Peak memory | 205388 kb |
| Host | smart-3877f92f-dde1-4b89-ab5a-0917721c15a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1136685816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1136685816 |
| Directory | /workspace/26.edn_genbits/latest |
| Test location | /workspace/coverage/default/26.edn_intr.513340469 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 20336400 ps |
| CPU time | 1.15 seconds |
| Started | Jan 21 01:08:51 PM PST 24 |
| Finished | Jan 21 01:08:53 PM PST 24 |
| Peak memory | 221412 kb |
| Host | smart-bb42bd70-b4bf-424d-b09f-f7c04b833a06 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=513340469 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.513340469 |
| Directory | /workspace/26.edn_intr/latest |
| Test location | /workspace/coverage/default/26.edn_smoke.877962753 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 31001151 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 01:21:08 PM PST 24 |
| Finished | Jan 21 01:21:10 PM PST 24 |
| Peak memory | 204252 kb |
| Host | smart-b9efa907-ef08-4a26-98d3-7c6efd04c040 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=877962753 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.877962753 |
| Directory | /workspace/26.edn_smoke/latest |
| Test location | /workspace/coverage/default/26.edn_stress_all.3409442546 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 321777890 ps |
| CPU time | 4 seconds |
| Started | Jan 21 01:19:03 PM PST 24 |
| Finished | Jan 21 01:19:08 PM PST 24 |
| Peak memory | 205944 kb |
| Host | smart-78a7f2e4-815c-47ce-b7be-bfdbb782b3ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409442546 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3409442546 |
| Directory | /workspace/26.edn_stress_all/latest |
| Test location | /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2543459651 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 219347024204 ps |
| CPU time | 835.32 seconds |
| Started | Jan 21 01:13:16 PM PST 24 |
| Finished | Jan 21 01:27:12 PM PST 24 |
| Peak memory | 214848 kb |
| Host | smart-7e5eeb5e-8608-4df6-972a-48a2cd01cf51 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543459651 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2543459651 |
| Directory | /workspace/26.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/260.edn_genbits.2217542217 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 29674493 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 01:00:30 PM PST 24 |
| Finished | Jan 21 01:00:33 PM PST 24 |
| Peak memory | 205228 kb |
| Host | smart-19766881-40bb-41e1-849b-8430714b8bf5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2217542217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2217542217 |
| Directory | /workspace/260.edn_genbits/latest |
| Test location | /workspace/coverage/default/262.edn_genbits.1486339520 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 26824365 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 01:56:22 PM PST 24 |
| Finished | Jan 21 01:56:24 PM PST 24 |
| Peak memory | 204596 kb |
| Host | smart-719fe704-5ffa-452a-b551-2d685008d574 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1486339520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1486339520 |
| Directory | /workspace/262.edn_genbits/latest |
| Test location | /workspace/coverage/default/264.edn_genbits.697743622 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 18050677 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 01:00:40 PM PST 24 |
| Finished | Jan 21 01:00:42 PM PST 24 |
| Peak memory | 204988 kb |
| Host | smart-099d747d-2e66-4cf4-a52d-ca2d7ac2bff0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=697743622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.697743622 |
| Directory | /workspace/264.edn_genbits/latest |
| Test location | /workspace/coverage/default/265.edn_genbits.1640224611 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 17362399 ps |
| CPU time | 1.16 seconds |
| Started | Jan 21 01:00:29 PM PST 24 |
| Finished | Jan 21 01:00:32 PM PST 24 |
| Peak memory | 205024 kb |
| Host | smart-9676b91d-5d97-4c8b-b6dc-c746e3c8d20e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1640224611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1640224611 |
| Directory | /workspace/265.edn_genbits/latest |
| Test location | /workspace/coverage/default/266.edn_genbits.900973542 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 25948226 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 01:00:29 PM PST 24 |
| Finished | Jan 21 01:00:32 PM PST 24 |
| Peak memory | 204940 kb |
| Host | smart-ec7eb151-f078-4dc1-b6d8-c41b71f4f992 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=900973542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.900973542 |
| Directory | /workspace/266.edn_genbits/latest |
| Test location | /workspace/coverage/default/268.edn_genbits.1495015062 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 15845652 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 01:00:40 PM PST 24 |
| Finished | Jan 21 01:00:42 PM PST 24 |
| Peak memory | 204944 kb |
| Host | smart-8b70fa2d-45d9-42d6-9e95-2a9336f63b57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1495015062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1495015062 |
| Directory | /workspace/268.edn_genbits/latest |
| Test location | /workspace/coverage/default/269.edn_genbits.328258759 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 62622063 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 01:00:30 PM PST 24 |
| Finished | Jan 21 01:00:33 PM PST 24 |
| Peak memory | 205064 kb |
| Host | smart-198bf248-350a-4261-b546-d9e2e6fb9bf3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=328258759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.328258759 |
| Directory | /workspace/269.edn_genbits/latest |
| Test location | /workspace/coverage/default/27.edn_alert.418933235 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 84336817 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:55:03 PM PST 24 |
| Finished | Jan 21 12:55:05 PM PST 24 |
| Peak memory | 205120 kb |
| Host | smart-4a61039b-2da4-4d80-b387-ee047ecf7a80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=418933235 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.418933235 |
| Directory | /workspace/27.edn_alert/latest |
| Test location | /workspace/coverage/default/27.edn_alert_test.2198132486 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 44165736 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 02:38:19 PM PST 24 |
| Finished | Jan 21 02:38:23 PM PST 24 |
| Peak memory | 204036 kb |
| Host | smart-c498f80a-71f6-49a5-b7ad-7f6c2b7e5acd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198132486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2198132486 |
| Directory | /workspace/27.edn_alert_test/latest |
| Test location | /workspace/coverage/default/27.edn_disable.4103296790 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 28827881 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 02:05:49 PM PST 24 |
| Finished | Jan 21 02:05:51 PM PST 24 |
| Peak memory | 214308 kb |
| Host | smart-8838ce9b-bf9a-46c9-b3c1-44479e2b7360 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103296790 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.4103296790 |
| Directory | /workspace/27.edn_disable/latest |
| Test location | /workspace/coverage/default/27.edn_disable_auto_req_mode.111561998 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 262552797 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:55:07 PM PST 24 |
| Finished | Jan 21 12:55:09 PM PST 24 |
| Peak memory | 214092 kb |
| Host | smart-8379dfe0-bbe3-4795-9a54-f4f09a6e23ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111561998 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di sable_auto_req_mode.111561998 |
| Directory | /workspace/27.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/27.edn_err.2309680367 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 42599528 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:55:07 PM PST 24 |
| Finished | Jan 21 12:55:08 PM PST 24 |
| Peak memory | 214992 kb |
| Host | smart-32264f0e-260f-42a4-a615-0b346f5e1173 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2309680367 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2309680367 |
| Directory | /workspace/27.edn_err/latest |
| Test location | /workspace/coverage/default/27.edn_genbits.3163501891 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 41507226 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:55:00 PM PST 24 |
| Finished | Jan 21 12:55:02 PM PST 24 |
| Peak memory | 204548 kb |
| Host | smart-ffd591b4-e773-48b8-8603-3b05627fe1f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3163501891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.3163501891 |
| Directory | /workspace/27.edn_genbits/latest |
| Test location | /workspace/coverage/default/27.edn_intr.1890664102 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 18210035 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 12:55:00 PM PST 24 |
| Finished | Jan 21 12:55:02 PM PST 24 |
| Peak memory | 214036 kb |
| Host | smart-97678633-82e4-4b2a-88d2-9c83f1ce9055 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1890664102 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1890664102 |
| Directory | /workspace/27.edn_intr/latest |
| Test location | /workspace/coverage/default/27.edn_smoke.2921627133 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 61498527 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:55:00 PM PST 24 |
| Finished | Jan 21 12:55:02 PM PST 24 |
| Peak memory | 204444 kb |
| Host | smart-e390ce0c-0b3a-4c6c-b7c7-9b5cc3426b45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2921627133 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.2921627133 |
| Directory | /workspace/27.edn_smoke/latest |
| Test location | /workspace/coverage/default/27.edn_stress_all.2988216750 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 124997071 ps |
| CPU time | 3.36 seconds |
| Started | Jan 21 12:55:01 PM PST 24 |
| Finished | Jan 21 12:55:05 PM PST 24 |
| Peak memory | 205548 kb |
| Host | smart-6d23a2c3-7120-4267-befc-b63550429993 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988216750 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.2988216750 |
| Directory | /workspace/27.edn_stress_all/latest |
| Test location | /workspace/coverage/default/270.edn_genbits.2048213116 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 14569430 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 01:00:30 PM PST 24 |
| Finished | Jan 21 01:00:33 PM PST 24 |
| Peak memory | 204912 kb |
| Host | smart-9e71d38c-5266-4ea8-a1ee-fcd5370f7bc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2048213116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2048213116 |
| Directory | /workspace/270.edn_genbits/latest |
| Test location | /workspace/coverage/default/271.edn_genbits.2345675834 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 155775006 ps |
| CPU time | 2.6 seconds |
| Started | Jan 21 01:41:18 PM PST 24 |
| Finished | Jan 21 01:41:21 PM PST 24 |
| Peak memory | 213832 kb |
| Host | smart-446aaaa5-8e7d-4976-aa52-10bc78203721 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2345675834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2345675834 |
| Directory | /workspace/271.edn_genbits/latest |
| Test location | /workspace/coverage/default/273.edn_genbits.2960267358 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 17893553 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 01:41:20 PM PST 24 |
| Finished | Jan 21 01:41:22 PM PST 24 |
| Peak memory | 213876 kb |
| Host | smart-ad9fe8d3-88e6-4873-b054-c97b6d6aa244 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2960267358 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2960267358 |
| Directory | /workspace/273.edn_genbits/latest |
| Test location | /workspace/coverage/default/274.edn_genbits.4053869516 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 16059213 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 01:09:19 PM PST 24 |
| Finished | Jan 21 01:09:21 PM PST 24 |
| Peak memory | 205444 kb |
| Host | smart-fd414256-6b64-4a9c-a539-d59dfa4161b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4053869516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.4053869516 |
| Directory | /workspace/274.edn_genbits/latest |
| Test location | /workspace/coverage/default/275.edn_genbits.2111253588 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 17550975 ps |
| CPU time | 0.94 seconds |
| Started | Jan 21 01:00:35 PM PST 24 |
| Finished | Jan 21 01:00:37 PM PST 24 |
| Peak memory | 204804 kb |
| Host | smart-4c376907-0543-4f1b-864a-6c1b6caca23d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2111253588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2111253588 |
| Directory | /workspace/275.edn_genbits/latest |
| Test location | /workspace/coverage/default/276.edn_genbits.1581146174 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 26088948 ps |
| CPU time | 1.2 seconds |
| Started | Jan 21 01:00:35 PM PST 24 |
| Finished | Jan 21 01:00:37 PM PST 24 |
| Peak memory | 213768 kb |
| Host | smart-cd7408a9-9b9e-43ea-bdf4-d5b40fb3505b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1581146174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1581146174 |
| Directory | /workspace/276.edn_genbits/latest |
| Test location | /workspace/coverage/default/278.edn_genbits.3482864727 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 78598414 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 01:00:36 PM PST 24 |
| Finished | Jan 21 01:00:39 PM PST 24 |
| Peak memory | 204648 kb |
| Host | smart-30aa707f-0192-4a48-85a2-e6e90be9b3b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3482864727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3482864727 |
| Directory | /workspace/278.edn_genbits/latest |
| Test location | /workspace/coverage/default/279.edn_genbits.2403655366 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 49226144 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 01:34:16 PM PST 24 |
| Finished | Jan 21 01:34:18 PM PST 24 |
| Peak memory | 204856 kb |
| Host | smart-e1ca840b-4c87-42bb-8bcd-2828a52b7c3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2403655366 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2403655366 |
| Directory | /workspace/279.edn_genbits/latest |
| Test location | /workspace/coverage/default/28.edn_alert_test.2900198599 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 22661781 ps |
| CPU time | 1.05 seconds |
| Started | Jan 21 12:55:18 PM PST 24 |
| Finished | Jan 21 12:55:20 PM PST 24 |
| Peak memory | 204656 kb |
| Host | smart-bb35a163-9eb7-4c50-8595-8e12c4e66872 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900198599 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2900198599 |
| Directory | /workspace/28.edn_alert_test/latest |
| Test location | /workspace/coverage/default/28.edn_disable.2605194199 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 33824596 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:55:17 PM PST 24 |
| Finished | Jan 21 12:55:19 PM PST 24 |
| Peak memory | 213952 kb |
| Host | smart-93f12a8e-fce3-46b8-ab4e-5c5aae79ad9b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605194199 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2605194199 |
| Directory | /workspace/28.edn_disable/latest |
| Test location | /workspace/coverage/default/28.edn_disable_auto_req_mode.3878350273 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 30252131 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 12:55:25 PM PST 24 |
| Finished | Jan 21 12:55:27 PM PST 24 |
| Peak memory | 214208 kb |
| Host | smart-c7b862cd-f27a-47f0-b4ae-5893fb83695e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878350273 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d isable_auto_req_mode.3878350273 |
| Directory | /workspace/28.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/28.edn_genbits.3369981589 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 142259182 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:55:07 PM PST 24 |
| Finished | Jan 21 12:55:08 PM PST 24 |
| Peak memory | 204624 kb |
| Host | smart-4832eefc-6a4e-4c62-9224-259277093c33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3369981589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.3369981589 |
| Directory | /workspace/28.edn_genbits/latest |
| Test location | /workspace/coverage/default/28.edn_intr.2924119813 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 33665659 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:55:10 PM PST 24 |
| Finished | Jan 21 12:55:11 PM PST 24 |
| Peak memory | 224908 kb |
| Host | smart-5520e923-5c2d-4725-aac7-4ac17a4c9f8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924119813 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2924119813 |
| Directory | /workspace/28.edn_intr/latest |
| Test location | /workspace/coverage/default/28.edn_smoke.1471662375 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 35077682 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:55:11 PM PST 24 |
| Finished | Jan 21 12:55:12 PM PST 24 |
| Peak memory | 204416 kb |
| Host | smart-8e172b05-171f-46dd-93a6-52f70115266d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1471662375 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1471662375 |
| Directory | /workspace/28.edn_smoke/latest |
| Test location | /workspace/coverage/default/28.edn_stress_all.2807198897 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 123814627 ps |
| CPU time | 2.93 seconds |
| Started | Jan 21 12:55:08 PM PST 24 |
| Finished | Jan 21 12:55:11 PM PST 24 |
| Peak memory | 205748 kb |
| Host | smart-b6fcae68-e27f-41fb-bbb5-d48c5de5e312 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807198897 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2807198897 |
| Directory | /workspace/28.edn_stress_all/latest |
| Test location | /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2765584213 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 823621600026 ps |
| CPU time | 1696.79 seconds |
| Started | Jan 21 12:55:06 PM PST 24 |
| Finished | Jan 21 01:23:23 PM PST 24 |
| Peak memory | 217688 kb |
| Host | smart-f54f6475-2160-4277-9cd7-b51edb923f8c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765584213 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2765584213 |
| Directory | /workspace/28.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/280.edn_genbits.1408567251 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 75185800 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 01:00:40 PM PST 24 |
| Finished | Jan 21 01:00:42 PM PST 24 |
| Peak memory | 205064 kb |
| Host | smart-c1d1fd89-452c-45aa-82b7-11ba8125cf01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1408567251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1408567251 |
| Directory | /workspace/280.edn_genbits/latest |
| Test location | /workspace/coverage/default/281.edn_genbits.2641215116 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 38960644 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 01:00:35 PM PST 24 |
| Finished | Jan 21 01:00:38 PM PST 24 |
| Peak memory | 205052 kb |
| Host | smart-5bd75c41-6369-4266-8153-68bac65cc325 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2641215116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2641215116 |
| Directory | /workspace/281.edn_genbits/latest |
| Test location | /workspace/coverage/default/282.edn_genbits.2342837418 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 47848563 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 01:00:38 PM PST 24 |
| Finished | Jan 21 01:00:40 PM PST 24 |
| Peak memory | 204536 kb |
| Host | smart-62a4770e-7f57-431a-8e33-438dff2f9d95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2342837418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2342837418 |
| Directory | /workspace/282.edn_genbits/latest |
| Test location | /workspace/coverage/default/283.edn_genbits.472522193 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 21706545 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 03:12:32 PM PST 24 |
| Finished | Jan 21 03:12:34 PM PST 24 |
| Peak memory | 213840 kb |
| Host | smart-afa103a6-b2c9-4b0d-a1df-7873a1867aab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=472522193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.472522193 |
| Directory | /workspace/283.edn_genbits/latest |
| Test location | /workspace/coverage/default/285.edn_genbits.3698600453 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 67084742 ps |
| CPU time | 2.55 seconds |
| Started | Jan 21 01:00:42 PM PST 24 |
| Finished | Jan 21 01:00:45 PM PST 24 |
| Peak memory | 213740 kb |
| Host | smart-d63c0bf8-8934-4603-93c0-7a70d0f463d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3698600453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3698600453 |
| Directory | /workspace/285.edn_genbits/latest |
| Test location | /workspace/coverage/default/286.edn_genbits.235482422 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 17524208 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 01:00:43 PM PST 24 |
| Finished | Jan 21 01:00:45 PM PST 24 |
| Peak memory | 205044 kb |
| Host | smart-83b923ee-5ac5-42b9-bfd5-3510ed9f0f10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=235482422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.235482422 |
| Directory | /workspace/286.edn_genbits/latest |
| Test location | /workspace/coverage/default/287.edn_genbits.2627361162 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 18881114 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 01:00:47 PM PST 24 |
| Finished | Jan 21 01:00:49 PM PST 24 |
| Peak memory | 204792 kb |
| Host | smart-4e32f6ac-38b1-4a4f-ac7c-baf8080b98ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2627361162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2627361162 |
| Directory | /workspace/287.edn_genbits/latest |
| Test location | /workspace/coverage/default/288.edn_genbits.3072987479 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 37546605 ps |
| CPU time | 1.58 seconds |
| Started | Jan 21 01:00:48 PM PST 24 |
| Finished | Jan 21 01:00:51 PM PST 24 |
| Peak memory | 213772 kb |
| Host | smart-0f1d96ab-d82a-4fb1-b7fb-06c57cc5247c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3072987479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3072987479 |
| Directory | /workspace/288.edn_genbits/latest |
| Test location | /workspace/coverage/default/289.edn_genbits.238649363 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 105436455 ps |
| CPU time | 2.63 seconds |
| Started | Jan 21 01:00:43 PM PST 24 |
| Finished | Jan 21 01:00:47 PM PST 24 |
| Peak memory | 214084 kb |
| Host | smart-7c100af0-39dd-4c96-aea6-667fd7ea150c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=238649363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.238649363 |
| Directory | /workspace/289.edn_genbits/latest |
| Test location | /workspace/coverage/default/29.edn_alert.887472161 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 64493253 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:55:17 PM PST 24 |
| Finished | Jan 21 12:55:19 PM PST 24 |
| Peak memory | 204612 kb |
| Host | smart-7d5e87cc-e85c-45b9-bae5-afe7ec7d8db5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=887472161 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.887472161 |
| Directory | /workspace/29.edn_alert/latest |
| Test location | /workspace/coverage/default/29.edn_alert_test.2102142165 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 13446033 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:55:22 PM PST 24 |
| Finished | Jan 21 12:55:23 PM PST 24 |
| Peak memory | 204000 kb |
| Host | smart-09f9356d-e0f3-4335-b30a-f6bae3626ffe |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102142165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.2102142165 |
| Directory | /workspace/29.edn_alert_test/latest |
| Test location | /workspace/coverage/default/29.edn_disable.1157622976 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 13956468 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:55:25 PM PST 24 |
| Finished | Jan 21 12:55:27 PM PST 24 |
| Peak memory | 214128 kb |
| Host | smart-66b49689-cd1d-4afb-917a-fb0c05b94617 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157622976 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1157622976 |
| Directory | /workspace/29.edn_disable/latest |
| Test location | /workspace/coverage/default/29.edn_disable_auto_req_mode.2801799787 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 35364413 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:55:18 PM PST 24 |
| Finished | Jan 21 12:55:20 PM PST 24 |
| Peak memory | 205952 kb |
| Host | smart-859f6f08-4d68-4e95-b446-0f6d236eedba |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801799787 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d isable_auto_req_mode.2801799787 |
| Directory | /workspace/29.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/29.edn_err.374362074 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 23173996 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:55:18 PM PST 24 |
| Finished | Jan 21 12:55:20 PM PST 24 |
| Peak memory | 215312 kb |
| Host | smart-e26e9cb3-fbd6-44da-9d15-29077f4435c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=374362074 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.374362074 |
| Directory | /workspace/29.edn_err/latest |
| Test location | /workspace/coverage/default/29.edn_genbits.3583195368 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 102315947 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:55:16 PM PST 24 |
| Finished | Jan 21 12:55:17 PM PST 24 |
| Peak memory | 204400 kb |
| Host | smart-c6d2bfc4-d9c2-4c0a-a15c-4872ee51322f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3583195368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3583195368 |
| Directory | /workspace/29.edn_genbits/latest |
| Test location | /workspace/coverage/default/29.edn_intr.1815397074 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 30863967 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:55:22 PM PST 24 |
| Finished | Jan 21 12:55:24 PM PST 24 |
| Peak memory | 213856 kb |
| Host | smart-fabc5d55-4e23-42fb-84a7-7bdcbaecdf89 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1815397074 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1815397074 |
| Directory | /workspace/29.edn_intr/latest |
| Test location | /workspace/coverage/default/29.edn_smoke.561929754 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 15914004 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:55:22 PM PST 24 |
| Finished | Jan 21 12:55:23 PM PST 24 |
| Peak memory | 204536 kb |
| Host | smart-0b68e10f-5021-4226-82ba-0d7297e09280 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=561929754 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.561929754 |
| Directory | /workspace/29.edn_smoke/latest |
| Test location | /workspace/coverage/default/29.edn_stress_all.258894590 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 459875363 ps |
| CPU time | 2.9 seconds |
| Started | Jan 21 12:55:25 PM PST 24 |
| Finished | Jan 21 12:55:28 PM PST 24 |
| Peak memory | 205568 kb |
| Host | smart-7f1dcd06-ef23-41cc-81eb-3ba88320f08e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258894590 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.258894590 |
| Directory | /workspace/29.edn_stress_all/latest |
| Test location | /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3825056662 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 88405366837 ps |
| CPU time | 1149.28 seconds |
| Started | Jan 21 12:55:25 PM PST 24 |
| Finished | Jan 21 01:14:35 PM PST 24 |
| Peak memory | 218212 kb |
| Host | smart-863ef145-637b-48ec-bec6-55bd4eaa5c9c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825056662 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3825056662 |
| Directory | /workspace/29.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/291.edn_genbits.262222173 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 56612514 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 02:36:28 PM PST 24 |
| Finished | Jan 21 02:36:29 PM PST 24 |
| Peak memory | 204748 kb |
| Host | smart-f0ab1a11-033b-4970-8cc5-61befc61759a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=262222173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.262222173 |
| Directory | /workspace/291.edn_genbits/latest |
| Test location | /workspace/coverage/default/292.edn_genbits.944992305 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 14688034 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 01:32:10 PM PST 24 |
| Finished | Jan 21 01:32:12 PM PST 24 |
| Peak memory | 204632 kb |
| Host | smart-a236b3f2-f045-4993-836a-951032756c0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=944992305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.944992305 |
| Directory | /workspace/292.edn_genbits/latest |
| Test location | /workspace/coverage/default/293.edn_genbits.1062712694 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 30134257 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 01:00:46 PM PST 24 |
| Finished | Jan 21 01:00:47 PM PST 24 |
| Peak memory | 204432 kb |
| Host | smart-1656a416-a0e7-455d-a6a3-545eee74c8f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1062712694 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1062712694 |
| Directory | /workspace/293.edn_genbits/latest |
| Test location | /workspace/coverage/default/294.edn_genbits.2713285964 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 19645457 ps |
| CPU time | 1.18 seconds |
| Started | Jan 21 01:00:47 PM PST 24 |
| Finished | Jan 21 01:00:49 PM PST 24 |
| Peak memory | 205076 kb |
| Host | smart-a1be6c3c-3ef5-4bba-9d21-bfa1ddc6a15f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2713285964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2713285964 |
| Directory | /workspace/294.edn_genbits/latest |
| Test location | /workspace/coverage/default/295.edn_genbits.1035374153 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 22539705 ps |
| CPU time | 1.15 seconds |
| Started | Jan 21 01:00:48 PM PST 24 |
| Finished | Jan 21 01:00:50 PM PST 24 |
| Peak memory | 205100 kb |
| Host | smart-935b0956-023c-4c0c-9ca6-5ca3cc40b0c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1035374153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1035374153 |
| Directory | /workspace/295.edn_genbits/latest |
| Test location | /workspace/coverage/default/296.edn_genbits.2223368662 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 17944880 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 01:35:14 PM PST 24 |
| Finished | Jan 21 01:35:15 PM PST 24 |
| Peak memory | 204920 kb |
| Host | smart-6744d6b3-9946-4fe7-9e6e-045650d5fc59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2223368662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2223368662 |
| Directory | /workspace/296.edn_genbits/latest |
| Test location | /workspace/coverage/default/297.edn_genbits.1963334914 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 58004267 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 01:01:02 PM PST 24 |
| Finished | Jan 21 01:01:04 PM PST 24 |
| Peak memory | 204832 kb |
| Host | smart-9b410e7b-27c2-449e-911f-29c1286be1b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1963334914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1963334914 |
| Directory | /workspace/297.edn_genbits/latest |
| Test location | /workspace/coverage/default/298.edn_genbits.3170023885 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 15992139 ps |
| CPU time | 1.01 seconds |
| Started | Jan 21 01:00:54 PM PST 24 |
| Finished | Jan 21 01:00:56 PM PST 24 |
| Peak memory | 205096 kb |
| Host | smart-2a55e36f-8276-46fb-a43d-ad10fb40e699 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3170023885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3170023885 |
| Directory | /workspace/298.edn_genbits/latest |
| Test location | /workspace/coverage/default/299.edn_genbits.724557835 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 63506733 ps |
| CPU time | 1.54 seconds |
| Started | Jan 21 01:00:53 PM PST 24 |
| Finished | Jan 21 01:00:56 PM PST 24 |
| Peak memory | 213748 kb |
| Host | smart-54678e11-8268-499a-906c-bbe8290aae22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=724557835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.724557835 |
| Directory | /workspace/299.edn_genbits/latest |
| Test location | /workspace/coverage/default/3.edn_alert.121681435 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 58835494 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:51:45 PM PST 24 |
| Finished | Jan 21 12:51:47 PM PST 24 |
| Peak memory | 204696 kb |
| Host | smart-9f90d0e9-3e25-493f-b876-239578cfe2ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=121681435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.121681435 |
| Directory | /workspace/3.edn_alert/latest |
| Test location | /workspace/coverage/default/3.edn_alert_test.3453244615 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 79968692 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:51:48 PM PST 24 |
| Finished | Jan 21 12:51:53 PM PST 24 |
| Peak memory | 203972 kb |
| Host | smart-7c62818d-f427-462a-9510-902f774348c7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453244615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3453244615 |
| Directory | /workspace/3.edn_alert_test/latest |
| Test location | /workspace/coverage/default/3.edn_disable.1366743712 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 11941004 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:51:42 PM PST 24 |
| Finished | Jan 21 12:51:44 PM PST 24 |
| Peak memory | 213900 kb |
| Host | smart-39feb8b0-3510-497f-9cfa-2112dbc80c12 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366743712 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1366743712 |
| Directory | /workspace/3.edn_disable/latest |
| Test location | /workspace/coverage/default/3.edn_disable_auto_req_mode.1079696419 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 20525135 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:51:40 PM PST 24 |
| Finished | Jan 21 12:51:42 PM PST 24 |
| Peak memory | 214128 kb |
| Host | smart-222e11db-e02b-43c2-b3e2-65f21e8cab97 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079696419 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di sable_auto_req_mode.1079696419 |
| Directory | /workspace/3.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/3.edn_err.1970681362 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 18032570 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 01:57:53 PM PST 24 |
| Finished | Jan 21 01:58:00 PM PST 24 |
| Peak memory | 215240 kb |
| Host | smart-2bb537d9-ce4d-45d3-b71f-db1b76a1c39b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1970681362 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1970681362 |
| Directory | /workspace/3.edn_err/latest |
| Test location | /workspace/coverage/default/3.edn_genbits.341180692 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 356295091 ps |
| CPU time | 3.22 seconds |
| Started | Jan 21 12:51:42 PM PST 24 |
| Finished | Jan 21 12:51:46 PM PST 24 |
| Peak memory | 213716 kb |
| Host | smart-ea416173-dc63-44b3-841b-f52f83db0fdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=341180692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.341180692 |
| Directory | /workspace/3.edn_genbits/latest |
| Test location | /workspace/coverage/default/3.edn_intr.3519642446 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 23072370 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:51:41 PM PST 24 |
| Finished | Jan 21 12:51:43 PM PST 24 |
| Peak memory | 213796 kb |
| Host | smart-48e06534-7b3b-4452-bae0-631485ed2f00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3519642446 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3519642446 |
| Directory | /workspace/3.edn_intr/latest |
| Test location | /workspace/coverage/default/3.edn_regwen.1271015957 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 23988000 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 12:51:40 PM PST 24 |
| Finished | Jan 21 12:51:42 PM PST 24 |
| Peak memory | 204464 kb |
| Host | smart-3bd2757e-d272-48af-9ac1-1912c27793cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1271015957 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1271015957 |
| Directory | /workspace/3.edn_regwen/latest |
| Test location | /workspace/coverage/default/3.edn_sec_cm.763461250 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 220045170 ps |
| CPU time | 3.94 seconds |
| Started | Jan 21 12:51:40 PM PST 24 |
| Finished | Jan 21 12:51:45 PM PST 24 |
| Peak memory | 232708 kb |
| Host | smart-0913a0ee-bcf7-4446-b0c7-a277c5d1c801 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763461250 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.763461250 |
| Directory | /workspace/3.edn_sec_cm/latest |
| Test location | /workspace/coverage/default/3.edn_smoke.2265370077 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 71302035 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 12:51:33 PM PST 24 |
| Finished | Jan 21 12:51:35 PM PST 24 |
| Peak memory | 204184 kb |
| Host | smart-2ad9c3f7-7d16-434c-924a-bc05ce28f6fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2265370077 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2265370077 |
| Directory | /workspace/3.edn_smoke/latest |
| Test location | /workspace/coverage/default/3.edn_stress_all.749134271 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 136169124 ps |
| CPU time | 1.85 seconds |
| Started | Jan 21 12:51:40 PM PST 24 |
| Finished | Jan 21 12:51:43 PM PST 24 |
| Peak memory | 204988 kb |
| Host | smart-bb828584-87c8-4261-a1f4-f860d4a792ae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749134271 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.749134271 |
| Directory | /workspace/3.edn_stress_all/latest |
| Test location | /workspace/coverage/default/3.edn_stress_all_with_rand_reset.4293486434 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 35092832961 ps |
| CPU time | 783.35 seconds |
| Started | Jan 21 12:51:40 PM PST 24 |
| Finished | Jan 21 01:04:44 PM PST 24 |
| Peak memory | 215404 kb |
| Host | smart-3b0b4b6f-b389-49b5-874d-4a3aa8f6d6ba |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293486434 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.4293486434 |
| Directory | /workspace/3.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.edn_alert.2103974250 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 31836525 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:55:25 PM PST 24 |
| Finished | Jan 21 12:55:27 PM PST 24 |
| Peak memory | 204808 kb |
| Host | smart-526ec711-0cd7-4b20-a6cb-d143a2730433 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2103974250 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2103974250 |
| Directory | /workspace/30.edn_alert/latest |
| Test location | /workspace/coverage/default/30.edn_alert_test.2228365141 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 42196001 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:55:26 PM PST 24 |
| Finished | Jan 21 12:55:28 PM PST 24 |
| Peak memory | 204096 kb |
| Host | smart-6cc7bfbf-0d5d-49dd-8763-cdc0b72d134a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228365141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2228365141 |
| Directory | /workspace/30.edn_alert_test/latest |
| Test location | /workspace/coverage/default/30.edn_disable.1327409385 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 23648218 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 01:27:46 PM PST 24 |
| Finished | Jan 21 01:27:49 PM PST 24 |
| Peak memory | 214044 kb |
| Host | smart-a6630fde-1c2c-46e3-97c0-61b2e7204b93 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327409385 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1327409385 |
| Directory | /workspace/30.edn_disable/latest |
| Test location | /workspace/coverage/default/30.edn_disable_auto_req_mode.3441665660 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 88157298 ps |
| CPU time | 1 seconds |
| Started | Jan 21 01:46:18 PM PST 24 |
| Finished | Jan 21 01:46:19 PM PST 24 |
| Peak memory | 214220 kb |
| Host | smart-6bd837a7-1ff2-4ee4-8ee0-681dd0797439 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441665660 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d isable_auto_req_mode.3441665660 |
| Directory | /workspace/30.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/30.edn_err.1689229000 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 49523189 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 12:55:29 PM PST 24 |
| Finished | Jan 21 12:55:30 PM PST 24 |
| Peak memory | 215832 kb |
| Host | smart-daeb6cc5-2b08-4b18-9bdf-0f1fc7309423 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1689229000 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1689229000 |
| Directory | /workspace/30.edn_err/latest |
| Test location | /workspace/coverage/default/30.edn_genbits.4157393223 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 29359357 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 02:35:43 PM PST 24 |
| Finished | Jan 21 02:35:45 PM PST 24 |
| Peak memory | 205092 kb |
| Host | smart-a4abe35b-6145-4f39-b148-92a0301b5464 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4157393223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.4157393223 |
| Directory | /workspace/30.edn_genbits/latest |
| Test location | /workspace/coverage/default/30.edn_intr.3992968999 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 29759017 ps |
| CPU time | 1 seconds |
| Started | Jan 21 12:55:26 PM PST 24 |
| Finished | Jan 21 12:55:27 PM PST 24 |
| Peak memory | 213832 kb |
| Host | smart-162cfc9b-7c7f-40ea-978d-fa05c3d4b1ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3992968999 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3992968999 |
| Directory | /workspace/30.edn_intr/latest |
| Test location | /workspace/coverage/default/30.edn_smoke.520064007 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 172592653 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:55:26 PM PST 24 |
| Finished | Jan 21 12:55:27 PM PST 24 |
| Peak memory | 204188 kb |
| Host | smart-86df0230-2572-4c2c-ba6f-1bcab6168ad7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=520064007 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.520064007 |
| Directory | /workspace/30.edn_smoke/latest |
| Test location | /workspace/coverage/default/30.edn_stress_all.3957932278 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 1552580514 ps |
| CPU time | 3.95 seconds |
| Started | Jan 21 02:06:52 PM PST 24 |
| Finished | Jan 21 02:06:59 PM PST 24 |
| Peak memory | 205888 kb |
| Host | smart-4438d080-dbe3-4dab-9004-fdcf1b98d6aa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957932278 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3957932278 |
| Directory | /workspace/30.edn_stress_all/latest |
| Test location | /workspace/coverage/default/30.edn_stress_all_with_rand_reset.1626791983 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 20308097365 ps |
| CPU time | 513.73 seconds |
| Started | Jan 21 12:55:25 PM PST 24 |
| Finished | Jan 21 01:03:59 PM PST 24 |
| Peak memory | 215900 kb |
| Host | smart-74167026-daca-4c8d-86f3-6f171560555b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626791983 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.1626791983 |
| Directory | /workspace/30.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.edn_alert.3351391454 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 66346211 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:55:38 PM PST 24 |
| Finished | Jan 21 12:55:40 PM PST 24 |
| Peak memory | 204484 kb |
| Host | smart-fd7b0cb9-78d2-4391-a1af-d8df11184b29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3351391454 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3351391454 |
| Directory | /workspace/31.edn_alert/latest |
| Test location | /workspace/coverage/default/31.edn_alert_test.648686290 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 33076293 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:55:37 PM PST 24 |
| Finished | Jan 21 12:55:39 PM PST 24 |
| Peak memory | 204696 kb |
| Host | smart-0484fc65-8bfb-45fc-b604-c6de47dcbb3c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648686290 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.648686290 |
| Directory | /workspace/31.edn_alert_test/latest |
| Test location | /workspace/coverage/default/31.edn_disable.523773126 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 33897050 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 12:55:38 PM PST 24 |
| Finished | Jan 21 12:55:40 PM PST 24 |
| Peak memory | 214024 kb |
| Host | smart-998e4ea9-fa1b-4fb4-98cd-233122789b13 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523773126 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.523773126 |
| Directory | /workspace/31.edn_disable/latest |
| Test location | /workspace/coverage/default/31.edn_disable_auto_req_mode.2053821106 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 29951564 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:55:37 PM PST 24 |
| Finished | Jan 21 12:55:39 PM PST 24 |
| Peak memory | 214088 kb |
| Host | smart-29000bfb-cc87-46b8-8df4-d913db7ca05d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053821106 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d isable_auto_req_mode.2053821106 |
| Directory | /workspace/31.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/31.edn_err.2884313960 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 22886174 ps |
| CPU time | 0.87 seconds |
| Started | Jan 21 12:55:36 PM PST 24 |
| Finished | Jan 21 12:55:38 PM PST 24 |
| Peak memory | 215092 kb |
| Host | smart-7e153afb-1f71-40f8-9fd4-487fd5a4ad0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2884313960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2884313960 |
| Directory | /workspace/31.edn_err/latest |
| Test location | /workspace/coverage/default/31.edn_genbits.941213235 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 49587850 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:55:25 PM PST 24 |
| Finished | Jan 21 12:55:27 PM PST 24 |
| Peak memory | 204336 kb |
| Host | smart-aa9c5c03-cfde-45ef-a6c0-edb164c3809e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=941213235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.941213235 |
| Directory | /workspace/31.edn_genbits/latest |
| Test location | /workspace/coverage/default/31.edn_intr.4283909544 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 25413849 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:55:34 PM PST 24 |
| Finished | Jan 21 12:55:36 PM PST 24 |
| Peak memory | 214140 kb |
| Host | smart-1859e7cc-2e23-4b01-9322-03625cb1bc41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4283909544 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.4283909544 |
| Directory | /workspace/31.edn_intr/latest |
| Test location | /workspace/coverage/default/31.edn_smoke.2666947388 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 30689293 ps |
| CPU time | 0.87 seconds |
| Started | Jan 21 12:55:27 PM PST 24 |
| Finished | Jan 21 12:55:28 PM PST 24 |
| Peak memory | 204944 kb |
| Host | smart-ee4ac320-53c3-4210-aca6-e66afa0106eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2666947388 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2666947388 |
| Directory | /workspace/31.edn_smoke/latest |
| Test location | /workspace/coverage/default/31.edn_stress_all.1230742580 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 316827517 ps |
| CPU time | 3.58 seconds |
| Started | Jan 21 01:25:59 PM PST 24 |
| Finished | Jan 21 01:26:03 PM PST 24 |
| Peak memory | 205576 kb |
| Host | smart-999ecc11-21ea-4324-a0a9-3709825e0936 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230742580 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1230742580 |
| Directory | /workspace/31.edn_stress_all/latest |
| Test location | /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2335259124 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 82640650129 ps |
| CPU time | 529.64 seconds |
| Started | Jan 21 01:13:29 PM PST 24 |
| Finished | Jan 21 01:22:20 PM PST 24 |
| Peak memory | 215376 kb |
| Host | smart-64077af8-1dee-4aa1-a92a-1e7b1b1b38eb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335259124 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2335259124 |
| Directory | /workspace/31.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.edn_alert.1695467349 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 22046616 ps |
| CPU time | 1.01 seconds |
| Started | Jan 21 12:55:38 PM PST 24 |
| Finished | Jan 21 12:55:40 PM PST 24 |
| Peak memory | 205392 kb |
| Host | smart-d570666a-1821-49c0-8545-ef7af34df3c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1695467349 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1695467349 |
| Directory | /workspace/32.edn_alert/latest |
| Test location | /workspace/coverage/default/32.edn_alert_test.2483085509 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 70733414 ps |
| CPU time | 1.73 seconds |
| Started | Jan 21 12:55:46 PM PST 24 |
| Finished | Jan 21 12:55:49 PM PST 24 |
| Peak memory | 204628 kb |
| Host | smart-3bc1724f-4384-49bb-92ea-3154a0fe405c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483085509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2483085509 |
| Directory | /workspace/32.edn_alert_test/latest |
| Test location | /workspace/coverage/default/32.edn_disable.2117059795 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 28446499 ps |
| CPU time | 0.81 seconds |
| Started | Jan 21 12:55:49 PM PST 24 |
| Finished | Jan 21 12:55:51 PM PST 24 |
| Peak memory | 213932 kb |
| Host | smart-954ae066-08ec-4d57-844a-a8b3c105644a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117059795 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2117059795 |
| Directory | /workspace/32.edn_disable/latest |
| Test location | /workspace/coverage/default/32.edn_disable_auto_req_mode.1231796418 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 102725583 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 12:55:46 PM PST 24 |
| Finished | Jan 21 12:55:48 PM PST 24 |
| Peak memory | 214088 kb |
| Host | smart-53a53a32-493a-4f9f-b79f-c3db231d076d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231796418 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d isable_auto_req_mode.1231796418 |
| Directory | /workspace/32.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/32.edn_err.718782596 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 100645247 ps |
| CPU time | 1.22 seconds |
| Started | Jan 21 12:55:48 PM PST 24 |
| Finished | Jan 21 12:55:50 PM PST 24 |
| Peak memory | 216452 kb |
| Host | smart-031c29a0-bbb5-444a-aa9a-42dbc24bf429 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=718782596 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.718782596 |
| Directory | /workspace/32.edn_err/latest |
| Test location | /workspace/coverage/default/32.edn_genbits.1019402335 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 59491580 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 12:55:37 PM PST 24 |
| Finished | Jan 21 12:55:39 PM PST 24 |
| Peak memory | 205016 kb |
| Host | smart-a70bf7a8-0065-4463-8960-da3a5a8bd17e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1019402335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1019402335 |
| Directory | /workspace/32.edn_genbits/latest |
| Test location | /workspace/coverage/default/32.edn_intr.1056560332 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 17538292 ps |
| CPU time | 1.04 seconds |
| Started | Jan 21 12:55:37 PM PST 24 |
| Finished | Jan 21 12:55:39 PM PST 24 |
| Peak memory | 214016 kb |
| Host | smart-f4f5e5e6-f414-4854-a2d9-cb3fa3766bb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1056560332 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1056560332 |
| Directory | /workspace/32.edn_intr/latest |
| Test location | /workspace/coverage/default/32.edn_smoke.75324034 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 12138553 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:55:38 PM PST 24 |
| Finished | Jan 21 12:55:40 PM PST 24 |
| Peak memory | 204808 kb |
| Host | smart-8266fb8b-b275-4047-97b1-d811afd88095 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=75324034 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.75324034 |
| Directory | /workspace/32.edn_smoke/latest |
| Test location | /workspace/coverage/default/32.edn_stress_all.227788779 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 19209311 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:55:38 PM PST 24 |
| Finished | Jan 21 12:55:41 PM PST 24 |
| Peak memory | 203892 kb |
| Host | smart-8ee3b5f7-e25e-4c68-8734-3fb744950f35 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227788779 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.227788779 |
| Directory | /workspace/32.edn_stress_all/latest |
| Test location | /workspace/coverage/default/32.edn_stress_all_with_rand_reset.231382890 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 63723781667 ps |
| CPU time | 702.77 seconds |
| Started | Jan 21 12:55:37 PM PST 24 |
| Finished | Jan 21 01:07:21 PM PST 24 |
| Peak memory | 215028 kb |
| Host | smart-b540a5d0-adc6-4de9-a028-c0c9d033733e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231382890 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.231382890 |
| Directory | /workspace/32.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.edn_alert.3189214967 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 17037708 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:55:48 PM PST 24 |
| Finished | Jan 21 12:55:50 PM PST 24 |
| Peak memory | 205480 kb |
| Host | smart-eec07096-edac-479f-b7e7-2386182f01f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3189214967 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3189214967 |
| Directory | /workspace/33.edn_alert/latest |
| Test location | /workspace/coverage/default/33.edn_alert_test.3699360451 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 22516681 ps |
| CPU time | 1 seconds |
| Started | Jan 21 12:55:46 PM PST 24 |
| Finished | Jan 21 12:55:48 PM PST 24 |
| Peak memory | 204116 kb |
| Host | smart-d62a9f27-00a4-4336-9e26-a60d130bfeb9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699360451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3699360451 |
| Directory | /workspace/33.edn_alert_test/latest |
| Test location | /workspace/coverage/default/33.edn_disable_auto_req_mode.1495015555 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 29629805 ps |
| CPU time | 0.94 seconds |
| Started | Jan 21 12:55:49 PM PST 24 |
| Finished | Jan 21 12:55:51 PM PST 24 |
| Peak memory | 214204 kb |
| Host | smart-8de8ec19-c90a-4c71-9319-61c3bab7dcef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495015555 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d isable_auto_req_mode.1495015555 |
| Directory | /workspace/33.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/33.edn_intr.444120772 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 35772043 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:55:47 PM PST 24 |
| Finished | Jan 21 12:55:49 PM PST 24 |
| Peak memory | 213620 kb |
| Host | smart-50ee9189-f8b4-4955-9415-c31752043abb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=444120772 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.444120772 |
| Directory | /workspace/33.edn_intr/latest |
| Test location | /workspace/coverage/default/33.edn_smoke.3712703486 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 15692222 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:55:44 PM PST 24 |
| Finished | Jan 21 12:55:46 PM PST 24 |
| Peak memory | 204420 kb |
| Host | smart-c9dbc0a3-010f-412e-8d4c-3e26a730952e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3712703486 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.3712703486 |
| Directory | /workspace/33.edn_smoke/latest |
| Test location | /workspace/coverage/default/33.edn_stress_all.1342532809 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 337097816 ps |
| CPU time | 2.17 seconds |
| Started | Jan 21 12:55:49 PM PST 24 |
| Finished | Jan 21 12:55:52 PM PST 24 |
| Peak memory | 205504 kb |
| Host | smart-df3aa27d-4514-4407-84c8-ba3ebff507ca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342532809 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1342532809 |
| Directory | /workspace/33.edn_stress_all/latest |
| Test location | /workspace/coverage/default/33.edn_stress_all_with_rand_reset.2020346335 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 17487315546 ps |
| CPU time | 446.62 seconds |
| Started | Jan 21 12:55:49 PM PST 24 |
| Finished | Jan 21 01:03:16 PM PST 24 |
| Peak memory | 215632 kb |
| Host | smart-e125f47a-d24a-4b23-b559-96db7a1856c2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020346335 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.2020346335 |
| Directory | /workspace/33.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.edn_alert.497354225 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 21149245 ps |
| CPU time | 1 seconds |
| Started | Jan 21 01:31:18 PM PST 24 |
| Finished | Jan 21 01:31:20 PM PST 24 |
| Peak memory | 204872 kb |
| Host | smart-bb6daf9d-ca6f-4a66-906a-c9383eec240d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=497354225 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.497354225 |
| Directory | /workspace/34.edn_alert/latest |
| Test location | /workspace/coverage/default/34.edn_alert_test.771790246 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 15674162 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:55:55 PM PST 24 |
| Finished | Jan 21 12:55:57 PM PST 24 |
| Peak memory | 204648 kb |
| Host | smart-573f842b-a312-487e-a642-9d217bb9c3f7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771790246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.771790246 |
| Directory | /workspace/34.edn_alert_test/latest |
| Test location | /workspace/coverage/default/34.edn_disable.692648473 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 12106939 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 01:21:26 PM PST 24 |
| Finished | Jan 21 01:21:27 PM PST 24 |
| Peak memory | 214172 kb |
| Host | smart-f6319d96-1c2a-46f4-8c3f-114a9259c6ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692648473 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.692648473 |
| Directory | /workspace/34.edn_disable/latest |
| Test location | /workspace/coverage/default/34.edn_err.694791231 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 18311874 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 12:55:54 PM PST 24 |
| Finished | Jan 21 12:55:56 PM PST 24 |
| Peak memory | 215308 kb |
| Host | smart-3f718c92-3a38-4060-b183-44f21b1b753a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=694791231 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.694791231 |
| Directory | /workspace/34.edn_err/latest |
| Test location | /workspace/coverage/default/34.edn_genbits.3954326939 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 116857854 ps |
| CPU time | 2.51 seconds |
| Started | Jan 21 12:55:54 PM PST 24 |
| Finished | Jan 21 12:55:58 PM PST 24 |
| Peak memory | 213804 kb |
| Host | smart-d0d56880-15c5-434f-bbfa-386f01b571aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3954326939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3954326939 |
| Directory | /workspace/34.edn_genbits/latest |
| Test location | /workspace/coverage/default/34.edn_intr.1441899160 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 79762555 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 12:55:54 PM PST 24 |
| Finished | Jan 21 12:55:56 PM PST 24 |
| Peak memory | 213908 kb |
| Host | smart-45572540-c340-4339-80b3-f04f3ec61f93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441899160 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1441899160 |
| Directory | /workspace/34.edn_intr/latest |
| Test location | /workspace/coverage/default/34.edn_smoke.613827603 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 41788901 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:55:45 PM PST 24 |
| Finished | Jan 21 12:55:47 PM PST 24 |
| Peak memory | 204176 kb |
| Host | smart-43159f3d-40ea-4d69-ad11-70c086e1c42b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=613827603 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.613827603 |
| Directory | /workspace/34.edn_smoke/latest |
| Test location | /workspace/coverage/default/34.edn_stress_all.2496733503 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 397914158 ps |
| CPU time | 2.82 seconds |
| Started | Jan 21 12:55:55 PM PST 24 |
| Finished | Jan 21 12:55:59 PM PST 24 |
| Peak memory | 205568 kb |
| Host | smart-f4bbf90b-01df-4a8c-ab1f-f037e2a74896 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496733503 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2496733503 |
| Directory | /workspace/34.edn_stress_all/latest |
| Test location | /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3790931620 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 897591587925 ps |
| CPU time | 1916.01 seconds |
| Started | Jan 21 12:55:57 PM PST 24 |
| Finished | Jan 21 01:27:54 PM PST 24 |
| Peak memory | 220688 kb |
| Host | smart-f2b88835-39aa-4d2f-8e38-455bacd9e167 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790931620 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3790931620 |
| Directory | /workspace/34.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.edn_alert.349770111 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 26436508 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 12:56:08 PM PST 24 |
| Finished | Jan 21 12:56:10 PM PST 24 |
| Peak memory | 204864 kb |
| Host | smart-a2220b70-37e2-42a4-a094-ce0efd9638c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=349770111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.349770111 |
| Directory | /workspace/35.edn_alert/latest |
| Test location | /workspace/coverage/default/35.edn_alert_test.1841514686 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 54927072 ps |
| CPU time | 0.8 seconds |
| Started | Jan 21 12:56:07 PM PST 24 |
| Finished | Jan 21 12:56:09 PM PST 24 |
| Peak memory | 204012 kb |
| Host | smart-7c7ba6af-9c8b-4161-8822-920bfd218511 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841514686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1841514686 |
| Directory | /workspace/35.edn_alert_test/latest |
| Test location | /workspace/coverage/default/35.edn_disable.233032426 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 18555788 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 12:56:09 PM PST 24 |
| Finished | Jan 21 12:56:11 PM PST 24 |
| Peak memory | 213936 kb |
| Host | smart-2662a4c1-037e-4dfd-9d0b-572ee623b549 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233032426 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.233032426 |
| Directory | /workspace/35.edn_disable/latest |
| Test location | /workspace/coverage/default/35.edn_disable_auto_req_mode.2507849887 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 30789252 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 12:56:03 PM PST 24 |
| Finished | Jan 21 12:56:05 PM PST 24 |
| Peak memory | 214064 kb |
| Host | smart-fea3182d-6bb9-4857-b0fd-aa33518517ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507849887 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d isable_auto_req_mode.2507849887 |
| Directory | /workspace/35.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/35.edn_err.135651161 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 21824051 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 12:56:04 PM PST 24 |
| Finished | Jan 21 12:56:06 PM PST 24 |
| Peak memory | 215388 kb |
| Host | smart-18093aef-f5d3-4e01-83a5-6e0643f4778e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=135651161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.135651161 |
| Directory | /workspace/35.edn_err/latest |
| Test location | /workspace/coverage/default/35.edn_genbits.1272298407 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 106082429 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:55:57 PM PST 24 |
| Finished | Jan 21 12:55:59 PM PST 24 |
| Peak memory | 204580 kb |
| Host | smart-6b8a0e8c-2a20-4556-a8ee-380145262e51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1272298407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1272298407 |
| Directory | /workspace/35.edn_genbits/latest |
| Test location | /workspace/coverage/default/35.edn_intr.883293524 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 19397795 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:56:07 PM PST 24 |
| Finished | Jan 21 12:56:09 PM PST 24 |
| Peak memory | 213860 kb |
| Host | smart-32769b9e-ffb9-4dff-a372-c41ec0a21e2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=883293524 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.883293524 |
| Directory | /workspace/35.edn_intr/latest |
| Test location | /workspace/coverage/default/35.edn_smoke.1898024620 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 186217442 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:55:57 PM PST 24 |
| Finished | Jan 21 12:55:58 PM PST 24 |
| Peak memory | 204268 kb |
| Host | smart-4bd82479-e6dc-412c-a0c3-9ba29f7422f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1898024620 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1898024620 |
| Directory | /workspace/35.edn_smoke/latest |
| Test location | /workspace/coverage/default/35.edn_stress_all.209185664 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 268821540 ps |
| CPU time | 3.46 seconds |
| Started | Jan 21 01:10:43 PM PST 24 |
| Finished | Jan 21 01:10:49 PM PST 24 |
| Peak memory | 205520 kb |
| Host | smart-2fa32e3c-74e1-4391-a92b-04f1f50110a5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209185664 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.209185664 |
| Directory | /workspace/35.edn_stress_all/latest |
| Test location | /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3384539032 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 64500656281 ps |
| CPU time | 797.18 seconds |
| Started | Jan 21 12:56:06 PM PST 24 |
| Finished | Jan 21 01:09:24 PM PST 24 |
| Peak memory | 214368 kb |
| Host | smart-983748b2-4774-4c59-bdcd-a1e028b7c7c4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384539032 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3384539032 |
| Directory | /workspace/35.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.edn_alert.848324942 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 18888543 ps |
| CPU time | 1.01 seconds |
| Started | Jan 21 12:56:12 PM PST 24 |
| Finished | Jan 21 12:56:19 PM PST 24 |
| Peak memory | 205476 kb |
| Host | smart-5775658e-e16e-4fea-bce4-288d99a4f1da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=848324942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.848324942 |
| Directory | /workspace/36.edn_alert/latest |
| Test location | /workspace/coverage/default/36.edn_alert_test.939951415 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 63360690 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:56:10 PM PST 24 |
| Finished | Jan 21 12:56:12 PM PST 24 |
| Peak memory | 204120 kb |
| Host | smart-ab4c2a41-46be-412f-945d-7d00f42639bd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939951415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.939951415 |
| Directory | /workspace/36.edn_alert_test/latest |
| Test location | /workspace/coverage/default/36.edn_disable.115810691 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 20501054 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 01:42:09 PM PST 24 |
| Finished | Jan 21 01:42:11 PM PST 24 |
| Peak memory | 214064 kb |
| Host | smart-9960d141-6b69-48af-a505-40b33f771d45 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115810691 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.115810691 |
| Directory | /workspace/36.edn_disable/latest |
| Test location | /workspace/coverage/default/36.edn_disable_auto_req_mode.1038574949 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 33137696 ps |
| CPU time | 1.12 seconds |
| Started | Jan 21 12:56:13 PM PST 24 |
| Finished | Jan 21 12:56:21 PM PST 24 |
| Peak memory | 205944 kb |
| Host | smart-febd7878-7070-4244-af76-5cc9eb9900ad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038574949 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d isable_auto_req_mode.1038574949 |
| Directory | /workspace/36.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/36.edn_err.3246313903 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 30795855 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 12:56:14 PM PST 24 |
| Finished | Jan 21 12:56:21 PM PST 24 |
| Peak memory | 215056 kb |
| Host | smart-b259c00d-97e5-432f-a69d-c0ac1ae1586c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3246313903 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.3246313903 |
| Directory | /workspace/36.edn_err/latest |
| Test location | /workspace/coverage/default/36.edn_genbits.3628978456 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 214513590 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:56:06 PM PST 24 |
| Finished | Jan 21 12:56:08 PM PST 24 |
| Peak memory | 204520 kb |
| Host | smart-f9fa843a-271e-4c7d-9b61-833dc2c2dd3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3628978456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3628978456 |
| Directory | /workspace/36.edn_genbits/latest |
| Test location | /workspace/coverage/default/36.edn_intr.1782181822 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 20931695 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:56:17 PM PST 24 |
| Finished | Jan 21 12:56:21 PM PST 24 |
| Peak memory | 213816 kb |
| Host | smart-36c3ea2d-a6ab-4b01-b110-fb7e2ecfc2b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1782181822 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1782181822 |
| Directory | /workspace/36.edn_intr/latest |
| Test location | /workspace/coverage/default/36.edn_smoke.3506222628 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 14085422 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 12:56:05 PM PST 24 |
| Finished | Jan 21 12:56:07 PM PST 24 |
| Peak memory | 204424 kb |
| Host | smart-908e37b2-e917-4826-b98d-f700098878a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3506222628 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3506222628 |
| Directory | /workspace/36.edn_smoke/latest |
| Test location | /workspace/coverage/default/36.edn_stress_all.3237866230 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 1068015581 ps |
| CPU time | 4.04 seconds |
| Started | Jan 21 12:56:06 PM PST 24 |
| Finished | Jan 21 12:56:10 PM PST 24 |
| Peak memory | 205640 kb |
| Host | smart-fa0c5691-832e-4cf1-9aa9-ce6b14a71abf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237866230 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3237866230 |
| Directory | /workspace/36.edn_stress_all/latest |
| Test location | /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3940083885 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 30902108200 ps |
| CPU time | 386.89 seconds |
| Started | Jan 21 12:56:03 PM PST 24 |
| Finished | Jan 21 01:02:31 PM PST 24 |
| Peak memory | 214844 kb |
| Host | smart-16b7d2c2-ee7c-4754-b040-381af539ef0d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940083885 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3940083885 |
| Directory | /workspace/36.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.edn_alert.1941405566 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 36541927 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 01:08:03 PM PST 24 |
| Finished | Jan 21 01:08:06 PM PST 24 |
| Peak memory | 204980 kb |
| Host | smart-36d55aeb-07e7-41c9-ac9c-3ae1bdaa792c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1941405566 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1941405566 |
| Directory | /workspace/37.edn_alert/latest |
| Test location | /workspace/coverage/default/37.edn_alert_test.2135389633 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 122103878 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 01:28:20 PM PST 24 |
| Finished | Jan 21 01:28:22 PM PST 24 |
| Peak memory | 204796 kb |
| Host | smart-f939eaf9-ecbe-438a-b66d-7de836a9c195 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135389633 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2135389633 |
| Directory | /workspace/37.edn_alert_test/latest |
| Test location | /workspace/coverage/default/37.edn_disable.1996209385 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 16174928 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 02:27:20 PM PST 24 |
| Finished | Jan 21 02:27:21 PM PST 24 |
| Peak memory | 214076 kb |
| Host | smart-b68723a0-8f10-449e-aaea-026331e45707 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996209385 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1996209385 |
| Directory | /workspace/37.edn_disable/latest |
| Test location | /workspace/coverage/default/37.edn_disable_auto_req_mode.279068645 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 85279741 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 01:13:24 PM PST 24 |
| Finished | Jan 21 01:13:26 PM PST 24 |
| Peak memory | 214220 kb |
| Host | smart-caf51c69-4149-44f5-9b15-806f6588cc19 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279068645 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di sable_auto_req_mode.279068645 |
| Directory | /workspace/37.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/37.edn_err.1777458634 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 32070859 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:56:14 PM PST 24 |
| Finished | Jan 21 12:56:21 PM PST 24 |
| Peak memory | 220592 kb |
| Host | smart-216ffa83-7591-4eab-a971-f7c31b24ba66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1777458634 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1777458634 |
| Directory | /workspace/37.edn_err/latest |
| Test location | /workspace/coverage/default/37.edn_intr.1699718912 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 19233575 ps |
| CPU time | 1.05 seconds |
| Started | Jan 21 01:19:15 PM PST 24 |
| Finished | Jan 21 01:19:22 PM PST 24 |
| Peak memory | 214128 kb |
| Host | smart-1f0ac907-ed56-41d7-b66c-e0dc9f62fda1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1699718912 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1699718912 |
| Directory | /workspace/37.edn_intr/latest |
| Test location | /workspace/coverage/default/37.edn_smoke.2183397143 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 16149679 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 12:56:13 PM PST 24 |
| Finished | Jan 21 12:56:21 PM PST 24 |
| Peak memory | 204148 kb |
| Host | smart-e48a7ebd-aa66-4dfa-ba91-7f7ce6fe902c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2183397143 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2183397143 |
| Directory | /workspace/37.edn_smoke/latest |
| Test location | /workspace/coverage/default/37.edn_stress_all.118567341 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 61084138 ps |
| CPU time | 1.81 seconds |
| Started | Jan 21 12:56:16 PM PST 24 |
| Finished | Jan 21 12:56:21 PM PST 24 |
| Peak memory | 205484 kb |
| Host | smart-4309aa45-e81f-451e-9018-a472fd54d958 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118567341 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.118567341 |
| Directory | /workspace/37.edn_stress_all/latest |
| Test location | /workspace/coverage/default/37.edn_stress_all_with_rand_reset.577665649 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 29417707009 ps |
| CPU time | 386.54 seconds |
| Started | Jan 21 12:56:12 PM PST 24 |
| Finished | Jan 21 01:02:39 PM PST 24 |
| Peak memory | 215248 kb |
| Host | smart-c20cc06b-850b-4c92-9309-a0de0ec73e57 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577665649 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.577665649 |
| Directory | /workspace/37.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.edn_alert.2199532675 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 55758183 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:56:26 PM PST 24 |
| Finished | Jan 21 12:56:28 PM PST 24 |
| Peak memory | 205380 kb |
| Host | smart-a486f3fe-1e8d-4a46-852e-73c1df92cd09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2199532675 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2199532675 |
| Directory | /workspace/38.edn_alert/latest |
| Test location | /workspace/coverage/default/38.edn_alert_test.681597521 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 57229830 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:56:27 PM PST 24 |
| Finished | Jan 21 12:56:34 PM PST 24 |
| Peak memory | 204152 kb |
| Host | smart-11b4fa08-7ecf-4d72-8c7b-c6f2955c7e73 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681597521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.681597521 |
| Directory | /workspace/38.edn_alert_test/latest |
| Test location | /workspace/coverage/default/38.edn_disable.3866721683 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 10952802 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:57:46 PM PST 24 |
| Finished | Jan 21 12:57:49 PM PST 24 |
| Peak memory | 212840 kb |
| Host | smart-26cf214f-1cfc-4a38-98d1-ca9c98b65f64 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866721683 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3866721683 |
| Directory | /workspace/38.edn_disable/latest |
| Test location | /workspace/coverage/default/38.edn_disable_auto_req_mode.1351315038 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 54034244 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 01:09:35 PM PST 24 |
| Finished | Jan 21 01:09:37 PM PST 24 |
| Peak memory | 216184 kb |
| Host | smart-7166304f-846c-4774-93f5-f4e6bdb96290 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351315038 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d isable_auto_req_mode.1351315038 |
| Directory | /workspace/38.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/38.edn_err.1712958001 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 47098904 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 12:56:27 PM PST 24 |
| Finished | Jan 21 12:56:34 PM PST 24 |
| Peak memory | 215300 kb |
| Host | smart-c4b1436b-c562-454e-b59a-76ede60b0b08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1712958001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1712958001 |
| Directory | /workspace/38.edn_err/latest |
| Test location | /workspace/coverage/default/38.edn_genbits.1847096420 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 24351760 ps |
| CPU time | 1.19 seconds |
| Started | Jan 21 12:56:19 PM PST 24 |
| Finished | Jan 21 12:56:24 PM PST 24 |
| Peak memory | 204736 kb |
| Host | smart-29cd2fbe-ec66-4c1e-b7af-17dfc206b491 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1847096420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1847096420 |
| Directory | /workspace/38.edn_genbits/latest |
| Test location | /workspace/coverage/default/38.edn_intr.3188388894 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 26286877 ps |
| CPU time | 1.05 seconds |
| Started | Jan 21 01:11:11 PM PST 24 |
| Finished | Jan 21 01:11:15 PM PST 24 |
| Peak memory | 220964 kb |
| Host | smart-8601369d-62af-4add-a044-4628c1381887 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3188388894 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.3188388894 |
| Directory | /workspace/38.edn_intr/latest |
| Test location | /workspace/coverage/default/38.edn_smoke.2015466965 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 23796270 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 12:56:20 PM PST 24 |
| Finished | Jan 21 12:56:24 PM PST 24 |
| Peak memory | 204448 kb |
| Host | smart-80e65acb-cdce-4ec9-9927-a7c34f2d2d85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2015466965 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.2015466965 |
| Directory | /workspace/38.edn_smoke/latest |
| Test location | /workspace/coverage/default/38.edn_stress_all.176031871 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1260792183 ps |
| CPU time | 4.35 seconds |
| Started | Jan 21 12:56:20 PM PST 24 |
| Finished | Jan 21 12:56:28 PM PST 24 |
| Peak memory | 205596 kb |
| Host | smart-e2c8e205-6ed4-449d-8cf7-43e1db3bc621 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176031871 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.176031871 |
| Directory | /workspace/38.edn_stress_all/latest |
| Test location | /workspace/coverage/default/38.edn_stress_all_with_rand_reset.4070749331 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 61833380045 ps |
| CPU time | 455.12 seconds |
| Started | Jan 21 12:56:33 PM PST 24 |
| Finished | Jan 21 01:04:10 PM PST 24 |
| Peak memory | 214792 kb |
| Host | smart-d92cbb1f-3ee5-47fe-9bea-43cd72ddd3df |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070749331 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.4070749331 |
| Directory | /workspace/38.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.edn_alert.3296839075 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 33750010 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:56:39 PM PST 24 |
| Finished | Jan 21 12:56:41 PM PST 24 |
| Peak memory | 205476 kb |
| Host | smart-a7ace897-8cae-42a6-8b0b-73dac581f967 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3296839075 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3296839075 |
| Directory | /workspace/39.edn_alert/latest |
| Test location | /workspace/coverage/default/39.edn_alert_test.20315171 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 15114691 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:56:41 PM PST 24 |
| Finished | Jan 21 12:56:43 PM PST 24 |
| Peak memory | 204116 kb |
| Host | smart-b6c86ad4-9a98-46f5-8840-4dd6ff877dad |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20315171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.20315171 |
| Directory | /workspace/39.edn_alert_test/latest |
| Test location | /workspace/coverage/default/39.edn_disable.1221423024 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 16085778 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 12:56:39 PM PST 24 |
| Finished | Jan 21 12:56:41 PM PST 24 |
| Peak memory | 213908 kb |
| Host | smart-6b6614d6-7dc4-4c47-a123-06518f41625a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221423024 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1221423024 |
| Directory | /workspace/39.edn_disable/latest |
| Test location | /workspace/coverage/default/39.edn_disable_auto_req_mode.40044124 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 92756205 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:56:39 PM PST 24 |
| Finished | Jan 21 12:56:41 PM PST 24 |
| Peak memory | 214076 kb |
| Host | smart-77114cf8-9aa6-4fe3-9d4b-5cc1dfc7416a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40044124 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_dis able_auto_req_mode.40044124 |
| Directory | /workspace/39.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/39.edn_err.1766921184 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 21426547 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:56:40 PM PST 24 |
| Finished | Jan 21 12:56:42 PM PST 24 |
| Peak memory | 215228 kb |
| Host | smart-df7c0702-40c8-40aa-a895-dfafac5a401e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1766921184 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1766921184 |
| Directory | /workspace/39.edn_err/latest |
| Test location | /workspace/coverage/default/39.edn_intr.3244424874 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 35114273 ps |
| CPU time | 1.23 seconds |
| Started | Jan 21 12:56:33 PM PST 24 |
| Finished | Jan 21 12:56:36 PM PST 24 |
| Peak memory | 214352 kb |
| Host | smart-c520c809-826a-4d8d-8b4c-e60745a4cb0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244424874 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3244424874 |
| Directory | /workspace/39.edn_intr/latest |
| Test location | /workspace/coverage/default/39.edn_smoke.3421983606 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 47425554 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 01:22:18 PM PST 24 |
| Finished | Jan 21 01:22:24 PM PST 24 |
| Peak memory | 204536 kb |
| Host | smart-e460e314-e53b-4b71-8065-8096185580fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3421983606 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3421983606 |
| Directory | /workspace/39.edn_smoke/latest |
| Test location | /workspace/coverage/default/39.edn_stress_all.1038817653 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 369939589 ps |
| CPU time | 3.19 seconds |
| Started | Jan 21 12:57:46 PM PST 24 |
| Finished | Jan 21 12:57:51 PM PST 24 |
| Peak memory | 204116 kb |
| Host | smart-4389a5bc-4122-47b5-bbd6-fa29fc766198 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038817653 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.1038817653 |
| Directory | /workspace/39.edn_stress_all/latest |
| Test location | /workspace/coverage/default/39.edn_stress_all_with_rand_reset.848071984 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 1261018286031 ps |
| CPU time | 2606.11 seconds |
| Started | Jan 21 12:56:29 PM PST 24 |
| Finished | Jan 21 01:40:01 PM PST 24 |
| Peak memory | 221676 kb |
| Host | smart-aee6da46-ee00-4c6b-bd3a-3e8041f281b4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848071984 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.848071984 |
| Directory | /workspace/39.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/4.edn_alert.1458222190 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 21068717 ps |
| CPU time | 1.01 seconds |
| Started | Jan 21 12:51:50 PM PST 24 |
| Finished | Jan 21 12:51:55 PM PST 24 |
| Peak memory | 205468 kb |
| Host | smart-73b87be1-ac05-4b29-a303-1e9f9fa9b4d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1458222190 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1458222190 |
| Directory | /workspace/4.edn_alert/latest |
| Test location | /workspace/coverage/default/4.edn_alert_test.1127785833 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 162730216 ps |
| CPU time | 0.81 seconds |
| Started | Jan 21 12:51:52 PM PST 24 |
| Finished | Jan 21 12:51:56 PM PST 24 |
| Peak memory | 204780 kb |
| Host | smart-a2a9bbce-af90-48d3-8847-f8b5f57fe1a7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127785833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1127785833 |
| Directory | /workspace/4.edn_alert_test/latest |
| Test location | /workspace/coverage/default/4.edn_disable.2003732894 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 11610198 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:51:53 PM PST 24 |
| Finished | Jan 21 12:51:56 PM PST 24 |
| Peak memory | 213988 kb |
| Host | smart-898c1a54-b81c-4195-946e-b523f8ad3f11 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003732894 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2003732894 |
| Directory | /workspace/4.edn_disable/latest |
| Test location | /workspace/coverage/default/4.edn_disable_auto_req_mode.2738710548 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 77315939 ps |
| CPU time | 1.04 seconds |
| Started | Jan 21 12:51:50 PM PST 24 |
| Finished | Jan 21 12:51:55 PM PST 24 |
| Peak memory | 214136 kb |
| Host | smart-2c801215-e283-4cd3-9127-7c087829cf17 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738710548 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di sable_auto_req_mode.2738710548 |
| Directory | /workspace/4.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/4.edn_err.3004880321 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 20087412 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:51:50 PM PST 24 |
| Finished | Jan 21 12:51:54 PM PST 24 |
| Peak memory | 215412 kb |
| Host | smart-3e4bd294-64ef-41c3-94bf-04fa3df9aa34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3004880321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3004880321 |
| Directory | /workspace/4.edn_err/latest |
| Test location | /workspace/coverage/default/4.edn_genbits.1745322434 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 28757171 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 12:51:49 PM PST 24 |
| Finished | Jan 21 12:51:54 PM PST 24 |
| Peak memory | 204624 kb |
| Host | smart-a3f0e9a6-8016-47e4-9a03-6bd17f8231e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1745322434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1745322434 |
| Directory | /workspace/4.edn_genbits/latest |
| Test location | /workspace/coverage/default/4.edn_intr.3918254411 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 31828003 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:51:52 PM PST 24 |
| Finished | Jan 21 12:51:56 PM PST 24 |
| Peak memory | 221448 kb |
| Host | smart-adab347e-c22c-455d-8cd9-7163bc3df71a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3918254411 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3918254411 |
| Directory | /workspace/4.edn_intr/latest |
| Test location | /workspace/coverage/default/4.edn_regwen.2379088645 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 12462506 ps |
| CPU time | 0.87 seconds |
| Started | Jan 21 12:51:40 PM PST 24 |
| Finished | Jan 21 12:51:42 PM PST 24 |
| Peak memory | 204408 kb |
| Host | smart-de03b954-0b3f-48b2-b6eb-97d9ed108b3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2379088645 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2379088645 |
| Directory | /workspace/4.edn_regwen/latest |
| Test location | /workspace/coverage/default/4.edn_sec_cm.2326232144 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 468530555 ps |
| CPU time | 6.87 seconds |
| Started | Jan 21 12:51:51 PM PST 24 |
| Finished | Jan 21 12:52:01 PM PST 24 |
| Peak memory | 231516 kb |
| Host | smart-c95022b3-9aa3-4a8c-a19b-e117700c2aaa |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326232144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2326232144 |
| Directory | /workspace/4.edn_sec_cm/latest |
| Test location | /workspace/coverage/default/4.edn_smoke.1006001887 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 24294200 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 12:51:45 PM PST 24 |
| Finished | Jan 21 12:51:47 PM PST 24 |
| Peak memory | 204612 kb |
| Host | smart-4fc5c0ed-7e58-4612-a6c6-dc02261944ae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1006001887 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1006001887 |
| Directory | /workspace/4.edn_smoke/latest |
| Test location | /workspace/coverage/default/4.edn_stress_all.1365097551 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 84759806 ps |
| CPU time | 2.36 seconds |
| Started | Jan 21 12:51:51 PM PST 24 |
| Finished | Jan 21 12:51:56 PM PST 24 |
| Peak memory | 205224 kb |
| Host | smart-cf54363c-33b4-483f-be95-377a2ee6b6e5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365097551 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1365097551 |
| Directory | /workspace/4.edn_stress_all/latest |
| Test location | /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1551669130 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 313442404124 ps |
| CPU time | 1801.04 seconds |
| Started | Jan 21 12:51:49 PM PST 24 |
| Finished | Jan 21 01:21:54 PM PST 24 |
| Peak memory | 221856 kb |
| Host | smart-9518bd0e-d8d7-4600-83c3-6291a7b520af |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551669130 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1551669130 |
| Directory | /workspace/4.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.edn_alert.4044776783 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 17385809 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:56:41 PM PST 24 |
| Finished | Jan 21 12:56:43 PM PST 24 |
| Peak memory | 204664 kb |
| Host | smart-6bd84467-b708-4511-8ef1-589d3ac32926 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4044776783 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.4044776783 |
| Directory | /workspace/40.edn_alert/latest |
| Test location | /workspace/coverage/default/40.edn_alert_test.748298984 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 158436110 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:56:38 PM PST 24 |
| Finished | Jan 21 12:56:40 PM PST 24 |
| Peak memory | 204412 kb |
| Host | smart-f1950229-40d2-4dc4-80b4-be15df083ae7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748298984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.748298984 |
| Directory | /workspace/40.edn_alert_test/latest |
| Test location | /workspace/coverage/default/40.edn_disable.1186680980 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 29210740 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:56:42 PM PST 24 |
| Finished | Jan 21 12:56:44 PM PST 24 |
| Peak memory | 213956 kb |
| Host | smart-a3edf0a5-b2a3-43e3-afd5-8961985bd22b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186680980 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1186680980 |
| Directory | /workspace/40.edn_disable/latest |
| Test location | /workspace/coverage/default/40.edn_disable_auto_req_mode.1862616266 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 23576960 ps |
| CPU time | 1.01 seconds |
| Started | Jan 21 12:56:38 PM PST 24 |
| Finished | Jan 21 12:56:40 PM PST 24 |
| Peak memory | 214212 kb |
| Host | smart-7dadae43-0d17-419c-86c8-edc5fd3c8e02 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862616266 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d isable_auto_req_mode.1862616266 |
| Directory | /workspace/40.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/40.edn_err.2642438071 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 18126822 ps |
| CPU time | 1.12 seconds |
| Started | Jan 21 12:56:40 PM PST 24 |
| Finished | Jan 21 12:56:42 PM PST 24 |
| Peak memory | 221344 kb |
| Host | smart-46cdee0a-63f4-4410-b6c0-b4a98deb8643 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2642438071 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2642438071 |
| Directory | /workspace/40.edn_err/latest |
| Test location | /workspace/coverage/default/40.edn_genbits.1992548476 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 17212905 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 12:56:40 PM PST 24 |
| Finished | Jan 21 12:56:42 PM PST 24 |
| Peak memory | 204664 kb |
| Host | smart-4c4ddb75-40ef-40be-b8cf-4855dba0aa12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1992548476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1992548476 |
| Directory | /workspace/40.edn_genbits/latest |
| Test location | /workspace/coverage/default/40.edn_intr.1830947811 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 28979453 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:56:36 PM PST 24 |
| Finished | Jan 21 12:56:40 PM PST 24 |
| Peak memory | 213848 kb |
| Host | smart-e71d11c9-249e-44eb-916e-28e84038aaed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1830947811 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1830947811 |
| Directory | /workspace/40.edn_intr/latest |
| Test location | /workspace/coverage/default/40.edn_smoke.1590729080 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 23358766 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:56:39 PM PST 24 |
| Finished | Jan 21 12:56:41 PM PST 24 |
| Peak memory | 204288 kb |
| Host | smart-eba63ef2-f6ee-4a38-94cd-ebbcf884fc93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1590729080 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1590729080 |
| Directory | /workspace/40.edn_smoke/latest |
| Test location | /workspace/coverage/default/40.edn_stress_all.831421330 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 202342359 ps |
| CPU time | 4.09 seconds |
| Started | Jan 21 12:56:37 PM PST 24 |
| Finished | Jan 21 12:56:43 PM PST 24 |
| Peak memory | 205232 kb |
| Host | smart-18709c47-6f55-4a84-b314-96fa1738a627 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831421330 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.831421330 |
| Directory | /workspace/40.edn_stress_all/latest |
| Test location | /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2518380140 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 103997534700 ps |
| CPU time | 585.65 seconds |
| Started | Jan 21 12:56:41 PM PST 24 |
| Finished | Jan 21 01:06:28 PM PST 24 |
| Peak memory | 213972 kb |
| Host | smart-b3c8f3f1-94c7-4435-a7ca-1e7510530bdd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518380140 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2518380140 |
| Directory | /workspace/40.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.edn_alert.2442886083 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 20572050 ps |
| CPU time | 1.04 seconds |
| Started | Jan 21 12:56:47 PM PST 24 |
| Finished | Jan 21 12:56:50 PM PST 24 |
| Peak memory | 205536 kb |
| Host | smart-ec3a03be-bfe9-4dc7-ac6f-cd8287337ed3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2442886083 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2442886083 |
| Directory | /workspace/41.edn_alert/latest |
| Test location | /workspace/coverage/default/41.edn_alert_test.1759378182 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 16454265 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 12:56:46 PM PST 24 |
| Finished | Jan 21 12:56:48 PM PST 24 |
| Peak memory | 204680 kb |
| Host | smart-948e5f8e-e079-4897-8b05-0c7f4e19d4dd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759378182 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1759378182 |
| Directory | /workspace/41.edn_alert_test/latest |
| Test location | /workspace/coverage/default/41.edn_disable.3729201134 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 11854371 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:56:46 PM PST 24 |
| Finished | Jan 21 12:56:48 PM PST 24 |
| Peak memory | 213816 kb |
| Host | smart-92102afe-b61b-42fe-a00c-4f7499e5953e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729201134 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3729201134 |
| Directory | /workspace/41.edn_disable/latest |
| Test location | /workspace/coverage/default/41.edn_disable_auto_req_mode.1204760341 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 39787502 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:56:46 PM PST 24 |
| Finished | Jan 21 12:56:48 PM PST 24 |
| Peak memory | 205988 kb |
| Host | smart-c5209f56-87b6-4a32-ba07-36407ee6c0c3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204760341 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d isable_auto_req_mode.1204760341 |
| Directory | /workspace/41.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/41.edn_err.1673566855 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 57931070 ps |
| CPU time | 1.11 seconds |
| Started | Jan 21 12:56:47 PM PST 24 |
| Finished | Jan 21 12:56:49 PM PST 24 |
| Peak memory | 221380 kb |
| Host | smart-a7960c6f-0f09-40b9-8352-2cc6091cf7c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1673566855 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.1673566855 |
| Directory | /workspace/41.edn_err/latest |
| Test location | /workspace/coverage/default/41.edn_genbits.3414466484 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 17013998 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:56:46 PM PST 24 |
| Finished | Jan 21 12:56:48 PM PST 24 |
| Peak memory | 204704 kb |
| Host | smart-91c82cbc-f3c2-43d6-bfb5-dba92887af0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3414466484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3414466484 |
| Directory | /workspace/41.edn_genbits/latest |
| Test location | /workspace/coverage/default/41.edn_intr.2656144591 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 21002810 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 12:56:44 PM PST 24 |
| Finished | Jan 21 12:56:46 PM PST 24 |
| Peak memory | 214064 kb |
| Host | smart-9202f47f-897a-4668-a6fc-9e598c048940 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2656144591 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2656144591 |
| Directory | /workspace/41.edn_intr/latest |
| Test location | /workspace/coverage/default/41.edn_smoke.2400225615 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 31386818 ps |
| CPU time | 0.77 seconds |
| Started | Jan 21 12:56:47 PM PST 24 |
| Finished | Jan 21 12:56:48 PM PST 24 |
| Peak memory | 204144 kb |
| Host | smart-eab60209-a843-4ac6-b337-75964fb424e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2400225615 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2400225615 |
| Directory | /workspace/41.edn_smoke/latest |
| Test location | /workspace/coverage/default/41.edn_stress_all.1484418513 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 131808592 ps |
| CPU time | 1.33 seconds |
| Started | Jan 21 12:56:48 PM PST 24 |
| Finished | Jan 21 12:56:52 PM PST 24 |
| Peak memory | 205304 kb |
| Host | smart-4e110a55-d259-4697-a60f-594d7d42d277 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484418513 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1484418513 |
| Directory | /workspace/41.edn_stress_all/latest |
| Test location | /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1846262852 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 24658072888 ps |
| CPU time | 288.8 seconds |
| Started | Jan 21 12:56:48 PM PST 24 |
| Finished | Jan 21 01:01:40 PM PST 24 |
| Peak memory | 214480 kb |
| Host | smart-3bd8d873-ba19-477f-854d-3504a1ee4c66 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846262852 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1846262852 |
| Directory | /workspace/41.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.edn_alert.1650208096 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 73739580 ps |
| CPU time | 1.01 seconds |
| Started | Jan 21 12:57:07 PM PST 24 |
| Finished | Jan 21 12:57:09 PM PST 24 |
| Peak memory | 205324 kb |
| Host | smart-627cbba4-5fdd-44fa-860e-ca34d7cc7358 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1650208096 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1650208096 |
| Directory | /workspace/42.edn_alert/latest |
| Test location | /workspace/coverage/default/42.edn_alert_test.1648096923 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 85317687 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 12:57:07 PM PST 24 |
| Finished | Jan 21 12:57:09 PM PST 24 |
| Peak memory | 203812 kb |
| Host | smart-978e94b9-37c3-4f05-8b78-1729bc69fce0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648096923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1648096923 |
| Directory | /workspace/42.edn_alert_test/latest |
| Test location | /workspace/coverage/default/42.edn_disable.1923229175 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 14690761 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:56:57 PM PST 24 |
| Finished | Jan 21 12:57:00 PM PST 24 |
| Peak memory | 214104 kb |
| Host | smart-9a92998b-bb86-4879-8bef-b8fbe8d95419 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923229175 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1923229175 |
| Directory | /workspace/42.edn_disable/latest |
| Test location | /workspace/coverage/default/42.edn_disable_auto_req_mode.3173329244 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 59228384 ps |
| CPU time | 1.11 seconds |
| Started | Jan 21 12:56:56 PM PST 24 |
| Finished | Jan 21 12:57:00 PM PST 24 |
| Peak memory | 214108 kb |
| Host | smart-f60ea881-8ff1-4400-8180-5d81ff074653 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173329244 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d isable_auto_req_mode.3173329244 |
| Directory | /workspace/42.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/42.edn_err.2471594540 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 24371698 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 12:56:56 PM PST 24 |
| Finished | Jan 21 12:57:00 PM PST 24 |
| Peak memory | 213668 kb |
| Host | smart-2547c893-8b78-40d6-8901-643ece8a0b10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2471594540 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2471594540 |
| Directory | /workspace/42.edn_err/latest |
| Test location | /workspace/coverage/default/42.edn_genbits.4195370761 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 51461207 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:56:49 PM PST 24 |
| Finished | Jan 21 12:56:53 PM PST 24 |
| Peak memory | 204684 kb |
| Host | smart-d3a2778e-5196-4efe-a610-4e7548481445 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4195370761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.4195370761 |
| Directory | /workspace/42.edn_genbits/latest |
| Test location | /workspace/coverage/default/42.edn_intr.4111696077 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 22375571 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:56:54 PM PST 24 |
| Finished | Jan 21 12:57:00 PM PST 24 |
| Peak memory | 220760 kb |
| Host | smart-18b121a7-8158-47f0-867a-e8c8e864a7ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4111696077 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.4111696077 |
| Directory | /workspace/42.edn_intr/latest |
| Test location | /workspace/coverage/default/42.edn_smoke.707934039 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 26078489 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:56:47 PM PST 24 |
| Finished | Jan 21 12:56:50 PM PST 24 |
| Peak memory | 204292 kb |
| Host | smart-4989b4c9-dbe1-428a-b48a-670e97d11e15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=707934039 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.707934039 |
| Directory | /workspace/42.edn_smoke/latest |
| Test location | /workspace/coverage/default/42.edn_stress_all.3491654432 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 81343429 ps |
| CPU time | 1.33 seconds |
| Started | Jan 21 12:56:46 PM PST 24 |
| Finished | Jan 21 12:56:48 PM PST 24 |
| Peak memory | 205264 kb |
| Host | smart-580c64d1-21e0-41c1-81ca-86d8d47ff552 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491654432 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3491654432 |
| Directory | /workspace/42.edn_stress_all/latest |
| Test location | /workspace/coverage/default/42.edn_stress_all_with_rand_reset.545199263 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 7983380454 ps |
| CPU time | 204.85 seconds |
| Started | Jan 21 02:20:49 PM PST 24 |
| Finished | Jan 21 02:24:15 PM PST 24 |
| Peak memory | 215048 kb |
| Host | smart-56800873-eadb-4059-b723-bb706bc4aa63 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545199263 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.545199263 |
| Directory | /workspace/42.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.edn_alert.1957414247 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 72844821 ps |
| CPU time | 1 seconds |
| Started | Jan 21 12:56:58 PM PST 24 |
| Finished | Jan 21 12:57:05 PM PST 24 |
| Peak memory | 204592 kb |
| Host | smart-a4475b08-3cf0-4da9-a7d7-9b17e9ca2ba2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1957414247 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1957414247 |
| Directory | /workspace/43.edn_alert/latest |
| Test location | /workspace/coverage/default/43.edn_alert_test.2156444729 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 16490712 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:57:06 PM PST 24 |
| Finished | Jan 21 12:57:08 PM PST 24 |
| Peak memory | 203940 kb |
| Host | smart-cada2afc-95dc-4588-8a36-3ac728eb6012 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156444729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.2156444729 |
| Directory | /workspace/43.edn_alert_test/latest |
| Test location | /workspace/coverage/default/43.edn_disable.1017649756 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 13858061 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:57:06 PM PST 24 |
| Finished | Jan 21 12:57:08 PM PST 24 |
| Peak memory | 213916 kb |
| Host | smart-a2111252-6d96-4866-a9f7-e29475163986 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017649756 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1017649756 |
| Directory | /workspace/43.edn_disable/latest |
| Test location | /workspace/coverage/default/43.edn_disable_auto_req_mode.3782873204 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 119675988 ps |
| CPU time | 1.15 seconds |
| Started | Jan 21 02:12:57 PM PST 24 |
| Finished | Jan 21 02:12:59 PM PST 24 |
| Peak memory | 214212 kb |
| Host | smart-66b49a76-4d8d-4efe-8d1b-92e6344e62fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782873204 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d isable_auto_req_mode.3782873204 |
| Directory | /workspace/43.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/43.edn_err.444509073 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 33168992 ps |
| CPU time | 0.85 seconds |
| Started | Jan 21 12:57:08 PM PST 24 |
| Finished | Jan 21 12:57:09 PM PST 24 |
| Peak memory | 214964 kb |
| Host | smart-94494dc1-e197-40ae-b449-bf8078747c50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=444509073 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.444509073 |
| Directory | /workspace/43.edn_err/latest |
| Test location | /workspace/coverage/default/43.edn_genbits.3882146168 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 108690105 ps |
| CPU time | 1.79 seconds |
| Started | Jan 21 12:57:00 PM PST 24 |
| Finished | Jan 21 12:57:06 PM PST 24 |
| Peak memory | 214092 kb |
| Host | smart-cac3bea0-0f8e-41e4-b83d-f77328e30321 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3882146168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3882146168 |
| Directory | /workspace/43.edn_genbits/latest |
| Test location | /workspace/coverage/default/43.edn_smoke.2881562661 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 28971475 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:56:56 PM PST 24 |
| Finished | Jan 21 12:57:00 PM PST 24 |
| Peak memory | 204468 kb |
| Host | smart-c36fc67f-a848-436b-a35a-2fcac531d133 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2881562661 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2881562661 |
| Directory | /workspace/43.edn_smoke/latest |
| Test location | /workspace/coverage/default/43.edn_stress_all.4199075746 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 1228593648 ps |
| CPU time | 2.91 seconds |
| Started | Jan 21 12:57:07 PM PST 24 |
| Finished | Jan 21 12:57:11 PM PST 24 |
| Peak memory | 205380 kb |
| Host | smart-231ace54-ea51-4ee8-b211-86406977d292 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199075746 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.4199075746 |
| Directory | /workspace/43.edn_stress_all/latest |
| Test location | /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1671827011 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 28279144955 ps |
| CPU time | 371.92 seconds |
| Started | Jan 21 12:57:08 PM PST 24 |
| Finished | Jan 21 01:03:20 PM PST 24 |
| Peak memory | 214840 kb |
| Host | smart-e1c44e35-979c-440e-be15-cb5d7498c7ca |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671827011 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1671827011 |
| Directory | /workspace/43.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.edn_alert.2039683220 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 31284165 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:57:11 PM PST 24 |
| Finished | Jan 21 12:57:13 PM PST 24 |
| Peak memory | 204764 kb |
| Host | smart-f0b10fbd-e7bc-44a8-8333-7f32646e6416 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2039683220 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2039683220 |
| Directory | /workspace/44.edn_alert/latest |
| Test location | /workspace/coverage/default/44.edn_alert_test.1568461172 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 59917871 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:57:14 PM PST 24 |
| Finished | Jan 21 12:57:16 PM PST 24 |
| Peak memory | 204140 kb |
| Host | smart-2ed12139-8c17-438a-bf8f-1493bd383b84 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568461172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1568461172 |
| Directory | /workspace/44.edn_alert_test/latest |
| Test location | /workspace/coverage/default/44.edn_disable.1662965928 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 11090253 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 12:57:12 PM PST 24 |
| Finished | Jan 21 12:57:14 PM PST 24 |
| Peak memory | 214004 kb |
| Host | smart-b53aadcc-8243-43ba-be69-9e607c67ee1a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662965928 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1662965928 |
| Directory | /workspace/44.edn_disable/latest |
| Test location | /workspace/coverage/default/44.edn_disable_auto_req_mode.775931045 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 26951903 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 12:57:14 PM PST 24 |
| Finished | Jan 21 12:57:16 PM PST 24 |
| Peak memory | 214196 kb |
| Host | smart-b3f363bc-ce0d-47e6-94ce-49426ed99da2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775931045 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di sable_auto_req_mode.775931045 |
| Directory | /workspace/44.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/44.edn_err.3741638415 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 22928657 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:57:12 PM PST 24 |
| Finished | Jan 21 12:57:14 PM PST 24 |
| Peak memory | 215388 kb |
| Host | smart-7eb9b5f6-7e07-4b57-81b4-4d58b218c98a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3741638415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.3741638415 |
| Directory | /workspace/44.edn_err/latest |
| Test location | /workspace/coverage/default/44.edn_genbits.3172589914 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 4456101270 ps |
| CPU time | 75.72 seconds |
| Started | Jan 21 12:57:02 PM PST 24 |
| Finished | Jan 21 12:58:21 PM PST 24 |
| Peak memory | 213864 kb |
| Host | smart-5f584d8e-d10e-4c40-b63f-931324793dd4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172589914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3172589914 |
| Directory | /workspace/44.edn_genbits/latest |
| Test location | /workspace/coverage/default/44.edn_intr.1536245995 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 25097716 ps |
| CPU time | 1 seconds |
| Started | Jan 21 12:57:12 PM PST 24 |
| Finished | Jan 21 12:57:13 PM PST 24 |
| Peak memory | 221008 kb |
| Host | smart-101636c4-25af-42de-bc63-0214d0e82ead |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1536245995 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1536245995 |
| Directory | /workspace/44.edn_intr/latest |
| Test location | /workspace/coverage/default/44.edn_smoke.911080247 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 27523200 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:57:00 PM PST 24 |
| Finished | Jan 21 12:57:06 PM PST 24 |
| Peak memory | 204592 kb |
| Host | smart-1bffeb7a-21a3-4d26-8b9b-f3b2c1432572 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=911080247 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.911080247 |
| Directory | /workspace/44.edn_smoke/latest |
| Test location | /workspace/coverage/default/44.edn_stress_all.1635757891 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 343251591 ps |
| CPU time | 2.32 seconds |
| Started | Jan 21 12:57:12 PM PST 24 |
| Finished | Jan 21 12:57:15 PM PST 24 |
| Peak memory | 205192 kb |
| Host | smart-cb48c9eb-cada-404b-a17f-2f5349dfbd44 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635757891 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1635757891 |
| Directory | /workspace/44.edn_stress_all/latest |
| Test location | /workspace/coverage/default/44.edn_stress_all_with_rand_reset.951429063 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 14800641643 ps |
| CPU time | 331.64 seconds |
| Started | Jan 21 12:57:11 PM PST 24 |
| Finished | Jan 21 01:02:44 PM PST 24 |
| Peak memory | 215544 kb |
| Host | smart-ffbce55d-0a26-41b1-b96d-5e6b5393d878 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951429063 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.951429063 |
| Directory | /workspace/44.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.edn_alert.1186951749 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 26457792 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:57:19 PM PST 24 |
| Finished | Jan 21 12:57:20 PM PST 24 |
| Peak memory | 205384 kb |
| Host | smart-c27c3b5c-b780-4b4d-afa4-47882f29e543 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1186951749 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1186951749 |
| Directory | /workspace/45.edn_alert/latest |
| Test location | /workspace/coverage/default/45.edn_alert_test.3775869904 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 20240633 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:57:20 PM PST 24 |
| Finished | Jan 21 12:57:23 PM PST 24 |
| Peak memory | 205328 kb |
| Host | smart-d87ca744-4397-4540-9837-ef5f08cd94ff |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775869904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3775869904 |
| Directory | /workspace/45.edn_alert_test/latest |
| Test location | /workspace/coverage/default/45.edn_disable.2242390563 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 15454440 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 12:57:20 PM PST 24 |
| Finished | Jan 21 12:57:23 PM PST 24 |
| Peak memory | 213932 kb |
| Host | smart-2c0647bd-f715-4d56-b230-f5859944f19c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242390563 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2242390563 |
| Directory | /workspace/45.edn_disable/latest |
| Test location | /workspace/coverage/default/45.edn_disable_auto_req_mode.1794099729 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 88815022 ps |
| CPU time | 1.03 seconds |
| Started | Jan 21 12:57:20 PM PST 24 |
| Finished | Jan 21 12:57:23 PM PST 24 |
| Peak memory | 214148 kb |
| Host | smart-8ec8c325-9958-4dd7-baea-9ea0a4468813 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794099729 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d isable_auto_req_mode.1794099729 |
| Directory | /workspace/45.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/45.edn_genbits.780458968 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 12455536 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:57:19 PM PST 24 |
| Finished | Jan 21 12:57:20 PM PST 24 |
| Peak memory | 204684 kb |
| Host | smart-1dfb6fca-f010-4a40-b75d-062b24b2c95e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=780458968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.780458968 |
| Directory | /workspace/45.edn_genbits/latest |
| Test location | /workspace/coverage/default/45.edn_intr.919439283 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 25762136 ps |
| CPU time | 0.94 seconds |
| Started | Jan 21 12:57:20 PM PST 24 |
| Finished | Jan 21 12:57:23 PM PST 24 |
| Peak memory | 214000 kb |
| Host | smart-40fbf2a1-eaa6-4e77-a928-148e80fc199d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=919439283 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.919439283 |
| Directory | /workspace/45.edn_intr/latest |
| Test location | /workspace/coverage/default/45.edn_smoke.2451259776 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 28588482 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 12:57:10 PM PST 24 |
| Finished | Jan 21 12:57:12 PM PST 24 |
| Peak memory | 204160 kb |
| Host | smart-e52b065f-1fe7-4ee5-91e9-bcfec784e790 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2451259776 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2451259776 |
| Directory | /workspace/45.edn_smoke/latest |
| Test location | /workspace/coverage/default/45.edn_stress_all.2111379283 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 45543907 ps |
| CPU time | 1.36 seconds |
| Started | Jan 21 12:57:19 PM PST 24 |
| Finished | Jan 21 12:57:21 PM PST 24 |
| Peak memory | 204700 kb |
| Host | smart-f648c00d-b778-4a77-b9f1-170eb4a4c61e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111379283 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2111379283 |
| Directory | /workspace/45.edn_stress_all/latest |
| Test location | /workspace/coverage/default/45.edn_stress_all_with_rand_reset.2418251996 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 258002973270 ps |
| CPU time | 678.44 seconds |
| Started | Jan 21 12:57:19 PM PST 24 |
| Finished | Jan 21 01:08:40 PM PST 24 |
| Peak memory | 215004 kb |
| Host | smart-6035643b-6a06-40a0-9309-6e280ea94253 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418251996 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.2418251996 |
| Directory | /workspace/45.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.edn_alert.271974122 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 69095963 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:57:28 PM PST 24 |
| Finished | Jan 21 12:57:30 PM PST 24 |
| Peak memory | 204640 kb |
| Host | smart-6a92eb54-4913-4180-80f6-399ee26bcd56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=271974122 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.271974122 |
| Directory | /workspace/46.edn_alert/latest |
| Test location | /workspace/coverage/default/46.edn_alert_test.191603136 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 11727380 ps |
| CPU time | 0.8 seconds |
| Started | Jan 21 12:57:31 PM PST 24 |
| Finished | Jan 21 12:57:32 PM PST 24 |
| Peak memory | 203848 kb |
| Host | smart-d3abd225-3ded-4dac-b9a3-b14b4abb0bb1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191603136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.191603136 |
| Directory | /workspace/46.edn_alert_test/latest |
| Test location | /workspace/coverage/default/46.edn_disable.2377081020 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 18259215 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:57:32 PM PST 24 |
| Finished | Jan 21 12:57:34 PM PST 24 |
| Peak memory | 213992 kb |
| Host | smart-3a18e692-c75c-4bde-8784-58cc2e4d994b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377081020 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.2377081020 |
| Directory | /workspace/46.edn_disable/latest |
| Test location | /workspace/coverage/default/46.edn_disable_auto_req_mode.4209176950 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 75435028 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:57:28 PM PST 24 |
| Finished | Jan 21 12:57:30 PM PST 24 |
| Peak memory | 214076 kb |
| Host | smart-90a0369e-48a1-403f-8070-7520beb719a6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209176950 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d isable_auto_req_mode.4209176950 |
| Directory | /workspace/46.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/46.edn_err.2329595695 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 18270463 ps |
| CPU time | 1 seconds |
| Started | Jan 21 12:57:26 PM PST 24 |
| Finished | Jan 21 12:57:28 PM PST 24 |
| Peak memory | 215396 kb |
| Host | smart-df37158f-bd1f-4f27-8a6c-9a9e9ab72dbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2329595695 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2329595695 |
| Directory | /workspace/46.edn_err/latest |
| Test location | /workspace/coverage/default/46.edn_genbits.1584228923 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 18168785 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:57:28 PM PST 24 |
| Finished | Jan 21 12:57:31 PM PST 24 |
| Peak memory | 204760 kb |
| Host | smart-5415cadb-da3b-43e3-9691-7d3152e876f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1584228923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.1584228923 |
| Directory | /workspace/46.edn_genbits/latest |
| Test location | /workspace/coverage/default/46.edn_intr.1092692569 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 21277974 ps |
| CPU time | 1.17 seconds |
| Started | Jan 21 12:57:30 PM PST 24 |
| Finished | Jan 21 12:57:32 PM PST 24 |
| Peak memory | 214036 kb |
| Host | smart-2c927f2f-5b3e-42e4-ab5d-414cb0cf8505 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1092692569 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1092692569 |
| Directory | /workspace/46.edn_intr/latest |
| Test location | /workspace/coverage/default/46.edn_smoke.3713258596 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 197323611 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:57:19 PM PST 24 |
| Finished | Jan 21 12:57:22 PM PST 24 |
| Peak memory | 204184 kb |
| Host | smart-2d743d19-5d1b-4e8b-abd7-1c6346055b9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3713258596 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3713258596 |
| Directory | /workspace/46.edn_smoke/latest |
| Test location | /workspace/coverage/default/46.edn_stress_all.2817982967 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2112804194 ps |
| CPU time | 3.61 seconds |
| Started | Jan 21 12:57:32 PM PST 24 |
| Finished | Jan 21 12:57:37 PM PST 24 |
| Peak memory | 205196 kb |
| Host | smart-68fe2612-38d4-4fba-be08-d683eabfb6a9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817982967 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2817982967 |
| Directory | /workspace/46.edn_stress_all/latest |
| Test location | /workspace/coverage/default/46.edn_stress_all_with_rand_reset.427838733 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 48935468026 ps |
| CPU time | 1056.36 seconds |
| Started | Jan 21 01:31:37 PM PST 24 |
| Finished | Jan 21 01:49:14 PM PST 24 |
| Peak memory | 214680 kb |
| Host | smart-1d92e02e-dd6e-4f11-99d0-8fd61e84d631 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427838733 -assert nopostpro c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.427838733 |
| Directory | /workspace/46.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/47.edn_alert.1591253061 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 30997582 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 12:57:28 PM PST 24 |
| Finished | Jan 21 12:57:30 PM PST 24 |
| Peak memory | 205480 kb |
| Host | smart-bced3535-e4be-42da-a305-d92d9d6c85f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1591253061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1591253061 |
| Directory | /workspace/47.edn_alert/latest |
| Test location | /workspace/coverage/default/47.edn_alert_test.4080361782 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 22690105 ps |
| CPU time | 0.87 seconds |
| Started | Jan 21 12:57:29 PM PST 24 |
| Finished | Jan 21 12:57:31 PM PST 24 |
| Peak memory | 204620 kb |
| Host | smart-b901b10f-1dbd-407c-8da7-51c095e3c49e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080361782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.4080361782 |
| Directory | /workspace/47.edn_alert_test/latest |
| Test location | /workspace/coverage/default/47.edn_disable.1132911540 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 25559311 ps |
| CPU time | 0.77 seconds |
| Started | Jan 21 12:57:27 PM PST 24 |
| Finished | Jan 21 12:57:29 PM PST 24 |
| Peak memory | 213980 kb |
| Host | smart-2908dd23-0cd0-4990-86ee-526d8e606293 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132911540 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1132911540 |
| Directory | /workspace/47.edn_disable/latest |
| Test location | /workspace/coverage/default/47.edn_disable_auto_req_mode.3257793137 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 27891815 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 12:57:31 PM PST 24 |
| Finished | Jan 21 12:57:33 PM PST 24 |
| Peak memory | 214932 kb |
| Host | smart-bd648fa5-d267-46fb-b3a8-8d885830ee7b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257793137 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d isable_auto_req_mode.3257793137 |
| Directory | /workspace/47.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/47.edn_err.1400851688 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 18932891 ps |
| CPU time | 1.05 seconds |
| Started | Jan 21 12:57:27 PM PST 24 |
| Finished | Jan 21 12:57:29 PM PST 24 |
| Peak memory | 221292 kb |
| Host | smart-7c3b8ee3-7e35-4a2e-94e9-c457a8c8dfe6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1400851688 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1400851688 |
| Directory | /workspace/47.edn_err/latest |
| Test location | /workspace/coverage/default/47.edn_genbits.3154317188 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 15916579 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 12:57:31 PM PST 24 |
| Finished | Jan 21 12:57:32 PM PST 24 |
| Peak memory | 204672 kb |
| Host | smart-8815b092-ac0a-4d96-b9b8-fca96ec59601 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3154317188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3154317188 |
| Directory | /workspace/47.edn_genbits/latest |
| Test location | /workspace/coverage/default/47.edn_intr.1595612155 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 19699544 ps |
| CPU time | 1.24 seconds |
| Started | Jan 21 12:57:30 PM PST 24 |
| Finished | Jan 21 12:57:32 PM PST 24 |
| Peak memory | 221416 kb |
| Host | smart-85efc413-a0ed-433d-8f80-57a202cb9541 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1595612155 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1595612155 |
| Directory | /workspace/47.edn_intr/latest |
| Test location | /workspace/coverage/default/47.edn_smoke.3592660539 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 27091526 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:57:28 PM PST 24 |
| Finished | Jan 21 12:57:30 PM PST 24 |
| Peak memory | 204296 kb |
| Host | smart-5c105deb-c48c-424f-80a1-2ac3c1e727dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3592660539 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3592660539 |
| Directory | /workspace/47.edn_smoke/latest |
| Test location | /workspace/coverage/default/47.edn_stress_all.3433584630 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 76822339 ps |
| CPU time | 2.23 seconds |
| Started | Jan 21 12:57:30 PM PST 24 |
| Finished | Jan 21 12:57:33 PM PST 24 |
| Peak memory | 205932 kb |
| Host | smart-230695b6-8c32-4d0b-bbf9-2c1e6e0c8ffe |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433584630 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3433584630 |
| Directory | /workspace/47.edn_stress_all/latest |
| Test location | /workspace/coverage/default/48.edn_alert.3192420752 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 25698535 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:57:35 PM PST 24 |
| Finished | Jan 21 12:57:37 PM PST 24 |
| Peak memory | 204788 kb |
| Host | smart-8b4ceec6-c20d-4506-be7f-13907cc39db6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192420752 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.3192420752 |
| Directory | /workspace/48.edn_alert/latest |
| Test location | /workspace/coverage/default/48.edn_alert_test.2341953381 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 22140344 ps |
| CPU time | 0.81 seconds |
| Started | Jan 21 12:57:36 PM PST 24 |
| Finished | Jan 21 12:57:38 PM PST 24 |
| Peak memory | 204008 kb |
| Host | smart-ce58dd1e-01cd-42cf-bbca-2877e290aac0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341953381 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2341953381 |
| Directory | /workspace/48.edn_alert_test/latest |
| Test location | /workspace/coverage/default/48.edn_disable.2990873495 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 16518021 ps |
| CPU time | 0.83 seconds |
| Started | Jan 21 12:57:38 PM PST 24 |
| Finished | Jan 21 12:57:39 PM PST 24 |
| Peak memory | 213972 kb |
| Host | smart-93dd9231-a186-44d3-9f95-50379f4f0331 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990873495 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2990873495 |
| Directory | /workspace/48.edn_disable/latest |
| Test location | /workspace/coverage/default/48.edn_disable_auto_req_mode.155624099 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 28942750 ps |
| CPU time | 0.94 seconds |
| Started | Jan 21 12:57:37 PM PST 24 |
| Finished | Jan 21 12:57:39 PM PST 24 |
| Peak memory | 214148 kb |
| Host | smart-9754dcba-b606-49ea-9b3b-22c331254ac4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155624099 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di sable_auto_req_mode.155624099 |
| Directory | /workspace/48.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/48.edn_genbits.4224065416 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 55780349 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:57:37 PM PST 24 |
| Finished | Jan 21 12:57:39 PM PST 24 |
| Peak memory | 204948 kb |
| Host | smart-4e1780a2-7479-47e3-9c2c-a37953d3340a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4224065416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.4224065416 |
| Directory | /workspace/48.edn_genbits/latest |
| Test location | /workspace/coverage/default/48.edn_intr.2216566039 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 19787085 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:57:38 PM PST 24 |
| Finished | Jan 21 12:57:40 PM PST 24 |
| Peak memory | 214056 kb |
| Host | smart-7cc1c9ec-9767-4b69-a1f2-bfafe2e5e57d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2216566039 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2216566039 |
| Directory | /workspace/48.edn_intr/latest |
| Test location | /workspace/coverage/default/48.edn_smoke.3745636473 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 19558700 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:57:37 PM PST 24 |
| Finished | Jan 21 12:57:39 PM PST 24 |
| Peak memory | 204392 kb |
| Host | smart-d8747024-31ca-47ca-a4e0-47d6608772a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3745636473 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3745636473 |
| Directory | /workspace/48.edn_smoke/latest |
| Test location | /workspace/coverage/default/48.edn_stress_all.3033282929 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 80754941 ps |
| CPU time | 1.12 seconds |
| Started | Jan 21 12:57:36 PM PST 24 |
| Finished | Jan 21 12:57:38 PM PST 24 |
| Peak memory | 204884 kb |
| Host | smart-46a691ae-3e1c-4147-bc7b-b58e6083e2e9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033282929 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3033282929 |
| Directory | /workspace/48.edn_stress_all/latest |
| Test location | /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3145861399 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 19397905428 ps |
| CPU time | 229.11 seconds |
| Started | Jan 21 12:57:38 PM PST 24 |
| Finished | Jan 21 01:01:29 PM PST 24 |
| Peak memory | 214008 kb |
| Host | smart-541b6dfc-bddb-4c88-a15a-9061edfeff0c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145861399 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3145861399 |
| Directory | /workspace/48.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.edn_alert.2010232175 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 66035551 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:57:45 PM PST 24 |
| Finished | Jan 21 12:57:46 PM PST 24 |
| Peak memory | 205460 kb |
| Host | smart-1beb5796-a9a2-4534-b4ce-9c8e399f6921 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2010232175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2010232175 |
| Directory | /workspace/49.edn_alert/latest |
| Test location | /workspace/coverage/default/49.edn_alert_test.453086460 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 22631013 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:57:48 PM PST 24 |
| Finished | Jan 21 12:57:49 PM PST 24 |
| Peak memory | 203964 kb |
| Host | smart-8b096fea-f18e-4a5c-9ab1-e9934a706504 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453086460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.453086460 |
| Directory | /workspace/49.edn_alert_test/latest |
| Test location | /workspace/coverage/default/49.edn_disable.1245398225 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 10225461 ps |
| CPU time | 0.87 seconds |
| Started | Jan 21 12:57:46 PM PST 24 |
| Finished | Jan 21 12:57:49 PM PST 24 |
| Peak memory | 213928 kb |
| Host | smart-45cd91b3-5755-4b4b-b412-461fc8422b21 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245398225 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1245398225 |
| Directory | /workspace/49.edn_disable/latest |
| Test location | /workspace/coverage/default/49.edn_disable_auto_req_mode.2164242324 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 171293240 ps |
| CPU time | 1 seconds |
| Started | Jan 21 12:57:45 PM PST 24 |
| Finished | Jan 21 12:57:47 PM PST 24 |
| Peak memory | 205960 kb |
| Host | smart-1929af56-f57f-4775-a63e-1f25d88c9db2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164242324 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d isable_auto_req_mode.2164242324 |
| Directory | /workspace/49.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/49.edn_err.382899176 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 25464881 ps |
| CPU time | 1.26 seconds |
| Started | Jan 21 12:57:47 PM PST 24 |
| Finished | Jan 21 12:57:49 PM PST 24 |
| Peak memory | 221396 kb |
| Host | smart-d2c20627-4df9-46ac-9511-654db77d481a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=382899176 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.382899176 |
| Directory | /workspace/49.edn_err/latest |
| Test location | /workspace/coverage/default/49.edn_genbits.4134331751 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 94975791 ps |
| CPU time | 2.73 seconds |
| Started | Jan 21 12:57:44 PM PST 24 |
| Finished | Jan 21 12:57:48 PM PST 24 |
| Peak memory | 213804 kb |
| Host | smart-db561491-5061-4e08-9fe3-2f44f7ffe49d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4134331751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.4134331751 |
| Directory | /workspace/49.edn_genbits/latest |
| Test location | /workspace/coverage/default/49.edn_intr.3550232461 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 23645311 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 12:57:46 PM PST 24 |
| Finished | Jan 21 12:57:48 PM PST 24 |
| Peak memory | 213872 kb |
| Host | smart-d87e4c30-4c38-458e-beb3-f0b16cf6cd87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3550232461 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3550232461 |
| Directory | /workspace/49.edn_intr/latest |
| Test location | /workspace/coverage/default/49.edn_smoke.4211092004 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 23174308 ps |
| CPU time | 0.87 seconds |
| Started | Jan 21 12:57:35 PM PST 24 |
| Finished | Jan 21 12:57:37 PM PST 24 |
| Peak memory | 204328 kb |
| Host | smart-70c035b9-558a-4ded-b30d-b798379a0b86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4211092004 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.4211092004 |
| Directory | /workspace/49.edn_smoke/latest |
| Test location | /workspace/coverage/default/49.edn_stress_all.312494975 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 419298294 ps |
| CPU time | 4.1 seconds |
| Started | Jan 21 12:57:40 PM PST 24 |
| Finished | Jan 21 12:57:45 PM PST 24 |
| Peak memory | 205504 kb |
| Host | smart-a3df8294-ede4-45c9-8852-47c78e5cb330 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312494975 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.312494975 |
| Directory | /workspace/49.edn_stress_all/latest |
| Test location | /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2934444088 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 242591604174 ps |
| CPU time | 3443.08 seconds |
| Started | Jan 21 12:57:35 PM PST 24 |
| Finished | Jan 21 01:54:59 PM PST 24 |
| Peak memory | 231496 kb |
| Host | smart-6f3bdea8-4470-41a6-a37e-a2ebc4736321 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934444088 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2934444088 |
| Directory | /workspace/49.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.edn_alert.3193169773 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 34228421 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 01:30:17 PM PST 24 |
| Finished | Jan 21 01:30:18 PM PST 24 |
| Peak memory | 205096 kb |
| Host | smart-db2428b1-fa92-45fb-a95f-290c86ada629 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3193169773 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3193169773 |
| Directory | /workspace/5.edn_alert/latest |
| Test location | /workspace/coverage/default/5.edn_alert_test.209426624 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 154707619 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 12:52:07 PM PST 24 |
| Finished | Jan 21 12:52:08 PM PST 24 |
| Peak memory | 203924 kb |
| Host | smart-1ab71d17-45b7-4c4b-a84d-dfee03188070 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209426624 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.209426624 |
| Directory | /workspace/5.edn_alert_test/latest |
| Test location | /workspace/coverage/default/5.edn_disable_auto_req_mode.1376276866 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 36104049 ps |
| CPU time | 1.1 seconds |
| Started | Jan 21 12:52:09 PM PST 24 |
| Finished | Jan 21 12:52:11 PM PST 24 |
| Peak memory | 214204 kb |
| Host | smart-2ffeb4fa-eb0e-4d46-bd56-5fb3a6b6e814 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376276866 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di sable_auto_req_mode.1376276866 |
| Directory | /workspace/5.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/5.edn_err.3787054220 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 52546266 ps |
| CPU time | 1.25 seconds |
| Started | Jan 21 01:46:18 PM PST 24 |
| Finished | Jan 21 01:46:20 PM PST 24 |
| Peak memory | 221508 kb |
| Host | smart-1f707353-d00c-447f-ad9e-a779fa37970d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3787054220 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3787054220 |
| Directory | /workspace/5.edn_err/latest |
| Test location | /workspace/coverage/default/5.edn_genbits.1674902984 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 49446482 ps |
| CPU time | 1.11 seconds |
| Started | Jan 21 12:51:51 PM PST 24 |
| Finished | Jan 21 12:51:55 PM PST 24 |
| Peak memory | 213588 kb |
| Host | smart-eed82f95-dc2d-48c9-be62-6b6ca2b48ec0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1674902984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1674902984 |
| Directory | /workspace/5.edn_genbits/latest |
| Test location | /workspace/coverage/default/5.edn_intr.2102727653 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 20853344 ps |
| CPU time | 1.16 seconds |
| Started | Jan 21 02:21:25 PM PST 24 |
| Finished | Jan 21 02:21:28 PM PST 24 |
| Peak memory | 221076 kb |
| Host | smart-6e9d664f-77ac-421f-8dbf-3a95a256c798 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2102727653 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.2102727653 |
| Directory | /workspace/5.edn_intr/latest |
| Test location | /workspace/coverage/default/5.edn_regwen.1697048823 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 45471237 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:51:50 PM PST 24 |
| Finished | Jan 21 12:51:54 PM PST 24 |
| Peak memory | 204572 kb |
| Host | smart-3da09490-4c22-4fc8-9446-4c253ffe0492 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1697048823 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1697048823 |
| Directory | /workspace/5.edn_regwen/latest |
| Test location | /workspace/coverage/default/5.edn_smoke.3468175444 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 88953492 ps |
| CPU time | 0.81 seconds |
| Started | Jan 21 12:51:49 PM PST 24 |
| Finished | Jan 21 12:51:54 PM PST 24 |
| Peak memory | 204336 kb |
| Host | smart-8246943d-c864-4954-89d2-9f0b17db8277 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3468175444 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3468175444 |
| Directory | /workspace/5.edn_smoke/latest |
| Test location | /workspace/coverage/default/5.edn_stress_all.1537349937 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 154226610 ps |
| CPU time | 2.01 seconds |
| Started | Jan 21 12:51:56 PM PST 24 |
| Finished | Jan 21 12:51:59 PM PST 24 |
| Peak memory | 205496 kb |
| Host | smart-d2218331-3f6b-4cbf-afb7-c1ff3c8febe8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537349937 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1537349937 |
| Directory | /workspace/5.edn_stress_all/latest |
| Test location | /workspace/coverage/default/5.edn_stress_all_with_rand_reset.3507711195 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 114356144014 ps |
| CPU time | 250.76 seconds |
| Started | Jan 21 01:26:08 PM PST 24 |
| Finished | Jan 21 01:30:20 PM PST 24 |
| Peak memory | 215500 kb |
| Host | smart-f9472fe0-b7d2-4137-93fe-7b85cdac9d70 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507711195 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.3507711195 |
| Directory | /workspace/5.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/50.edn_err.2949082491 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 19412069 ps |
| CPU time | 1.01 seconds |
| Started | Jan 21 12:57:46 PM PST 24 |
| Finished | Jan 21 12:57:48 PM PST 24 |
| Peak memory | 215368 kb |
| Host | smart-f3961227-83a3-454d-a277-22fcfa45220b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2949082491 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2949082491 |
| Directory | /workspace/50.edn_err/latest |
| Test location | /workspace/coverage/default/50.edn_genbits.2663015929 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 22180326 ps |
| CPU time | 1.11 seconds |
| Started | Jan 21 12:57:46 PM PST 24 |
| Finished | Jan 21 12:57:49 PM PST 24 |
| Peak memory | 205032 kb |
| Host | smart-3fbbb7b2-a5e9-4460-9f69-1776e21d3d52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2663015929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2663015929 |
| Directory | /workspace/50.edn_genbits/latest |
| Test location | /workspace/coverage/default/51.edn_err.4138313271 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 29492537 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 12:57:44 PM PST 24 |
| Finished | Jan 21 12:57:45 PM PST 24 |
| Peak memory | 213872 kb |
| Host | smart-ad59fab8-e315-4b2d-a288-4e0da0937fa2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4138313271 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.4138313271 |
| Directory | /workspace/51.edn_err/latest |
| Test location | /workspace/coverage/default/52.edn_err.2616345625 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 35403065 ps |
| CPU time | 0.94 seconds |
| Started | Jan 21 12:57:45 PM PST 24 |
| Finished | Jan 21 12:57:47 PM PST 24 |
| Peak memory | 221232 kb |
| Host | smart-8d8ba90f-3e35-4fe3-9abf-260f3dfa5364 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2616345625 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2616345625 |
| Directory | /workspace/52.edn_err/latest |
| Test location | /workspace/coverage/default/52.edn_genbits.3989643262 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 16207340 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 12:57:49 PM PST 24 |
| Finished | Jan 21 12:57:51 PM PST 24 |
| Peak memory | 204752 kb |
| Host | smart-e1d03723-aec2-4696-b267-5606b2d27a20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3989643262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3989643262 |
| Directory | /workspace/52.edn_genbits/latest |
| Test location | /workspace/coverage/default/53.edn_err.4091829080 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 25382937 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:57:45 PM PST 24 |
| Finished | Jan 21 12:57:48 PM PST 24 |
| Peak memory | 215176 kb |
| Host | smart-3ab9f50a-5438-4f9b-8a8d-eddb4c5e81f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4091829080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.4091829080 |
| Directory | /workspace/53.edn_err/latest |
| Test location | /workspace/coverage/default/54.edn_err.2539992488 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 24889951 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 12:57:58 PM PST 24 |
| Finished | Jan 21 12:58:00 PM PST 24 |
| Peak memory | 215136 kb |
| Host | smart-0e41e05d-e069-45ed-80fd-f82a3539a03a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2539992488 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2539992488 |
| Directory | /workspace/54.edn_err/latest |
| Test location | /workspace/coverage/default/54.edn_genbits.2174404113 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 31724576 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 12:58:02 PM PST 24 |
| Finished | Jan 21 12:58:04 PM PST 24 |
| Peak memory | 205392 kb |
| Host | smart-687c9217-dc56-49c9-acd0-977435bb7d43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2174404113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2174404113 |
| Directory | /workspace/54.edn_genbits/latest |
| Test location | /workspace/coverage/default/55.edn_genbits.212487826 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 44987767 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:57:57 PM PST 24 |
| Finished | Jan 21 12:57:59 PM PST 24 |
| Peak memory | 204988 kb |
| Host | smart-aaf80eb0-ea61-4e6c-b3e2-975bdcf3b648 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=212487826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.212487826 |
| Directory | /workspace/55.edn_genbits/latest |
| Test location | /workspace/coverage/default/56.edn_err.3229498236 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 72329904 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 12:58:02 PM PST 24 |
| Finished | Jan 21 12:58:04 PM PST 24 |
| Peak memory | 214844 kb |
| Host | smart-4faf26ff-0721-4d10-af89-991d86e1c052 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3229498236 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3229498236 |
| Directory | /workspace/56.edn_err/latest |
| Test location | /workspace/coverage/default/56.edn_genbits.2943770024 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 21028837 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 12:58:02 PM PST 24 |
| Finished | Jan 21 12:58:04 PM PST 24 |
| Peak memory | 205348 kb |
| Host | smart-2abb2d2f-21c0-4258-9617-ac0565ded769 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2943770024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.2943770024 |
| Directory | /workspace/56.edn_genbits/latest |
| Test location | /workspace/coverage/default/57.edn_err.3243288351 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 25532921 ps |
| CPU time | 1.34 seconds |
| Started | Jan 21 12:58:02 PM PST 24 |
| Finished | Jan 21 12:58:04 PM PST 24 |
| Peak memory | 221516 kb |
| Host | smart-776ac0fa-1327-4f05-b153-8dcaa4f65020 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3243288351 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3243288351 |
| Directory | /workspace/57.edn_err/latest |
| Test location | /workspace/coverage/default/57.edn_genbits.2565150703 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 48480499 ps |
| CPU time | 1.03 seconds |
| Started | Jan 21 12:57:57 PM PST 24 |
| Finished | Jan 21 12:57:58 PM PST 24 |
| Peak memory | 205000 kb |
| Host | smart-5629c0d6-a434-497d-a947-144ebbb35daa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2565150703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2565150703 |
| Directory | /workspace/57.edn_genbits/latest |
| Test location | /workspace/coverage/default/58.edn_err.2758586472 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 112497644 ps |
| CPU time | 1.1 seconds |
| Started | Jan 21 12:57:57 PM PST 24 |
| Finished | Jan 21 12:57:59 PM PST 24 |
| Peak memory | 221312 kb |
| Host | smart-095952d8-2cce-4dbe-a005-ceda9ca5e5c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758586472 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2758586472 |
| Directory | /workspace/58.edn_err/latest |
| Test location | /workspace/coverage/default/59.edn_err.868349452 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 30168687 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 01:10:56 PM PST 24 |
| Finished | Jan 21 01:10:58 PM PST 24 |
| Peak memory | 221460 kb |
| Host | smart-293659e2-fb95-4f37-b811-e1d36c32f0e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=868349452 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.868349452 |
| Directory | /workspace/59.edn_err/latest |
| Test location | /workspace/coverage/default/59.edn_genbits.389545862 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 80308721 ps |
| CPU time | 0.87 seconds |
| Started | Jan 21 01:37:59 PM PST 24 |
| Finished | Jan 21 01:38:00 PM PST 24 |
| Peak memory | 204680 kb |
| Host | smart-c8d06d26-10cb-48ce-b343-379b345d898d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=389545862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.389545862 |
| Directory | /workspace/59.edn_genbits/latest |
| Test location | /workspace/coverage/default/6.edn_alert.1693660029 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 54865182 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:52:12 PM PST 24 |
| Finished | Jan 21 12:52:14 PM PST 24 |
| Peak memory | 204756 kb |
| Host | smart-88357e8a-9b0e-40f4-9bb5-803a413f27c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1693660029 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.1693660029 |
| Directory | /workspace/6.edn_alert/latest |
| Test location | /workspace/coverage/default/6.edn_alert_test.2463130747 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 42924310 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 01:19:07 PM PST 24 |
| Finished | Jan 21 01:19:08 PM PST 24 |
| Peak memory | 204216 kb |
| Host | smart-195955a2-202e-4123-b262-0a53935bd11d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463130747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2463130747 |
| Directory | /workspace/6.edn_alert_test/latest |
| Test location | /workspace/coverage/default/6.edn_disable.983200360 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 14045771 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:52:10 PM PST 24 |
| Finished | Jan 21 12:52:12 PM PST 24 |
| Peak memory | 213952 kb |
| Host | smart-c56d84c2-3400-4ce2-b532-6b6e41507ed5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983200360 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.983200360 |
| Directory | /workspace/6.edn_disable/latest |
| Test location | /workspace/coverage/default/6.edn_disable_auto_req_mode.4049109711 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 20486726 ps |
| CPU time | 1.01 seconds |
| Started | Jan 21 12:52:13 PM PST 24 |
| Finished | Jan 21 12:52:15 PM PST 24 |
| Peak memory | 214076 kb |
| Host | smart-2be31a7d-a7bf-4671-912f-d09b28fa80a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049109711 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di sable_auto_req_mode.4049109711 |
| Directory | /workspace/6.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/6.edn_err.4009512523 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 21960475 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 12:52:11 PM PST 24 |
| Finished | Jan 21 12:52:13 PM PST 24 |
| Peak memory | 215492 kb |
| Host | smart-bbb406d2-6924-434c-a9d0-c838e64c6c4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4009512523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.4009512523 |
| Directory | /workspace/6.edn_err/latest |
| Test location | /workspace/coverage/default/6.edn_genbits.2512500717 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 98185477 ps |
| CPU time | 2.49 seconds |
| Started | Jan 21 12:52:05 PM PST 24 |
| Finished | Jan 21 12:52:08 PM PST 24 |
| Peak memory | 213760 kb |
| Host | smart-f7a58211-2f80-42d2-bd6e-76a42b86fc9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2512500717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.2512500717 |
| Directory | /workspace/6.edn_genbits/latest |
| Test location | /workspace/coverage/default/6.edn_intr.1440417039 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 24981329 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:52:10 PM PST 24 |
| Finished | Jan 21 12:52:12 PM PST 24 |
| Peak memory | 214020 kb |
| Host | smart-8574b773-968d-4db0-b002-8f7efa5e24a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1440417039 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1440417039 |
| Directory | /workspace/6.edn_intr/latest |
| Test location | /workspace/coverage/default/6.edn_smoke.2193958846 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 16099628 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:52:03 PM PST 24 |
| Finished | Jan 21 12:52:05 PM PST 24 |
| Peak memory | 204264 kb |
| Host | smart-0195703d-5e2d-4886-9c4f-ba4798aa5006 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2193958846 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2193958846 |
| Directory | /workspace/6.edn_smoke/latest |
| Test location | /workspace/coverage/default/6.edn_stress_all.3052070706 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 491950562 ps |
| CPU time | 1.67 seconds |
| Started | Jan 21 12:52:03 PM PST 24 |
| Finished | Jan 21 12:52:05 PM PST 24 |
| Peak memory | 205476 kb |
| Host | smart-1358cce4-34af-4130-8b70-6348fc40cf35 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052070706 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3052070706 |
| Directory | /workspace/6.edn_stress_all/latest |
| Test location | /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2281586123 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 602013352902 ps |
| CPU time | 2749.6 seconds |
| Started | Jan 21 12:52:10 PM PST 24 |
| Finished | Jan 21 01:38:00 PM PST 24 |
| Peak memory | 221448 kb |
| Host | smart-76852c72-8418-46ef-a6aa-ca041575d9b6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281586123 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2281586123 |
| Directory | /workspace/6.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/60.edn_err.1086380576 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 42708787 ps |
| CPU time | 1.32 seconds |
| Started | Jan 21 01:06:37 PM PST 24 |
| Finished | Jan 21 01:06:39 PM PST 24 |
| Peak memory | 221476 kb |
| Host | smart-fddca61d-cd4c-4af8-a82d-5d3e16544721 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1086380576 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1086380576 |
| Directory | /workspace/60.edn_err/latest |
| Test location | /workspace/coverage/default/60.edn_genbits.2703969420 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 380946972 ps |
| CPU time | 4.45 seconds |
| Started | Jan 21 01:10:17 PM PST 24 |
| Finished | Jan 21 01:10:22 PM PST 24 |
| Peak memory | 213868 kb |
| Host | smart-f51cf226-cfab-49d6-873a-222dff939d9d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2703969420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2703969420 |
| Directory | /workspace/60.edn_genbits/latest |
| Test location | /workspace/coverage/default/61.edn_err.670754182 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 19706994 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 02:29:18 PM PST 24 |
| Finished | Jan 21 02:29:20 PM PST 24 |
| Peak memory | 215408 kb |
| Host | smart-ef89ee25-e703-4057-b034-e88393f7e63b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=670754182 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.670754182 |
| Directory | /workspace/61.edn_err/latest |
| Test location | /workspace/coverage/default/61.edn_genbits.1474342247 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 42394999 ps |
| CPU time | 1.57 seconds |
| Started | Jan 21 01:10:31 PM PST 24 |
| Finished | Jan 21 01:10:36 PM PST 24 |
| Peak memory | 213864 kb |
| Host | smart-37185147-43a6-422f-9079-a83f7493f045 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1474342247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1474342247 |
| Directory | /workspace/61.edn_genbits/latest |
| Test location | /workspace/coverage/default/62.edn_err.3380217861 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 20846862 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 01:25:42 PM PST 24 |
| Finished | Jan 21 01:25:44 PM PST 24 |
| Peak memory | 221332 kb |
| Host | smart-986bc440-a165-4e6e-812a-a1ec9fa06e1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3380217861 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3380217861 |
| Directory | /workspace/62.edn_err/latest |
| Test location | /workspace/coverage/default/62.edn_genbits.152227756 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 57718718 ps |
| CPU time | 1.09 seconds |
| Started | Jan 21 02:08:38 PM PST 24 |
| Finished | Jan 21 02:08:39 PM PST 24 |
| Peak memory | 213892 kb |
| Host | smart-96db9db7-4e21-4612-9eb0-28b1d7e8569f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=152227756 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.152227756 |
| Directory | /workspace/62.edn_genbits/latest |
| Test location | /workspace/coverage/default/63.edn_err.1101042677 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 30202544 ps |
| CPU time | 1.16 seconds |
| Started | Jan 21 01:50:28 PM PST 24 |
| Finished | Jan 21 01:50:30 PM PST 24 |
| Peak memory | 216496 kb |
| Host | smart-ed103f9f-7e50-46dd-a99f-6578814f4908 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1101042677 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1101042677 |
| Directory | /workspace/63.edn_err/latest |
| Test location | /workspace/coverage/default/63.edn_genbits.249574611 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 184899993 ps |
| CPU time | 1.09 seconds |
| Started | Jan 21 01:52:00 PM PST 24 |
| Finished | Jan 21 01:52:01 PM PST 24 |
| Peak memory | 205248 kb |
| Host | smart-3966d201-7e1c-47a1-b96e-1981c0f6bd1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=249574611 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.249574611 |
| Directory | /workspace/63.edn_genbits/latest |
| Test location | /workspace/coverage/default/64.edn_genbits.398879703 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4378427577 ps |
| CPU time | 92.01 seconds |
| Started | Jan 21 01:54:03 PM PST 24 |
| Finished | Jan 21 01:55:35 PM PST 24 |
| Peak memory | 213952 kb |
| Host | smart-ad563ce1-3a86-4c18-b31e-7e0746adb1b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=398879703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.398879703 |
| Directory | /workspace/64.edn_genbits/latest |
| Test location | /workspace/coverage/default/65.edn_err.1887510159 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 22144054 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 12:58:19 PM PST 24 |
| Finished | Jan 21 12:58:21 PM PST 24 |
| Peak memory | 221172 kb |
| Host | smart-676643d1-e5ca-49a9-9e5a-ea79829c80ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1887510159 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1887510159 |
| Directory | /workspace/65.edn_err/latest |
| Test location | /workspace/coverage/default/65.edn_genbits.2805185584 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 44596213 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 02:37:01 PM PST 24 |
| Finished | Jan 21 02:37:03 PM PST 24 |
| Peak memory | 204772 kb |
| Host | smart-f3e592bc-b350-44dd-bafd-8d52edfd1816 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2805185584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2805185584 |
| Directory | /workspace/65.edn_genbits/latest |
| Test location | /workspace/coverage/default/66.edn_genbits.2369155856 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 64628992 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:58:11 PM PST 24 |
| Finished | Jan 21 12:58:13 PM PST 24 |
| Peak memory | 213800 kb |
| Host | smart-08c221f8-4ad9-4cab-9243-8ad9b90f0679 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2369155856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2369155856 |
| Directory | /workspace/66.edn_genbits/latest |
| Test location | /workspace/coverage/default/67.edn_genbits.2344932151 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 22160005 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:58:12 PM PST 24 |
| Finished | Jan 21 12:58:13 PM PST 24 |
| Peak memory | 205012 kb |
| Host | smart-f50edafa-f7f4-4c47-bcfc-3b1984c81a6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2344932151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2344932151 |
| Directory | /workspace/67.edn_genbits/latest |
| Test location | /workspace/coverage/default/68.edn_err.2068192770 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 62065204 ps |
| CPU time | 1.09 seconds |
| Started | Jan 21 12:58:20 PM PST 24 |
| Finished | Jan 21 12:58:22 PM PST 24 |
| Peak memory | 229504 kb |
| Host | smart-12be9e29-53ec-421a-875b-ba11a017c791 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2068192770 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2068192770 |
| Directory | /workspace/68.edn_err/latest |
| Test location | /workspace/coverage/default/68.edn_genbits.2394404075 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 101255766 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 12:58:12 PM PST 24 |
| Finished | Jan 21 12:58:14 PM PST 24 |
| Peak memory | 204436 kb |
| Host | smart-22e55b96-dade-4108-b55a-21fdaf4bd668 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2394404075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2394404075 |
| Directory | /workspace/68.edn_genbits/latest |
| Test location | /workspace/coverage/default/69.edn_genbits.3554757038 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 64097639 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 12:58:18 PM PST 24 |
| Finished | Jan 21 12:58:20 PM PST 24 |
| Peak memory | 204676 kb |
| Host | smart-9aaf9136-02fd-44a0-bd39-b568368b614f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3554757038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3554757038 |
| Directory | /workspace/69.edn_genbits/latest |
| Test location | /workspace/coverage/default/7.edn_alert.3139032013 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 20020689 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:52:17 PM PST 24 |
| Finished | Jan 21 12:52:19 PM PST 24 |
| Peak memory | 204944 kb |
| Host | smart-a67427ff-e102-4a22-9c55-a2f4ebc47d68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3139032013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.3139032013 |
| Directory | /workspace/7.edn_alert/latest |
| Test location | /workspace/coverage/default/7.edn_alert_test.51551405 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 13240099 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:52:27 PM PST 24 |
| Finished | Jan 21 12:52:28 PM PST 24 |
| Peak memory | 204652 kb |
| Host | smart-67fe449e-56c7-4d9c-8aa1-2c3b5f7f8084 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51551405 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.51551405 |
| Directory | /workspace/7.edn_alert_test/latest |
| Test location | /workspace/coverage/default/7.edn_disable_auto_req_mode.1249345692 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 23392438 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:52:16 PM PST 24 |
| Finished | Jan 21 12:52:17 PM PST 24 |
| Peak memory | 214128 kb |
| Host | smart-7b4eb4a3-7766-423f-98ab-9ceee0e70919 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249345692 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di sable_auto_req_mode.1249345692 |
| Directory | /workspace/7.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/7.edn_err.636060262 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 49606520 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:52:20 PM PST 24 |
| Finished | Jan 21 12:52:21 PM PST 24 |
| Peak memory | 215344 kb |
| Host | smart-ce001ef6-99a7-4319-a270-1649fd1588bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=636060262 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.636060262 |
| Directory | /workspace/7.edn_err/latest |
| Test location | /workspace/coverage/default/7.edn_genbits.963287877 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 25299356 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:52:16 PM PST 24 |
| Finished | Jan 21 12:52:18 PM PST 24 |
| Peak memory | 204472 kb |
| Host | smart-c79cc054-b15b-4062-81fb-28a779790c6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=963287877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.963287877 |
| Directory | /workspace/7.edn_genbits/latest |
| Test location | /workspace/coverage/default/7.edn_intr.410935020 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 62432108 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 01:10:21 PM PST 24 |
| Finished | Jan 21 01:10:23 PM PST 24 |
| Peak memory | 213736 kb |
| Host | smart-76befb0c-d744-456b-bc76-27996bf0dffe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=410935020 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.410935020 |
| Directory | /workspace/7.edn_intr/latest |
| Test location | /workspace/coverage/default/7.edn_regwen.285427040 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 18477061 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:52:17 PM PST 24 |
| Finished | Jan 21 12:52:18 PM PST 24 |
| Peak memory | 204548 kb |
| Host | smart-32c54026-70d9-4568-b23a-89b86db4e192 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=285427040 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.285427040 |
| Directory | /workspace/7.edn_regwen/latest |
| Test location | /workspace/coverage/default/7.edn_smoke.1114833355 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 25988688 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:52:17 PM PST 24 |
| Finished | Jan 21 12:52:19 PM PST 24 |
| Peak memory | 204248 kb |
| Host | smart-8cb9a98e-da85-4213-9492-7581f1a4495c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1114833355 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1114833355 |
| Directory | /workspace/7.edn_smoke/latest |
| Test location | /workspace/coverage/default/7.edn_stress_all.1220800875 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 340833500 ps |
| CPU time | 3.68 seconds |
| Started | Jan 21 01:54:55 PM PST 24 |
| Finished | Jan 21 01:54:59 PM PST 24 |
| Peak memory | 205892 kb |
| Host | smart-98139803-dee1-4c13-b74e-472c47edeac4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220800875 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1220800875 |
| Directory | /workspace/7.edn_stress_all/latest |
| Test location | /workspace/coverage/default/70.edn_err.2435747400 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 18927981 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:58:17 PM PST 24 |
| Finished | Jan 21 12:58:19 PM PST 24 |
| Peak memory | 215072 kb |
| Host | smart-6fd7881e-051f-422c-93f2-bc1f827487c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2435747400 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2435747400 |
| Directory | /workspace/70.edn_err/latest |
| Test location | /workspace/coverage/default/70.edn_genbits.1058017973 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 35056142 ps |
| CPU time | 1.09 seconds |
| Started | Jan 21 12:58:26 PM PST 24 |
| Finished | Jan 21 12:58:28 PM PST 24 |
| Peak memory | 204620 kb |
| Host | smart-607e3d92-20cb-4167-979e-af77891f3969 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1058017973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1058017973 |
| Directory | /workspace/70.edn_genbits/latest |
| Test location | /workspace/coverage/default/71.edn_genbits.1629881509 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 41814237 ps |
| CPU time | 1.05 seconds |
| Started | Jan 21 12:58:24 PM PST 24 |
| Finished | Jan 21 12:58:25 PM PST 24 |
| Peak memory | 213736 kb |
| Host | smart-32bd1793-981b-41d0-8330-fad1e4cdeb88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1629881509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1629881509 |
| Directory | /workspace/71.edn_genbits/latest |
| Test location | /workspace/coverage/default/72.edn_err.1650885179 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 33279813 ps |
| CPU time | 0.81 seconds |
| Started | Jan 21 12:58:22 PM PST 24 |
| Finished | Jan 21 12:58:23 PM PST 24 |
| Peak memory | 214920 kb |
| Host | smart-3044b337-e019-4b64-9efb-6eb9af34245e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1650885179 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1650885179 |
| Directory | /workspace/72.edn_err/latest |
| Test location | /workspace/coverage/default/72.edn_genbits.178557019 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 84859374 ps |
| CPU time | 1.15 seconds |
| Started | Jan 21 12:58:26 PM PST 24 |
| Finished | Jan 21 12:58:28 PM PST 24 |
| Peak memory | 205064 kb |
| Host | smart-b3c65e2d-8cab-4a93-943b-0fe5843f960d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=178557019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.178557019 |
| Directory | /workspace/72.edn_genbits/latest |
| Test location | /workspace/coverage/default/73.edn_err.525545709 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 18004080 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 12:58:21 PM PST 24 |
| Finished | Jan 21 12:58:23 PM PST 24 |
| Peak memory | 214900 kb |
| Host | smart-b36866ae-92e1-49fa-9218-385199bf5fdb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=525545709 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.525545709 |
| Directory | /workspace/73.edn_err/latest |
| Test location | /workspace/coverage/default/73.edn_genbits.544403393 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 63457398 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:58:21 PM PST 24 |
| Finished | Jan 21 12:58:22 PM PST 24 |
| Peak memory | 204568 kb |
| Host | smart-06bd6e69-8c83-407c-85b6-e48edaf2a3dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=544403393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.544403393 |
| Directory | /workspace/73.edn_genbits/latest |
| Test location | /workspace/coverage/default/74.edn_err.2071818410 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 19028139 ps |
| CPU time | 1.03 seconds |
| Started | Jan 21 12:58:19 PM PST 24 |
| Finished | Jan 21 12:58:22 PM PST 24 |
| Peak memory | 215048 kb |
| Host | smart-e1166c8c-e35b-430a-8847-065a5f94dae2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2071818410 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2071818410 |
| Directory | /workspace/74.edn_err/latest |
| Test location | /workspace/coverage/default/74.edn_genbits.1553470925 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 19657826 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 12:58:21 PM PST 24 |
| Finished | Jan 21 12:58:23 PM PST 24 |
| Peak memory | 204708 kb |
| Host | smart-708c9d66-7721-4c45-baa8-61fbfafd1d9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1553470925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1553470925 |
| Directory | /workspace/74.edn_genbits/latest |
| Test location | /workspace/coverage/default/75.edn_err.3387367523 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 26929482 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 12:58:26 PM PST 24 |
| Finished | Jan 21 12:58:28 PM PST 24 |
| Peak memory | 220484 kb |
| Host | smart-00ec1db7-ad5c-4b46-8df3-0ef60dd71ecc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3387367523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3387367523 |
| Directory | /workspace/75.edn_err/latest |
| Test location | /workspace/coverage/default/75.edn_genbits.2678857311 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 79091870 ps |
| CPU time | 1.24 seconds |
| Started | Jan 21 12:58:26 PM PST 24 |
| Finished | Jan 21 12:58:28 PM PST 24 |
| Peak memory | 214092 kb |
| Host | smart-59c40ead-0b3f-49e0-94a0-269f9b8723e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2678857311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2678857311 |
| Directory | /workspace/75.edn_genbits/latest |
| Test location | /workspace/coverage/default/76.edn_err.632541457 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 114010892 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:58:26 PM PST 24 |
| Finished | Jan 21 12:58:27 PM PST 24 |
| Peak memory | 216072 kb |
| Host | smart-14b3da2e-f032-40eb-9e35-f04d3a0c11c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632541457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.632541457 |
| Directory | /workspace/76.edn_err/latest |
| Test location | /workspace/coverage/default/76.edn_genbits.1964476442 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 19162734 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:58:26 PM PST 24 |
| Finished | Jan 21 12:58:28 PM PST 24 |
| Peak memory | 205048 kb |
| Host | smart-3efc2cf8-b54d-408d-948a-60885f125e15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1964476442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1964476442 |
| Directory | /workspace/76.edn_genbits/latest |
| Test location | /workspace/coverage/default/77.edn_err.4219993075 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 36404646 ps |
| CPU time | 0.77 seconds |
| Started | Jan 21 12:58:30 PM PST 24 |
| Finished | Jan 21 12:58:32 PM PST 24 |
| Peak memory | 215012 kb |
| Host | smart-feee4e1c-f171-4ca3-b8ee-529be6f5f80e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4219993075 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.4219993075 |
| Directory | /workspace/77.edn_err/latest |
| Test location | /workspace/coverage/default/77.edn_genbits.3479904329 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 16899103 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:58:20 PM PST 24 |
| Finished | Jan 21 12:58:22 PM PST 24 |
| Peak memory | 205072 kb |
| Host | smart-f74b3779-9b53-44bf-b540-1c64f2cd772d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3479904329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3479904329 |
| Directory | /workspace/77.edn_genbits/latest |
| Test location | /workspace/coverage/default/78.edn_err.910482181 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 40600452 ps |
| CPU time | 1.04 seconds |
| Started | Jan 21 12:58:29 PM PST 24 |
| Finished | Jan 21 12:58:31 PM PST 24 |
| Peak memory | 216420 kb |
| Host | smart-fabb17f7-7e2e-40c7-ab18-74c0b497fdab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=910482181 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.910482181 |
| Directory | /workspace/78.edn_err/latest |
| Test location | /workspace/coverage/default/78.edn_genbits.2483001088 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 28267506 ps |
| CPU time | 1.28 seconds |
| Started | Jan 21 12:58:30 PM PST 24 |
| Finished | Jan 21 12:58:32 PM PST 24 |
| Peak memory | 213732 kb |
| Host | smart-b635203b-d353-4f12-8865-56ffdb4b3532 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2483001088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2483001088 |
| Directory | /workspace/78.edn_genbits/latest |
| Test location | /workspace/coverage/default/79.edn_err.29934821 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 36638279 ps |
| CPU time | 0.81 seconds |
| Started | Jan 21 12:58:29 PM PST 24 |
| Finished | Jan 21 12:58:30 PM PST 24 |
| Peak memory | 214888 kb |
| Host | smart-c20ec5cf-babd-4dff-86fe-49a24b900ec9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=29934821 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.29934821 |
| Directory | /workspace/79.edn_err/latest |
| Test location | /workspace/coverage/default/79.edn_genbits.2049689292 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 26517385 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:58:38 PM PST 24 |
| Finished | Jan 21 12:58:39 PM PST 24 |
| Peak memory | 204600 kb |
| Host | smart-67d1025e-9a41-4b51-9092-548b4c6da4c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2049689292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2049689292 |
| Directory | /workspace/79.edn_genbits/latest |
| Test location | /workspace/coverage/default/8.edn_alert_test.2773665556 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 29956635 ps |
| CPU time | 0.76 seconds |
| Started | Jan 21 12:52:31 PM PST 24 |
| Finished | Jan 21 12:52:33 PM PST 24 |
| Peak memory | 203488 kb |
| Host | smart-ffbaf62f-5d15-44c0-a621-41e2449f0f2d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773665556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2773665556 |
| Directory | /workspace/8.edn_alert_test/latest |
| Test location | /workspace/coverage/default/8.edn_disable.1620854495 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 28123984 ps |
| CPU time | 0.78 seconds |
| Started | Jan 21 12:52:31 PM PST 24 |
| Finished | Jan 21 12:52:32 PM PST 24 |
| Peak memory | 213928 kb |
| Host | smart-a0451c22-2866-4ff9-89ae-25e5fe2e7432 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620854495 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1620854495 |
| Directory | /workspace/8.edn_disable/latest |
| Test location | /workspace/coverage/default/8.edn_disable_auto_req_mode.1768942682 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 41816243 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 12:52:31 PM PST 24 |
| Finished | Jan 21 12:52:33 PM PST 24 |
| Peak memory | 214096 kb |
| Host | smart-cd86b214-e8b2-4e12-a540-6d6c0ce05a09 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768942682 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di sable_auto_req_mode.1768942682 |
| Directory | /workspace/8.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/8.edn_err.1303581514 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 50488020 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:52:31 PM PST 24 |
| Finished | Jan 21 12:52:33 PM PST 24 |
| Peak memory | 215304 kb |
| Host | smart-b6d27a3e-f294-4ea3-b410-6f9426e1288d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1303581514 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1303581514 |
| Directory | /workspace/8.edn_err/latest |
| Test location | /workspace/coverage/default/8.edn_genbits.1636134831 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 20877617 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 12:52:32 PM PST 24 |
| Finished | Jan 21 12:52:33 PM PST 24 |
| Peak memory | 205228 kb |
| Host | smart-65f40fee-e0c1-41f7-b456-795d371a9035 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1636134831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1636134831 |
| Directory | /workspace/8.edn_genbits/latest |
| Test location | /workspace/coverage/default/8.edn_intr.387884947 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 20143471 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 12:52:31 PM PST 24 |
| Finished | Jan 21 12:52:32 PM PST 24 |
| Peak memory | 214084 kb |
| Host | smart-a2d75e6b-0bea-4573-b709-0694a3a7d2c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=387884947 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.387884947 |
| Directory | /workspace/8.edn_intr/latest |
| Test location | /workspace/coverage/default/8.edn_regwen.2279383653 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 50804936 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 12:52:26 PM PST 24 |
| Finished | Jan 21 12:52:28 PM PST 24 |
| Peak memory | 204468 kb |
| Host | smart-2bbfae2d-7848-4229-b55c-db4945b08715 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2279383653 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2279383653 |
| Directory | /workspace/8.edn_regwen/latest |
| Test location | /workspace/coverage/default/8.edn_smoke.3493745420 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 21703532 ps |
| CPU time | 0.89 seconds |
| Started | Jan 21 12:52:25 PM PST 24 |
| Finished | Jan 21 12:52:26 PM PST 24 |
| Peak memory | 204556 kb |
| Host | smart-4189cb8c-c322-4312-99f5-562985e6ecae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3493745420 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3493745420 |
| Directory | /workspace/8.edn_smoke/latest |
| Test location | /workspace/coverage/default/8.edn_stress_all.3198338191 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 24921967 ps |
| CPU time | 1.03 seconds |
| Started | Jan 21 12:52:32 PM PST 24 |
| Finished | Jan 21 12:52:34 PM PST 24 |
| Peak memory | 204100 kb |
| Host | smart-36166cba-235b-4050-b595-90ebccb28f15 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198338191 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3198338191 |
| Directory | /workspace/8.edn_stress_all/latest |
| Test location | /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2740428429 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 128847159936 ps |
| CPU time | 2328.14 seconds |
| Started | Jan 21 12:52:32 PM PST 24 |
| Finished | Jan 21 01:31:21 PM PST 24 |
| Peak memory | 220656 kb |
| Host | smart-e16c2338-f4f1-4d8f-b7f8-32b2396cc3e5 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740428429 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2740428429 |
| Directory | /workspace/8.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/80.edn_err.3059580785 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 30570180 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 12:58:26 PM PST 24 |
| Finished | Jan 21 12:58:28 PM PST 24 |
| Peak memory | 214932 kb |
| Host | smart-5ec53c66-4849-425c-9491-0faf73cbfbd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3059580785 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3059580785 |
| Directory | /workspace/80.edn_err/latest |
| Test location | /workspace/coverage/default/80.edn_genbits.3350438894 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 392478049 ps |
| CPU time | 1.43 seconds |
| Started | Jan 21 12:58:29 PM PST 24 |
| Finished | Jan 21 12:58:32 PM PST 24 |
| Peak memory | 205292 kb |
| Host | smart-ae9d29a1-1ef0-40ad-b3b7-ced943ca966d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3350438894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3350438894 |
| Directory | /workspace/80.edn_genbits/latest |
| Test location | /workspace/coverage/default/81.edn_genbits.177048708 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 17867030 ps |
| CPU time | 1.05 seconds |
| Started | Jan 21 12:58:31 PM PST 24 |
| Finished | Jan 21 12:58:33 PM PST 24 |
| Peak memory | 205076 kb |
| Host | smart-40b17713-3e11-4d04-8556-728914a5434c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=177048708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.177048708 |
| Directory | /workspace/81.edn_genbits/latest |
| Test location | /workspace/coverage/default/82.edn_genbits.3537719766 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 14318118 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:58:38 PM PST 24 |
| Finished | Jan 21 12:58:39 PM PST 24 |
| Peak memory | 204592 kb |
| Host | smart-28be9cdd-d472-4c94-b6c3-b02b7b5f12dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3537719766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3537719766 |
| Directory | /workspace/82.edn_genbits/latest |
| Test location | /workspace/coverage/default/83.edn_err.3083864835 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 23244637 ps |
| CPU time | 0.9 seconds |
| Started | Jan 21 12:58:30 PM PST 24 |
| Finished | Jan 21 12:58:31 PM PST 24 |
| Peak memory | 214948 kb |
| Host | smart-9238c591-2e24-474a-a7b5-685d6763d224 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3083864835 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3083864835 |
| Directory | /workspace/83.edn_err/latest |
| Test location | /workspace/coverage/default/83.edn_genbits.1968661201 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 20621360 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:58:27 PM PST 24 |
| Finished | Jan 21 12:58:28 PM PST 24 |
| Peak memory | 204636 kb |
| Host | smart-2ff040aa-cc83-4bb0-a474-7e164b823546 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1968661201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1968661201 |
| Directory | /workspace/83.edn_genbits/latest |
| Test location | /workspace/coverage/default/84.edn_err.1547778443 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 77656655 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:58:35 PM PST 24 |
| Finished | Jan 21 12:58:36 PM PST 24 |
| Peak memory | 215436 kb |
| Host | smart-88d7f13f-ae48-4eb2-929e-865a811e56eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1547778443 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1547778443 |
| Directory | /workspace/84.edn_err/latest |
| Test location | /workspace/coverage/default/84.edn_genbits.996139731 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 44134499 ps |
| CPU time | 1.18 seconds |
| Started | Jan 21 12:58:35 PM PST 24 |
| Finished | Jan 21 12:58:37 PM PST 24 |
| Peak memory | 205080 kb |
| Host | smart-cdab9236-a5d6-4294-9f77-ad3bed16d43a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=996139731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.996139731 |
| Directory | /workspace/84.edn_genbits/latest |
| Test location | /workspace/coverage/default/85.edn_genbits.2181692581 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 18841329 ps |
| CPU time | 1.04 seconds |
| Started | Jan 21 12:58:39 PM PST 24 |
| Finished | Jan 21 12:58:40 PM PST 24 |
| Peak memory | 204524 kb |
| Host | smart-e6c8fec0-38eb-430c-a96f-0b64203f2ff6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2181692581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2181692581 |
| Directory | /workspace/85.edn_genbits/latest |
| Test location | /workspace/coverage/default/87.edn_err.1329402961 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 34395165 ps |
| CPU time | 1.08 seconds |
| Started | Jan 21 12:58:34 PM PST 24 |
| Finished | Jan 21 12:58:36 PM PST 24 |
| Peak memory | 221340 kb |
| Host | smart-43ce5c00-17bc-4b37-942c-76227d8248d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1329402961 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1329402961 |
| Directory | /workspace/87.edn_err/latest |
| Test location | /workspace/coverage/default/89.edn_err.3136307591 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 72971545 ps |
| CPU time | 1.03 seconds |
| Started | Jan 21 12:58:40 PM PST 24 |
| Finished | Jan 21 12:58:42 PM PST 24 |
| Peak memory | 216460 kb |
| Host | smart-54c3eaf3-0939-4d48-ad4f-61e126276f50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3136307591 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3136307591 |
| Directory | /workspace/89.edn_err/latest |
| Test location | /workspace/coverage/default/89.edn_genbits.2536949454 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 226157254 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:58:47 PM PST 24 |
| Finished | Jan 21 12:58:48 PM PST 24 |
| Peak memory | 204644 kb |
| Host | smart-0380c6bd-476c-480a-b0f4-8b8021429002 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2536949454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2536949454 |
| Directory | /workspace/89.edn_genbits/latest |
| Test location | /workspace/coverage/default/9.edn_alert.2858431639 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 20174354 ps |
| CPU time | 1.04 seconds |
| Started | Jan 21 12:52:39 PM PST 24 |
| Finished | Jan 21 12:52:41 PM PST 24 |
| Peak memory | 204624 kb |
| Host | smart-8f06e0be-4eec-4177-8ec1-94bfb540b115 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2858431639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.2858431639 |
| Directory | /workspace/9.edn_alert/latest |
| Test location | /workspace/coverage/default/9.edn_alert_test.2342724057 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 31344380 ps |
| CPU time | 1.01 seconds |
| Started | Jan 21 12:52:42 PM PST 24 |
| Finished | Jan 21 12:52:44 PM PST 24 |
| Peak memory | 204188 kb |
| Host | smart-6048c38a-cf57-4eb7-b34e-074745c40a93 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342724057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2342724057 |
| Directory | /workspace/9.edn_alert_test/latest |
| Test location | /workspace/coverage/default/9.edn_disable.1684315315 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 21829062 ps |
| CPU time | 0.84 seconds |
| Started | Jan 21 12:52:40 PM PST 24 |
| Finished | Jan 21 12:52:41 PM PST 24 |
| Peak memory | 213972 kb |
| Host | smart-1f77a22a-7bb4-4e75-afc2-3fcbf0f4d5d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684315315 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1684315315 |
| Directory | /workspace/9.edn_disable/latest |
| Test location | /workspace/coverage/default/9.edn_disable_auto_req_mode.2216533243 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 23716832 ps |
| CPU time | 1.04 seconds |
| Started | Jan 21 12:52:39 PM PST 24 |
| Finished | Jan 21 12:52:41 PM PST 24 |
| Peak memory | 215180 kb |
| Host | smart-815987dc-cc38-4e2e-88bf-1cb574518f74 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216533243 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di sable_auto_req_mode.2216533243 |
| Directory | /workspace/9.edn_disable_auto_req_mode/latest |
| Test location | /workspace/coverage/default/9.edn_err.1796951390 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 23323532 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:52:42 PM PST 24 |
| Finished | Jan 21 12:52:43 PM PST 24 |
| Peak memory | 215220 kb |
| Host | smart-a12e6ac6-18e9-4383-ac4f-b82dcbffb3c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1796951390 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1796951390 |
| Directory | /workspace/9.edn_err/latest |
| Test location | /workspace/coverage/default/9.edn_genbits.2079976646 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 33568330 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 12:52:41 PM PST 24 |
| Finished | Jan 21 12:52:43 PM PST 24 |
| Peak memory | 213808 kb |
| Host | smart-9ed4f582-d64b-4fc3-a5c9-2972efad15d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2079976646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2079976646 |
| Directory | /workspace/9.edn_genbits/latest |
| Test location | /workspace/coverage/default/9.edn_intr.1936299890 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 24143711 ps |
| CPU time | 0.92 seconds |
| Started | Jan 21 12:52:40 PM PST 24 |
| Finished | Jan 21 12:52:42 PM PST 24 |
| Peak memory | 214008 kb |
| Host | smart-ba39de94-c549-443d-b099-22079917559e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1936299890 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1936299890 |
| Directory | /workspace/9.edn_intr/latest |
| Test location | /workspace/coverage/default/9.edn_regwen.1426869993 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 47852027 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:52:40 PM PST 24 |
| Finished | Jan 21 12:52:42 PM PST 24 |
| Peak memory | 204536 kb |
| Host | smart-5b516081-c517-4ae8-8704-4b8016e86000 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1426869993 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1426869993 |
| Directory | /workspace/9.edn_regwen/latest |
| Test location | /workspace/coverage/default/9.edn_smoke.1333007450 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 33558786 ps |
| CPU time | 0.78 seconds |
| Started | Jan 21 12:52:30 PM PST 24 |
| Finished | Jan 21 12:52:31 PM PST 24 |
| Peak memory | 204168 kb |
| Host | smart-cf9723a8-f37c-4a67-bcd1-ffead5b80c51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1333007450 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1333007450 |
| Directory | /workspace/9.edn_smoke/latest |
| Test location | /workspace/coverage/default/9.edn_stress_all.3070225969 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 152100713 ps |
| CPU time | 3.61 seconds |
| Started | Jan 21 12:52:43 PM PST 24 |
| Finished | Jan 21 12:52:47 PM PST 24 |
| Peak memory | 205572 kb |
| Host | smart-e5bce32b-afa2-4037-98ac-1035bd1f9295 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070225969 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3070225969 |
| Directory | /workspace/9.edn_stress_all/latest |
| Test location | /workspace/coverage/default/9.edn_stress_all_with_rand_reset.4203397777 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 30630879598 ps |
| CPU time | 679.66 seconds |
| Started | Jan 21 12:52:40 PM PST 24 |
| Finished | Jan 21 01:04:00 PM PST 24 |
| Peak memory | 215232 kb |
| Host | smart-4d6c0c3d-d4a7-477a-ba09-301a66f035db |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203397777 -assert nopostpr oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.4203397777 |
| Directory | /workspace/9.edn_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/90.edn_err.4287311538 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 41268768 ps |
| CPU time | 0.82 seconds |
| Started | Jan 21 12:58:36 PM PST 24 |
| Finished | Jan 21 12:58:37 PM PST 24 |
| Peak memory | 215004 kb |
| Host | smart-9d565e06-8935-4183-8172-8d3bca4e7bc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4287311538 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.4287311538 |
| Directory | /workspace/90.edn_err/latest |
| Test location | /workspace/coverage/default/90.edn_genbits.815966050 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 16781817 ps |
| CPU time | 0.96 seconds |
| Started | Jan 21 12:58:47 PM PST 24 |
| Finished | Jan 21 12:58:48 PM PST 24 |
| Peak memory | 204928 kb |
| Host | smart-ff0c1f07-041c-44e3-a85b-1e7e5c14fb41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=815966050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.815966050 |
| Directory | /workspace/90.edn_genbits/latest |
| Test location | /workspace/coverage/default/91.edn_genbits.688927823 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 29449163 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:58:39 PM PST 24 |
| Finished | Jan 21 12:58:40 PM PST 24 |
| Peak memory | 204868 kb |
| Host | smart-a5d09fe7-a174-4828-89c3-344e1c645b09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=688927823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.688927823 |
| Directory | /workspace/91.edn_genbits/latest |
| Test location | /workspace/coverage/default/92.edn_err.2911559344 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 34267325 ps |
| CPU time | 0.91 seconds |
| Started | Jan 21 12:58:40 PM PST 24 |
| Finished | Jan 21 12:58:42 PM PST 24 |
| Peak memory | 214796 kb |
| Host | smart-423be75a-e598-41de-a569-45e5d2029d62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2911559344 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2911559344 |
| Directory | /workspace/92.edn_err/latest |
| Test location | /workspace/coverage/default/93.edn_err.3332107872 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 21894498 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 01:19:13 PM PST 24 |
| Finished | Jan 21 01:19:17 PM PST 24 |
| Peak memory | 220920 kb |
| Host | smart-40f2ff9b-ec62-4fc8-90b4-7772d248f366 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3332107872 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3332107872 |
| Directory | /workspace/93.edn_err/latest |
| Test location | /workspace/coverage/default/93.edn_genbits.497062618 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 34829389 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 12:58:46 PM PST 24 |
| Finished | Jan 21 12:58:47 PM PST 24 |
| Peak memory | 205584 kb |
| Host | smart-f21786b7-8a2c-45ab-bc76-785539b1a5b3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=497062618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.497062618 |
| Directory | /workspace/93.edn_genbits/latest |
| Test location | /workspace/coverage/default/94.edn_err.2880715794 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 17930998 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:58:47 PM PST 24 |
| Finished | Jan 21 12:58:48 PM PST 24 |
| Peak memory | 215020 kb |
| Host | smart-1cd14e2a-2299-4053-b654-02ddb589c99c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2880715794 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2880715794 |
| Directory | /workspace/94.edn_err/latest |
| Test location | /workspace/coverage/default/95.edn_err.4154211079 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 20618920 ps |
| CPU time | 0.88 seconds |
| Started | Jan 21 12:58:46 PM PST 24 |
| Finished | Jan 21 12:58:48 PM PST 24 |
| Peak memory | 214792 kb |
| Host | smart-7aba1c66-fc61-46f4-b8ac-5ab9a5598386 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4154211079 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.4154211079 |
| Directory | /workspace/95.edn_err/latest |
| Test location | /workspace/coverage/default/96.edn_err.1897439055 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 18175055 ps |
| CPU time | 1.05 seconds |
| Started | Jan 21 12:58:45 PM PST 24 |
| Finished | Jan 21 12:58:47 PM PST 24 |
| Peak memory | 215136 kb |
| Host | smart-9e9a2575-66b8-4b6d-baaf-1df12f782e09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1897439055 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1897439055 |
| Directory | /workspace/96.edn_err/latest |
| Test location | /workspace/coverage/default/96.edn_genbits.2203910527 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 32083843 ps |
| CPU time | 1.02 seconds |
| Started | Jan 21 12:58:45 PM PST 24 |
| Finished | Jan 21 12:58:47 PM PST 24 |
| Peak memory | 204836 kb |
| Host | smart-c0522848-0082-4e09-a56b-b3084c920077 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2203910527 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2203910527 |
| Directory | /workspace/96.edn_genbits/latest |
| Test location | /workspace/coverage/default/97.edn_err.2624427259 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 199961878 ps |
| CPU time | 1.09 seconds |
| Started | Jan 21 12:58:54 PM PST 24 |
| Finished | Jan 21 12:58:56 PM PST 24 |
| Peak memory | 221224 kb |
| Host | smart-0f3ae3ac-bd07-420a-860c-9168c131007d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2624427259 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2624427259 |
| Directory | /workspace/97.edn_err/latest |
| Test location | /workspace/coverage/default/97.edn_genbits.883061480 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 33078652 ps |
| CPU time | 1.09 seconds |
| Started | Jan 21 12:58:47 PM PST 24 |
| Finished | Jan 21 12:58:49 PM PST 24 |
| Peak memory | 204780 kb |
| Host | smart-1aedaadc-e706-460f-8c4a-5e977fd2a59c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=883061480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.883061480 |
| Directory | /workspace/97.edn_genbits/latest |
| Test location | /workspace/coverage/default/98.edn_err.4113225147 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 20375078 ps |
| CPU time | 1.07 seconds |
| Started | Jan 21 12:58:57 PM PST 24 |
| Finished | Jan 21 12:58:59 PM PST 24 |
| Peak memory | 215004 kb |
| Host | smart-baff53f2-b2c7-49ff-9e4f-86761f639b43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4113225147 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.4113225147 |
| Directory | /workspace/98.edn_err/latest |
| Test location | /workspace/coverage/default/98.edn_genbits.762093124 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 30953314 ps |
| CPU time | 1.17 seconds |
| Started | Jan 21 12:58:53 PM PST 24 |
| Finished | Jan 21 12:58:54 PM PST 24 |
| Peak memory | 205432 kb |
| Host | smart-cb19feb9-39fa-4ad0-abff-fe3d0784f499 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=762093124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.762093124 |
| Directory | /workspace/98.edn_genbits/latest |
| Test location | /workspace/coverage/default/99.edn_err.1708647357 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 41918533 ps |
| CPU time | 1.04 seconds |
| Started | Jan 21 12:58:57 PM PST 24 |
| Finished | Jan 21 12:58:59 PM PST 24 |
| Peak memory | 216460 kb |
| Host | smart-6cfe22e3-4580-424a-9a51-ed36ee0d4184 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1708647357 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1708647357 |
| Directory | /workspace/99.edn_err/latest |
| Test location | /workspace/coverage/default/99.edn_genbits.4631939 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 48922025 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 12:58:55 PM PST 24 |
| Finished | Jan 21 12:58:57 PM PST 24 |
| Peak memory | 213664 kb |
| Host | smart-65c07686-99a8-4f9c-8091-4d95cf320cbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4631939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.4631939 |
| Directory | /workspace/99.edn_genbits/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |