Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.65 98.70 91.81 96.79 89.24 97.62 96.60 98.78


Total test records in report: 954
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T765 /workspace/coverage/default/86.edn_genbits.481365219 Jan 24 07:43:03 PM PST 24 Jan 24 07:43:06 PM PST 24 42084099 ps
T766 /workspace/coverage/default/38.edn_genbits.4033679184 Jan 24 07:40:09 PM PST 24 Jan 24 07:40:12 PM PST 24 29281635 ps
T767 /workspace/coverage/default/31.edn_stress_all.3321381852 Jan 24 07:53:16 PM PST 24 Jan 24 07:53:20 PM PST 24 289023848 ps
T768 /workspace/coverage/default/12.edn_smoke.2820084682 Jan 24 07:37:03 PM PST 24 Jan 24 07:37:04 PM PST 24 37229684 ps
T769 /workspace/coverage/default/270.edn_genbits.374189079 Jan 24 07:45:04 PM PST 24 Jan 24 07:45:08 PM PST 24 35130517 ps
T770 /workspace/coverage/default/14.edn_genbits.2489336664 Jan 24 07:37:25 PM PST 24 Jan 24 07:37:27 PM PST 24 36672364 ps
T771 /workspace/coverage/default/4.edn_disable_auto_req_mode.3850715011 Jan 24 07:36:17 PM PST 24 Jan 24 07:36:22 PM PST 24 36463821 ps
T250 /workspace/coverage/default/38.edn_alert.22447841 Jan 24 07:40:22 PM PST 24 Jan 24 07:40:24 PM PST 24 31664943 ps
T772 /workspace/coverage/default/29.edn_stress_all.757734258 Jan 24 07:39:10 PM PST 24 Jan 24 07:39:14 PM PST 24 678378980 ps
T773 /workspace/coverage/default/144.edn_genbits.2990785814 Jan 24 07:43:34 PM PST 24 Jan 24 07:43:36 PM PST 24 23037665 ps
T774 /workspace/coverage/default/250.edn_genbits.3476337378 Jan 24 07:44:47 PM PST 24 Jan 24 07:44:52 PM PST 24 14382205 ps
T244 /workspace/coverage/default/6.edn_regwen.107218837 Jan 24 08:19:10 PM PST 24 Jan 24 08:19:14 PM PST 24 12725337 ps
T775 /workspace/coverage/default/286.edn_genbits.852955073 Jan 24 07:45:05 PM PST 24 Jan 24 07:45:09 PM PST 24 60659121 ps
T776 /workspace/coverage/default/46.edn_alert.1223144820 Jan 24 07:41:23 PM PST 24 Jan 24 07:41:25 PM PST 24 20813643 ps
T777 /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3506630729 Jan 24 07:38:50 PM PST 24 Jan 24 07:45:45 PM PST 24 37022268808 ps
T778 /workspace/coverage/default/6.edn_stress_all_with_rand_reset.231823534 Jan 24 07:36:29 PM PST 24 Jan 24 07:58:06 PM PST 24 52218684179 ps
T779 /workspace/coverage/default/214.edn_genbits.1123761922 Jan 24 07:44:27 PM PST 24 Jan 24 07:44:32 PM PST 24 308984256 ps
T780 /workspace/coverage/default/39.edn_genbits.614902216 Jan 24 07:40:36 PM PST 24 Jan 24 07:40:38 PM PST 24 24805587 ps
T781 /workspace/coverage/default/105.edn_genbits.2994156485 Jan 24 10:12:17 PM PST 24 Jan 24 10:12:19 PM PST 24 18666919 ps
T782 /workspace/coverage/default/158.edn_genbits.993653059 Jan 24 07:43:51 PM PST 24 Jan 24 07:43:52 PM PST 24 17704069 ps
T783 /workspace/coverage/default/5.edn_genbits.2045239403 Jan 24 07:36:16 PM PST 24 Jan 24 07:36:21 PM PST 24 38998153 ps
T784 /workspace/coverage/default/34.edn_err.3639919472 Jan 24 07:39:52 PM PST 24 Jan 24 07:39:55 PM PST 24 61701769 ps
T785 /workspace/coverage/default/24.edn_disable.139287923 Jan 24 07:38:47 PM PST 24 Jan 24 07:38:57 PM PST 24 18003998 ps
T786 /workspace/coverage/default/65.edn_err.2042023091 Jan 24 07:42:14 PM PST 24 Jan 24 07:42:18 PM PST 24 24291548 ps
T787 /workspace/coverage/default/244.edn_genbits.692644847 Jan 24 07:44:49 PM PST 24 Jan 24 07:44:53 PM PST 24 18622709 ps
T788 /workspace/coverage/default/42.edn_alert_test.1303080123 Jan 24 07:41:00 PM PST 24 Jan 24 07:41:02 PM PST 24 16890309 ps
T789 /workspace/coverage/default/193.edn_genbits.3490413342 Jan 24 07:44:09 PM PST 24 Jan 24 07:44:11 PM PST 24 14546518 ps
T790 /workspace/coverage/default/45.edn_stress_all.3869994023 Jan 24 07:41:23 PM PST 24 Jan 24 07:41:25 PM PST 24 28259055 ps
T791 /workspace/coverage/default/42.edn_smoke.158716662 Jan 24 07:40:45 PM PST 24 Jan 24 07:40:46 PM PST 24 133434653 ps
T792 /workspace/coverage/default/59.edn_err.1418827349 Jan 24 08:14:42 PM PST 24 Jan 24 08:14:48 PM PST 24 56910810 ps
T793 /workspace/coverage/default/14.edn_intr.3286531426 Jan 24 07:37:25 PM PST 24 Jan 24 07:37:27 PM PST 24 22059857 ps
T794 /workspace/coverage/default/147.edn_genbits.3164406625 Jan 24 07:43:41 PM PST 24 Jan 24 07:43:43 PM PST 24 251766150 ps
T795 /workspace/coverage/default/18.edn_intr.1618216644 Jan 24 07:37:50 PM PST 24 Jan 24 07:37:52 PM PST 24 23347343 ps
T796 /workspace/coverage/default/298.edn_genbits.4174420324 Jan 24 07:45:23 PM PST 24 Jan 24 07:45:29 PM PST 24 175420358 ps
T797 /workspace/coverage/default/255.edn_genbits.799464051 Jan 24 07:44:58 PM PST 24 Jan 24 07:45:03 PM PST 24 23059820 ps
T798 /workspace/coverage/default/23.edn_err.515555785 Jan 24 07:38:25 PM PST 24 Jan 24 07:38:32 PM PST 24 19131906 ps
T799 /workspace/coverage/default/13.edn_err.3171899668 Jan 24 07:37:18 PM PST 24 Jan 24 07:37:19 PM PST 24 24114659 ps
T800 /workspace/coverage/default/40.edn_genbits.111979827 Jan 24 07:40:40 PM PST 24 Jan 24 07:40:51 PM PST 24 1331772404 ps
T801 /workspace/coverage/default/40.edn_intr.1685847896 Jan 24 07:40:47 PM PST 24 Jan 24 07:40:50 PM PST 24 19191313 ps
T802 /workspace/coverage/default/31.edn_err.3137148950 Jan 24 07:39:26 PM PST 24 Jan 24 07:39:28 PM PST 24 75620918 ps
T803 /workspace/coverage/default/41.edn_alert.50653986 Jan 24 07:40:44 PM PST 24 Jan 24 07:40:46 PM PST 24 48282752 ps
T804 /workspace/coverage/default/76.edn_genbits.1198292181 Jan 24 07:42:31 PM PST 24 Jan 24 07:42:34 PM PST 24 16093312 ps
T805 /workspace/coverage/default/39.edn_disable_auto_req_mode.3658637494 Jan 24 09:22:32 PM PST 24 Jan 24 09:22:34 PM PST 24 84504889 ps
T806 /workspace/coverage/default/26.edn_intr.3821599584 Jan 24 08:02:14 PM PST 24 Jan 24 08:02:17 PM PST 24 23516465 ps
T807 /workspace/coverage/default/9.edn_disable_auto_req_mode.1272764209 Jan 24 07:45:42 PM PST 24 Jan 24 07:45:44 PM PST 24 44438979 ps
T808 /workspace/coverage/default/8.edn_smoke.3371772319 Jan 24 07:36:28 PM PST 24 Jan 24 07:36:31 PM PST 24 17109210 ps
T809 /workspace/coverage/default/149.edn_genbits.1521432167 Jan 24 07:43:42 PM PST 24 Jan 24 07:43:45 PM PST 24 68179193 ps
T810 /workspace/coverage/default/219.edn_genbits.3989977867 Jan 24 07:44:33 PM PST 24 Jan 24 07:44:36 PM PST 24 86773984 ps
T811 /workspace/coverage/default/181.edn_genbits.3077743607 Jan 24 07:44:05 PM PST 24 Jan 24 07:44:07 PM PST 24 96871838 ps
T812 /workspace/coverage/default/29.edn_smoke.349306220 Jan 24 07:39:11 PM PST 24 Jan 24 07:39:14 PM PST 24 22468371 ps
T813 /workspace/coverage/default/285.edn_genbits.3506311259 Jan 24 07:45:05 PM PST 24 Jan 24 07:45:08 PM PST 24 23508152 ps
T139 /workspace/coverage/default/39.edn_disable.3812049579 Jan 24 07:40:40 PM PST 24 Jan 24 07:40:42 PM PST 24 12199445 ps
T263 /workspace/coverage/default/251.edn_genbits.2727078895 Jan 24 07:44:55 PM PST 24 Jan 24 07:44:57 PM PST 24 16388619 ps
T67 /workspace/coverage/default/2.edn_sec_cm.2777645550 Jan 24 08:00:47 PM PST 24 Jan 24 08:00:54 PM PST 24 1345025978 ps
T814 /workspace/coverage/default/226.edn_genbits.2115997943 Jan 24 07:44:32 PM PST 24 Jan 24 07:44:39 PM PST 24 637343639 ps
T815 /workspace/coverage/default/20.edn_err.1342085584 Jan 24 07:38:13 PM PST 24 Jan 24 07:38:16 PM PST 24 261294136 ps
T816 /workspace/coverage/default/130.edn_genbits.2639194530 Jan 24 07:43:24 PM PST 24 Jan 24 07:43:26 PM PST 24 37709719 ps
T817 /workspace/coverage/default/39.edn_intr.1488483810 Jan 24 07:40:33 PM PST 24 Jan 24 07:40:35 PM PST 24 34575451 ps
T818 /workspace/coverage/default/67.edn_genbits.544214164 Jan 24 07:49:14 PM PST 24 Jan 24 07:49:17 PM PST 24 54329404 ps
T819 /workspace/coverage/default/10.edn_err.1142746518 Jan 24 07:36:52 PM PST 24 Jan 24 07:36:55 PM PST 24 35960176 ps
T820 /workspace/coverage/default/28.edn_stress_all_with_rand_reset.73081984 Jan 24 07:39:09 PM PST 24 Jan 24 08:02:01 PM PST 24 801492782506 ps
T821 /workspace/coverage/default/1.edn_alert.1218032450 Jan 24 07:35:54 PM PST 24 Jan 24 07:35:59 PM PST 24 18921188 ps
T822 /workspace/coverage/default/5.edn_intr.3534049231 Jan 24 07:36:15 PM PST 24 Jan 24 07:36:19 PM PST 24 36991999 ps
T823 /workspace/coverage/default/14.edn_stress_all.2877180687 Jan 24 07:37:14 PM PST 24 Jan 24 07:37:17 PM PST 24 116726192 ps
T824 /workspace/coverage/default/5.edn_smoke.2107962017 Jan 24 07:36:18 PM PST 24 Jan 24 07:36:23 PM PST 24 11498296 ps
T825 /workspace/coverage/default/282.edn_genbits.364790683 Jan 24 10:14:43 PM PST 24 Jan 24 10:14:46 PM PST 24 33308461 ps
T826 /workspace/coverage/default/41.edn_disable.735858654 Jan 24 07:40:49 PM PST 24 Jan 24 07:40:51 PM PST 24 75318672 ps
T827 /workspace/coverage/default/17.edn_disable.4029110577 Jan 24 07:37:50 PM PST 24 Jan 24 07:37:53 PM PST 24 51531792 ps
T828 /workspace/coverage/default/27.edn_stress_all.1577586062 Jan 24 07:39:03 PM PST 24 Jan 24 07:39:09 PM PST 24 96256082 ps
T829 /workspace/coverage/default/19.edn_disable_auto_req_mode.784493253 Jan 24 07:38:06 PM PST 24 Jan 24 07:38:08 PM PST 24 91077194 ps
T830 /workspace/coverage/default/116.edn_genbits.1539423078 Jan 24 07:43:11 PM PST 24 Jan 24 07:43:14 PM PST 24 28298776 ps
T831 /workspace/coverage/default/26.edn_stress_all.3449738868 Jan 24 07:38:50 PM PST 24 Jan 24 07:38:59 PM PST 24 107353882 ps
T832 /workspace/coverage/default/101.edn_genbits.885799480 Jan 24 07:43:03 PM PST 24 Jan 24 07:43:07 PM PST 24 25026216 ps
T833 /workspace/coverage/default/0.edn_disable_auto_req_mode.524734346 Jan 24 10:48:43 PM PST 24 Jan 24 10:48:45 PM PST 24 45745495 ps
T834 /workspace/coverage/default/85.edn_genbits.709318715 Jan 24 08:03:08 PM PST 24 Jan 24 08:03:18 PM PST 24 45132011 ps
T835 /workspace/coverage/default/42.edn_disable_auto_req_mode.2396771029 Jan 24 07:41:01 PM PST 24 Jan 24 07:41:04 PM PST 24 41747346 ps
T836 /workspace/coverage/default/53.edn_genbits.505397516 Jan 24 07:46:30 PM PST 24 Jan 24 07:46:31 PM PST 24 17932736 ps
T144 /workspace/coverage/default/46.edn_disable.1628143367 Jan 24 07:41:31 PM PST 24 Jan 24 07:41:33 PM PST 24 21221107 ps
T837 /workspace/coverage/default/13.edn_stress_all.151667715 Jan 24 07:37:18 PM PST 24 Jan 24 07:37:22 PM PST 24 1603657853 ps
T838 /workspace/coverage/default/288.edn_genbits.639638425 Jan 24 07:45:14 PM PST 24 Jan 24 07:45:16 PM PST 24 25477156 ps
T839 /workspace/coverage/default/18.edn_err.4201900348 Jan 24 07:38:01 PM PST 24 Jan 24 07:38:03 PM PST 24 18218417 ps
T840 /workspace/coverage/default/20.edn_stress_all_with_rand_reset.297717560 Jan 24 09:56:54 PM PST 24 Jan 24 10:10:47 PM PST 24 65675471072 ps
T841 /workspace/coverage/default/39.edn_smoke.4292930096 Jan 24 07:40:30 PM PST 24 Jan 24 07:40:32 PM PST 24 35301467 ps
T842 /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3594456432 Jan 24 07:40:47 PM PST 24 Jan 24 08:04:23 PM PST 24 149419358672 ps
T843 /workspace/coverage/default/10.edn_genbits.3838134696 Jan 24 09:21:51 PM PST 24 Jan 24 09:22:00 PM PST 24 533477305 ps
T844 /workspace/coverage/default/37.edn_genbits.3661017570 Jan 24 07:40:01 PM PST 24 Jan 24 07:40:04 PM PST 24 89967791 ps
T845 /workspace/coverage/default/264.edn_genbits.2734480740 Jan 24 07:45:05 PM PST 24 Jan 24 07:45:08 PM PST 24 85168495 ps
T846 /workspace/coverage/default/5.edn_alert.2469731706 Jan 24 07:36:25 PM PST 24 Jan 24 07:36:28 PM PST 24 103879883 ps
T847 /workspace/coverage/default/90.edn_err.1859659501 Jan 24 07:43:03 PM PST 24 Jan 24 07:43:06 PM PST 24 20004532 ps
T848 /workspace/coverage/default/96.edn_err.2197995291 Jan 24 07:43:05 PM PST 24 Jan 24 07:43:09 PM PST 24 29516942 ps
T849 /workspace/coverage/default/4.edn_stress_all.114044138 Jan 24 07:36:15 PM PST 24 Jan 24 07:36:22 PM PST 24 748303755 ps
T270 /workspace/coverage/default/133.edn_genbits.733744118 Jan 24 08:45:18 PM PST 24 Jan 24 08:45:22 PM PST 24 99412903 ps
T850 /workspace/coverage/default/71.edn_genbits.2023220302 Jan 24 07:42:26 PM PST 24 Jan 24 07:42:28 PM PST 24 26333086 ps
T851 /workspace/coverage/default/9.edn_alert.3905088990 Jan 24 07:36:53 PM PST 24 Jan 24 07:36:55 PM PST 24 69196354 ps
T852 /workspace/coverage/default/202.edn_genbits.3432076060 Jan 24 07:59:48 PM PST 24 Jan 24 07:59:53 PM PST 24 310106333 ps
T853 /workspace/coverage/default/49.edn_intr.2247254461 Jan 24 07:41:53 PM PST 24 Jan 24 07:41:59 PM PST 24 24667242 ps
T280 /workspace/coverage/default/54.edn_genbits.1438647229 Jan 24 07:42:04 PM PST 24 Jan 24 07:42:11 PM PST 24 85918566 ps
T854 /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1522321349 Jan 24 07:39:52 PM PST 24 Jan 24 08:18:03 PM PST 24 216555590461 ps
T855 /workspace/coverage/default/7.edn_disable.3044736862 Jan 24 07:36:31 PM PST 24 Jan 24 07:36:33 PM PST 24 36529130 ps
T856 /workspace/coverage/default/48.edn_disable.510561090 Jan 24 07:41:44 PM PST 24 Jan 24 07:41:47 PM PST 24 27307815 ps
T857 /workspace/coverage/default/109.edn_genbits.107267052 Jan 24 07:43:12 PM PST 24 Jan 24 07:43:14 PM PST 24 21965456 ps
T274 /workspace/coverage/default/177.edn_genbits.2782372682 Jan 24 07:44:00 PM PST 24 Jan 24 07:44:02 PM PST 24 75151058 ps
T858 /workspace/coverage/default/91.edn_genbits.3221789808 Jan 24 07:42:59 PM PST 24 Jan 24 07:43:02 PM PST 24 83776531 ps
T859 /workspace/coverage/default/243.edn_genbits.1755726522 Jan 24 07:44:50 PM PST 24 Jan 24 07:44:54 PM PST 24 49900871 ps
T860 /workspace/coverage/default/169.edn_genbits.4195476158 Jan 24 07:44:00 PM PST 24 Jan 24 07:44:02 PM PST 24 48418355 ps
T861 /workspace/coverage/default/44.edn_intr.1721235819 Jan 24 07:41:07 PM PST 24 Jan 24 07:41:09 PM PST 24 18764532 ps
T862 /workspace/coverage/default/278.edn_genbits.1430278180 Jan 24 07:45:05 PM PST 24 Jan 24 07:45:08 PM PST 24 27578509 ps
T863 /workspace/coverage/default/26.edn_disable.1112739820 Jan 24 07:38:52 PM PST 24 Jan 24 07:39:00 PM PST 24 29070215 ps
T864 /workspace/coverage/default/1.edn_smoke.4082571074 Jan 24 07:35:38 PM PST 24 Jan 24 07:35:42 PM PST 24 27017819 ps
T865 /workspace/coverage/default/39.edn_alert.1506076447 Jan 24 07:40:37 PM PST 24 Jan 24 07:40:39 PM PST 24 70022984 ps
T866 /workspace/coverage/default/112.edn_genbits.1822829682 Jan 25 02:13:13 AM PST 24 Jan 25 02:13:15 AM PST 24 19600979 ps
T867 /workspace/coverage/default/17.edn_disable_auto_req_mode.3839647880 Jan 24 07:37:49 PM PST 24 Jan 24 07:37:52 PM PST 24 43113838 ps
T868 /workspace/coverage/default/7.edn_intr.3474696903 Jan 24 07:36:32 PM PST 24 Jan 24 07:36:36 PM PST 24 20952003 ps
T869 /workspace/coverage/default/253.edn_genbits.4061614556 Jan 24 07:45:03 PM PST 24 Jan 24 07:45:07 PM PST 24 15278099 ps
T275 /workspace/coverage/default/11.edn_genbits.1999131471 Jan 24 07:37:04 PM PST 24 Jan 24 07:37:06 PM PST 24 19875488 ps
T870 /workspace/coverage/default/27.edn_disable_auto_req_mode.3846372874 Jan 24 07:38:58 PM PST 24 Jan 24 07:39:04 PM PST 24 24071390 ps
T871 /workspace/coverage/default/110.edn_genbits.1508914514 Jan 24 07:43:13 PM PST 24 Jan 24 07:43:15 PM PST 24 26698419 ps
T872 /workspace/coverage/default/43.edn_smoke.3747960368 Jan 24 07:41:09 PM PST 24 Jan 24 07:41:11 PM PST 24 44499574 ps
T873 /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1792107250 Jan 24 07:37:23 PM PST 24 Jan 24 07:48:29 PM PST 24 61679633421 ps
T874 /workspace/coverage/default/30.edn_intr.3416598080 Jan 24 08:16:24 PM PST 24 Jan 24 08:16:27 PM PST 24 18703688 ps
T875 /workspace/coverage/default/45.edn_alert.4266868289 Jan 24 07:41:23 PM PST 24 Jan 24 07:41:25 PM PST 24 90967048 ps
T876 /workspace/coverage/default/247.edn_genbits.1483883228 Jan 24 07:44:50 PM PST 24 Jan 24 07:44:53 PM PST 24 41403899 ps
T877 /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2430034910 Jan 24 07:39:52 PM PST 24 Jan 24 07:51:00 PM PST 24 26798487574 ps
T878 /workspace/coverage/default/23.edn_intr.2246323408 Jan 24 07:38:18 PM PST 24 Jan 24 07:38:20 PM PST 24 25778544 ps
T879 /workspace/coverage/default/30.edn_disable.2036039007 Jan 24 07:51:01 PM PST 24 Jan 24 07:51:04 PM PST 24 58475577 ps
T880 /workspace/coverage/default/38.edn_smoke.2853142650 Jan 24 07:40:12 PM PST 24 Jan 24 07:40:14 PM PST 24 20506421 ps
T881 /workspace/coverage/default/25.edn_alert_test.1117338443 Jan 24 07:38:42 PM PST 24 Jan 24 07:38:52 PM PST 24 27790037 ps
T882 /workspace/coverage/default/34.edn_alert_test.3734860718 Jan 24 07:39:50 PM PST 24 Jan 24 07:39:52 PM PST 24 189091801 ps
T883 /workspace/coverage/default/46.edn_genbits.2437448982 Jan 24 07:41:23 PM PST 24 Jan 24 07:41:26 PM PST 24 20237492 ps
T884 /workspace/coverage/default/242.edn_genbits.1671010686 Jan 24 07:44:47 PM PST 24 Jan 24 07:44:52 PM PST 24 26672495 ps
T255 /workspace/coverage/default/23.edn_alert.3488069826 Jan 24 07:38:20 PM PST 24 Jan 24 07:38:22 PM PST 24 24856031 ps
T885 /workspace/coverage/default/168.edn_genbits.1806759982 Jan 24 07:44:05 PM PST 24 Jan 24 07:44:07 PM PST 24 38251460 ps
T886 /workspace/coverage/default/31.edn_smoke.2217006379 Jan 24 07:39:17 PM PST 24 Jan 24 07:39:19 PM PST 24 130031132 ps
T887 /workspace/coverage/default/14.edn_alert.3471329351 Jan 24 07:37:26 PM PST 24 Jan 24 07:37:28 PM PST 24 19521487 ps
T888 /workspace/coverage/default/249.edn_genbits.4161022142 Jan 24 07:44:49 PM PST 24 Jan 24 07:44:54 PM PST 24 74323088 ps
T889 /workspace/coverage/default/26.edn_alert_test.525574561 Jan 24 07:38:58 PM PST 24 Jan 24 07:39:04 PM PST 24 28370251 ps
T890 /workspace/coverage/default/120.edn_genbits.2442558684 Jan 24 07:43:22 PM PST 24 Jan 24 07:43:24 PM PST 24 42352407 ps
T891 /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1305152938 Jan 24 07:38:23 PM PST 24 Jan 24 07:59:19 PM PST 24 49417956114 ps
T892 /workspace/coverage/default/18.edn_genbits.3876640972 Jan 24 10:03:41 PM PST 24 Jan 24 10:03:43 PM PST 24 54772695 ps
T893 /workspace/coverage/default/31.edn_genbits.3874216586 Jan 24 07:39:12 PM PST 24 Jan 24 07:39:14 PM PST 24 44301415 ps
T132 /workspace/coverage/default/19.edn_disable.801852809 Jan 24 07:38:09 PM PST 24 Jan 24 07:38:12 PM PST 24 10826050 ps
T894 /workspace/coverage/default/211.edn_genbits.328800058 Jan 24 07:44:27 PM PST 24 Jan 24 07:44:28 PM PST 24 17841411 ps
T895 /workspace/coverage/default/68.edn_genbits.193796635 Jan 24 07:42:18 PM PST 24 Jan 24 07:42:20 PM PST 24 52983367 ps
T896 /workspace/coverage/default/43.edn_genbits.2576299944 Jan 24 07:41:02 PM PST 24 Jan 24 07:41:05 PM PST 24 17593400 ps
T897 /workspace/coverage/default/28.edn_stress_all.2718314370 Jan 24 07:39:12 PM PST 24 Jan 24 07:39:16 PM PST 24 92529883 ps
T898 /workspace/coverage/default/3.edn_alert_test.4100907017 Jan 24 07:36:09 PM PST 24 Jan 24 07:36:13 PM PST 24 40668390 ps
T899 /workspace/coverage/default/33.edn_intr.2178352080 Jan 24 07:39:52 PM PST 24 Jan 24 07:39:54 PM PST 24 99737482 ps
T900 /workspace/coverage/default/35.edn_stress_all.1260845006 Jan 24 07:39:52 PM PST 24 Jan 24 07:39:55 PM PST 24 75943430 ps
T901 /workspace/coverage/default/23.edn_smoke.3242924189 Jan 24 08:38:26 PM PST 24 Jan 24 08:38:28 PM PST 24 24546640 ps
T902 /workspace/coverage/default/266.edn_genbits.2843642627 Jan 24 07:45:03 PM PST 24 Jan 24 07:45:07 PM PST 24 130885717 ps
T903 /workspace/coverage/default/262.edn_genbits.626329709 Jan 24 07:44:57 PM PST 24 Jan 24 07:45:03 PM PST 24 39216735 ps
T904 /workspace/coverage/default/17.edn_genbits.2261508958 Jan 24 07:37:50 PM PST 24 Jan 24 07:37:53 PM PST 24 65434376 ps
T905 /workspace/coverage/default/21.edn_disable.1264442938 Jan 24 07:38:21 PM PST 24 Jan 24 07:38:23 PM PST 24 13288952 ps
T906 /workspace/coverage/default/25.edn_stress_all.1870415373 Jan 24 07:38:42 PM PST 24 Jan 24 07:38:52 PM PST 24 70630892 ps
T907 /workspace/coverage/default/75.edn_genbits.1038414400 Jan 24 07:42:27 PM PST 24 Jan 24 07:42:29 PM PST 24 24845241 ps
T908 /workspace/coverage/default/43.edn_disable.2074966054 Jan 24 07:41:02 PM PST 24 Jan 24 07:41:05 PM PST 24 39430067 ps
T909 /workspace/coverage/default/33.edn_alert_test.1382160093 Jan 24 07:39:47 PM PST 24 Jan 24 07:39:49 PM PST 24 16598176 ps
T910 /workspace/coverage/default/1.edn_stress_all.4105053369 Jan 24 07:35:49 PM PST 24 Jan 24 07:35:52 PM PST 24 73198014 ps
T911 /workspace/coverage/default/44.edn_genbits.3655020113 Jan 24 07:41:02 PM PST 24 Jan 24 07:41:04 PM PST 24 36917384 ps
T912 /workspace/coverage/default/7.edn_err.3981279707 Jan 24 09:15:47 PM PST 24 Jan 24 09:15:49 PM PST 24 20575368 ps
T913 /workspace/coverage/default/34.edn_smoke.1522014026 Jan 24 07:39:50 PM PST 24 Jan 24 07:39:53 PM PST 24 14031485 ps
T129 /workspace/coverage/default/16.edn_disable.2922245827 Jan 24 07:37:51 PM PST 24 Jan 24 07:37:53 PM PST 24 19948463 ps
T914 /workspace/coverage/default/69.edn_genbits.622017061 Jan 24 07:42:29 PM PST 24 Jan 24 07:42:31 PM PST 24 18417287 ps
T915 /workspace/coverage/default/44.edn_alert_test.3747560558 Jan 24 07:41:08 PM PST 24 Jan 24 07:41:10 PM PST 24 18249823 ps
T916 /workspace/coverage/default/227.edn_genbits.2942953971 Jan 24 09:13:04 PM PST 24 Jan 24 09:13:10 PM PST 24 60353106 ps
T917 /workspace/coverage/default/47.edn_smoke.2364959632 Jan 24 07:41:29 PM PST 24 Jan 24 07:41:31 PM PST 24 11792951 ps
T918 /workspace/coverage/default/260.edn_genbits.331612720 Jan 24 07:44:56 PM PST 24 Jan 24 07:45:01 PM PST 24 25313928 ps
T919 /workspace/coverage/default/201.edn_genbits.2168420181 Jan 24 07:44:20 PM PST 24 Jan 24 07:44:22 PM PST 24 18255190 ps
T920 /workspace/coverage/default/2.edn_alert.2922512706 Jan 24 07:46:15 PM PST 24 Jan 24 07:46:17 PM PST 24 39567016 ps
T921 /workspace/coverage/default/23.edn_alert_test.423023980 Jan 24 08:16:44 PM PST 24 Jan 24 08:16:46 PM PST 24 66081728 ps
T922 /workspace/coverage/default/32.edn_intr.1058038314 Jan 24 07:39:42 PM PST 24 Jan 24 07:39:44 PM PST 24 26522731 ps
T923 /workspace/coverage/default/14.edn_disable.3424594613 Jan 24 07:37:22 PM PST 24 Jan 24 07:37:24 PM PST 24 42398287 ps
T924 /workspace/coverage/default/165.edn_genbits.3083023503 Jan 24 07:44:01 PM PST 24 Jan 24 07:44:03 PM PST 24 28751027 ps
T925 /workspace/coverage/default/12.edn_stress_all.3271721560 Jan 24 07:37:15 PM PST 24 Jan 24 07:37:20 PM PST 24 196166616 ps
T926 /workspace/coverage/default/19.edn_stress_all_with_rand_reset.854803871 Jan 24 07:38:02 PM PST 24 Jan 24 07:55:19 PM PST 24 46842260962 ps
T927 /workspace/coverage/default/281.edn_genbits.3435939676 Jan 24 07:45:06 PM PST 24 Jan 24 07:45:10 PM PST 24 134560400 ps
T928 /workspace/coverage/default/12.edn_alert_test.2939947958 Jan 24 07:37:18 PM PST 24 Jan 24 07:37:20 PM PST 24 22742323 ps
T929 /workspace/coverage/default/12.edn_alert.715054332 Jan 24 07:37:14 PM PST 24 Jan 24 07:37:15 PM PST 24 90121770 ps
T930 /workspace/coverage/default/3.edn_smoke.2217467270 Jan 24 07:36:01 PM PST 24 Jan 24 07:36:10 PM PST 24 69900147 ps
T931 /workspace/coverage/default/254.edn_genbits.741628372 Jan 24 07:45:04 PM PST 24 Jan 24 07:45:08 PM PST 24 59771692 ps
T932 /workspace/coverage/default/57.edn_err.704088979 Jan 24 10:31:08 PM PST 24 Jan 24 10:31:13 PM PST 24 23653215 ps
T933 /workspace/coverage/default/10.edn_alert_test.101236505 Jan 24 07:36:56 PM PST 24 Jan 24 07:36:58 PM PST 24 19134258 ps
T934 /workspace/coverage/default/4.edn_alert_test.26179965 Jan 24 07:36:18 PM PST 24 Jan 24 07:36:23 PM PST 24 44529708 ps
T935 /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1258315333 Jan 24 07:37:57 PM PST 24 Jan 24 07:53:44 PM PST 24 74303680096 ps
T936 /workspace/coverage/default/26.edn_genbits.918164933 Jan 24 07:38:51 PM PST 24 Jan 24 07:38:59 PM PST 24 88873757 ps
T937 /workspace/coverage/default/139.edn_genbits.2563251317 Jan 24 07:43:36 PM PST 24 Jan 24 07:43:38 PM PST 24 62721662 ps
T938 /workspace/coverage/default/64.edn_genbits.2935356681 Jan 24 07:42:10 PM PST 24 Jan 24 07:42:16 PM PST 24 74853847 ps
T939 /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1909997654 Jan 24 07:39:11 PM PST 24 Jan 24 07:45:25 PM PST 24 63417329140 ps
T940 /workspace/coverage/default/36.edn_stress_all_with_rand_reset.703160198 Jan 24 07:39:58 PM PST 24 Jan 24 07:44:29 PM PST 24 41957436144 ps
T941 /workspace/coverage/default/4.edn_alert.175373044 Jan 24 07:36:16 PM PST 24 Jan 24 07:36:19 PM PST 24 136511277 ps
T942 /workspace/coverage/default/111.edn_genbits.1834532759 Jan 24 07:43:11 PM PST 24 Jan 24 07:43:13 PM PST 24 74429020 ps
T943 /workspace/coverage/default/34.edn_stress_all.1111651512 Jan 24 07:39:51 PM PST 24 Jan 24 07:39:54 PM PST 24 32089828 ps
T944 /workspace/coverage/default/128.edn_genbits.514621263 Jan 24 07:43:22 PM PST 24 Jan 24 07:43:24 PM PST 24 32206500 ps
T945 /workspace/coverage/default/66.edn_genbits.3265227338 Jan 24 07:42:13 PM PST 24 Jan 24 07:42:16 PM PST 24 14557698 ps
T946 /workspace/coverage/default/172.edn_genbits.4283608141 Jan 24 07:44:05 PM PST 24 Jan 24 07:44:08 PM PST 24 230041948 ps
T278 /workspace/coverage/default/297.edn_genbits.2516694911 Jan 24 07:45:20 PM PST 24 Jan 24 07:45:23 PM PST 24 96000322 ps
T947 /workspace/coverage/default/41.edn_stress_all.1434058057 Jan 24 09:23:23 PM PST 24 Jan 24 09:23:26 PM PST 24 322941467 ps
T948 /workspace/coverage/default/98.edn_err.3229968773 Jan 24 07:43:07 PM PST 24 Jan 24 07:43:09 PM PST 24 42480095 ps
T949 /workspace/coverage/default/209.edn_genbits.3980447349 Jan 24 07:44:18 PM PST 24 Jan 24 07:44:21 PM PST 24 53282484 ps
T950 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2192602175 Jan 24 03:48:59 PM PST 24 Jan 24 03:49:02 PM PST 24 225877227 ps
T951 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1015164669 Jan 24 03:46:34 PM PST 24 Jan 24 03:46:38 PM PST 24 29129257 ps
T952 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3724476810 Jan 24 04:27:42 PM PST 24 Jan 24 04:27:44 PM PST 24 17909135 ps
T953 /workspace/coverage/cover_reg_top/4.edn_intr_test.3860262021 Jan 24 03:45:37 PM PST 24 Jan 24 03:45:39 PM PST 24 44768108 ps
T954 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3337479548 Jan 24 04:13:19 PM PST 24 Jan 24 04:13:23 PM PST 24 225852153 ps

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.904964541
Short name T24
Test name
Test status
Simulation time 14496772 ps
CPU time 0.9 seconds
Started Jan 24 03:43:48 PM PST 24
Finished Jan 24 03:43:54 PM PST 24
Peak memory 206316 kb
Host smart-c685c5c3-f2fc-4998-93a4-6dedc2949662
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904964541 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.904964541
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/default/96.edn_genbits.2203083145
Short name T33
Test name
Test status
Simulation time 49829005 ps
CPU time 1.23 seconds
Started Jan 24 08:06:48 PM PST 24
Finished Jan 24 08:06:51 PM PST 24
Peak memory 214924 kb
Host smart-9380bf70-7184-4365-98c7-51a0de0cbb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203083145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2203083145
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.1459354802
Short name T42
Test name
Test status
Simulation time 282432284 ps
CPU time 3.62 seconds
Started Jan 24 07:45:14 PM PST 24
Finished Jan 24 07:45:19 PM PST 24
Peak memory 214924 kb
Host smart-001a7085-7e4b-4c20-9c3f-589d893aa671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459354802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1459354802
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3919565715
Short name T145
Test name
Test status
Simulation time 30786843 ps
CPU time 2.19 seconds
Started Jan 24 04:38:27 PM PST 24
Finished Jan 24 04:38:35 PM PST 24
Peak memory 214644 kb
Host smart-4de9f195-779e-4770-9130-ca2a0972522d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919565715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3919565715
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/default/99.edn_err.740079085
Short name T77
Test name
Test status
Simulation time 18224626 ps
CPU time 1.07 seconds
Started Jan 24 07:43:04 PM PST 24
Finished Jan 24 07:43:08 PM PST 24
Peak memory 216460 kb
Host smart-fd609861-72e3-40c6-8b66-2d8dbb637443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740079085 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.740079085
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1449707259
Short name T4
Test name
Test status
Simulation time 196042885842 ps
CPU time 1158.19 seconds
Started Jan 24 07:36:29 PM PST 24
Finished Jan 24 07:55:48 PM PST 24
Peak memory 219372 kb
Host smart-ab6d2cab-ee00-4fd3-a19c-71cb376526ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449707259 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1449707259
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.edn_sec_cm.3838126334
Short name T20
Test name
Test status
Simulation time 3054802527 ps
CPU time 6.79 seconds
Started Jan 24 07:35:41 PM PST 24
Finished Jan 24 07:35:50 PM PST 24
Peak memory 234792 kb
Host smart-9e203ab7-7fc3-4317-b32c-1ce9a7170bef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838126334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3838126334
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1374851227
Short name T10
Test name
Test status
Simulation time 326043471 ps
CPU time 1.1 seconds
Started Jan 24 07:41:09 PM PST 24
Finished Jan 24 07:41:11 PM PST 24
Peak memory 215052 kb
Host smart-59215968-cc31-4f5f-a221-d99359ec465f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374851227 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1374851227
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.714553512
Short name T150
Test name
Test status
Simulation time 846909844 ps
CPU time 2.44 seconds
Started Jan 24 03:49:26 PM PST 24
Finished Jan 24 03:49:30 PM PST 24
Peak memory 206412 kb
Host smart-dd277c2d-c7ec-4ff4-94a2-3dde9780b750
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714553512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.714553512
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1599665847
Short name T170
Test name
Test status
Simulation time 27889550 ps
CPU time 0.9 seconds
Started Jan 24 03:49:43 PM PST 24
Finished Jan 24 03:49:45 PM PST 24
Peak memory 206260 kb
Host smart-f4567190-ea35-412e-85ca-e8ee0145d29c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599665847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1599665847
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.472921361
Short name T30
Test name
Test status
Simulation time 110977160 ps
CPU time 1.52 seconds
Started Jan 24 03:46:45 PM PST 24
Finished Jan 24 03:46:49 PM PST 24
Peak memory 214580 kb
Host smart-750b5927-2bc6-49fa-a5b0-daa746763b80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472921361 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.472921361
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/194.edn_genbits.2199131226
Short name T34
Test name
Test status
Simulation time 71473280 ps
CPU time 1.11 seconds
Started Jan 24 07:44:13 PM PST 24
Finished Jan 24 07:44:15 PM PST 24
Peak memory 214792 kb
Host smart-b7d45e05-ca47-421b-bdbf-0cf57432b872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199131226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2199131226
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.1284238161
Short name T408
Test name
Test status
Simulation time 95379922838 ps
CPU time 1097.29 seconds
Started Jan 24 07:37:05 PM PST 24
Finished Jan 24 07:55:24 PM PST 24
Peak memory 220108 kb
Host smart-dada5852-9b3b-4260-89de-bb19e1dd25ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284238161 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.1284238161
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.edn_intr.1721395187
Short name T91
Test name
Test status
Simulation time 32010636 ps
CPU time 0.85 seconds
Started Jan 24 07:35:40 PM PST 24
Finished Jan 24 07:35:44 PM PST 24
Peak memory 214632 kb
Host smart-b26f28e5-9567-4f8c-917f-dc2ac6a1dcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721395187 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1721395187
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/22.edn_alert.3050650704
Short name T204
Test name
Test status
Simulation time 18084671 ps
CPU time 0.99 seconds
Started Jan 24 07:38:17 PM PST 24
Finished Jan 24 07:38:20 PM PST 24
Peak memory 205624 kb
Host smart-e850d974-34e7-435f-ad3e-231273563012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050650704 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.3050650704
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.2094227213
Short name T152
Test name
Test status
Simulation time 84918508 ps
CPU time 0.87 seconds
Started Jan 24 03:49:37 PM PST 24
Finished Jan 24 03:49:40 PM PST 24
Peak memory 206296 kb
Host smart-a96b235f-e420-4134-80ec-b1c1764e1da0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094227213 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.2094227213
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2443906469
Short name T167
Test name
Test status
Simulation time 36047143 ps
CPU time 1.69 seconds
Started Jan 24 03:44:54 PM PST 24
Finished Jan 24 03:44:57 PM PST 24
Peak memory 222768 kb
Host smart-465c3751-5c12-44b3-85c4-29c651a03bc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443906469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2443906469
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/default/2.edn_regwen.3246455146
Short name T208
Test name
Test status
Simulation time 13095090 ps
CPU time 0.93 seconds
Started Jan 24 07:35:53 PM PST 24
Finished Jan 24 07:35:57 PM PST 24
Peak memory 206416 kb
Host smart-cd9f7906-2b2a-4838-9440-7a442b834509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246455146 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3246455146
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/12.edn_intr.3157557397
Short name T90
Test name
Test status
Simulation time 31313767 ps
CPU time 0.97 seconds
Started Jan 24 07:37:19 PM PST 24
Finished Jan 24 07:37:22 PM PST 24
Peak memory 225864 kb
Host smart-f0aa6062-482e-4c02-ae98-234260a15123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157557397 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3157557397
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/95.edn_err.47903715
Short name T88
Test name
Test status
Simulation time 24620058 ps
CPU time 0.92 seconds
Started Jan 24 07:43:04 PM PST 24
Finished Jan 24 07:43:07 PM PST 24
Peak memory 216332 kb
Host smart-ba353ff0-1fbc-4533-9d4e-1e9e8154f290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47903715 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.47903715
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/148.edn_genbits.2356878340
Short name T102
Test name
Test status
Simulation time 66802617 ps
CPU time 1.05 seconds
Started Jan 24 07:43:40 PM PST 24
Finished Jan 24 07:43:42 PM PST 24
Peak memory 216168 kb
Host smart-196afc00-4836-4c16-b9ae-749d34333ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356878340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2356878340
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.4047069693
Short name T162
Test name
Test status
Simulation time 228615270 ps
CPU time 5.76 seconds
Started Jan 24 04:48:44 PM PST 24
Finished Jan 24 04:48:51 PM PST 24
Peak memory 206360 kb
Host smart-6ce9ddda-246f-49a8-9c9f-7cfdeed0e927
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047069693 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.4047069693
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/default/15.edn_alert.4010721024
Short name T246
Test name
Test status
Simulation time 49137486 ps
CPU time 0.98 seconds
Started Jan 24 07:37:24 PM PST 24
Finished Jan 24 07:37:26 PM PST 24
Peak memory 206384 kb
Host smart-efbce71b-7f99-4af7-8ebe-e25401e361d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010721024 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.4010721024
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/95.edn_genbits.2129369835
Short name T475
Test name
Test status
Simulation time 23112010 ps
CPU time 1.17 seconds
Started Jan 24 07:43:02 PM PST 24
Finished Jan 24 07:43:06 PM PST 24
Peak memory 215004 kb
Host smart-4a8f3332-2808-4797-870e-292e55b6c87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129369835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2129369835
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.801193164
Short name T297
Test name
Test status
Simulation time 100176354 ps
CPU time 0.83 seconds
Started Jan 24 03:59:24 PM PST 24
Finished Jan 24 03:59:25 PM PST 24
Peak memory 206248 kb
Host smart-5ccd99c4-6171-403b-9c4f-cc9196e501ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801193164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.801193164
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/default/6.edn_genbits.1982938317
Short name T125
Test name
Test status
Simulation time 62701534 ps
CPU time 1 seconds
Started Jan 24 08:19:09 PM PST 24
Finished Jan 24 08:19:13 PM PST 24
Peak memory 214684 kb
Host smart-c19cf844-84f6-4e7d-b923-8054f12b1869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982938317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1982938317
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_regwen.3250276026
Short name T207
Test name
Test status
Simulation time 17129880 ps
CPU time 0.98 seconds
Started Jan 24 07:36:30 PM PST 24
Finished Jan 24 07:36:33 PM PST 24
Peak memory 206384 kb
Host smart-376f8fc4-edbf-4253-9412-01b158df9ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250276026 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3250276026
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/11.edn_alert.2953151217
Short name T201
Test name
Test status
Simulation time 53000561 ps
CPU time 0.96 seconds
Started Jan 24 07:37:06 PM PST 24
Finished Jan 24 07:37:08 PM PST 24
Peak memory 206368 kb
Host smart-bcc460fb-5c69-4758-94fc-e8d4eb49ed0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953151217 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2953151217
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert.1721567367
Short name T251
Test name
Test status
Simulation time 19581307 ps
CPU time 1 seconds
Started Jan 24 07:38:13 PM PST 24
Finished Jan 24 07:38:16 PM PST 24
Peak memory 206360 kb
Host smart-e8f52d37-5a13-4135-9e0d-cf973616f55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721567367 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1721567367
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2743249094
Short name T175
Test name
Test status
Simulation time 125732842 ps
CPU time 2.4 seconds
Started Jan 24 04:18:36 PM PST 24
Finished Jan 24 04:18:40 PM PST 24
Peak memory 206396 kb
Host smart-e75bd3ee-7891-4897-85f3-8b27c8ab0829
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743249094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2743249094
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_stress_all.169498270
Short name T83
Test name
Test status
Simulation time 288494326 ps
CPU time 3.51 seconds
Started Jan 24 07:35:37 PM PST 24
Finished Jan 24 07:35:44 PM PST 24
Peak memory 214684 kb
Host smart-7d5bf009-2dcb-4e55-b65f-507288b54bbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169498270 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.169498270
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_genbits.1241258539
Short name T115
Test name
Test status
Simulation time 21793442 ps
CPU time 1.14 seconds
Started Jan 24 07:37:27 PM PST 24
Finished Jan 24 07:37:29 PM PST 24
Peak memory 216136 kb
Host smart-a5d3ceaf-d95b-4c2d-b218-969f8c6f72a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241258539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.1241258539
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1101702553
Short name T505
Test name
Test status
Simulation time 101254524929 ps
CPU time 1152.94 seconds
Started Jan 24 07:40:00 PM PST 24
Finished Jan 24 07:59:15 PM PST 24
Peak memory 220756 kb
Host smart-c94e4155-76c2-429e-8108-7dcc18581e45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101702553 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1101702553
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_stress_all.1601458980
Short name T218
Test name
Test status
Simulation time 122760813 ps
CPU time 3.4 seconds
Started Jan 24 07:40:49 PM PST 24
Finished Jan 24 07:40:53 PM PST 24
Peak memory 214928 kb
Host smart-1064a9d8-7af7-44a3-93a1-9921427d9f54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601458980 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.1601458980
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_genbits.4099120762
Short name T141
Test name
Test status
Simulation time 81011584 ps
CPU time 3.14 seconds
Started Jan 24 07:36:50 PM PST 24
Finished Jan 24 07:36:54 PM PST 24
Peak memory 215164 kb
Host smart-3f5c3aad-41d4-4b75-be56-596d5d11ae68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099120762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.4099120762
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_genbits.1999131471
Short name T275
Test name
Test status
Simulation time 19875488 ps
CPU time 1.17 seconds
Started Jan 24 07:37:04 PM PST 24
Finished Jan 24 07:37:06 PM PST 24
Peak memory 214908 kb
Host smart-2e7e06fd-653e-4335-bcab-0340694812eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999131471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1999131471
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.1932414495
Short name T670
Test name
Test status
Simulation time 703883243 ps
CPU time 3.57 seconds
Started Jan 24 07:43:14 PM PST 24
Finished Jan 24 07:43:19 PM PST 24
Peak memory 217532 kb
Host smart-02e77e2b-5ca3-4275-a292-ec1c9321af16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932414495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1932414495
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1019233090
Short name T713
Test name
Test status
Simulation time 33519879 ps
CPU time 1.1 seconds
Started Jan 24 07:37:20 PM PST 24
Finished Jan 24 07:37:23 PM PST 24
Peak memory 214952 kb
Host smart-afa08c22-7170-4689-8325-36d00faad8ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019233090 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1019233090
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/222.edn_genbits.704819395
Short name T551
Test name
Test status
Simulation time 24393294 ps
CPU time 1.04 seconds
Started Jan 24 07:44:32 PM PST 24
Finished Jan 24 07:44:35 PM PST 24
Peak memory 214824 kb
Host smart-8bb5be3c-a023-448f-a3c0-e4fac56b83d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704819395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.704819395
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2944035887
Short name T520
Test name
Test status
Simulation time 93933126 ps
CPU time 1.13 seconds
Started Jan 24 07:44:45 PM PST 24
Finished Jan 24 07:44:49 PM PST 24
Peak memory 214084 kb
Host smart-76f2810a-27a4-4239-a6c3-333fb59664d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944035887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2944035887
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_regwen.596946013
Short name T243
Test name
Test status
Simulation time 12778489 ps
CPU time 0.9 seconds
Started Jan 24 09:31:55 PM PST 24
Finished Jan 24 09:32:04 PM PST 24
Peak memory 206412 kb
Host smart-ff01fce4-cc4c-4a14-adfa-1da2c124f69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596946013 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.596946013
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/22.edn_intr.5845961
Short name T95
Test name
Test status
Simulation time 24115121 ps
CPU time 0.97 seconds
Started Jan 24 07:38:23 PM PST 24
Finished Jan 24 07:38:27 PM PST 24
Peak memory 214908 kb
Host smart-9bf739d7-9c0c-418b-9846-203390f351da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5845961 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.5845961
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/14.edn_alert_test.607679966
Short name T113
Test name
Test status
Simulation time 22868414 ps
CPU time 1.09 seconds
Started Jan 24 07:37:27 PM PST 24
Finished Jan 24 07:37:29 PM PST 24
Peak memory 205172 kb
Host smart-d4addaf4-9285-44c2-bf32-f770ab41b2f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607679966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.607679966
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/289.edn_genbits.558783751
Short name T233
Test name
Test status
Simulation time 24939862 ps
CPU time 1.25 seconds
Started Jan 24 07:45:08 PM PST 24
Finished Jan 24 07:45:11 PM PST 24
Peak memory 215132 kb
Host smart-8e6af9ef-8b97-487c-8181-25b43881c14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558783751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.558783751
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.638868847
Short name T212
Test name
Test status
Simulation time 99029139 ps
CPU time 3.62 seconds
Started Jan 24 03:44:06 PM PST 24
Finished Jan 24 03:44:11 PM PST 24
Peak memory 214708 kb
Host smart-a1d5e8ba-2d55-40aa-8455-520344bd4745
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638868847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.638868847
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2076592414
Short name T189
Test name
Test status
Simulation time 29595378 ps
CPU time 0.81 seconds
Started Jan 24 03:49:25 PM PST 24
Finished Jan 24 03:49:28 PM PST 24
Peak memory 206120 kb
Host smart-95aecb53-7cfa-4f17-8111-86f10554bcbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076592414 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2076592414
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/default/1.edn_err.2821248380
Short name T15
Test name
Test status
Simulation time 20323910 ps
CPU time 1.22 seconds
Started Jan 24 09:50:36 PM PST 24
Finished Jan 24 09:50:38 PM PST 24
Peak memory 222180 kb
Host smart-45a9f811-b36b-42da-8039-c1ff0a46ac44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821248380 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2821248380
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_regwen.19736349
Short name T247
Test name
Test status
Simulation time 20978121 ps
CPU time 0.9 seconds
Started Jan 24 07:35:37 PM PST 24
Finished Jan 24 07:35:41 PM PST 24
Peak memory 206400 kb
Host smart-7adc9cdd-4a8b-4f58-834f-5f73f555bf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19736349 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.19736349
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/103.edn_genbits.2285355533
Short name T272
Test name
Test status
Simulation time 17441344 ps
CPU time 1.11 seconds
Started Jan 24 08:26:25 PM PST 24
Finished Jan 24 08:26:29 PM PST 24
Peak memory 216336 kb
Host smart-b458440c-41fa-4709-97c0-a12d423fbeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285355533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2285355533
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.733744118
Short name T270
Test name
Test status
Simulation time 99412903 ps
CPU time 2.51 seconds
Started Jan 24 08:45:18 PM PST 24
Finished Jan 24 08:45:22 PM PST 24
Peak memory 217572 kb
Host smart-44e97196-5345-4a16-939e-08c609e46f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733744118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.733744118
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3356817984
Short name T245
Test name
Test status
Simulation time 42344431 ps
CPU time 0.96 seconds
Started Jan 24 07:37:42 PM PST 24
Finished Jan 24 07:37:44 PM PST 24
Peak memory 205628 kb
Host smart-6eb60dc3-2fef-4adf-b37e-3e6191bf1640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356817984 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3356817984
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/207.edn_genbits.1072701590
Short name T283
Test name
Test status
Simulation time 60193024 ps
CPU time 1.02 seconds
Started Jan 24 07:53:46 PM PST 24
Finished Jan 24 07:53:48 PM PST 24
Peak memory 214960 kb
Host smart-a73ffc85-c67a-4754-a03f-d4aff1c6b884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072701590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1072701590
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2727078895
Short name T263
Test name
Test status
Simulation time 16388619 ps
CPU time 1.07 seconds
Started Jan 24 07:44:55 PM PST 24
Finished Jan 24 07:44:57 PM PST 24
Peak memory 216156 kb
Host smart-df8c19b6-068a-4dcd-82bf-adaa3d295a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727078895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2727078895
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2516694911
Short name T278
Test name
Test status
Simulation time 96000322 ps
CPU time 1 seconds
Started Jan 24 07:45:20 PM PST 24
Finished Jan 24 07:45:23 PM PST 24
Peak memory 216364 kb
Host smart-80834181-164b-407b-acc8-61571e38ac6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516694911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2516694911
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1182483791
Short name T178
Test name
Test status
Simulation time 23125567 ps
CPU time 1.05 seconds
Started Jan 24 03:43:59 PM PST 24
Finished Jan 24 03:44:02 PM PST 24
Peak memory 206388 kb
Host smart-ff236f29-0254-41fd-900a-2573ce441f80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182483791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1182483791
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/35.edn_disable.3621215509
Short name T143
Test name
Test status
Simulation time 17930833 ps
CPU time 0.84 seconds
Started Jan 24 07:39:58 PM PST 24
Finished Jan 24 07:40:00 PM PST 24
Peak memory 214804 kb
Host smart-d8825508-16b1-4b2f-96c1-e892ee65eb12
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621215509 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3621215509
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable.1113493890
Short name T127
Test name
Test status
Simulation time 21781556 ps
CPU time 0.86 seconds
Started Jan 24 07:35:38 PM PST 24
Finished Jan 24 07:35:42 PM PST 24
Peak memory 214808 kb
Host smart-9fade846-0b63-46d9-9441-7a0d620a9585
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113493890 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1113493890
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1022037049
Short name T702
Test name
Test status
Simulation time 24760060 ps
CPU time 1.02 seconds
Started Jan 24 07:37:24 PM PST 24
Finished Jan 24 07:37:26 PM PST 24
Peak memory 214972 kb
Host smart-66fb3bf0-ace0-44d1-9f91-2c1230d4a67e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022037049 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1022037049
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_disable.2922245827
Short name T129
Test name
Test status
Simulation time 19948463 ps
CPU time 0.86 seconds
Started Jan 24 07:37:51 PM PST 24
Finished Jan 24 07:37:53 PM PST 24
Peak memory 214832 kb
Host smart-797ab017-a816-4420-af57-835ab2a787b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922245827 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2922245827
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable.801852809
Short name T132
Test name
Test status
Simulation time 10826050 ps
CPU time 0.86 seconds
Started Jan 24 07:38:09 PM PST 24
Finished Jan 24 07:38:12 PM PST 24
Peak memory 214816 kb
Host smart-b04483c8-ec60-4bb1-afac-8020d316e83e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801852809 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.801852809
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.4224454935
Short name T118
Test name
Test status
Simulation time 21653209 ps
CPU time 0.97 seconds
Started Jan 24 07:38:21 PM PST 24
Finished Jan 24 07:38:24 PM PST 24
Peak memory 214900 kb
Host smart-65744543-1698-494e-a073-8cee4a88733b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224454935 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.4224454935
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_disable.3386542834
Short name T138
Test name
Test status
Simulation time 10725775 ps
CPU time 0.85 seconds
Started Jan 24 07:38:21 PM PST 24
Finished Jan 24 07:38:23 PM PST 24
Peak memory 214780 kb
Host smart-51827945-c31d-4f5d-8bf7-aaaa2ece5de3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386542834 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3386542834
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3481075642
Short name T123
Test name
Test status
Simulation time 31757301 ps
CPU time 1 seconds
Started Jan 24 07:39:57 PM PST 24
Finished Jan 24 07:40:00 PM PST 24
Peak memory 215036 kb
Host smart-5436e631-c117-4235-9041-585b244f5d75
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481075642 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3481075642
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_genbits.1174287869
Short name T264
Test name
Test status
Simulation time 71459164 ps
CPU time 1.15 seconds
Started Jan 24 07:35:31 PM PST 24
Finished Jan 24 07:35:34 PM PST 24
Peak memory 217568 kb
Host smart-c769bb24-7ef6-4e36-aaab-de705259eace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174287869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1174287869
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.1015259924
Short name T539
Test name
Test status
Simulation time 37474221 ps
CPU time 1.36 seconds
Started Jan 24 07:43:40 PM PST 24
Finished Jan 24 07:43:42 PM PST 24
Peak memory 214876 kb
Host smart-ff538f20-5e34-4938-bc4c-77e8a9d5eaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015259924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1015259924
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2605801694
Short name T151
Test name
Test status
Simulation time 30989779 ps
CPU time 1.05 seconds
Started Jan 24 04:16:15 PM PST 24
Finished Jan 24 04:16:18 PM PST 24
Peak memory 214612 kb
Host smart-556e4319-f3f7-4c25-8483-da25e95f324b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605801694 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2605801694
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.4206484988
Short name T296
Test name
Test status
Simulation time 57342367 ps
CPU time 0.93 seconds
Started Jan 24 03:43:47 PM PST 24
Finished Jan 24 03:43:53 PM PST 24
Peak memory 206344 kb
Host smart-d7a6d84e-708d-4aad-8f71-8f7cf1b37b60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206484988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.4206484988
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2225052794
Short name T161
Test name
Test status
Simulation time 18435954 ps
CPU time 0.89 seconds
Started Jan 24 03:43:50 PM PST 24
Finished Jan 24 03:43:56 PM PST 24
Peak memory 206228 kb
Host smart-684dbc9e-93d0-483e-b35c-17c8e6c038e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225052794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2225052794
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.123323681
Short name T191
Test name
Test status
Simulation time 82319304 ps
CPU time 2.22 seconds
Started Jan 24 03:43:50 PM PST 24
Finished Jan 24 03:43:57 PM PST 24
Peak memory 214948 kb
Host smart-b680812d-4200-4d1d-ad39-6824b9c7586c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123323681 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.123323681
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3693878431
Short name T215
Test name
Test status
Simulation time 219660731 ps
CPU time 4.17 seconds
Started Jan 24 03:59:48 PM PST 24
Finished Jan 24 04:00:00 PM PST 24
Peak memory 206400 kb
Host smart-9548aee7-f348-4f41-b783-f85fed9398b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693878431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3693878431
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3724476810
Short name T952
Test name
Test status
Simulation time 17909135 ps
CPU time 1.02 seconds
Started Jan 24 04:27:42 PM PST 24
Finished Jan 24 04:27:44 PM PST 24
Peak memory 206300 kb
Host smart-26c9ea50-796f-4179-8a08-5a8632876704
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724476810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3724476810
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.744730138
Short name T168
Test name
Test status
Simulation time 399633830 ps
CPU time 4.89 seconds
Started Jan 24 03:44:32 PM PST 24
Finished Jan 24 03:44:38 PM PST 24
Peak memory 206272 kb
Host smart-44eed8fe-a23e-46d3-8f21-2e2553e58524
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744730138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.744730138
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.2350799895
Short name T190
Test name
Test status
Simulation time 13025910 ps
CPU time 0.87 seconds
Started Jan 24 03:44:31 PM PST 24
Finished Jan 24 03:44:33 PM PST 24
Peak memory 206288 kb
Host smart-20a09f79-cfe6-4560-8249-13f7f9ab2b86
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350799895 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.2350799895
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.284089785
Short name T28
Test name
Test status
Simulation time 45518115 ps
CPU time 0.82 seconds
Started Jan 24 03:44:17 PM PST 24
Finished Jan 24 03:44:19 PM PST 24
Peak memory 206240 kb
Host smart-8763ffa1-be00-479c-877a-721ad36bd1b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284089785 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.284089785
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1329845265
Short name T327
Test name
Test status
Simulation time 18672619 ps
CPU time 1.06 seconds
Started Jan 24 03:44:42 PM PST 24
Finished Jan 24 03:44:44 PM PST 24
Peak memory 206456 kb
Host smart-03a93202-ce42-4e8a-acd2-57420ea8e11a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329845265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1329845265
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1734620745
Short name T313
Test name
Test status
Simulation time 89447504 ps
CPU time 2.44 seconds
Started Jan 24 03:44:18 PM PST 24
Finished Jan 24 03:44:22 PM PST 24
Peak memory 206360 kb
Host smart-31513a08-6299-428b-a611-f0c98c1ab499
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734620745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1734620745
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3748377116
Short name T193
Test name
Test status
Simulation time 34193305 ps
CPU time 1.49 seconds
Started Jan 24 03:47:18 PM PST 24
Finished Jan 24 03:47:21 PM PST 24
Peak memory 216956 kb
Host smart-8d6b5763-d5ab-4cf9-8897-e887f82bb952
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748377116 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3748377116
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1824607680
Short name T184
Test name
Test status
Simulation time 11799790 ps
CPU time 0.84 seconds
Started Jan 24 04:31:12 PM PST 24
Finished Jan 24 04:31:15 PM PST 24
Peak memory 206332 kb
Host smart-eb939797-c96e-4389-ba1e-dc8995f7999c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824607680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1824607680
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.382655342
Short name T173
Test name
Test status
Simulation time 16090962 ps
CPU time 0.91 seconds
Started Jan 24 03:47:10 PM PST 24
Finished Jan 24 03:47:13 PM PST 24
Peak memory 206272 kb
Host smart-8526a516-9ae4-423b-81f4-f88ee18e1628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382655342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.382655342
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3249892088
Short name T155
Test name
Test status
Simulation time 108185560 ps
CPU time 3.49 seconds
Started Jan 24 03:46:56 PM PST 24
Finished Jan 24 03:47:02 PM PST 24
Peak memory 214680 kb
Host smart-a0e7612c-3a08-448a-9d0b-50725a45aa06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249892088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3249892088
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3874930682
Short name T348
Test name
Test status
Simulation time 175021769 ps
CPU time 2.3 seconds
Started Jan 24 03:47:10 PM PST 24
Finished Jan 24 03:47:14 PM PST 24
Peak memory 206388 kb
Host smart-ea451278-77dc-408a-acc3-59909010275e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874930682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3874930682
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2161057468
Short name T157
Test name
Test status
Simulation time 30267493 ps
CPU time 1.38 seconds
Started Jan 24 03:47:29 PM PST 24
Finished Jan 24 03:47:32 PM PST 24
Peak memory 214628 kb
Host smart-a7b76e9b-dff6-497f-8ab6-2848057cc47b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161057468 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2161057468
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3560035377
Short name T289
Test name
Test status
Simulation time 11858400 ps
CPU time 0.86 seconds
Started Jan 24 03:47:31 PM PST 24
Finished Jan 24 03:47:33 PM PST 24
Peak memory 206300 kb
Host smart-3dbe5655-33fe-483d-a8a8-36958e7c81fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560035377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3560035377
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.421030819
Short name T321
Test name
Test status
Simulation time 12598899 ps
CPU time 0.94 seconds
Started Jan 24 03:47:17 PM PST 24
Finished Jan 24 03:47:19 PM PST 24
Peak memory 206200 kb
Host smart-bb8996a0-e0bf-4f30-86d8-ebd60267e882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421030819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.421030819
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3134433050
Short name T328
Test name
Test status
Simulation time 28932640 ps
CPU time 1 seconds
Started Jan 24 04:21:09 PM PST 24
Finished Jan 24 04:21:12 PM PST 24
Peak memory 206360 kb
Host smart-684c1421-c6d5-4b17-a35d-e42ac019d2e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134433050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3134433050
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2182364471
Short name T356
Test name
Test status
Simulation time 104680569 ps
CPU time 1.97 seconds
Started Jan 24 03:47:17 PM PST 24
Finished Jan 24 03:47:20 PM PST 24
Peak memory 214624 kb
Host smart-fafe95da-d5d5-499a-9f2b-8cdd755e8a1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182364471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2182364471
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.3337479548
Short name T954
Test name
Test status
Simulation time 225852153 ps
CPU time 1.51 seconds
Started Jan 24 04:13:19 PM PST 24
Finished Jan 24 04:13:23 PM PST 24
Peak memory 206392 kb
Host smart-9fa2cb3e-b9e5-47d7-b673-aefcf0934a31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337479548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.3337479548
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2273514438
Short name T209
Test name
Test status
Simulation time 138823092 ps
CPU time 2 seconds
Started Jan 24 03:48:43 PM PST 24
Finished Jan 24 03:48:47 PM PST 24
Peak memory 214676 kb
Host smart-6885319d-d777-4844-8dfd-84973354d424
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273514438 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2273514438
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1770319330
Short name T163
Test name
Test status
Simulation time 14912275 ps
CPU time 0.93 seconds
Started Jan 24 03:48:44 PM PST 24
Finished Jan 24 03:48:46 PM PST 24
Peak memory 206328 kb
Host smart-5ad4b903-ce93-407f-83bb-1c3cc4b94d90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770319330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1770319330
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2441975951
Short name T362
Test name
Test status
Simulation time 13029558 ps
CPU time 0.86 seconds
Started Jan 24 03:48:43 PM PST 24
Finished Jan 24 03:48:46 PM PST 24
Peak memory 206244 kb
Host smart-3a95244b-c59d-4790-95de-22ae7b90b9d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441975951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2441975951
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3940823321
Short name T177
Test name
Test status
Simulation time 306848470 ps
CPU time 1.14 seconds
Started Jan 24 03:48:41 PM PST 24
Finished Jan 24 03:48:42 PM PST 24
Peak memory 206452 kb
Host smart-8a3162f5-a3e6-45ba-a200-1ab29f892961
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940823321 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3940823321
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3119422397
Short name T324
Test name
Test status
Simulation time 151467811 ps
CPU time 1.42 seconds
Started Jan 24 03:48:42 PM PST 24
Finished Jan 24 03:48:46 PM PST 24
Peak memory 206432 kb
Host smart-9a99b2f7-cd25-4db5-a456-d8df49af693b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119422397 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3119422397
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.303592789
Short name T196
Test name
Test status
Simulation time 55733165 ps
CPU time 1.11 seconds
Started Jan 24 03:48:58 PM PST 24
Finished Jan 24 03:49:00 PM PST 24
Peak memory 214704 kb
Host smart-23b8e9f6-23ac-4bba-9719-44a671684f3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303592789 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.303592789
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.1904935225
Short name T197
Test name
Test status
Simulation time 23718243 ps
CPU time 0.91 seconds
Started Jan 24 03:48:51 PM PST 24
Finished Jan 24 03:48:53 PM PST 24
Peak memory 206320 kb
Host smart-9d5a042a-efcc-45f4-a6ed-5273644e1903
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904935225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.1904935225
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.319549669
Short name T169
Test name
Test status
Simulation time 87860076 ps
CPU time 0.8 seconds
Started Jan 24 03:49:19 PM PST 24
Finished Jan 24 03:49:24 PM PST 24
Peak memory 205996 kb
Host smart-ce2bf37d-0625-4fbe-be01-7af7b2e177ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319549669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.319549669
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2295727353
Short name T309
Test name
Test status
Simulation time 17755775 ps
CPU time 1.13 seconds
Started Jan 24 03:48:52 PM PST 24
Finished Jan 24 03:48:54 PM PST 24
Peak memory 206384 kb
Host smart-10e45821-378d-48d6-aaff-f211df88ad81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295727353 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2295727353
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.388338933
Short name T341
Test name
Test status
Simulation time 88005513 ps
CPU time 1.99 seconds
Started Jan 24 03:48:40 PM PST 24
Finished Jan 24 03:48:43 PM PST 24
Peak memory 214704 kb
Host smart-ecb469c4-4b11-4a2d-a64d-01619aeaea9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388338933 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.388338933
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3715283729
Short name T312
Test name
Test status
Simulation time 89780412 ps
CPU time 1.63 seconds
Started Jan 24 03:48:50 PM PST 24
Finished Jan 24 03:48:53 PM PST 24
Peak memory 206364 kb
Host smart-2261d17d-4473-41cf-97af-3da9546601d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715283729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3715283729
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2990692468
Short name T323
Test name
Test status
Simulation time 23583762 ps
CPU time 1.57 seconds
Started Jan 24 03:48:59 PM PST 24
Finished Jan 24 03:49:02 PM PST 24
Peak memory 214692 kb
Host smart-05938ab0-7df8-4066-a253-1e623d273509
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990692468 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2990692468
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2228888729
Short name T181
Test name
Test status
Simulation time 13955869 ps
CPU time 0.89 seconds
Started Jan 24 03:49:01 PM PST 24
Finished Jan 24 03:49:04 PM PST 24
Peak memory 206348 kb
Host smart-6b7acf75-3ec8-4860-8e9c-53c060318c16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228888729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2228888729
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.1970785181
Short name T318
Test name
Test status
Simulation time 13918295 ps
CPU time 0.88 seconds
Started Jan 24 03:49:00 PM PST 24
Finished Jan 24 03:49:03 PM PST 24
Peak memory 206308 kb
Host smart-8d2e1942-ce25-46c5-8564-cd4ca3629bed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970785181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.1970785181
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2192602175
Short name T950
Test name
Test status
Simulation time 225877227 ps
CPU time 1.41 seconds
Started Jan 24 03:48:59 PM PST 24
Finished Jan 24 03:49:02 PM PST 24
Peak memory 206404 kb
Host smart-db5372bc-e1a9-46a7-abc1-b59a4903de2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192602175 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2192602175
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.581312210
Short name T148
Test name
Test status
Simulation time 1262654320 ps
CPU time 3.17 seconds
Started Jan 24 03:49:00 PM PST 24
Finished Jan 24 03:49:06 PM PST 24
Peak memory 214896 kb
Host smart-eabafd38-429e-42bf-a522-6212d0a78e79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581312210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.581312210
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.482762094
Short name T211
Test name
Test status
Simulation time 79488567 ps
CPU time 1.54 seconds
Started Jan 24 03:49:01 PM PST 24
Finished Jan 24 03:49:05 PM PST 24
Peak memory 206456 kb
Host smart-eeb5b3be-18cb-4659-ab92-01db2b37ec18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482762094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.482762094
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.4265251035
Short name T154
Test name
Test status
Simulation time 46622005 ps
CPU time 1.22 seconds
Started Jan 24 03:49:26 PM PST 24
Finished Jan 24 03:49:29 PM PST 24
Peak memory 214564 kb
Host smart-a6c42075-a93a-4485-822d-2a66643e287d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265251035 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.4265251035
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.3118851469
Short name T174
Test name
Test status
Simulation time 14268337 ps
CPU time 0.87 seconds
Started Jan 24 05:14:37 PM PST 24
Finished Jan 24 05:14:38 PM PST 24
Peak memory 206336 kb
Host smart-18035807-c435-4541-851e-12e19e4a9a6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118851469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.3118851469
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2153463611
Short name T295
Test name
Test status
Simulation time 92827246 ps
CPU time 0.82 seconds
Started Jan 24 03:49:14 PM PST 24
Finished Jan 24 03:49:20 PM PST 24
Peak memory 206088 kb
Host smart-f9b2392e-b762-4b27-a49a-6874ff4031d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153463611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2153463611
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2280342697
Short name T179
Test name
Test status
Simulation time 76702275 ps
CPU time 1.17 seconds
Started Jan 24 03:49:26 PM PST 24
Finished Jan 24 03:49:29 PM PST 24
Peak memory 206456 kb
Host smart-b9316cc3-5a0e-48fb-87b2-22898aee7242
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280342697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2280342697
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2242708003
Short name T192
Test name
Test status
Simulation time 135513070 ps
CPU time 2.9 seconds
Started Jan 24 03:49:01 PM PST 24
Finished Jan 24 03:49:08 PM PST 24
Peak memory 214676 kb
Host smart-a767a2a9-7f03-4621-80cf-f13ec05fc09c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242708003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2242708003
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.3452337854
Short name T146
Test name
Test status
Simulation time 202307706 ps
CPU time 2.33 seconds
Started Jan 24 03:49:12 PM PST 24
Finished Jan 24 03:49:17 PM PST 24
Peak memory 206400 kb
Host smart-c5f42ee6-7721-46ce-9c27-d422cc9558d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452337854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.3452337854
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2901442826
Short name T334
Test name
Test status
Simulation time 82155209 ps
CPU time 1.08 seconds
Started Jan 24 03:49:26 PM PST 24
Finished Jan 24 03:49:28 PM PST 24
Peak memory 214684 kb
Host smart-3ed2946b-1d5c-4500-a46c-dfbcd6c8cd00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901442826 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2901442826
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.774723868
Short name T311
Test name
Test status
Simulation time 17256227 ps
CPU time 0.92 seconds
Started Jan 24 03:49:24 PM PST 24
Finished Jan 24 03:49:27 PM PST 24
Peak memory 206244 kb
Host smart-a2087fc4-2757-4cb9-ad1b-a74676313d62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774723868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.774723868
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3517646515
Short name T85
Test name
Test status
Simulation time 14222749 ps
CPU time 0.97 seconds
Started Jan 24 03:49:28 PM PST 24
Finished Jan 24 03:49:31 PM PST 24
Peak memory 206456 kb
Host smart-696a2d8c-c635-46d9-a09c-5f5bf3572e9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517646515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3517646515
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.861483754
Short name T308
Test name
Test status
Simulation time 78378979 ps
CPU time 1.57 seconds
Started Jan 24 03:49:29 PM PST 24
Finished Jan 24 03:49:33 PM PST 24
Peak memory 214704 kb
Host smart-8aeaba92-fe93-46a1-a1e7-54a59d8fbc64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861483754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.861483754
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2869698406
Short name T325
Test name
Test status
Simulation time 22096760 ps
CPU time 1.22 seconds
Started Jan 24 03:49:36 PM PST 24
Finished Jan 24 03:49:38 PM PST 24
Peak memory 214660 kb
Host smart-d3ad6e5e-21e8-42d1-87d1-b981dfb04e54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869698406 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2869698406
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1890527723
Short name T346
Test name
Test status
Simulation time 12909439 ps
CPU time 0.92 seconds
Started Jan 24 03:49:34 PM PST 24
Finished Jan 24 03:49:36 PM PST 24
Peak memory 206320 kb
Host smart-f1badfb5-456f-4d13-bc1e-0b62a1ec7aef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890527723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1890527723
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2563571990
Short name T49
Test name
Test status
Simulation time 37215870 ps
CPU time 0.86 seconds
Started Jan 24 03:49:51 PM PST 24
Finished Jan 24 03:49:59 PM PST 24
Peak memory 206000 kb
Host smart-4b021735-6ee3-43a8-8dbe-8986c0441ef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563571990 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2563571990
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.144975971
Short name T320
Test name
Test status
Simulation time 154058574 ps
CPU time 1.51 seconds
Started Jan 24 03:49:37 PM PST 24
Finished Jan 24 03:49:40 PM PST 24
Peak memory 206392 kb
Host smart-59e388bc-f80a-4443-ba6d-8e1911575a7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144975971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.144975971
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2535477533
Short name T165
Test name
Test status
Simulation time 120833179 ps
CPU time 2.38 seconds
Started Jan 24 03:49:26 PM PST 24
Finished Jan 24 03:49:30 PM PST 24
Peak memory 217724 kb
Host smart-167d31d6-8699-4b94-8d82-1ed491ca1072
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535477533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2535477533
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1623260805
Short name T164
Test name
Test status
Simulation time 53093416 ps
CPU time 1.67 seconds
Started Jan 24 04:07:08 PM PST 24
Finished Jan 24 04:07:13 PM PST 24
Peak memory 206408 kb
Host smart-8865c78e-8580-4b39-9e18-660e16127ea6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623260805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1623260805
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3596661293
Short name T337
Test name
Test status
Simulation time 62434244 ps
CPU time 1.34 seconds
Started Jan 24 04:27:36 PM PST 24
Finished Jan 24 04:27:39 PM PST 24
Peak memory 214632 kb
Host smart-a2d09ce1-ff92-4e97-ae2b-b57b89d311a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596661293 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3596661293
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2705830739
Short name T319
Test name
Test status
Simulation time 12738468 ps
CPU time 0.87 seconds
Started Jan 24 03:49:37 PM PST 24
Finished Jan 24 03:49:40 PM PST 24
Peak memory 206304 kb
Host smart-e0d75234-0abe-467a-a49b-dd003715ad07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705830739 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2705830739
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2394747634
Short name T361
Test name
Test status
Simulation time 34557888 ps
CPU time 0.8 seconds
Started Jan 24 03:49:38 PM PST 24
Finished Jan 24 03:49:41 PM PST 24
Peak memory 206040 kb
Host smart-ac54abab-17aa-404a-95a1-5205e14eedbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394747634 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2394747634
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.163713084
Short name T86
Test name
Test status
Simulation time 26306867 ps
CPU time 1.14 seconds
Started Jan 24 03:54:18 PM PST 24
Finished Jan 24 03:54:24 PM PST 24
Peak memory 206452 kb
Host smart-2f6f553f-64be-488a-be82-c9b9316ffd97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163713084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.163713084
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.75771434
Short name T210
Test name
Test status
Simulation time 92463232 ps
CPU time 3.29 seconds
Started Jan 24 03:49:36 PM PST 24
Finished Jan 24 03:49:40 PM PST 24
Peak memory 214644 kb
Host smart-81d845a4-80bb-42d9-8fb0-68a02cb65053
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75771434 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.75771434
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1592937121
Short name T214
Test name
Test status
Simulation time 474449053 ps
CPU time 2.26 seconds
Started Jan 24 04:53:56 PM PST 24
Finished Jan 24 04:53:59 PM PST 24
Peak memory 206448 kb
Host smart-8af32b3d-a01a-4025-9c21-6e85cd7e33c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592937121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1592937121
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3425769740
Short name T159
Test name
Test status
Simulation time 21963314 ps
CPU time 1.16 seconds
Started Jan 24 03:49:44 PM PST 24
Finished Jan 24 03:49:46 PM PST 24
Peak memory 214624 kb
Host smart-5d993fb0-2b06-48b4-a440-b537ffaf854c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425769740 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3425769740
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.174170682
Short name T340
Test name
Test status
Simulation time 139057545 ps
CPU time 0.79 seconds
Started Jan 24 04:17:51 PM PST 24
Finished Jan 24 04:17:55 PM PST 24
Peak memory 206072 kb
Host smart-0358c8f0-6506-4394-9fdd-5f1c8bfacc30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174170682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.174170682
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1377558391
Short name T172
Test name
Test status
Simulation time 32454670 ps
CPU time 1.21 seconds
Started Jan 24 03:49:46 PM PST 24
Finished Jan 24 03:49:48 PM PST 24
Peak memory 206432 kb
Host smart-68a7ff47-5c4f-40e4-8221-ffce51e152b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377558391 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1377558391
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1781517622
Short name T158
Test name
Test status
Simulation time 170206314 ps
CPU time 2.41 seconds
Started Jan 24 03:49:37 PM PST 24
Finished Jan 24 03:49:41 PM PST 24
Peak memory 214676 kb
Host smart-92544010-6504-4f9c-bfc6-7fb626112531
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781517622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1781517622
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1225045730
Short name T176
Test name
Test status
Simulation time 255383605 ps
CPU time 1.7 seconds
Started Jan 24 03:49:34 PM PST 24
Finished Jan 24 03:49:37 PM PST 24
Peak memory 206364 kb
Host smart-72814d4a-29fb-4dad-8ab6-af7ebafd5e39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225045730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1225045730
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1855151307
Short name T182
Test name
Test status
Simulation time 21299316 ps
CPU time 1.1 seconds
Started Jan 24 03:55:16 PM PST 24
Finished Jan 24 03:55:18 PM PST 24
Peak memory 206372 kb
Host smart-3cda9a1d-2f44-4f15-81ae-89d8effa8835
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855151307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1855151307
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1357286454
Short name T336
Test name
Test status
Simulation time 135888201 ps
CPU time 2.04 seconds
Started Jan 24 04:07:07 PM PST 24
Finished Jan 24 04:07:12 PM PST 24
Peak memory 206364 kb
Host smart-faa497b2-017a-4a66-913f-8c54234e71bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357286454 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1357286454
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1105212646
Short name T307
Test name
Test status
Simulation time 74878293 ps
CPU time 0.94 seconds
Started Jan 24 03:44:56 PM PST 24
Finished Jan 24 03:44:58 PM PST 24
Peak memory 206288 kb
Host smart-3b9bc5f8-e4a4-4e79-b3bd-69079417b69a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105212646 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1105212646
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3368569208
Short name T316
Test name
Test status
Simulation time 23564784 ps
CPU time 1.3 seconds
Started Jan 24 03:58:34 PM PST 24
Finished Jan 24 03:58:37 PM PST 24
Peak memory 214668 kb
Host smart-1c8cdffe-f4e4-4dcf-9ed4-3f9ed34527ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368569208 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3368569208
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3188704942
Short name T160
Test name
Test status
Simulation time 13557392 ps
CPU time 0.94 seconds
Started Jan 24 06:31:37 PM PST 24
Finished Jan 24 06:31:38 PM PST 24
Peak memory 206328 kb
Host smart-6223ada7-eeef-4566-9d30-522acc01f803
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188704942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3188704942
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.105167237
Short name T322
Test name
Test status
Simulation time 14743795 ps
CPU time 0.8 seconds
Started Jan 24 03:44:52 PM PST 24
Finished Jan 24 03:44:54 PM PST 24
Peak memory 206232 kb
Host smart-60b984e2-9812-443c-bb3a-8047494df832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105167237 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.105167237
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3532430091
Short name T199
Test name
Test status
Simulation time 19692438 ps
CPU time 1.12 seconds
Started Jan 24 03:44:55 PM PST 24
Finished Jan 24 03:44:57 PM PST 24
Peak memory 206468 kb
Host smart-545fe8e3-ec64-47ff-814d-efc862cd6b64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532430091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3532430091
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.765180725
Short name T331
Test name
Test status
Simulation time 458552237 ps
CPU time 4.47 seconds
Started Jan 24 03:44:41 PM PST 24
Finished Jan 24 03:44:46 PM PST 24
Peak memory 218088 kb
Host smart-93b9e6b4-a786-40ca-be94-350d6646dcb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765180725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.765180725
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3907992254
Short name T352
Test name
Test status
Simulation time 159690782 ps
CPU time 2.28 seconds
Started Jan 24 04:03:49 PM PST 24
Finished Jan 24 04:03:52 PM PST 24
Peak memory 206452 kb
Host smart-15326086-9179-4a47-82a5-bda955327c56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907992254 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3907992254
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2325990695
Short name T302
Test name
Test status
Simulation time 26161879 ps
CPU time 0.87 seconds
Started Jan 24 06:04:29 PM PST 24
Finished Jan 24 06:04:30 PM PST 24
Peak memory 206260 kb
Host smart-698da92d-f312-4f12-9ae4-0db66f180d8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325990695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2325990695
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2163565357
Short name T343
Test name
Test status
Simulation time 13898923 ps
CPU time 0.83 seconds
Started Jan 24 03:49:46 PM PST 24
Finished Jan 24 03:49:48 PM PST 24
Peak memory 206252 kb
Host smart-2eb62bca-8983-46eb-929d-1e41f8072add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163565357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2163565357
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.857873236
Short name T305
Test name
Test status
Simulation time 45612643 ps
CPU time 0.84 seconds
Started Jan 24 04:28:27 PM PST 24
Finished Jan 24 04:28:29 PM PST 24
Peak memory 206224 kb
Host smart-67fd3b99-3813-4834-a151-91ce7eaf7009
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857873236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.857873236
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.4140282668
Short name T360
Test name
Test status
Simulation time 15388650 ps
CPU time 0.89 seconds
Started Jan 24 03:49:57 PM PST 24
Finished Jan 24 03:50:02 PM PST 24
Peak memory 206204 kb
Host smart-617edae5-c5e3-4651-a396-9e2408ef40b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140282668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.4140282668
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3654124977
Short name T298
Test name
Test status
Simulation time 48014592 ps
CPU time 0.77 seconds
Started Jan 24 03:49:56 PM PST 24
Finished Jan 24 03:50:02 PM PST 24
Peak memory 206012 kb
Host smart-72c63c2f-4428-42da-8836-5759a89b1559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654124977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3654124977
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3922481166
Short name T216
Test name
Test status
Simulation time 12482809 ps
CPU time 0.84 seconds
Started Jan 24 03:49:55 PM PST 24
Finished Jan 24 03:50:01 PM PST 24
Peak memory 206256 kb
Host smart-3cfbcd35-2abb-4b05-92b5-72b9ce5f3d15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922481166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3922481166
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3253123885
Short name T290
Test name
Test status
Simulation time 19487322 ps
CPU time 0.81 seconds
Started Jan 24 03:49:56 PM PST 24
Finished Jan 24 03:50:01 PM PST 24
Peak memory 206020 kb
Host smart-22b03dbe-d104-4a56-bf4b-b2ffdf1704a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253123885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3253123885
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3123741505
Short name T294
Test name
Test status
Simulation time 38205163 ps
CPU time 0.82 seconds
Started Jan 24 03:49:58 PM PST 24
Finished Jan 24 03:50:06 PM PST 24
Peak memory 206228 kb
Host smart-d9646fb6-1132-486f-8a3c-74d54ead5292
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123741505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3123741505
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3929882532
Short name T288
Test name
Test status
Simulation time 34621128 ps
CPU time 0.84 seconds
Started Jan 24 03:49:54 PM PST 24
Finished Jan 24 03:50:01 PM PST 24
Peak memory 206268 kb
Host smart-a5cd9098-ad5e-4746-bc26-c44872fa97a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929882532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3929882532
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.4256604508
Short name T185
Test name
Test status
Simulation time 64378008 ps
CPU time 1.21 seconds
Started Jan 24 03:45:22 PM PST 24
Finished Jan 24 03:45:28 PM PST 24
Peak memory 206356 kb
Host smart-df7e1e14-f4db-49b0-9566-a37e4ae51719
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256604508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.4256604508
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3743654100
Short name T200
Test name
Test status
Simulation time 61420791 ps
CPU time 2.06 seconds
Started Jan 24 03:45:11 PM PST 24
Finished Jan 24 03:45:14 PM PST 24
Peak memory 206372 kb
Host smart-94803f14-8a78-49f2-bc54-dc4fed8f6d46
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743654100 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3743654100
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2572131396
Short name T357
Test name
Test status
Simulation time 65076155 ps
CPU time 0.92 seconds
Started Jan 24 03:55:05 PM PST 24
Finished Jan 24 03:55:09 PM PST 24
Peak memory 206300 kb
Host smart-d0496a60-6805-4453-b140-e594a86dec94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572131396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2572131396
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2601663998
Short name T303
Test name
Test status
Simulation time 42755358 ps
CPU time 0.9 seconds
Started Jan 24 03:45:28 PM PST 24
Finished Jan 24 03:45:30 PM PST 24
Peak memory 206332 kb
Host smart-8aa95466-3c46-464a-bb3c-b8f4d1123c14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601663998 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2601663998
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.184188392
Short name T84
Test name
Test status
Simulation time 29771828 ps
CPU time 0.8 seconds
Started Jan 24 03:45:12 PM PST 24
Finished Jan 24 03:45:13 PM PST 24
Peak memory 206144 kb
Host smart-6300b0d3-74ab-4289-a7f9-2008900e40e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184188392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.184188392
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1119862080
Short name T359
Test name
Test status
Simulation time 119290436 ps
CPU time 0.8 seconds
Started Jan 24 03:44:54 PM PST 24
Finished Jan 24 03:44:56 PM PST 24
Peak memory 206056 kb
Host smart-18662928-7cbb-4c3c-9449-8a8b5be1b3e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119862080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1119862080
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1444521826
Short name T329
Test name
Test status
Simulation time 60081591 ps
CPU time 1.07 seconds
Started Jan 24 03:45:20 PM PST 24
Finished Jan 24 03:45:23 PM PST 24
Peak memory 206428 kb
Host smart-80eb55fb-3409-490e-a620-67684dd15658
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444521826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1444521826
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.3802048946
Short name T147
Test name
Test status
Simulation time 87673258 ps
CPU time 1.57 seconds
Started Jan 24 03:44:55 PM PST 24
Finished Jan 24 03:44:58 PM PST 24
Peak memory 206436 kb
Host smart-12fd49b4-aaa1-4922-9086-9f30c29f3db1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802048946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.3802048946
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3617332163
Short name T195
Test name
Test status
Simulation time 89255186 ps
CPU time 0.84 seconds
Started Jan 24 03:50:02 PM PST 24
Finished Jan 24 03:50:08 PM PST 24
Peak memory 206080 kb
Host smart-808518fa-77da-4578-98b6-5cbb0557286c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617332163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3617332163
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3976543943
Short name T301
Test name
Test status
Simulation time 16404291 ps
CPU time 0.88 seconds
Started Jan 24 03:50:04 PM PST 24
Finished Jan 24 03:50:09 PM PST 24
Peak memory 206256 kb
Host smart-f53d7cbb-dc28-4663-a418-524ef57907bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976543943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3976543943
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3415984112
Short name T25
Test name
Test status
Simulation time 78817762 ps
CPU time 0.77 seconds
Started Jan 24 03:50:13 PM PST 24
Finished Jan 24 03:50:15 PM PST 24
Peak memory 206092 kb
Host smart-1b652e18-68ba-4c8d-82c2-4281913621e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415984112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3415984112
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.4230387818
Short name T317
Test name
Test status
Simulation time 48855456 ps
CPU time 0.86 seconds
Started Jan 24 03:50:13 PM PST 24
Finished Jan 24 03:50:15 PM PST 24
Peak memory 206272 kb
Host smart-1a82a3cc-4a94-4fa7-8cb9-0b3ec7c3df51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230387818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.4230387818
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.705604382
Short name T304
Test name
Test status
Simulation time 26191295 ps
CPU time 0.86 seconds
Started Jan 24 03:50:13 PM PST 24
Finished Jan 24 03:50:15 PM PST 24
Peak memory 206180 kb
Host smart-009561f5-360b-433a-8001-43268a51c6cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705604382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.705604382
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1096638085
Short name T300
Test name
Test status
Simulation time 22280382 ps
CPU time 0.85 seconds
Started Jan 24 03:50:19 PM PST 24
Finished Jan 24 03:50:23 PM PST 24
Peak memory 206260 kb
Host smart-c1eb3834-23e4-48cf-a562-ba9b393f6003
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096638085 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1096638085
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3421510983
Short name T335
Test name
Test status
Simulation time 13402127 ps
CPU time 0.85 seconds
Started Jan 24 03:50:19 PM PST 24
Finished Jan 24 03:50:22 PM PST 24
Peak memory 206280 kb
Host smart-b614d8f8-de17-4e57-9f94-bb958f737291
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421510983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3421510983
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.3000629778
Short name T345
Test name
Test status
Simulation time 38283023 ps
CPU time 0.76 seconds
Started Jan 24 03:50:19 PM PST 24
Finished Jan 24 03:50:22 PM PST 24
Peak memory 206056 kb
Host smart-ab85bf17-b849-4d7c-b920-9a595babfc98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000629778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.3000629778
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.4117291711
Short name T315
Test name
Test status
Simulation time 20529534 ps
CPU time 0.87 seconds
Started Jan 24 03:50:18 PM PST 24
Finished Jan 24 03:50:21 PM PST 24
Peak memory 206260 kb
Host smart-f41f1e3b-dcd7-4a62-81cd-f453bdd02c04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117291711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.4117291711
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3922483934
Short name T310
Test name
Test status
Simulation time 12307452 ps
CPU time 0.85 seconds
Started Jan 24 03:50:20 PM PST 24
Finished Jan 24 03:50:23 PM PST 24
Peak memory 206240 kb
Host smart-50296bc6-148b-4653-81c6-9c45028a93b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922483934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3922483934
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.813802376
Short name T187
Test name
Test status
Simulation time 72213147 ps
CPU time 1.42 seconds
Started Jan 24 03:45:47 PM PST 24
Finished Jan 24 03:45:51 PM PST 24
Peak memory 206312 kb
Host smart-776b42fe-e804-4d25-895d-51a5893c85dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813802376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.813802376
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.762335620
Short name T186
Test name
Test status
Simulation time 295366899 ps
CPU time 2.2 seconds
Started Jan 24 03:45:38 PM PST 24
Finished Jan 24 03:45:41 PM PST 24
Peak memory 206404 kb
Host smart-86089b95-8021-499d-998f-455e01ae7832
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762335620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.762335620
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3820965392
Short name T27
Test name
Test status
Simulation time 19293111 ps
CPU time 0.98 seconds
Started Jan 24 03:45:36 PM PST 24
Finished Jan 24 03:45:39 PM PST 24
Peak memory 206272 kb
Host smart-172c5439-e3c9-4f7d-b523-52f808dbcd12
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820965392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3820965392
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1253799122
Short name T293
Test name
Test status
Simulation time 21797123 ps
CPU time 1.18 seconds
Started Jan 24 03:45:46 PM PST 24
Finished Jan 24 03:45:50 PM PST 24
Peak memory 214600 kb
Host smart-e7c0b26d-152b-49c5-86dc-9ac3a5b03d50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253799122 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1253799122
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.4241108437
Short name T198
Test name
Test status
Simulation time 32108873 ps
CPU time 0.88 seconds
Started Jan 24 03:45:37 PM PST 24
Finished Jan 24 03:45:39 PM PST 24
Peak memory 206148 kb
Host smart-0d2eb334-61b4-4970-9b6a-b1a08a5f6c46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241108437 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.4241108437
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3860262021
Short name T953
Test name
Test status
Simulation time 44768108 ps
CPU time 0.86 seconds
Started Jan 24 03:45:37 PM PST 24
Finished Jan 24 03:45:39 PM PST 24
Peak memory 206252 kb
Host smart-eabd0267-fe67-4693-a6d0-42fcf65fd61b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860262021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3860262021
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2515410273
Short name T156
Test name
Test status
Simulation time 34014086 ps
CPU time 1.14 seconds
Started Jan 24 04:16:48 PM PST 24
Finished Jan 24 04:16:50 PM PST 24
Peak memory 206444 kb
Host smart-7c92bf6d-1ead-4a67-819f-baacb09b2718
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515410273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2515410273
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1327315924
Short name T166
Test name
Test status
Simulation time 31787014 ps
CPU time 1.26 seconds
Started Jan 24 03:45:29 PM PST 24
Finished Jan 24 03:45:31 PM PST 24
Peak memory 214700 kb
Host smart-25fde9ae-7822-46e6-aeaa-93a13c374e48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327315924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1327315924
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1374360029
Short name T29
Test name
Test status
Simulation time 87593899 ps
CPU time 1.55 seconds
Started Jan 24 03:45:41 PM PST 24
Finished Jan 24 03:45:43 PM PST 24
Peak memory 206276 kb
Host smart-5cf487e1-7561-404b-b8e4-517fed76e070
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374360029 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1374360029
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2488415082
Short name T306
Test name
Test status
Simulation time 39561155 ps
CPU time 0.83 seconds
Started Jan 24 03:50:19 PM PST 24
Finished Jan 24 03:50:22 PM PST 24
Peak memory 206064 kb
Host smart-057d1734-e2cc-46b8-97bc-8c0e74da3905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488415082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2488415082
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1328150779
Short name T339
Test name
Test status
Simulation time 14664367 ps
CPU time 0.91 seconds
Started Jan 24 03:50:20 PM PST 24
Finished Jan 24 03:50:23 PM PST 24
Peak memory 206224 kb
Host smart-8758ec2a-5189-4520-bd51-37181ba24031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328150779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1328150779
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1242024270
Short name T363
Test name
Test status
Simulation time 21551779 ps
CPU time 0.82 seconds
Started Jan 24 03:50:20 PM PST 24
Finished Jan 24 03:50:23 PM PST 24
Peak memory 206228 kb
Host smart-1ef28d64-ed0c-494c-9a7a-358bf9491774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242024270 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1242024270
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.298339689
Short name T351
Test name
Test status
Simulation time 17398673 ps
CPU time 0.91 seconds
Started Jan 24 03:50:19 PM PST 24
Finished Jan 24 03:50:23 PM PST 24
Peak memory 206180 kb
Host smart-248d23d7-168e-42ab-b0ba-8b3f2869584d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298339689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.298339689
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.1804945082
Short name T364
Test name
Test status
Simulation time 16730218 ps
CPU time 0.85 seconds
Started Jan 24 03:50:18 PM PST 24
Finished Jan 24 03:50:22 PM PST 24
Peak memory 206252 kb
Host smart-d4725866-16f0-4432-a574-ff4a86197a71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804945082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.1804945082
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.4158158017
Short name T355
Test name
Test status
Simulation time 17160804 ps
CPU time 0.88 seconds
Started Jan 24 03:50:30 PM PST 24
Finished Jan 24 03:50:34 PM PST 24
Peak memory 206268 kb
Host smart-4480000f-4c0b-46c1-a33d-8d8ed050db94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158158017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.4158158017
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3632830606
Short name T349
Test name
Test status
Simulation time 33486495 ps
CPU time 0.77 seconds
Started Jan 24 03:50:27 PM PST 24
Finished Jan 24 03:50:29 PM PST 24
Peak memory 206044 kb
Host smart-166ede36-cbad-4cae-9036-d4ca80c8887c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632830606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3632830606
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2785285918
Short name T51
Test name
Test status
Simulation time 12686838 ps
CPU time 0.87 seconds
Started Jan 24 03:50:27 PM PST 24
Finished Jan 24 03:50:29 PM PST 24
Peak memory 206228 kb
Host smart-bd72209b-0178-4995-ae4a-459e0df28dc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785285918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2785285918
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.821719258
Short name T26
Test name
Test status
Simulation time 28049638 ps
CPU time 1.35 seconds
Started Jan 24 03:45:46 PM PST 24
Finished Jan 24 03:45:50 PM PST 24
Peak memory 214624 kb
Host smart-caa2118c-a4f8-4059-a9ae-0baca72ccb62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821719258 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.821719258
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3725950064
Short name T188
Test name
Test status
Simulation time 46178770 ps
CPU time 0.83 seconds
Started Jan 24 03:45:46 PM PST 24
Finished Jan 24 03:45:50 PM PST 24
Peak memory 206304 kb
Host smart-980b1319-b1cd-4173-8d88-c56516f26c69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725950064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3725950064
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.847544392
Short name T291
Test name
Test status
Simulation time 19452902 ps
CPU time 0.81 seconds
Started Jan 24 04:27:42 PM PST 24
Finished Jan 24 04:27:45 PM PST 24
Peak memory 206244 kb
Host smart-edb7ed87-7fa9-41c7-b893-d623ded8f058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847544392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.847544392
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1775017989
Short name T292
Test name
Test status
Simulation time 148755697 ps
CPU time 1.13 seconds
Started Jan 24 03:45:48 PM PST 24
Finished Jan 24 03:45:52 PM PST 24
Peak memory 206320 kb
Host smart-62ba09f1-909e-4bdb-952a-6015cae3495c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775017989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1775017989
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3177531914
Short name T358
Test name
Test status
Simulation time 215879483 ps
CPU time 3.95 seconds
Started Jan 24 03:45:45 PM PST 24
Finished Jan 24 03:45:51 PM PST 24
Peak memory 214660 kb
Host smart-35010e08-ed46-4ecb-b8c3-0622b1db651f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177531914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3177531914
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2615173697
Short name T213
Test name
Test status
Simulation time 200768248 ps
CPU time 2.58 seconds
Started Jan 24 03:45:47 PM PST 24
Finished Jan 24 03:45:53 PM PST 24
Peak memory 206468 kb
Host smart-57d546d9-4c15-43d0-b87a-e1c7e10031e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615173697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2615173697
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1351847604
Short name T332
Test name
Test status
Simulation time 154771694 ps
CPU time 1.11 seconds
Started Jan 24 04:07:11 PM PST 24
Finished Jan 24 04:07:15 PM PST 24
Peak memory 214708 kb
Host smart-652ff947-d3aa-4104-b51f-e020d5686cb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351847604 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1351847604
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3338060402
Short name T342
Test name
Test status
Simulation time 25420875 ps
CPU time 0.83 seconds
Started Jan 24 04:36:35 PM PST 24
Finished Jan 24 04:36:38 PM PST 24
Peak memory 206152 kb
Host smart-9cfbd357-4ffa-4fac-8c2b-54cf3da1c627
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338060402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3338060402
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2061597209
Short name T50
Test name
Test status
Simulation time 45991485 ps
CPU time 0.83 seconds
Started Jan 24 03:45:57 PM PST 24
Finished Jan 24 03:46:02 PM PST 24
Peak memory 206228 kb
Host smart-351abe61-e109-4fd4-8a1a-efc82f92bdcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061597209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2061597209
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2575920142
Short name T153
Test name
Test status
Simulation time 326770410 ps
CPU time 1.33 seconds
Started Jan 24 04:05:25 PM PST 24
Finished Jan 24 04:05:27 PM PST 24
Peak memory 206392 kb
Host smart-777a55df-a9b0-401d-9ef0-2f77af324514
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575920142 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2575920142
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1256076651
Short name T326
Test name
Test status
Simulation time 222623515 ps
CPU time 2.29 seconds
Started Jan 24 04:24:49 PM PST 24
Finished Jan 24 04:24:53 PM PST 24
Peak memory 214656 kb
Host smart-cef4aec7-fa38-42a5-99cd-56f78717c671
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256076651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1256076651
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3839994553
Short name T353
Test name
Test status
Simulation time 90558113 ps
CPU time 2.32 seconds
Started Jan 24 03:45:45 PM PST 24
Finished Jan 24 03:45:50 PM PST 24
Peak memory 206384 kb
Host smart-701f7b2d-93d4-4ae1-a0e2-9655e0f08706
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839994553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3839994553
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1015164669
Short name T951
Test name
Test status
Simulation time 29129257 ps
CPU time 1.35 seconds
Started Jan 24 03:46:34 PM PST 24
Finished Jan 24 03:46:38 PM PST 24
Peak memory 214756 kb
Host smart-02a4ba42-0929-4bcb-a7e7-18db5f00e9d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015164669 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1015164669
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.2531468615
Short name T344
Test name
Test status
Simulation time 68468747 ps
CPU time 0.89 seconds
Started Jan 24 04:03:36 PM PST 24
Finished Jan 24 04:03:40 PM PST 24
Peak memory 206300 kb
Host smart-fb9442d7-53f9-49d7-a7ed-c92b1f746add
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531468615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.2531468615
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.884338459
Short name T314
Test name
Test status
Simulation time 15812875 ps
CPU time 0.85 seconds
Started Jan 24 04:44:38 PM PST 24
Finished Jan 24 04:44:40 PM PST 24
Peak memory 206268 kb
Host smart-18a5328b-c7c5-4bea-9955-062aeb6ed943
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884338459 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.884338459
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3284343189
Short name T194
Test name
Test status
Simulation time 46758750 ps
CPU time 0.99 seconds
Started Jan 24 03:46:35 PM PST 24
Finished Jan 24 03:46:41 PM PST 24
Peak memory 206360 kb
Host smart-143000d3-75a8-4346-81d8-124f5d1ce0a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284343189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3284343189
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2958089753
Short name T330
Test name
Test status
Simulation time 472910772 ps
CPU time 2.14 seconds
Started Jan 24 03:46:11 PM PST 24
Finished Jan 24 03:46:15 PM PST 24
Peak memory 214804 kb
Host smart-fedcaf4a-1b7d-4e3a-9d9e-b14bd09cfabb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958089753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2958089753
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.4165752918
Short name T347
Test name
Test status
Simulation time 63060179 ps
CPU time 1.6 seconds
Started Jan 24 03:46:34 PM PST 24
Finished Jan 24 03:46:37 PM PST 24
Peak memory 206336 kb
Host smart-2197167f-057b-47c5-84d3-4dda279b5a16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165752918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.4165752918
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2498612556
Short name T183
Test name
Test status
Simulation time 152209456 ps
CPU time 0.88 seconds
Started Jan 24 03:46:46 PM PST 24
Finished Jan 24 03:46:51 PM PST 24
Peak memory 206296 kb
Host smart-37734432-40e9-4a64-922b-d9bd586dbb4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498612556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2498612556
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2368635767
Short name T299
Test name
Test status
Simulation time 15216784 ps
CPU time 0.8 seconds
Started Jan 24 03:46:45 PM PST 24
Finished Jan 24 03:46:48 PM PST 24
Peak memory 206064 kb
Host smart-2f9169ed-3a9e-4066-8e59-e592bc380cf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368635767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2368635767
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2727291750
Short name T338
Test name
Test status
Simulation time 31319823 ps
CPU time 1.29 seconds
Started Jan 24 03:46:46 PM PST 24
Finished Jan 24 03:46:51 PM PST 24
Peak memory 206396 kb
Host smart-40cbfdc5-bda7-48c9-998b-42bacf3e5790
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727291750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2727291750
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1714190393
Short name T350
Test name
Test status
Simulation time 61675301 ps
CPU time 1.84 seconds
Started Jan 24 04:35:20 PM PST 24
Finished Jan 24 04:35:27 PM PST 24
Peak memory 214628 kb
Host smart-c004493c-319b-4ebd-b4a2-502fec750e88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714190393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1714190393
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1917076396
Short name T149
Test name
Test status
Simulation time 29977532 ps
CPU time 1.27 seconds
Started Jan 24 03:46:57 PM PST 24
Finished Jan 24 03:47:00 PM PST 24
Peak memory 214708 kb
Host smart-b3fcd01c-51c2-44d8-8469-9ddd47052456
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917076396 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1917076396
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2014349101
Short name T354
Test name
Test status
Simulation time 23186747 ps
CPU time 0.89 seconds
Started Jan 24 03:46:48 PM PST 24
Finished Jan 24 03:46:53 PM PST 24
Peak memory 206304 kb
Host smart-e4b9ed08-32ed-4712-b50a-bd108e91d42f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014349101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2014349101
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1604661685
Short name T171
Test name
Test status
Simulation time 12869664 ps
CPU time 0.86 seconds
Started Jan 24 04:01:52 PM PST 24
Finished Jan 24 04:01:55 PM PST 24
Peak memory 206252 kb
Host smart-225a69ac-494f-4139-9e70-7b7b6067a303
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604661685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1604661685
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1726387929
Short name T180
Test name
Test status
Simulation time 75584172 ps
CPU time 1.09 seconds
Started Jan 24 03:46:46 PM PST 24
Finished Jan 24 03:46:49 PM PST 24
Peak memory 206276 kb
Host smart-321a47b4-f052-4a56-84fb-51881296c8e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726387929 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1726387929
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2721693032
Short name T333
Test name
Test status
Simulation time 42987916 ps
CPU time 1.78 seconds
Started Jan 24 03:46:46 PM PST 24
Finished Jan 24 03:46:51 PM PST 24
Peak memory 214704 kb
Host smart-719c8b71-38f8-4bf5-8def-f0913fab930c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721693032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2721693032
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/default/0.edn_alert.1482902176
Short name T705
Test name
Test status
Simulation time 21097860 ps
CPU time 1.01 seconds
Started Jan 24 07:35:37 PM PST 24
Finished Jan 24 07:35:42 PM PST 24
Peak memory 205716 kb
Host smart-2abe1945-8dcd-4222-b3b5-20a463e60086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482902176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.1482902176
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.1573628255
Short name T636
Test name
Test status
Simulation time 16312417 ps
CPU time 0.94 seconds
Started Jan 24 10:25:07 PM PST 24
Finished Jan 24 10:25:11 PM PST 24
Peak memory 205060 kb
Host smart-33a9d0de-477a-4f5f-98f3-ef315eea3412
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573628255 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1573628255
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.524734346
Short name T833
Test name
Test status
Simulation time 45745495 ps
CPU time 1.06 seconds
Started Jan 24 10:48:43 PM PST 24
Finished Jan 24 10:48:45 PM PST 24
Peak memory 215036 kb
Host smart-fa7ef5de-3b63-4875-8326-8b5fb2301082
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524734346 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.524734346
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.456895237
Short name T466
Test name
Test status
Simulation time 23187103 ps
CPU time 0.89 seconds
Started Jan 24 09:08:21 PM PST 24
Finished Jan 24 09:08:24 PM PST 24
Peak memory 216056 kb
Host smart-0f50ad8f-6315-4e2b-875a-598ea09086a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456895237 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.456895237
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_regwen.3593069740
Short name T249
Test name
Test status
Simulation time 25734752 ps
CPU time 0.88 seconds
Started Jan 24 07:35:28 PM PST 24
Finished Jan 24 07:35:33 PM PST 24
Peak memory 206376 kb
Host smart-cec091b0-b463-4138-9a51-c565b88294eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593069740 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3593069740
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.601015237
Short name T561
Test name
Test status
Simulation time 20314392 ps
CPU time 0.88 seconds
Started Jan 24 07:35:33 PM PST 24
Finished Jan 24 07:35:37 PM PST 24
Peak memory 214584 kb
Host smart-85522cf2-5a94-4352-926a-49074869576c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601015237 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.601015237
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3780815986
Short name T533
Test name
Test status
Simulation time 125910541410 ps
CPU time 551.13 seconds
Started Jan 24 07:35:39 PM PST 24
Finished Jan 24 07:44:53 PM PST 24
Peak memory 216828 kb
Host smart-6ec3e980-3673-4002-adfa-7e54883a4c8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780815986 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3780815986
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1218032450
Short name T821
Test name
Test status
Simulation time 18921188 ps
CPU time 0.99 seconds
Started Jan 24 07:35:54 PM PST 24
Finished Jan 24 07:35:59 PM PST 24
Peak memory 206324 kb
Host smart-04ce2779-481d-42dd-b849-12884292935a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218032450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1218032450
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1146740669
Short name T650
Test name
Test status
Simulation time 30966545 ps
CPU time 0.91 seconds
Started Jan 24 07:35:53 PM PST 24
Finished Jan 24 07:35:56 PM PST 24
Peak memory 205112 kb
Host smart-d4cba0b6-50cb-41e4-9b4a-93b78af22049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146740669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1146740669
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.3301065694
Short name T449
Test name
Test status
Simulation time 13902290 ps
CPU time 0.89 seconds
Started Jan 24 07:35:51 PM PST 24
Finished Jan 24 07:35:55 PM PST 24
Peak memory 214948 kb
Host smart-c80f684b-6deb-4e3d-ba8d-7a745cd8df4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301065694 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3301065694
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1506292895
Short name T532
Test name
Test status
Simulation time 85577050 ps
CPU time 1.01 seconds
Started Jan 24 07:35:52 PM PST 24
Finished Jan 24 07:35:56 PM PST 24
Peak memory 215076 kb
Host smart-fd17bdc7-0df4-4987-8da5-15e187c23ed2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506292895 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1506292895
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_genbits.1450041057
Short name T511
Test name
Test status
Simulation time 39518419 ps
CPU time 1.09 seconds
Started Jan 24 07:35:39 PM PST 24
Finished Jan 24 07:35:43 PM PST 24
Peak memory 214732 kb
Host smart-08afd4e4-6219-4fee-9902-2256688e85f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450041057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1450041057
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.1683693522
Short name T93
Test name
Test status
Simulation time 19711098 ps
CPU time 1.03 seconds
Started Jan 24 07:35:52 PM PST 24
Finished Jan 24 07:35:56 PM PST 24
Peak memory 214968 kb
Host smart-4c13b0c2-98ca-4cf5-8126-2ab44c8fc203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683693522 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1683693522
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.523208381
Short name T66
Test name
Test status
Simulation time 1251552559 ps
CPU time 5.81 seconds
Started Jan 24 07:35:49 PM PST 24
Finished Jan 24 07:35:56 PM PST 24
Peak memory 233264 kb
Host smart-a86520d0-04ed-48f6-8ed5-36544f906c62
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523208381 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.523208381
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.4082571074
Short name T864
Test name
Test status
Simulation time 27017819 ps
CPU time 0.95 seconds
Started Jan 24 07:35:38 PM PST 24
Finished Jan 24 07:35:42 PM PST 24
Peak memory 214588 kb
Host smart-23389a47-0011-4e8e-8044-0311aa9932a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082571074 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.4082571074
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.4105053369
Short name T910
Test name
Test status
Simulation time 73198014 ps
CPU time 1.8 seconds
Started Jan 24 07:35:49 PM PST 24
Finished Jan 24 07:35:52 PM PST 24
Peak memory 214556 kb
Host smart-701baeeb-e468-4243-b918-56f8b5646aa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105053369 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.4105053369
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.4275793274
Short name T555
Test name
Test status
Simulation time 208823606557 ps
CPU time 2758.63 seconds
Started Jan 24 07:35:50 PM PST 24
Finished Jan 24 08:21:50 PM PST 24
Peak memory 230348 kb
Host smart-79d82475-bff0-48a0-a422-acf8e68c4476
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275793274 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.4275793274
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1641029621
Short name T628
Test name
Test status
Simulation time 19832181 ps
CPU time 0.97 seconds
Started Jan 24 07:51:29 PM PST 24
Finished Jan 24 07:51:31 PM PST 24
Peak memory 206368 kb
Host smart-1ccba366-d651-4163-be81-9f82d5d01fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641029621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1641029621
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.101236505
Short name T933
Test name
Test status
Simulation time 19134258 ps
CPU time 0.94 seconds
Started Jan 24 07:36:56 PM PST 24
Finished Jan 24 07:36:58 PM PST 24
Peak memory 205608 kb
Host smart-2e81b47e-cad3-41a0-8e22-27689541b459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101236505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.101236505
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.2183623282
Short name T672
Test name
Test status
Simulation time 19642654 ps
CPU time 0.85 seconds
Started Jan 24 07:36:50 PM PST 24
Finished Jan 24 07:36:51 PM PST 24
Peak memory 214744 kb
Host smart-c62ca24a-d72b-42a4-b783-1cb3c0b62871
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183623282 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2183623282
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3965712828
Short name T501
Test name
Test status
Simulation time 62365282 ps
CPU time 1.05 seconds
Started Jan 24 08:24:46 PM PST 24
Finished Jan 24 08:24:49 PM PST 24
Peak memory 214972 kb
Host smart-8e5c829c-a42a-453e-874d-f05bb977f73a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965712828 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3965712828
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.1142746518
Short name T819
Test name
Test status
Simulation time 35960176 ps
CPU time 1.32 seconds
Started Jan 24 07:36:52 PM PST 24
Finished Jan 24 07:36:55 PM PST 24
Peak memory 217452 kb
Host smart-b3a77191-212a-4702-bdaf-e5f648b0ed8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142746518 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1142746518
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.3838134696
Short name T843
Test name
Test status
Simulation time 533477305 ps
CPU time 4.84 seconds
Started Jan 24 09:21:51 PM PST 24
Finished Jan 24 09:22:00 PM PST 24
Peak memory 216188 kb
Host smart-9171c04c-bca1-4040-9d86-9ed95918708e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838134696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3838134696
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.454243912
Short name T546
Test name
Test status
Simulation time 18816243 ps
CPU time 1.15 seconds
Started Jan 24 09:09:46 PM PST 24
Finished Jan 24 09:09:51 PM PST 24
Peak memory 222156 kb
Host smart-5b47a6e4-ed89-44e7-b9d6-9700c96b519a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454243912 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.454243912
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1047352490
Short name T59
Test name
Test status
Simulation time 20271909 ps
CPU time 0.91 seconds
Started Jan 24 07:36:52 PM PST 24
Finished Jan 24 07:36:54 PM PST 24
Peak memory 214596 kb
Host smart-f5b20c5d-fbc0-472e-86e5-f72b24de1f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047352490 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1047352490
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.1374086204
Short name T2
Test name
Test status
Simulation time 211748316 ps
CPU time 3.61 seconds
Started Jan 24 07:36:46 PM PST 24
Finished Jan 24 07:36:50 PM PST 24
Peak memory 214700 kb
Host smart-2fefef43-0c70-4ad0-82a4-72ebcd9a4979
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374086204 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.1374086204
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.749139487
Short name T688
Test name
Test status
Simulation time 232191871419 ps
CPU time 910.13 seconds
Started Jan 24 07:36:50 PM PST 24
Finished Jan 24 07:52:01 PM PST 24
Peak memory 219964 kb
Host smart-c78c6311-21c4-47a4-a7f6-82f53118dd8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749139487 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.749139487
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.2909777560
Short name T110
Test name
Test status
Simulation time 18628934 ps
CPU time 1.17 seconds
Started Jan 24 07:43:03 PM PST 24
Finished Jan 24 07:43:06 PM PST 24
Peak memory 214612 kb
Host smart-f705bedd-177d-4d8f-a2b8-31bc861fbb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909777560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2909777560
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.885799480
Short name T832
Test name
Test status
Simulation time 25026216 ps
CPU time 1.58 seconds
Started Jan 24 07:43:03 PM PST 24
Finished Jan 24 07:43:07 PM PST 24
Peak memory 216028 kb
Host smart-10744c29-5385-43d9-8835-f329656c76ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885799480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.885799480
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.1281862710
Short name T655
Test name
Test status
Simulation time 80711943 ps
CPU time 1.13 seconds
Started Jan 24 07:43:00 PM PST 24
Finished Jan 24 07:43:02 PM PST 24
Peak memory 214960 kb
Host smart-3d3d2d12-1fff-42e3-b43c-4ec66b433766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281862710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1281862710
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.383354969
Short name T695
Test name
Test status
Simulation time 31221352 ps
CPU time 1.24 seconds
Started Jan 24 07:43:08 PM PST 24
Finished Jan 24 07:43:11 PM PST 24
Peak memory 214816 kb
Host smart-3df57dce-98bd-4c35-8479-bb009fe1ac56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383354969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.383354969
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.2994156485
Short name T781
Test name
Test status
Simulation time 18666919 ps
CPU time 1.05 seconds
Started Jan 24 10:12:17 PM PST 24
Finished Jan 24 10:12:19 PM PST 24
Peak memory 215028 kb
Host smart-80829242-27d0-4a44-87d6-d2f23d4458ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994156485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2994156485
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.429860895
Short name T448
Test name
Test status
Simulation time 58318013 ps
CPU time 1.18 seconds
Started Jan 24 07:43:13 PM PST 24
Finished Jan 24 07:43:15 PM PST 24
Peak memory 216216 kb
Host smart-8e045af5-10e4-476a-8780-a49e6777f9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429860895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.429860895
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.3825651959
Short name T588
Test name
Test status
Simulation time 17821504 ps
CPU time 1.11 seconds
Started Jan 24 07:43:13 PM PST 24
Finished Jan 24 07:43:16 PM PST 24
Peak memory 214916 kb
Host smart-d0e21ced-414f-45f9-9ed6-e81d54590177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825651959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3825651959
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.745041724
Short name T386
Test name
Test status
Simulation time 20543200 ps
CPU time 1.13 seconds
Started Jan 24 07:43:14 PM PST 24
Finished Jan 24 07:43:17 PM PST 24
Peak memory 216192 kb
Host smart-c998865f-c76e-413f-8829-6c5a781f640f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745041724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.745041724
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.107267052
Short name T857
Test name
Test status
Simulation time 21965456 ps
CPU time 1.32 seconds
Started Jan 24 07:43:12 PM PST 24
Finished Jan 24 07:43:14 PM PST 24
Peak memory 214728 kb
Host smart-47bc7177-1353-4287-a4ac-00019099de1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107267052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.107267052
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.467936718
Short name T553
Test name
Test status
Simulation time 38590971 ps
CPU time 0.87 seconds
Started Jan 24 07:37:06 PM PST 24
Finished Jan 24 07:37:08 PM PST 24
Peak memory 204908 kb
Host smart-1b8ccde7-86a4-4803-9e75-9cd16a541848
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467936718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.467936718
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.549619462
Short name T133
Test name
Test status
Simulation time 18260266 ps
CPU time 0.81 seconds
Started Jan 24 07:37:05 PM PST 24
Finished Jan 24 07:37:06 PM PST 24
Peak memory 214756 kb
Host smart-92316b2d-8b69-42c6-bbe3-2e2ab087b099
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549619462 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.549619462
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1591079683
Short name T119
Test name
Test status
Simulation time 33259808 ps
CPU time 1.19 seconds
Started Jan 24 07:37:06 PM PST 24
Finished Jan 24 07:37:08 PM PST 24
Peak memory 215036 kb
Host smart-32a9b158-2f82-48d0-903d-45bdc69a2346
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591079683 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1591079683
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.2384693617
Short name T715
Test name
Test status
Simulation time 19737007 ps
CPU time 1.12 seconds
Started Jan 24 07:37:05 PM PST 24
Finished Jan 24 07:37:07 PM PST 24
Peak memory 221768 kb
Host smart-94078413-f7f7-49a3-bd3d-3f939aa33abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384693617 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2384693617
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.4056972310
Short name T467
Test name
Test status
Simulation time 27477017 ps
CPU time 0.93 seconds
Started Jan 24 07:37:07 PM PST 24
Finished Jan 24 07:37:09 PM PST 24
Peak memory 214680 kb
Host smart-79d34827-5896-4b45-9f79-cee5a99dc929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056972310 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.4056972310
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.1841961710
Short name T468
Test name
Test status
Simulation time 18102020 ps
CPU time 0.89 seconds
Started Jan 24 07:37:05 PM PST 24
Finished Jan 24 07:37:07 PM PST 24
Peak memory 214620 kb
Host smart-34583718-7918-4222-986d-ee18fdffee3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841961710 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1841961710
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2044928124
Short name T508
Test name
Test status
Simulation time 269776865 ps
CPU time 2.75 seconds
Started Jan 24 07:37:03 PM PST 24
Finished Jan 24 07:37:07 PM PST 24
Peak memory 217736 kb
Host smart-42ca4f2e-4ec1-41e1-beb3-fb3ec84ac8fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044928124 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2044928124
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/110.edn_genbits.1508914514
Short name T871
Test name
Test status
Simulation time 26698419 ps
CPU time 1.01 seconds
Started Jan 24 07:43:13 PM PST 24
Finished Jan 24 07:43:15 PM PST 24
Peak memory 214708 kb
Host smart-7de14314-eab0-4d66-afe1-daf9b7fb4f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508914514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.1508914514
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.1834532759
Short name T942
Test name
Test status
Simulation time 74429020 ps
CPU time 1.07 seconds
Started Jan 24 07:43:11 PM PST 24
Finished Jan 24 07:43:13 PM PST 24
Peak memory 214812 kb
Host smart-33ed4064-6e2b-48a8-9f48-a0ccc18fe510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834532759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1834532759
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1822829682
Short name T866
Test name
Test status
Simulation time 19600979 ps
CPU time 1.13 seconds
Started Jan 25 02:13:13 AM PST 24
Finished Jan 25 02:13:15 AM PST 24
Peak memory 214792 kb
Host smart-d77e1031-9de0-4513-bdb8-db14a7d3f26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822829682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1822829682
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.734000033
Short name T276
Test name
Test status
Simulation time 118606705 ps
CPU time 0.98 seconds
Started Jan 24 07:43:12 PM PST 24
Finished Jan 24 07:43:15 PM PST 24
Peak memory 214708 kb
Host smart-8817aa5e-f06a-492a-8201-46fb0804218d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734000033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.734000033
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.418524582
Short name T418
Test name
Test status
Simulation time 66045400 ps
CPU time 1.05 seconds
Started Jan 24 07:43:11 PM PST 24
Finished Jan 24 07:43:13 PM PST 24
Peak memory 215080 kb
Host smart-afe757a1-09fa-4eb4-a9ab-8d3d73af404a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418524582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.418524582
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.1539423078
Short name T830
Test name
Test status
Simulation time 28298776 ps
CPU time 1.19 seconds
Started Jan 24 07:43:11 PM PST 24
Finished Jan 24 07:43:14 PM PST 24
Peak memory 214960 kb
Host smart-e997143b-7ef1-4303-a44c-45fd6de032df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539423078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1539423078
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.1622442154
Short name T366
Test name
Test status
Simulation time 17585479 ps
CPU time 1.07 seconds
Started Jan 24 07:43:12 PM PST 24
Finished Jan 24 07:43:14 PM PST 24
Peak memory 214736 kb
Host smart-6b7b97cd-8e70-4149-80c7-fd1b3a386a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622442154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1622442154
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.2685444562
Short name T72
Test name
Test status
Simulation time 44740874 ps
CPU time 1.26 seconds
Started Jan 24 07:43:20 PM PST 24
Finished Jan 24 07:43:22 PM PST 24
Peak memory 214888 kb
Host smart-e57dd4f0-102b-4a34-bddb-c60181cfaa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685444562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2685444562
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.1339845306
Short name T409
Test name
Test status
Simulation time 63656362 ps
CPU time 1.12 seconds
Started Jan 24 07:51:24 PM PST 24
Finished Jan 24 07:51:29 PM PST 24
Peak memory 214860 kb
Host smart-83e5a464-2722-42ba-8045-0316515d344b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339845306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1339845306
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.715054332
Short name T929
Test name
Test status
Simulation time 90121770 ps
CPU time 1.01 seconds
Started Jan 24 07:37:14 PM PST 24
Finished Jan 24 07:37:15 PM PST 24
Peak memory 206316 kb
Host smart-7773a486-d53d-4b53-8ac3-550114bc7e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715054332 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.715054332
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2939947958
Short name T928
Test name
Test status
Simulation time 22742323 ps
CPU time 0.83 seconds
Started Jan 24 07:37:18 PM PST 24
Finished Jan 24 07:37:20 PM PST 24
Peak memory 205912 kb
Host smart-8ca9601c-8dca-4425-be09-19077d2d3f93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939947958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2939947958
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.4265470406
Short name T759
Test name
Test status
Simulation time 24320617 ps
CPU time 0.9 seconds
Started Jan 24 07:37:24 PM PST 24
Finished Jan 24 07:37:26 PM PST 24
Peak memory 214896 kb
Host smart-85130f21-e76f-4061-ace7-94cc382502f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265470406 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.4265470406
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_genbits.4231571264
Short name T385
Test name
Test status
Simulation time 27953148 ps
CPU time 1.02 seconds
Started Jan 24 07:37:19 PM PST 24
Finished Jan 24 07:37:22 PM PST 24
Peak memory 216256 kb
Host smart-07cf4dbf-6071-496a-bc6a-0cb1c51f0d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231571264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.4231571264
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_smoke.2820084682
Short name T768
Test name
Test status
Simulation time 37229684 ps
CPU time 0.86 seconds
Started Jan 24 07:37:03 PM PST 24
Finished Jan 24 07:37:04 PM PST 24
Peak memory 214612 kb
Host smart-6659cc6c-c576-4d41-8478-725d88d36fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820084682 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2820084682
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3271721560
Short name T925
Test name
Test status
Simulation time 196166616 ps
CPU time 3.85 seconds
Started Jan 24 07:37:15 PM PST 24
Finished Jan 24 07:37:20 PM PST 24
Peak memory 214852 kb
Host smart-dd13c3d8-9407-453e-90a3-2b900c8010d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271721560 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3271721560
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1243855699
Short name T637
Test name
Test status
Simulation time 292704180823 ps
CPU time 555.88 seconds
Started Jan 24 07:37:20 PM PST 24
Finished Jan 24 07:46:38 PM PST 24
Peak memory 216868 kb
Host smart-83d33f12-9449-48f4-906e-ad91df364b53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243855699 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1243855699
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.2442558684
Short name T890
Test name
Test status
Simulation time 42352407 ps
CPU time 1.15 seconds
Started Jan 24 07:43:22 PM PST 24
Finished Jan 24 07:43:24 PM PST 24
Peak memory 214984 kb
Host smart-16354fac-f025-4b74-bd85-6f7458627794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442558684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2442558684
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.1429660922
Short name T742
Test name
Test status
Simulation time 31513044 ps
CPU time 1.47 seconds
Started Jan 24 07:43:16 PM PST 24
Finished Jan 24 07:43:19 PM PST 24
Peak memory 215000 kb
Host smart-401c251d-0446-4fe8-8752-c51149d905dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429660922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1429660922
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.375856594
Short name T126
Test name
Test status
Simulation time 128267065 ps
CPU time 1.24 seconds
Started Jan 24 07:43:21 PM PST 24
Finished Jan 24 07:43:23 PM PST 24
Peak memory 214740 kb
Host smart-29768fee-65c4-4a7e-812b-80f3809ff895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375856594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.375856594
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2651700958
Short name T41
Test name
Test status
Simulation time 476700099 ps
CPU time 4.71 seconds
Started Jan 24 07:43:24 PM PST 24
Finished Jan 24 07:43:30 PM PST 24
Peak memory 215044 kb
Host smart-33bb2427-21d6-41f6-bec2-e2bb27c3bb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651700958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2651700958
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.1143659034
Short name T239
Test name
Test status
Simulation time 137908797 ps
CPU time 1.3 seconds
Started Jan 24 07:43:17 PM PST 24
Finished Jan 24 07:43:20 PM PST 24
Peak memory 214688 kb
Host smart-c216f763-60a0-4530-a60f-1cbc84307c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143659034 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1143659034
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2694829757
Short name T104
Test name
Test status
Simulation time 46972533 ps
CPU time 1.01 seconds
Started Jan 24 07:43:24 PM PST 24
Finished Jan 24 07:43:26 PM PST 24
Peak memory 215088 kb
Host smart-5587429b-9c00-44db-807d-c8d96f611881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694829757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2694829757
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.2544906323
Short name T114
Test name
Test status
Simulation time 46413457 ps
CPU time 1.87 seconds
Started Jan 24 07:43:23 PM PST 24
Finished Jan 24 07:43:26 PM PST 24
Peak memory 216004 kb
Host smart-c534b06d-994e-4444-9910-89efc58e1830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544906323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2544906323
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.3892397133
Short name T3
Test name
Test status
Simulation time 300844910 ps
CPU time 3.87 seconds
Started Jan 24 07:43:21 PM PST 24
Finished Jan 24 07:43:26 PM PST 24
Peak memory 217468 kb
Host smart-937f6fca-f381-476a-8796-80fea0e2324d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892397133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3892397133
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.514621263
Short name T944
Test name
Test status
Simulation time 32206500 ps
CPU time 1.08 seconds
Started Jan 24 07:43:22 PM PST 24
Finished Jan 24 07:43:24 PM PST 24
Peak memory 214732 kb
Host smart-9a1c7553-eb2a-4e15-be69-01b4dacaada1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514621263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.514621263
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.1592299582
Short name T236
Test name
Test status
Simulation time 152576902 ps
CPU time 2.21 seconds
Started Jan 24 07:43:19 PM PST 24
Finished Jan 24 07:43:23 PM PST 24
Peak memory 216260 kb
Host smart-fda0ae7f-9601-40c1-802a-3ff23879dfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592299582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.1592299582
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.2046388222
Short name T256
Test name
Test status
Simulation time 37696010 ps
CPU time 1.02 seconds
Started Jan 24 07:37:24 PM PST 24
Finished Jan 24 07:37:26 PM PST 24
Peak memory 206280 kb
Host smart-93f0b7ca-b14a-4cb9-8e4c-25a6da099b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046388222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.2046388222
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.1911089716
Short name T440
Test name
Test status
Simulation time 76225704 ps
CPU time 0.85 seconds
Started Jan 24 07:38:23 PM PST 24
Finished Jan 24 07:38:26 PM PST 24
Peak memory 204944 kb
Host smart-a82941f6-a118-4316-ac04-88199d1f9b04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911089716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1911089716
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.2120398899
Short name T502
Test name
Test status
Simulation time 12664087 ps
CPU time 0.86 seconds
Started Jan 24 07:37:19 PM PST 24
Finished Jan 24 07:37:22 PM PST 24
Peak memory 214784 kb
Host smart-471ea06d-72cc-4983-8f03-71c2ca5f7b28
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120398899 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2120398899
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.4241517918
Short name T633
Test name
Test status
Simulation time 28400553 ps
CPU time 0.94 seconds
Started Jan 24 07:37:20 PM PST 24
Finished Jan 24 07:37:23 PM PST 24
Peak memory 214904 kb
Host smart-c434644f-4f7b-4f87-8645-fb3bd88f9ee4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241517918 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.4241517918
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.3171899668
Short name T799
Test name
Test status
Simulation time 24114659 ps
CPU time 0.89 seconds
Started Jan 24 07:37:18 PM PST 24
Finished Jan 24 07:37:19 PM PST 24
Peak memory 216276 kb
Host smart-25c355f3-b815-4139-a279-1461bf76373a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171899668 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.3171899668
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2452315077
Short name T592
Test name
Test status
Simulation time 13613099 ps
CPU time 1.03 seconds
Started Jan 24 07:37:18 PM PST 24
Finished Jan 24 07:37:20 PM PST 24
Peak memory 214912 kb
Host smart-7fe11843-51bb-4bb9-8eed-965c02714c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452315077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2452315077
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3080451560
Short name T530
Test name
Test status
Simulation time 25555170 ps
CPU time 0.97 seconds
Started Jan 24 07:37:15 PM PST 24
Finished Jan 24 07:37:16 PM PST 24
Peak memory 214888 kb
Host smart-339e3382-086c-4229-9b87-5619bff5c246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080451560 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3080451560
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.2259121973
Short name T365
Test name
Test status
Simulation time 19584811 ps
CPU time 0.87 seconds
Started Jan 24 07:37:19 PM PST 24
Finished Jan 24 07:37:21 PM PST 24
Peak memory 214596 kb
Host smart-06891a0f-cb67-407e-8793-6d39578c46d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259121973 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.2259121973
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.151667715
Short name T837
Test name
Test status
Simulation time 1603657853 ps
CPU time 2.97 seconds
Started Jan 24 07:37:18 PM PST 24
Finished Jan 24 07:37:22 PM PST 24
Peak memory 214836 kb
Host smart-923c8edb-b3c7-457e-b08d-3550ef961da7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151667715 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.151667715
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.3525055068
Short name T750
Test name
Test status
Simulation time 77988181603 ps
CPU time 1342.74 seconds
Started Jan 24 07:37:21 PM PST 24
Finished Jan 24 07:59:45 PM PST 24
Peak memory 219536 kb
Host smart-186c6022-da31-439c-9463-08a6929f6b16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525055068 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.3525055068
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.2639194530
Short name T816
Test name
Test status
Simulation time 37709719 ps
CPU time 1.09 seconds
Started Jan 24 07:43:24 PM PST 24
Finished Jan 24 07:43:26 PM PST 24
Peak memory 216012 kb
Host smart-9060206f-ac2c-40b6-9657-b7d6fa465966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639194530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2639194530
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.2022420314
Short name T749
Test name
Test status
Simulation time 62026045 ps
CPU time 1 seconds
Started Jan 24 08:25:27 PM PST 24
Finished Jan 24 08:25:29 PM PST 24
Peak memory 215044 kb
Host smart-743e0f89-b6ff-426f-9987-f9b7ba296dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022420314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2022420314
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.2951168556
Short name T479
Test name
Test status
Simulation time 38872253 ps
CPU time 1.08 seconds
Started Jan 24 07:43:23 PM PST 24
Finished Jan 24 07:43:25 PM PST 24
Peak memory 214896 kb
Host smart-32a4aefb-f6be-4eb3-be92-66e3ef0316b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951168556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.2951168556
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.960620767
Short name T721
Test name
Test status
Simulation time 49663589 ps
CPU time 0.94 seconds
Started Jan 24 07:43:23 PM PST 24
Finished Jan 24 07:43:24 PM PST 24
Peak memory 214776 kb
Host smart-ffe141ae-c247-41a4-96b2-298238c2ec8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960620767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.960620767
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.313897590
Short name T663
Test name
Test status
Simulation time 41909058 ps
CPU time 1.19 seconds
Started Jan 24 07:54:44 PM PST 24
Finished Jan 24 07:54:47 PM PST 24
Peak memory 214952 kb
Host smart-70d3f669-475a-498b-b081-ee9f3889e2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313897590 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.313897590
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.2912491233
Short name T557
Test name
Test status
Simulation time 88180272 ps
CPU time 1.19 seconds
Started Jan 24 07:43:24 PM PST 24
Finished Jan 24 07:43:26 PM PST 24
Peak memory 217592 kb
Host smart-c8b91c51-1f6f-4bb6-b09d-b6653fd5ee5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912491233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2912491233
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.374607141
Short name T35
Test name
Test status
Simulation time 49775182 ps
CPU time 1.12 seconds
Started Jan 24 09:33:16 PM PST 24
Finished Jan 24 09:33:18 PM PST 24
Peak memory 214908 kb
Host smart-da7e7f1c-659f-44c9-8359-fe48c54bc391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374607141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.374607141
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.1999746710
Short name T500
Test name
Test status
Simulation time 25167831 ps
CPU time 1 seconds
Started Jan 24 07:43:35 PM PST 24
Finished Jan 24 07:43:37 PM PST 24
Peak memory 215080 kb
Host smart-7798f757-fdaf-4071-ae12-af4d25085820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999746710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1999746710
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.2563251317
Short name T937
Test name
Test status
Simulation time 62721662 ps
CPU time 1.2 seconds
Started Jan 24 07:43:36 PM PST 24
Finished Jan 24 07:43:38 PM PST 24
Peak memory 216064 kb
Host smart-969332a4-f808-4fda-b22d-18bbf12ec587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563251317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2563251317
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3471329351
Short name T887
Test name
Test status
Simulation time 19521487 ps
CPU time 1.07 seconds
Started Jan 24 07:37:26 PM PST 24
Finished Jan 24 07:37:28 PM PST 24
Peak memory 206344 kb
Host smart-89ec99af-b3f7-4fac-9770-0d06121b9672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471329351 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3471329351
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_disable.3424594613
Short name T923
Test name
Test status
Simulation time 42398287 ps
CPU time 0.89 seconds
Started Jan 24 07:37:22 PM PST 24
Finished Jan 24 07:37:24 PM PST 24
Peak memory 214812 kb
Host smart-f92cabb2-3e06-4e24-9e86-7783c80ceca8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424594613 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3424594613
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.882234706
Short name T491
Test name
Test status
Simulation time 225997026 ps
CPU time 0.97 seconds
Started Jan 24 07:37:25 PM PST 24
Finished Jan 24 07:37:26 PM PST 24
Peak memory 214948 kb
Host smart-9237c692-180d-4ac5-8186-78385c76e92c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882234706 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.882234706
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.945652045
Short name T717
Test name
Test status
Simulation time 32717064 ps
CPU time 0.97 seconds
Started Jan 24 07:37:35 PM PST 24
Finished Jan 24 07:37:37 PM PST 24
Peak memory 216568 kb
Host smart-737090ba-6f12-4a87-9794-94bdc820284a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945652045 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.945652045
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2489336664
Short name T770
Test name
Test status
Simulation time 36672364 ps
CPU time 1.24 seconds
Started Jan 24 07:37:25 PM PST 24
Finished Jan 24 07:37:27 PM PST 24
Peak memory 214564 kb
Host smart-dd7d0272-7bea-474c-9692-b47a73033ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489336664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2489336664
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3286531426
Short name T793
Test name
Test status
Simulation time 22059857 ps
CPU time 0.94 seconds
Started Jan 24 07:37:25 PM PST 24
Finished Jan 24 07:37:27 PM PST 24
Peak memory 214884 kb
Host smart-f3fe9c6c-b069-4772-ac99-09607cbec202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286531426 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3286531426
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.69245723
Short name T124
Test name
Test status
Simulation time 40430597 ps
CPU time 0.92 seconds
Started Jan 24 07:37:17 PM PST 24
Finished Jan 24 07:37:19 PM PST 24
Peak memory 214616 kb
Host smart-9d84c0d4-320b-4a6e-a8fe-c8295e274aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69245723 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.69245723
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2877180687
Short name T823
Test name
Test status
Simulation time 116726192 ps
CPU time 1.96 seconds
Started Jan 24 07:37:14 PM PST 24
Finished Jan 24 07:37:17 PM PST 24
Peak memory 214696 kb
Host smart-b0459c76-929e-4d10-bfba-f33ba426b2e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877180687 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2877180687
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.620897372
Short name T430
Test name
Test status
Simulation time 205075863838 ps
CPU time 1291.81 seconds
Started Jan 24 07:37:19 PM PST 24
Finished Jan 24 07:58:52 PM PST 24
Peak memory 223128 kb
Host smart-e71ecda4-3993-4523-8430-decf4638461d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620897372 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.620897372
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.2934023303
Short name T690
Test name
Test status
Simulation time 79452945 ps
CPU time 1.15 seconds
Started Jan 24 07:51:04 PM PST 24
Finished Jan 24 07:51:14 PM PST 24
Peak memory 216016 kb
Host smart-71ebffc0-fdfe-420d-ac2a-614615c24d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934023303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2934023303
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.3114650077
Short name T604
Test name
Test status
Simulation time 32456560 ps
CPU time 0.98 seconds
Started Jan 24 07:43:34 PM PST 24
Finished Jan 24 07:43:36 PM PST 24
Peak memory 216116 kb
Host smart-8061dc33-0be5-4ec4-b0ad-593bf80e14cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114650077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3114650077
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.234156782
Short name T753
Test name
Test status
Simulation time 47416034 ps
CPU time 0.97 seconds
Started Jan 24 07:43:34 PM PST 24
Finished Jan 24 07:43:36 PM PST 24
Peak memory 214804 kb
Host smart-dda61f8c-2250-4800-ab1f-a0f33021f833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234156782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.234156782
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.2990785814
Short name T773
Test name
Test status
Simulation time 23037665 ps
CPU time 0.99 seconds
Started Jan 24 07:43:34 PM PST 24
Finished Jan 24 07:43:36 PM PST 24
Peak memory 214868 kb
Host smart-6260e463-e6e1-4c58-8f8d-cb7730d03f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990785814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2990785814
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.589427036
Short name T494
Test name
Test status
Simulation time 22873990 ps
CPU time 0.9 seconds
Started Jan 24 07:43:36 PM PST 24
Finished Jan 24 07:43:37 PM PST 24
Peak memory 214700 kb
Host smart-fda8655c-9d81-49e8-8781-e5c06f980f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589427036 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.589427036
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.1131271119
Short name T265
Test name
Test status
Simulation time 117465711 ps
CPU time 2.59 seconds
Started Jan 24 07:43:35 PM PST 24
Finished Jan 24 07:43:38 PM PST 24
Peak memory 216136 kb
Host smart-2077777e-9849-4b50-901c-0497a76a886f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131271119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1131271119
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.3164406625
Short name T794
Test name
Test status
Simulation time 251766150 ps
CPU time 1.31 seconds
Started Jan 24 07:43:41 PM PST 24
Finished Jan 24 07:43:43 PM PST 24
Peak memory 215084 kb
Host smart-e6b0d4b7-1bfb-46ca-9170-ebacb0f7b7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164406625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.3164406625
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1521432167
Short name T809
Test name
Test status
Simulation time 68179193 ps
CPU time 2.55 seconds
Started Jan 24 07:43:42 PM PST 24
Finished Jan 24 07:43:45 PM PST 24
Peak memory 217876 kb
Host smart-e9998fa0-c758-49b9-b946-e8f18f6a6285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521432167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1521432167
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert_test.162753152
Short name T609
Test name
Test status
Simulation time 14760623 ps
CPU time 0.92 seconds
Started Jan 24 07:37:25 PM PST 24
Finished Jan 24 07:37:26 PM PST 24
Peak memory 205608 kb
Host smart-6f34e3c4-06ba-4fdb-a15e-5726c8ef7972
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162753152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.162753152
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.375312249
Short name T65
Test name
Test status
Simulation time 14347983 ps
CPU time 0.91 seconds
Started Jan 24 07:37:24 PM PST 24
Finished Jan 24 07:37:26 PM PST 24
Peak memory 214952 kb
Host smart-59dec6f6-7a70-4bb8-90ef-7912f98d5f0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375312249 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.375312249
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.872244138
Short name T398
Test name
Test status
Simulation time 25223898 ps
CPU time 1.15 seconds
Started Jan 24 07:37:23 PM PST 24
Finished Jan 24 07:37:26 PM PST 24
Peak memory 216520 kb
Host smart-9f790c93-a7c5-4e20-b62b-2ca06339d453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872244138 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.872244138
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.985729728
Short name T477
Test name
Test status
Simulation time 113156376 ps
CPU time 2.66 seconds
Started Jan 24 07:37:26 PM PST 24
Finished Jan 24 07:37:29 PM PST 24
Peak memory 215152 kb
Host smart-07d98a44-3a2a-4be6-9d05-8cf4814e33d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985729728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.985729728
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1546266354
Short name T668
Test name
Test status
Simulation time 89663038 ps
CPU time 0.82 seconds
Started Jan 24 07:37:25 PM PST 24
Finished Jan 24 07:37:27 PM PST 24
Peak memory 214704 kb
Host smart-6c818090-ff8c-47ee-b3e8-384a629166ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546266354 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1546266354
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3760957498
Short name T416
Test name
Test status
Simulation time 12828972 ps
CPU time 0.91 seconds
Started Jan 24 07:37:22 PM PST 24
Finished Jan 24 07:37:24 PM PST 24
Peak memory 214580 kb
Host smart-529d5f2b-6cfe-462c-9435-1695cbe2bcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760957498 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3760957498
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1147776872
Short name T71
Test name
Test status
Simulation time 188621330 ps
CPU time 2.65 seconds
Started Jan 24 07:37:27 PM PST 24
Finished Jan 24 07:37:31 PM PST 24
Peak memory 217584 kb
Host smart-f020e99d-8a33-4494-acb7-8b0527081d7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147776872 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1147776872
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1792107250
Short name T873
Test name
Test status
Simulation time 61679633421 ps
CPU time 664.55 seconds
Started Jan 24 07:37:23 PM PST 24
Finished Jan 24 07:48:29 PM PST 24
Peak memory 216728 kb
Host smart-b6d5193c-af9b-4a31-9bd4-6e09a4504743
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792107250 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1792107250
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.3776227392
Short name T630
Test name
Test status
Simulation time 135536577 ps
CPU time 1.88 seconds
Started Jan 24 07:43:42 PM PST 24
Finished Jan 24 07:43:45 PM PST 24
Peak memory 216100 kb
Host smart-7646869f-d1c9-475a-a817-798b7428ec63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776227392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3776227392
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.847557701
Short name T60
Test name
Test status
Simulation time 17397691 ps
CPU time 1.03 seconds
Started Jan 24 07:57:24 PM PST 24
Finished Jan 24 07:57:27 PM PST 24
Peak memory 214904 kb
Host smart-d4018add-65b8-4b83-96e1-57b5d5fbd2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847557701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.847557701
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.3957490158
Short name T595
Test name
Test status
Simulation time 15353893 ps
CPU time 1.07 seconds
Started Jan 24 09:01:34 PM PST 24
Finished Jan 24 09:01:36 PM PST 24
Peak memory 216244 kb
Host smart-320813d4-284d-4c5a-864f-8e91dc0e3d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957490158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3957490158
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.1716303538
Short name T682
Test name
Test status
Simulation time 17565705 ps
CPU time 1.19 seconds
Started Jan 24 07:43:42 PM PST 24
Finished Jan 24 07:43:44 PM PST 24
Peak memory 216040 kb
Host smart-49b4a183-6019-4633-ae29-2adb9ddf393f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716303538 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1716303538
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.949078276
Short name T685
Test name
Test status
Simulation time 174893133 ps
CPU time 1.17 seconds
Started Jan 24 07:43:42 PM PST 24
Finished Jan 24 07:43:44 PM PST 24
Peak memory 214916 kb
Host smart-ae1b6fbe-ee3d-4fa0-955e-1b1263b3f912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949078276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.949078276
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.2086297799
Short name T497
Test name
Test status
Simulation time 59415418 ps
CPU time 2.43 seconds
Started Jan 24 07:43:54 PM PST 24
Finished Jan 24 07:43:57 PM PST 24
Peak memory 214840 kb
Host smart-84da80f3-b390-4dc5-a55d-d2f15044f42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086297799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2086297799
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.3243769224
Short name T46
Test name
Test status
Simulation time 47135962 ps
CPU time 1.22 seconds
Started Jan 24 07:43:51 PM PST 24
Finished Jan 24 07:43:53 PM PST 24
Peak memory 214600 kb
Host smart-4eaac460-36e2-49c2-97b1-18cf83c111c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243769224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3243769224
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.1337811304
Short name T286
Test name
Test status
Simulation time 52534963 ps
CPU time 0.94 seconds
Started Jan 24 07:43:48 PM PST 24
Finished Jan 24 07:43:49 PM PST 24
Peak memory 214872 kb
Host smart-cad2a290-0d34-4f19-9596-88dabda5eb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337811304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.1337811304
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.993653059
Short name T782
Test name
Test status
Simulation time 17704069 ps
CPU time 1.13 seconds
Started Jan 24 07:43:51 PM PST 24
Finished Jan 24 07:43:52 PM PST 24
Peak memory 214592 kb
Host smart-7fb0e3d4-7ab8-4cf6-9228-5c77e2baf6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993653059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.993653059
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.1664536984
Short name T679
Test name
Test status
Simulation time 27557604 ps
CPU time 1.26 seconds
Started Jan 24 07:43:53 PM PST 24
Finished Jan 24 07:43:54 PM PST 24
Peak memory 217300 kb
Host smart-a4df2fce-05bd-45d8-80ea-2a200dc93de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664536984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1664536984
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.395172271
Short name T607
Test name
Test status
Simulation time 32771317 ps
CPU time 0.94 seconds
Started Jan 24 07:37:36 PM PST 24
Finished Jan 24 07:37:38 PM PST 24
Peak memory 206396 kb
Host smart-09dffcaf-00c7-41e1-86d4-16cd6f626c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395172271 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.395172271
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2578848505
Short name T584
Test name
Test status
Simulation time 27138770 ps
CPU time 1.12 seconds
Started Jan 24 07:37:43 PM PST 24
Finished Jan 24 07:37:45 PM PST 24
Peak memory 205132 kb
Host smart-f04d470c-c8d3-4a20-8147-d1db06f24e61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578848505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2578848505
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3765433052
Short name T370
Test name
Test status
Simulation time 160202976 ps
CPU time 1.23 seconds
Started Jan 24 08:01:03 PM PST 24
Finished Jan 24 08:01:06 PM PST 24
Peak memory 215036 kb
Host smart-20362502-27b3-4157-90dc-660c5f313045
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765433052 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3765433052
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_intr.1025881003
Short name T562
Test name
Test status
Simulation time 19788512 ps
CPU time 1.04 seconds
Started Jan 24 07:37:32 PM PST 24
Finished Jan 24 07:37:34 PM PST 24
Peak memory 214860 kb
Host smart-f851db68-64b7-4d2e-897a-3e55b650196f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025881003 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1025881003
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.669679360
Short name T712
Test name
Test status
Simulation time 14841322 ps
CPU time 0.92 seconds
Started Jan 24 07:37:27 PM PST 24
Finished Jan 24 07:37:28 PM PST 24
Peak memory 214540 kb
Host smart-2c197257-b636-48ea-9a86-17fc0d11daca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669679360 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.669679360
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2432458464
Short name T496
Test name
Test status
Simulation time 109628798 ps
CPU time 2.84 seconds
Started Jan 24 07:37:27 PM PST 24
Finished Jan 24 07:37:31 PM PST 24
Peak memory 214832 kb
Host smart-ca6337bd-3484-4dbd-8ef8-e4bb473b9e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432458464 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2432458464
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.161480454
Short name T461
Test name
Test status
Simulation time 32309184130 ps
CPU time 742.35 seconds
Started Jan 24 07:37:33 PM PST 24
Finished Jan 24 07:49:56 PM PST 24
Peak memory 215676 kb
Host smart-63fa5525-4a86-4ae0-a429-bb9258261477
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161480454 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.161480454
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.1824078374
Short name T287
Test name
Test status
Simulation time 36843642 ps
CPU time 1.35 seconds
Started Jan 24 07:43:48 PM PST 24
Finished Jan 24 07:43:50 PM PST 24
Peak memory 214920 kb
Host smart-15a83348-3f3e-42be-920a-576b58c8898c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824078374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1824078374
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.4105405865
Short name T473
Test name
Test status
Simulation time 33247221 ps
CPU time 0.96 seconds
Started Jan 24 07:43:59 PM PST 24
Finished Jan 24 07:44:00 PM PST 24
Peak memory 214712 kb
Host smart-e37b1e58-d361-4eb8-9b89-129ce8c44bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105405865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.4105405865
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.1031091661
Short name T485
Test name
Test status
Simulation time 18505318 ps
CPU time 1.07 seconds
Started Jan 24 07:44:04 PM PST 24
Finished Jan 24 07:44:06 PM PST 24
Peak memory 214676 kb
Host smart-8849c978-b360-4817-956c-96d76d305531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031091661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1031091661
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.3052303446
Short name T269
Test name
Test status
Simulation time 93405702 ps
CPU time 2.06 seconds
Started Jan 24 07:43:58 PM PST 24
Finished Jan 24 07:44:01 PM PST 24
Peak memory 216056 kb
Host smart-ce229ddd-4c40-4260-a0e5-cc75f89fadec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052303446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3052303446
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.396941178
Short name T388
Test name
Test status
Simulation time 44103996 ps
CPU time 1.05 seconds
Started Jan 24 07:44:01 PM PST 24
Finished Jan 24 07:44:03 PM PST 24
Peak memory 214704 kb
Host smart-186f3e34-a314-47f1-a157-89cde292b4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396941178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.396941178
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3083023503
Short name T924
Test name
Test status
Simulation time 28751027 ps
CPU time 1.04 seconds
Started Jan 24 07:44:01 PM PST 24
Finished Jan 24 07:44:03 PM PST 24
Peak memory 214636 kb
Host smart-7546aa29-3aa7-4e6a-9f1f-04bfae54d81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083023503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3083023503
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.694923093
Short name T231
Test name
Test status
Simulation time 64494952 ps
CPU time 1.02 seconds
Started Jan 24 07:44:09 PM PST 24
Finished Jan 24 07:44:11 PM PST 24
Peak memory 214668 kb
Host smart-eea7497e-4cfa-4320-9d5f-a596835dbf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694923093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.694923093
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.1261800777
Short name T554
Test name
Test status
Simulation time 76357074 ps
CPU time 2.62 seconds
Started Jan 24 07:43:59 PM PST 24
Finished Jan 24 07:44:02 PM PST 24
Peak memory 217776 kb
Host smart-76e2d990-c5c2-4161-aa1d-1c9c3672aca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261800777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1261800777
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.1806759982
Short name T885
Test name
Test status
Simulation time 38251460 ps
CPU time 1.21 seconds
Started Jan 24 07:44:05 PM PST 24
Finished Jan 24 07:44:07 PM PST 24
Peak memory 215024 kb
Host smart-a6a9798a-491b-406f-8a86-cf8ad1011229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806759982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1806759982
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.4195476158
Short name T860
Test name
Test status
Simulation time 48418355 ps
CPU time 1.17 seconds
Started Jan 24 07:44:00 PM PST 24
Finished Jan 24 07:44:02 PM PST 24
Peak memory 214616 kb
Host smart-3bb95553-7328-47e8-8de3-f26868c708be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195476158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.4195476158
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert_test.1291298018
Short name T382
Test name
Test status
Simulation time 14535447 ps
CPU time 0.94 seconds
Started Jan 24 08:41:08 PM PST 24
Finished Jan 24 08:41:10 PM PST 24
Peak memory 205128 kb
Host smart-7dd109f6-1f8b-44a9-9c28-6c36925ce7ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291298018 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1291298018
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.4029110577
Short name T827
Test name
Test status
Simulation time 51531792 ps
CPU time 0.85 seconds
Started Jan 24 07:37:50 PM PST 24
Finished Jan 24 07:37:53 PM PST 24
Peak memory 214820 kb
Host smart-84db62a9-21a0-4a67-b4ca-18790b641147
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029110577 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.4029110577
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3839647880
Short name T867
Test name
Test status
Simulation time 43113838 ps
CPU time 1.04 seconds
Started Jan 24 07:37:49 PM PST 24
Finished Jan 24 07:37:52 PM PST 24
Peak memory 214904 kb
Host smart-2aeb52f4-6df2-4d7b-a18d-cc09fa96fe3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839647880 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3839647880
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.1308929158
Short name T428
Test name
Test status
Simulation time 22344306 ps
CPU time 0.93 seconds
Started Jan 24 07:37:49 PM PST 24
Finished Jan 24 07:37:51 PM PST 24
Peak memory 215972 kb
Host smart-103e6ec2-96aa-4847-a4fc-cc9ef6c4b4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308929158 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.1308929158
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2261508958
Short name T904
Test name
Test status
Simulation time 65434376 ps
CPU time 1.28 seconds
Started Jan 24 07:37:50 PM PST 24
Finished Jan 24 07:37:53 PM PST 24
Peak memory 216164 kb
Host smart-18287d8a-4333-4b1c-bd84-ddea1ffdab7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261508958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2261508958
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3531972201
Short name T537
Test name
Test status
Simulation time 19034897 ps
CPU time 1.08 seconds
Started Jan 24 07:55:32 PM PST 24
Finished Jan 24 07:55:34 PM PST 24
Peak memory 214908 kb
Host smart-bd0b8e7e-d181-475e-b26f-07f78841a0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531972201 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3531972201
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.1268129103
Short name T453
Test name
Test status
Simulation time 23099352 ps
CPU time 0.87 seconds
Started Jan 24 07:37:50 PM PST 24
Finished Jan 24 07:37:53 PM PST 24
Peak memory 214632 kb
Host smart-c5aed5dc-48a5-4325-9347-0951aecb8d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268129103 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.1268129103
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2071529421
Short name T486
Test name
Test status
Simulation time 139481316 ps
CPU time 3.17 seconds
Started Jan 24 07:37:43 PM PST 24
Finished Jan 24 07:37:47 PM PST 24
Peak memory 214728 kb
Host smart-ce349029-bb53-4128-8857-d87462ebb68f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071529421 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2071529421
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3486184434
Short name T217
Test name
Test status
Simulation time 283081987316 ps
CPU time 1795.44 seconds
Started Jan 24 07:37:51 PM PST 24
Finished Jan 24 08:07:48 PM PST 24
Peak memory 223548 kb
Host smart-b56455d9-108a-4d27-90d3-c453cf696de7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486184434 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3486184434
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.1527090226
Short name T619
Test name
Test status
Simulation time 54524793 ps
CPU time 0.99 seconds
Started Jan 24 07:44:09 PM PST 24
Finished Jan 24 07:44:11 PM PST 24
Peak memory 214532 kb
Host smart-c7662304-3e38-47ac-afb4-e79d06b2cf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527090226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1527090226
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.3041102680
Short name T445
Test name
Test status
Simulation time 46267040 ps
CPU time 1.12 seconds
Started Jan 24 07:44:00 PM PST 24
Finished Jan 24 07:44:02 PM PST 24
Peak memory 217292 kb
Host smart-5682c16c-e820-433d-b538-0cb2e3fc23dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041102680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3041102680
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.4283608141
Short name T946
Test name
Test status
Simulation time 230041948 ps
CPU time 2.93 seconds
Started Jan 24 07:44:05 PM PST 24
Finished Jan 24 07:44:08 PM PST 24
Peak memory 215012 kb
Host smart-ebfba5b8-7b78-4445-b0b8-485e3aacfe55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283608141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.4283608141
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.3399980257
Short name T415
Test name
Test status
Simulation time 84032412 ps
CPU time 1.19 seconds
Started Jan 24 07:43:59 PM PST 24
Finished Jan 24 07:44:01 PM PST 24
Peak memory 216068 kb
Host smart-869d0326-302b-44e0-8ccc-eb179f2b0e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399980257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3399980257
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.450096593
Short name T756
Test name
Test status
Simulation time 18492467 ps
CPU time 1.03 seconds
Started Jan 24 07:43:59 PM PST 24
Finished Jan 24 07:44:01 PM PST 24
Peak memory 214788 kb
Host smart-0c4b9f8e-0269-4b97-a52f-2fe68b67d871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450096593 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.450096593
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.478497299
Short name T422
Test name
Test status
Simulation time 23703717 ps
CPU time 1.23 seconds
Started Jan 24 07:44:09 PM PST 24
Finished Jan 24 07:44:11 PM PST 24
Peak memory 214964 kb
Host smart-9b8538fc-5e3f-4973-94ee-d36967e0bcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478497299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.478497299
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.3929719983
Short name T394
Test name
Test status
Simulation time 22668985 ps
CPU time 1.04 seconds
Started Jan 24 07:44:01 PM PST 24
Finished Jan 24 07:44:03 PM PST 24
Peak memory 215212 kb
Host smart-341d858e-6fb9-4bf7-9ccb-88d5af8bf62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929719983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3929719983
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.2782372682
Short name T274
Test name
Test status
Simulation time 75151058 ps
CPU time 1.23 seconds
Started Jan 24 07:44:00 PM PST 24
Finished Jan 24 07:44:02 PM PST 24
Peak memory 214972 kb
Host smart-dc40b1e2-6a9e-4e9f-8cd8-132a56c9a7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782372682 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2782372682
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.3779757997
Short name T512
Test name
Test status
Simulation time 18972458 ps
CPU time 1.07 seconds
Started Jan 24 07:44:03 PM PST 24
Finished Jan 24 07:44:05 PM PST 24
Peak memory 216280 kb
Host smart-fd26fbd8-094c-4a4a-87e3-76dc5fb0d4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779757997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3779757997
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.990741564
Short name T268
Test name
Test status
Simulation time 87229860 ps
CPU time 1.2 seconds
Started Jan 24 07:44:05 PM PST 24
Finished Jan 24 07:44:07 PM PST 24
Peak memory 216156 kb
Host smart-6dc4efe7-955d-456a-ae91-584dcaaff188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990741564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.990741564
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.2711719745
Short name T69
Test name
Test status
Simulation time 18982159 ps
CPU time 0.96 seconds
Started Jan 24 07:38:14 PM PST 24
Finished Jan 24 07:38:16 PM PST 24
Peak memory 205696 kb
Host smart-2e53543c-f2de-405f-ab70-3a05885787ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711719745 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2711719745
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3724456716
Short name T735
Test name
Test status
Simulation time 57547340 ps
CPU time 0.91 seconds
Started Jan 24 07:38:14 PM PST 24
Finished Jan 24 07:38:16 PM PST 24
Peak memory 205616 kb
Host smart-e6346b7d-82ac-4fd2-9a94-46cbfa61eb79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724456716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3724456716
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2039942627
Short name T635
Test name
Test status
Simulation time 14885661 ps
CPU time 0.93 seconds
Started Jan 24 07:38:01 PM PST 24
Finished Jan 24 07:38:04 PM PST 24
Peak memory 214968 kb
Host smart-1a10ec80-fd89-4388-8ca4-95fcd296eba7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039942627 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2039942627
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2485724834
Short name T754
Test name
Test status
Simulation time 49515061 ps
CPU time 1.09 seconds
Started Jan 24 07:38:00 PM PST 24
Finished Jan 24 07:38:02 PM PST 24
Peak memory 214976 kb
Host smart-6598fc0b-42e4-451a-9ed2-e62fe3b2fe00
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485724834 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2485724834
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.4201900348
Short name T839
Test name
Test status
Simulation time 18218417 ps
CPU time 1.11 seconds
Started Jan 24 07:38:01 PM PST 24
Finished Jan 24 07:38:03 PM PST 24
Peak memory 221684 kb
Host smart-e867cdf7-fad0-4d4c-a7ee-9370d0bc84c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201900348 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.4201900348
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3876640972
Short name T892
Test name
Test status
Simulation time 54772695 ps
CPU time 1.11 seconds
Started Jan 24 10:03:41 PM PST 24
Finished Jan 24 10:03:43 PM PST 24
Peak memory 216180 kb
Host smart-4c69b5e2-0e55-48e0-8140-9dd130d4b5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876640972 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3876640972
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1618216644
Short name T795
Test name
Test status
Simulation time 23347343 ps
CPU time 0.88 seconds
Started Jan 24 07:37:50 PM PST 24
Finished Jan 24 07:37:52 PM PST 24
Peak memory 214860 kb
Host smart-200a346f-22b7-41a0-b303-e415d2a2fad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618216644 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1618216644
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.797456612
Short name T374
Test name
Test status
Simulation time 46755315 ps
CPU time 0.88 seconds
Started Jan 24 07:37:54 PM PST 24
Finished Jan 24 07:37:56 PM PST 24
Peak memory 214604 kb
Host smart-993b33ae-9cef-42fe-8f9a-846d79f7c4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797456612 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.797456612
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3316120387
Short name T601
Test name
Test status
Simulation time 796636122 ps
CPU time 4.31 seconds
Started Jan 24 07:37:54 PM PST 24
Finished Jan 24 07:37:59 PM PST 24
Peak memory 214868 kb
Host smart-fd5499c0-36cc-45ba-bbc5-499c5ef8d3c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316120387 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3316120387
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1258315333
Short name T935
Test name
Test status
Simulation time 74303680096 ps
CPU time 946.81 seconds
Started Jan 24 07:37:57 PM PST 24
Finished Jan 24 07:53:44 PM PST 24
Peak memory 222976 kb
Host smart-21e85dc6-e92d-4d60-ad0b-c5c97bac8a91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258315333 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1258315333
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.3344258144
Short name T229
Test name
Test status
Simulation time 23990678 ps
CPU time 1.04 seconds
Started Jan 24 07:44:04 PM PST 24
Finished Jan 24 07:44:06 PM PST 24
Peak memory 215012 kb
Host smart-591e1634-30ad-48bb-a94f-abae48d90d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344258144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.3344258144
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.3077743607
Short name T811
Test name
Test status
Simulation time 96871838 ps
CPU time 1.33 seconds
Started Jan 24 07:44:05 PM PST 24
Finished Jan 24 07:44:07 PM PST 24
Peak memory 216132 kb
Host smart-a9c3be87-7836-43db-a776-1a4440cdeb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077743607 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3077743607
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.209969548
Short name T429
Test name
Test status
Simulation time 32321635 ps
CPU time 1 seconds
Started Jan 24 07:43:59 PM PST 24
Finished Jan 24 07:44:01 PM PST 24
Peak memory 214860 kb
Host smart-e64687e2-142b-493d-971b-0e43d738d23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209969548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.209969548
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.3227153254
Short name T558
Test name
Test status
Simulation time 31262291 ps
CPU time 1.02 seconds
Started Jan 24 08:54:06 PM PST 24
Finished Jan 24 08:54:08 PM PST 24
Peak memory 215036 kb
Host smart-4568da1a-e5a8-497c-ba61-eb42c834ec26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227153254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3227153254
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.2674659326
Short name T474
Test name
Test status
Simulation time 33910330 ps
CPU time 1.08 seconds
Started Jan 24 07:44:15 PM PST 24
Finished Jan 24 07:44:17 PM PST 24
Peak memory 215020 kb
Host smart-854cbced-7be4-42f7-bf17-6f60c85d1619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674659326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2674659326
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.1447885758
Short name T142
Test name
Test status
Simulation time 30525754 ps
CPU time 1.08 seconds
Started Jan 24 07:44:15 PM PST 24
Finished Jan 24 07:44:18 PM PST 24
Peak memory 214796 kb
Host smart-9be08f9d-848c-4682-a594-68550c7a3475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447885758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.1447885758
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.1004084258
Short name T404
Test name
Test status
Simulation time 160809288 ps
CPU time 1.13 seconds
Started Jan 24 07:44:16 PM PST 24
Finished Jan 24 07:44:19 PM PST 24
Peak memory 214760 kb
Host smart-74718a09-4053-419f-955e-c1695c5c1936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004084258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1004084258
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.1343906767
Short name T443
Test name
Test status
Simulation time 314738640 ps
CPU time 1.11 seconds
Started Jan 24 07:44:16 PM PST 24
Finished Jan 24 07:44:19 PM PST 24
Peak memory 214860 kb
Host smart-2adba8a2-476e-4cde-880f-a5b63900c36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343906767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1343906767
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1721996476
Short name T230
Test name
Test status
Simulation time 17085398 ps
CPU time 1.04 seconds
Started Jan 24 07:56:19 PM PST 24
Finished Jan 24 07:56:21 PM PST 24
Peak memory 215008 kb
Host smart-a2c2b9d3-6d54-44f9-be9e-a641e880c5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721996476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1721996476
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.1894836710
Short name T32
Test name
Test status
Simulation time 311873077 ps
CPU time 1.22 seconds
Started Jan 24 07:44:14 PM PST 24
Finished Jan 24 07:44:17 PM PST 24
Peak memory 214756 kb
Host smart-43fa1925-0e75-427d-a0dc-53708ade1a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894836710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.1894836710
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert_test.3453753956
Short name T522
Test name
Test status
Simulation time 52046653 ps
CPU time 0.85 seconds
Started Jan 24 07:38:10 PM PST 24
Finished Jan 24 07:38:13 PM PST 24
Peak memory 205024 kb
Host smart-593d989b-60b9-427d-bba4-ab1db1d666ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453753956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3453753956
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.784493253
Short name T829
Test name
Test status
Simulation time 91077194 ps
CPU time 0.97 seconds
Started Jan 24 07:38:06 PM PST 24
Finished Jan 24 07:38:08 PM PST 24
Peak memory 214896 kb
Host smart-6ad8c54d-b4e8-4dcd-9c1d-6c4124005551
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784493253 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.784493253
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.3888742709
Short name T548
Test name
Test status
Simulation time 25881676 ps
CPU time 0.84 seconds
Started Jan 24 07:38:10 PM PST 24
Finished Jan 24 07:38:12 PM PST 24
Peak memory 216216 kb
Host smart-2bd2bc0d-7c4e-4d6b-806c-89b5bfee66a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888742709 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3888742709
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1270559477
Short name T136
Test name
Test status
Simulation time 63324763 ps
CPU time 1.14 seconds
Started Jan 24 07:38:00 PM PST 24
Finished Jan 24 07:38:02 PM PST 24
Peak memory 214696 kb
Host smart-458eb2fc-ee3d-4565-8cc9-283857fd030c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270559477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1270559477
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3274025891
Short name T53
Test name
Test status
Simulation time 29458911 ps
CPU time 0.93 seconds
Started Jan 24 07:38:00 PM PST 24
Finished Jan 24 07:38:01 PM PST 24
Peak memory 221992 kb
Host smart-fda4d9a5-3238-4f95-a643-66bda157f63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274025891 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3274025891
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.979530213
Short name T31
Test name
Test status
Simulation time 21437093 ps
CPU time 0.87 seconds
Started Jan 24 07:38:01 PM PST 24
Finished Jan 24 07:38:03 PM PST 24
Peak memory 214628 kb
Host smart-f95e6a75-14e8-461b-a453-21263e4aa3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979530213 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.979530213
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1120651101
Short name T662
Test name
Test status
Simulation time 550064253 ps
CPU time 2.61 seconds
Started Jan 24 07:38:13 PM PST 24
Finished Jan 24 07:38:18 PM PST 24
Peak memory 214660 kb
Host smart-edd54ee7-7203-453b-b4b2-315d30c0057e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120651101 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1120651101
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.854803871
Short name T926
Test name
Test status
Simulation time 46842260962 ps
CPU time 1036.34 seconds
Started Jan 24 07:38:02 PM PST 24
Finished Jan 24 07:55:19 PM PST 24
Peak memory 223076 kb
Host smart-c2864d69-8154-4253-b86f-9c3f767146cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854803871 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.854803871
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.1639174768
Short name T406
Test name
Test status
Simulation time 70437365 ps
CPU time 1.01 seconds
Started Jan 24 07:44:13 PM PST 24
Finished Jan 24 07:44:14 PM PST 24
Peak memory 214896 kb
Host smart-0788c50f-2f94-4c38-b73c-c2ae42bb14ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639174768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1639174768
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.2692119928
Short name T640
Test name
Test status
Simulation time 15964444 ps
CPU time 1 seconds
Started Jan 24 07:44:14 PM PST 24
Finished Jan 24 07:44:16 PM PST 24
Peak memory 214844 kb
Host smart-28336e9e-7a7b-4bf4-972b-bf83b1089f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692119928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2692119928
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.1523551246
Short name T228
Test name
Test status
Simulation time 59596309 ps
CPU time 1.01 seconds
Started Jan 24 07:44:09 PM PST 24
Finished Jan 24 07:44:11 PM PST 24
Peak memory 214692 kb
Host smart-c36651b1-a5a5-4233-8dec-c1ae6974702c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523551246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1523551246
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3490413342
Short name T789
Test name
Test status
Simulation time 14546518 ps
CPU time 1.07 seconds
Started Jan 24 07:44:09 PM PST 24
Finished Jan 24 07:44:11 PM PST 24
Peak memory 216000 kb
Host smart-70b9f58a-cf54-4397-811f-cd327ee008c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490413342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3490413342
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.4152752057
Short name T105
Test name
Test status
Simulation time 62945438 ps
CPU time 2.46 seconds
Started Jan 24 07:44:13 PM PST 24
Finished Jan 24 07:44:16 PM PST 24
Peak memory 216220 kb
Host smart-6f5ed0e7-f955-4f84-bf8f-1929a118d05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152752057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.4152752057
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.562135395
Short name T436
Test name
Test status
Simulation time 155136290 ps
CPU time 2.16 seconds
Started Jan 24 07:44:10 PM PST 24
Finished Jan 24 07:44:13 PM PST 24
Peak memory 217624 kb
Host smart-6d19b4b0-24b1-47c1-bb07-5a06386bd600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562135395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.562135395
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.803702952
Short name T405
Test name
Test status
Simulation time 26402480 ps
CPU time 0.96 seconds
Started Jan 24 07:44:12 PM PST 24
Finished Jan 24 07:44:14 PM PST 24
Peak memory 214824 kb
Host smart-1237908b-923f-4364-a1f1-eed6735d8df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803702952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.803702952
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.2600456508
Short name T576
Test name
Test status
Simulation time 24385274 ps
CPU time 0.99 seconds
Started Jan 24 07:44:15 PM PST 24
Finished Jan 24 07:44:18 PM PST 24
Peak memory 214664 kb
Host smart-39c947cd-2a2f-4eff-8cc3-8fd17cb9ecf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600456508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2600456508
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.2722274717
Short name T465
Test name
Test status
Simulation time 84437196 ps
CPU time 2.07 seconds
Started Jan 24 07:44:12 PM PST 24
Finished Jan 24 07:44:14 PM PST 24
Peak memory 214932 kb
Host smart-9845a9fa-1e12-41e9-8051-d074182a8af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722274717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2722274717
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2922512706
Short name T920
Test name
Test status
Simulation time 39567016 ps
CPU time 0.94 seconds
Started Jan 24 07:46:15 PM PST 24
Finished Jan 24 07:46:17 PM PST 24
Peak memory 206320 kb
Host smart-9824e4d5-9d6d-4003-8b90-7f894f72633b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922512706 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2922512706
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.721362072
Short name T618
Test name
Test status
Simulation time 23599995 ps
CPU time 0.84 seconds
Started Jan 24 07:36:00 PM PST 24
Finished Jan 24 07:36:10 PM PST 24
Peak memory 205000 kb
Host smart-cc024c33-3367-4817-8253-ba5c9a627c39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721362072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.721362072
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3848733248
Short name T128
Test name
Test status
Simulation time 24921571 ps
CPU time 0.84 seconds
Started Jan 24 07:52:53 PM PST 24
Finished Jan 24 07:52:54 PM PST 24
Peak memory 214828 kb
Host smart-9ef6757d-3574-4809-875a-7e64612e4a29
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848733248 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3848733248
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.3524127098
Short name T523
Test name
Test status
Simulation time 50990859 ps
CPU time 1.17 seconds
Started Jan 24 07:45:28 PM PST 24
Finished Jan 24 07:45:34 PM PST 24
Peak memory 217472 kb
Host smart-b441be04-5338-46a5-a09f-b73ec3c77253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524127098 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.3524127098
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1526990620
Short name T39
Test name
Test status
Simulation time 13956289 ps
CPU time 1.1 seconds
Started Jan 24 07:35:56 PM PST 24
Finished Jan 24 07:36:00 PM PST 24
Peak memory 214604 kb
Host smart-d2d26d95-d828-4f6d-8668-a2f16df2c9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526990620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1526990620
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3711949079
Short name T5
Test name
Test status
Simulation time 22804663 ps
CPU time 1.04 seconds
Started Jan 24 07:35:56 PM PST 24
Finished Jan 24 07:36:00 PM PST 24
Peak memory 225924 kb
Host smart-f65026b4-13bc-4aa8-8eb4-0edd258f4d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711949079 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3711949079
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2777645550
Short name T67
Test name
Test status
Simulation time 1345025978 ps
CPU time 3.48 seconds
Started Jan 24 08:00:47 PM PST 24
Finished Jan 24 08:00:54 PM PST 24
Peak memory 232300 kb
Host smart-efee0650-a56e-4a02-bffd-071c57c8e5cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777645550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2777645550
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.2229344572
Short name T439
Test name
Test status
Simulation time 45735978 ps
CPU time 0.93 seconds
Started Jan 24 07:35:56 PM PST 24
Finished Jan 24 07:36:00 PM PST 24
Peak memory 214572 kb
Host smart-a6b60d59-b428-48f8-a711-cea75d664ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229344572 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.2229344572
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3209086313
Short name T569
Test name
Test status
Simulation time 1184901354 ps
CPU time 3.84 seconds
Started Jan 24 07:35:50 PM PST 24
Finished Jan 24 07:35:56 PM PST 24
Peak memory 214784 kb
Host smart-3fc2df0d-6a9f-4099-bcec-1b80b3bf2719
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209086313 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3209086313
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.245311098
Short name T107
Test name
Test status
Simulation time 13287770308 ps
CPU time 180.29 seconds
Started Jan 24 07:35:53 PM PST 24
Finished Jan 24 07:38:55 PM PST 24
Peak memory 216024 kb
Host smart-1f534e08-b084-4009-9af8-790ea5f07596
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245311098 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.245311098
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.47064429
Short name T420
Test name
Test status
Simulation time 17577078 ps
CPU time 0.96 seconds
Started Jan 24 07:38:13 PM PST 24
Finished Jan 24 07:38:16 PM PST 24
Peak memory 206300 kb
Host smart-dffa5953-4191-4e40-b7cf-0a399d899ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47064429 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.47064429
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1091338695
Short name T716
Test name
Test status
Simulation time 15258442 ps
CPU time 0.93 seconds
Started Jan 24 07:38:20 PM PST 24
Finished Jan 24 07:38:22 PM PST 24
Peak memory 205016 kb
Host smart-fa9e5875-66b0-4806-b2a6-521c3883fd41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091338695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1091338695
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.4256322474
Short name T481
Test name
Test status
Simulation time 17785809 ps
CPU time 0.88 seconds
Started Jan 24 07:38:23 PM PST 24
Finished Jan 24 07:38:26 PM PST 24
Peak memory 214832 kb
Host smart-54a628ec-8467-4367-b4f3-e49dea5529b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256322474 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.4256322474
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.4067599496
Short name T62
Test name
Test status
Simulation time 63546123 ps
CPU time 1.18 seconds
Started Jan 24 07:38:21 PM PST 24
Finished Jan 24 07:38:24 PM PST 24
Peak memory 214888 kb
Host smart-83b0a39b-af61-4ba2-b2b3-20c7535d6682
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067599496 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.4067599496
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1342085584
Short name T815
Test name
Test status
Simulation time 261294136 ps
CPU time 1.01 seconds
Started Jan 24 07:38:13 PM PST 24
Finished Jan 24 07:38:16 PM PST 24
Peak memory 217324 kb
Host smart-ada419d1-ed1c-434d-8c33-42f85a3927d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342085584 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1342085584
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2338511554
Short name T714
Test name
Test status
Simulation time 19326677 ps
CPU time 1.08 seconds
Started Jan 24 07:38:07 PM PST 24
Finished Jan 24 07:38:10 PM PST 24
Peak memory 216100 kb
Host smart-3af29783-a16b-41c5-9576-7e9483f252c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338511554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2338511554
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_smoke.3266478273
Short name T514
Test name
Test status
Simulation time 12601635 ps
CPU time 0.93 seconds
Started Jan 24 07:38:14 PM PST 24
Finished Jan 24 07:38:16 PM PST 24
Peak memory 214620 kb
Host smart-059217b9-2c10-4ab1-9e67-17423ec56979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266478273 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.3266478273
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1406098486
Short name T737
Test name
Test status
Simulation time 263598374 ps
CPU time 3.43 seconds
Started Jan 24 07:38:06 PM PST 24
Finished Jan 24 07:38:10 PM PST 24
Peak memory 214688 kb
Host smart-2d3657be-7aab-4b55-a8b6-cf63542f768a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406098486 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1406098486
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.297717560
Short name T840
Test name
Test status
Simulation time 65675471072 ps
CPU time 832.35 seconds
Started Jan 24 09:56:54 PM PST 24
Finished Jan 24 10:10:47 PM PST 24
Peak memory 218908 kb
Host smart-c2f3143c-a963-48e4-9195-f2ef0d40dd48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297717560 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.297717560
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2410999637
Short name T707
Test name
Test status
Simulation time 15824482 ps
CPU time 1.03 seconds
Started Jan 24 07:44:15 PM PST 24
Finished Jan 24 07:44:17 PM PST 24
Peak memory 214928 kb
Host smart-702c1d4f-33a7-4e75-9c3c-e06ffdc7787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410999637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2410999637
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2168420181
Short name T919
Test name
Test status
Simulation time 18255190 ps
CPU time 1.04 seconds
Started Jan 24 07:44:20 PM PST 24
Finished Jan 24 07:44:22 PM PST 24
Peak memory 214880 kb
Host smart-70e968ef-0081-4f93-87d5-5c984e656faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168420181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2168420181
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3432076060
Short name T852
Test name
Test status
Simulation time 310106333 ps
CPU time 1.34 seconds
Started Jan 24 07:59:48 PM PST 24
Finished Jan 24 07:59:53 PM PST 24
Peak memory 216296 kb
Host smart-d24d4c1a-e4a7-410d-928b-98f66348722c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432076060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3432076060
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2922570936
Short name T693
Test name
Test status
Simulation time 90500574 ps
CPU time 1.13 seconds
Started Jan 24 07:44:15 PM PST 24
Finished Jan 24 07:44:17 PM PST 24
Peak memory 214860 kb
Host smart-ddc36ad0-794f-482d-9d87-d985d28538de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922570936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2922570936
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.4014434237
Short name T605
Test name
Test status
Simulation time 32778383 ps
CPU time 1.02 seconds
Started Jan 24 08:29:06 PM PST 24
Finished Jan 24 08:29:08 PM PST 24
Peak memory 215092 kb
Host smart-87b2c63c-cd8c-48a0-9d7e-4c0c780af696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014434237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.4014434237
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3134238469
Short name T704
Test name
Test status
Simulation time 48454220 ps
CPU time 1.13 seconds
Started Jan 24 07:44:15 PM PST 24
Finished Jan 24 07:44:18 PM PST 24
Peak memory 214960 kb
Host smart-f0180939-37eb-4473-bd61-8f57677de6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134238469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3134238469
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.3719564813
Short name T373
Test name
Test status
Simulation time 36022421 ps
CPU time 1.02 seconds
Started Jan 24 08:01:27 PM PST 24
Finished Jan 24 08:01:29 PM PST 24
Peak memory 214720 kb
Host smart-ecaad688-20d0-4b02-874b-d4ae75950d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719564813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.3719564813
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2718047862
Short name T13
Test name
Test status
Simulation time 75709344 ps
CPU time 1.18 seconds
Started Jan 24 07:44:17 PM PST 24
Finished Jan 24 07:44:20 PM PST 24
Peak memory 216108 kb
Host smart-4ba4882d-8985-4b3d-86de-1f243790b1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718047862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2718047862
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3980447349
Short name T949
Test name
Test status
Simulation time 53282484 ps
CPU time 0.97 seconds
Started Jan 24 07:44:18 PM PST 24
Finished Jan 24 07:44:21 PM PST 24
Peak memory 214672 kb
Host smart-d39e621d-8cbb-48de-b847-9c781c4b61af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980447349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3980447349
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.1576482584
Short name T585
Test name
Test status
Simulation time 61672920 ps
CPU time 0.97 seconds
Started Jan 24 07:38:17 PM PST 24
Finished Jan 24 07:38:20 PM PST 24
Peak memory 206336 kb
Host smart-5efb581c-f303-47d3-b60e-b2fe250502b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576482584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1576482584
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3752390392
Short name T545
Test name
Test status
Simulation time 60441709 ps
CPU time 0.99 seconds
Started Jan 24 08:08:09 PM PST 24
Finished Jan 24 08:08:10 PM PST 24
Peak memory 205632 kb
Host smart-f7694531-c80a-4e56-8e2a-74444770a114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752390392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3752390392
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1264442938
Short name T905
Test name
Test status
Simulation time 13288952 ps
CPU time 0.93 seconds
Started Jan 24 07:38:21 PM PST 24
Finished Jan 24 07:38:23 PM PST 24
Peak memory 214944 kb
Host smart-88430d97-8483-4d50-bdcf-b89e2477e363
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264442938 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1264442938
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_err.462703919
Short name T452
Test name
Test status
Simulation time 51034044 ps
CPU time 1.07 seconds
Started Jan 24 07:38:20 PM PST 24
Finished Jan 24 07:38:23 PM PST 24
Peak memory 216476 kb
Host smart-447e57c2-cd5a-490d-920f-ea4a6ec9089d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462703919 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.462703919
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3336279920
Short name T535
Test name
Test status
Simulation time 31915264 ps
CPU time 1.14 seconds
Started Jan 24 07:38:16 PM PST 24
Finished Jan 24 07:38:19 PM PST 24
Peak memory 216244 kb
Host smart-2aece1f6-978a-44fd-9889-69722eba2679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336279920 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3336279920
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.4122491196
Short name T581
Test name
Test status
Simulation time 26097241 ps
CPU time 0.95 seconds
Started Jan 24 07:38:20 PM PST 24
Finished Jan 24 07:38:23 PM PST 24
Peak memory 214916 kb
Host smart-e0c146ed-7f63-4f46-bc79-bf27b5a26438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122491196 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.4122491196
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1917496879
Short name T61
Test name
Test status
Simulation time 41989560 ps
CPU time 0.86 seconds
Started Jan 24 07:38:17 PM PST 24
Finished Jan 24 07:38:20 PM PST 24
Peak memory 214604 kb
Host smart-f9e5bf1d-e96a-4dcf-a595-6fa7e5683d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917496879 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1917496879
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1329196092
Short name T515
Test name
Test status
Simulation time 265875341 ps
CPU time 1.95 seconds
Started Jan 24 07:38:21 PM PST 24
Finished Jan 24 07:38:25 PM PST 24
Peak memory 214648 kb
Host smart-c686b4ce-a1e3-40c2-a45f-2bc8f5fac7ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329196092 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1329196092
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1305152938
Short name T891
Test name
Test status
Simulation time 49417956114 ps
CPU time 1253 seconds
Started Jan 24 07:38:23 PM PST 24
Finished Jan 24 07:59:19 PM PST 24
Peak memory 222924 kb
Host smart-05d2764a-596e-4171-8d5a-b451287ed7df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305152938 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1305152938
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1528275549
Short name T402
Test name
Test status
Simulation time 78726924 ps
CPU time 1.12 seconds
Started Jan 24 07:44:17 PM PST 24
Finished Jan 24 07:44:20 PM PST 24
Peak memory 216236 kb
Host smart-618c67fe-3983-40f3-acac-4e999d7c0382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528275549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1528275549
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.328800058
Short name T894
Test name
Test status
Simulation time 17841411 ps
CPU time 1 seconds
Started Jan 24 07:44:27 PM PST 24
Finished Jan 24 07:44:28 PM PST 24
Peak memory 214604 kb
Host smart-95c81aa2-0e09-460e-bead-2154a21022ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328800058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.328800058
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2368929818
Short name T743
Test name
Test status
Simulation time 16369917 ps
CPU time 1.03 seconds
Started Jan 24 07:44:30 PM PST 24
Finished Jan 24 07:44:33 PM PST 24
Peak memory 216196 kb
Host smart-56f2ae9a-38f1-46e7-9d48-1d0fd1197584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368929818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2368929818
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3631430723
Short name T542
Test name
Test status
Simulation time 38314249 ps
CPU time 1.28 seconds
Started Jan 24 07:44:33 PM PST 24
Finished Jan 24 07:44:36 PM PST 24
Peak memory 216068 kb
Host smart-f79f55f7-eee3-414f-bb35-3d01451975fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631430723 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3631430723
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1123761922
Short name T779
Test name
Test status
Simulation time 308984256 ps
CPU time 4.08 seconds
Started Jan 24 07:44:27 PM PST 24
Finished Jan 24 07:44:32 PM PST 24
Peak memory 214900 kb
Host smart-97664f5b-c053-4e26-9279-927b4c725b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123761922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1123761922
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.457893520
Short name T285
Test name
Test status
Simulation time 16533966 ps
CPU time 0.98 seconds
Started Jan 24 07:44:30 PM PST 24
Finished Jan 24 07:44:33 PM PST 24
Peak memory 214636 kb
Host smart-4dccc70c-b095-4f19-a530-bb715a0bd3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457893520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.457893520
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1654697042
Short name T419
Test name
Test status
Simulation time 35518116 ps
CPU time 1.15 seconds
Started Jan 24 07:44:26 PM PST 24
Finished Jan 24 07:44:28 PM PST 24
Peak memory 216068 kb
Host smart-5ddea829-aea1-4b85-a541-c2ed5d87ae9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654697042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1654697042
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.1825997327
Short name T642
Test name
Test status
Simulation time 19806809 ps
CPU time 1.07 seconds
Started Jan 24 07:44:26 PM PST 24
Finished Jan 24 07:44:28 PM PST 24
Peak memory 214624 kb
Host smart-a92b20bb-fc29-416d-b9c8-036becc793c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825997327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.1825997327
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3017524939
Short name T653
Test name
Test status
Simulation time 31567010 ps
CPU time 1.11 seconds
Started Jan 24 08:00:22 PM PST 24
Finished Jan 24 08:00:27 PM PST 24
Peak memory 214984 kb
Host smart-5a7cbf87-ba4c-41bd-9108-e43901cdeb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017524939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3017524939
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3989977867
Short name T810
Test name
Test status
Simulation time 86773984 ps
CPU time 1.22 seconds
Started Jan 24 07:44:33 PM PST 24
Finished Jan 24 07:44:36 PM PST 24
Peak memory 214676 kb
Host smart-ec1b5947-1960-48ae-9d2d-07804f5f2262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989977867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3989977867
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert_test.782023906
Short name T659
Test name
Test status
Simulation time 14489174 ps
CPU time 0.89 seconds
Started Jan 24 07:38:20 PM PST 24
Finished Jan 24 07:38:23 PM PST 24
Peak memory 205004 kb
Host smart-0566d465-fc73-4fd4-b26e-524bef2afefb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782023906 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.782023906
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2544337729
Short name T658
Test name
Test status
Simulation time 41410370 ps
CPU time 1.02 seconds
Started Jan 24 07:38:17 PM PST 24
Finished Jan 24 07:38:19 PM PST 24
Peak memory 214952 kb
Host smart-ba696599-1921-4317-b0ef-ddd6457c2273
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544337729 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2544337729
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.662134021
Short name T78
Test name
Test status
Simulation time 32492627 ps
CPU time 0.91 seconds
Started Jan 24 07:38:19 PM PST 24
Finished Jan 24 07:38:21 PM PST 24
Peak memory 215896 kb
Host smart-f88d7b00-bc2f-4739-92f9-6e3d9cb5fdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662134021 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.662134021
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.3146741099
Short name T423
Test name
Test status
Simulation time 19011964 ps
CPU time 1.09 seconds
Started Jan 24 07:38:18 PM PST 24
Finished Jan 24 07:38:21 PM PST 24
Peak memory 214944 kb
Host smart-1a861b91-2df2-47c0-8cbf-cd929197915e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146741099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3146741099
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_smoke.220559373
Short name T369
Test name
Test status
Simulation time 35160983 ps
CPU time 0.88 seconds
Started Jan 24 07:38:18 PM PST 24
Finished Jan 24 07:38:20 PM PST 24
Peak memory 214596 kb
Host smart-947d9086-584c-4c3e-a9d6-c92c04c8f0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220559373 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.220559373
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2695754321
Short name T606
Test name
Test status
Simulation time 456319658 ps
CPU time 3.09 seconds
Started Jan 24 07:38:20 PM PST 24
Finished Jan 24 07:38:25 PM PST 24
Peak memory 214820 kb
Host smart-50c06486-e118-4d63-b27b-68a147fb3a94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695754321 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2695754321
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3887715954
Short name T101
Test name
Test status
Simulation time 332114260248 ps
CPU time 2083.36 seconds
Started Jan 24 07:38:23 PM PST 24
Finished Jan 24 08:13:09 PM PST 24
Peak memory 223160 kb
Host smart-9f1921a9-6f95-4ad8-ab09-138ec18f78e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887715954 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3887715954
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.738665585
Short name T612
Test name
Test status
Simulation time 98578961 ps
CPU time 1.05 seconds
Started Jan 24 07:44:33 PM PST 24
Finished Jan 24 07:44:36 PM PST 24
Peak memory 214696 kb
Host smart-0159a0fe-64b3-4a81-9bf0-cb500c1b80b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738665585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.738665585
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.583675785
Short name T648
Test name
Test status
Simulation time 28710415 ps
CPU time 1.25 seconds
Started Jan 24 07:44:39 PM PST 24
Finished Jan 24 07:44:42 PM PST 24
Peak memory 215096 kb
Host smart-07f189c9-227d-4fdb-bb91-f8b96662d082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583675785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.583675785
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.1976648360
Short name T708
Test name
Test status
Simulation time 49973753 ps
CPU time 1.92 seconds
Started Jan 24 07:44:32 PM PST 24
Finished Jan 24 07:44:35 PM PST 24
Peak memory 216200 kb
Host smart-314bbae2-d9c6-4484-b9b3-265fb607f9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976648360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1976648360
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1723916301
Short name T450
Test name
Test status
Simulation time 46612257 ps
CPU time 1.96 seconds
Started Jan 24 07:44:30 PM PST 24
Finished Jan 24 07:44:33 PM PST 24
Peak memory 215020 kb
Host smart-9bf87d12-e9b8-44c7-a352-ded2b8d0f5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723916301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1723916301
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.1220465395
Short name T603
Test name
Test status
Simulation time 25854070 ps
CPU time 0.96 seconds
Started Jan 24 08:41:58 PM PST 24
Finished Jan 24 08:42:00 PM PST 24
Peak memory 214668 kb
Host smart-684167bd-ec2a-4a40-851c-d0475cebe910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220465395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.1220465395
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2115997943
Short name T814
Test name
Test status
Simulation time 637343639 ps
CPU time 4.91 seconds
Started Jan 24 07:44:32 PM PST 24
Finished Jan 24 07:44:39 PM PST 24
Peak memory 214956 kb
Host smart-d547e0ac-b033-4465-b08b-4e64c9446ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115997943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2115997943
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2942953971
Short name T916
Test name
Test status
Simulation time 60353106 ps
CPU time 1.07 seconds
Started Jan 24 09:13:04 PM PST 24
Finished Jan 24 09:13:10 PM PST 24
Peak memory 215216 kb
Host smart-578ca8d9-4911-4e60-ba8e-153e9de2230f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942953971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2942953971
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2301686274
Short name T427
Test name
Test status
Simulation time 75331790 ps
CPU time 1.18 seconds
Started Jan 24 07:44:49 PM PST 24
Finished Jan 24 07:44:53 PM PST 24
Peak memory 215084 kb
Host smart-8e88bad6-1ec9-4615-8efb-8d2f95d9d2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301686274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2301686274
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.2289753865
Short name T375
Test name
Test status
Simulation time 16005942 ps
CPU time 1.03 seconds
Started Jan 24 09:03:28 PM PST 24
Finished Jan 24 09:03:29 PM PST 24
Peak memory 214976 kb
Host smart-3f753221-a4ea-497b-b154-967df691de05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289753865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2289753865
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3488069826
Short name T255
Test name
Test status
Simulation time 24856031 ps
CPU time 1.07 seconds
Started Jan 24 07:38:20 PM PST 24
Finished Jan 24 07:38:22 PM PST 24
Peak memory 206336 kb
Host smart-64a4eaa0-eabd-4c97-b472-439086eceb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488069826 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3488069826
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.423023980
Short name T921
Test name
Test status
Simulation time 66081728 ps
CPU time 0.84 seconds
Started Jan 24 08:16:44 PM PST 24
Finished Jan 24 08:16:46 PM PST 24
Peak memory 204864 kb
Host smart-3c1eb1aa-d3e6-47fa-ab57-a59f26331fbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423023980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.423023980
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1793236039
Short name T641
Test name
Test status
Simulation time 13908888 ps
CPU time 0.88 seconds
Started Jan 24 07:38:35 PM PST 24
Finished Jan 24 07:38:38 PM PST 24
Peak memory 215004 kb
Host smart-5a9018f3-0349-4f31-9416-967fff5b5394
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793236039 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1793236039
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3880017767
Short name T686
Test name
Test status
Simulation time 30747012 ps
CPU time 1.04 seconds
Started Jan 24 07:50:56 PM PST 24
Finished Jan 24 07:50:58 PM PST 24
Peak memory 215004 kb
Host smart-c2458f93-9126-459a-9161-fa5bf1e20619
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880017767 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3880017767
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.515555785
Short name T798
Test name
Test status
Simulation time 19131906 ps
CPU time 1.04 seconds
Started Jan 24 07:38:25 PM PST 24
Finished Jan 24 07:38:32 PM PST 24
Peak memory 215800 kb
Host smart-70995ff9-dca4-4bd2-a959-ee36d3873c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515555785 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.515555785
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.618477561
Short name T739
Test name
Test status
Simulation time 226603819 ps
CPU time 1.12 seconds
Started Jan 24 07:38:17 PM PST 24
Finished Jan 24 07:38:20 PM PST 24
Peak memory 216060 kb
Host smart-e062a35c-c288-43e5-8ae1-bdaf99e8fb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618477561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.618477561
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.2246323408
Short name T878
Test name
Test status
Simulation time 25778544 ps
CPU time 0.94 seconds
Started Jan 24 07:38:18 PM PST 24
Finished Jan 24 07:38:20 PM PST 24
Peak memory 214912 kb
Host smart-d25c2e26-0573-4191-b138-fa73ee6af7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246323408 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.2246323408
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3242924189
Short name T901
Test name
Test status
Simulation time 24546640 ps
CPU time 0.95 seconds
Started Jan 24 08:38:26 PM PST 24
Finished Jan 24 08:38:28 PM PST 24
Peak memory 214576 kb
Host smart-d19ff2d3-0551-45fd-86ca-07c10b804ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242924189 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3242924189
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.108623964
Short name T632
Test name
Test status
Simulation time 151097704 ps
CPU time 3.25 seconds
Started Jan 24 07:38:20 PM PST 24
Finished Jan 24 07:38:25 PM PST 24
Peak memory 214856 kb
Host smart-a1f76a99-2548-47e0-b933-7fd6a15c687d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108623964 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.108623964
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2999240477
Short name T391
Test name
Test status
Simulation time 69277484141 ps
CPU time 430.81 seconds
Started Jan 24 07:38:19 PM PST 24
Finished Jan 24 07:45:32 PM PST 24
Peak memory 215756 kb
Host smart-bbd4075d-408f-428e-9e8d-8116b922fded
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999240477 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2999240477
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2133270653
Short name T751
Test name
Test status
Simulation time 15933767 ps
CPU time 1 seconds
Started Jan 24 07:44:43 PM PST 24
Finished Jan 24 07:44:48 PM PST 24
Peak memory 214740 kb
Host smart-832476e1-70bb-41a4-ba9c-fdec6b1ba352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133270653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2133270653
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.666162816
Short name T493
Test name
Test status
Simulation time 23218560 ps
CPU time 1.15 seconds
Started Jan 24 09:20:22 PM PST 24
Finished Jan 24 09:20:24 PM PST 24
Peak memory 215052 kb
Host smart-aa192dfc-7d56-4e1e-9307-62b0edca6f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666162816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.666162816
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1025729266
Short name T684
Test name
Test status
Simulation time 36136637 ps
CPU time 1.17 seconds
Started Jan 24 08:10:03 PM PST 24
Finished Jan 24 08:10:06 PM PST 24
Peak memory 214996 kb
Host smart-6102f221-f061-476b-9888-e6773e75346a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025729266 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1025729266
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.889511778
Short name T701
Test name
Test status
Simulation time 61445440 ps
CPU time 1.49 seconds
Started Jan 24 07:44:45 PM PST 24
Finished Jan 24 07:44:49 PM PST 24
Peak memory 214464 kb
Host smart-45d12b05-13a1-440d-b750-2473351e5cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889511778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.889511778
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.3674286117
Short name T552
Test name
Test status
Simulation time 99133115 ps
CPU time 1.21 seconds
Started Jan 24 07:44:48 PM PST 24
Finished Jan 24 07:44:52 PM PST 24
Peak memory 216928 kb
Host smart-046e7823-e62f-4655-83a1-ff19ba626242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674286117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.3674286117
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3833206949
Short name T478
Test name
Test status
Simulation time 18254929 ps
CPU time 1.16 seconds
Started Jan 24 07:44:49 PM PST 24
Finished Jan 24 07:44:53 PM PST 24
Peak memory 216272 kb
Host smart-7def70ef-b702-410f-8984-0e3df3ebc3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833206949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3833206949
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2646050260
Short name T273
Test name
Test status
Simulation time 89590959 ps
CPU time 1.57 seconds
Started Jan 24 07:44:48 PM PST 24
Finished Jan 24 07:44:53 PM PST 24
Peak memory 217516 kb
Host smart-62bf34bf-2fd6-45ae-9b96-dc1dd0fc7a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646050260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2646050260
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3822124990
Short name T608
Test name
Test status
Simulation time 24987568 ps
CPU time 0.95 seconds
Started Jan 24 07:44:46 PM PST 24
Finished Jan 24 07:44:51 PM PST 24
Peak memory 214940 kb
Host smart-df93de2c-1440-461c-9849-d1894f00e373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822124990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3822124990
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.579156388
Short name T68
Test name
Test status
Simulation time 49980425 ps
CPU time 0.97 seconds
Started Jan 24 07:44:48 PM PST 24
Finished Jan 24 07:44:53 PM PST 24
Peak memory 214756 kb
Host smart-bdfd4ad1-a2f5-4730-b713-b470347bc04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579156388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.579156388
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3719689065
Short name T747
Test name
Test status
Simulation time 20122773 ps
CPU time 1.01 seconds
Started Jan 24 07:38:38 PM PST 24
Finished Jan 24 07:38:41 PM PST 24
Peak memory 206332 kb
Host smart-4dd40d52-b1ea-4585-b1fb-900396fa15be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719689065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3719689065
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.1990965495
Short name T516
Test name
Test status
Simulation time 34779516 ps
CPU time 0.94 seconds
Started Jan 24 07:38:48 PM PST 24
Finished Jan 24 07:38:57 PM PST 24
Peak memory 205620 kb
Host smart-17eea2db-05e7-4f2c-8af8-ddb5abf46a80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990965495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1990965495
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.139287923
Short name T785
Test name
Test status
Simulation time 18003998 ps
CPU time 0.81 seconds
Started Jan 24 07:38:47 PM PST 24
Finished Jan 24 07:38:57 PM PST 24
Peak memory 214800 kb
Host smart-265c15b2-1f59-4a27-aaca-50059d278f56
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139287923 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.139287923
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1734596966
Short name T393
Test name
Test status
Simulation time 23047330 ps
CPU time 1.1 seconds
Started Jan 24 07:38:43 PM PST 24
Finished Jan 24 07:38:52 PM PST 24
Peak memory 215036 kb
Host smart-2e69130a-6e9b-42cd-a4c2-69922194b73e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734596966 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1734596966
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.545200422
Short name T709
Test name
Test status
Simulation time 23401076 ps
CPU time 0.98 seconds
Started Jan 24 07:50:02 PM PST 24
Finished Jan 24 07:50:04 PM PST 24
Peak memory 216488 kb
Host smart-94b71507-f65c-400b-8d00-ee61fe0a274c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545200422 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.545200422
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.4169142309
Short name T282
Test name
Test status
Simulation time 26813837 ps
CPU time 1.23 seconds
Started Jan 24 08:52:05 PM PST 24
Finished Jan 24 08:52:08 PM PST 24
Peak memory 216072 kb
Host smart-9bfa4ce6-0ce0-4b8f-8351-f985001c7bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169142309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.4169142309
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.307513606
Short name T94
Test name
Test status
Simulation time 48705075 ps
CPU time 0.83 seconds
Started Jan 24 08:18:30 PM PST 24
Finished Jan 24 08:18:32 PM PST 24
Peak memory 214756 kb
Host smart-69dc4d5b-cc1c-46b8-afb5-ca1fa3a3a86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307513606 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.307513606
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.4116537170
Short name T463
Test name
Test status
Simulation time 21967702 ps
CPU time 0.88 seconds
Started Jan 24 07:38:26 PM PST 24
Finished Jan 24 07:38:33 PM PST 24
Peak memory 214592 kb
Host smart-2222165b-ca07-4f3e-ae90-83a2dbb82f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116537170 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.4116537170
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.1038722290
Short name T645
Test name
Test status
Simulation time 1187368991 ps
CPU time 4.99 seconds
Started Jan 24 07:51:26 PM PST 24
Finished Jan 24 07:51:34 PM PST 24
Peak memory 214692 kb
Host smart-c83c8400-096c-43db-a2fe-dece1b17edb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038722290 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.1038722290
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.519831457
Short name T683
Test name
Test status
Simulation time 47199574926 ps
CPU time 543.89 seconds
Started Jan 24 08:22:19 PM PST 24
Finished Jan 24 08:31:26 PM PST 24
Peak memory 216272 kb
Host smart-6dfa8124-d022-427e-8bc3-15f4f5c7c399
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519831457 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.519831457
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.972050519
Short name T703
Test name
Test status
Simulation time 18991471 ps
CPU time 1.01 seconds
Started Jan 24 07:44:49 PM PST 24
Finished Jan 24 07:44:53 PM PST 24
Peak memory 214876 kb
Host smart-865afd20-9f99-4ae9-b855-ab877ba63911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972050519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.972050519
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1193876906
Short name T582
Test name
Test status
Simulation time 139180813 ps
CPU time 1.01 seconds
Started Jan 24 07:44:48 PM PST 24
Finished Jan 24 07:44:52 PM PST 24
Peak memory 214720 kb
Host smart-29add109-6309-40c2-9f58-60a5e6c93736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193876906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1193876906
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1671010686
Short name T884
Test name
Test status
Simulation time 26672495 ps
CPU time 1.07 seconds
Started Jan 24 07:44:47 PM PST 24
Finished Jan 24 07:44:52 PM PST 24
Peak memory 214956 kb
Host smart-5646c2f5-a13d-4198-b4b1-099ea9c5cd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671010686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1671010686
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1755726522
Short name T859
Test name
Test status
Simulation time 49900871 ps
CPU time 1.75 seconds
Started Jan 24 07:44:50 PM PST 24
Finished Jan 24 07:44:54 PM PST 24
Peak memory 216176 kb
Host smart-7d0db71e-0344-4484-ae30-00cac751013b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755726522 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1755726522
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.692644847
Short name T787
Test name
Test status
Simulation time 18622709 ps
CPU time 1 seconds
Started Jan 24 07:44:49 PM PST 24
Finished Jan 24 07:44:53 PM PST 24
Peak memory 214812 kb
Host smart-823a538c-04d4-46f9-a901-2d2038638d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692644847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.692644847
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.4150176594
Short name T74
Test name
Test status
Simulation time 20338004 ps
CPU time 1.17 seconds
Started Jan 24 07:45:04 PM PST 24
Finished Jan 24 07:45:08 PM PST 24
Peak memory 214744 kb
Host smart-cafe0560-3134-4301-9da9-c0c0e65b1528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150176594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.4150176594
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1141635748
Short name T697
Test name
Test status
Simulation time 15124934 ps
CPU time 1.06 seconds
Started Jan 24 07:44:50 PM PST 24
Finished Jan 24 07:44:53 PM PST 24
Peak memory 214800 kb
Host smart-9cb7b372-9ce0-4c2c-86f7-e314099eda4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141635748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1141635748
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1483883228
Short name T876
Test name
Test status
Simulation time 41403899 ps
CPU time 0.95 seconds
Started Jan 24 07:44:50 PM PST 24
Finished Jan 24 07:44:53 PM PST 24
Peak memory 214692 kb
Host smart-97152a9f-3374-46c2-aa03-5053b200cf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483883228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1483883228
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3652618239
Short name T531
Test name
Test status
Simulation time 15891936 ps
CPU time 1.08 seconds
Started Jan 24 07:44:51 PM PST 24
Finished Jan 24 07:44:53 PM PST 24
Peak memory 214720 kb
Host smart-16b7751a-eca6-4d9e-a3c2-acce9f2c1978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652618239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3652618239
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.4161022142
Short name T888
Test name
Test status
Simulation time 74323088 ps
CPU time 1.81 seconds
Started Jan 24 07:44:49 PM PST 24
Finished Jan 24 07:44:54 PM PST 24
Peak memory 216072 kb
Host smart-ece7637f-76c5-444c-9d74-2c1b6b8cef6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161022142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.4161022142
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3031998769
Short name T252
Test name
Test status
Simulation time 18490045 ps
CPU time 1.03 seconds
Started Jan 24 07:38:44 PM PST 24
Finished Jan 24 07:38:52 PM PST 24
Peak memory 205732 kb
Host smart-9d512683-4638-4ef0-96ff-1acc4a996ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031998769 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3031998769
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1117338443
Short name T881
Test name
Test status
Simulation time 27790037 ps
CPU time 0.99 seconds
Started Jan 24 07:38:42 PM PST 24
Finished Jan 24 07:38:52 PM PST 24
Peak memory 204968 kb
Host smart-cf8ea9bf-759e-4bb3-930d-3a1419d19c7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117338443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1117338443
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.1002662014
Short name T727
Test name
Test status
Simulation time 12722404 ps
CPU time 0.87 seconds
Started Jan 24 07:38:42 PM PST 24
Finished Jan 24 07:38:52 PM PST 24
Peak memory 214744 kb
Host smart-14dcb9a8-4c9e-4ac8-8e03-a3f031f31481
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002662014 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1002662014
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2809368847
Short name T432
Test name
Test status
Simulation time 26285673 ps
CPU time 1.09 seconds
Started Jan 24 07:38:46 PM PST 24
Finished Jan 24 07:38:57 PM PST 24
Peak memory 215036 kb
Host smart-6b3f4dbf-d234-4d2b-b182-31cfc4b7e82e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809368847 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2809368847
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1401388471
Short name T79
Test name
Test status
Simulation time 29986850 ps
CPU time 0.84 seconds
Started Jan 24 07:38:46 PM PST 24
Finished Jan 24 07:38:56 PM PST 24
Peak memory 215896 kb
Host smart-891f36d3-2fb9-476c-b482-edfc5024d59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401388471 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1401388471
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3434331096
Short name T572
Test name
Test status
Simulation time 61040686 ps
CPU time 1.15 seconds
Started Jan 24 07:38:45 PM PST 24
Finished Jan 24 07:38:53 PM PST 24
Peak memory 216932 kb
Host smart-50d90c0c-7caa-4b62-b93c-cbbd10eaa3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434331096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3434331096
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1990957897
Short name T23
Test name
Test status
Simulation time 34340792 ps
CPU time 0.84 seconds
Started Jan 24 07:38:47 PM PST 24
Finished Jan 24 07:38:57 PM PST 24
Peak memory 214760 kb
Host smart-3193396c-64c0-4f65-b237-14980729801b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990957897 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1990957897
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.792790911
Short name T372
Test name
Test status
Simulation time 13202609 ps
CPU time 0.97 seconds
Started Jan 24 07:38:44 PM PST 24
Finished Jan 24 07:38:52 PM PST 24
Peak memory 214600 kb
Host smart-d5e15ae2-8ca8-4a82-a7b4-f0a94e588d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792790911 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.792790911
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.1870415373
Short name T906
Test name
Test status
Simulation time 70630892 ps
CPU time 1.38 seconds
Started Jan 24 07:38:42 PM PST 24
Finished Jan 24 07:38:52 PM PST 24
Peak memory 214728 kb
Host smart-df3d8201-6505-4b06-95ca-757ed7427d0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870415373 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.1870415373
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1122682339
Short name T222
Test name
Test status
Simulation time 71455352524 ps
CPU time 302.59 seconds
Started Jan 24 07:38:41 PM PST 24
Finished Jan 24 07:43:48 PM PST 24
Peak memory 216912 kb
Host smart-9a661d03-c93e-454d-8105-b5f538c9bdf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122682339 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1122682339
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3476337378
Short name T774
Test name
Test status
Simulation time 14382205 ps
CPU time 0.97 seconds
Started Jan 24 07:44:47 PM PST 24
Finished Jan 24 07:44:52 PM PST 24
Peak memory 214684 kb
Host smart-a2b12546-0827-4029-951c-5714d983ef1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476337378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3476337378
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1323379669
Short name T226
Test name
Test status
Simulation time 63510758 ps
CPU time 1 seconds
Started Jan 24 07:44:58 PM PST 24
Finished Jan 24 07:45:03 PM PST 24
Peak memory 214712 kb
Host smart-f6c9714d-ac64-47a0-a125-095e7f7bdcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323379669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1323379669
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.4061614556
Short name T869
Test name
Test status
Simulation time 15278099 ps
CPU time 1.04 seconds
Started Jan 24 07:45:03 PM PST 24
Finished Jan 24 07:45:07 PM PST 24
Peak memory 215016 kb
Host smart-e3944583-39ab-4a1b-8f25-161c0e909e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061614556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.4061614556
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.741628372
Short name T931
Test name
Test status
Simulation time 59771692 ps
CPU time 1.08 seconds
Started Jan 24 07:45:04 PM PST 24
Finished Jan 24 07:45:08 PM PST 24
Peak memory 216272 kb
Host smart-17e098e7-a3b5-47af-85a0-87eb9c52c1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741628372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.741628372
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.799464051
Short name T797
Test name
Test status
Simulation time 23059820 ps
CPU time 1.46 seconds
Started Jan 24 07:44:58 PM PST 24
Finished Jan 24 07:45:03 PM PST 24
Peak memory 216240 kb
Host smart-0c47c31e-8601-477f-9224-c980abac2a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799464051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.799464051
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2919387163
Short name T519
Test name
Test status
Simulation time 73032684 ps
CPU time 2.83 seconds
Started Jan 24 07:45:05 PM PST 24
Finished Jan 24 07:45:10 PM PST 24
Peak memory 214976 kb
Host smart-90103923-9e9d-4de5-a7e8-13c4c93ac7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919387163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2919387163
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1162972825
Short name T63
Test name
Test status
Simulation time 104935919 ps
CPU time 1.12 seconds
Started Jan 24 07:45:03 PM PST 24
Finished Jan 24 07:45:07 PM PST 24
Peak memory 214816 kb
Host smart-d6c9c6a5-99e9-4c2e-b883-6574e9b92a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162972825 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1162972825
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.916685067
Short name T37
Test name
Test status
Simulation time 21529860 ps
CPU time 1.29 seconds
Started Jan 24 07:44:57 PM PST 24
Finished Jan 24 07:45:03 PM PST 24
Peak memory 214668 kb
Host smart-bc48d53a-7621-44d5-94e7-c2e8a9e2e3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916685067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.916685067
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.4274275311
Short name T610
Test name
Test status
Simulation time 16345908 ps
CPU time 1.07 seconds
Started Jan 24 07:44:58 PM PST 24
Finished Jan 24 07:45:03 PM PST 24
Peak memory 214784 kb
Host smart-bf4abdb6-e565-44e0-95c1-1058fd143d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274275311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.4274275311
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.4252714490
Short name T202
Test name
Test status
Simulation time 23669453 ps
CPU time 0.95 seconds
Started Jan 24 07:38:50 PM PST 24
Finished Jan 24 07:38:58 PM PST 24
Peak memory 206328 kb
Host smart-bef6ce30-d025-43e9-ba13-7268c3f8ef87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252714490 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.4252714490
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.525574561
Short name T889
Test name
Test status
Simulation time 28370251 ps
CPU time 0.92 seconds
Started Jan 24 07:38:58 PM PST 24
Finished Jan 24 07:39:04 PM PST 24
Peak memory 205108 kb
Host smart-4884a49d-8329-4ceb-8153-b14d0244d9b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525574561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.525574561
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1112739820
Short name T863
Test name
Test status
Simulation time 29070215 ps
CPU time 0.78 seconds
Started Jan 24 07:38:52 PM PST 24
Finished Jan 24 07:39:00 PM PST 24
Peak memory 214820 kb
Host smart-8294ab14-6ceb-4946-8c10-766f8ddca150
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112739820 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1112739820
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1621706384
Short name T563
Test name
Test status
Simulation time 19903049 ps
CPU time 0.98 seconds
Started Jan 24 07:38:57 PM PST 24
Finished Jan 24 07:39:03 PM PST 24
Peak memory 214940 kb
Host smart-42ffa02b-4a77-4fa5-8f42-33535c7694bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621706384 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1621706384
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2187148249
Short name T240
Test name
Test status
Simulation time 48354593 ps
CPU time 1.04 seconds
Started Jan 24 07:47:47 PM PST 24
Finished Jan 24 07:47:49 PM PST 24
Peak memory 222148 kb
Host smart-abe7a422-4895-4571-8620-ddbe7dfcfa77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187148249 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2187148249
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.918164933
Short name T936
Test name
Test status
Simulation time 88873757 ps
CPU time 1.14 seconds
Started Jan 24 07:38:51 PM PST 24
Finished Jan 24 07:38:59 PM PST 24
Peak memory 214960 kb
Host smart-0e46e1d8-d142-41fb-a73c-36047c75ac06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918164933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.918164933
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3821599584
Short name T806
Test name
Test status
Simulation time 23516465 ps
CPU time 0.9 seconds
Started Jan 24 08:02:14 PM PST 24
Finished Jan 24 08:02:17 PM PST 24
Peak memory 214880 kb
Host smart-20f14f5c-0142-44ba-929d-0e9a2c316b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821599584 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3821599584
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.693586749
Short name T111
Test name
Test status
Simulation time 100378984 ps
CPU time 0.92 seconds
Started Jan 24 07:38:51 PM PST 24
Finished Jan 24 07:39:00 PM PST 24
Peak memory 214600 kb
Host smart-57a370d8-3fd4-4465-aee7-67890a7350ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693586749 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.693586749
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3449738868
Short name T831
Test name
Test status
Simulation time 107353882 ps
CPU time 2.24 seconds
Started Jan 24 07:38:50 PM PST 24
Finished Jan 24 07:38:59 PM PST 24
Peak memory 214616 kb
Host smart-4783c26a-acd2-447c-934a-78ff65da1573
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449738868 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3449738868
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3506630729
Short name T777
Test name
Test status
Simulation time 37022268808 ps
CPU time 408.39 seconds
Started Jan 24 07:38:50 PM PST 24
Finished Jan 24 07:45:45 PM PST 24
Peak memory 215500 kb
Host smart-4215214d-f863-4399-8e76-6fd59b6edbdf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506630729 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3506630729
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.331612720
Short name T918
Test name
Test status
Simulation time 25313928 ps
CPU time 0.92 seconds
Started Jan 24 07:44:56 PM PST 24
Finished Jan 24 07:45:01 PM PST 24
Peak memory 214912 kb
Host smart-f7aa77bc-1a03-440c-86d6-ddee02153b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331612720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.331612720
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.1569121938
Short name T367
Test name
Test status
Simulation time 30834442 ps
CPU time 0.95 seconds
Started Jan 24 07:44:55 PM PST 24
Finished Jan 24 07:44:57 PM PST 24
Peak memory 214776 kb
Host smart-6050e071-880e-4a6f-99bc-073b02e8ae4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569121938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.1569121938
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.626329709
Short name T903
Test name
Test status
Simulation time 39216735 ps
CPU time 1.07 seconds
Started Jan 24 07:44:57 PM PST 24
Finished Jan 24 07:45:03 PM PST 24
Peak memory 216140 kb
Host smart-bbbd3fde-f388-4353-bdb6-ba0f9c55cd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626329709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.626329709
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.712036941
Short name T395
Test name
Test status
Simulation time 19336490 ps
CPU time 0.93 seconds
Started Jan 24 07:45:05 PM PST 24
Finished Jan 24 07:45:08 PM PST 24
Peak memory 214684 kb
Host smart-65700d95-b215-4c99-a2cd-0a0979cc61ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712036941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.712036941
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2734480740
Short name T845
Test name
Test status
Simulation time 85168495 ps
CPU time 1.18 seconds
Started Jan 24 07:45:05 PM PST 24
Finished Jan 24 07:45:08 PM PST 24
Peak memory 214872 kb
Host smart-f5479a4a-1883-4f4a-85d9-4cd03bed71c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734480740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2734480740
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.1367821743
Short name T620
Test name
Test status
Simulation time 27305911 ps
CPU time 1.27 seconds
Started Jan 24 07:45:04 PM PST 24
Finished Jan 24 07:45:08 PM PST 24
Peak memory 214720 kb
Host smart-03166ab2-e542-498f-8061-31ebf143a514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367821743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1367821743
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.2843642627
Short name T902
Test name
Test status
Simulation time 130885717 ps
CPU time 0.94 seconds
Started Jan 24 07:45:03 PM PST 24
Finished Jan 24 07:45:07 PM PST 24
Peak memory 214692 kb
Host smart-451eb445-67d3-4be8-a8a7-50fe5a501be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843642627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.2843642627
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2649566311
Short name T407
Test name
Test status
Simulation time 34540596 ps
CPU time 1.26 seconds
Started Jan 24 07:45:12 PM PST 24
Finished Jan 24 07:45:14 PM PST 24
Peak memory 216380 kb
Host smart-b8cd5296-f908-4db7-a3c9-32cf0041d056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649566311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2649566311
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1343027627
Short name T267
Test name
Test status
Simulation time 40625280 ps
CPU time 1.17 seconds
Started Jan 24 07:45:08 PM PST 24
Finished Jan 24 07:45:11 PM PST 24
Peak memory 216164 kb
Host smart-769c7752-3a4a-4698-8f11-a821520e775a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343027627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1343027627
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.1803371077
Short name T43
Test name
Test status
Simulation time 82194154 ps
CPU time 1.94 seconds
Started Jan 24 07:45:07 PM PST 24
Finished Jan 24 07:45:12 PM PST 24
Peak memory 216144 kb
Host smart-da3e4769-7ee4-4ec4-aafe-67ec2e14590c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803371077 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.1803371077
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.4205753764
Short name T437
Test name
Test status
Simulation time 62771955 ps
CPU time 0.94 seconds
Started Jan 24 07:38:58 PM PST 24
Finished Jan 24 07:39:04 PM PST 24
Peak memory 206344 kb
Host smart-8cd7b3cc-ddb4-416a-8de6-31a48f1e4cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205753764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.4205753764
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2762652415
Short name T566
Test name
Test status
Simulation time 195540312 ps
CPU time 0.91 seconds
Started Jan 24 07:38:59 PM PST 24
Finished Jan 24 07:39:04 PM PST 24
Peak memory 205876 kb
Host smart-47f2c34a-2ebb-455d-a0df-d98e4f832577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762652415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2762652415
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1001743446
Short name T509
Test name
Test status
Simulation time 12365321 ps
CPU time 0.87 seconds
Started Jan 24 07:39:04 PM PST 24
Finished Jan 24 07:39:07 PM PST 24
Peak memory 214796 kb
Host smart-5375a910-beda-41dc-bc78-9a3d17093dbd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001743446 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1001743446
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3846372874
Short name T870
Test name
Test status
Simulation time 24071390 ps
CPU time 1 seconds
Started Jan 24 07:38:58 PM PST 24
Finished Jan 24 07:39:04 PM PST 24
Peak memory 214972 kb
Host smart-d1f782fe-0dd4-4bab-ab0f-2f4ec0d654c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846372874 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3846372874
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.41090542
Short name T454
Test name
Test status
Simulation time 19816302 ps
CPU time 1.08 seconds
Started Jan 24 07:39:06 PM PST 24
Finished Jan 24 07:39:08 PM PST 24
Peak memory 216008 kb
Host smart-d1f4be52-5d3f-400f-857a-dcfcbe5aeab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41090542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.41090542
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.285141136
Short name T490
Test name
Test status
Simulation time 17099578 ps
CPU time 1.06 seconds
Started Jan 24 07:38:58 PM PST 24
Finished Jan 24 07:39:04 PM PST 24
Peak memory 214688 kb
Host smart-e26a9df4-1444-4691-a00b-58e00319b44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285141136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.285141136
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.3991184540
Short name T760
Test name
Test status
Simulation time 20241332 ps
CPU time 1.06 seconds
Started Jan 24 07:39:00 PM PST 24
Finished Jan 24 07:39:05 PM PST 24
Peak memory 214916 kb
Host smart-e8344727-3d9e-43fe-8f7a-0d6d628a99b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991184540 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.3991184540
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.759019987
Short name T575
Test name
Test status
Simulation time 12631196 ps
CPU time 0.87 seconds
Started Jan 24 07:39:04 PM PST 24
Finished Jan 24 07:39:07 PM PST 24
Peak memory 214588 kb
Host smart-6293c4a0-a85f-4f59-b993-9434d942243b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759019987 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.759019987
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1577586062
Short name T828
Test name
Test status
Simulation time 96256082 ps
CPU time 2.62 seconds
Started Jan 24 07:39:03 PM PST 24
Finished Jan 24 07:39:09 PM PST 24
Peak memory 214628 kb
Host smart-32172764-16a7-4ac3-9d0c-201502c293ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577586062 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1577586062
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3547715300
Short name T594
Test name
Test status
Simulation time 43947979663 ps
CPU time 493.56 seconds
Started Jan 24 07:39:04 PM PST 24
Finished Jan 24 07:47:20 PM PST 24
Peak memory 223004 kb
Host smart-0a375784-5310-4edd-805e-5dd644bbb2fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547715300 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3547715300
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.374189079
Short name T769
Test name
Test status
Simulation time 35130517 ps
CPU time 1.05 seconds
Started Jan 24 07:45:04 PM PST 24
Finished Jan 24 07:45:08 PM PST 24
Peak memory 214708 kb
Host smart-44a04883-e5fc-4e8f-8942-d48d12737be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374189079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.374189079
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3861035760
Short name T629
Test name
Test status
Simulation time 34952905 ps
CPU time 1.05 seconds
Started Jan 24 07:45:05 PM PST 24
Finished Jan 24 07:45:09 PM PST 24
Peak memory 214872 kb
Host smart-2375578c-332e-47f9-818a-21ef33d80473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861035760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3861035760
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.757337468
Short name T224
Test name
Test status
Simulation time 46438300 ps
CPU time 1 seconds
Started Jan 24 07:45:06 PM PST 24
Finished Jan 24 07:45:10 PM PST 24
Peak memory 215060 kb
Host smart-0c0611c0-6e2f-4954-acd8-a5eee2484e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757337468 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.757337468
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1238876577
Short name T675
Test name
Test status
Simulation time 24852995 ps
CPU time 1.23 seconds
Started Jan 24 07:45:06 PM PST 24
Finished Jan 24 07:45:10 PM PST 24
Peak memory 217088 kb
Host smart-b0770166-c967-4712-a9c8-c5f742645f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238876577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1238876577
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3563463964
Short name T762
Test name
Test status
Simulation time 22886046 ps
CPU time 1.17 seconds
Started Jan 24 07:45:07 PM PST 24
Finished Jan 24 07:45:10 PM PST 24
Peak memory 215084 kb
Host smart-56c00c59-dc1f-46f1-aa32-1eef663a1af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563463964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3563463964
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2217760063
Short name T583
Test name
Test status
Simulation time 24276538 ps
CPU time 1.21 seconds
Started Jan 24 07:45:07 PM PST 24
Finished Jan 24 07:45:10 PM PST 24
Peak memory 214920 kb
Host smart-de2cc7a0-3393-4aaa-85c5-c350373b5f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217760063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2217760063
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3994899873
Short name T225
Test name
Test status
Simulation time 34321836 ps
CPU time 1.16 seconds
Started Jan 24 07:45:08 PM PST 24
Finished Jan 24 07:45:11 PM PST 24
Peak memory 217108 kb
Host smart-6fdfafbe-71a3-4211-8c1b-43b083ec34b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994899873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3994899873
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.640343070
Short name T235
Test name
Test status
Simulation time 21040080 ps
CPU time 1.14 seconds
Started Jan 24 07:45:05 PM PST 24
Finished Jan 24 07:45:08 PM PST 24
Peak memory 215172 kb
Host smart-293ce25e-d095-4594-9a7a-4d9f0a339b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640343070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.640343070
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1430278180
Short name T862
Test name
Test status
Simulation time 27578509 ps
CPU time 1 seconds
Started Jan 24 07:45:05 PM PST 24
Finished Jan 24 07:45:08 PM PST 24
Peak memory 215032 kb
Host smart-252f7b99-aa58-4999-adb3-1326ea530f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430278180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1430278180
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.622848228
Short name T549
Test name
Test status
Simulation time 73575755 ps
CPU time 1.12 seconds
Started Jan 25 03:51:21 AM PST 24
Finished Jan 25 03:51:23 AM PST 24
Peak memory 214732 kb
Host smart-282438c1-65c7-4d58-a966-aff3827846fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622848228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.622848228
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.246940842
Short name T19
Test name
Test status
Simulation time 121822107 ps
CPU time 0.96 seconds
Started Jan 24 07:39:09 PM PST 24
Finished Jan 24 07:39:12 PM PST 24
Peak memory 205668 kb
Host smart-4ea03f3f-52c7-4d67-8b16-82b8525d5fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246940842 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.246940842
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.2598156727
Short name T112
Test name
Test status
Simulation time 17629925 ps
CPU time 0.93 seconds
Started Jan 24 07:39:09 PM PST 24
Finished Jan 24 07:39:12 PM PST 24
Peak memory 205632 kb
Host smart-8d13f586-b58c-4d1f-86f5-f5628df16ce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598156727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.2598156727
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2694344330
Short name T134
Test name
Test status
Simulation time 13641247 ps
CPU time 0.92 seconds
Started Jan 24 07:39:16 PM PST 24
Finished Jan 24 07:39:18 PM PST 24
Peak memory 214944 kb
Host smart-8313f5eb-ba65-4d39-ac3d-41baba5596e6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694344330 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2694344330
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.1397578096
Short name T499
Test name
Test status
Simulation time 85385271 ps
CPU time 1.13 seconds
Started Jan 24 07:39:05 PM PST 24
Finished Jan 24 07:39:08 PM PST 24
Peak memory 214984 kb
Host smart-6a06ae13-9846-4c3c-af91-43f647eb41c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397578096 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.1397578096
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2399404101
Short name T377
Test name
Test status
Simulation time 23757556 ps
CPU time 0.92 seconds
Started Jan 24 08:16:21 PM PST 24
Finished Jan 24 08:16:23 PM PST 24
Peak memory 216024 kb
Host smart-86a0efe0-3a31-4cc8-ae0c-2d773e56beb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399404101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2399404101
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.734913743
Short name T547
Test name
Test status
Simulation time 102920019 ps
CPU time 2.49 seconds
Started Jan 24 07:39:06 PM PST 24
Finished Jan 24 07:39:10 PM PST 24
Peak memory 217916 kb
Host smart-acee4dc1-fde9-4f9b-952c-4408b46e8f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734913743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.734913743
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3566159761
Short name T100
Test name
Test status
Simulation time 35456028 ps
CPU time 0.9 seconds
Started Jan 24 07:39:08 PM PST 24
Finished Jan 24 07:39:10 PM PST 24
Peak memory 214760 kb
Host smart-c4cac9c0-e6e5-4e6f-97a7-e6fd3e576876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566159761 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3566159761
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1749948510
Short name T390
Test name
Test status
Simulation time 79664132 ps
CPU time 0.9 seconds
Started Jan 24 07:38:57 PM PST 24
Finished Jan 24 07:39:03 PM PST 24
Peak memory 214616 kb
Host smart-a39680b3-3fea-48e1-95d0-46956b65517b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749948510 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1749948510
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2718314370
Short name T897
Test name
Test status
Simulation time 92529883 ps
CPU time 2.48 seconds
Started Jan 24 07:39:12 PM PST 24
Finished Jan 24 07:39:16 PM PST 24
Peak memory 214696 kb
Host smart-3ff8be27-334b-4877-820a-e723f65b1990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718314370 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2718314370
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.73081984
Short name T820
Test name
Test status
Simulation time 801492782506 ps
CPU time 1370.4 seconds
Started Jan 24 07:39:09 PM PST 24
Finished Jan 24 08:02:01 PM PST 24
Peak memory 222864 kb
Host smart-f4f65002-4f66-4252-af98-487e5f9b0228
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73081984 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.73081984
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3292911024
Short name T654
Test name
Test status
Simulation time 50443992 ps
CPU time 1.29 seconds
Started Jan 24 07:45:07 PM PST 24
Finished Jan 24 07:45:10 PM PST 24
Peak memory 214928 kb
Host smart-54ad6bac-6640-47c1-9786-53f0925b423b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292911024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3292911024
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3435939676
Short name T927
Test name
Test status
Simulation time 134560400 ps
CPU time 1.16 seconds
Started Jan 24 07:45:06 PM PST 24
Finished Jan 24 07:45:10 PM PST 24
Peak memory 214816 kb
Host smart-532054c8-15ef-4e6b-ba69-c56b02e28ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435939676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3435939676
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.364790683
Short name T825
Test name
Test status
Simulation time 33308461 ps
CPU time 1.01 seconds
Started Jan 24 10:14:43 PM PST 24
Finished Jan 24 10:14:46 PM PST 24
Peak memory 214908 kb
Host smart-b3efcc10-b622-4302-b90d-d54720aae065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364790683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.364790683
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2713370136
Short name T573
Test name
Test status
Simulation time 28032801 ps
CPU time 1.24 seconds
Started Jan 24 07:45:07 PM PST 24
Finished Jan 24 07:45:11 PM PST 24
Peak memory 214872 kb
Host smart-ab0871af-c073-4b08-98a7-431f471de05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713370136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2713370136
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3983471923
Short name T698
Test name
Test status
Simulation time 14226570 ps
CPU time 1.05 seconds
Started Jan 24 07:45:08 PM PST 24
Finished Jan 24 07:45:11 PM PST 24
Peak memory 215084 kb
Host smart-9e1942e9-bad7-41f6-b41a-25aef8aae9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983471923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3983471923
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3506311259
Short name T813
Test name
Test status
Simulation time 23508152 ps
CPU time 1.18 seconds
Started Jan 24 07:45:05 PM PST 24
Finished Jan 24 07:45:08 PM PST 24
Peak memory 214864 kb
Host smart-0f20feba-3201-41b4-892c-a65a5ce229d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506311259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3506311259
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.852955073
Short name T775
Test name
Test status
Simulation time 60659121 ps
CPU time 1.12 seconds
Started Jan 24 07:45:05 PM PST 24
Finished Jan 24 07:45:09 PM PST 24
Peak memory 215096 kb
Host smart-21c13235-de0e-4d3f-86de-c4ff9e67d720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852955073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.852955073
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.639564968
Short name T699
Test name
Test status
Simulation time 50374532 ps
CPU time 1.52 seconds
Started Jan 24 07:45:06 PM PST 24
Finished Jan 24 07:45:10 PM PST 24
Peak memory 214676 kb
Host smart-a58ec55f-a7cf-4256-ad38-203ec3abc49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639564968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.639564968
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.639638425
Short name T838
Test name
Test status
Simulation time 25477156 ps
CPU time 1.17 seconds
Started Jan 24 07:45:14 PM PST 24
Finished Jan 24 07:45:16 PM PST 24
Peak memory 214884 kb
Host smart-0013dbc2-5aba-40a9-8f2e-8bc0768cd1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639638425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.639638425
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.3963530480
Short name T738
Test name
Test status
Simulation time 17876590 ps
CPU time 0.98 seconds
Started Jan 24 07:39:08 PM PST 24
Finished Jan 24 07:39:11 PM PST 24
Peak memory 206364 kb
Host smart-27346de5-4d2b-4c2c-b820-1f72eacee8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963530480 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3963530480
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3320229614
Short name T400
Test name
Test status
Simulation time 124613859 ps
CPU time 0.87 seconds
Started Jan 24 07:39:12 PM PST 24
Finished Jan 24 07:39:14 PM PST 24
Peak memory 205476 kb
Host smart-dd3ab631-73fb-49c5-8602-0ce8a3998a90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320229614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3320229614
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.85482278
Short name T487
Test name
Test status
Simulation time 11888682 ps
CPU time 0.87 seconds
Started Jan 24 07:39:09 PM PST 24
Finished Jan 24 07:39:11 PM PST 24
Peak memory 214816 kb
Host smart-846d07c1-891c-4a60-a42c-f8bb3c7c09c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85482278 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.85482278
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.2061028083
Short name T56
Test name
Test status
Simulation time 57790788 ps
CPU time 1.11 seconds
Started Jan 24 07:39:11 PM PST 24
Finished Jan 24 07:39:14 PM PST 24
Peak memory 230380 kb
Host smart-a2e4950d-6912-4d3b-a02a-3ee93b3ed0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061028083 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2061028083
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3750345910
Short name T527
Test name
Test status
Simulation time 29926749 ps
CPU time 0.97 seconds
Started Jan 24 07:45:57 PM PST 24
Finished Jan 24 07:45:59 PM PST 24
Peak memory 215116 kb
Host smart-a164bfe3-7dff-4a87-a273-8bf9f4abe130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750345910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3750345910
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2099859932
Short name T414
Test name
Test status
Simulation time 20153581 ps
CPU time 1.05 seconds
Started Jan 24 09:14:23 PM PST 24
Finished Jan 24 09:14:25 PM PST 24
Peak memory 214916 kb
Host smart-5fb52065-4b70-45b4-b737-0fbd9a8242a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099859932 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2099859932
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.349306220
Short name T812
Test name
Test status
Simulation time 22468371 ps
CPU time 0.9 seconds
Started Jan 24 07:39:11 PM PST 24
Finished Jan 24 07:39:14 PM PST 24
Peak memory 214620 kb
Host smart-a31c6cce-8fab-40b4-b1b3-c999b5340fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349306220 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.349306220
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.757734258
Short name T772
Test name
Test status
Simulation time 678378980 ps
CPU time 2.44 seconds
Started Jan 24 07:39:10 PM PST 24
Finished Jan 24 07:39:14 PM PST 24
Peak memory 214680 kb
Host smart-6b1151ee-82e4-47d3-8476-8c4cfc084eae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757734258 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.757734258
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1587266689
Short name T103
Test name
Test status
Simulation time 40028823858 ps
CPU time 511.97 seconds
Started Jan 24 07:39:07 PM PST 24
Finished Jan 24 07:47:40 PM PST 24
Peak memory 217484 kb
Host smart-10f07b7b-718a-489b-ba28-17b967432103
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587266689 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1587266689
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1789822656
Short name T284
Test name
Test status
Simulation time 26198065 ps
CPU time 0.96 seconds
Started Jan 24 07:45:14 PM PST 24
Finished Jan 24 07:45:16 PM PST 24
Peak memory 214620 kb
Host smart-f332ea9b-ed5b-47e1-8e7c-3eda2fdc8f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789822656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1789822656
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.3093983133
Short name T593
Test name
Test status
Simulation time 73331699 ps
CPU time 1.15 seconds
Started Jan 24 07:45:13 PM PST 24
Finished Jan 24 07:45:15 PM PST 24
Peak memory 215084 kb
Host smart-73d1180b-8a28-4694-af3a-a8a1ab8c90cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093983133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.3093983133
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3468734815
Short name T757
Test name
Test status
Simulation time 76704750 ps
CPU time 1.08 seconds
Started Jan 24 07:45:09 PM PST 24
Finished Jan 24 07:45:13 PM PST 24
Peak memory 214916 kb
Host smart-c5aecdac-298b-4e25-a7aa-21c722722409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468734815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3468734815
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.2705495365
Short name T625
Test name
Test status
Simulation time 38524604 ps
CPU time 0.97 seconds
Started Jan 24 07:45:19 PM PST 24
Finished Jan 24 07:45:21 PM PST 24
Peak memory 214788 kb
Host smart-9352e479-76fe-487a-ada9-abb8d1463a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705495365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2705495365
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3552846332
Short name T258
Test name
Test status
Simulation time 20257246 ps
CPU time 1.19 seconds
Started Jan 24 07:58:45 PM PST 24
Finished Jan 24 07:58:47 PM PST 24
Peak memory 216300 kb
Host smart-3b8f976b-4e20-4461-a241-9916d2d74ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552846332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3552846332
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1706954247
Short name T425
Test name
Test status
Simulation time 47534580 ps
CPU time 1.05 seconds
Started Jan 24 07:45:19 PM PST 24
Finished Jan 24 07:45:21 PM PST 24
Peak memory 214848 kb
Host smart-9b9d5e03-9e74-4eaa-8e7b-cbc6f49c150c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706954247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1706954247
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.4174420324
Short name T796
Test name
Test status
Simulation time 175420358 ps
CPU time 1.05 seconds
Started Jan 24 07:45:23 PM PST 24
Finished Jan 24 07:45:29 PM PST 24
Peak memory 214768 kb
Host smart-30fab8a3-2166-4d84-9d2f-2bacbb1aafad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174420324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.4174420324
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.674159274
Short name T495
Test name
Test status
Simulation time 18192921 ps
CPU time 1.09 seconds
Started Jan 24 07:45:18 PM PST 24
Finished Jan 24 07:45:21 PM PST 24
Peak memory 214948 kb
Host smart-4a9b2762-661c-4022-980c-c2341d748221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674159274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.674159274
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1679988213
Short name T526
Test name
Test status
Simulation time 21580149 ps
CPU time 1.06 seconds
Started Jan 24 07:45:08 PM PST 24
Finished Jan 24 07:45:11 PM PST 24
Peak memory 206408 kb
Host smart-072aaba6-7977-4785-9171-573e439542e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679988213 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1679988213
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.4100907017
Short name T898
Test name
Test status
Simulation time 40668390 ps
CPU time 0.81 seconds
Started Jan 24 07:36:09 PM PST 24
Finished Jan 24 07:36:13 PM PST 24
Peak memory 204724 kb
Host smart-6b66b2bc-5b6d-43a4-8f32-32046e2d731a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100907017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.4100907017
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3007030313
Short name T122
Test name
Test status
Simulation time 10549091 ps
CPU time 0.89 seconds
Started Jan 24 09:08:24 PM PST 24
Finished Jan 24 09:08:27 PM PST 24
Peak memory 214836 kb
Host smart-e0eecfaf-68b2-4751-aede-0a326a2b2f05
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007030313 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3007030313
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_err.3954612182
Short name T538
Test name
Test status
Simulation time 25639365 ps
CPU time 1.15 seconds
Started Jan 24 08:32:19 PM PST 24
Finished Jan 24 08:32:21 PM PST 24
Peak memory 216916 kb
Host smart-739f06f7-51e4-447c-995c-e9cf445204da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954612182 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3954612182
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1796203885
Short name T392
Test name
Test status
Simulation time 75723793 ps
CPU time 1.25 seconds
Started Jan 24 09:04:15 PM PST 24
Finished Jan 24 09:04:24 PM PST 24
Peak memory 217692 kb
Host smart-6417d7c6-c5ae-45f1-83e1-835cadb8fffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796203885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1796203885
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2260041039
Short name T87
Test name
Test status
Simulation time 23053718 ps
CPU time 1.06 seconds
Started Jan 24 08:36:17 PM PST 24
Finished Jan 24 08:36:19 PM PST 24
Peak memory 214864 kb
Host smart-a87a78f6-98fb-4f55-be93-848f89a957eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260041039 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2260041039
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.694944663
Short name T600
Test name
Test status
Simulation time 15194942 ps
CPU time 0.96 seconds
Started Jan 24 07:46:27 PM PST 24
Finished Jan 24 07:46:29 PM PST 24
Peak memory 206396 kb
Host smart-4f193018-d576-431f-90cd-bdd569f50fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694944663 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.694944663
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3155723594
Short name T21
Test name
Test status
Simulation time 507132518 ps
CPU time 3.39 seconds
Started Jan 24 07:36:08 PM PST 24
Finished Jan 24 07:36:15 PM PST 24
Peak memory 233544 kb
Host smart-b3154d6a-b36e-4cef-915e-adb8ee87b2ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155723594 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3155723594
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2217467270
Short name T930
Test name
Test status
Simulation time 69900147 ps
CPU time 0.89 seconds
Started Jan 24 07:36:01 PM PST 24
Finished Jan 24 07:36:10 PM PST 24
Peak memory 214596 kb
Host smart-459e5d8e-97f3-417f-b918-76cee229bf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217467270 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2217467270
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1998016883
Short name T524
Test name
Test status
Simulation time 121608305 ps
CPU time 0.96 seconds
Started Jan 24 08:21:34 PM PST 24
Finished Jan 24 08:21:43 PM PST 24
Peak memory 204908 kb
Host smart-3dc60090-f05f-4608-879a-5ebc45b789c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998016883 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1998016883
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3702176682
Short name T447
Test name
Test status
Simulation time 31017034941 ps
CPU time 643.58 seconds
Started Jan 24 07:35:58 PM PST 24
Finished Jan 24 07:46:43 PM PST 24
Peak memory 216396 kb
Host smart-4558b7c8-e1ec-414b-8901-0ce6913e350d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702176682 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3702176682
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3067572264
Short name T622
Test name
Test status
Simulation time 98906150 ps
CPU time 1.03 seconds
Started Jan 24 07:39:12 PM PST 24
Finished Jan 24 07:39:15 PM PST 24
Peak memory 205660 kb
Host smart-6149eaff-0d13-4d0a-baed-a982be43a44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067572264 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3067572264
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3336189948
Short name T525
Test name
Test status
Simulation time 13923471 ps
CPU time 0.87 seconds
Started Jan 24 07:49:16 PM PST 24
Finished Jan 24 07:49:19 PM PST 24
Peak memory 205008 kb
Host smart-ef226293-87cd-41d1-9c79-3180739fe38e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336189948 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3336189948
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2036039007
Short name T879
Test name
Test status
Simulation time 58475577 ps
CPU time 0.9 seconds
Started Jan 24 07:51:01 PM PST 24
Finished Jan 24 07:51:04 PM PST 24
Peak memory 214852 kb
Host smart-67d47837-b32b-4c89-9989-98faac0bb10c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036039007 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2036039007
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.621028083
Short name T626
Test name
Test status
Simulation time 19156193 ps
CPU time 0.92 seconds
Started Jan 24 10:38:55 PM PST 24
Finished Jan 24 10:38:57 PM PST 24
Peak memory 214968 kb
Host smart-863816f2-e298-4ca0-984f-25b1f57fe65e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621028083 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.621028083
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.414373677
Short name T379
Test name
Test status
Simulation time 21999351 ps
CPU time 1.19 seconds
Started Jan 24 07:39:17 PM PST 24
Finished Jan 24 07:39:20 PM PST 24
Peak memory 216220 kb
Host smart-33918066-d611-4ee9-84d1-2b6fa3f918f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414373677 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.414373677
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2694724829
Short name T234
Test name
Test status
Simulation time 27014751 ps
CPU time 1.05 seconds
Started Jan 24 07:45:38 PM PST 24
Finished Jan 24 07:45:42 PM PST 24
Peak memory 214920 kb
Host smart-9d852bb0-e4c3-4654-9083-2ec93e4f71b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694724829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2694724829
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3416598080
Short name T874
Test name
Test status
Simulation time 18703688 ps
CPU time 1.13 seconds
Started Jan 24 08:16:24 PM PST 24
Finished Jan 24 08:16:27 PM PST 24
Peak memory 221720 kb
Host smart-e802b75f-5d12-40c1-b87c-433ad238b294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416598080 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3416598080
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3357764256
Short name T564
Test name
Test status
Simulation time 29890282 ps
CPU time 1 seconds
Started Jan 24 08:43:59 PM PST 24
Finished Jan 24 08:44:07 PM PST 24
Peak memory 214580 kb
Host smart-7b044d75-32da-4587-b463-1ee71b463839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357764256 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3357764256
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.4183406437
Short name T667
Test name
Test status
Simulation time 1968015139 ps
CPU time 4.29 seconds
Started Jan 24 07:39:17 PM PST 24
Finished Jan 24 07:39:23 PM PST 24
Peak memory 214660 kb
Host smart-9f31da65-7434-4526-8dad-7fe3b58b4de1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183406437 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.4183406437
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.570930947
Short name T220
Test name
Test status
Simulation time 172618984430 ps
CPU time 782.99 seconds
Started Jan 24 07:39:11 PM PST 24
Finished Jan 24 07:52:16 PM PST 24
Peak memory 219224 kb
Host smart-ef511afc-f72f-434d-8510-2462dd481feb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570930947 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.570930947
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2004593907
Short name T237
Test name
Test status
Simulation time 251406405 ps
CPU time 1.05 seconds
Started Jan 24 07:39:14 PM PST 24
Finished Jan 24 07:39:16 PM PST 24
Peak memory 205636 kb
Host smart-07641543-fb42-4e43-b67d-175398d06f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004593907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2004593907
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1647819184
Short name T371
Test name
Test status
Simulation time 41508442 ps
CPU time 1.19 seconds
Started Jan 24 07:39:37 PM PST 24
Finished Jan 24 07:39:38 PM PST 24
Peak memory 205300 kb
Host smart-56959e3b-b813-4bea-8f66-6f6acf069504
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647819184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1647819184
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.149201645
Short name T413
Test name
Test status
Simulation time 22182158 ps
CPU time 0.85 seconds
Started Jan 24 07:39:25 PM PST 24
Finished Jan 24 07:39:26 PM PST 24
Peak memory 214784 kb
Host smart-03a0fbd2-5e58-46b0-bde0-f2a52f83b255
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149201645 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.149201645
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3830652926
Short name T11
Test name
Test status
Simulation time 73314707 ps
CPU time 0.99 seconds
Started Jan 24 07:39:28 PM PST 24
Finished Jan 24 07:39:30 PM PST 24
Peak memory 214972 kb
Host smart-5ea30998-0319-4130-a88d-6d6a81071e92
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830652926 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3830652926
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3137148950
Short name T802
Test name
Test status
Simulation time 75620918 ps
CPU time 1.06 seconds
Started Jan 24 07:39:26 PM PST 24
Finished Jan 24 07:39:28 PM PST 24
Peak memory 217336 kb
Host smart-033fc544-5052-431f-b313-271d66b5c679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137148950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3137148950
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3874216586
Short name T893
Test name
Test status
Simulation time 44301415 ps
CPU time 1.12 seconds
Started Jan 24 07:39:12 PM PST 24
Finished Jan 24 07:39:14 PM PST 24
Peak memory 214900 kb
Host smart-a590c70b-5b51-4db9-a8ed-0a1f612ecec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874216586 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3874216586
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.557925571
Short name T97
Test name
Test status
Simulation time 24590598 ps
CPU time 0.84 seconds
Started Jan 24 07:39:13 PM PST 24
Finished Jan 24 07:39:16 PM PST 24
Peak memory 214728 kb
Host smart-c8fbbeaa-5f9f-4954-8a2d-f8b601fde3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557925571 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.557925571
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2217006379
Short name T886
Test name
Test status
Simulation time 130031132 ps
CPU time 0.88 seconds
Started Jan 24 07:39:17 PM PST 24
Finished Jan 24 07:39:19 PM PST 24
Peak memory 214416 kb
Host smart-669233af-131d-4d85-8ee3-ab41d8414bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217006379 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2217006379
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3321381852
Short name T767
Test name
Test status
Simulation time 289023848 ps
CPU time 3.14 seconds
Started Jan 24 07:53:16 PM PST 24
Finished Jan 24 07:53:20 PM PST 24
Peak memory 214968 kb
Host smart-c116bc51-c59e-4c87-b304-0614dfc68614
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321381852 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3321381852
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1909997654
Short name T939
Test name
Test status
Simulation time 63417329140 ps
CPU time 371.82 seconds
Started Jan 24 07:39:11 PM PST 24
Finished Jan 24 07:45:25 PM PST 24
Peak memory 218908 kb
Host smart-1f4929e4-3385-42ef-aaca-047eb139847c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909997654 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1909997654
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3576695027
Short name T696
Test name
Test status
Simulation time 19689744 ps
CPU time 1.02 seconds
Started Jan 24 07:39:43 PM PST 24
Finished Jan 24 07:39:45 PM PST 24
Peak memory 205548 kb
Host smart-791bca99-795d-402b-9700-8c6c0ccbf265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576695027 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3576695027
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2365089410
Short name T729
Test name
Test status
Simulation time 45365952 ps
CPU time 0.88 seconds
Started Jan 24 07:39:43 PM PST 24
Finished Jan 24 07:39:45 PM PST 24
Peak memory 205020 kb
Host smart-e6fa59ef-ffcd-45b1-8f6c-7092e2d39e74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365089410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2365089410
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.148046989
Short name T108
Test name
Test status
Simulation time 41596336 ps
CPU time 0.86 seconds
Started Jan 24 07:39:50 PM PST 24
Finished Jan 24 07:39:53 PM PST 24
Peak memory 214740 kb
Host smart-24abf26e-ce2f-4686-a6c6-35ecefa99906
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148046989 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.148046989
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1659269030
Short name T748
Test name
Test status
Simulation time 15657233 ps
CPU time 0.94 seconds
Started Jan 24 07:39:49 PM PST 24
Finished Jan 24 07:39:51 PM PST 24
Peak memory 214896 kb
Host smart-f718d4a4-e4dc-4c1b-9628-7c3e6e900111
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659269030 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1659269030
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.627778493
Short name T462
Test name
Test status
Simulation time 24402844 ps
CPU time 1.16 seconds
Started Jan 24 07:39:44 PM PST 24
Finished Jan 24 07:39:46 PM PST 24
Peak memory 222116 kb
Host smart-6d96a6b2-dd59-4570-bfd2-3ad8171387e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627778493 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.627778493
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_intr.1058038314
Short name T922
Test name
Test status
Simulation time 26522731 ps
CPU time 0.93 seconds
Started Jan 24 07:39:42 PM PST 24
Finished Jan 24 07:39:44 PM PST 24
Peak memory 214656 kb
Host smart-e13a7f9f-c304-4434-b272-c9752bb4ecc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058038314 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1058038314
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2980103906
Short name T81
Test name
Test status
Simulation time 69232003 ps
CPU time 0.93 seconds
Started Jan 24 09:56:45 PM PST 24
Finished Jan 24 09:56:46 PM PST 24
Peak memory 214600 kb
Host smart-e4a309ab-fd58-463a-8d38-b1691a292205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980103906 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2980103906
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.843066715
Short name T64
Test name
Test status
Simulation time 1762581234 ps
CPU time 5.14 seconds
Started Jan 24 07:39:36 PM PST 24
Finished Jan 24 07:39:42 PM PST 24
Peak memory 217672 kb
Host smart-5123b54f-6da5-4b8b-a3f9-0d3f3c530486
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843066715 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.843066715
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3247491057
Short name T433
Test name
Test status
Simulation time 158472593398 ps
CPU time 604.16 seconds
Started Jan 24 07:39:43 PM PST 24
Finished Jan 24 07:49:48 PM PST 24
Peak memory 220804 kb
Host smart-96dde381-b9de-4af2-b59e-bcdfbff23358
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247491057 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3247491057
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3961410908
Short name T205
Test name
Test status
Simulation time 25458815 ps
CPU time 0.95 seconds
Started Jan 24 07:39:51 PM PST 24
Finished Jan 24 07:39:54 PM PST 24
Peak memory 205560 kb
Host smart-f09f9562-6539-4b2b-abf4-be2d55560f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961410908 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3961410908
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1382160093
Short name T909
Test name
Test status
Simulation time 16598176 ps
CPU time 0.91 seconds
Started Jan 24 07:39:47 PM PST 24
Finished Jan 24 07:39:49 PM PST 24
Peak memory 205640 kb
Host smart-baefdee7-27ba-46e7-a498-52e7ddc5c956
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382160093 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1382160093
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3202483958
Short name T536
Test name
Test status
Simulation time 12953405 ps
CPU time 0.89 seconds
Started Jan 24 07:39:54 PM PST 24
Finished Jan 24 07:39:57 PM PST 24
Peak memory 214976 kb
Host smart-b1806a62-7bb3-4eb0-b8a6-85f2402d1855
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202483958 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3202483958
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_err.2626053212
Short name T627
Test name
Test status
Simulation time 22301737 ps
CPU time 0.86 seconds
Started Jan 24 07:39:52 PM PST 24
Finished Jan 24 07:39:55 PM PST 24
Peak memory 215656 kb
Host smart-1409d8be-4569-4c40-88f8-8deac83f00bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626053212 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2626053212
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.654818145
Short name T45
Test name
Test status
Simulation time 25834453 ps
CPU time 1.14 seconds
Started Jan 24 07:39:42 PM PST 24
Finished Jan 24 07:39:44 PM PST 24
Peak memory 214980 kb
Host smart-da8dfb87-7e6d-4607-abee-2f6c4dc3f2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654818145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.654818145
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2178352080
Short name T899
Test name
Test status
Simulation time 99737482 ps
CPU time 0.81 seconds
Started Jan 24 07:39:52 PM PST 24
Finished Jan 24 07:39:54 PM PST 24
Peak memory 214728 kb
Host smart-14f0ed3e-9454-4055-8445-10f476d2c0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178352080 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2178352080
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2955262174
Short name T741
Test name
Test status
Simulation time 17743698 ps
CPU time 0.98 seconds
Started Jan 24 07:39:43 PM PST 24
Finished Jan 24 07:39:45 PM PST 24
Peak memory 206372 kb
Host smart-784e2c11-dde5-40b2-89c4-5e59a5f5b2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955262174 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2955262174
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.419781587
Short name T676
Test name
Test status
Simulation time 137012232 ps
CPU time 3.35 seconds
Started Jan 24 07:39:50 PM PST 24
Finished Jan 24 07:39:55 PM PST 24
Peak memory 214800 kb
Host smart-87ba44dd-4073-483b-9f07-df94682e6255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419781587 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.419781587
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1522321349
Short name T854
Test name
Test status
Simulation time 216555590461 ps
CPU time 2288.73 seconds
Started Jan 24 07:39:52 PM PST 24
Finished Jan 24 08:18:03 PM PST 24
Peak memory 228620 kb
Host smart-aae158b4-776f-4c59-8a2d-0be505b69606
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522321349 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1522321349
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3396067436
Short name T678
Test name
Test status
Simulation time 64812502 ps
CPU time 0.97 seconds
Started Jan 24 07:39:52 PM PST 24
Finished Jan 24 07:39:55 PM PST 24
Peak memory 205584 kb
Host smart-3e855990-9b59-466f-9839-6294e99a621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396067436 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3396067436
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.3734860718
Short name T882
Test name
Test status
Simulation time 189091801 ps
CPU time 0.85 seconds
Started Jan 24 07:39:50 PM PST 24
Finished Jan 24 07:39:52 PM PST 24
Peak memory 205040 kb
Host smart-ea2d7f4a-9f55-4747-bcfb-5a1b27a66bb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734860718 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.3734860718
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.756946349
Short name T758
Test name
Test status
Simulation time 12802342 ps
CPU time 0.87 seconds
Started Jan 24 07:39:50 PM PST 24
Finished Jan 24 07:39:52 PM PST 24
Peak memory 214920 kb
Host smart-0bb12b4d-e2ae-4071-acab-9acae4374404
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756946349 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.756946349
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.3639919472
Short name T784
Test name
Test status
Simulation time 61701769 ps
CPU time 0.9 seconds
Started Jan 24 07:39:52 PM PST 24
Finished Jan 24 07:39:55 PM PST 24
Peak memory 216292 kb
Host smart-cec6d7db-d6bf-4a17-be01-460722c23862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639919472 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3639919472
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3130235501
Short name T281
Test name
Test status
Simulation time 16654282 ps
CPU time 1.1 seconds
Started Jan 24 07:39:52 PM PST 24
Finished Jan 24 07:39:55 PM PST 24
Peak memory 216052 kb
Host smart-0b71f756-8ff1-4af7-8644-a28b4a8a4937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130235501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3130235501
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1137730741
Short name T99
Test name
Test status
Simulation time 19494617 ps
CPU time 0.97 seconds
Started Jan 24 07:39:50 PM PST 24
Finished Jan 24 07:39:52 PM PST 24
Peak memory 214888 kb
Host smart-11661773-fa35-4009-8154-207ebb2e90e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137730741 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1137730741
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1522014026
Short name T913
Test name
Test status
Simulation time 14031485 ps
CPU time 0.88 seconds
Started Jan 24 07:39:50 PM PST 24
Finished Jan 24 07:39:53 PM PST 24
Peak memory 214604 kb
Host smart-fb439dda-643c-45a3-b523-432b9500f4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522014026 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1522014026
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1111651512
Short name T943
Test name
Test status
Simulation time 32089828 ps
CPU time 0.96 seconds
Started Jan 24 07:39:51 PM PST 24
Finished Jan 24 07:39:54 PM PST 24
Peak memory 214588 kb
Host smart-dada504c-ce06-456b-8c31-852d1eead422
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111651512 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1111651512
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2430034910
Short name T877
Test name
Test status
Simulation time 26798487574 ps
CPU time 665.66 seconds
Started Jan 24 07:39:52 PM PST 24
Finished Jan 24 07:51:00 PM PST 24
Peak memory 215756 kb
Host smart-eb4eb712-7e7d-436b-b273-ba8aa0887b56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430034910 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2430034910
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3485189648
Short name T203
Test name
Test status
Simulation time 16539423 ps
CPU time 1 seconds
Started Jan 24 07:40:03 PM PST 24
Finished Jan 24 07:40:06 PM PST 24
Peak memory 206324 kb
Host smart-a1795f31-bc9d-4453-ace5-56aeccde7a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485189648 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3485189648
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.850672923
Short name T383
Test name
Test status
Simulation time 29370395 ps
CPU time 0.98 seconds
Started Jan 24 07:40:03 PM PST 24
Finished Jan 24 07:40:06 PM PST 24
Peak memory 205024 kb
Host smart-9dbf240d-191c-463b-9a6d-d1360372b959
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850672923 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.850672923
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_err.807743552
Short name T438
Test name
Test status
Simulation time 27983874 ps
CPU time 0.85 seconds
Started Jan 24 07:40:00 PM PST 24
Finished Jan 24 07:40:03 PM PST 24
Peak memory 215792 kb
Host smart-2c7b41c4-692f-4a35-81a1-6eb3e0e3fb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807743552 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.807743552
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1372185606
Short name T577
Test name
Test status
Simulation time 48486898 ps
CPU time 0.99 seconds
Started Jan 24 07:39:50 PM PST 24
Finished Jan 24 07:39:52 PM PST 24
Peak memory 216060 kb
Host smart-1e2b9adf-9dd6-4910-b8ad-4950dcbcdf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372185606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1372185606
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.4204806042
Short name T417
Test name
Test status
Simulation time 28121650 ps
CPU time 0.88 seconds
Started Jan 24 07:40:02 PM PST 24
Finished Jan 24 07:40:05 PM PST 24
Peak memory 214500 kb
Host smart-14e8a73a-d429-406b-bcc7-c23cbf4ab05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204806042 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.4204806042
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.4094416250
Short name T687
Test name
Test status
Simulation time 12688108 ps
CPU time 0.94 seconds
Started Jan 24 07:39:52 PM PST 24
Finished Jan 24 07:39:55 PM PST 24
Peak memory 206396 kb
Host smart-aff3dbef-605c-4f33-9e52-55eebe945812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094416250 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.4094416250
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1260845006
Short name T900
Test name
Test status
Simulation time 75943430 ps
CPU time 1.33 seconds
Started Jan 24 07:39:52 PM PST 24
Finished Jan 24 07:39:55 PM PST 24
Peak memory 214644 kb
Host smart-803d8cb3-0d51-4972-b008-dec9a3904e42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260845006 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1260845006
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_alert.2007019593
Short name T80
Test name
Test status
Simulation time 37307498 ps
CPU time 0.98 seconds
Started Jan 24 07:40:03 PM PST 24
Finished Jan 24 07:40:06 PM PST 24
Peak memory 206364 kb
Host smart-f9eb1ee9-59e6-4aae-9e4b-a87584b57d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007019593 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2007019593
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.960182068
Short name T458
Test name
Test status
Simulation time 39703726 ps
CPU time 1.26 seconds
Started Jan 24 07:39:58 PM PST 24
Finished Jan 24 07:40:00 PM PST 24
Peak memory 205348 kb
Host smart-b1f50a32-5166-433f-87cd-d92c25bd2d03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960182068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.960182068
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3182035001
Short name T36
Test name
Test status
Simulation time 12033321 ps
CPU time 0.86 seconds
Started Jan 24 07:40:01 PM PST 24
Finished Jan 24 07:40:04 PM PST 24
Peak memory 214848 kb
Host smart-0e353bce-8618-4883-8479-262c14701c6b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182035001 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3182035001
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.366723819
Short name T116
Test name
Test status
Simulation time 14971034 ps
CPU time 1 seconds
Started Jan 24 07:40:03 PM PST 24
Finished Jan 24 07:40:06 PM PST 24
Peak memory 214952 kb
Host smart-fbe4652a-7852-427f-bd64-cb2e83f94a47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366723819 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_di
sable_auto_req_mode.366723819
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.40578130
Short name T719
Test name
Test status
Simulation time 21099119 ps
CPU time 1.1 seconds
Started Jan 24 07:39:59 PM PST 24
Finished Jan 24 07:40:03 PM PST 24
Peak memory 222228 kb
Host smart-24f99ee0-a848-4d4e-bfa5-22675349f321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40578130 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.40578130
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1703187132
Short name T706
Test name
Test status
Simulation time 16772574 ps
CPU time 1.12 seconds
Started Jan 24 07:40:03 PM PST 24
Finished Jan 24 07:40:07 PM PST 24
Peak memory 214888 kb
Host smart-b15150e6-181a-4321-bdf5-3cb4efbe089b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703187132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1703187132
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1104764589
Short name T489
Test name
Test status
Simulation time 33405502 ps
CPU time 0.91 seconds
Started Jan 24 07:40:03 PM PST 24
Finished Jan 24 07:40:06 PM PST 24
Peak memory 214928 kb
Host smart-9d2f0752-eb97-4455-8572-0823c29e678d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104764589 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1104764589
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.2839239692
Short name T52
Test name
Test status
Simulation time 13829436 ps
CPU time 0.92 seconds
Started Jan 24 07:40:01 PM PST 24
Finished Jan 24 07:40:04 PM PST 24
Peak memory 214608 kb
Host smart-0de41eff-c3af-40ec-9f41-ea7a6cd716ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839239692 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.2839239692
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3815191563
Short name T665
Test name
Test status
Simulation time 994579099 ps
CPU time 4.74 seconds
Started Jan 24 07:39:59 PM PST 24
Finished Jan 24 07:40:04 PM PST 24
Peak memory 214788 kb
Host smart-000ae12f-3972-4bb4-8ed1-7955c05dba29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815191563 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3815191563
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.703160198
Short name T940
Test name
Test status
Simulation time 41957436144 ps
CPU time 270.44 seconds
Started Jan 24 07:39:58 PM PST 24
Finished Jan 24 07:44:29 PM PST 24
Peak memory 222948 kb
Host smart-692be65f-b6e6-48c5-b09e-1c4daf4b967a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703160198 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.703160198
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.2831226468
Short name T253
Test name
Test status
Simulation time 37294372 ps
CPU time 0.97 seconds
Started Jan 24 07:40:13 PM PST 24
Finished Jan 24 07:40:15 PM PST 24
Peak memory 206316 kb
Host smart-70d56710-0b17-43ac-ab64-5d83ca304035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831226468 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2831226468
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.242595846
Short name T518
Test name
Test status
Simulation time 50337583 ps
CPU time 0.88 seconds
Started Jan 24 07:40:13 PM PST 24
Finished Jan 24 07:40:14 PM PST 24
Peak memory 205024 kb
Host smart-6a91302d-d018-42f8-bf67-c8bec0c82145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242595846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.242595846
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1470849282
Short name T435
Test name
Test status
Simulation time 27579554 ps
CPU time 0.83 seconds
Started Jan 24 07:40:13 PM PST 24
Finished Jan 24 07:40:14 PM PST 24
Peak memory 214812 kb
Host smart-9352cace-d56c-45e2-99d4-055cb1586bf3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470849282 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1470849282
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1749676760
Short name T140
Test name
Test status
Simulation time 58536721 ps
CPU time 1.05 seconds
Started Jan 24 07:40:06 PM PST 24
Finished Jan 24 07:40:09 PM PST 24
Peak memory 215036 kb
Host smart-abe0ffab-c98f-4dd6-a620-df4b65bea011
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749676760 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1749676760
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_genbits.3661017570
Short name T844
Test name
Test status
Simulation time 89967791 ps
CPU time 0.95 seconds
Started Jan 24 07:40:01 PM PST 24
Finished Jan 24 07:40:04 PM PST 24
Peak memory 214876 kb
Host smart-f1c1fa01-eb9d-4db5-87b3-c4b83d1a7033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661017570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3661017570
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1951045365
Short name T681
Test name
Test status
Simulation time 18803314 ps
CPU time 1.05 seconds
Started Jan 24 07:40:09 PM PST 24
Finished Jan 24 07:40:11 PM PST 24
Peak memory 214852 kb
Host smart-c33b5d6f-177f-4a67-b47f-d87cdc23e088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951045365 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1951045365
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.3797231192
Short name T598
Test name
Test status
Simulation time 24131697 ps
CPU time 0.95 seconds
Started Jan 24 07:40:02 PM PST 24
Finished Jan 24 07:40:05 PM PST 24
Peak memory 214592 kb
Host smart-24f393be-60d3-49ed-8798-111afaedde29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797231192 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.3797231192
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1501295553
Short name T631
Test name
Test status
Simulation time 31787715 ps
CPU time 1.21 seconds
Started Jan 24 07:40:03 PM PST 24
Finished Jan 24 07:40:07 PM PST 24
Peak memory 214584 kb
Host smart-0fab4f81-d4ee-4fb4-abe4-a5f32139e838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501295553 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1501295553
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2179300395
Short name T567
Test name
Test status
Simulation time 187825302782 ps
CPU time 845.98 seconds
Started Jan 24 07:39:59 PM PST 24
Finished Jan 24 07:54:08 PM PST 24
Peak memory 217924 kb
Host smart-7ac5f1ff-a7ae-475e-b7ed-9809f854ce92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179300395 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2179300395
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.22447841
Short name T250
Test name
Test status
Simulation time 31664943 ps
CPU time 0.95 seconds
Started Jan 24 07:40:22 PM PST 24
Finished Jan 24 07:40:24 PM PST 24
Peak memory 206356 kb
Host smart-14d38942-3970-45f2-9e1e-e39a42ff37b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22447841 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.22447841
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2670786588
Short name T1
Test name
Test status
Simulation time 27364841 ps
CPU time 0.86 seconds
Started Jan 24 07:40:32 PM PST 24
Finished Jan 24 07:40:34 PM PST 24
Peak memory 205008 kb
Host smart-4c82a0f2-c71f-4c18-a375-f1366fc25aed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670786588 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2670786588
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2279964880
Short name T763
Test name
Test status
Simulation time 13542499 ps
CPU time 0.9 seconds
Started Jan 24 07:40:31 PM PST 24
Finished Jan 24 07:40:32 PM PST 24
Peak memory 214936 kb
Host smart-dc818db7-6660-4a95-9ee5-8dd9a7cfbfd1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279964880 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2279964880
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.4192921515
Short name T746
Test name
Test status
Simulation time 17644153 ps
CPU time 1 seconds
Started Jan 24 07:40:32 PM PST 24
Finished Jan 24 07:40:34 PM PST 24
Peak memory 214980 kb
Host smart-6a457a9f-ee50-4eaf-b947-28b0a620d15f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192921515 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.4192921515
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3430351595
Short name T724
Test name
Test status
Simulation time 67801833 ps
CPU time 0.86 seconds
Started Jan 24 07:40:36 PM PST 24
Finished Jan 24 07:40:37 PM PST 24
Peak memory 216220 kb
Host smart-05ec2dd8-2a00-4f65-8e4c-aefd56116d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430351595 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3430351595
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.4033679184
Short name T766
Test name
Test status
Simulation time 29281635 ps
CPU time 1.11 seconds
Started Jan 24 07:40:09 PM PST 24
Finished Jan 24 07:40:12 PM PST 24
Peak memory 216308 kb
Host smart-64fe997c-3fd9-449f-8548-8b0c10374f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033679184 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.4033679184
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.179658992
Short name T389
Test name
Test status
Simulation time 30369895 ps
CPU time 1.24 seconds
Started Jan 24 07:40:20 PM PST 24
Finished Jan 24 07:40:22 PM PST 24
Peak memory 214680 kb
Host smart-806ec304-d441-458b-8d93-11a0cb4bcf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179658992 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.179658992
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.2853142650
Short name T880
Test name
Test status
Simulation time 20506421 ps
CPU time 0.93 seconds
Started Jan 24 07:40:12 PM PST 24
Finished Jan 24 07:40:14 PM PST 24
Peak memory 214536 kb
Host smart-602195f4-2eea-491d-8172-95f0196725cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853142650 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.2853142650
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3717127319
Short name T260
Test name
Test status
Simulation time 132459394 ps
CPU time 3.26 seconds
Started Jan 24 08:36:01 PM PST 24
Finished Jan 24 08:36:05 PM PST 24
Peak memory 214560 kb
Host smart-f15de0ae-0916-4d5e-9338-d13a0d7b66fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717127319 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3717127319
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1018764923
Short name T664
Test name
Test status
Simulation time 66807665832 ps
CPU time 918.69 seconds
Started Jan 24 07:40:18 PM PST 24
Finished Jan 24 07:55:37 PM PST 24
Peak memory 219304 kb
Host smart-04b7ceb5-3791-4614-a661-a3089cc6ec50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018764923 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1018764923
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.1506076447
Short name T865
Test name
Test status
Simulation time 70022984 ps
CPU time 0.99 seconds
Started Jan 24 07:40:37 PM PST 24
Finished Jan 24 07:40:39 PM PST 24
Peak memory 206336 kb
Host smart-a8ab17b9-87e1-450d-8216-8fc2f2c55330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506076447 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.1506076447
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1529123211
Short name T732
Test name
Test status
Simulation time 15128555 ps
CPU time 0.93 seconds
Started Jan 24 07:44:35 PM PST 24
Finished Jan 24 07:44:37 PM PST 24
Peak memory 205044 kb
Host smart-f60f69ed-a6c3-4ab7-b9b5-b0105c6a6a7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529123211 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1529123211
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.3812049579
Short name T139
Test name
Test status
Simulation time 12199445 ps
CPU time 0.89 seconds
Started Jan 24 07:40:40 PM PST 24
Finished Jan 24 07:40:42 PM PST 24
Peak memory 214944 kb
Host smart-65dde869-7395-401c-9760-4ae15e753444
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812049579 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.3812049579
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.3658637494
Short name T805
Test name
Test status
Simulation time 84504889 ps
CPU time 1.08 seconds
Started Jan 24 09:22:32 PM PST 24
Finished Jan 24 09:22:34 PM PST 24
Peak memory 215028 kb
Host smart-1cb7796c-ace6-4f10-aca7-976b298bdd93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658637494 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.3658637494
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1538008379
Short name T586
Test name
Test status
Simulation time 57740189 ps
CPU time 1.04 seconds
Started Jan 24 08:17:05 PM PST 24
Finished Jan 24 08:17:07 PM PST 24
Peak memory 216384 kb
Host smart-4e03b2fb-90c1-49c6-bbdc-687bb11dee58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538008379 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1538008379
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.614902216
Short name T780
Test name
Test status
Simulation time 24805587 ps
CPU time 1.24 seconds
Started Jan 24 07:40:36 PM PST 24
Finished Jan 24 07:40:38 PM PST 24
Peak memory 215056 kb
Host smart-32005954-30b7-4356-88e2-42e34bfdcda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614902216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.614902216
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1488483810
Short name T817
Test name
Test status
Simulation time 34575451 ps
CPU time 0.86 seconds
Started Jan 24 07:40:33 PM PST 24
Finished Jan 24 07:40:35 PM PST 24
Peak memory 214544 kb
Host smart-2c37d6f2-6b56-4463-9b69-6c5fe4ec1c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488483810 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1488483810
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.4292930096
Short name T841
Test name
Test status
Simulation time 35301467 ps
CPU time 0.95 seconds
Started Jan 24 07:40:30 PM PST 24
Finished Jan 24 07:40:32 PM PST 24
Peak memory 214536 kb
Host smart-21169f57-f83e-49c7-b487-d8704c20b2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292930096 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.4292930096
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.838530333
Short name T589
Test name
Test status
Simulation time 68402852 ps
CPU time 1.74 seconds
Started Jan 24 09:14:27 PM PST 24
Finished Jan 24 09:14:29 PM PST 24
Peak memory 214564 kb
Host smart-6c44a402-b133-4ea5-a0bb-0362a966736b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838530333 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.838530333
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.4259798579
Short name T434
Test name
Test status
Simulation time 13165632102 ps
CPU time 299.82 seconds
Started Jan 24 07:40:34 PM PST 24
Finished Jan 24 07:45:35 PM PST 24
Peak memory 216796 kb
Host smart-47284f26-2908-43ca-afff-e37facf0b45d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259798579 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.4259798579
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.175373044
Short name T941
Test name
Test status
Simulation time 136511277 ps
CPU time 0.98 seconds
Started Jan 24 07:36:16 PM PST 24
Finished Jan 24 07:36:19 PM PST 24
Peak memory 205632 kb
Host smart-ce1f2ea4-2a18-4233-a8a5-e09eefdb9d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175373044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.175373044
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.26179965
Short name T934
Test name
Test status
Simulation time 44529708 ps
CPU time 0.85 seconds
Started Jan 24 07:36:18 PM PST 24
Finished Jan 24 07:36:23 PM PST 24
Peak memory 205064 kb
Host smart-2980d215-6095-4139-a04d-48d72ff495c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26179965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.26179965
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1267295041
Short name T543
Test name
Test status
Simulation time 38114151 ps
CPU time 0.82 seconds
Started Jan 24 07:36:13 PM PST 24
Finished Jan 24 07:36:17 PM PST 24
Peak memory 214796 kb
Host smart-8e0ba626-058d-444f-b5a3-864337d2622d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267295041 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1267295041
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.3850715011
Short name T771
Test name
Test status
Simulation time 36463821 ps
CPU time 1.05 seconds
Started Jan 24 07:36:17 PM PST 24
Finished Jan 24 07:36:22 PM PST 24
Peak memory 215024 kb
Host smart-384ed6fb-1e70-43cd-b5d3-990278a3adb8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850715011 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.3850715011
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.4013547853
Short name T55
Test name
Test status
Simulation time 20146449 ps
CPU time 1.19 seconds
Started Jan 24 07:36:18 PM PST 24
Finished Jan 24 07:36:23 PM PST 24
Peak memory 222140 kb
Host smart-a9a975bb-6750-43bb-85f4-4821c850e019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013547853 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.4013547853
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3955065311
Short name T745
Test name
Test status
Simulation time 192578614 ps
CPU time 1.22 seconds
Started Jan 24 07:36:16 PM PST 24
Finished Jan 24 07:36:20 PM PST 24
Peak memory 216176 kb
Host smart-cb8170a2-7c0d-4fbf-9047-6731d02a434a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955065311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3955065311
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.3338033076
Short name T700
Test name
Test status
Simulation time 23303636 ps
CPU time 0.86 seconds
Started Jan 24 07:36:14 PM PST 24
Finished Jan 24 07:36:19 PM PST 24
Peak memory 214936 kb
Host smart-20906bc7-b7e3-4f52-adca-e94a1b5c9d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338033076 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.3338033076
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1278294421
Short name T242
Test name
Test status
Simulation time 14361265 ps
CPU time 0.98 seconds
Started Jan 24 07:36:16 PM PST 24
Finished Jan 24 07:36:20 PM PST 24
Peak memory 206400 kb
Host smart-3020457f-64e1-446a-8e8c-d308f8324ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278294421 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1278294421
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3883125703
Short name T22
Test name
Test status
Simulation time 1250850160 ps
CPU time 5.87 seconds
Started Jan 24 07:36:15 PM PST 24
Finished Jan 24 07:36:24 PM PST 24
Peak memory 233208 kb
Host smart-b20ed315-99d1-4550-9df3-fe1a545a275d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883125703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3883125703
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.3240573170
Short name T657
Test name
Test status
Simulation time 24457890 ps
CPU time 0.89 seconds
Started Jan 24 08:48:47 PM PST 24
Finished Jan 24 08:48:49 PM PST 24
Peak memory 214608 kb
Host smart-295fcca9-de21-47de-ab23-ad8d5da8c2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240573170 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3240573170
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.114044138
Short name T849
Test name
Test status
Simulation time 748303755 ps
CPU time 4.29 seconds
Started Jan 24 07:36:15 PM PST 24
Finished Jan 24 07:36:22 PM PST 24
Peak memory 215032 kb
Host smart-f6ce4d16-ffaf-41db-b728-96044c74d843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114044138 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.114044138
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2649965947
Short name T510
Test name
Test status
Simulation time 49360319117 ps
CPU time 1085.41 seconds
Started Jan 24 07:36:19 PM PST 24
Finished Jan 24 07:54:27 PM PST 24
Peak memory 219364 kb
Host smart-52a30165-f070-4283-9336-687f07c84084
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649965947 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2649965947
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.383854661
Short name T18
Test name
Test status
Simulation time 81905429 ps
CPU time 0.99 seconds
Started Jan 24 07:55:51 PM PST 24
Finished Jan 24 07:55:54 PM PST 24
Peak memory 205756 kb
Host smart-7673c579-9111-4484-8291-1839de563339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383854661 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.383854661
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1209930745
Short name T656
Test name
Test status
Simulation time 17235041 ps
CPU time 0.95 seconds
Started Jan 24 07:40:38 PM PST 24
Finished Jan 24 07:40:39 PM PST 24
Peak memory 205100 kb
Host smart-6b3ab960-0f9a-4c7c-8f71-95908b244500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209930745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1209930745
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1624247626
Short name T578
Test name
Test status
Simulation time 13624959 ps
CPU time 0.93 seconds
Started Jan 24 07:40:38 PM PST 24
Finished Jan 24 07:40:40 PM PST 24
Peak memory 215024 kb
Host smart-8552f8d9-78e0-4921-ab33-17e5664f1be8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624247626 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1624247626
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.1536760156
Short name T48
Test name
Test status
Simulation time 72824152 ps
CPU time 1.08 seconds
Started Jan 24 09:01:35 PM PST 24
Finished Jan 24 09:01:37 PM PST 24
Peak memory 214976 kb
Host smart-e23194c4-af23-45c8-ae82-15589d242dc1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536760156 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.1536760156
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.2212171654
Short name T528
Test name
Test status
Simulation time 21665009 ps
CPU time 1.01 seconds
Started Jan 24 07:40:40 PM PST 24
Finished Jan 24 07:40:42 PM PST 24
Peak memory 216268 kb
Host smart-b8aa851f-6bd1-46ef-80e9-e0cb59fe14a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212171654 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2212171654
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.111979827
Short name T800
Test name
Test status
Simulation time 1331772404 ps
CPU time 9.24 seconds
Started Jan 24 07:40:40 PM PST 24
Finished Jan 24 07:40:51 PM PST 24
Peak memory 217828 kb
Host smart-6f4cda6f-b555-4859-9b3a-39e995b1760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111979827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.111979827
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1685847896
Short name T801
Test name
Test status
Simulation time 19191313 ps
CPU time 1.09 seconds
Started Jan 24 07:40:47 PM PST 24
Finished Jan 24 07:40:50 PM PST 24
Peak memory 214612 kb
Host smart-bf0e476a-c5d9-4b4a-8451-89a138373720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685847896 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1685847896
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3426222287
Short name T722
Test name
Test status
Simulation time 104828088 ps
CPU time 0.89 seconds
Started Jan 24 07:40:47 PM PST 24
Finished Jan 24 07:40:49 PM PST 24
Peak memory 214556 kb
Host smart-e0b9aeb2-16a1-4059-a3fb-a82e3d7c98ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426222287 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3426222287
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3492028868
Short name T109
Test name
Test status
Simulation time 1035100282 ps
CPU time 2.97 seconds
Started Jan 24 07:40:47 PM PST 24
Finished Jan 24 07:40:52 PM PST 24
Peak memory 214544 kb
Host smart-ef51bbbc-4f94-4618-ae78-4e893a30c86c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492028868 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3492028868
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1640116659
Short name T674
Test name
Test status
Simulation time 76431737687 ps
CPU time 510.63 seconds
Started Jan 24 07:40:41 PM PST 24
Finished Jan 24 07:49:13 PM PST 24
Peak memory 216888 kb
Host smart-2b570d38-b8e7-42de-9a60-260adde94a70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640116659 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1640116659
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.50653986
Short name T803
Test name
Test status
Simulation time 48282752 ps
CPU time 0.92 seconds
Started Jan 24 07:40:44 PM PST 24
Finished Jan 24 07:40:46 PM PST 24
Peak memory 205696 kb
Host smart-379a22de-a987-4960-8e62-620890f3ca88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50653986 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.50653986
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1329049821
Short name T483
Test name
Test status
Simulation time 46159047 ps
CPU time 0.84 seconds
Started Jan 24 07:40:49 PM PST 24
Finished Jan 24 07:40:52 PM PST 24
Peak memory 205084 kb
Host smart-78878457-9f45-4817-8df7-a46ca2729239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329049821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1329049821
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.735858654
Short name T826
Test name
Test status
Simulation time 75318672 ps
CPU time 0.81 seconds
Started Jan 24 07:40:49 PM PST 24
Finished Jan 24 07:40:51 PM PST 24
Peak memory 214784 kb
Host smart-9ea931e2-29d4-4346-bba2-e6e5aa49fe0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735858654 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.735858654
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_err.2786768953
Short name T456
Test name
Test status
Simulation time 17993200 ps
CPU time 1.13 seconds
Started Jan 24 07:40:47 PM PST 24
Finished Jan 24 07:40:50 PM PST 24
Peak memory 222096 kb
Host smart-efafa591-1458-4cee-bfd4-adabbba88021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786768953 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2786768953
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2577513452
Short name T591
Test name
Test status
Simulation time 18200828 ps
CPU time 1.22 seconds
Started Jan 24 07:55:49 PM PST 24
Finished Jan 24 07:55:51 PM PST 24
Peak memory 216220 kb
Host smart-59585cd4-9786-4c4c-b2cb-0360d4dba9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577513452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2577513452
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1697014394
Short name T711
Test name
Test status
Simulation time 35616318 ps
CPU time 0.86 seconds
Started Jan 24 09:07:57 PM PST 24
Finished Jan 24 09:07:59 PM PST 24
Peak memory 214536 kb
Host smart-09cc61da-086c-40e7-aec6-5d7222059886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697014394 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1697014394
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1974381742
Short name T480
Test name
Test status
Simulation time 15157895 ps
CPU time 0.96 seconds
Started Jan 24 08:13:58 PM PST 24
Finished Jan 24 08:13:59 PM PST 24
Peak memory 214616 kb
Host smart-de4d6e99-e387-4fe9-abe4-37f924154f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974381742 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1974381742
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1434058057
Short name T947
Test name
Test status
Simulation time 322941467 ps
CPU time 2.98 seconds
Started Jan 24 09:23:23 PM PST 24
Finished Jan 24 09:23:26 PM PST 24
Peak memory 217644 kb
Host smart-ca55ef62-175e-4d32-b5a2-5d8ca9682986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434058057 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1434058057
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3594456432
Short name T842
Test name
Test status
Simulation time 149419358672 ps
CPU time 1414.73 seconds
Started Jan 24 07:40:47 PM PST 24
Finished Jan 24 08:04:23 PM PST 24
Peak memory 223620 kb
Host smart-14753e6e-1c30-4a7d-8828-a19119f7190d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594456432 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3594456432
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.812691814
Short name T248
Test name
Test status
Simulation time 75210112 ps
CPU time 0.98 seconds
Started Jan 24 07:41:02 PM PST 24
Finished Jan 24 07:41:04 PM PST 24
Peak memory 206424 kb
Host smart-9ab85215-3da0-4610-9500-52f9d680dbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812691814 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.812691814
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1303080123
Short name T788
Test name
Test status
Simulation time 16890309 ps
CPU time 0.92 seconds
Started Jan 24 07:41:00 PM PST 24
Finished Jan 24 07:41:02 PM PST 24
Peak memory 205620 kb
Host smart-70ec1de1-0f48-4695-bd7f-c41200d77abf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303080123 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1303080123
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2396771029
Short name T835
Test name
Test status
Simulation time 41747346 ps
CPU time 0.93 seconds
Started Jan 24 07:41:01 PM PST 24
Finished Jan 24 07:41:04 PM PST 24
Peak memory 214968 kb
Host smart-0de1eac2-53cb-4ff8-81f5-b637e3eabc62
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396771029 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2396771029
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.115231451
Short name T412
Test name
Test status
Simulation time 22412219 ps
CPU time 0.89 seconds
Started Jan 24 07:41:02 PM PST 24
Finished Jan 24 07:41:04 PM PST 24
Peak memory 216160 kb
Host smart-4df37a13-9e3a-411d-bb9c-15357af1d8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115231451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.115231451
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2043578970
Short name T507
Test name
Test status
Simulation time 232460993 ps
CPU time 1.03 seconds
Started Jan 24 07:40:45 PM PST 24
Finished Jan 24 07:40:47 PM PST 24
Peak memory 214716 kb
Host smart-939edd7a-1d33-412f-8a6e-b3c1a31acef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043578970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2043578970
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2386601451
Short name T120
Test name
Test status
Simulation time 20339904 ps
CPU time 1.01 seconds
Started Jan 24 07:40:59 PM PST 24
Finished Jan 24 07:41:02 PM PST 24
Peak memory 214932 kb
Host smart-dae44376-4c98-4a22-8dcd-3fdc388b73b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386601451 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2386601451
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.158716662
Short name T791
Test name
Test status
Simulation time 133434653 ps
CPU time 0.95 seconds
Started Jan 24 07:40:45 PM PST 24
Finished Jan 24 07:40:46 PM PST 24
Peak memory 214608 kb
Host smart-a195ffe7-da7e-4267-aaba-b54e6f212464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158716662 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.158716662
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1376481157
Short name T271
Test name
Test status
Simulation time 172648562471 ps
CPU time 1104.06 seconds
Started Jan 24 07:41:01 PM PST 24
Finished Jan 24 07:59:26 PM PST 24
Peak memory 220752 kb
Host smart-28530eed-b121-4aaa-9f28-d09251c4b7ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376481157 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1376481157
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.4200306280
Short name T241
Test name
Test status
Simulation time 62391765 ps
CPU time 0.94 seconds
Started Jan 24 07:40:58 PM PST 24
Finished Jan 24 07:41:00 PM PST 24
Peak memory 206364 kb
Host smart-fb678783-11d7-4df5-87c3-f20f2661a009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200306280 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.4200306280
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1556594392
Short name T426
Test name
Test status
Simulation time 17637318 ps
CPU time 0.96 seconds
Started Jan 24 07:41:02 PM PST 24
Finished Jan 24 07:41:05 PM PST 24
Peak memory 205036 kb
Host smart-7e83607d-9c78-4a84-a8c1-79e9e8a5ccee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556594392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1556594392
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2074966054
Short name T908
Test name
Test status
Simulation time 39430067 ps
CPU time 0.87 seconds
Started Jan 24 07:41:02 PM PST 24
Finished Jan 24 07:41:05 PM PST 24
Peak memory 214820 kb
Host smart-fe8e81a0-1fcf-42ff-96f7-b9098c5302c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074966054 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2074966054
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2414412825
Short name T550
Test name
Test status
Simulation time 89798723 ps
CPU time 1.11 seconds
Started Jan 24 07:40:59 PM PST 24
Finished Jan 24 07:41:01 PM PST 24
Peak memory 214968 kb
Host smart-46365cf3-5c7d-4e26-ae11-4dfa4fcad7a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414412825 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2414412825
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.1519971179
Short name T469
Test name
Test status
Simulation time 20692546 ps
CPU time 0.98 seconds
Started Jan 24 07:41:05 PM PST 24
Finished Jan 24 07:41:07 PM PST 24
Peak memory 221980 kb
Host smart-e4a86053-03b7-41c7-bbb5-620f55081f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519971179 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.1519971179
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.2576299944
Short name T896
Test name
Test status
Simulation time 17593400 ps
CPU time 1.11 seconds
Started Jan 24 07:41:02 PM PST 24
Finished Jan 24 07:41:05 PM PST 24
Peak memory 214948 kb
Host smart-9d6ba721-fb39-4d48-8d35-23463139939b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576299944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.2576299944
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1006405049
Short name T89
Test name
Test status
Simulation time 27177936 ps
CPU time 0.93 seconds
Started Jan 24 07:41:00 PM PST 24
Finished Jan 24 07:41:02 PM PST 24
Peak memory 214740 kb
Host smart-edb886d9-d1d4-4c69-8509-79e63acc0ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006405049 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1006405049
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3747960368
Short name T872
Test name
Test status
Simulation time 44499574 ps
CPU time 0.9 seconds
Started Jan 24 07:41:09 PM PST 24
Finished Jan 24 07:41:11 PM PST 24
Peak memory 214576 kb
Host smart-73538220-5e6b-4871-a193-e98e9d3dc99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747960368 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3747960368
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.12917350
Short name T590
Test name
Test status
Simulation time 142091088 ps
CPU time 1.39 seconds
Started Jan 24 07:41:01 PM PST 24
Finished Jan 24 07:41:03 PM PST 24
Peak memory 206488 kb
Host smart-dfca39fc-e1eb-4650-8d29-7c3a553da4d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12917350 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.12917350
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1158470345
Short name T614
Test name
Test status
Simulation time 20986026792 ps
CPU time 446.18 seconds
Started Jan 24 07:41:01 PM PST 24
Finished Jan 24 07:48:28 PM PST 24
Peak memory 222992 kb
Host smart-692213b3-d739-458c-8427-093a2dbe40c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158470345 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1158470345
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.195489646
Short name T17
Test name
Test status
Simulation time 69973019 ps
CPU time 1 seconds
Started Jan 24 07:41:08 PM PST 24
Finished Jan 24 07:41:10 PM PST 24
Peak memory 205704 kb
Host smart-078bb6cb-719b-485f-8968-b65cbea92301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195489646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.195489646
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.3747560558
Short name T915
Test name
Test status
Simulation time 18249823 ps
CPU time 0.89 seconds
Started Jan 24 07:41:08 PM PST 24
Finished Jan 24 07:41:10 PM PST 24
Peak memory 205000 kb
Host smart-3d24f571-4876-41f5-90e8-b55f9cf2f42c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747560558 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.3747560558
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.411204793
Short name T368
Test name
Test status
Simulation time 69197371 ps
CPU time 0.86 seconds
Started Jan 24 07:41:08 PM PST 24
Finished Jan 24 07:41:10 PM PST 24
Peak memory 214792 kb
Host smart-f8c75132-47da-4ef3-997a-141fe2ab47f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411204793 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.411204793
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_err.2281764759
Short name T459
Test name
Test status
Simulation time 18092280 ps
CPU time 1.05 seconds
Started Jan 24 07:41:09 PM PST 24
Finished Jan 24 07:41:12 PM PST 24
Peak memory 216128 kb
Host smart-677177ff-bc33-4f79-a89f-e2dcc3c63fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281764759 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2281764759
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3655020113
Short name T911
Test name
Test status
Simulation time 36917384 ps
CPU time 1.08 seconds
Started Jan 24 07:41:02 PM PST 24
Finished Jan 24 07:41:04 PM PST 24
Peak memory 215000 kb
Host smart-b02b188f-2bf9-424e-a03d-f43f53f24346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655020113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3655020113
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1721235819
Short name T861
Test name
Test status
Simulation time 18764532 ps
CPU time 1.13 seconds
Started Jan 24 07:41:07 PM PST 24
Finished Jan 24 07:41:09 PM PST 24
Peak memory 221644 kb
Host smart-e5d43d35-8d8d-4e02-9cdc-45212857c331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721235819 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1721235819
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3448921115
Short name T488
Test name
Test status
Simulation time 13721093 ps
CPU time 0.98 seconds
Started Jan 24 07:41:02 PM PST 24
Finished Jan 24 07:41:05 PM PST 24
Peak memory 214604 kb
Host smart-ee00c9f0-369f-44a4-8042-ca0cc5c8de1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448921115 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3448921115
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3004312770
Short name T731
Test name
Test status
Simulation time 308172737 ps
CPU time 3.18 seconds
Started Jan 24 07:41:01 PM PST 24
Finished Jan 24 07:41:05 PM PST 24
Peak memory 214880 kb
Host smart-969d5a49-fba1-4774-88c5-195180cdb55f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004312770 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3004312770
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.3311367132
Short name T455
Test name
Test status
Simulation time 103990614738 ps
CPU time 2069 seconds
Started Jan 24 07:41:09 PM PST 24
Finished Jan 24 08:15:40 PM PST 24
Peak memory 224464 kb
Host smart-a61d0fed-658b-409e-880c-3215e031cd47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311367132 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.3311367132
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.4266868289
Short name T875
Test name
Test status
Simulation time 90967048 ps
CPU time 0.99 seconds
Started Jan 24 07:41:23 PM PST 24
Finished Jan 24 07:41:25 PM PST 24
Peak memory 206400 kb
Host smart-d0f7f99a-c5bc-4fe7-a372-204b00772dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266868289 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.4266868289
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2947498223
Short name T410
Test name
Test status
Simulation time 118387058 ps
CPU time 0.86 seconds
Started Jan 24 07:41:25 PM PST 24
Finished Jan 24 07:41:27 PM PST 24
Peak memory 205500 kb
Host smart-1e6e172b-1663-4736-a138-fee2a5f1de02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947498223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2947498223
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2928344619
Short name T471
Test name
Test status
Simulation time 11104062 ps
CPU time 0.85 seconds
Started Jan 24 07:41:18 PM PST 24
Finished Jan 24 07:41:20 PM PST 24
Peak memory 214788 kb
Host smart-71c4a9e4-2a93-4e75-a5f2-631517959bcd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928344619 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2928344619
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.31272098
Short name T644
Test name
Test status
Simulation time 60258674 ps
CPU time 0.94 seconds
Started Jan 24 08:52:27 PM PST 24
Finished Jan 24 08:52:29 PM PST 24
Peak memory 214976 kb
Host smart-a014c6c6-ef05-4b15-a47e-e4bc9c6d2875
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31272098 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_dis
able_auto_req_mode.31272098
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.2887462674
Short name T623
Test name
Test status
Simulation time 28768642 ps
CPU time 0.97 seconds
Started Jan 24 07:41:18 PM PST 24
Finished Jan 24 07:41:21 PM PST 24
Peak memory 221592 kb
Host smart-2d8314a4-ae82-43ff-8048-bb0160b939eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887462674 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2887462674
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1303104519
Short name T651
Test name
Test status
Simulation time 33851943 ps
CPU time 1.17 seconds
Started Jan 24 07:41:09 PM PST 24
Finished Jan 24 07:41:12 PM PST 24
Peak memory 216212 kb
Host smart-e0637796-869d-4a94-89ed-e61121057d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303104519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1303104519
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3470487999
Short name T579
Test name
Test status
Simulation time 31023302 ps
CPU time 1.04 seconds
Started Jan 24 07:41:17 PM PST 24
Finished Jan 24 07:41:19 PM PST 24
Peak memory 222152 kb
Host smart-03ad9afd-c789-4c8c-a441-77ee0c9c7ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470487999 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3470487999
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.338272486
Short name T506
Test name
Test status
Simulation time 19674287 ps
CPU time 0.94 seconds
Started Jan 24 07:41:09 PM PST 24
Finished Jan 24 07:41:12 PM PST 24
Peak memory 214612 kb
Host smart-c91140ff-420d-454f-808d-68141d449a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338272486 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.338272486
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3869994023
Short name T790
Test name
Test status
Simulation time 28259055 ps
CPU time 1.2 seconds
Started Jan 24 07:41:23 PM PST 24
Finished Jan 24 07:41:25 PM PST 24
Peak memory 214572 kb
Host smart-f3858504-cdd3-437f-9189-ae037e77beca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869994023 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3869994023
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3246497010
Short name T669
Test name
Test status
Simulation time 152899631281 ps
CPU time 1670.85 seconds
Started Jan 24 07:57:42 PM PST 24
Finished Jan 24 08:25:34 PM PST 24
Peak memory 222864 kb
Host smart-9625c96a-33bd-43ca-b765-9210a39dba53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246497010 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3246497010
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1223144820
Short name T776
Test name
Test status
Simulation time 20813643 ps
CPU time 1.01 seconds
Started Jan 24 07:41:23 PM PST 24
Finished Jan 24 07:41:25 PM PST 24
Peak memory 205708 kb
Host smart-53851130-4377-44fb-93ef-b5a43ad8d7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223144820 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1223144820
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1355369938
Short name T639
Test name
Test status
Simulation time 43242478 ps
CPU time 0.86 seconds
Started Jan 24 07:41:29 PM PST 24
Finished Jan 24 07:41:31 PM PST 24
Peak memory 205064 kb
Host smart-6aca98ef-47ca-4597-b7b4-88363f52488a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355369938 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1355369938
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1628143367
Short name T144
Test name
Test status
Simulation time 21221107 ps
CPU time 0.88 seconds
Started Jan 24 07:41:31 PM PST 24
Finished Jan 24 07:41:33 PM PST 24
Peak memory 214840 kb
Host smart-e6fa2f70-4d0e-4020-ac32-4cf11db68f07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628143367 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1628143367
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2418635564
Short name T492
Test name
Test status
Simulation time 19318120 ps
CPU time 1.03 seconds
Started Jan 24 07:41:30 PM PST 24
Finished Jan 24 07:41:33 PM PST 24
Peak memory 215004 kb
Host smart-84b2051f-5f09-457b-a393-2a19afdee633
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418635564 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2418635564
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.5560889
Short name T444
Test name
Test status
Simulation time 22978240 ps
CPU time 0.89 seconds
Started Jan 24 07:41:30 PM PST 24
Finished Jan 24 07:41:32 PM PST 24
Peak memory 215788 kb
Host smart-b7934ff7-015e-4b6c-a3a6-ebc69cfecd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5560889 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.5560889
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2437448982
Short name T883
Test name
Test status
Simulation time 20237492 ps
CPU time 1.17 seconds
Started Jan 24 07:41:23 PM PST 24
Finished Jan 24 07:41:26 PM PST 24
Peak memory 215008 kb
Host smart-2e5fc0bc-b9dd-4126-b901-70a0f91d450d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437448982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2437448982
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1141897458
Short name T96
Test name
Test status
Simulation time 18512006 ps
CPU time 1.03 seconds
Started Jan 24 07:41:23 PM PST 24
Finished Jan 24 07:41:26 PM PST 24
Peak memory 214864 kb
Host smart-5ee7ab20-2ab3-4743-aa6d-20138f1106fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141897458 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1141897458
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.464896071
Short name T451
Test name
Test status
Simulation time 15870695 ps
CPU time 0.91 seconds
Started Jan 24 07:41:20 PM PST 24
Finished Jan 24 07:41:22 PM PST 24
Peak memory 214596 kb
Host smart-90f1045e-b286-40bb-bfc2-9d661cdcae18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464896071 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.464896071
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3285340191
Short name T541
Test name
Test status
Simulation time 92167389 ps
CPU time 1.23 seconds
Started Jan 24 07:41:24 PM PST 24
Finished Jan 24 07:41:27 PM PST 24
Peak memory 206396 kb
Host smart-5468e3fb-0cf3-4cdf-b000-ca5fc45030bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285340191 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3285340191
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.449472640
Short name T261
Test name
Test status
Simulation time 12727092878 ps
CPU time 282.04 seconds
Started Jan 24 07:41:22 PM PST 24
Finished Jan 24 07:46:05 PM PST 24
Peak memory 216396 kb
Host smart-d53a73bf-943e-4f5a-992a-1b5a109426a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449472640 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.449472640
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2350514608
Short name T254
Test name
Test status
Simulation time 30613631 ps
CPU time 0.9 seconds
Started Jan 24 07:41:42 PM PST 24
Finished Jan 24 07:41:45 PM PST 24
Peak memory 205600 kb
Host smart-82313516-b0cd-4cbc-9350-5cf3a9517652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350514608 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2350514608
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.551404028
Short name T384
Test name
Test status
Simulation time 36537763 ps
CPU time 0.86 seconds
Started Jan 24 07:41:47 PM PST 24
Finished Jan 24 07:41:56 PM PST 24
Peak memory 204828 kb
Host smart-36b5db4b-e9d3-4a80-b17b-c4598687c5b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551404028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.551404028
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.2164073817
Short name T559
Test name
Test status
Simulation time 12660042 ps
CPU time 0.91 seconds
Started Jan 24 07:41:44 PM PST 24
Finished Jan 24 07:41:46 PM PST 24
Peak memory 214740 kb
Host smart-fe98f900-589a-4f9e-b0bb-3dcedc2017e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164073817 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.2164073817
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2504045379
Short name T482
Test name
Test status
Simulation time 65038778 ps
CPU time 1 seconds
Started Jan 24 07:41:41 PM PST 24
Finished Jan 24 07:41:44 PM PST 24
Peak memory 214976 kb
Host smart-1b9ec03e-ff3c-4c67-afb1-337c0e609d82
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504045379 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2504045379
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1095618492
Short name T8
Test name
Test status
Simulation time 46965034 ps
CPU time 0.94 seconds
Started Jan 24 07:41:42 PM PST 24
Finished Jan 24 07:41:45 PM PST 24
Peak memory 216332 kb
Host smart-e9097ce0-12e9-4d4c-ab72-4ccfbaec1e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095618492 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1095618492
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1753582058
Short name T649
Test name
Test status
Simulation time 194071797 ps
CPU time 1.02 seconds
Started Jan 24 07:41:31 PM PST 24
Finished Jan 24 07:41:33 PM PST 24
Peak memory 214876 kb
Host smart-a56fc485-8a10-402a-b33f-d5e168daeb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753582058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1753582058
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2032743172
Short name T470
Test name
Test status
Simulation time 28466332 ps
CPU time 0.96 seconds
Started Jan 24 07:41:43 PM PST 24
Finished Jan 24 07:41:46 PM PST 24
Peak memory 222052 kb
Host smart-f22adfda-837d-44a5-84de-ea6f2b70f07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032743172 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2032743172
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2364959632
Short name T917
Test name
Test status
Simulation time 11792951 ps
CPU time 0.94 seconds
Started Jan 24 07:41:29 PM PST 24
Finished Jan 24 07:41:31 PM PST 24
Peak memory 214620 kb
Host smart-ed7004bf-cb9e-4f68-a5e1-7e14994acae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364959632 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2364959632
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2664816039
Short name T401
Test name
Test status
Simulation time 672140795 ps
CPU time 4.17 seconds
Started Jan 24 07:41:41 PM PST 24
Finished Jan 24 07:41:48 PM PST 24
Peak memory 214936 kb
Host smart-f9626a57-0ad2-4151-9244-804fbd891ed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664816039 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2664816039
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3089517825
Short name T544
Test name
Test status
Simulation time 61034660238 ps
CPU time 684.35 seconds
Started Jan 24 07:41:42 PM PST 24
Finished Jan 24 07:53:09 PM PST 24
Peak memory 215816 kb
Host smart-2f7553e0-9908-4105-babf-0825aacc71f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089517825 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3089517825
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert_test.2081190360
Short name T638
Test name
Test status
Simulation time 133535830 ps
CPU time 2.68 seconds
Started Jan 24 07:41:50 PM PST 24
Finished Jan 24 07:42:00 PM PST 24
Peak memory 206084 kb
Host smart-56e1f019-16ec-41a9-8f0a-027e1a15d73f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081190360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2081190360
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.510561090
Short name T856
Test name
Test status
Simulation time 27307815 ps
CPU time 0.81 seconds
Started Jan 24 07:41:44 PM PST 24
Finished Jan 24 07:41:47 PM PST 24
Peak memory 214744 kb
Host smart-09aef256-afc0-48dd-bcf0-8e903aeb9255
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510561090 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.510561090
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.4053988146
Short name T680
Test name
Test status
Simulation time 27630565 ps
CPU time 1.14 seconds
Started Jan 24 07:41:56 PM PST 24
Finished Jan 24 07:42:04 PM PST 24
Peak memory 215064 kb
Host smart-fd926b5c-7dcf-41b6-865b-4bdf40f83b26
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053988146 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.4053988146
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.4098020715
Short name T534
Test name
Test status
Simulation time 18576664 ps
CPU time 1 seconds
Started Jan 24 07:41:41 PM PST 24
Finished Jan 24 07:41:45 PM PST 24
Peak memory 215984 kb
Host smart-bc98df98-2feb-4b95-a2d8-9e3e944a6b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098020715 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.4098020715
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.2050003936
Short name T14
Test name
Test status
Simulation time 102197700 ps
CPU time 1.29 seconds
Started Jan 24 07:41:44 PM PST 24
Finished Jan 24 07:41:47 PM PST 24
Peak memory 216012 kb
Host smart-3fbe678a-fed8-47f2-9fb4-abc0a276fc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050003936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.2050003936
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3766265720
Short name T728
Test name
Test status
Simulation time 19516193 ps
CPU time 1.19 seconds
Started Jan 24 07:41:50 PM PST 24
Finished Jan 24 07:41:59 PM PST 24
Peak memory 221940 kb
Host smart-be600e6d-faa2-4188-83ad-b442b2f58af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766265720 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3766265720
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3998772277
Short name T381
Test name
Test status
Simulation time 14541580 ps
CPU time 0.93 seconds
Started Jan 24 07:41:46 PM PST 24
Finished Jan 24 07:41:48 PM PST 24
Peak memory 214576 kb
Host smart-0babf426-0c56-4c8f-9671-187c25267824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998772277 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3998772277
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.1510242412
Short name T647
Test name
Test status
Simulation time 975142691 ps
CPU time 4.02 seconds
Started Jan 24 07:41:46 PM PST 24
Finished Jan 24 07:41:52 PM PST 24
Peak memory 214712 kb
Host smart-dd042e59-b03f-4e8b-8011-98ab9b5ef3d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510242412 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.1510242412
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.775344043
Short name T259
Test name
Test status
Simulation time 56038134681 ps
CPU time 1304.62 seconds
Started Jan 24 07:41:49 PM PST 24
Finished Jan 24 08:03:42 PM PST 24
Peak memory 218552 kb
Host smart-6c51326b-238c-4f9e-94fe-67352353c456
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775344043 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.775344043
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.13435414
Short name T206
Test name
Test status
Simulation time 66622811 ps
CPU time 0.94 seconds
Started Jan 24 07:41:52 PM PST 24
Finished Jan 24 07:41:59 PM PST 24
Peak memory 206348 kb
Host smart-43c4e52e-bb6b-41d0-b99d-0191bdef91bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13435414 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.13435414
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.3676781835
Short name T643
Test name
Test status
Simulation time 38329646 ps
CPU time 0.77 seconds
Started Jan 24 07:41:53 PM PST 24
Finished Jan 24 07:42:00 PM PST 24
Peak memory 204476 kb
Host smart-d8f2631f-b397-44fd-a889-c62c723319c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676781835 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.3676781835
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.3892132267
Short name T137
Test name
Test status
Simulation time 32355127 ps
CPU time 0.81 seconds
Started Jan 24 07:41:53 PM PST 24
Finished Jan 24 07:42:00 PM PST 24
Peak memory 214836 kb
Host smart-b111301c-eebe-4d12-bfe7-2f5a5e6a47eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892132267 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.3892132267
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.705399850
Short name T733
Test name
Test status
Simulation time 27523038 ps
CPU time 1.09 seconds
Started Jan 24 07:41:56 PM PST 24
Finished Jan 24 07:42:08 PM PST 24
Peak memory 214960 kb
Host smart-9bd608f4-0b7a-46c5-9d75-c43aad04138f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705399850 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_di
sable_auto_req_mode.705399850
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3709205458
Short name T710
Test name
Test status
Simulation time 18565628 ps
CPU time 1.01 seconds
Started Jan 24 07:41:53 PM PST 24
Finished Jan 24 07:42:01 PM PST 24
Peak memory 216472 kb
Host smart-0789d499-9d5f-4501-8c03-c7fb45619284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709205458 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3709205458
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.1484541707
Short name T571
Test name
Test status
Simulation time 17390341 ps
CPU time 1.13 seconds
Started Jan 24 07:41:50 PM PST 24
Finished Jan 24 07:41:59 PM PST 24
Peak memory 214880 kb
Host smart-08790aaa-6cc8-4b90-b0a1-8eef66c5476d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484541707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.1484541707
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2247254461
Short name T853
Test name
Test status
Simulation time 24667242 ps
CPU time 0.95 seconds
Started Jan 24 07:41:53 PM PST 24
Finished Jan 24 07:41:59 PM PST 24
Peak memory 214736 kb
Host smart-3e864010-5cdf-4e40-a582-e45432fb6770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247254461 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2247254461
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2915702126
Short name T399
Test name
Test status
Simulation time 20995915 ps
CPU time 0.9 seconds
Started Jan 24 07:41:53 PM PST 24
Finished Jan 24 07:42:01 PM PST 24
Peak memory 214632 kb
Host smart-3964ceb1-9ae3-4161-93cd-9e261fa05e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915702126 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2915702126
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.1381044596
Short name T574
Test name
Test status
Simulation time 60854316 ps
CPU time 1.88 seconds
Started Jan 24 07:41:50 PM PST 24
Finished Jan 24 07:41:59 PM PST 24
Peak memory 214672 kb
Host smart-a9e8435c-ca10-4b4b-80b8-b3aea61c6b24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381044596 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.1381044596
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.245612183
Short name T556
Test name
Test status
Simulation time 65149243152 ps
CPU time 1445.4 seconds
Started Jan 24 07:41:56 PM PST 24
Finished Jan 24 08:06:12 PM PST 24
Peak memory 220816 kb
Host smart-86718bff-1c5d-4ba2-ad9f-e623976636ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245612183 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.245612183
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.2469731706
Short name T846
Test name
Test status
Simulation time 103879883 ps
CPU time 0.98 seconds
Started Jan 24 07:36:25 PM PST 24
Finished Jan 24 07:36:28 PM PST 24
Peak memory 206412 kb
Host smart-52dc4c82-ee1a-4f1b-ba50-4803d183b14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469731706 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.2469731706
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2885237630
Short name T602
Test name
Test status
Simulation time 68303549 ps
CPU time 0.86 seconds
Started Jan 24 07:41:23 PM PST 24
Finished Jan 24 07:41:25 PM PST 24
Peak memory 205488 kb
Host smart-8214f238-0d45-4d2e-857b-915586a358d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885237630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2885237630
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1744748971
Short name T460
Test name
Test status
Simulation time 21075674 ps
CPU time 0.83 seconds
Started Jan 24 08:59:43 PM PST 24
Finished Jan 24 08:59:45 PM PST 24
Peak memory 214832 kb
Host smart-194cac2b-24aa-4c74-aa41-18406bf32474
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744748971 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1744748971
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1994021823
Short name T117
Test name
Test status
Simulation time 91783673 ps
CPU time 1.05 seconds
Started Jan 24 07:36:26 PM PST 24
Finished Jan 24 07:36:28 PM PST 24
Peak memory 214988 kb
Host smart-2587518f-c274-4d9a-9e2f-155831187a8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994021823 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1994021823
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.627268296
Short name T503
Test name
Test status
Simulation time 19561889 ps
CPU time 0.94 seconds
Started Jan 24 07:36:24 PM PST 24
Finished Jan 24 07:36:27 PM PST 24
Peak memory 216092 kb
Host smart-fb269b66-9f43-4873-979f-f2c45dc2ee73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627268296 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.627268296
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2045239403
Short name T783
Test name
Test status
Simulation time 38998153 ps
CPU time 1.33 seconds
Started Jan 24 07:36:16 PM PST 24
Finished Jan 24 07:36:21 PM PST 24
Peak memory 216212 kb
Host smart-3d4f39b7-c93f-460c-816f-07bf8d0b0042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045239403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2045239403
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3534049231
Short name T822
Test name
Test status
Simulation time 36991999 ps
CPU time 0.89 seconds
Started Jan 24 07:36:15 PM PST 24
Finished Jan 24 07:36:19 PM PST 24
Peak memory 214760 kb
Host smart-e5fd8b1a-e5b6-4be3-90d5-0de9230385c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534049231 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3534049231
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3664558764
Short name T73
Test name
Test status
Simulation time 37549606 ps
CPU time 0.85 seconds
Started Jan 24 07:36:17 PM PST 24
Finished Jan 24 07:36:21 PM PST 24
Peak memory 206372 kb
Host smart-0c764164-202a-443b-b69f-561e77306b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664558764 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3664558764
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.2107962017
Short name T824
Test name
Test status
Simulation time 11498296 ps
CPU time 0.92 seconds
Started Jan 24 07:36:18 PM PST 24
Finished Jan 24 07:36:23 PM PST 24
Peak memory 214552 kb
Host smart-3adb5399-dba0-440b-8061-7f1373899ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107962017 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2107962017
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.1062189762
Short name T464
Test name
Test status
Simulation time 53979060 ps
CPU time 1.77 seconds
Started Jan 24 07:36:18 PM PST 24
Finished Jan 24 07:36:23 PM PST 24
Peak memory 214564 kb
Host smart-8fecf0be-e071-498c-8262-50522cb43011
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062189762 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.1062189762
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.3753701080
Short name T411
Test name
Test status
Simulation time 128139987045 ps
CPU time 795.14 seconds
Started Jan 24 07:36:14 PM PST 24
Finished Jan 24 07:49:33 PM PST 24
Peak memory 223016 kb
Host smart-aac203a3-7b89-4557-bedf-aaf001605a2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753701080 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.3753701080
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.102132220
Short name T652
Test name
Test status
Simulation time 50348537 ps
CPU time 1.07 seconds
Started Jan 24 07:41:55 PM PST 24
Finished Jan 24 07:42:04 PM PST 24
Peak memory 222140 kb
Host smart-cfb29477-90ba-4201-a876-e0f563f73fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102132220 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.102132220
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.134635325
Short name T634
Test name
Test status
Simulation time 97595674 ps
CPU time 1.25 seconds
Started Jan 24 07:41:56 PM PST 24
Finished Jan 24 07:42:05 PM PST 24
Peak memory 214736 kb
Host smart-fdd397b3-def9-4b31-8d59-f43a395dca31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134635325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.134635325
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.317655687
Short name T54
Test name
Test status
Simulation time 23993666 ps
CPU time 1 seconds
Started Jan 24 07:41:50 PM PST 24
Finished Jan 24 07:41:59 PM PST 24
Peak memory 221644 kb
Host smart-c31e3adb-0a9d-495e-a591-cc9c6f7d1752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317655687 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.317655687
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.4115915312
Short name T587
Test name
Test status
Simulation time 18691378 ps
CPU time 1.05 seconds
Started Jan 24 07:41:53 PM PST 24
Finished Jan 24 07:42:01 PM PST 24
Peak memory 214760 kb
Host smart-835821f3-7415-4e1a-a524-2e670bf22c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115915312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.4115915312
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.3680754676
Short name T580
Test name
Test status
Simulation time 25961399 ps
CPU time 0.98 seconds
Started Jan 24 07:42:01 PM PST 24
Finished Jan 24 07:42:10 PM PST 24
Peak memory 222032 kb
Host smart-90afc69c-778f-406a-a7b1-e62ee5d86893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680754676 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3680754676
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.899781168
Short name T442
Test name
Test status
Simulation time 95189206 ps
CPU time 1.09 seconds
Started Jan 24 07:41:54 PM PST 24
Finished Jan 24 07:42:03 PM PST 24
Peak memory 215968 kb
Host smart-e57e28a7-dffa-475f-97aa-094f9c0aed6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899781168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.899781168
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.1971384402
Short name T70
Test name
Test status
Simulation time 44575555 ps
CPU time 1.12 seconds
Started Jan 24 07:42:02 PM PST 24
Finished Jan 24 07:42:11 PM PST 24
Peak memory 217444 kb
Host smart-a6709f59-9aec-4e3c-86be-033b08ab5acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971384402 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1971384402
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.505397516
Short name T836
Test name
Test status
Simulation time 17932736 ps
CPU time 1.02 seconds
Started Jan 24 07:46:30 PM PST 24
Finished Jan 24 07:46:31 PM PST 24
Peak memory 214848 kb
Host smart-332b37b1-01e8-4d7e-80e0-f04f6ec4d203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505397516 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.505397516
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.1466556363
Short name T599
Test name
Test status
Simulation time 23070743 ps
CPU time 0.97 seconds
Started Jan 24 07:42:04 PM PST 24
Finished Jan 24 07:42:12 PM PST 24
Peak memory 216512 kb
Host smart-7701e620-c534-40d5-8bbe-d540718bcd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466556363 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1466556363
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1438647229
Short name T280
Test name
Test status
Simulation time 85918566 ps
CPU time 1.09 seconds
Started Jan 24 07:42:04 PM PST 24
Finished Jan 24 07:42:11 PM PST 24
Peak memory 214912 kb
Host smart-60bf4ba6-7879-434a-afff-23c088484c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438647229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1438647229
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.891175270
Short name T689
Test name
Test status
Simulation time 29522059 ps
CPU time 1.26 seconds
Started Jan 24 07:41:59 PM PST 24
Finished Jan 24 07:42:10 PM PST 24
Peak memory 217532 kb
Host smart-9f8dce22-a958-4754-8dcd-6fc3eafdca57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891175270 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.891175270
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.391458180
Short name T540
Test name
Test status
Simulation time 88471498 ps
CPU time 1.15 seconds
Started Jan 24 07:42:04 PM PST 24
Finished Jan 24 07:42:11 PM PST 24
Peak memory 214848 kb
Host smart-46ee81de-0490-4ded-b616-8181bfdd10e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391458180 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.391458180
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.1974657045
Short name T691
Test name
Test status
Simulation time 26894070 ps
CPU time 0.95 seconds
Started Jan 24 08:43:53 PM PST 24
Finished Jan 24 08:44:04 PM PST 24
Peak memory 222076 kb
Host smart-21897e7d-0434-49a0-ba80-e10b82a49221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974657045 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1974657045
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.746617061
Short name T40
Test name
Test status
Simulation time 34880218 ps
CPU time 1.08 seconds
Started Jan 24 07:42:02 PM PST 24
Finished Jan 24 07:42:10 PM PST 24
Peak memory 214988 kb
Host smart-3ad59078-4d55-48de-968e-53d6e6bdf96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746617061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.746617061
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.704088979
Short name T932
Test name
Test status
Simulation time 23653215 ps
CPU time 0.93 seconds
Started Jan 24 10:31:08 PM PST 24
Finished Jan 24 10:31:13 PM PST 24
Peak memory 221600 kb
Host smart-6811a606-c092-4cf4-aef0-d5f00874e330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704088979 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.704088979
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3658205888
Short name T740
Test name
Test status
Simulation time 63922896 ps
CPU time 1.17 seconds
Started Jan 24 07:42:03 PM PST 24
Finished Jan 24 07:42:11 PM PST 24
Peak memory 216264 kb
Host smart-80750b34-647d-483f-b3e0-46838ec4e92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658205888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3658205888
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.3820131698
Short name T673
Test name
Test status
Simulation time 18496629 ps
CPU time 0.97 seconds
Started Jan 24 07:42:04 PM PST 24
Finished Jan 24 07:42:11 PM PST 24
Peak memory 216016 kb
Host smart-2fa0474c-6397-4833-92f2-d522239fa7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820131698 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3820131698
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1234957846
Short name T560
Test name
Test status
Simulation time 28443685 ps
CPU time 1.3 seconds
Started Jan 24 07:42:04 PM PST 24
Finished Jan 24 07:42:12 PM PST 24
Peak memory 216188 kb
Host smart-92540071-e0ed-4140-ac74-ef4ecee10c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234957846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1234957846
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.1418827349
Short name T792
Test name
Test status
Simulation time 56910810 ps
CPU time 1.17 seconds
Started Jan 24 08:14:42 PM PST 24
Finished Jan 24 08:14:48 PM PST 24
Peak memory 230332 kb
Host smart-9c86416f-f84a-4575-b314-522f70538e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418827349 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1418827349
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.2386958570
Short name T219
Test name
Test status
Simulation time 43208893 ps
CPU time 0.9 seconds
Started Jan 24 07:42:05 PM PST 24
Finished Jan 24 07:42:11 PM PST 24
Peak memory 214848 kb
Host smart-045885b5-ae0b-4368-856d-53a54dfb330d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386958570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.2386958570
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3019975319
Short name T82
Test name
Test status
Simulation time 21446647 ps
CPU time 1.04 seconds
Started Jan 24 07:36:21 PM PST 24
Finished Jan 24 07:36:25 PM PST 24
Peak memory 205644 kb
Host smart-f8fbc916-0861-4198-80e1-eaa675d9be2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019975319 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3019975319
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.1605082003
Short name T621
Test name
Test status
Simulation time 12305353 ps
CPU time 0.91 seconds
Started Jan 24 07:36:31 PM PST 24
Finished Jan 24 07:36:33 PM PST 24
Peak memory 204924 kb
Host smart-2e2c714c-9ffe-4527-a673-df86a839996b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605082003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1605082003
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1417633335
Short name T106
Test name
Test status
Simulation time 14290281 ps
CPU time 0.89 seconds
Started Jan 24 07:36:27 PM PST 24
Finished Jan 24 07:36:29 PM PST 24
Peak memory 214932 kb
Host smart-f4be8984-da75-48cb-8e8d-c8a6af8df357
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417633335 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1417633335
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2118106276
Short name T131
Test name
Test status
Simulation time 98659413 ps
CPU time 1.11 seconds
Started Jan 24 07:36:32 PM PST 24
Finished Jan 24 07:36:35 PM PST 24
Peak memory 214980 kb
Host smart-b4a4bb4c-db82-41ce-8afd-7aacb6fcefaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118106276 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2118106276
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2239357508
Short name T723
Test name
Test status
Simulation time 23467491 ps
CPU time 1.06 seconds
Started Jan 24 07:36:29 PM PST 24
Finished Jan 24 07:36:32 PM PST 24
Peak memory 222220 kb
Host smart-1a0c57c1-3d22-4e5c-9b9f-95672a5850d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239357508 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2239357508
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_intr.2942550166
Short name T92
Test name
Test status
Simulation time 24636395 ps
CPU time 0.83 seconds
Started Jan 24 07:36:21 PM PST 24
Finished Jan 24 07:36:24 PM PST 24
Peak memory 214732 kb
Host smart-0b8f90ff-0afb-45f6-a7f3-45f073d4eb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942550166 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2942550166
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.107218837
Short name T244
Test name
Test status
Simulation time 12725337 ps
CPU time 0.93 seconds
Started Jan 24 08:19:10 PM PST 24
Finished Jan 24 08:19:14 PM PST 24
Peak memory 206408 kb
Host smart-9a9c9bb3-d67b-4029-a7cb-80503514ccac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107218837 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.107218837
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3586339684
Short name T376
Test name
Test status
Simulation time 42615514 ps
CPU time 0.88 seconds
Started Jan 24 07:36:22 PM PST 24
Finished Jan 24 07:36:27 PM PST 24
Peak memory 214612 kb
Host smart-11bfdaf1-e452-4726-8734-61ac53241bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586339684 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3586339684
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1484807306
Short name T221
Test name
Test status
Simulation time 34891673 ps
CPU time 1.3 seconds
Started Jan 24 07:36:25 PM PST 24
Finished Jan 24 07:36:28 PM PST 24
Peak memory 214488 kb
Host smart-0039ad15-7540-4702-a4ed-cb8d9030fc5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484807306 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1484807306
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.231823534
Short name T778
Test name
Test status
Simulation time 52218684179 ps
CPU time 1294.81 seconds
Started Jan 24 07:36:29 PM PST 24
Finished Jan 24 07:58:06 PM PST 24
Peak memory 220876 kb
Host smart-dede45d3-9b57-454c-bef4-1f0bbf59ec14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231823534 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.231823534
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_genbits.3532987144
Short name T403
Test name
Test status
Simulation time 37307180 ps
CPU time 1.04 seconds
Started Jan 24 07:42:01 PM PST 24
Finished Jan 24 07:42:10 PM PST 24
Peak memory 214720 kb
Host smart-fda5acf6-cfe7-46a0-9df4-374d0afed7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532987144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3532987144
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.159949969
Short name T730
Test name
Test status
Simulation time 19736985 ps
CPU time 1 seconds
Started Jan 24 07:42:03 PM PST 24
Finished Jan 24 07:42:11 PM PST 24
Peak memory 216488 kb
Host smart-e3dae208-fbdc-45e3-887a-6847b940fabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159949969 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.159949969
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2056670494
Short name T671
Test name
Test status
Simulation time 29387813 ps
CPU time 1.17 seconds
Started Jan 24 08:50:15 PM PST 24
Finished Jan 24 08:50:17 PM PST 24
Peak memory 215964 kb
Host smart-1b01c038-99a7-4692-aaa4-5348a1746d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056670494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2056670494
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_genbits.4176565133
Short name T266
Test name
Test status
Simulation time 39780489 ps
CPU time 1.03 seconds
Started Jan 24 07:42:04 PM PST 24
Finished Jan 24 07:42:11 PM PST 24
Peak memory 214964 kb
Host smart-8b16089a-d335-430d-9355-aabefb815187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176565133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.4176565133
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.481943805
Short name T736
Test name
Test status
Simulation time 18740636 ps
CPU time 1.15 seconds
Started Jan 24 07:42:15 PM PST 24
Finished Jan 24 07:42:18 PM PST 24
Peak memory 221676 kb
Host smart-070ad942-0e81-4a01-bdd5-2514b0dca1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481943805 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.481943805
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.4268415523
Short name T498
Test name
Test status
Simulation time 34343538 ps
CPU time 1.23 seconds
Started Jan 24 07:42:13 PM PST 24
Finished Jan 24 07:42:17 PM PST 24
Peak memory 216956 kb
Host smart-9807d8ec-0837-4eae-a319-e9a5363db9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268415523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.4268415523
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.39314402
Short name T694
Test name
Test status
Simulation time 85606934 ps
CPU time 0.82 seconds
Started Jan 24 07:42:09 PM PST 24
Finished Jan 24 07:42:15 PM PST 24
Peak memory 215964 kb
Host smart-79adcd78-b185-4414-a8f7-014553a97b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39314402 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.39314402
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2935356681
Short name T938
Test name
Test status
Simulation time 74853847 ps
CPU time 1.17 seconds
Started Jan 24 07:42:10 PM PST 24
Finished Jan 24 07:42:16 PM PST 24
Peak memory 215120 kb
Host smart-1cc0eea2-2960-45db-94be-2d3afbe31ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935356681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2935356681
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.2042023091
Short name T786
Test name
Test status
Simulation time 24291548 ps
CPU time 1.06 seconds
Started Jan 24 07:42:14 PM PST 24
Finished Jan 24 07:42:18 PM PST 24
Peak memory 222156 kb
Host smart-c24a13b1-edbf-48be-ac11-525fde426aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042023091 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.2042023091
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2472299323
Short name T504
Test name
Test status
Simulation time 288573653 ps
CPU time 1.26 seconds
Started Jan 24 07:42:13 PM PST 24
Finished Jan 24 07:42:17 PM PST 24
Peak memory 217204 kb
Host smart-69625978-458f-406e-aa1a-0e7021f74345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472299323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2472299323
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.1361987316
Short name T725
Test name
Test status
Simulation time 34578528 ps
CPU time 0.86 seconds
Started Jan 24 07:42:26 PM PST 24
Finished Jan 24 07:42:28 PM PST 24
Peak memory 216080 kb
Host smart-280292d7-cd2e-4605-ad12-2f8b2ad0c1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361987316 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1361987316
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3265227338
Short name T945
Test name
Test status
Simulation time 14557698 ps
CPU time 0.93 seconds
Started Jan 24 07:42:13 PM PST 24
Finished Jan 24 07:42:16 PM PST 24
Peak memory 214792 kb
Host smart-1c4dbe43-dfc3-48c6-aae3-d2f7c5a35c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265227338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3265227338
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.3700184149
Short name T7
Test name
Test status
Simulation time 46103618 ps
CPU time 1.24 seconds
Started Jan 24 07:42:20 PM PST 24
Finished Jan 24 07:42:22 PM PST 24
Peak memory 222240 kb
Host smart-57d041ff-0da3-4906-b3b7-01380d8956fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700184149 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3700184149
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.544214164
Short name T818
Test name
Test status
Simulation time 54329404 ps
CPU time 1.11 seconds
Started Jan 24 07:49:14 PM PST 24
Finished Jan 24 07:49:17 PM PST 24
Peak memory 215980 kb
Host smart-05b507fd-d5b7-4e86-b1fc-750212bf1c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544214164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.544214164
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1369542566
Short name T744
Test name
Test status
Simulation time 18346727 ps
CPU time 1.11 seconds
Started Jan 24 09:41:10 PM PST 24
Finished Jan 24 09:41:13 PM PST 24
Peak memory 221696 kb
Host smart-9d137821-62e0-435f-9628-07767efcad8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369542566 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1369542566
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.193796635
Short name T895
Test name
Test status
Simulation time 52983367 ps
CPU time 1.07 seconds
Started Jan 24 07:42:18 PM PST 24
Finished Jan 24 07:42:20 PM PST 24
Peak memory 214964 kb
Host smart-78a558bf-4329-46c5-86b6-1cdfbc729596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193796635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.193796635
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.3332176342
Short name T615
Test name
Test status
Simulation time 44786896 ps
CPU time 1.08 seconds
Started Jan 24 07:42:26 PM PST 24
Finished Jan 24 07:42:28 PM PST 24
Peak memory 222088 kb
Host smart-eb6827f5-bc37-490b-9cd8-6a969f552a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332176342 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3332176342
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.622017061
Short name T914
Test name
Test status
Simulation time 18417287 ps
CPU time 1.08 seconds
Started Jan 24 07:42:29 PM PST 24
Finished Jan 24 07:42:31 PM PST 24
Peak memory 214944 kb
Host smart-a4b8332e-58f4-4cdb-9b34-bbba00bd414f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622017061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.622017061
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.767742438
Short name T397
Test name
Test status
Simulation time 26390434 ps
CPU time 0.97 seconds
Started Jan 24 07:36:32 PM PST 24
Finished Jan 24 07:36:35 PM PST 24
Peak memory 206304 kb
Host smart-5a7a9cd1-0dbb-4363-9ac6-515a2c997b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767742438 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.767742438
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.407761443
Short name T616
Test name
Test status
Simulation time 79840389 ps
CPU time 0.8 seconds
Started Jan 24 07:36:31 PM PST 24
Finished Jan 24 07:36:33 PM PST 24
Peak memory 204896 kb
Host smart-56cb4696-bc3f-471b-9d3a-65ec29d0cd1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407761443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.407761443
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.3044736862
Short name T855
Test name
Test status
Simulation time 36529130 ps
CPU time 0.86 seconds
Started Jan 24 07:36:31 PM PST 24
Finished Jan 24 07:36:33 PM PST 24
Peak memory 214812 kb
Host smart-1e7b1964-dc0d-44a4-8ac2-4dbf39eda876
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044736862 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3044736862
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.76844084
Short name T764
Test name
Test status
Simulation time 93550963 ps
CPU time 1.1 seconds
Started Jan 24 07:36:30 PM PST 24
Finished Jan 24 07:36:33 PM PST 24
Peak memory 215924 kb
Host smart-75527286-6d05-4dc6-8753-71f3fbd73982
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76844084 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disa
ble_auto_req_mode.76844084
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3981279707
Short name T912
Test name
Test status
Simulation time 20575368 ps
CPU time 0.92 seconds
Started Jan 24 09:15:47 PM PST 24
Finished Jan 24 09:15:49 PM PST 24
Peak memory 216132 kb
Host smart-ff03de5e-f214-4d89-ad37-5ded1d63876e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981279707 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3981279707
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.4260188105
Short name T660
Test name
Test status
Simulation time 21437885 ps
CPU time 1.17 seconds
Started Jan 24 07:36:31 PM PST 24
Finished Jan 24 07:36:34 PM PST 24
Peak memory 215060 kb
Host smart-27705725-a89b-4f29-bf05-81c01c5f2efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260188105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.4260188105
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3474696903
Short name T868
Test name
Test status
Simulation time 20952003 ps
CPU time 1.06 seconds
Started Jan 24 07:36:32 PM PST 24
Finished Jan 24 07:36:36 PM PST 24
Peak memory 214836 kb
Host smart-c04523d7-1361-4697-ac3d-533197954cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474696903 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3474696903
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_smoke.649966247
Short name T734
Test name
Test status
Simulation time 26922146 ps
CPU time 0.93 seconds
Started Jan 24 07:36:28 PM PST 24
Finished Jan 24 07:36:31 PM PST 24
Peak memory 214616 kb
Host smart-a909aacb-ef22-4786-b4b7-204d351c74c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649966247 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.649966247
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.568003658
Short name T752
Test name
Test status
Simulation time 63350861 ps
CPU time 1.82 seconds
Started Jan 24 07:36:33 PM PST 24
Finished Jan 24 07:36:36 PM PST 24
Peak memory 214752 kb
Host smart-b06ddd8e-f308-4393-8e48-c45aeefa37ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568003658 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.568003658
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/70.edn_err.3544620233
Short name T597
Test name
Test status
Simulation time 18188507 ps
CPU time 1.04 seconds
Started Jan 24 07:42:21 PM PST 24
Finished Jan 24 07:42:23 PM PST 24
Peak memory 216460 kb
Host smart-ec125f4f-89e6-4913-871c-ae75db5acf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544620233 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3544620233
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3378285142
Short name T277
Test name
Test status
Simulation time 18593623 ps
CPU time 1.4 seconds
Started Jan 24 07:42:29 PM PST 24
Finished Jan 24 07:42:31 PM PST 24
Peak memory 215080 kb
Host smart-398d91de-b149-42da-ae1d-fa7ce535d083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378285142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3378285142
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.2457648370
Short name T76
Test name
Test status
Simulation time 62425555 ps
CPU time 0.86 seconds
Started Jan 24 07:42:25 PM PST 24
Finished Jan 24 07:42:27 PM PST 24
Peak memory 216280 kb
Host smart-39c4c32a-1bf3-45f4-89ab-264e311a2929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457648370 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2457648370
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2023220302
Short name T850
Test name
Test status
Simulation time 26333086 ps
CPU time 1.12 seconds
Started Jan 24 07:42:26 PM PST 24
Finished Jan 24 07:42:28 PM PST 24
Peak memory 214904 kb
Host smart-1f672db9-d35c-4d12-b6a3-acbaebd3c643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023220302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2023220302
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.1324640586
Short name T677
Test name
Test status
Simulation time 25048850 ps
CPU time 1.27 seconds
Started Jan 24 07:42:26 PM PST 24
Finished Jan 24 07:42:28 PM PST 24
Peak memory 222100 kb
Host smart-2626501e-db7d-4b28-aeca-41aa792949a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324640586 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1324640586
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1239444004
Short name T424
Test name
Test status
Simulation time 20491658 ps
CPU time 1.12 seconds
Started Jan 24 07:42:22 PM PST 24
Finished Jan 24 07:42:24 PM PST 24
Peak memory 216320 kb
Host smart-2bf60890-1e13-413b-ac9a-86c9a8d8c679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239444004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1239444004
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.2101545422
Short name T387
Test name
Test status
Simulation time 38649128 ps
CPU time 1.09 seconds
Started Jan 24 07:42:21 PM PST 24
Finished Jan 24 07:42:24 PM PST 24
Peak memory 216208 kb
Host smart-52dcbba7-d68a-4467-837e-5e3c12de3754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101545422 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2101545422
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1484711495
Short name T223
Test name
Test status
Simulation time 103635359 ps
CPU time 2.39 seconds
Started Jan 24 07:42:28 PM PST 24
Finished Jan 24 07:42:32 PM PST 24
Peak memory 215040 kb
Host smart-32e59660-cc54-4fbe-8719-ccaf5137856f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484711495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1484711495
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.915066830
Short name T98
Test name
Test status
Simulation time 56826968 ps
CPU time 1.03 seconds
Started Jan 24 07:42:31 PM PST 24
Finished Jan 24 07:42:34 PM PST 24
Peak memory 216620 kb
Host smart-b5c7f585-5b41-4bbe-a1a9-fd808ad4cee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915066830 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.915066830
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.4281480941
Short name T44
Test name
Test status
Simulation time 31938312 ps
CPU time 1.17 seconds
Started Jan 24 07:42:28 PM PST 24
Finished Jan 24 07:42:31 PM PST 24
Peak memory 214804 kb
Host smart-e4018eea-c339-4a26-bc2a-72495c16f247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281480941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.4281480941
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.3351310378
Short name T755
Test name
Test status
Simulation time 19810952 ps
CPU time 1.14 seconds
Started Jan 24 07:42:33 PM PST 24
Finished Jan 24 07:42:36 PM PST 24
Peak memory 222160 kb
Host smart-f720a7d2-69c4-4935-993f-7a52cea30a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351310378 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3351310378
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1038414400
Short name T907
Test name
Test status
Simulation time 24845241 ps
CPU time 1.14 seconds
Started Jan 24 07:42:27 PM PST 24
Finished Jan 24 07:42:29 PM PST 24
Peak memory 214904 kb
Host smart-23320a79-f638-4755-9166-f21c3a91b083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038414400 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1038414400
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.243063340
Short name T238
Test name
Test status
Simulation time 45487346 ps
CPU time 0.91 seconds
Started Jan 24 07:42:36 PM PST 24
Finished Jan 24 07:42:39 PM PST 24
Peak memory 216676 kb
Host smart-ee8c5b5f-fc51-4226-81a0-aa1baeb45ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243063340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.243063340
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1198292181
Short name T804
Test name
Test status
Simulation time 16093312 ps
CPU time 1.04 seconds
Started Jan 24 07:42:31 PM PST 24
Finished Jan 24 07:42:34 PM PST 24
Peak memory 214848 kb
Host smart-67aa7914-29a6-4564-9ce5-e998a5a503a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198292181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1198292181
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.3105440466
Short name T75
Test name
Test status
Simulation time 33840889 ps
CPU time 0.91 seconds
Started Jan 24 07:42:40 PM PST 24
Finished Jan 24 07:42:42 PM PST 24
Peak memory 215924 kb
Host smart-fa971a57-e1fb-4798-92ad-0ec010308dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105440466 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3105440466
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1376853591
Short name T521
Test name
Test status
Simulation time 21517735 ps
CPU time 1.11 seconds
Started Jan 24 07:42:41 PM PST 24
Finished Jan 24 07:42:43 PM PST 24
Peak memory 216040 kb
Host smart-87aa68c6-9eb0-4fd1-933d-a3ca2bca5d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376853591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1376853591
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.3490562505
Short name T472
Test name
Test status
Simulation time 23625842 ps
CPU time 0.95 seconds
Started Jan 24 07:42:39 PM PST 24
Finished Jan 24 07:42:40 PM PST 24
Peak memory 216500 kb
Host smart-653f6a60-5ffa-4cd8-a2c5-af86775e869c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490562505 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3490562505
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2814763558
Short name T517
Test name
Test status
Simulation time 66867773 ps
CPU time 1.08 seconds
Started Jan 24 07:42:41 PM PST 24
Finished Jan 24 07:42:43 PM PST 24
Peak memory 216176 kb
Host smart-75036ba0-7cb8-4533-9d4e-ced584c44364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814763558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2814763558
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.897712732
Short name T57
Test name
Test status
Simulation time 32525356 ps
CPU time 1.17 seconds
Started Jan 24 07:42:36 PM PST 24
Finished Jan 24 07:42:39 PM PST 24
Peak memory 222156 kb
Host smart-0bcc5f34-fe41-43f4-b59c-3952152f108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897712732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.897712732
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3627464587
Short name T232
Test name
Test status
Simulation time 75963924 ps
CPU time 1.15 seconds
Started Jan 24 10:14:35 PM PST 24
Finished Jan 24 10:14:37 PM PST 24
Peak memory 215160 kb
Host smart-f84cff5d-d59f-4cfd-a80b-9ac3fb9e2289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627464587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3627464587
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3660009388
Short name T421
Test name
Test status
Simulation time 176030770 ps
CPU time 0.89 seconds
Started Jan 24 07:36:31 PM PST 24
Finished Jan 24 07:36:34 PM PST 24
Peak memory 206312 kb
Host smart-2f16532e-04dc-4d8e-ac23-f85b7085a28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660009388 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3660009388
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.969036347
Short name T529
Test name
Test status
Simulation time 43957939 ps
CPU time 0.84 seconds
Started Jan 24 07:36:38 PM PST 24
Finished Jan 24 07:36:40 PM PST 24
Peak memory 205096 kb
Host smart-9d889970-b3d0-43ed-b3aa-c902e1bc0bf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969036347 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.969036347
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3372247817
Short name T130
Test name
Test status
Simulation time 33530932 ps
CPU time 0.81 seconds
Started Jan 24 08:02:14 PM PST 24
Finished Jan 24 08:02:17 PM PST 24
Peak memory 214832 kb
Host smart-e722bd22-f681-451c-93a3-ca55afd11f25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372247817 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3372247817
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1064123035
Short name T513
Test name
Test status
Simulation time 94717934 ps
CPU time 0.93 seconds
Started Jan 24 07:36:37 PM PST 24
Finished Jan 24 07:36:39 PM PST 24
Peak memory 214980 kb
Host smart-03a48253-1ab7-410f-b3de-e63551e17be0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064123035 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1064123035
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_genbits.966188148
Short name T380
Test name
Test status
Simulation time 106129963 ps
CPU time 0.96 seconds
Started Jan 24 07:36:32 PM PST 24
Finished Jan 24 07:36:35 PM PST 24
Peak memory 214848 kb
Host smart-f1d2f5c5-f3c2-4416-9e40-a077bc25463d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966188148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.966188148
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.726575004
Short name T718
Test name
Test status
Simulation time 34853317 ps
CPU time 0.94 seconds
Started Jan 24 08:36:43 PM PST 24
Finished Jan 24 08:36:45 PM PST 24
Peak memory 222008 kb
Host smart-e6dcb297-96d7-43aa-bf7d-b92c75344fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726575004 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.726575004
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.2784025462
Short name T257
Test name
Test status
Simulation time 13367847 ps
CPU time 0.94 seconds
Started Jan 24 09:24:05 PM PST 24
Finished Jan 24 09:24:07 PM PST 24
Peak memory 206408 kb
Host smart-91ecce80-59ab-4340-9e9d-58b545c7585c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784025462 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2784025462
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3371772319
Short name T808
Test name
Test status
Simulation time 17109210 ps
CPU time 0.89 seconds
Started Jan 24 07:36:28 PM PST 24
Finished Jan 24 07:36:31 PM PST 24
Peak memory 214612 kb
Host smart-3844536c-d0f2-4f56-abc2-10dfe9c30d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371772319 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3371772319
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.418815590
Short name T720
Test name
Test status
Simulation time 459225015 ps
CPU time 3.3 seconds
Started Jan 24 07:36:33 PM PST 24
Finished Jan 24 07:36:38 PM PST 24
Peak memory 214548 kb
Host smart-e15faeef-923c-4b09-8c37-b3a5f27e42fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418815590 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.418815590
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3073131889
Short name T596
Test name
Test status
Simulation time 75423150147 ps
CPU time 450.13 seconds
Started Jan 24 07:36:30 PM PST 24
Finished Jan 24 07:44:02 PM PST 24
Peak memory 222972 kb
Host smart-bc4f9005-3831-4c39-a6d4-48d51f1a68ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073131889 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3073131889
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_genbits.1222073328
Short name T227
Test name
Test status
Simulation time 20762044 ps
CPU time 1.1 seconds
Started Jan 24 07:42:37 PM PST 24
Finished Jan 24 07:42:39 PM PST 24
Peak memory 214760 kb
Host smart-065db997-a1bd-48a8-899f-20110855a7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222073328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1222073328
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.731610696
Short name T121
Test name
Test status
Simulation time 21007851 ps
CPU time 0.9 seconds
Started Jan 24 07:42:41 PM PST 24
Finished Jan 24 07:42:43 PM PST 24
Peak memory 216044 kb
Host smart-659be050-9545-4a6c-8365-5c36c4f29a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731610696 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.731610696
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1226962414
Short name T431
Test name
Test status
Simulation time 27417652 ps
CPU time 1.03 seconds
Started Jan 24 07:42:41 PM PST 24
Finished Jan 24 07:42:43 PM PST 24
Peak memory 214864 kb
Host smart-e7ee19a2-0197-4f56-978f-224825874e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226962414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1226962414
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.2186291151
Short name T617
Test name
Test status
Simulation time 18185277 ps
CPU time 1.03 seconds
Started Jan 24 08:20:51 PM PST 24
Finished Jan 24 08:20:53 PM PST 24
Peak memory 215904 kb
Host smart-397a3f38-96ab-4758-9c1b-fc88dcd8788f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186291151 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2186291151
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.968146341
Short name T613
Test name
Test status
Simulation time 42653584 ps
CPU time 2.01 seconds
Started Jan 24 07:42:46 PM PST 24
Finished Jan 24 07:42:49 PM PST 24
Peak memory 215060 kb
Host smart-f2f77556-e487-4f3e-a737-270b07c3fb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968146341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.968146341
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.2350077677
Short name T565
Test name
Test status
Simulation time 77395263 ps
CPU time 1.11 seconds
Started Jan 24 08:00:27 PM PST 24
Finished Jan 24 08:00:30 PM PST 24
Peak memory 217200 kb
Host smart-afe29dc3-44c6-4d7c-9830-ae2d23375e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350077677 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2350077677
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.4062299700
Short name T611
Test name
Test status
Simulation time 38467114 ps
CPU time 1.35 seconds
Started Jan 24 07:42:47 PM PST 24
Finished Jan 24 07:42:49 PM PST 24
Peak memory 214640 kb
Host smart-cb7c8df8-5d95-4f9e-8d0c-bb3307179a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062299700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.4062299700
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.3689882186
Short name T692
Test name
Test status
Simulation time 69029033 ps
CPU time 0.92 seconds
Started Jan 24 07:42:43 PM PST 24
Finished Jan 24 07:42:45 PM PST 24
Peak memory 221592 kb
Host smart-942720c8-88c7-4177-8b6f-8b6e09290fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689882186 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3689882186
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1492960815
Short name T761
Test name
Test status
Simulation time 38875494 ps
CPU time 1.06 seconds
Started Jan 24 07:42:46 PM PST 24
Finished Jan 24 07:42:48 PM PST 24
Peak memory 214792 kb
Host smart-e7fbb164-4ddd-4f56-b82b-171d55719d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492960815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1492960815
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.3440066722
Short name T16
Test name
Test status
Simulation time 28632440 ps
CPU time 1.31 seconds
Started Jan 24 07:42:52 PM PST 24
Finished Jan 24 07:42:54 PM PST 24
Peak memory 222116 kb
Host smart-2be89937-f9c0-4f73-875f-40e62425c5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440066722 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3440066722
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.709318715
Short name T834
Test name
Test status
Simulation time 45132011 ps
CPU time 0.95 seconds
Started Jan 24 08:03:08 PM PST 24
Finished Jan 24 08:03:18 PM PST 24
Peak memory 214852 kb
Host smart-6024d8b6-a5c0-42bb-962d-e62605f398ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709318715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.709318715
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.3697914962
Short name T9
Test name
Test status
Simulation time 55631357 ps
CPU time 0.97 seconds
Started Jan 24 07:42:55 PM PST 24
Finished Jan 24 07:42:56 PM PST 24
Peak memory 216600 kb
Host smart-bea79e00-75b3-4e12-b467-8f2d7119ffc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697914962 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3697914962
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.481365219
Short name T765
Test name
Test status
Simulation time 42084099 ps
CPU time 1.15 seconds
Started Jan 24 07:43:03 PM PST 24
Finished Jan 24 07:43:06 PM PST 24
Peak memory 215164 kb
Host smart-b487d183-c0a0-4ef4-bbcd-65916b8d9abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481365219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.481365219
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.114247223
Short name T484
Test name
Test status
Simulation time 19200932 ps
CPU time 0.99 seconds
Started Jan 24 07:42:54 PM PST 24
Finished Jan 24 07:42:55 PM PST 24
Peak memory 216276 kb
Host smart-4035282c-16fd-4028-86fe-94787cb5be1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114247223 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.114247223
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.1819120397
Short name T568
Test name
Test status
Simulation time 62716245 ps
CPU time 1.01 seconds
Started Jan 24 07:42:53 PM PST 24
Finished Jan 24 07:42:55 PM PST 24
Peak memory 215984 kb
Host smart-310e3a5b-f9a6-4b5f-847c-0e093cfec105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819120397 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1819120397
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.2292432847
Short name T476
Test name
Test status
Simulation time 41018478 ps
CPU time 1.02 seconds
Started Jan 24 07:42:57 PM PST 24
Finished Jan 24 07:42:59 PM PST 24
Peak memory 222056 kb
Host smart-ea4f1d53-a6ce-4c9c-aa1a-0fc7498f4261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292432847 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2292432847
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3394321420
Short name T661
Test name
Test status
Simulation time 21513740 ps
CPU time 1.12 seconds
Started Jan 24 07:42:57 PM PST 24
Finished Jan 24 07:42:58 PM PST 24
Peak memory 216292 kb
Host smart-f3bcafbf-f1e3-47b0-ae67-ed82712eb59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394321420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3394321420
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_genbits.3724012078
Short name T47
Test name
Test status
Simulation time 59259930 ps
CPU time 1.13 seconds
Started Jan 24 07:42:53 PM PST 24
Finished Jan 24 07:42:55 PM PST 24
Peak memory 216096 kb
Host smart-8b8cabd3-05c6-4e9e-ab00-543a0c609a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724012078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3724012078
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3905088990
Short name T851
Test name
Test status
Simulation time 69196354 ps
CPU time 0.99 seconds
Started Jan 24 07:36:53 PM PST 24
Finished Jan 24 07:36:55 PM PST 24
Peak memory 206372 kb
Host smart-2f0c2810-d095-4464-aa64-f3f25e01f166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905088990 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3905088990
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2974193861
Short name T396
Test name
Test status
Simulation time 22905797 ps
CPU time 0.81 seconds
Started Jan 24 07:36:50 PM PST 24
Finished Jan 24 07:36:52 PM PST 24
Peak memory 204756 kb
Host smart-70f1fad7-30fb-42ab-ab05-c19016a9900d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974193861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2974193861
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1466491128
Short name T135
Test name
Test status
Simulation time 10344103 ps
CPU time 0.83 seconds
Started Jan 24 07:36:46 PM PST 24
Finished Jan 24 07:36:47 PM PST 24
Peak memory 214840 kb
Host smart-78a94d2a-9987-4906-833e-36124a2330e4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466491128 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1466491128
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1272764209
Short name T807
Test name
Test status
Simulation time 44438979 ps
CPU time 1.03 seconds
Started Jan 24 07:45:42 PM PST 24
Finished Jan 24 07:45:44 PM PST 24
Peak memory 214956 kb
Host smart-b1843a79-3feb-4b45-a38d-e4f5a8b35665
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272764209 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1272764209
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.722790958
Short name T457
Test name
Test status
Simulation time 27248327 ps
CPU time 0.82 seconds
Started Jan 24 08:12:04 PM PST 24
Finished Jan 24 08:12:06 PM PST 24
Peak memory 215672 kb
Host smart-80fbf594-f2eb-4d23-a954-17fdead05ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722790958 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.722790958
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_intr.1894020226
Short name T446
Test name
Test status
Simulation time 27187974 ps
CPU time 0.92 seconds
Started Jan 24 07:52:17 PM PST 24
Finished Jan 24 07:52:18 PM PST 24
Peak memory 214924 kb
Host smart-a488c210-c999-47b1-89c1-31eeb33da43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894020226 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1894020226
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_stress_all.3525791675
Short name T646
Test name
Test status
Simulation time 2840605051 ps
CPU time 5.67 seconds
Started Jan 24 07:36:47 PM PST 24
Finished Jan 24 07:36:54 PM PST 24
Peak memory 214984 kb
Host smart-bdc703a7-5f7f-4fdf-be18-854aa0dcc1ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525791675 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3525791675
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3307508515
Short name T441
Test name
Test status
Simulation time 319201421629 ps
CPU time 1142.29 seconds
Started Jan 24 07:36:52 PM PST 24
Finished Jan 24 07:55:55 PM PST 24
Peak memory 220264 kb
Host smart-4f69fb38-c2ff-4120-973a-3f4e00e2800b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307508515 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3307508515
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.1859659501
Short name T847
Test name
Test status
Simulation time 20004532 ps
CPU time 1.15 seconds
Started Jan 24 07:43:03 PM PST 24
Finished Jan 24 07:43:06 PM PST 24
Peak memory 221980 kb
Host smart-1ae1e4c3-843b-43c6-a9e6-b753514b200c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859659501 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1859659501
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.4035534536
Short name T38
Test name
Test status
Simulation time 69394860 ps
CPU time 1.04 seconds
Started Jan 24 07:43:02 PM PST 24
Finished Jan 24 07:43:06 PM PST 24
Peak memory 214712 kb
Host smart-40678e43-da2f-4f8f-975d-29089740e5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035534536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.4035534536
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_genbits.3221789808
Short name T858
Test name
Test status
Simulation time 83776531 ps
CPU time 1.3 seconds
Started Jan 24 07:42:59 PM PST 24
Finished Jan 24 07:43:02 PM PST 24
Peak memory 215112 kb
Host smart-58f22903-c2ee-4206-a0d0-f847d88d5be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221789808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3221789808
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.1126835291
Short name T624
Test name
Test status
Simulation time 56721322 ps
CPU time 1.13 seconds
Started Jan 24 11:57:43 PM PST 24
Finished Jan 24 11:57:45 PM PST 24
Peak memory 222132 kb
Host smart-fc549103-46e4-43c3-a51c-944c1de6abc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126835291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.1126835291
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1659032419
Short name T12
Test name
Test status
Simulation time 23831036 ps
CPU time 1.21 seconds
Started Jan 24 07:43:00 PM PST 24
Finished Jan 24 07:43:03 PM PST 24
Peak memory 217672 kb
Host smart-8de67a20-1f57-46bb-acae-75785ad7c55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659032419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1659032419
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.674217114
Short name T666
Test name
Test status
Simulation time 29212222 ps
CPU time 1.34 seconds
Started Jan 24 07:43:03 PM PST 24
Finished Jan 24 07:43:07 PM PST 24
Peak memory 222256 kb
Host smart-c671dda6-ca05-405a-9985-c4f2f6c107fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674217114 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.674217114
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2666242808
Short name T570
Test name
Test status
Simulation time 22094107 ps
CPU time 1.08 seconds
Started Jan 24 07:43:04 PM PST 24
Finished Jan 24 07:43:08 PM PST 24
Peak memory 214724 kb
Host smart-7b59b77a-2ad9-4d9f-b42d-e332539900c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666242808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2666242808
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.2975935534
Short name T378
Test name
Test status
Simulation time 20506171 ps
CPU time 0.89 seconds
Started Jan 24 07:43:02 PM PST 24
Finished Jan 24 07:43:06 PM PST 24
Peak memory 215996 kb
Host smart-d7675972-13d6-4dfc-a117-17179424495b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975935534 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2975935534
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.3231056662
Short name T262
Test name
Test status
Simulation time 27955277 ps
CPU time 1.12 seconds
Started Jan 24 07:43:05 PM PST 24
Finished Jan 24 07:43:09 PM PST 24
Peak memory 216280 kb
Host smart-525837f7-8aff-4ddb-9fbd-091d3d3481e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231056662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.3231056662
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.2197995291
Short name T848
Test name
Test status
Simulation time 29516942 ps
CPU time 0.84 seconds
Started Jan 24 07:43:05 PM PST 24
Finished Jan 24 07:43:09 PM PST 24
Peak memory 215924 kb
Host smart-245a6f08-5538-49eb-a63f-19a118152df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197995291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2197995291
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/97.edn_err.2915140614
Short name T58
Test name
Test status
Simulation time 101655942 ps
CPU time 1.03 seconds
Started Jan 24 07:43:05 PM PST 24
Finished Jan 24 07:43:08 PM PST 24
Peak memory 222176 kb
Host smart-24455a8a-b34e-4798-bacb-6218ed89871d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915140614 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2915140614
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.210334453
Short name T726
Test name
Test status
Simulation time 32122878 ps
CPU time 1.03 seconds
Started Jan 24 07:43:03 PM PST 24
Finished Jan 24 07:43:06 PM PST 24
Peak memory 214732 kb
Host smart-d04b4527-2843-4766-b326-acdefb19c3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210334453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.210334453
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.3229968773
Short name T948
Test name
Test status
Simulation time 42480095 ps
CPU time 0.83 seconds
Started Jan 24 07:43:07 PM PST 24
Finished Jan 24 07:43:09 PM PST 24
Peak memory 215828 kb
Host smart-5b1e973f-36bb-489f-8aa9-bf770afad5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229968773 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3229968773
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1878823580
Short name T279
Test name
Test status
Simulation time 43012981 ps
CPU time 1.86 seconds
Started Jan 24 07:43:02 PM PST 24
Finished Jan 24 07:43:06 PM PST 24
Peak memory 216104 kb
Host smart-de72c52c-2838-4500-8948-f72b87e09927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878823580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1878823580
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_genbits.2074057981
Short name T6
Test name
Test status
Simulation time 16306740 ps
CPU time 1.13 seconds
Started Jan 24 07:43:04 PM PST 24
Finished Jan 24 07:43:08 PM PST 24
Peak memory 214688 kb
Host smart-35478d32-2ea7-4b54-b300-f437729cf2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074057981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2074057981
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%