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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.65 98.70 91.81 96.79 89.24 97.62 96.60 98.78


Total test records in report: 968
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T772 /workspace/coverage/default/6.edn_alert.3026457942 Feb 04 04:19:40 PM PST 24 Feb 04 04:19:44 PM PST 24 19952053 ps
T773 /workspace/coverage/default/56.edn_genbits.906303954 Feb 04 04:22:39 PM PST 24 Feb 04 04:22:44 PM PST 24 15925725 ps
T774 /workspace/coverage/default/45.edn_alert.3448396655 Feb 04 04:22:26 PM PST 24 Feb 04 04:22:28 PM PST 24 20382441 ps
T775 /workspace/coverage/default/15.edn_smoke.656586377 Feb 04 04:20:06 PM PST 24 Feb 04 04:20:11 PM PST 24 22108950 ps
T776 /workspace/coverage/default/46.edn_alert_test.1013824728 Feb 04 04:22:23 PM PST 24 Feb 04 04:22:27 PM PST 24 54291623 ps
T171 /workspace/coverage/default/11.edn_disable.612295622 Feb 04 04:20:02 PM PST 24 Feb 04 04:20:04 PM PST 24 20734211 ps
T777 /workspace/coverage/default/79.edn_genbits.3551324114 Feb 04 04:22:58 PM PST 24 Feb 04 04:23:03 PM PST 24 20751178 ps
T161 /workspace/coverage/default/0.edn_disable.4264492123 Feb 04 04:18:44 PM PST 24 Feb 04 04:18:47 PM PST 24 27331823 ps
T778 /workspace/coverage/default/12.edn_stress_all.1969803573 Feb 04 04:20:03 PM PST 24 Feb 04 04:20:07 PM PST 24 88426740 ps
T779 /workspace/coverage/default/43.edn_smoke.2468694472 Feb 04 04:22:13 PM PST 24 Feb 04 04:22:16 PM PST 24 25516039 ps
T780 /workspace/coverage/default/30.edn_disable.4145195721 Feb 04 04:21:25 PM PST 24 Feb 04 04:21:29 PM PST 24 26008578 ps
T781 /workspace/coverage/default/25.edn_stress_all.3673569093 Feb 04 04:20:53 PM PST 24 Feb 04 04:21:00 PM PST 24 33972209 ps
T315 /workspace/coverage/default/96.edn_genbits.408489765 Feb 04 04:23:10 PM PST 24 Feb 04 04:23:14 PM PST 24 127666668 ps
T782 /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2762028446 Feb 04 04:21:16 PM PST 24 Feb 04 04:24:59 PM PST 24 22266336522 ps
T783 /workspace/coverage/default/112.edn_genbits.4247634718 Feb 04 04:23:19 PM PST 24 Feb 04 04:23:21 PM PST 24 56058429 ps
T784 /workspace/coverage/default/33.edn_alert.3313326650 Feb 04 04:21:29 PM PST 24 Feb 04 04:21:31 PM PST 24 55079355 ps
T785 /workspace/coverage/default/44.edn_disable.2887208361 Feb 04 04:22:22 PM PST 24 Feb 04 04:22:25 PM PST 24 23441739 ps
T786 /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1275894674 Feb 04 04:20:43 PM PST 24 Feb 04 04:30:37 PM PST 24 87865953287 ps
T787 /workspace/coverage/default/92.edn_err.3591570812 Feb 04 04:23:11 PM PST 24 Feb 04 04:23:14 PM PST 24 23284355 ps
T788 /workspace/coverage/default/3.edn_intr.1366508668 Feb 04 04:19:14 PM PST 24 Feb 04 04:19:17 PM PST 24 48221975 ps
T789 /workspace/coverage/default/4.edn_intr.5883600 Feb 04 04:19:09 PM PST 24 Feb 04 04:19:11 PM PST 24 18563933 ps
T790 /workspace/coverage/default/50.edn_genbits.3113764648 Feb 04 04:22:31 PM PST 24 Feb 04 04:22:34 PM PST 24 68710168 ps
T791 /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2042492419 Feb 04 04:19:09 PM PST 24 Feb 04 04:51:52 PM PST 24 84179098282 ps
T792 /workspace/coverage/default/22.edn_stress_all.35250342 Feb 04 04:20:49 PM PST 24 Feb 04 04:20:54 PM PST 24 118288593 ps
T793 /workspace/coverage/default/5.edn_regwen.536933685 Feb 04 04:19:20 PM PST 24 Feb 04 04:19:27 PM PST 24 15519263 ps
T794 /workspace/coverage/default/8.edn_smoke.1089741367 Feb 04 04:19:40 PM PST 24 Feb 04 04:19:44 PM PST 24 13417285 ps
T795 /workspace/coverage/default/47.edn_intr.1403999853 Feb 04 04:22:32 PM PST 24 Feb 04 04:22:35 PM PST 24 19286487 ps
T796 /workspace/coverage/default/12.edn_alert_test.3614043447 Feb 04 04:20:01 PM PST 24 Feb 04 04:20:04 PM PST 24 29783931 ps
T797 /workspace/coverage/default/45.edn_intr.468069558 Feb 04 04:22:26 PM PST 24 Feb 04 04:22:28 PM PST 24 21034747 ps
T798 /workspace/coverage/default/37.edn_smoke.1281163732 Feb 04 04:21:56 PM PST 24 Feb 04 04:22:00 PM PST 24 15130864 ps
T799 /workspace/coverage/default/284.edn_genbits.1024301639 Feb 04 04:24:15 PM PST 24 Feb 04 04:24:19 PM PST 24 17356063 ps
T800 /workspace/coverage/default/14.edn_alert_test.1224903324 Feb 04 04:20:06 PM PST 24 Feb 04 04:20:10 PM PST 24 40447014 ps
T801 /workspace/coverage/default/237.edn_genbits.3386300962 Feb 04 04:23:55 PM PST 24 Feb 04 04:23:57 PM PST 24 60292098 ps
T802 /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1844933171 Feb 04 04:20:56 PM PST 24 Feb 04 04:54:15 PM PST 24 88921444746 ps
T803 /workspace/coverage/default/233.edn_genbits.1812958165 Feb 04 04:24:02 PM PST 24 Feb 04 04:24:07 PM PST 24 285640613 ps
T804 /workspace/coverage/default/25.edn_disable_auto_req_mode.3977579472 Feb 04 04:20:59 PM PST 24 Feb 04 04:21:02 PM PST 24 18152901 ps
T805 /workspace/coverage/default/19.edn_stress_all.2513498686 Feb 04 04:20:28 PM PST 24 Feb 04 04:20:32 PM PST 24 98537846 ps
T806 /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2826382822 Feb 04 04:20:36 PM PST 24 Feb 04 04:33:56 PM PST 24 154543873041 ps
T807 /workspace/coverage/default/35.edn_alert.3851121313 Feb 04 04:21:37 PM PST 24 Feb 04 04:21:39 PM PST 24 209929104 ps
T808 /workspace/coverage/default/10.edn_intr.578982416 Feb 04 04:19:40 PM PST 24 Feb 04 04:19:45 PM PST 24 28853408 ps
T809 /workspace/coverage/default/6.edn_smoke.548626944 Feb 04 04:19:23 PM PST 24 Feb 04 04:19:27 PM PST 24 13479985 ps
T810 /workspace/coverage/default/201.edn_genbits.2537670738 Feb 04 04:23:46 PM PST 24 Feb 04 04:23:52 PM PST 24 404070011 ps
T811 /workspace/coverage/default/235.edn_genbits.2133254605 Feb 04 04:23:59 PM PST 24 Feb 04 04:24:01 PM PST 24 15690335 ps
T812 /workspace/coverage/default/44.edn_stress_all.3353069194 Feb 04 04:22:26 PM PST 24 Feb 04 04:22:32 PM PST 24 353627705 ps
T813 /workspace/coverage/default/35.edn_genbits.1576947938 Feb 04 04:21:38 PM PST 24 Feb 04 04:21:40 PM PST 24 44023987 ps
T814 /workspace/coverage/default/31.edn_genbits.3169857324 Feb 04 04:21:25 PM PST 24 Feb 04 04:21:29 PM PST 24 55475449 ps
T815 /workspace/coverage/default/184.edn_genbits.1745526848 Feb 04 04:23:46 PM PST 24 Feb 04 04:23:49 PM PST 24 35483680 ps
T816 /workspace/coverage/default/272.edn_genbits.1186138628 Feb 04 04:24:10 PM PST 24 Feb 04 04:24:17 PM PST 24 33183760 ps
T817 /workspace/coverage/default/38.edn_smoke.104484371 Feb 04 04:21:47 PM PST 24 Feb 04 04:21:48 PM PST 24 42616959 ps
T818 /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1610929707 Feb 04 04:20:46 PM PST 24 Feb 04 04:34:40 PM PST 24 56990613264 ps
T819 /workspace/coverage/default/287.edn_genbits.536519484 Feb 04 04:24:11 PM PST 24 Feb 04 04:24:17 PM PST 24 41026692 ps
T86 /workspace/coverage/default/38.edn_intr.1898868505 Feb 04 04:21:52 PM PST 24 Feb 04 04:21:54 PM PST 24 20433799 ps
T820 /workspace/coverage/default/231.edn_genbits.143414900 Feb 04 04:23:57 PM PST 24 Feb 04 04:24:04 PM PST 24 667562553 ps
T821 /workspace/coverage/default/80.edn_genbits.2157224323 Feb 04 04:23:00 PM PST 24 Feb 04 04:23:03 PM PST 24 45074920 ps
T822 /workspace/coverage/default/28.edn_stress_all.2141406063 Feb 04 04:21:17 PM PST 24 Feb 04 04:21:23 PM PST 24 1871744348 ps
T823 /workspace/coverage/default/8.edn_alert.2327107244 Feb 04 04:19:38 PM PST 24 Feb 04 04:19:41 PM PST 24 32353746 ps
T63 /workspace/coverage/default/0.edn_sec_cm.308090364 Feb 04 04:18:41 PM PST 24 Feb 04 04:18:52 PM PST 24 439214548 ps
T824 /workspace/coverage/default/26.edn_genbits.1434795636 Feb 04 04:20:57 PM PST 24 Feb 04 04:21:00 PM PST 24 48137692 ps
T825 /workspace/coverage/default/27.edn_alert.1682328203 Feb 04 04:21:07 PM PST 24 Feb 04 04:21:09 PM PST 24 50955756 ps
T826 /workspace/coverage/default/41.edn_stress_all.726202462 Feb 04 04:22:01 PM PST 24 Feb 04 04:22:04 PM PST 24 229934957 ps
T827 /workspace/coverage/default/18.edn_err.3473918085 Feb 04 04:20:41 PM PST 24 Feb 04 04:20:43 PM PST 24 33149358 ps
T828 /workspace/coverage/default/265.edn_genbits.3223661912 Feb 04 04:24:15 PM PST 24 Feb 04 04:24:19 PM PST 24 209649780 ps
T82 /workspace/coverage/default/44.edn_intr.3447573254 Feb 04 04:22:22 PM PST 24 Feb 04 04:22:25 PM PST 24 22401067 ps
T829 /workspace/coverage/default/31.edn_err.2500585566 Feb 04 04:21:29 PM PST 24 Feb 04 04:21:31 PM PST 24 17864351 ps
T830 /workspace/coverage/default/48.edn_stress_all.4192154248 Feb 04 04:22:28 PM PST 24 Feb 04 04:22:32 PM PST 24 118586124 ps
T831 /workspace/coverage/default/25.edn_genbits.1397929551 Feb 04 04:20:54 PM PST 24 Feb 04 04:21:00 PM PST 24 127049715 ps
T832 /workspace/coverage/default/40.edn_err.1957736756 Feb 04 04:21:56 PM PST 24 Feb 04 04:22:00 PM PST 24 38746674 ps
T833 /workspace/coverage/default/1.edn_err.211736976 Feb 04 04:19:03 PM PST 24 Feb 04 04:19:09 PM PST 24 31651917 ps
T834 /workspace/coverage/default/27.edn_disable_auto_req_mode.3767682104 Feb 04 04:21:10 PM PST 24 Feb 04 04:21:12 PM PST 24 78435140 ps
T835 /workspace/coverage/default/40.edn_smoke.1983845597 Feb 04 04:21:57 PM PST 24 Feb 04 04:22:00 PM PST 24 22167782 ps
T836 /workspace/coverage/default/12.edn_stress_all_with_rand_reset.934359136 Feb 04 04:19:58 PM PST 24 Feb 04 04:38:18 PM PST 24 156908647188 ps
T163 /workspace/coverage/default/10.edn_err.1453931944 Feb 04 04:19:45 PM PST 24 Feb 04 04:19:52 PM PST 24 25601229 ps
T125 /workspace/coverage/default/21.edn_disable.2108311860 Feb 04 04:20:45 PM PST 24 Feb 04 04:20:47 PM PST 24 19203052 ps
T837 /workspace/coverage/default/10.edn_alert_test.2859115416 Feb 04 04:19:47 PM PST 24 Feb 04 04:19:53 PM PST 24 16530596 ps
T838 /workspace/coverage/default/20.edn_genbits.2772324901 Feb 04 04:20:46 PM PST 24 Feb 04 04:20:48 PM PST 24 28690800 ps
T839 /workspace/coverage/default/188.edn_genbits.3425005288 Feb 04 04:23:49 PM PST 24 Feb 04 04:23:51 PM PST 24 12782821 ps
T840 /workspace/coverage/default/92.edn_genbits.2988631517 Feb 04 04:23:14 PM PST 24 Feb 04 04:23:23 PM PST 24 1129047706 ps
T841 /workspace/coverage/default/277.edn_genbits.96256793 Feb 04 04:24:06 PM PST 24 Feb 04 04:24:09 PM PST 24 29628507 ps
T842 /workspace/coverage/default/19.edn_smoke.1379856100 Feb 04 04:20:31 PM PST 24 Feb 04 04:20:36 PM PST 24 85724177 ps
T843 /workspace/coverage/default/12.edn_err.884698154 Feb 04 04:20:04 PM PST 24 Feb 04 04:20:08 PM PST 24 34904286 ps
T844 /workspace/coverage/default/5.edn_alert_test.2735914023 Feb 04 04:19:19 PM PST 24 Feb 04 04:19:26 PM PST 24 37368420 ps
T99 /workspace/coverage/default/13.edn_intr.303579229 Feb 04 04:20:00 PM PST 24 Feb 04 04:20:02 PM PST 24 51123165 ps
T845 /workspace/coverage/default/44.edn_alert_test.1763652710 Feb 04 04:22:27 PM PST 24 Feb 04 04:22:29 PM PST 24 20065918 ps
T846 /workspace/coverage/default/248.edn_genbits.4142650159 Feb 04 04:24:08 PM PST 24 Feb 04 04:24:11 PM PST 24 25721205 ps
T847 /workspace/coverage/default/41.edn_alert_test.143868902 Feb 04 04:22:01 PM PST 24 Feb 04 04:22:03 PM PST 24 241357769 ps
T127 /workspace/coverage/default/8.edn_err.1041924734 Feb 04 04:19:45 PM PST 24 Feb 04 04:19:52 PM PST 24 52111407 ps
T848 /workspace/coverage/default/3.edn_alert.4081720412 Feb 04 04:19:13 PM PST 24 Feb 04 04:19:15 PM PST 24 31939544 ps
T849 /workspace/coverage/default/138.edn_genbits.61357445 Feb 04 04:23:27 PM PST 24 Feb 04 04:23:29 PM PST 24 19855631 ps
T850 /workspace/coverage/default/58.edn_err.889420695 Feb 04 04:22:43 PM PST 24 Feb 04 04:22:46 PM PST 24 165435739 ps
T152 /workspace/coverage/default/29.edn_disable.2127179925 Feb 04 04:21:12 PM PST 24 Feb 04 04:21:17 PM PST 24 12750789 ps
T851 /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2252447709 Feb 04 04:20:21 PM PST 24 Feb 04 04:46:15 PM PST 24 123793899587 ps
T852 /workspace/coverage/default/20.edn_err.739372184 Feb 04 04:20:44 PM PST 24 Feb 04 04:20:46 PM PST 24 23733443 ps
T853 /workspace/coverage/default/45.edn_stress_all_with_rand_reset.467558332 Feb 04 04:22:16 PM PST 24 Feb 04 04:31:06 PM PST 24 79064184350 ps
T854 /workspace/coverage/default/33.edn_disable_auto_req_mode.1115483594 Feb 04 04:21:35 PM PST 24 Feb 04 04:21:38 PM PST 24 26182812 ps
T855 /workspace/coverage/default/157.edn_genbits.2923438859 Feb 04 04:23:30 PM PST 24 Feb 04 04:23:38 PM PST 24 16658884 ps
T856 /workspace/coverage/default/52.edn_err.843684986 Feb 04 04:22:39 PM PST 24 Feb 04 04:22:44 PM PST 24 22904915 ps
T857 /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2819424727 Feb 04 04:21:18 PM PST 24 Feb 04 04:30:43 PM PST 24 44899434972 ps
T858 /workspace/coverage/default/78.edn_err.4044967471 Feb 04 04:22:56 PM PST 24 Feb 04 04:23:00 PM PST 24 64201521 ps
T859 /workspace/coverage/default/0.edn_stress_all.1671028297 Feb 04 04:18:45 PM PST 24 Feb 04 04:18:48 PM PST 24 62125416 ps
T860 /workspace/coverage/default/29.edn_err.3983863908 Feb 04 04:21:21 PM PST 24 Feb 04 04:21:28 PM PST 24 45893543 ps
T861 /workspace/coverage/default/23.edn_err.890861725 Feb 04 04:20:50 PM PST 24 Feb 04 04:20:54 PM PST 24 19216904 ps
T862 /workspace/coverage/default/49.edn_stress_all.2557313958 Feb 04 04:22:33 PM PST 24 Feb 04 04:22:38 PM PST 24 60740895 ps
T313 /workspace/coverage/default/242.edn_genbits.1537727459 Feb 04 04:23:57 PM PST 24 Feb 04 04:24:00 PM PST 24 23120319 ps
T863 /workspace/coverage/default/11.edn_err.3769606462 Feb 04 04:19:58 PM PST 24 Feb 04 04:20:00 PM PST 24 55705940 ps
T864 /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1321356446 Feb 04 04:22:32 PM PST 24 Feb 04 04:53:41 PM PST 24 89557203623 ps
T865 /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2670247192 Feb 04 04:20:01 PM PST 24 Feb 04 04:25:34 PM PST 24 28579358946 ps
T866 /workspace/coverage/default/58.edn_genbits.2354352108 Feb 04 04:22:39 PM PST 24 Feb 04 04:22:44 PM PST 24 252011872 ps
T867 /workspace/coverage/default/229.edn_genbits.1288576911 Feb 04 04:23:55 PM PST 24 Feb 04 04:23:57 PM PST 24 34081909 ps
T868 /workspace/coverage/default/0.edn_alert_test.3207589854 Feb 04 04:18:56 PM PST 24 Feb 04 04:18:58 PM PST 24 47914593 ps
T869 /workspace/coverage/default/30.edn_err.1575626479 Feb 04 04:21:19 PM PST 24 Feb 04 04:21:22 PM PST 24 18921674 ps
T870 /workspace/coverage/default/22.edn_smoke.3635860917 Feb 04 04:20:46 PM PST 24 Feb 04 04:20:49 PM PST 24 10793251 ps
T871 /workspace/coverage/default/103.edn_genbits.3248826986 Feb 04 04:23:11 PM PST 24 Feb 04 04:23:13 PM PST 24 50918015 ps
T872 /workspace/coverage/default/25.edn_err.1516874794 Feb 04 04:20:55 PM PST 24 Feb 04 04:21:00 PM PST 24 30133555 ps
T104 /workspace/coverage/default/14.edn_disable_auto_req_mode.2827959802 Feb 04 04:20:04 PM PST 24 Feb 04 04:20:07 PM PST 24 28240830 ps
T873 /workspace/coverage/default/83.edn_genbits.983178243 Feb 04 04:23:08 PM PST 24 Feb 04 04:23:11 PM PST 24 138131917 ps
T109 /workspace/coverage/default/28.edn_err.3510323544 Feb 04 04:21:14 PM PST 24 Feb 04 04:21:17 PM PST 24 43635751 ps
T874 /workspace/coverage/default/1.edn_disable.324579178 Feb 04 04:19:10 PM PST 24 Feb 04 04:19:12 PM PST 24 13176255 ps
T875 /workspace/coverage/default/279.edn_genbits.2911234697 Feb 04 04:24:14 PM PST 24 Feb 04 04:24:17 PM PST 24 28153033 ps
T876 /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3614969129 Feb 04 04:21:33 PM PST 24 Feb 04 04:36:55 PM PST 24 68271881191 ps
T110 /workspace/coverage/default/64.edn_err.1775904440 Feb 04 04:22:51 PM PST 24 Feb 04 04:22:53 PM PST 24 53353325 ps
T183 /workspace/coverage/default/38.edn_disable.2023984017 Feb 04 04:21:55 PM PST 24 Feb 04 04:22:00 PM PST 24 34554944 ps
T877 /workspace/coverage/default/78.edn_genbits.3207575700 Feb 04 04:22:57 PM PST 24 Feb 04 04:23:02 PM PST 24 106314072 ps
T878 /workspace/coverage/default/239.edn_genbits.3216590251 Feb 04 04:24:02 PM PST 24 Feb 04 04:24:04 PM PST 24 22165609 ps
T879 /workspace/coverage/default/27.edn_smoke.659978124 Feb 04 04:21:10 PM PST 24 Feb 04 04:21:12 PM PST 24 23279796 ps
T880 /workspace/coverage/default/298.edn_genbits.2185672371 Feb 04 04:24:15 PM PST 24 Feb 04 04:24:18 PM PST 24 27215003 ps
T881 /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2134822691 Feb 04 04:20:33 PM PST 24 Feb 04 04:42:13 PM PST 24 299715106442 ps
T882 /workspace/coverage/default/9.edn_stress_all.3905634767 Feb 04 04:19:41 PM PST 24 Feb 04 04:19:46 PM PST 24 96299372 ps
T883 /workspace/coverage/default/289.edn_genbits.2461094092 Feb 04 04:24:12 PM PST 24 Feb 04 04:24:17 PM PST 24 127164585 ps
T128 /workspace/coverage/default/97.edn_err.2715826284 Feb 04 04:23:13 PM PST 24 Feb 04 04:23:16 PM PST 24 58005507 ps
T884 /workspace/coverage/default/299.edn_genbits.651379771 Feb 04 04:24:17 PM PST 24 Feb 04 04:24:20 PM PST 24 17081453 ps
T885 /workspace/coverage/default/6.edn_disable_auto_req_mode.2240848890 Feb 04 04:19:42 PM PST 24 Feb 04 04:19:45 PM PST 24 19331254 ps
T886 /workspace/coverage/default/234.edn_genbits.2491231659 Feb 04 04:23:57 PM PST 24 Feb 04 04:23:59 PM PST 24 26755652 ps
T887 /workspace/coverage/default/25.edn_smoke.3246784271 Feb 04 04:20:56 PM PST 24 Feb 04 04:21:00 PM PST 24 45774583 ps
T888 /workspace/coverage/default/28.edn_genbits.4227833708 Feb 04 04:21:16 PM PST 24 Feb 04 04:21:20 PM PST 24 96829868 ps
T889 /workspace/coverage/default/43.edn_intr.352278850 Feb 04 04:22:16 PM PST 24 Feb 04 04:22:19 PM PST 24 38919978 ps
T890 /workspace/coverage/default/24.edn_alert.1038147197 Feb 04 04:20:58 PM PST 24 Feb 04 04:21:00 PM PST 24 180574557 ps
T891 /workspace/coverage/default/41.edn_alert.3736176425 Feb 04 04:22:05 PM PST 24 Feb 04 04:22:07 PM PST 24 56232693 ps
T892 /workspace/coverage/default/82.edn_err.4212788618 Feb 04 04:23:00 PM PST 24 Feb 04 04:23:03 PM PST 24 30257097 ps
T893 /workspace/coverage/default/7.edn_stress_all.4042682468 Feb 04 04:19:37 PM PST 24 Feb 04 04:19:41 PM PST 24 548197001 ps
T153 /workspace/coverage/default/9.edn_disable_auto_req_mode.3854964223 Feb 04 04:19:47 PM PST 24 Feb 04 04:19:53 PM PST 24 53866638 ps
T159 /workspace/coverage/default/48.edn_disable.3471311582 Feb 04 04:22:33 PM PST 24 Feb 04 04:22:37 PM PST 24 59313816 ps
T894 /workspace/coverage/default/183.edn_genbits.323858467 Feb 04 04:23:38 PM PST 24 Feb 04 04:23:42 PM PST 24 78626762 ps
T172 /workspace/coverage/default/9.edn_disable.422628322 Feb 04 04:19:49 PM PST 24 Feb 04 04:19:53 PM PST 24 21454877 ps
T895 /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1232007344 Feb 04 04:20:17 PM PST 24 Feb 04 04:24:27 PM PST 24 16474540173 ps
T896 /workspace/coverage/default/215.edn_genbits.254092977 Feb 04 04:23:47 PM PST 24 Feb 04 04:23:50 PM PST 24 37787059 ps
T897 /workspace/coverage/default/49.edn_disable.942789029 Feb 04 04:22:34 PM PST 24 Feb 04 04:22:37 PM PST 24 13083936 ps
T898 /workspace/coverage/default/2.edn_regwen.4283929939 Feb 04 04:19:06 PM PST 24 Feb 04 04:19:09 PM PST 24 15358192 ps
T899 /workspace/coverage/default/36.edn_smoke.1911038507 Feb 04 04:21:39 PM PST 24 Feb 04 04:21:41 PM PST 24 29957370 ps
T900 /workspace/coverage/default/33.edn_disable.854692034 Feb 04 04:21:36 PM PST 24 Feb 04 04:21:39 PM PST 24 27897554 ps
T901 /workspace/coverage/default/40.edn_intr.2099126278 Feb 04 04:21:55 PM PST 24 Feb 04 04:22:00 PM PST 24 55614698 ps
T902 /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2375932187 Feb 04 04:21:51 PM PST 24 Feb 04 04:25:48 PM PST 24 144697989624 ps
T903 /workspace/coverage/default/17.edn_smoke.4015352250 Feb 04 04:20:18 PM PST 24 Feb 04 04:20:21 PM PST 24 15536203 ps
T904 /workspace/coverage/default/3.edn_stress_all.125419558 Feb 04 04:19:11 PM PST 24 Feb 04 04:19:16 PM PST 24 167662672 ps
T905 /workspace/coverage/default/260.edn_genbits.1775284753 Feb 04 04:24:07 PM PST 24 Feb 04 04:24:10 PM PST 24 17026462 ps
T906 /workspace/coverage/default/147.edn_genbits.2273525629 Feb 04 04:23:27 PM PST 24 Feb 04 04:23:29 PM PST 24 18076928 ps
T907 /workspace/coverage/default/6.edn_stress_all.2999759059 Feb 04 04:19:20 PM PST 24 Feb 04 04:19:28 PM PST 24 35344862 ps
T908 /workspace/coverage/default/259.edn_genbits.88057886 Feb 04 04:24:07 PM PST 24 Feb 04 04:24:10 PM PST 24 55331868 ps
T909 /workspace/coverage/default/53.edn_genbits.3731804108 Feb 04 04:22:36 PM PST 24 Feb 04 04:22:38 PM PST 24 82511315 ps
T910 /workspace/coverage/default/21.edn_stress_all.1259330663 Feb 04 04:20:43 PM PST 24 Feb 04 04:20:46 PM PST 24 113026959 ps
T911 /workspace/coverage/default/44.edn_err.4153989270 Feb 04 04:22:26 PM PST 24 Feb 04 04:22:29 PM PST 24 122681795 ps
T912 /workspace/coverage/default/73.edn_genbits.4039470236 Feb 04 04:22:57 PM PST 24 Feb 04 04:23:02 PM PST 24 41703348 ps
T913 /workspace/coverage/default/104.edn_genbits.2894252156 Feb 04 04:23:19 PM PST 24 Feb 04 04:23:23 PM PST 24 130593852 ps
T914 /workspace/coverage/default/219.edn_genbits.1089350248 Feb 04 04:23:58 PM PST 24 Feb 04 04:24:00 PM PST 24 121625945 ps
T915 /workspace/coverage/default/26.edn_smoke.3557652849 Feb 04 04:20:58 PM PST 24 Feb 04 04:21:00 PM PST 24 45537426 ps
T916 /workspace/coverage/default/107.edn_genbits.838432101 Feb 04 04:23:16 PM PST 24 Feb 04 04:23:19 PM PST 24 321068644 ps
T917 /workspace/coverage/default/65.edn_genbits.2023334624 Feb 04 04:22:52 PM PST 24 Feb 04 04:22:54 PM PST 24 44209985 ps
T918 /workspace/coverage/default/35.edn_disable.1039115935 Feb 04 04:21:36 PM PST 24 Feb 04 04:21:38 PM PST 24 17148184 ps
T919 /workspace/coverage/default/31.edn_disable_auto_req_mode.2345822778 Feb 04 04:21:27 PM PST 24 Feb 04 04:21:29 PM PST 24 22366415 ps
T920 /workspace/coverage/default/33.edn_genbits.1986459503 Feb 04 04:21:30 PM PST 24 Feb 04 04:21:32 PM PST 24 146722124 ps
T921 /workspace/coverage/default/116.edn_genbits.832436697 Feb 04 04:23:19 PM PST 24 Feb 04 04:23:21 PM PST 24 71874090 ps
T922 /workspace/coverage/default/35.edn_intr.3470679745 Feb 04 04:21:38 PM PST 24 Feb 04 04:21:40 PM PST 24 26239566 ps
T923 /workspace/coverage/default/202.edn_genbits.54819764 Feb 04 04:23:47 PM PST 24 Feb 04 04:23:53 PM PST 24 278345309 ps
T924 /workspace/coverage/default/15.edn_stress_all.2757442284 Feb 04 04:20:05 PM PST 24 Feb 04 04:20:12 PM PST 24 94457102 ps
T925 /workspace/coverage/default/238.edn_genbits.3469875829 Feb 04 04:24:02 PM PST 24 Feb 04 04:24:04 PM PST 24 25339664 ps
T926 /workspace/coverage/default/130.edn_genbits.836962258 Feb 04 04:23:21 PM PST 24 Feb 04 04:23:23 PM PST 24 20587388 ps
T927 /workspace/coverage/default/162.edn_genbits.219510091 Feb 04 04:23:30 PM PST 24 Feb 04 04:23:37 PM PST 24 58940194 ps
T928 /workspace/coverage/default/154.edn_genbits.1516984824 Feb 04 04:23:29 PM PST 24 Feb 04 04:23:37 PM PST 24 154138803 ps
T929 /workspace/coverage/default/20.edn_disable_auto_req_mode.2398225957 Feb 04 04:20:36 PM PST 24 Feb 04 04:20:38 PM PST 24 58519637 ps
T930 /workspace/coverage/default/212.edn_genbits.3083622680 Feb 04 04:23:58 PM PST 24 Feb 04 04:24:00 PM PST 24 66483943 ps
T931 /workspace/coverage/default/5.edn_stress_all_with_rand_reset.3846724918 Feb 04 04:19:28 PM PST 24 Feb 04 04:29:51 PM PST 24 218823967143 ps
T932 /workspace/coverage/default/156.edn_genbits.170279222 Feb 04 04:23:29 PM PST 24 Feb 04 04:23:31 PM PST 24 17203772 ps
T933 /workspace/coverage/default/39.edn_err.2572354594 Feb 04 04:21:59 PM PST 24 Feb 04 04:22:02 PM PST 24 33030499 ps
T934 /workspace/coverage/default/27.edn_intr.1448386204 Feb 04 04:21:10 PM PST 24 Feb 04 04:21:13 PM PST 24 53431275 ps
T935 /workspace/coverage/default/126.edn_genbits.2160256235 Feb 04 04:23:27 PM PST 24 Feb 04 04:23:30 PM PST 24 24323657 ps
T936 /workspace/coverage/default/82.edn_genbits.528877026 Feb 04 04:23:00 PM PST 24 Feb 04 04:23:05 PM PST 24 24970877 ps
T937 /workspace/coverage/default/41.edn_genbits.1311160065 Feb 04 04:22:09 PM PST 24 Feb 04 04:22:11 PM PST 24 56152438 ps
T938 /workspace/coverage/default/54.edn_genbits.3219837770 Feb 04 04:22:39 PM PST 24 Feb 04 04:22:44 PM PST 24 147922837 ps
T939 /workspace/coverage/default/23.edn_intr.204382359 Feb 04 04:20:45 PM PST 24 Feb 04 04:20:47 PM PST 24 52923519 ps
T940 /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3583773538 Feb 04 04:21:12 PM PST 24 Feb 04 04:42:32 PM PST 24 53089601957 ps
T941 /workspace/coverage/default/36.edn_alert_test.1617919015 Feb 04 04:21:49 PM PST 24 Feb 04 04:21:51 PM PST 24 16917554 ps
T942 /workspace/coverage/default/296.edn_genbits.1013333823 Feb 04 04:24:15 PM PST 24 Feb 04 04:24:19 PM PST 24 61070434 ps
T943 /workspace/coverage/default/176.edn_genbits.2186834960 Feb 04 04:23:39 PM PST 24 Feb 04 04:23:43 PM PST 24 31092418 ps
T944 /workspace/coverage/default/282.edn_genbits.2022147961 Feb 04 04:24:22 PM PST 24 Feb 04 04:24:24 PM PST 24 39706390 ps
T945 /workspace/coverage/default/36.edn_intr.2843154795 Feb 04 04:22:09 PM PST 24 Feb 04 04:22:11 PM PST 24 23951260 ps
T946 /workspace/coverage/default/32.edn_alert.699188969 Feb 04 04:21:25 PM PST 24 Feb 04 04:21:29 PM PST 24 22528757 ps
T947 /workspace/coverage/default/17.edn_stress_all.291229095 Feb 04 04:20:20 PM PST 24 Feb 04 04:20:25 PM PST 24 224754932 ps
T948 /workspace/coverage/default/17.edn_alert_test.2332260537 Feb 04 04:20:30 PM PST 24 Feb 04 04:20:36 PM PST 24 30346418 ps
T949 /workspace/coverage/default/41.edn_smoke.2210236448 Feb 04 04:21:55 PM PST 24 Feb 04 04:22:00 PM PST 24 64289324 ps
T950 /workspace/coverage/default/46.edn_disable.401487718 Feb 04 04:22:22 PM PST 24 Feb 04 04:22:25 PM PST 24 27895261 ps
T951 /workspace/coverage/default/33.edn_alert_test.963786857 Feb 04 04:21:38 PM PST 24 Feb 04 04:21:40 PM PST 24 35661704 ps
T952 /workspace/coverage/default/38.edn_genbits.1538283713 Feb 04 04:21:57 PM PST 24 Feb 04 04:22:00 PM PST 24 31996523 ps
T953 /workspace/coverage/default/268.edn_genbits.2679343144 Feb 04 04:24:15 PM PST 24 Feb 04 04:24:19 PM PST 24 78953585 ps
T954 /workspace/coverage/default/47.edn_alert_test.16315472 Feb 04 04:22:27 PM PST 24 Feb 04 04:22:29 PM PST 24 34195178 ps
T955 /workspace/coverage/default/19.edn_alert.902132072 Feb 04 04:20:39 PM PST 24 Feb 04 04:20:41 PM PST 24 39027583 ps
T956 /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3822548938 Feb 04 04:21:48 PM PST 24 Feb 04 04:33:45 PM PST 24 99518772650 ps
T957 /workspace/coverage/default/217.edn_genbits.3574871119 Feb 04 04:23:58 PM PST 24 Feb 04 04:24:00 PM PST 24 32052903 ps
T958 /workspace/coverage/default/46.edn_alert.1641930482 Feb 04 04:22:17 PM PST 24 Feb 04 04:22:19 PM PST 24 73944072 ps
T959 /workspace/coverage/default/0.edn_alert.3109113350 Feb 04 04:18:40 PM PST 24 Feb 04 04:18:45 PM PST 24 30849449 ps
T960 /workspace/coverage/default/243.edn_genbits.806422860 Feb 04 04:23:59 PM PST 24 Feb 04 04:24:01 PM PST 24 17732066 ps
T961 /workspace/coverage/default/28.edn_intr.724097769 Feb 04 04:21:17 PM PST 24 Feb 04 04:21:21 PM PST 24 49560791 ps
T962 /workspace/coverage/default/221.edn_genbits.2624723117 Feb 04 04:23:55 PM PST 24 Feb 04 04:23:58 PM PST 24 45106892 ps
T963 /workspace/coverage/default/32.edn_alert_test.3486644824 Feb 04 04:21:30 PM PST 24 Feb 04 04:21:32 PM PST 24 39605551 ps
T964 /workspace/coverage/default/158.edn_genbits.1440885651 Feb 04 04:23:35 PM PST 24 Feb 04 04:23:39 PM PST 24 117829643 ps
T965 /workspace/coverage/default/11.edn_intr.299366670 Feb 04 04:20:01 PM PST 24 Feb 04 04:20:04 PM PST 24 19524824 ps
T310 /workspace/coverage/default/59.edn_genbits.1212844038 Feb 04 04:22:45 PM PST 24 Feb 04 04:22:47 PM PST 24 50308403 ps
T966 /workspace/coverage/default/26.edn_disable_auto_req_mode.1575130858 Feb 04 04:21:01 PM PST 24 Feb 04 04:21:03 PM PST 24 31459560 ps
T967 /workspace/coverage/default/211.edn_genbits.3711973837 Feb 04 04:23:47 PM PST 24 Feb 04 04:23:50 PM PST 24 135912498 ps
T968 /workspace/coverage/default/31.edn_alert.3606035382 Feb 04 04:21:26 PM PST 24 Feb 04 04:21:29 PM PST 24 19788408 ps

Test location /workspace/coverage/default/74.edn_genbits.381744470
Short name T1
Test name
Test status
Simulation time 191251748 ps
CPU time 1.11 seconds
Started Feb 04 04:23:03 PM PST 24
Finished Feb 04 04:23:10 PM PST 24
Peak memory 216720 kb
Host smart-c75bee36-79b4-466b-b156-9316d85c4100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381744470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.381744470
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.1188218914
Short name T11
Test name
Test status
Simulation time 44077076 ps
CPU time 1.2 seconds
Started Feb 04 04:23:32 PM PST 24
Finished Feb 04 04:23:38 PM PST 24
Peak memory 218044 kb
Host smart-deb42b4e-c598-4a0e-b2b7-6d12454e3e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188218914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1188218914
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.2412963493
Short name T25
Test name
Test status
Simulation time 402177495 ps
CPU time 2.48 seconds
Started Feb 04 12:46:47 PM PST 24
Finished Feb 04 12:46:52 PM PST 24
Peak memory 205712 kb
Host smart-4b25b7d8-60d8-4410-b89c-4b47bc56804d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412963493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.2412963493
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/default/85.edn_err.2509934813
Short name T6
Test name
Test status
Simulation time 34123235 ps
CPU time 1.11 seconds
Started Feb 04 04:23:02 PM PST 24
Finished Feb 04 04:23:10 PM PST 24
Peak memory 222588 kb
Host smart-4b49c20c-ad9d-43f2-9525-b286d37e31b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509934813 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2509934813
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3241775490
Short name T20
Test name
Test status
Simulation time 684416151 ps
CPU time 3.77 seconds
Started Feb 04 04:19:20 PM PST 24
Finished Feb 04 04:19:30 PM PST 24
Peak memory 234004 kb
Host smart-8d56e921-328b-485b-8795-47a3fab082c4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241775490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3241775490
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1973294712
Short name T4
Test name
Test status
Simulation time 83533956839 ps
CPU time 2026.47 seconds
Started Feb 04 04:20:11 PM PST 24
Finished Feb 04 04:54:00 PM PST 24
Peak memory 228152 kb
Host smart-be4bd0f9-3f1c-4732-bf3a-96ef3fdf6b98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973294712 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1973294712
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.2408543431
Short name T39
Test name
Test status
Simulation time 60458586 ps
CPU time 1.78 seconds
Started Feb 04 04:23:35 PM PST 24
Finished Feb 04 04:23:42 PM PST 24
Peak memory 215600 kb
Host smart-1978490b-cfb8-4f81-a4f7-f31609b3f40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408543431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2408543431
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2320760502
Short name T212
Test name
Test status
Simulation time 66668470 ps
CPU time 0.79 seconds
Started Feb 04 12:47:04 PM PST 24
Finished Feb 04 12:47:06 PM PST 24
Peak memory 205672 kb
Host smart-7208d212-5ef2-4b4f-ab2a-e637759a4290
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320760502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2320760502
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3364292545
Short name T193
Test name
Test status
Simulation time 344626122 ps
CPU time 3.29 seconds
Started Feb 04 12:46:52 PM PST 24
Finished Feb 04 12:46:59 PM PST 24
Peak memory 214000 kb
Host smart-a984df0c-269b-46c7-9921-3fcd2a2921f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364292545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3364292545
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3435814904
Short name T450
Test name
Test status
Simulation time 51852238 ps
CPU time 1.1 seconds
Started Feb 04 04:21:56 PM PST 24
Finished Feb 04 04:22:00 PM PST 24
Peak memory 216412 kb
Host smart-4b7356b2-f782-40b7-bc0e-04331663344a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435814904 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3435814904
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.3337242653
Short name T194
Test name
Test status
Simulation time 46819954 ps
CPU time 1.16 seconds
Started Feb 04 12:46:49 PM PST 24
Finished Feb 04 12:46:53 PM PST 24
Peak memory 205812 kb
Host smart-a84534a0-99ec-4f2e-9892-972cd2c5e5c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337242653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.3337242653
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/default/34.edn_genbits.2633198206
Short name T29
Test name
Test status
Simulation time 45213353 ps
CPU time 1.48 seconds
Started Feb 04 04:21:36 PM PST 24
Finished Feb 04 04:21:39 PM PST 24
Peak memory 216524 kb
Host smart-600838cb-9304-4cae-8f02-68537bbb840c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633198206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.2633198206
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3475126615
Short name T79
Test name
Test status
Simulation time 23053754 ps
CPU time 1.14 seconds
Started Feb 04 04:19:09 PM PST 24
Finished Feb 04 04:19:12 PM PST 24
Peak memory 215428 kb
Host smart-ac5ffd01-e7b6-4268-bb2d-559b32ec7f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475126615 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3475126615
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.4282722047
Short name T102
Test name
Test status
Simulation time 19641957 ps
CPU time 1.11 seconds
Started Feb 04 04:19:11 PM PST 24
Finished Feb 04 04:19:13 PM PST 24
Peak memory 215320 kb
Host smart-8c01490e-f8b4-4a70-96c5-b6c96c002649
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282722047 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.4282722047
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_alert.2108291483
Short name T249
Test name
Test status
Simulation time 233408452 ps
CPU time 1.19 seconds
Started Feb 04 04:19:09 PM PST 24
Finished Feb 04 04:19:12 PM PST 24
Peak memory 205944 kb
Host smart-e0720216-1729-453d-83e5-03588e705b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108291483 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2108291483
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable.2528993066
Short name T46
Test name
Test status
Simulation time 16485112 ps
CPU time 0.88 seconds
Started Feb 04 04:20:05 PM PST 24
Finished Feb 04 04:20:09 PM PST 24
Peak memory 215076 kb
Host smart-e2df10fa-b1e0-4f96-a870-4b2192962788
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528993066 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2528993066
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/2.edn_regwen.4283929939
Short name T898
Test name
Test status
Simulation time 15358192 ps
CPU time 1.05 seconds
Started Feb 04 04:19:06 PM PST 24
Finished Feb 04 04:19:09 PM PST 24
Peak memory 206732 kb
Host smart-7d455364-45d3-4d80-a800-b1ce1921a6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283929939 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.4283929939
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/12.edn_disable.4229386122
Short name T134
Test name
Test status
Simulation time 48711324 ps
CPU time 0.84 seconds
Started Feb 04 04:20:04 PM PST 24
Finished Feb 04 04:20:07 PM PST 24
Peak memory 215048 kb
Host smart-9bc43109-99a5-44ec-a094-dbcb6db4b61b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229386122 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.4229386122
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable.324579178
Short name T874
Test name
Test status
Simulation time 13176255 ps
CPU time 1.04 seconds
Started Feb 04 04:19:10 PM PST 24
Finished Feb 04 04:19:12 PM PST 24
Peak memory 215228 kb
Host smart-25b6baa4-bfb9-4d50-923f-5b7ed290dd3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324579178 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.324579178
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.4291736371
Short name T117
Test name
Test status
Simulation time 104493326 ps
CPU time 1.19 seconds
Started Feb 04 04:19:19 PM PST 24
Finished Feb 04 04:19:21 PM PST 24
Peak memory 215392 kb
Host smart-42c1a162-e3f6-4ebe-9b08-5b12e4bce26d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291736371 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.4291736371
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_intr.1898868505
Short name T86
Test name
Test status
Simulation time 20433799 ps
CPU time 1.04 seconds
Started Feb 04 04:21:52 PM PST 24
Finished Feb 04 04:21:54 PM PST 24
Peak memory 226472 kb
Host smart-48789f87-fb7a-4fcb-befb-0283891c9c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898868505 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1898868505
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3719255692
Short name T5
Test name
Test status
Simulation time 319179990411 ps
CPU time 1954.98 seconds
Started Feb 04 04:21:28 PM PST 24
Finished Feb 04 04:54:05 PM PST 24
Peak memory 227808 kb
Host smart-58190535-4f4a-4af1-b609-593418a5cc98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719255692 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3719255692
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2538015456
Short name T492
Test name
Test status
Simulation time 22098862 ps
CPU time 0.97 seconds
Started Feb 04 04:20:30 PM PST 24
Finished Feb 04 04:20:36 PM PST 24
Peak memory 215248 kb
Host smart-fde9eda1-1976-4692-8873-3a6cc654de1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538015456 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2538015456
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_disable.3933303912
Short name T143
Test name
Test status
Simulation time 12478609 ps
CPU time 0.9 seconds
Started Feb 04 04:19:47 PM PST 24
Finished Feb 04 04:19:53 PM PST 24
Peak memory 215220 kb
Host smart-a56d27eb-b1a0-445f-ae97-a97dbd843443
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933303912 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3933303912
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.2978276022
Short name T33
Test name
Test status
Simulation time 34064386 ps
CPU time 1.22 seconds
Started Feb 04 04:20:03 PM PST 24
Finished Feb 04 04:20:05 PM PST 24
Peak memory 217836 kb
Host smart-a59da6bb-b197-4805-b191-a776742d33c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978276022 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2978276022
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/17.edn_err.35408932
Short name T136
Test name
Test status
Simulation time 23018608 ps
CPU time 0.95 seconds
Started Feb 04 04:20:20 PM PST 24
Finished Feb 04 04:20:22 PM PST 24
Peak memory 216656 kb
Host smart-baed9123-7aab-4781-9176-828e617917c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35408932 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.35408932
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/214.edn_genbits.2043866675
Short name T68
Test name
Test status
Simulation time 56101570 ps
CPU time 1.44 seconds
Started Feb 04 04:23:56 PM PST 24
Finished Feb 04 04:23:59 PM PST 24
Peak memory 215424 kb
Host smart-14687c0b-b1b2-4dba-963d-10ce5356245b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043866675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.2043866675
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_disable.795056527
Short name T178
Test name
Test status
Simulation time 10748895 ps
CPU time 0.87 seconds
Started Feb 04 04:20:50 PM PST 24
Finished Feb 04 04:20:53 PM PST 24
Peak memory 215052 kb
Host smart-4cc1d86e-061b-4b76-8eee-ac0adf914148
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795056527 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.795056527
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable.126868653
Short name T150
Test name
Test status
Simulation time 11129275 ps
CPU time 0.93 seconds
Started Feb 04 04:22:07 PM PST 24
Finished Feb 04 04:22:09 PM PST 24
Peak memory 214988 kb
Host smart-a9ec2bbe-edc7-4359-a1a5-3ff0e7be49c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126868653 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.126868653
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/198.edn_genbits.4198474950
Short name T320
Test name
Test status
Simulation time 25297892 ps
CPU time 1.23 seconds
Started Feb 04 04:23:46 PM PST 24
Finished Feb 04 04:23:49 PM PST 24
Peak memory 217968 kb
Host smart-53d0d172-ec30-4127-b482-641a139f28a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198474950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.4198474950
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_genbits.1831590144
Short name T176
Test name
Test status
Simulation time 57288420 ps
CPU time 1.25 seconds
Started Feb 04 04:21:06 PM PST 24
Finished Feb 04 04:21:07 PM PST 24
Peak memory 216816 kb
Host smart-111a3bff-96a0-466d-95a1-2c38fb856f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831590144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1831590144
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_disable.4264492123
Short name T161
Test name
Test status
Simulation time 27331823 ps
CPU time 0.87 seconds
Started Feb 04 04:18:44 PM PST 24
Finished Feb 04 04:18:47 PM PST 24
Peak memory 214984 kb
Host smart-63d807f7-9528-424f-b439-825d6a359f18
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264492123 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.4264492123
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3191800030
Short name T147
Test name
Test status
Simulation time 102836546 ps
CPU time 1.14 seconds
Started Feb 04 04:20:04 PM PST 24
Finished Feb 04 04:20:06 PM PST 24
Peak memory 215268 kb
Host smart-0ae0686f-4deb-4954-8793-032684a6345f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191800030 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3191800030
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_disable.3921123066
Short name T124
Test name
Test status
Simulation time 46196707 ps
CPU time 0.88 seconds
Started Feb 04 04:20:20 PM PST 24
Finished Feb 04 04:20:23 PM PST 24
Peak memory 215064 kb
Host smart-76386319-e9ff-4c7e-93f3-211b3f340534
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921123066 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3921123066
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2873135343
Short name T157
Test name
Test status
Simulation time 33475482 ps
CPU time 1.01 seconds
Started Feb 04 04:20:20 PM PST 24
Finished Feb 04 04:20:22 PM PST 24
Peak memory 215216 kb
Host smart-155b4237-c807-44e5-96c0-7a530b536efc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873135343 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2873135343
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.1408885529
Short name T555
Test name
Test status
Simulation time 58977952 ps
CPU time 0.97 seconds
Started Feb 04 04:20:22 PM PST 24
Finished Feb 04 04:20:26 PM PST 24
Peak memory 215268 kb
Host smart-836ab253-6197-4251-8a68-da2e40bd502b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408885529 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.1408885529
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.2930667270
Short name T574
Test name
Test status
Simulation time 126348504 ps
CPU time 1.05 seconds
Started Feb 04 04:19:04 PM PST 24
Finished Feb 04 04:19:09 PM PST 24
Peak memory 215208 kb
Host smart-cd59a6f9-06ce-4696-b4f9-b77b2c091794
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930667270 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.2930667270
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_disable.1029832279
Short name T542
Test name
Test status
Simulation time 14187471 ps
CPU time 0.93 seconds
Started Feb 04 04:20:58 PM PST 24
Finished Feb 04 04:21:00 PM PST 24
Peak memory 215236 kb
Host smart-4fa9f16c-79bb-4c70-944c-f83f570b8208
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029832279 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.1029832279
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable.3471311582
Short name T159
Test name
Test status
Simulation time 59313816 ps
CPU time 0.88 seconds
Started Feb 04 04:22:33 PM PST 24
Finished Feb 04 04:22:37 PM PST 24
Peak memory 214984 kb
Host smart-c1ecdbf7-ce8e-4deb-9642-3a0f924861c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471311582 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3471311582
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1886978875
Short name T258
Test name
Test status
Simulation time 87119385 ps
CPU time 2.42 seconds
Started Feb 04 12:46:52 PM PST 24
Finished Feb 04 12:46:57 PM PST 24
Peak memory 205644 kb
Host smart-0eb6151c-65e2-41a3-bac5-3813a3d6e95c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886978875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1886978875
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3109113350
Short name T959
Test name
Test status
Simulation time 30849449 ps
CPU time 0.97 seconds
Started Feb 04 04:18:40 PM PST 24
Finished Feb 04 04:18:45 PM PST 24
Peak memory 206068 kb
Host smart-e9ecc928-8cc2-4041-b149-e32794634941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109113350 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3109113350
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert.990916972
Short name T573
Test name
Test status
Simulation time 279120209 ps
CPU time 0.97 seconds
Started Feb 04 04:19:46 PM PST 24
Finished Feb 04 04:19:53 PM PST 24
Peak memory 206648 kb
Host smart-90c7ad18-3d3c-4e14-ba86-a1afdce2d3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990916972 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.990916972
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert.902132072
Short name T955
Test name
Test status
Simulation time 39027583 ps
CPU time 0.98 seconds
Started Feb 04 04:20:39 PM PST 24
Finished Feb 04 04:20:41 PM PST 24
Peak memory 206664 kb
Host smart-f4c561fa-ba50-46a6-aabf-2c25ea21d8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902132072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.902132072
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/253.edn_genbits.1354572758
Short name T38
Test name
Test status
Simulation time 59786385 ps
CPU time 1.12 seconds
Started Feb 04 04:24:07 PM PST 24
Finished Feb 04 04:24:10 PM PST 24
Peak memory 215664 kb
Host smart-b826cd52-4bb2-41d8-a462-cb925af58e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354572758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1354572758
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_genbits.814605793
Short name T300
Test name
Test status
Simulation time 24027936 ps
CPU time 1.36 seconds
Started Feb 04 04:22:38 PM PST 24
Finished Feb 04 04:22:44 PM PST 24
Peak memory 215420 kb
Host smart-2df6fbff-8b0d-4b4f-8416-aa620f7ac128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814605793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.814605793
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_regwen.1665842814
Short name T281
Test name
Test status
Simulation time 51372893 ps
CPU time 0.92 seconds
Started Feb 04 04:19:46 PM PST 24
Finished Feb 04 04:19:53 PM PST 24
Peak memory 206668 kb
Host smart-d6f03e19-4f08-4e67-ae2e-b988d8ef6024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665842814 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.1665842814
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_regwen.766581158
Short name T289
Test name
Test status
Simulation time 18101783 ps
CPU time 0.92 seconds
Started Feb 04 04:19:43 PM PST 24
Finished Feb 04 04:19:46 PM PST 24
Peak memory 206740 kb
Host smart-084c11d1-5631-4774-bd98-abf0da358dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766581158 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.766581158
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/25.edn_genbits.1397929551
Short name T831
Test name
Test status
Simulation time 127049715 ps
CPU time 1.5 seconds
Started Feb 04 04:20:54 PM PST 24
Finished Feb 04 04:21:00 PM PST 24
Peak memory 217004 kb
Host smart-05ae870d-6ed7-4d58-9e49-e45af7c3ab37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397929551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.1397929551
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.671880081
Short name T236
Test name
Test status
Simulation time 20199411 ps
CPU time 0.8 seconds
Started Feb 04 12:47:05 PM PST 24
Finished Feb 04 12:47:06 PM PST 24
Peak memory 205604 kb
Host smart-8473f962-78e1-47da-bccf-4af9b1f2e43b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671880081 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.671880081
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/default/179.edn_genbits.4147670111
Short name T175
Test name
Test status
Simulation time 260868077 ps
CPU time 1.19 seconds
Started Feb 04 04:23:37 PM PST 24
Finished Feb 04 04:23:42 PM PST 24
Peak memory 214932 kb
Host smart-d72f9299-c7d8-43f8-986b-197d88906261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147670111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.4147670111
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.253199769
Short name T432
Test name
Test status
Simulation time 18461507 ps
CPU time 0.85 seconds
Started Feb 04 04:20:06 PM PST 24
Finished Feb 04 04:20:10 PM PST 24
Peak memory 205028 kb
Host smart-a0e0f345-3793-4c0d-a577-059baf9a9141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253199769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.253199769
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.811732401
Short name T216
Test name
Test status
Simulation time 111330171 ps
CPU time 1.76 seconds
Started Feb 04 12:46:48 PM PST 24
Finished Feb 04 12:46:52 PM PST 24
Peak memory 213980 kb
Host smart-a9af0da5-319f-41f9-837c-96f04673aa69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811732401 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.811732401
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.949665266
Short name T238
Test name
Test status
Simulation time 35371477 ps
CPU time 1.13 seconds
Started Feb 04 12:47:03 PM PST 24
Finished Feb 04 12:47:05 PM PST 24
Peak memory 205692 kb
Host smart-052c1468-95a0-4480-ac3d-dfa0c78523b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949665266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_ou
tstanding.949665266
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/default/13.edn_intr.303579229
Short name T99
Test name
Test status
Simulation time 51123165 ps
CPU time 0.84 seconds
Started Feb 04 04:20:00 PM PST 24
Finished Feb 04 04:20:02 PM PST 24
Peak memory 215092 kb
Host smart-a65cc6df-3ca9-4b95-9f69-b11f59fac3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303579229 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.303579229
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2209943469
Short name T376
Test name
Test status
Simulation time 301274474 ps
CPU time 2.25 seconds
Started Feb 04 12:46:46 PM PST 24
Finished Feb 04 12:46:52 PM PST 24
Peak memory 205796 kb
Host smart-5345472e-0fc2-49bd-b609-6dd42f9f7ede
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209943469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2209943469
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2477852930
Short name T327
Test name
Test status
Simulation time 151914968 ps
CPU time 2.32 seconds
Started Feb 04 04:18:40 PM PST 24
Finished Feb 04 04:18:46 PM PST 24
Peak memory 215556 kb
Host smart-4bc75f69-1503-4f5d-b5b4-f086c3cadd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477852930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2477852930
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_alert.2112823744
Short name T291
Test name
Test status
Simulation time 38712341 ps
CPU time 1.09 seconds
Started Feb 04 04:19:01 PM PST 24
Finished Feb 04 04:19:03 PM PST 24
Peak memory 205868 kb
Host smart-e5ec6cda-45e1-433d-8e2c-d375af9a0168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112823744 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2112823744
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_genbits.1575592139
Short name T312
Test name
Test status
Simulation time 131973882 ps
CPU time 2.32 seconds
Started Feb 04 04:19:08 PM PST 24
Finished Feb 04 04:19:12 PM PST 24
Peak memory 215648 kb
Host smart-a995163e-d6b3-4cf4-95d1-adc1c50dbf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575592139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1575592139
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.1942265191
Short name T739
Test name
Test status
Simulation time 39154887 ps
CPU time 1.19 seconds
Started Feb 04 04:23:12 PM PST 24
Finished Feb 04 04:23:15 PM PST 24
Peak memory 214912 kb
Host smart-587a110a-1c16-4762-9484-2828520fa1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942265191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1942265191
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/110.edn_genbits.646434010
Short name T314
Test name
Test status
Simulation time 72094619 ps
CPU time 1.32 seconds
Started Feb 04 04:23:20 PM PST 24
Finished Feb 04 04:23:23 PM PST 24
Peak memory 216820 kb
Host smart-0f920b85-7b4d-4bc2-9b0f-c520e8a77423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646434010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.646434010
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.156701824
Short name T595
Test name
Test status
Simulation time 30949917 ps
CPU time 1.27 seconds
Started Feb 04 04:23:18 PM PST 24
Finished Feb 04 04:23:21 PM PST 24
Peak memory 215236 kb
Host smart-506999e2-dc5e-4178-9c41-2f87bddc12da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156701824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.156701824
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.1735619068
Short name T685
Test name
Test status
Simulation time 184076827 ps
CPU time 1.13 seconds
Started Feb 04 04:23:18 PM PST 24
Finished Feb 04 04:23:20 PM PST 24
Peak memory 215428 kb
Host smart-0e6fbd8c-743a-473a-a5fa-758e8ea32154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735619068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1735619068
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.2804077312
Short name T35
Test name
Test status
Simulation time 71752924 ps
CPU time 1.1 seconds
Started Feb 04 04:23:42 PM PST 24
Finished Feb 04 04:23:48 PM PST 24
Peak memory 215448 kb
Host smart-1e2319de-8922-40bc-bc0c-c960d4e0a5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804077312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2804077312
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_genbits.2715755018
Short name T305
Test name
Test status
Simulation time 64797000 ps
CPU time 1.2 seconds
Started Feb 04 04:20:30 PM PST 24
Finished Feb 04 04:20:36 PM PST 24
Peak memory 216664 kb
Host smart-cf1a84c2-59e1-49b6-9607-4e4174daac41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715755018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2715755018
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.2157867692
Short name T43
Test name
Test status
Simulation time 26791167 ps
CPU time 1.33 seconds
Started Feb 04 04:23:46 PM PST 24
Finished Feb 04 04:23:49 PM PST 24
Peak memory 216640 kb
Host smart-202496cf-23e0-46e3-b12d-84bc055da7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157867692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2157867692
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.4182243501
Short name T545
Test name
Test status
Simulation time 37308012 ps
CPU time 1.09 seconds
Started Feb 04 04:21:00 PM PST 24
Finished Feb 04 04:21:03 PM PST 24
Peak memory 206040 kb
Host smart-f7c76f10-dab3-4caf-b5ea-f6f1e8c94c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182243501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.4182243501
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/290.edn_genbits.3631349520
Short name T168
Test name
Test status
Simulation time 46707419 ps
CPU time 1.06 seconds
Started Feb 04 04:24:14 PM PST 24
Finished Feb 04 04:24:17 PM PST 24
Peak memory 216572 kb
Host smart-c60991e4-f912-446d-83aa-ca40e07ea943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631349520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3631349520
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.299366670
Short name T965
Test name
Test status
Simulation time 19524824 ps
CPU time 1.1 seconds
Started Feb 04 04:20:01 PM PST 24
Finished Feb 04 04:20:04 PM PST 24
Peak memory 215328 kb
Host smart-f65f420f-92ac-40c8-91e0-b9cb0e32fbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299366670 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.299366670
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.421736157
Short name T202
Test name
Test status
Simulation time 31075486 ps
CPU time 1.09 seconds
Started Feb 04 12:46:51 PM PST 24
Finished Feb 04 12:46:56 PM PST 24
Peak memory 205780 kb
Host smart-e8dc1fac-2b24-421c-98ab-af8dd4f05da7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421736157 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.421736157
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2920033859
Short name T353
Test name
Test status
Simulation time 367280458 ps
CPU time 3.52 seconds
Started Feb 04 12:46:44 PM PST 24
Finished Feb 04 12:46:53 PM PST 24
Peak memory 214080 kb
Host smart-5c4f108e-4635-438c-87a3-eed54ba532d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920033859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2920033859
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/default/10.edn_disable.2250307643
Short name T173
Test name
Test status
Simulation time 17894596 ps
CPU time 0.87 seconds
Started Feb 04 04:19:48 PM PST 24
Finished Feb 04 04:19:53 PM PST 24
Peak memory 215032 kb
Host smart-a8ba4016-0fbc-47ed-9162-bf5573ee4001
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250307643 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2250307643
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.3113663976
Short name T96
Test name
Test status
Simulation time 25584881 ps
CPU time 1.43 seconds
Started Feb 04 04:20:38 PM PST 24
Finished Feb 04 04:20:40 PM PST 24
Peak memory 215320 kb
Host smart-7445fd47-5222-42a9-8182-66323c54bf69
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113663976 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.3113663976
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_disable.4044302581
Short name T182
Test name
Test status
Simulation time 13794920 ps
CPU time 0.94 seconds
Started Feb 04 04:21:08 PM PST 24
Finished Feb 04 04:21:10 PM PST 24
Peak memory 215260 kb
Host smart-9854b676-0126-458e-9f40-2b66a7cbccb2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044302581 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.4044302581
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2879623192
Short name T224
Test name
Test status
Simulation time 83459715 ps
CPU time 1.12 seconds
Started Feb 04 12:46:51 PM PST 24
Finished Feb 04 12:46:55 PM PST 24
Peak memory 205648 kb
Host smart-74e634ce-0f7a-4cd0-8d3d-eb789d85422f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879623192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2879623192
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.925463666
Short name T368
Test name
Test status
Simulation time 34119528 ps
CPU time 2.06 seconds
Started Feb 04 12:46:50 PM PST 24
Finished Feb 04 12:46:56 PM PST 24
Peak memory 205732 kb
Host smart-529ac398-61f5-422b-8f10-a176e86dee99
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925463666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.925463666
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.941274847
Short name T412
Test name
Test status
Simulation time 52307712 ps
CPU time 0.88 seconds
Started Feb 04 12:46:36 PM PST 24
Finished Feb 04 12:46:40 PM PST 24
Peak memory 205820 kb
Host smart-2ceaf02e-0d94-47a6-9199-bd357ba62679
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941274847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.941274847
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3735223034
Short name T28
Test name
Test status
Simulation time 73216699 ps
CPU time 1.15 seconds
Started Feb 04 12:46:49 PM PST 24
Finished Feb 04 12:46:53 PM PST 24
Peak memory 214140 kb
Host smart-a38d9cee-8807-4726-8f0d-c471819a543c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735223034 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3735223034
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.3382209399
Short name T403
Test name
Test status
Simulation time 42050786 ps
CPU time 0.85 seconds
Started Feb 04 12:46:46 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 205708 kb
Host smart-7e82c950-6240-4491-9842-12af29bcdab6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382209399 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.3382209399
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3304683469
Short name T375
Test name
Test status
Simulation time 17701713 ps
CPU time 0.85 seconds
Started Feb 04 12:46:45 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 205648 kb
Host smart-b26bd9f2-6f48-4855-af4a-ebec90900759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304683469 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3304683469
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3167250491
Short name T218
Test name
Test status
Simulation time 93971208 ps
CPU time 1.22 seconds
Started Feb 04 12:46:45 PM PST 24
Finished Feb 04 12:46:51 PM PST 24
Peak memory 205812 kb
Host smart-c9f867bd-1413-4b4e-88e7-a4b2c9ca534d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167250491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3167250491
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3018646660
Short name T351
Test name
Test status
Simulation time 161241422 ps
CPU time 3.71 seconds
Started Feb 04 12:46:42 PM PST 24
Finished Feb 04 12:46:52 PM PST 24
Peak memory 205972 kb
Host smart-3d9edc6f-cec9-48f4-a52c-74b4a74ab5c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018646660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3018646660
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1314760537
Short name T420
Test name
Test status
Simulation time 544709396 ps
CPU time 3.6 seconds
Started Feb 04 12:46:49 PM PST 24
Finished Feb 04 12:46:55 PM PST 24
Peak memory 205748 kb
Host smart-8dbc7c3c-9b77-4f09-951c-7fdc5adc1e93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314760537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1314760537
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1817968462
Short name T200
Test name
Test status
Simulation time 33068996 ps
CPU time 0.88 seconds
Started Feb 04 12:46:46 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 205608 kb
Host smart-c02f6bb2-7271-4b5a-ac6f-ebf5100508c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817968462 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1817968462
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1125524378
Short name T196
Test name
Test status
Simulation time 84692475 ps
CPU time 1.22 seconds
Started Feb 04 12:46:47 PM PST 24
Finished Feb 04 12:46:51 PM PST 24
Peak memory 214092 kb
Host smart-b0fb0546-5bc9-4a9b-b100-a50381206d5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125524378 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1125524378
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.861448698
Short name T233
Test name
Test status
Simulation time 29764302 ps
CPU time 0.8 seconds
Started Feb 04 12:46:41 PM PST 24
Finished Feb 04 12:46:44 PM PST 24
Peak memory 205580 kb
Host smart-d86291ee-e1a3-4013-8537-7e2996018ac3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861448698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.861448698
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3773423883
Short name T388
Test name
Test status
Simulation time 33606316 ps
CPU time 0.82 seconds
Started Feb 04 12:46:42 PM PST 24
Finished Feb 04 12:46:49 PM PST 24
Peak memory 205612 kb
Host smart-a101a3e8-8eee-4a8a-b46c-05a8e70d8e01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773423883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3773423883
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1016820745
Short name T225
Test name
Test status
Simulation time 132258417 ps
CPU time 1.05 seconds
Started Feb 04 12:46:53 PM PST 24
Finished Feb 04 12:46:58 PM PST 24
Peak memory 205784 kb
Host smart-51c4b840-f779-4cfe-854a-f71025f5527b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016820745 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1016820745
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1962085522
Short name T417
Test name
Test status
Simulation time 183284784 ps
CPU time 3.49 seconds
Started Feb 04 12:46:46 PM PST 24
Finished Feb 04 12:46:53 PM PST 24
Peak memory 214032 kb
Host smart-bcd03b01-3b06-4107-9e8e-74c464cb5c82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962085522 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1962085522
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1843722969
Short name T235
Test name
Test status
Simulation time 46765320 ps
CPU time 0.89 seconds
Started Feb 04 12:46:46 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 205672 kb
Host smart-82dedec9-1e45-4ce2-8b6d-ea2088d75148
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843722969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1843722969
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.95965645
Short name T386
Test name
Test status
Simulation time 18419846 ps
CPU time 0.84 seconds
Started Feb 04 12:47:03 PM PST 24
Finished Feb 04 12:47:05 PM PST 24
Peak memory 205628 kb
Host smart-d1f3df9e-6d62-4fd7-aa55-7051420b2288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95965645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.95965645
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2876215772
Short name T392
Test name
Test status
Simulation time 95539511 ps
CPU time 1.87 seconds
Started Feb 04 12:47:03 PM PST 24
Finished Feb 04 12:47:06 PM PST 24
Peak memory 213820 kb
Host smart-9126589d-a9e1-4693-b964-f829e9149327
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876215772 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2876215772
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1109858741
Short name T26
Test name
Test status
Simulation time 159578327 ps
CPU time 3.41 seconds
Started Feb 04 12:46:51 PM PST 24
Finished Feb 04 12:46:58 PM PST 24
Peak memory 205788 kb
Host smart-7efa3a11-87e7-473b-9288-4a9a5df61eda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109858741 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1109858741
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3303290567
Short name T346
Test name
Test status
Simulation time 153505132 ps
CPU time 1.18 seconds
Started Feb 04 12:46:51 PM PST 24
Finished Feb 04 12:46:56 PM PST 24
Peak memory 214048 kb
Host smart-15871371-c7e8-4db0-a634-d940fcf52427
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303290567 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3303290567
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2515490212
Short name T401
Test name
Test status
Simulation time 26702289 ps
CPU time 0.89 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:47:10 PM PST 24
Peak memory 205248 kb
Host smart-8886c099-c39e-4c4e-8209-12a5a799893c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515490212 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2515490212
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1080966988
Short name T27
Test name
Test status
Simulation time 17810219 ps
CPU time 0.89 seconds
Started Feb 04 12:46:46 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 205672 kb
Host smart-507e9888-f004-4953-9c08-cbb219fefda0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080966988 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1080966988
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.3634587492
Short name T373
Test name
Test status
Simulation time 33104191 ps
CPU time 0.92 seconds
Started Feb 04 12:46:51 PM PST 24
Finished Feb 04 12:46:55 PM PST 24
Peak memory 205776 kb
Host smart-f9cb7a48-c8f1-47a4-b2ce-7bd913967e2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634587492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.3634587492
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.4287986804
Short name T370
Test name
Test status
Simulation time 144121912 ps
CPU time 2.12 seconds
Started Feb 04 12:47:03 PM PST 24
Finished Feb 04 12:47:06 PM PST 24
Peak memory 213960 kb
Host smart-1d5dab15-9a01-48b8-b347-a9039e379f45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287986804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.4287986804
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2184737653
Short name T334
Test name
Test status
Simulation time 54284263 ps
CPU time 1.78 seconds
Started Feb 04 12:46:50 PM PST 24
Finished Feb 04 12:46:55 PM PST 24
Peak memory 205828 kb
Host smart-914f4ba2-f487-4ebf-a145-db7bfb2a1186
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184737653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2184737653
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1610454471
Short name T404
Test name
Test status
Simulation time 58729495 ps
CPU time 1.05 seconds
Started Feb 04 12:46:52 PM PST 24
Finished Feb 04 12:46:56 PM PST 24
Peak memory 205680 kb
Host smart-2d609f86-2d67-422e-8394-f2fad0ed8e93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610454471 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1610454471
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3406857058
Short name T341
Test name
Test status
Simulation time 39379222 ps
CPU time 0.81 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:47:10 PM PST 24
Peak memory 205656 kb
Host smart-e9da383f-75ee-41f2-aa3c-68cc21457977
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406857058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3406857058
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1516737158
Short name T367
Test name
Test status
Simulation time 22345845 ps
CPU time 0.85 seconds
Started Feb 04 12:46:49 PM PST 24
Finished Feb 04 12:46:52 PM PST 24
Peak memory 205608 kb
Host smart-a24a1797-1e7a-4a37-8bf5-c4a6892ab18d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516737158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1516737158
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3666290907
Short name T384
Test name
Test status
Simulation time 35471863 ps
CPU time 1.08 seconds
Started Feb 04 12:46:50 PM PST 24
Finished Feb 04 12:46:55 PM PST 24
Peak memory 205684 kb
Host smart-7ec493c3-2c51-49a6-8028-ede50ec0692e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666290907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3666290907
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1409421606
Short name T352
Test name
Test status
Simulation time 35148332 ps
CPU time 1.21 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:47:11 PM PST 24
Peak memory 214056 kb
Host smart-fc097ce4-cf4c-4387-a8e3-4ce397763c66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409421606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1409421606
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2590193272
Short name T213
Test name
Test status
Simulation time 84294128 ps
CPU time 2.15 seconds
Started Feb 04 12:46:50 PM PST 24
Finished Feb 04 12:46:56 PM PST 24
Peak memory 205752 kb
Host smart-a1a60fb2-20bb-417f-8607-c2c620bd28d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590193272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2590193272
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.824428870
Short name T383
Test name
Test status
Simulation time 41697618 ps
CPU time 1.12 seconds
Started Feb 04 12:47:06 PM PST 24
Finished Feb 04 12:47:09 PM PST 24
Peak memory 214068 kb
Host smart-5cff973c-5ae3-45af-8f74-db821bcfdd99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824428870 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.824428870
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.866275627
Short name T331
Test name
Test status
Simulation time 34579885 ps
CPU time 0.91 seconds
Started Feb 04 12:46:46 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 205736 kb
Host smart-17f164a0-39c4-4932-8457-17d04105bf69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866275627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.866275627
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.142494086
Short name T336
Test name
Test status
Simulation time 17381229 ps
CPU time 0.88 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:47:10 PM PST 24
Peak memory 205692 kb
Host smart-f43f015f-2a4a-48a7-9c61-0b04ed79ce05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142494086 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.142494086
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2273412221
Short name T390
Test name
Test status
Simulation time 15411919 ps
CPU time 0.95 seconds
Started Feb 04 12:46:56 PM PST 24
Finished Feb 04 12:47:00 PM PST 24
Peak memory 205864 kb
Host smart-7f6d2a06-6c77-4c06-9ac6-3a91895a0a42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273412221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2273412221
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3990916680
Short name T395
Test name
Test status
Simulation time 239545074 ps
CPU time 4.37 seconds
Started Feb 04 12:46:50 PM PST 24
Finished Feb 04 12:46:58 PM PST 24
Peak memory 214000 kb
Host smart-1d3aef6e-c445-4a27-956a-82bbb11320a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990916680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3990916680
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.141056937
Short name T190
Test name
Test status
Simulation time 82198052 ps
CPU time 2.4 seconds
Started Feb 04 12:46:52 PM PST 24
Finished Feb 04 12:46:58 PM PST 24
Peak memory 205800 kb
Host smart-97341b02-0024-43b0-b4c5-ba8f307e0a00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141056937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.141056937
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3834881241
Short name T359
Test name
Test status
Simulation time 25817470 ps
CPU time 1.27 seconds
Started Feb 04 12:46:51 PM PST 24
Finished Feb 04 12:46:56 PM PST 24
Peak memory 214004 kb
Host smart-6c20ddf7-625d-4c53-83b9-4f769d39bdc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834881241 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3834881241
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3667327725
Short name T229
Test name
Test status
Simulation time 53261265 ps
CPU time 0.9 seconds
Started Feb 04 12:46:52 PM PST 24
Finished Feb 04 12:46:57 PM PST 24
Peak memory 205736 kb
Host smart-ed8843f4-61b2-4620-8824-13d48991ec3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667327725 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3667327725
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.716857779
Short name T204
Test name
Test status
Simulation time 24959127 ps
CPU time 0.85 seconds
Started Feb 04 12:46:56 PM PST 24
Finished Feb 04 12:46:59 PM PST 24
Peak memory 205720 kb
Host smart-ce9cb624-5e06-48b4-ad78-1e310ad611da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716857779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.716857779
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2564987987
Short name T362
Test name
Test status
Simulation time 26656785 ps
CPU time 1.15 seconds
Started Feb 04 12:46:56 PM PST 24
Finished Feb 04 12:47:00 PM PST 24
Peak memory 205788 kb
Host smart-b574da0d-e208-4be6-9a45-972d371984ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564987987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2564987987
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1014703910
Short name T349
Test name
Test status
Simulation time 36434516 ps
CPU time 1.1 seconds
Started Feb 04 12:47:06 PM PST 24
Finished Feb 04 12:47:09 PM PST 24
Peak memory 214088 kb
Host smart-c642b8e5-991d-444f-8713-4550f42cac78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014703910 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1014703910
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2243044636
Short name T394
Test name
Test status
Simulation time 21993825 ps
CPU time 0.92 seconds
Started Feb 04 12:46:53 PM PST 24
Finished Feb 04 12:46:58 PM PST 24
Peak memory 205676 kb
Host smart-3ffd2cec-6f84-4a9a-bdcc-ee7a32a9aab9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243044636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2243044636
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2560182755
Short name T423
Test name
Test status
Simulation time 14056456 ps
CPU time 0.86 seconds
Started Feb 04 12:46:52 PM PST 24
Finished Feb 04 12:46:56 PM PST 24
Peak memory 205672 kb
Host smart-8cf1382b-7387-4956-b17b-dd8a65bba382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560182755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2560182755
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1828700800
Short name T239
Test name
Test status
Simulation time 38598515 ps
CPU time 1.07 seconds
Started Feb 04 12:47:06 PM PST 24
Finished Feb 04 12:47:09 PM PST 24
Peak memory 205816 kb
Host smart-af0aaac1-0775-4dd2-bdb7-4142b7d92680
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828700800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1828700800
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3074945470
Short name T381
Test name
Test status
Simulation time 94214887 ps
CPU time 1.85 seconds
Started Feb 04 12:46:56 PM PST 24
Finished Feb 04 12:47:00 PM PST 24
Peak memory 214028 kb
Host smart-bd28b6d7-d99e-446b-acf0-c9d89e09b370
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074945470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3074945470
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1961343644
Short name T391
Test name
Test status
Simulation time 51685884 ps
CPU time 1.71 seconds
Started Feb 04 12:46:42 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 205680 kb
Host smart-3120835b-76d2-492e-b6aa-b794194fb47e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961343644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1961343644
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1872289633
Short name T188
Test name
Test status
Simulation time 75449647 ps
CPU time 1.5 seconds
Started Feb 04 12:46:52 PM PST 24
Finished Feb 04 12:46:58 PM PST 24
Peak memory 222100 kb
Host smart-c691ab30-599a-4a12-b4b9-04d38ee90347
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872289633 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1872289633
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2874613114
Short name T397
Test name
Test status
Simulation time 54835351 ps
CPU time 0.83 seconds
Started Feb 04 12:46:52 PM PST 24
Finished Feb 04 12:46:57 PM PST 24
Peak memory 205676 kb
Host smart-e4678ba7-cc8d-4815-9344-c0a26e92c66c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874613114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2874613114
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.180763445
Short name T350
Test name
Test status
Simulation time 13906669 ps
CPU time 0.79 seconds
Started Feb 04 12:46:52 PM PST 24
Finished Feb 04 12:46:56 PM PST 24
Peak memory 205524 kb
Host smart-1315ad4c-969e-49b7-83c1-7d818797849b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180763445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.180763445
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.4203302160
Short name T413
Test name
Test status
Simulation time 125080587 ps
CPU time 1.16 seconds
Started Feb 04 12:46:51 PM PST 24
Finished Feb 04 12:46:55 PM PST 24
Peak memory 205776 kb
Host smart-d64d1389-7dd5-4999-9bc8-bef7d91020df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203302160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.4203302160
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.889952657
Short name T201
Test name
Test status
Simulation time 387774423 ps
CPU time 3.45 seconds
Started Feb 04 12:46:53 PM PST 24
Finished Feb 04 12:47:01 PM PST 24
Peak memory 213576 kb
Host smart-d85b6f20-12dd-4633-b56d-b6c42a26b181
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889952657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.889952657
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.56706440
Short name T255
Test name
Test status
Simulation time 48781167 ps
CPU time 1.59 seconds
Started Feb 04 12:47:04 PM PST 24
Finished Feb 04 12:47:06 PM PST 24
Peak memory 205800 kb
Host smart-c2013aa8-d591-46be-9753-8571b834fc3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56706440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.56706440
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3897477593
Short name T419
Test name
Test status
Simulation time 74543062 ps
CPU time 1.36 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:47:11 PM PST 24
Peak memory 213680 kb
Host smart-3f892237-4262-41f4-bd08-74047430a39e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897477593 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3897477593
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1133250233
Short name T231
Test name
Test status
Simulation time 57844609 ps
CPU time 0.97 seconds
Started Feb 04 12:46:50 PM PST 24
Finished Feb 04 12:46:55 PM PST 24
Peak memory 205724 kb
Host smart-21d500ec-9690-4633-a901-d999127bd23b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133250233 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1133250233
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.4183911383
Short name T355
Test name
Test status
Simulation time 20931183 ps
CPU time 0.86 seconds
Started Feb 04 12:46:50 PM PST 24
Finished Feb 04 12:46:55 PM PST 24
Peak memory 205624 kb
Host smart-6034729e-be0b-4201-bcf2-560885856dd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183911383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.4183911383
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3618774352
Short name T340
Test name
Test status
Simulation time 161409019 ps
CPU time 2.93 seconds
Started Feb 04 12:47:05 PM PST 24
Finished Feb 04 12:47:09 PM PST 24
Peak memory 214100 kb
Host smart-a0acbd19-37b6-4a9f-a95d-bf6ef3093541
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618774352 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3618774352
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.3683705832
Short name T356
Test name
Test status
Simulation time 328772312 ps
CPU time 2.37 seconds
Started Feb 04 12:46:45 PM PST 24
Finished Feb 04 12:46:52 PM PST 24
Peak memory 205748 kb
Host smart-a519ea80-97e4-4bb4-93d4-f2a9c21950f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683705832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.3683705832
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2873494944
Short name T228
Test name
Test status
Simulation time 66876502 ps
CPU time 1.04 seconds
Started Feb 04 12:46:46 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 213992 kb
Host smart-fc0016b1-ff8a-441a-bcbf-3ac2278fc824
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873494944 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2873494944
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2563599964
Short name T227
Test name
Test status
Simulation time 23298385 ps
CPU time 0.85 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:47:11 PM PST 24
Peak memory 205512 kb
Host smart-e9cb2a86-6b99-4b59-b3f3-6d2204f719f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563599964 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2563599964
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.114932416
Short name T230
Test name
Test status
Simulation time 16623056 ps
CPU time 0.88 seconds
Started Feb 04 12:47:03 PM PST 24
Finished Feb 04 12:47:04 PM PST 24
Peak memory 205628 kb
Host smart-3790aff3-9f42-4fa5-8c3e-22e86c63ecfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114932416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.114932416
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3689453898
Short name T197
Test name
Test status
Simulation time 42772877 ps
CPU time 1.16 seconds
Started Feb 04 12:47:03 PM PST 24
Finished Feb 04 12:47:05 PM PST 24
Peak memory 205448 kb
Host smart-7912978b-bf9a-489b-882c-d4e945849d18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689453898 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3689453898
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3183155080
Short name T406
Test name
Test status
Simulation time 118253132 ps
CPU time 3.98 seconds
Started Feb 04 12:47:03 PM PST 24
Finished Feb 04 12:47:08 PM PST 24
Peak memory 213976 kb
Host smart-e98badae-0db4-42cd-8ff1-ee6d86359921
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183155080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3183155080
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3052911445
Short name T407
Test name
Test status
Simulation time 126800706 ps
CPU time 1.4 seconds
Started Feb 04 12:46:51 PM PST 24
Finished Feb 04 12:46:56 PM PST 24
Peak memory 205788 kb
Host smart-a07cb08a-06d1-4f45-bb85-f987d5121e97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052911445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3052911445
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.630919970
Short name T405
Test name
Test status
Simulation time 65771787 ps
CPU time 0.94 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:47:10 PM PST 24
Peak memory 205800 kb
Host smart-539442bf-5acc-4049-8bdd-1b7ca9d00943
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630919970 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.630919970
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1852936151
Short name T206
Test name
Test status
Simulation time 16857617 ps
CPU time 0.82 seconds
Started Feb 04 12:46:43 PM PST 24
Finished Feb 04 12:46:49 PM PST 24
Peak memory 205724 kb
Host smart-be359101-ee9d-4345-8f37-c93d63c65432
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852936151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1852936151
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.332859470
Short name T387
Test name
Test status
Simulation time 41524106 ps
CPU time 0.83 seconds
Started Feb 04 12:46:51 PM PST 24
Finished Feb 04 12:46:55 PM PST 24
Peak memory 205592 kb
Host smart-ce235cc4-f6e5-4c23-8687-cac57a4602e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332859470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.332859470
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1299295088
Short name T365
Test name
Test status
Simulation time 18879182 ps
CPU time 0.95 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:47:11 PM PST 24
Peak memory 205564 kb
Host smart-9630e4b9-e5c0-419d-9259-8c9ca329f997
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299295088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1299295088
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.2281856288
Short name T357
Test name
Test status
Simulation time 438560858 ps
CPU time 4.17 seconds
Started Feb 04 12:46:49 PM PST 24
Finished Feb 04 12:46:56 PM PST 24
Peak memory 214108 kb
Host smart-1f5abc0e-a6fe-4212-9785-57d2eff8c902
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281856288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.2281856288
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3196260676
Short name T259
Test name
Test status
Simulation time 287896007 ps
CPU time 1.47 seconds
Started Feb 04 12:47:08 PM PST 24
Finished Feb 04 12:47:12 PM PST 24
Peak memory 205732 kb
Host smart-03fafcf2-e98f-4fe2-9c13-966b5b9378b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196260676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3196260676
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.94016977
Short name T199
Test name
Test status
Simulation time 55584825 ps
CPU time 1.11 seconds
Started Feb 04 12:46:51 PM PST 24
Finished Feb 04 12:46:55 PM PST 24
Peak memory 205708 kb
Host smart-e384654c-b095-44a7-91f7-a45c3ce10bdc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94016977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.94016977
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2409320742
Short name T223
Test name
Test status
Simulation time 418696805 ps
CPU time 3.12 seconds
Started Feb 04 12:46:51 PM PST 24
Finished Feb 04 12:46:57 PM PST 24
Peak memory 205724 kb
Host smart-de6e1029-a9b3-444a-bca7-780439c828ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409320742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2409320742
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3824825801
Short name T348
Test name
Test status
Simulation time 16025427 ps
CPU time 0.88 seconds
Started Feb 04 12:46:49 PM PST 24
Finished Feb 04 12:46:53 PM PST 24
Peak memory 205812 kb
Host smart-ac5dc104-8851-4fd9-b0b6-82b9f62d8143
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824825801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3824825801
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1634794450
Short name T398
Test name
Test status
Simulation time 38755590 ps
CPU time 1.1 seconds
Started Feb 04 12:46:51 PM PST 24
Finished Feb 04 12:46:55 PM PST 24
Peak memory 214000 kb
Host smart-e0454785-df9c-4e1c-b092-6ee5a8d90aca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634794450 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1634794450
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2695401914
Short name T214
Test name
Test status
Simulation time 34317963 ps
CPU time 0.94 seconds
Started Feb 04 12:46:49 PM PST 24
Finished Feb 04 12:46:53 PM PST 24
Peak memory 205808 kb
Host smart-8ac26cdf-259d-4e5a-9373-988956c23611
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695401914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2695401914
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3933821801
Short name T49
Test name
Test status
Simulation time 14453474 ps
CPU time 0.94 seconds
Started Feb 04 12:46:49 PM PST 24
Finished Feb 04 12:46:53 PM PST 24
Peak memory 205748 kb
Host smart-ef420785-7202-49a6-b898-45f2ee8f5f14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933821801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3933821801
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3422512351
Short name T343
Test name
Test status
Simulation time 29522805 ps
CPU time 0.99 seconds
Started Feb 04 12:46:46 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 205688 kb
Host smart-7c2f5fdd-507c-486f-aa62-cd014a4109a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422512351 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3422512351
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.4078846146
Short name T192
Test name
Test status
Simulation time 77856006 ps
CPU time 2.88 seconds
Started Feb 04 12:46:49 PM PST 24
Finished Feb 04 12:46:54 PM PST 24
Peak memory 217264 kb
Host smart-8733fb50-ef0a-416b-aa70-23d3cac12487
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078846146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.4078846146
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2112829311
Short name T256
Test name
Test status
Simulation time 309861434 ps
CPU time 2.46 seconds
Started Feb 04 12:46:45 PM PST 24
Finished Feb 04 12:46:52 PM PST 24
Peak memory 205736 kb
Host smart-37075c1b-6ddc-44c6-bd84-a252e78102b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112829311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2112829311
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.4105810465
Short name T374
Test name
Test status
Simulation time 19669315 ps
CPU time 0.8 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:47:10 PM PST 24
Peak memory 205584 kb
Host smart-71a8a861-3574-4b7b-8240-7928b6a5a23e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105810465 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.4105810465
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.471957571
Short name T360
Test name
Test status
Simulation time 59144885 ps
CPU time 0.87 seconds
Started Feb 04 12:47:01 PM PST 24
Finished Feb 04 12:47:03 PM PST 24
Peak memory 205536 kb
Host smart-d956e1c5-05b8-4848-a9b0-d751bd1d2e48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471957571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.471957571
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.199959840
Short name T422
Test name
Test status
Simulation time 36411453 ps
CPU time 0.81 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:47:10 PM PST 24
Peak memory 205588 kb
Host smart-8ed5ddaf-a902-44ee-9bc4-a12f93d7ca9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199959840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.199959840
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.1974601954
Short name T210
Test name
Test status
Simulation time 38182248 ps
CPU time 0.91 seconds
Started Feb 04 12:47:08 PM PST 24
Finished Feb 04 12:47:11 PM PST 24
Peak memory 205612 kb
Host smart-f4e63329-680b-413c-9309-9e9113341305
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974601954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.1974601954
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1552966173
Short name T364
Test name
Test status
Simulation time 22350447 ps
CPU time 0.82 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:47:11 PM PST 24
Peak memory 205904 kb
Host smart-b42deee0-8596-444d-911a-2f92ee1b4a8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552966173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1552966173
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.2480217972
Short name T345
Test name
Test status
Simulation time 14139896 ps
CPU time 0.91 seconds
Started Feb 04 12:47:05 PM PST 24
Finished Feb 04 12:47:07 PM PST 24
Peak memory 205732 kb
Host smart-88a27a22-18f8-4377-9a89-ad446379efcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480217972 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.2480217972
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.4220582045
Short name T400
Test name
Test status
Simulation time 18204910 ps
CPU time 0.78 seconds
Started Feb 04 12:47:05 PM PST 24
Finished Feb 04 12:47:07 PM PST 24
Peak memory 205520 kb
Host smart-12e0c896-f9dd-4bd1-b06c-a90fab8d04e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220582045 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.4220582045
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.947388585
Short name T333
Test name
Test status
Simulation time 15076819 ps
CPU time 0.87 seconds
Started Feb 04 12:47:08 PM PST 24
Finished Feb 04 12:47:11 PM PST 24
Peak memory 205576 kb
Host smart-49a71029-9c30-435b-b5c6-62db4b8c4744
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947388585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.947388585
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.761794394
Short name T358
Test name
Test status
Simulation time 47943662 ps
CPU time 0.91 seconds
Started Feb 04 12:47:04 PM PST 24
Finished Feb 04 12:47:06 PM PST 24
Peak memory 205644 kb
Host smart-8c45d17c-6e74-4e8d-a2bb-66f6d44f8af9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761794394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.761794394
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3691921657
Short name T226
Test name
Test status
Simulation time 194367778 ps
CPU time 1.26 seconds
Started Feb 04 12:46:50 PM PST 24
Finished Feb 04 12:46:55 PM PST 24
Peak memory 205428 kb
Host smart-5a30a5b0-3a17-4414-b8ab-78634f6db5bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691921657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3691921657
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2220215112
Short name T234
Test name
Test status
Simulation time 117848146 ps
CPU time 1.9 seconds
Started Feb 04 12:46:51 PM PST 24
Finished Feb 04 12:46:56 PM PST 24
Peak memory 205724 kb
Host smart-85b9e33e-eb91-4e92-9557-66ad2698e551
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220215112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2220215112
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3863914491
Short name T408
Test name
Test status
Simulation time 17081933 ps
CPU time 0.95 seconds
Started Feb 04 12:46:46 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 205544 kb
Host smart-884e717d-9ee0-4ef6-a3e1-015a2ad7bd7f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863914491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3863914491
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.456633467
Short name T189
Test name
Test status
Simulation time 24711462 ps
CPU time 1.4 seconds
Started Feb 04 12:46:58 PM PST 24
Finished Feb 04 12:47:01 PM PST 24
Peak memory 213908 kb
Host smart-45175686-9ca6-48f4-a14a-362b3122a280
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456633467 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.456633467
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3887848551
Short name T242
Test name
Test status
Simulation time 28633288 ps
CPU time 0.9 seconds
Started Feb 04 12:46:53 PM PST 24
Finished Feb 04 12:46:58 PM PST 24
Peak memory 205300 kb
Host smart-80c28cbb-ad2e-4353-8a0b-769a89490cc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887848551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3887848551
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1898160867
Short name T380
Test name
Test status
Simulation time 17556908 ps
CPU time 0.9 seconds
Started Feb 04 12:46:47 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 205588 kb
Host smart-586db7c9-3f1b-411f-8dd8-a7cfc43af95c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898160867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1898160867
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1481490667
Short name T418
Test name
Test status
Simulation time 86520547 ps
CPU time 1.28 seconds
Started Feb 04 12:46:57 PM PST 24
Finished Feb 04 12:47:00 PM PST 24
Peak memory 205608 kb
Host smart-64ab6de0-cca2-4c64-9a97-4aa1e1dd8438
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481490667 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1481490667
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1022970364
Short name T424
Test name
Test status
Simulation time 213772084 ps
CPU time 2.3 seconds
Started Feb 04 12:46:55 PM PST 24
Finished Feb 04 12:47:01 PM PST 24
Peak memory 213876 kb
Host smart-9c4d14ae-e983-4c9f-af2f-f81606c88cf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022970364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1022970364
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.775601657
Short name T207
Test name
Test status
Simulation time 13519406 ps
CPU time 0.86 seconds
Started Feb 04 12:47:06 PM PST 24
Finished Feb 04 12:47:09 PM PST 24
Peak memory 205664 kb
Host smart-cc6ddf33-d66e-4472-9d92-b3ddee1d5f43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775601657 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.775601657
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1843161315
Short name T203
Test name
Test status
Simulation time 17657093 ps
CPU time 0.79 seconds
Started Feb 04 12:47:05 PM PST 24
Finished Feb 04 12:47:07 PM PST 24
Peak memory 205520 kb
Host smart-3cd246d5-b20a-486e-bec0-38068586c397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843161315 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1843161315
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3973557461
Short name T237
Test name
Test status
Simulation time 48546164 ps
CPU time 0.84 seconds
Started Feb 04 12:47:05 PM PST 24
Finished Feb 04 12:47:07 PM PST 24
Peak memory 205684 kb
Host smart-c3b1a010-ccf5-4043-98a7-64ac79eafc67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973557461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3973557461
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3945317346
Short name T372
Test name
Test status
Simulation time 22285111 ps
CPU time 0.85 seconds
Started Feb 04 12:47:08 PM PST 24
Finished Feb 04 12:47:12 PM PST 24
Peak memory 205804 kb
Host smart-130623c8-e1b8-4db2-baf5-69dc3b8a3363
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945317346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3945317346
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2354278932
Short name T363
Test name
Test status
Simulation time 14635681 ps
CPU time 0.81 seconds
Started Feb 04 12:47:14 PM PST 24
Finished Feb 04 12:47:18 PM PST 24
Peak memory 205676 kb
Host smart-7046f1d1-1691-487d-8e3b-b3d8611de5c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354278932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2354278932
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1968357122
Short name T347
Test name
Test status
Simulation time 14653739 ps
CPU time 0.9 seconds
Started Feb 04 12:47:04 PM PST 24
Finished Feb 04 12:47:06 PM PST 24
Peak memory 205640 kb
Host smart-92e5ce53-e01a-4236-ba45-94409078f95e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968357122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1968357122
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2794651824
Short name T338
Test name
Test status
Simulation time 84988062 ps
CPU time 0.82 seconds
Started Feb 04 12:47:11 PM PST 24
Finished Feb 04 12:47:13 PM PST 24
Peak memory 205680 kb
Host smart-b127fde5-5ff0-4ac4-87ea-479d966f4900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794651824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2794651824
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2266125968
Short name T329
Test name
Test status
Simulation time 20665855 ps
CPU time 0.85 seconds
Started Feb 04 12:47:04 PM PST 24
Finished Feb 04 12:47:06 PM PST 24
Peak memory 205652 kb
Host smart-b232c9fc-6c43-41e8-8bfa-c16bdbbc30bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266125968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2266125968
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2526608689
Short name T260
Test name
Test status
Simulation time 35462598 ps
CPU time 0.72 seconds
Started Feb 04 12:47:15 PM PST 24
Finished Feb 04 12:47:19 PM PST 24
Peak memory 205664 kb
Host smart-b8289c28-a8a8-48dc-95c2-ce19d25ef1e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526608689 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2526608689
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2610675665
Short name T198
Test name
Test status
Simulation time 129610492 ps
CPU time 1.18 seconds
Started Feb 04 12:46:53 PM PST 24
Finished Feb 04 12:46:58 PM PST 24
Peak memory 205728 kb
Host smart-82792275-1b21-46cd-8211-c6865cf9a49c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610675665 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2610675665
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3180003703
Short name T211
Test name
Test status
Simulation time 202764888 ps
CPU time 3.31 seconds
Started Feb 04 12:46:46 PM PST 24
Finished Feb 04 12:46:53 PM PST 24
Peak memory 205712 kb
Host smart-2babd621-9c81-4818-95dd-a0c01eb3baac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180003703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3180003703
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1376092902
Short name T409
Test name
Test status
Simulation time 85973615 ps
CPU time 0.87 seconds
Started Feb 04 12:46:50 PM PST 24
Finished Feb 04 12:46:55 PM PST 24
Peak memory 205328 kb
Host smart-ae06d896-2806-4c0b-b84a-78a8cb64569a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376092902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1376092902
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.1702009728
Short name T220
Test name
Test status
Simulation time 21891307 ps
CPU time 1.51 seconds
Started Feb 04 12:46:58 PM PST 24
Finished Feb 04 12:47:01 PM PST 24
Peak memory 213908 kb
Host smart-82df50b6-4ced-47d0-80c4-7e6c34cce14c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702009728 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.1702009728
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.339753239
Short name T371
Test name
Test status
Simulation time 12597668 ps
CPU time 0.86 seconds
Started Feb 04 12:46:58 PM PST 24
Finished Feb 04 12:47:01 PM PST 24
Peak memory 205632 kb
Host smart-85191166-bdbf-4286-997d-299b292b2c13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339753239 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.339753239
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1404080085
Short name T382
Test name
Test status
Simulation time 14087925 ps
CPU time 0.94 seconds
Started Feb 04 12:46:53 PM PST 24
Finished Feb 04 12:46:58 PM PST 24
Peak memory 205664 kb
Host smart-e5702554-bbdc-4802-9a98-564cb30d5f7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404080085 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1404080085
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.1749083152
Short name T402
Test name
Test status
Simulation time 19259459 ps
CPU time 1.21 seconds
Started Feb 04 12:46:43 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 205852 kb
Host smart-3afdbc48-7a63-4d6b-a9e6-4c6780b19644
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749083152 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.1749083152
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.748842014
Short name T217
Test name
Test status
Simulation time 108983949 ps
CPU time 2.13 seconds
Started Feb 04 12:46:53 PM PST 24
Finished Feb 04 12:46:59 PM PST 24
Peak memory 214120 kb
Host smart-46407f88-2478-4410-89a9-cc5db7ba8a7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748842014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.748842014
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1181191374
Short name T415
Test name
Test status
Simulation time 212032399 ps
CPU time 1.62 seconds
Started Feb 04 12:46:50 PM PST 24
Finished Feb 04 12:46:56 PM PST 24
Peak memory 205736 kb
Host smart-9e178665-a5bb-40e7-b0d6-9f06d9c54d8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181191374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1181191374
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.924050813
Short name T410
Test name
Test status
Simulation time 25805579 ps
CPU time 0.85 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:47:10 PM PST 24
Peak memory 205904 kb
Host smart-43302f63-cfc4-4fb8-bd2c-6a41fbf1cc49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924050813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.924050813
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.4166938274
Short name T393
Test name
Test status
Simulation time 12856563 ps
CPU time 0.85 seconds
Started Feb 04 12:47:06 PM PST 24
Finished Feb 04 12:47:09 PM PST 24
Peak memory 205672 kb
Host smart-624e8749-a568-43f5-9a9a-34e64f16ddc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166938274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.4166938274
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3577805084
Short name T361
Test name
Test status
Simulation time 19136875 ps
CPU time 0.85 seconds
Started Feb 04 12:47:01 PM PST 24
Finished Feb 04 12:47:03 PM PST 24
Peak memory 205612 kb
Host smart-1ac1d4a4-4285-4b55-8813-26ad4c221875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577805084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3577805084
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3814346310
Short name T222
Test name
Test status
Simulation time 44912241 ps
CPU time 0.86 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:47:10 PM PST 24
Peak memory 205636 kb
Host smart-7dd1cf38-c9f2-4c17-8b7b-7b89d58ca29b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814346310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3814346310
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3960337476
Short name T205
Test name
Test status
Simulation time 31428242 ps
CPU time 0.89 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:47:10 PM PST 24
Peak memory 205636 kb
Host smart-60776872-40fa-437f-b466-6eb7c0888b02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960337476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3960337476
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.353940097
Short name T241
Test name
Test status
Simulation time 25476348 ps
CPU time 0.84 seconds
Started Feb 04 12:47:00 PM PST 24
Finished Feb 04 12:47:02 PM PST 24
Peak memory 205664 kb
Host smart-b6ba3850-453c-48d1-9742-ba04036763eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353940097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.353940097
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3381813742
Short name T354
Test name
Test status
Simulation time 18324958 ps
CPU time 0.78 seconds
Started Feb 04 12:47:08 PM PST 24
Finished Feb 04 12:47:12 PM PST 24
Peak memory 205560 kb
Host smart-827a0fdf-fcd8-426e-9417-993d37ff3f87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381813742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3381813742
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.2096628910
Short name T332
Test name
Test status
Simulation time 16047160 ps
CPU time 0.86 seconds
Started Feb 04 12:47:08 PM PST 24
Finished Feb 04 12:47:11 PM PST 24
Peak memory 205584 kb
Host smart-aedd1f58-ff0f-4ae2-9318-a1b91c30dce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096628910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.2096628910
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1393013357
Short name T416
Test name
Test status
Simulation time 18242328 ps
CPU time 0.87 seconds
Started Feb 04 12:47:06 PM PST 24
Finished Feb 04 12:47:09 PM PST 24
Peak memory 205676 kb
Host smart-03add91e-634a-4ea9-9944-6938b73bdcbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393013357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1393013357
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2648383174
Short name T421
Test name
Test status
Simulation time 25587011 ps
CPU time 0.9 seconds
Started Feb 04 12:47:09 PM PST 24
Finished Feb 04 12:47:13 PM PST 24
Peak memory 205688 kb
Host smart-adf011af-a7e0-4a22-b08e-701591e1f29f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648383174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2648383174
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2058218961
Short name T414
Test name
Test status
Simulation time 25636695 ps
CPU time 1.29 seconds
Started Feb 04 12:46:56 PM PST 24
Finished Feb 04 12:47:00 PM PST 24
Peak memory 214068 kb
Host smart-85a9404f-aeb9-4558-9c82-d9d68b1dbf28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058218961 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2058218961
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1791669770
Short name T243
Test name
Test status
Simulation time 11966577 ps
CPU time 0.88 seconds
Started Feb 04 12:46:51 PM PST 24
Finished Feb 04 12:46:55 PM PST 24
Peak memory 205728 kb
Host smart-872712aa-4179-418f-b64b-ba833f107df8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791669770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1791669770
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.899194891
Short name T208
Test name
Test status
Simulation time 14448765 ps
CPU time 0.86 seconds
Started Feb 04 12:46:52 PM PST 24
Finished Feb 04 12:46:56 PM PST 24
Peak memory 205668 kb
Host smart-497fbd9e-683f-4ef2-b4e1-a641d2ca5010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899194891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.899194891
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2302844645
Short name T221
Test name
Test status
Simulation time 69740345 ps
CPU time 1.05 seconds
Started Feb 04 12:46:53 PM PST 24
Finished Feb 04 12:46:58 PM PST 24
Peak memory 205352 kb
Host smart-3b8a2cd1-7787-44d7-82f4-8764b8bb603a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302844645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2302844645
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2946561545
Short name T389
Test name
Test status
Simulation time 117088895 ps
CPU time 1.99 seconds
Started Feb 04 12:46:49 PM PST 24
Finished Feb 04 12:46:54 PM PST 24
Peak memory 214012 kb
Host smart-83d0afcb-2c8d-4356-94c1-2803b32f9fca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946561545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2946561545
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3527310244
Short name T411
Test name
Test status
Simulation time 268722081 ps
CPU time 1.55 seconds
Started Feb 04 12:46:49 PM PST 24
Finished Feb 04 12:46:53 PM PST 24
Peak memory 205804 kb
Host smart-c7d69e6e-3981-4a57-9a6a-0eec86426b5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527310244 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3527310244
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2194851273
Short name T385
Test name
Test status
Simulation time 159239210 ps
CPU time 1.22 seconds
Started Feb 04 12:46:44 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 214084 kb
Host smart-80d52949-3ab1-4c16-a742-342af0cbc177
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194851273 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2194851273
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3235712609
Short name T369
Test name
Test status
Simulation time 13999208 ps
CPU time 0.89 seconds
Started Feb 04 12:46:49 PM PST 24
Finished Feb 04 12:46:52 PM PST 24
Peak memory 205744 kb
Host smart-e157a8ba-aa5d-4ee9-a521-45b7b00d2a70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235712609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3235712609
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1400557369
Short name T330
Test name
Test status
Simulation time 38532236 ps
CPU time 0.8 seconds
Started Feb 04 12:46:57 PM PST 24
Finished Feb 04 12:47:00 PM PST 24
Peak memory 205424 kb
Host smart-d6a76aad-a8d4-402f-bf0b-2fa00008cfc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400557369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1400557369
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.737716491
Short name T339
Test name
Test status
Simulation time 58452175 ps
CPU time 1.01 seconds
Started Feb 04 12:46:52 PM PST 24
Finished Feb 04 12:46:56 PM PST 24
Peak memory 205788 kb
Host smart-b9caf0cb-32c7-461e-ae34-4a3fe46cbf82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737716491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_out
standing.737716491
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2784364627
Short name T335
Test name
Test status
Simulation time 185093981 ps
CPU time 3.68 seconds
Started Feb 04 12:46:56 PM PST 24
Finished Feb 04 12:47:02 PM PST 24
Peak memory 214148 kb
Host smart-1da2e4e5-799f-43a1-8a7a-6960cacca542
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784364627 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2784364627
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.165694606
Short name T257
Test name
Test status
Simulation time 484542671 ps
CPU time 2.75 seconds
Started Feb 04 12:46:56 PM PST 24
Finished Feb 04 12:47:01 PM PST 24
Peak memory 205684 kb
Host smart-8c43f6e5-7c90-440a-9a25-99d72cb023f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165694606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.165694606
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3896231608
Short name T209
Test name
Test status
Simulation time 48589982 ps
CPU time 0.9 seconds
Started Feb 04 12:46:44 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 205776 kb
Host smart-69e8e3a9-022c-4e62-bf65-95cabd4753a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896231608 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3896231608
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3494090358
Short name T215
Test name
Test status
Simulation time 50211856 ps
CPU time 0.86 seconds
Started Feb 04 12:47:05 PM PST 24
Finished Feb 04 12:47:07 PM PST 24
Peak memory 205756 kb
Host smart-6ca11a81-8424-44de-8baf-de371555806d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494090358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3494090358
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3919213226
Short name T48
Test name
Test status
Simulation time 27159154 ps
CPU time 0.98 seconds
Started Feb 04 12:46:46 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 205624 kb
Host smart-d1392624-0d76-4181-833c-f66090f22e08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919213226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3919213226
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.906574711
Short name T195
Test name
Test status
Simulation time 22132802 ps
CPU time 1.13 seconds
Started Feb 04 12:46:46 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 205664 kb
Host smart-b2839dc2-b21b-4e97-8d08-2c9d5c8671e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906574711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.906574711
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1537852555
Short name T399
Test name
Test status
Simulation time 74307499 ps
CPU time 2.87 seconds
Started Feb 04 12:46:58 PM PST 24
Finished Feb 04 12:47:03 PM PST 24
Peak memory 213840 kb
Host smart-14fda61c-4ad7-4433-8dab-ec83e3559507
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537852555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1537852555
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3452165398
Short name T219
Test name
Test status
Simulation time 87431629 ps
CPU time 1.58 seconds
Started Feb 04 12:46:41 PM PST 24
Finished Feb 04 12:46:45 PM PST 24
Peak memory 205740 kb
Host smart-4f65e2df-2009-4bc8-92a7-d86ac06041f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452165398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3452165398
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.3590520489
Short name T377
Test name
Test status
Simulation time 63503117 ps
CPU time 1.51 seconds
Started Feb 04 12:46:47 PM PST 24
Finished Feb 04 12:46:51 PM PST 24
Peak memory 214020 kb
Host smart-15ac13a4-1b65-4d14-ae62-42536022e7f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590520489 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.3590520489
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.1940196866
Short name T232
Test name
Test status
Simulation time 24357876 ps
CPU time 0.87 seconds
Started Feb 04 12:46:48 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 205664 kb
Host smart-9e377ec5-6189-422d-89d1-92b852037ea2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940196866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.1940196866
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.238696735
Short name T366
Test name
Test status
Simulation time 24743066 ps
CPU time 0.82 seconds
Started Feb 04 12:47:05 PM PST 24
Finished Feb 04 12:47:07 PM PST 24
Peak memory 205748 kb
Host smart-40ccb074-8fc7-422d-b605-f2da931972f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238696735 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.238696735
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2156550430
Short name T337
Test name
Test status
Simulation time 33981855 ps
CPU time 0.95 seconds
Started Feb 04 12:47:05 PM PST 24
Finished Feb 04 12:47:08 PM PST 24
Peak memory 205872 kb
Host smart-bf352c03-c202-4be6-93a3-e145b3afecec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156550430 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2156550430
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2093616427
Short name T379
Test name
Test status
Simulation time 162497890 ps
CPU time 2.92 seconds
Started Feb 04 12:47:06 PM PST 24
Finished Feb 04 12:47:11 PM PST 24
Peak memory 214096 kb
Host smart-be76ec06-e693-44b3-984d-0a4a72ebdd3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093616427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2093616427
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3691932084
Short name T378
Test name
Test status
Simulation time 370978644 ps
CPU time 1.57 seconds
Started Feb 04 12:46:53 PM PST 24
Finished Feb 04 12:46:59 PM PST 24
Peak memory 205664 kb
Host smart-2779f12d-9b42-44c5-9aa2-864aeacd4766
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691932084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3691932084
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.3467714426
Short name T191
Test name
Test status
Simulation time 40902320 ps
CPU time 0.89 seconds
Started Feb 04 12:46:51 PM PST 24
Finished Feb 04 12:46:55 PM PST 24
Peak memory 205800 kb
Host smart-0a5a7a8b-4ac7-4449-a715-155acf8bcfb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467714426 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.3467714426
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1818594943
Short name T344
Test name
Test status
Simulation time 147857124 ps
CPU time 0.84 seconds
Started Feb 04 12:46:47 PM PST 24
Finished Feb 04 12:46:50 PM PST 24
Peak memory 205884 kb
Host smart-33349126-ea2d-4561-a1de-1557d456b4c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818594943 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1818594943
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1228821813
Short name T396
Test name
Test status
Simulation time 48237089 ps
CPU time 0.89 seconds
Started Feb 04 12:46:51 PM PST 24
Finished Feb 04 12:46:55 PM PST 24
Peak memory 205664 kb
Host smart-300537a1-8451-4f80-8142-1ab22e736793
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228821813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1228821813
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.4288205505
Short name T240
Test name
Test status
Simulation time 132224090 ps
CPU time 1.09 seconds
Started Feb 04 12:47:07 PM PST 24
Finished Feb 04 12:47:10 PM PST 24
Peak memory 205644 kb
Host smart-f969b640-4104-40f0-bbcb-0cfae0248450
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288205505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.4288205505
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3355461999
Short name T342
Test name
Test status
Simulation time 93301039 ps
CPU time 1.84 seconds
Started Feb 04 12:46:53 PM PST 24
Finished Feb 04 12:46:59 PM PST 24
Peak memory 213628 kb
Host smart-8abf4b91-375d-484c-839f-56d876e074a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355461999 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3355461999
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1900768857
Short name T47
Test name
Test status
Simulation time 83446909 ps
CPU time 1.52 seconds
Started Feb 04 12:47:03 PM PST 24
Finished Feb 04 12:47:05 PM PST 24
Peak memory 205624 kb
Host smart-d9abd4e5-d463-43d8-9e4f-e01e4cb96d62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900768857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1900768857
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.3207589854
Short name T868
Test name
Test status
Simulation time 47914593 ps
CPU time 0.92 seconds
Started Feb 04 04:18:56 PM PST 24
Finished Feb 04 04:18:58 PM PST 24
Peak memory 205828 kb
Host smart-eef025f2-9af4-45ce-bb05-a412330ab51a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207589854 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3207589854
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3704952959
Short name T10
Test name
Test status
Simulation time 22355595 ps
CPU time 1.08 seconds
Started Feb 04 04:18:46 PM PST 24
Finished Feb 04 04:18:48 PM PST 24
Peak memory 215300 kb
Host smart-4184bbb9-cc7e-4bbf-be1d-09b26295d60c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704952959 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3704952959
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.278759104
Short name T577
Test name
Test status
Simulation time 35064843 ps
CPU time 1.07 seconds
Started Feb 04 04:18:46 PM PST 24
Finished Feb 04 04:18:48 PM PST 24
Peak memory 216820 kb
Host smart-096a4155-276d-493c-bc10-71b0f2441376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278759104 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.278759104
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_intr.3215100760
Short name T499
Test name
Test status
Simulation time 33917634 ps
CPU time 0.91 seconds
Started Feb 04 04:18:46 PM PST 24
Finished Feb 04 04:18:48 PM PST 24
Peak memory 215152 kb
Host smart-0c270e2b-f699-4efe-a908-e645a180ae88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215100760 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3215100760
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.3086023299
Short name T285
Test name
Test status
Simulation time 66985860 ps
CPU time 0.9 seconds
Started Feb 04 04:18:42 PM PST 24
Finished Feb 04 04:18:45 PM PST 24
Peak memory 206732 kb
Host smart-dbd006f9-aebd-4028-8112-35ccb03c6b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086023299 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.3086023299
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.308090364
Short name T63
Test name
Test status
Simulation time 439214548 ps
CPU time 7.6 seconds
Started Feb 04 04:18:41 PM PST 24
Finished Feb 04 04:18:52 PM PST 24
Peak memory 234108 kb
Host smart-52e28858-e413-4963-9657-72fd4eae2544
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308090364 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.308090364
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2914946082
Short name T477
Test name
Test status
Simulation time 13074334 ps
CPU time 0.98 seconds
Started Feb 04 04:18:44 PM PST 24
Finished Feb 04 04:18:47 PM PST 24
Peak memory 214976 kb
Host smart-ccf1c45d-be64-43f0-9975-375b3fa355c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914946082 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2914946082
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1671028297
Short name T859
Test name
Test status
Simulation time 62125416 ps
CPU time 1.45 seconds
Started Feb 04 04:18:45 PM PST 24
Finished Feb 04 04:18:48 PM PST 24
Peak memory 215312 kb
Host smart-00402803-13ea-4b88-bcaf-3c6b29400c37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671028297 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1671028297
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.544952611
Short name T549
Test name
Test status
Simulation time 57176252313 ps
CPU time 745.46 seconds
Started Feb 04 04:18:41 PM PST 24
Finished Feb 04 04:31:10 PM PST 24
Peak memory 219596 kb
Host smart-9671f5bc-574d-4fd2-ac4b-e9cc8750157d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544952611 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.544952611
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.2680359591
Short name T460
Test name
Test status
Simulation time 273944753 ps
CPU time 1 seconds
Started Feb 04 04:19:02 PM PST 24
Finished Feb 04 04:19:08 PM PST 24
Peak memory 205336 kb
Host smart-cacb94ff-b754-4d70-82fb-8a221caa6308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680359591 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.2680359591
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_err.211736976
Short name T833
Test name
Test status
Simulation time 31651917 ps
CPU time 0.98 seconds
Started Feb 04 04:19:03 PM PST 24
Finished Feb 04 04:19:09 PM PST 24
Peak memory 216532 kb
Host smart-9a3a65e4-5551-48b4-9bc4-a7bb155df743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211736976 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.211736976
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_regwen.2950573838
Short name T284
Test name
Test status
Simulation time 26769860 ps
CPU time 1.03 seconds
Started Feb 04 04:19:06 PM PST 24
Finished Feb 04 04:19:09 PM PST 24
Peak memory 206740 kb
Host smart-5579ac43-6415-42f8-b9d0-626dfa802d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950573838 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2950573838
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.4245152858
Short name T21
Test name
Test status
Simulation time 2350142301 ps
CPU time 7.03 seconds
Started Feb 04 04:19:06 PM PST 24
Finished Feb 04 04:19:15 PM PST 24
Peak memory 234236 kb
Host smart-b9eeae2a-4eaf-4a1a-aebd-a77292852a98
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245152858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.4245152858
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1917656649
Short name T429
Test name
Test status
Simulation time 36101039 ps
CPU time 0.95 seconds
Started Feb 04 04:18:57 PM PST 24
Finished Feb 04 04:19:01 PM PST 24
Peak memory 214956 kb
Host smart-7e403944-0dc8-44d6-aa78-4ff43b663244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917656649 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1917656649
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2313532976
Short name T480
Test name
Test status
Simulation time 222213302 ps
CPU time 1.37 seconds
Started Feb 04 04:19:03 PM PST 24
Finished Feb 04 04:19:09 PM PST 24
Peak memory 217888 kb
Host smart-ff6adc88-c0e3-467a-afe5-30bbf741c13e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313532976 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2313532976
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2042492419
Short name T791
Test name
Test status
Simulation time 84179098282 ps
CPU time 1961.65 seconds
Started Feb 04 04:19:09 PM PST 24
Finished Feb 04 04:51:52 PM PST 24
Peak memory 224408 kb
Host smart-c2308138-127b-4125-837c-ff2e800d6f4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042492419 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2042492419
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.2859115416
Short name T837
Test name
Test status
Simulation time 16530596 ps
CPU time 0.92 seconds
Started Feb 04 04:19:47 PM PST 24
Finished Feb 04 04:19:53 PM PST 24
Peak memory 205276 kb
Host smart-c83d484f-c747-4974-820e-a5e33f3ff7c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859115416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2859115416
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1565835395
Short name T609
Test name
Test status
Simulation time 24093359 ps
CPU time 1.12 seconds
Started Feb 04 04:19:49 PM PST 24
Finished Feb 04 04:19:53 PM PST 24
Peak memory 217872 kb
Host smart-73a4d458-2d89-4472-a825-5a9637ca1a39
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565835395 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1565835395
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.1453931944
Short name T163
Test name
Test status
Simulation time 25601229 ps
CPU time 1.02 seconds
Started Feb 04 04:19:45 PM PST 24
Finished Feb 04 04:19:52 PM PST 24
Peak memory 222572 kb
Host smart-f5570d3f-ecb5-4a05-8bdc-8609a281ebe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453931944 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1453931944
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.2197104540
Short name T655
Test name
Test status
Simulation time 69942190 ps
CPU time 1.31 seconds
Started Feb 04 04:19:47 PM PST 24
Finished Feb 04 04:19:53 PM PST 24
Peak memory 215380 kb
Host smart-ad09572e-3505-4817-b05c-f950c863c7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197104540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2197104540
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.578982416
Short name T808
Test name
Test status
Simulation time 28853408 ps
CPU time 0.91 seconds
Started Feb 04 04:19:40 PM PST 24
Finished Feb 04 04:19:45 PM PST 24
Peak memory 215116 kb
Host smart-721e8c9f-d566-44f9-945d-a586bd2af3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578982416 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.578982416
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1452225439
Short name T563
Test name
Test status
Simulation time 13683570 ps
CPU time 1.03 seconds
Started Feb 04 04:19:48 PM PST 24
Finished Feb 04 04:19:53 PM PST 24
Peak memory 214916 kb
Host smart-61a64395-c7ff-4059-ac23-d06ebb3b553a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452225439 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1452225439
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.978672234
Short name T262
Test name
Test status
Simulation time 186152107 ps
CPU time 4.45 seconds
Started Feb 04 04:19:46 PM PST 24
Finished Feb 04 04:19:56 PM PST 24
Peak memory 215420 kb
Host smart-62690545-9d0b-48bf-b08b-4fdc459da27c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978672234 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.978672234
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.52534776
Short name T569
Test name
Test status
Simulation time 681022242837 ps
CPU time 1289.14 seconds
Started Feb 04 04:19:48 PM PST 24
Finished Feb 04 04:41:21 PM PST 24
Peak memory 220432 kb
Host smart-7fa1c35f-ecc9-4dc8-b44a-ea1555c27da1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52534776 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.52534776
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.3683369099
Short name T511
Test name
Test status
Simulation time 69502098 ps
CPU time 2.71 seconds
Started Feb 04 04:23:10 PM PST 24
Finished Feb 04 04:23:14 PM PST 24
Peak memory 215648 kb
Host smart-691e5280-e32a-4201-b6d3-adf2f0294913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683369099 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3683369099
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.74555633
Short name T689
Test name
Test status
Simulation time 229526934 ps
CPU time 1.27 seconds
Started Feb 04 04:23:09 PM PST 24
Finished Feb 04 04:23:12 PM PST 24
Peak memory 216856 kb
Host smart-6d398388-93a4-46b7-a2bd-eb70839780cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74555633 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.74555633
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3248826986
Short name T871
Test name
Test status
Simulation time 50918015 ps
CPU time 1.16 seconds
Started Feb 04 04:23:11 PM PST 24
Finished Feb 04 04:23:13 PM PST 24
Peak memory 215236 kb
Host smart-596a7ccc-d29b-4718-92a8-3925c29397fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248826986 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3248826986
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.2894252156
Short name T913
Test name
Test status
Simulation time 130593852 ps
CPU time 2.54 seconds
Started Feb 04 04:23:19 PM PST 24
Finished Feb 04 04:23:23 PM PST 24
Peak memory 218288 kb
Host smart-5b66f71f-72e4-4bbf-9618-973623a06de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894252156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.2894252156
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.2117392938
Short name T592
Test name
Test status
Simulation time 58987152 ps
CPU time 1.09 seconds
Started Feb 04 04:23:19 PM PST 24
Finished Feb 04 04:23:21 PM PST 24
Peak memory 215460 kb
Host smart-a80f7207-de14-4c85-af1f-00edb7011bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117392938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2117392938
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.2523140210
Short name T271
Test name
Test status
Simulation time 18632225 ps
CPU time 1.12 seconds
Started Feb 04 04:23:14 PM PST 24
Finished Feb 04 04:23:16 PM PST 24
Peak memory 215504 kb
Host smart-ab0e1b75-c9f4-46c2-9d01-706a5b22c001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523140210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.2523140210
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.838432101
Short name T916
Test name
Test status
Simulation time 321068644 ps
CPU time 2.26 seconds
Started Feb 04 04:23:16 PM PST 24
Finished Feb 04 04:23:19 PM PST 24
Peak memory 216796 kb
Host smart-dcbc2519-f082-494b-a90a-78beffe3d72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838432101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.838432101
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.1593278250
Short name T167
Test name
Test status
Simulation time 68630759 ps
CPU time 1.13 seconds
Started Feb 04 04:23:16 PM PST 24
Finished Feb 04 04:23:18 PM PST 24
Peak memory 214956 kb
Host smart-80fbb0ae-ed7b-412d-81e9-4c956e10794b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593278250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1593278250
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.1426432057
Short name T770
Test name
Test status
Simulation time 23666103 ps
CPU time 1.01 seconds
Started Feb 04 04:23:21 PM PST 24
Finished Feb 04 04:23:23 PM PST 24
Peak memory 215128 kb
Host smart-8411fac8-7ae4-4500-8605-dd166b881d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426432057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1426432057
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.876368864
Short name T294
Test name
Test status
Simulation time 31360634 ps
CPU time 0.99 seconds
Started Feb 04 04:20:05 PM PST 24
Finished Feb 04 04:20:10 PM PST 24
Peak memory 206004 kb
Host smart-bd085017-c791-414a-aaa8-18d0d2615ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876368864 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.876368864
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.68876305
Short name T714
Test name
Test status
Simulation time 19722718 ps
CPU time 0.83 seconds
Started Feb 04 04:20:11 PM PST 24
Finished Feb 04 04:20:14 PM PST 24
Peak memory 205044 kb
Host smart-25b9222e-eee1-410e-9527-eaa21cba7db5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68876305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.68876305
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.612295622
Short name T171
Test name
Test status
Simulation time 20734211 ps
CPU time 0.93 seconds
Started Feb 04 04:20:02 PM PST 24
Finished Feb 04 04:20:04 PM PST 24
Peak memory 215060 kb
Host smart-61cc08f2-b9e2-4af6-9059-04d2743c635d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612295622 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.612295622
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.3769606462
Short name T863
Test name
Test status
Simulation time 55705940 ps
CPU time 1.08 seconds
Started Feb 04 04:19:58 PM PST 24
Finished Feb 04 04:20:00 PM PST 24
Peak memory 216752 kb
Host smart-23c7764a-3377-4ec8-9caa-1dccca5ba985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769606462 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3769606462
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1216510251
Short name T647
Test name
Test status
Simulation time 271151822 ps
CPU time 1.12 seconds
Started Feb 04 04:19:45 PM PST 24
Finished Feb 04 04:19:52 PM PST 24
Peak memory 215240 kb
Host smart-baae9c43-7b81-497f-8fbc-9f8deced7afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216510251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1216510251
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.2047165428
Short name T671
Test name
Test status
Simulation time 20284415 ps
CPU time 0.92 seconds
Started Feb 04 04:19:47 PM PST 24
Finished Feb 04 04:19:53 PM PST 24
Peak memory 214916 kb
Host smart-d19133ab-b59b-47e4-b847-fb3516a2f40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047165428 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2047165428
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.155019423
Short name T502
Test name
Test status
Simulation time 2261293160 ps
CPU time 4.9 seconds
Started Feb 04 04:19:47 PM PST 24
Finished Feb 04 04:19:57 PM PST 24
Peak memory 218252 kb
Host smart-19660412-0e47-454e-8101-b430717efdb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155019423 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.155019423
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.908289152
Short name T543
Test name
Test status
Simulation time 343396248744 ps
CPU time 1013.74 seconds
Started Feb 04 04:19:59 PM PST 24
Finished Feb 04 04:36:53 PM PST 24
Peak memory 223448 kb
Host smart-fa6a16e0-67b2-4976-837d-b5543a98ca8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908289152 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.908289152
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.edn_genbits.4247634718
Short name T783
Test name
Test status
Simulation time 56058429 ps
CPU time 1.09 seconds
Started Feb 04 04:23:19 PM PST 24
Finished Feb 04 04:23:21 PM PST 24
Peak memory 216676 kb
Host smart-c4fcf300-5798-4bf0-95c9-db8759a84e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247634718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.4247634718
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.1644260073
Short name T715
Test name
Test status
Simulation time 55751237 ps
CPU time 1.18 seconds
Started Feb 04 04:23:17 PM PST 24
Finished Feb 04 04:23:19 PM PST 24
Peak memory 216804 kb
Host smart-1528cd2c-d7dd-489f-b3bd-697750b96913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644260073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1644260073
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.1944966573
Short name T457
Test name
Test status
Simulation time 41943652 ps
CPU time 1.03 seconds
Started Feb 04 04:23:17 PM PST 24
Finished Feb 04 04:23:19 PM PST 24
Peak memory 214972 kb
Host smart-e5863c03-4a66-45ad-849e-2b2c4bd2448f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944966573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.1944966573
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.606514278
Short name T550
Test name
Test status
Simulation time 27177617 ps
CPU time 1.4 seconds
Started Feb 04 04:23:18 PM PST 24
Finished Feb 04 04:23:20 PM PST 24
Peak memory 215460 kb
Host smart-74a5c679-0ce3-4f92-a0db-4150838a067c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606514278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.606514278
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.832436697
Short name T921
Test name
Test status
Simulation time 71874090 ps
CPU time 1.1 seconds
Started Feb 04 04:23:19 PM PST 24
Finished Feb 04 04:23:21 PM PST 24
Peak memory 216752 kb
Host smart-c58172d8-1e8a-4fae-9a6b-f8868eb9e0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832436697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.832436697
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.3884070424
Short name T69
Test name
Test status
Simulation time 45719321 ps
CPU time 2.05 seconds
Started Feb 04 04:23:18 PM PST 24
Finished Feb 04 04:23:21 PM PST 24
Peak memory 218120 kb
Host smart-4ef738ea-c543-4d45-8e2d-ea8207f76a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884070424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3884070424
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.4206311451
Short name T738
Test name
Test status
Simulation time 37266570 ps
CPU time 1.56 seconds
Started Feb 04 04:23:18 PM PST 24
Finished Feb 04 04:23:20 PM PST 24
Peak memory 216756 kb
Host smart-03c1c08a-7863-4c66-850b-f0465d85c3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206311451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.4206311451
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.620403675
Short name T437
Test name
Test status
Simulation time 43226153 ps
CPU time 1 seconds
Started Feb 04 04:23:17 PM PST 24
Finished Feb 04 04:23:19 PM PST 24
Peak memory 215208 kb
Host smart-a427a1f6-3058-4dfd-b41a-1b1086012387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620403675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.620403675
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2976532452
Short name T248
Test name
Test status
Simulation time 19098842 ps
CPU time 1.07 seconds
Started Feb 04 04:20:05 PM PST 24
Finished Feb 04 04:20:09 PM PST 24
Peak memory 206632 kb
Host smart-609e6f2f-9da2-4dc7-9998-171559314ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976532452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2976532452
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3614043447
Short name T796
Test name
Test status
Simulation time 29783931 ps
CPU time 1.24 seconds
Started Feb 04 04:20:01 PM PST 24
Finished Feb 04 04:20:04 PM PST 24
Peak memory 205384 kb
Host smart-35f010df-9e32-4f18-b464-b84e3449fcb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614043447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3614043447
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_err.884698154
Short name T843
Test name
Test status
Simulation time 34904286 ps
CPU time 0.94 seconds
Started Feb 04 04:20:04 PM PST 24
Finished Feb 04 04:20:08 PM PST 24
Peak memory 215188 kb
Host smart-39b23a6e-b1ae-463f-8fd4-650dbf53558a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884698154 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.884698154
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.1500856033
Short name T541
Test name
Test status
Simulation time 40228468 ps
CPU time 1.22 seconds
Started Feb 04 04:20:05 PM PST 24
Finished Feb 04 04:20:11 PM PST 24
Peak memory 215552 kb
Host smart-38f17632-ca85-4e3a-8049-2dc3eb6c3f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500856033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.1500856033
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3748862936
Short name T75
Test name
Test status
Simulation time 18256701 ps
CPU time 1.08 seconds
Started Feb 04 04:20:05 PM PST 24
Finished Feb 04 04:20:10 PM PST 24
Peak memory 215364 kb
Host smart-65e2313e-a336-4310-90eb-9731f6a100e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748862936 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3748862936
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2153343624
Short name T538
Test name
Test status
Simulation time 48349886 ps
CPU time 0.95 seconds
Started Feb 04 04:20:04 PM PST 24
Finished Feb 04 04:20:06 PM PST 24
Peak memory 214968 kb
Host smart-584655b0-a357-4edc-bfc9-f0075f1cd432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153343624 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2153343624
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1969803573
Short name T778
Test name
Test status
Simulation time 88426740 ps
CPU time 2.37 seconds
Started Feb 04 04:20:03 PM PST 24
Finished Feb 04 04:20:07 PM PST 24
Peak memory 215380 kb
Host smart-fbe313e5-a510-4687-8a34-e4c2863113ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969803573 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1969803573
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.934359136
Short name T836
Test name
Test status
Simulation time 156908647188 ps
CPU time 1099.13 seconds
Started Feb 04 04:19:58 PM PST 24
Finished Feb 04 04:38:18 PM PST 24
Peak memory 220792 kb
Host smart-d9cc7d0a-20b3-4ccf-ba57-bdd6338b1bcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934359136 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.934359136
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.2848104241
Short name T517
Test name
Test status
Simulation time 52935754 ps
CPU time 1.22 seconds
Started Feb 04 04:23:26 PM PST 24
Finished Feb 04 04:23:28 PM PST 24
Peak memory 216708 kb
Host smart-2df5f9f6-6930-41f2-becb-734dbf95d35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848104241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2848104241
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.658845270
Short name T180
Test name
Test status
Simulation time 18938968 ps
CPU time 1.14 seconds
Started Feb 04 04:23:28 PM PST 24
Finished Feb 04 04:23:30 PM PST 24
Peak memory 215076 kb
Host smart-fe7e57da-823b-4e3f-aaea-873725bd04ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658845270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.658845270
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2197588337
Short name T479
Test name
Test status
Simulation time 184161092 ps
CPU time 1.2 seconds
Started Feb 04 04:23:22 PM PST 24
Finished Feb 04 04:23:24 PM PST 24
Peak memory 215388 kb
Host smart-a79d17d8-68fd-4666-90c9-f9986a9f354a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197588337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2197588337
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.3188465551
Short name T562
Test name
Test status
Simulation time 61648841 ps
CPU time 1.01 seconds
Started Feb 04 04:23:29 PM PST 24
Finished Feb 04 04:23:31 PM PST 24
Peak memory 216780 kb
Host smart-9e8afbd2-5512-423f-a8a5-27fd4fec1b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188465551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3188465551
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.3020302842
Short name T649
Test name
Test status
Simulation time 52746761 ps
CPU time 0.96 seconds
Started Feb 04 04:23:21 PM PST 24
Finished Feb 04 04:23:23 PM PST 24
Peak memory 215272 kb
Host smart-9df662d1-1a20-45e0-974c-e82b261ec1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020302842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3020302842
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.2160256235
Short name T935
Test name
Test status
Simulation time 24323657 ps
CPU time 1 seconds
Started Feb 04 04:23:27 PM PST 24
Finished Feb 04 04:23:30 PM PST 24
Peak memory 215452 kb
Host smart-cb99eb5a-f57e-41e8-b3ce-0224d8531bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160256235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.2160256235
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.901938489
Short name T41
Test name
Test status
Simulation time 78185971 ps
CPU time 1.21 seconds
Started Feb 04 04:23:20 PM PST 24
Finished Feb 04 04:23:22 PM PST 24
Peak memory 216760 kb
Host smart-8307b576-32ca-4fc0-be11-c5d44acae208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901938489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.901938489
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.2580989381
Short name T187
Test name
Test status
Simulation time 15759699 ps
CPU time 1.05 seconds
Started Feb 04 04:23:20 PM PST 24
Finished Feb 04 04:23:22 PM PST 24
Peak memory 214976 kb
Host smart-524876fb-03fd-428f-bc20-c724b3d9de4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580989381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.2580989381
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.3991906190
Short name T587
Test name
Test status
Simulation time 78881081 ps
CPU time 1.05 seconds
Started Feb 04 04:23:24 PM PST 24
Finished Feb 04 04:23:27 PM PST 24
Peak memory 216688 kb
Host smart-e21a77f8-ce45-4aed-bebd-c920fe0d776c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991906190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3991906190
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.4232484232
Short name T478
Test name
Test status
Simulation time 22124725 ps
CPU time 1.11 seconds
Started Feb 04 04:20:00 PM PST 24
Finished Feb 04 04:20:02 PM PST 24
Peak memory 206688 kb
Host smart-b2c5f1bf-c6be-4aae-b540-8cf182bd78d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232484232 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.4232484232
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1560215796
Short name T678
Test name
Test status
Simulation time 23821930 ps
CPU time 1.14 seconds
Started Feb 04 04:20:05 PM PST 24
Finished Feb 04 04:20:09 PM PST 24
Peak memory 215172 kb
Host smart-ef7f3b17-6604-4eaf-9ccb-166c4ff9f410
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560215796 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1560215796
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_genbits.2043661205
Short name T275
Test name
Test status
Simulation time 40153130 ps
CPU time 1.06 seconds
Started Feb 04 04:20:00 PM PST 24
Finished Feb 04 04:20:02 PM PST 24
Peak memory 215256 kb
Host smart-98861949-5a49-4002-b515-fbfc65fbfcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043661205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2043661205
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.882719246
Short name T456
Test name
Test status
Simulation time 59748082 ps
CPU time 0.97 seconds
Started Feb 04 04:20:04 PM PST 24
Finished Feb 04 04:20:07 PM PST 24
Peak memory 214924 kb
Host smart-ca98c773-0fe6-4aaa-8eb9-bf53b2fb3e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882719246 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.882719246
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1520814358
Short name T67
Test name
Test status
Simulation time 222593110 ps
CPU time 4.75 seconds
Started Feb 04 04:20:11 PM PST 24
Finished Feb 04 04:20:18 PM PST 24
Peak memory 215356 kb
Host smart-fb0156bc-96a1-4d68-805b-f91a230700b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520814358 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1520814358
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2670247192
Short name T865
Test name
Test status
Simulation time 28579358946 ps
CPU time 331.99 seconds
Started Feb 04 04:20:01 PM PST 24
Finished Feb 04 04:25:34 PM PST 24
Peak memory 219220 kb
Host smart-4774a8ae-db44-4cd5-bb89-9e11a97e80fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670247192 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2670247192
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.836962258
Short name T926
Test name
Test status
Simulation time 20587388 ps
CPU time 1.21 seconds
Started Feb 04 04:23:21 PM PST 24
Finished Feb 04 04:23:23 PM PST 24
Peak memory 215608 kb
Host smart-68ed23ab-e5b8-40bd-bf72-27e66cfd48a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836962258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.836962258
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.1621558129
Short name T328
Test name
Test status
Simulation time 58696559 ps
CPU time 1.2 seconds
Started Feb 04 04:23:21 PM PST 24
Finished Feb 04 04:23:23 PM PST 24
Peak memory 215520 kb
Host smart-3f18e687-1bbe-4714-8d4d-6ee29a9e5f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621558129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1621558129
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1654465955
Short name T604
Test name
Test status
Simulation time 17907572 ps
CPU time 1.06 seconds
Started Feb 04 04:23:22 PM PST 24
Finished Feb 04 04:23:25 PM PST 24
Peak memory 215376 kb
Host smart-82a72c07-2ec8-40fb-83bf-6a8e51148c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654465955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1654465955
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3983964484
Short name T703
Test name
Test status
Simulation time 48817280 ps
CPU time 1.99 seconds
Started Feb 04 04:23:28 PM PST 24
Finished Feb 04 04:23:31 PM PST 24
Peak memory 218068 kb
Host smart-befd2f50-e602-4c3b-ae29-51408015a7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983964484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3983964484
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.888267324
Short name T754
Test name
Test status
Simulation time 38675564 ps
CPU time 1.15 seconds
Started Feb 04 04:23:28 PM PST 24
Finished Feb 04 04:23:30 PM PST 24
Peak memory 215592 kb
Host smart-61a8a7fb-62af-4a3b-8a07-244e4f317617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888267324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.888267324
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.1551912341
Short name T627
Test name
Test status
Simulation time 112931770 ps
CPU time 1.09 seconds
Started Feb 04 04:23:27 PM PST 24
Finished Feb 04 04:23:29 PM PST 24
Peak memory 215344 kb
Host smart-d6c3946e-84d1-4d09-97cf-18ac56fc4114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551912341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1551912341
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1382016023
Short name T594
Test name
Test status
Simulation time 53313334 ps
CPU time 1.11 seconds
Started Feb 04 04:23:26 PM PST 24
Finished Feb 04 04:23:29 PM PST 24
Peak memory 216768 kb
Host smart-099bac91-0d93-48e4-9e8b-eb0083704312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382016023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1382016023
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.61357445
Short name T849
Test name
Test status
Simulation time 19855631 ps
CPU time 1.08 seconds
Started Feb 04 04:23:27 PM PST 24
Finished Feb 04 04:23:29 PM PST 24
Peak memory 215412 kb
Host smart-a00fbcf2-9756-426e-a29f-a8ffd93283eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61357445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.61357445
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.1771256818
Short name T442
Test name
Test status
Simulation time 30499452 ps
CPU time 1.01 seconds
Started Feb 04 04:23:27 PM PST 24
Finished Feb 04 04:23:30 PM PST 24
Peak memory 214896 kb
Host smart-68509b91-7c7e-4f44-ab7b-327bf6f8a97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771256818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1771256818
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.2852985928
Short name T623
Test name
Test status
Simulation time 19597040 ps
CPU time 0.96 seconds
Started Feb 04 04:20:11 PM PST 24
Finished Feb 04 04:20:14 PM PST 24
Peak memory 206572 kb
Host smart-56f3ecad-cbb9-4e2a-92b2-780a8baa29eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852985928 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2852985928
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1224903324
Short name T800
Test name
Test status
Simulation time 40447014 ps
CPU time 0.85 seconds
Started Feb 04 04:20:06 PM PST 24
Finished Feb 04 04:20:10 PM PST 24
Peak memory 205692 kb
Host smart-da11440c-daf4-43e7-ab1c-8534ed204ce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224903324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1224903324
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.899699645
Short name T513
Test name
Test status
Simulation time 149415564 ps
CPU time 0.86 seconds
Started Feb 04 04:20:05 PM PST 24
Finished Feb 04 04:20:08 PM PST 24
Peak memory 215028 kb
Host smart-7cbf0e76-59d6-4a27-901c-ace817966de4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899699645 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.899699645
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2827959802
Short name T104
Test name
Test status
Simulation time 28240830 ps
CPU time 1.1 seconds
Started Feb 04 04:20:04 PM PST 24
Finished Feb 04 04:20:07 PM PST 24
Peak memory 215260 kb
Host smart-58825ec8-6e6e-4ad5-b423-2818a7014a86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827959802 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2827959802
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.679895524
Short name T681
Test name
Test status
Simulation time 22248605 ps
CPU time 1.04 seconds
Started Feb 04 04:20:01 PM PST 24
Finished Feb 04 04:20:03 PM PST 24
Peak memory 216432 kb
Host smart-e6ae1beb-3bc9-4933-ba43-4360f22e4e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679895524 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.679895524
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.945253907
Short name T458
Test name
Test status
Simulation time 87443465 ps
CPU time 1.25 seconds
Started Feb 04 04:19:58 PM PST 24
Finished Feb 04 04:20:00 PM PST 24
Peak memory 216636 kb
Host smart-7d774d77-8978-4811-b3af-b7dc165cfe76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945253907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.945253907
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3784599242
Short name T487
Test name
Test status
Simulation time 19257097 ps
CPU time 1.14 seconds
Started Feb 04 04:19:59 PM PST 24
Finished Feb 04 04:20:02 PM PST 24
Peak memory 215240 kb
Host smart-b8edaa41-4a0f-4613-a489-156ecc245de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784599242 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3784599242
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.4027245682
Short name T474
Test name
Test status
Simulation time 20815992 ps
CPU time 0.93 seconds
Started Feb 04 04:20:00 PM PST 24
Finished Feb 04 04:20:02 PM PST 24
Peak memory 214932 kb
Host smart-d8c969c4-bb80-4d3e-a5e0-4dec4e3d4c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027245682 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.4027245682
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2889642806
Short name T641
Test name
Test status
Simulation time 410070434 ps
CPU time 2.73 seconds
Started Feb 04 04:20:04 PM PST 24
Finished Feb 04 04:20:08 PM PST 24
Peak memory 214972 kb
Host smart-dd0ba96c-87e0-416b-9044-ed850f22289b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889642806 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2889642806
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/140.edn_genbits.4122116552
Short name T553
Test name
Test status
Simulation time 21369885 ps
CPU time 1.14 seconds
Started Feb 04 04:23:27 PM PST 24
Finished Feb 04 04:23:29 PM PST 24
Peak memory 216660 kb
Host smart-34e66606-9f6d-4cc8-9fb7-69d99fa07435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122116552 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.4122116552
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.779238532
Short name T742
Test name
Test status
Simulation time 145635959 ps
CPU time 2.43 seconds
Started Feb 04 04:23:23 PM PST 24
Finished Feb 04 04:23:26 PM PST 24
Peak memory 218060 kb
Host smart-3c425791-d609-40db-8fce-758685cc7990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779238532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.779238532
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.94566575
Short name T728
Test name
Test status
Simulation time 60163346 ps
CPU time 1.11 seconds
Started Feb 04 04:23:31 PM PST 24
Finished Feb 04 04:23:38 PM PST 24
Peak memory 215540 kb
Host smart-abac50ce-ba2e-4430-aa54-3a4b35e3af61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94566575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.94566575
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.2025388765
Short name T277
Test name
Test status
Simulation time 17225570 ps
CPU time 1.13 seconds
Started Feb 04 04:23:30 PM PST 24
Finished Feb 04 04:23:38 PM PST 24
Peak memory 215436 kb
Host smart-d66d7f7a-c50b-4943-9e74-366f5f459b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025388765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2025388765
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.4246372948
Short name T568
Test name
Test status
Simulation time 80876422 ps
CPU time 1.24 seconds
Started Feb 04 04:23:27 PM PST 24
Finished Feb 04 04:23:29 PM PST 24
Peak memory 217524 kb
Host smart-202936e8-9386-4236-aa42-34affedf7b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246372948 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.4246372948
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.1541209196
Short name T488
Test name
Test status
Simulation time 19593619 ps
CPU time 1.19 seconds
Started Feb 04 04:23:28 PM PST 24
Finished Feb 04 04:23:31 PM PST 24
Peak memory 215292 kb
Host smart-660f98dd-92f2-4743-8275-257666f8e438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541209196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1541209196
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.3209301808
Short name T607
Test name
Test status
Simulation time 20609856 ps
CPU time 1.12 seconds
Started Feb 04 04:23:27 PM PST 24
Finished Feb 04 04:23:30 PM PST 24
Peak memory 215076 kb
Host smart-db4e1633-2cbc-4784-b384-5418b64a1581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209301808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.3209301808
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.2273525629
Short name T906
Test name
Test status
Simulation time 18076928 ps
CPU time 1.18 seconds
Started Feb 04 04:23:27 PM PST 24
Finished Feb 04 04:23:29 PM PST 24
Peak memory 216680 kb
Host smart-82ea168b-4584-4582-a6fe-c7665812de8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273525629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2273525629
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.4268979743
Short name T663
Test name
Test status
Simulation time 238998371 ps
CPU time 1.33 seconds
Started Feb 04 04:23:29 PM PST 24
Finished Feb 04 04:23:31 PM PST 24
Peak memory 216668 kb
Host smart-f1f82eab-75f1-4506-8146-ebe4084f26da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268979743 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.4268979743
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.273053610
Short name T323
Test name
Test status
Simulation time 22344658 ps
CPU time 1.47 seconds
Started Feb 04 04:23:29 PM PST 24
Finished Feb 04 04:23:36 PM PST 24
Peak memory 215428 kb
Host smart-2c946d43-468b-47fb-ba26-7d1217aef6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273053610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.273053610
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3874627075
Short name T465
Test name
Test status
Simulation time 68766553 ps
CPU time 0.99 seconds
Started Feb 04 04:20:06 PM PST 24
Finished Feb 04 04:20:11 PM PST 24
Peak memory 206032 kb
Host smart-eb7c477e-5843-4ca7-be32-cf64189119b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874627075 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3874627075
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2014080862
Short name T672
Test name
Test status
Simulation time 19716457 ps
CPU time 0.97 seconds
Started Feb 04 04:20:23 PM PST 24
Finished Feb 04 04:20:27 PM PST 24
Peak memory 205860 kb
Host smart-1ebf4386-c2c5-420a-80ed-dd9669b36f06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014080862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2014080862
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.2965398706
Short name T561
Test name
Test status
Simulation time 117618874 ps
CPU time 0.89 seconds
Started Feb 04 04:20:18 PM PST 24
Finished Feb 04 04:20:20 PM PST 24
Peak memory 214980 kb
Host smart-49e1e433-f2aa-4c9d-ab53-4c3aaa4c53bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965398706 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2965398706
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3481861946
Short name T644
Test name
Test status
Simulation time 108339333 ps
CPU time 1.01 seconds
Started Feb 04 04:20:20 PM PST 24
Finished Feb 04 04:20:23 PM PST 24
Peak memory 215260 kb
Host smart-f769cb13-e037-4104-a9ba-8af09de01559
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481861946 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3481861946
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2928750012
Short name T98
Test name
Test status
Simulation time 25471713 ps
CPU time 1.26 seconds
Started Feb 04 04:20:11 PM PST 24
Finished Feb 04 04:20:15 PM PST 24
Peak memory 222644 kb
Host smart-0396cfd8-c07f-4d10-bd38-55851716b96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928750012 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2928750012
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3361948573
Short name T680
Test name
Test status
Simulation time 36580235 ps
CPU time 1.26 seconds
Started Feb 04 04:20:06 PM PST 24
Finished Feb 04 04:20:12 PM PST 24
Peak memory 216412 kb
Host smart-6a45f724-53ee-4eef-b51e-65b41cf88c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361948573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3361948573
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.1171420491
Short name T2
Test name
Test status
Simulation time 19502660 ps
CPU time 1.06 seconds
Started Feb 04 04:20:06 PM PST 24
Finished Feb 04 04:20:11 PM PST 24
Peak memory 215208 kb
Host smart-857fa219-93c6-4b64-b5dc-844640d94f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171420491 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.1171420491
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.656586377
Short name T775
Test name
Test status
Simulation time 22108950 ps
CPU time 0.87 seconds
Started Feb 04 04:20:06 PM PST 24
Finished Feb 04 04:20:11 PM PST 24
Peak memory 214948 kb
Host smart-f5973280-9a49-4d11-bebc-efaef86edba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656586377 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.656586377
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.2757442284
Short name T924
Test name
Test status
Simulation time 94457102 ps
CPU time 2.51 seconds
Started Feb 04 04:20:05 PM PST 24
Finished Feb 04 04:20:12 PM PST 24
Peak memory 218208 kb
Host smart-68e93d79-aaa4-4dc7-89f0-e3137b542c8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757442284 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.2757442284
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2383602967
Short name T638
Test name
Test status
Simulation time 16524349010 ps
CPU time 375.71 seconds
Started Feb 04 04:20:06 PM PST 24
Finished Feb 04 04:26:26 PM PST 24
Peak memory 220372 kb
Host smart-153263f5-bdd4-4339-921c-4ba116778de6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383602967 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2383602967
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.157590263
Short name T475
Test name
Test status
Simulation time 20305187 ps
CPU time 1.18 seconds
Started Feb 04 04:23:31 PM PST 24
Finished Feb 04 04:23:38 PM PST 24
Peak memory 215484 kb
Host smart-8271445f-7ac1-4296-b316-d02be02352db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157590263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.157590263
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.1325340854
Short name T530
Test name
Test status
Simulation time 45693201 ps
CPU time 1.25 seconds
Started Feb 04 04:23:33 PM PST 24
Finished Feb 04 04:23:38 PM PST 24
Peak memory 215208 kb
Host smart-ca6a2ce8-2904-499e-9945-de407fcf0d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325340854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.1325340854
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.2420124380
Short name T670
Test name
Test status
Simulation time 71534315 ps
CPU time 1.14 seconds
Started Feb 04 04:23:32 PM PST 24
Finished Feb 04 04:23:38 PM PST 24
Peak memory 215340 kb
Host smart-6de00b8d-69b1-4105-84cc-558be5c2ff0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420124380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2420124380
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.1516984824
Short name T928
Test name
Test status
Simulation time 154138803 ps
CPU time 2.07 seconds
Started Feb 04 04:23:29 PM PST 24
Finished Feb 04 04:23:37 PM PST 24
Peak memory 215560 kb
Host smart-f55c8e01-85eb-4cc6-aad3-17d573224cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516984824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1516984824
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.578620616
Short name T299
Test name
Test status
Simulation time 211088492 ps
CPU time 3.16 seconds
Started Feb 04 04:23:31 PM PST 24
Finished Feb 04 04:23:40 PM PST 24
Peak memory 216792 kb
Host smart-a82cd712-4414-4c32-80a3-36db301747a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578620616 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.578620616
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.170279222
Short name T932
Test name
Test status
Simulation time 17203772 ps
CPU time 1.23 seconds
Started Feb 04 04:23:29 PM PST 24
Finished Feb 04 04:23:31 PM PST 24
Peak memory 215352 kb
Host smart-f0788e89-28a9-46ce-b87a-857ac3e00fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170279222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.170279222
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.2923438859
Short name T855
Test name
Test status
Simulation time 16658884 ps
CPU time 1.09 seconds
Started Feb 04 04:23:30 PM PST 24
Finished Feb 04 04:23:38 PM PST 24
Peak memory 215140 kb
Host smart-d0021761-2260-430d-9b4f-cedf84db3441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923438859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2923438859
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.1440885651
Short name T964
Test name
Test status
Simulation time 117829643 ps
CPU time 1.04 seconds
Started Feb 04 04:23:35 PM PST 24
Finished Feb 04 04:23:39 PM PST 24
Peak memory 215440 kb
Host smart-330790f1-e64a-4538-a43f-4561a3663e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440885651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1440885651
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.1543057375
Short name T650
Test name
Test status
Simulation time 83766943 ps
CPU time 1.2 seconds
Started Feb 04 04:23:31 PM PST 24
Finished Feb 04 04:23:38 PM PST 24
Peak memory 215552 kb
Host smart-4fa5e670-af63-43aa-9ccd-e50285db78bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543057375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.1543057375
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.263290435
Short name T251
Test name
Test status
Simulation time 16777876 ps
CPU time 1.02 seconds
Started Feb 04 04:20:19 PM PST 24
Finished Feb 04 04:20:21 PM PST 24
Peak memory 206672 kb
Host smart-b8e4f36e-aedb-4a1c-8c85-4c0510e549f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263290435 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.263290435
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1708896104
Short name T708
Test name
Test status
Simulation time 52605463 ps
CPU time 0.9 seconds
Started Feb 04 04:20:20 PM PST 24
Finished Feb 04 04:20:23 PM PST 24
Peak memory 205852 kb
Host smart-d4f9b923-101c-4c7c-8c64-156da07f908d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708896104 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1708896104
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_err.1686089341
Short name T137
Test name
Test status
Simulation time 18309489 ps
CPU time 1.08 seconds
Started Feb 04 04:20:17 PM PST 24
Finished Feb 04 04:20:21 PM PST 24
Peak memory 216904 kb
Host smart-457503bf-ecd1-4bc0-ab17-45db72704244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686089341 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1686089341
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.3031453921
Short name T316
Test name
Test status
Simulation time 32788015 ps
CPU time 1.21 seconds
Started Feb 04 04:20:21 PM PST 24
Finished Feb 04 04:20:25 PM PST 24
Peak memory 215120 kb
Host smart-5006f4bb-3050-4738-a8f8-79deb4a71c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031453921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3031453921
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.130386448
Short name T757
Test name
Test status
Simulation time 18713431 ps
CPU time 1.13 seconds
Started Feb 04 04:20:19 PM PST 24
Finished Feb 04 04:20:22 PM PST 24
Peak memory 215152 kb
Host smart-ebffb6ae-4505-45f2-928d-1e7dabb83739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130386448 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.130386448
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.3224384897
Short name T603
Test name
Test status
Simulation time 26754918 ps
CPU time 0.96 seconds
Started Feb 04 04:20:17 PM PST 24
Finished Feb 04 04:20:20 PM PST 24
Peak memory 214944 kb
Host smart-37d64194-5607-454d-bc43-8cdc4d82a983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224384897 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.3224384897
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2500345029
Short name T654
Test name
Test status
Simulation time 227342431 ps
CPU time 4.98 seconds
Started Feb 04 04:20:23 PM PST 24
Finished Feb 04 04:20:31 PM PST 24
Peak memory 217928 kb
Host smart-47fee733-6d8a-4939-9a28-5c1a6a121764
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500345029 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2500345029
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2252447709
Short name T851
Test name
Test status
Simulation time 123793899587 ps
CPU time 1550.48 seconds
Started Feb 04 04:20:21 PM PST 24
Finished Feb 04 04:46:15 PM PST 24
Peak memory 225368 kb
Host smart-b533306d-d61b-441b-b71c-07752f122b32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252447709 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2252447709
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.edn_genbits.951820956
Short name T620
Test name
Test status
Simulation time 21694495 ps
CPU time 1.21 seconds
Started Feb 04 04:23:31 PM PST 24
Finished Feb 04 04:23:38 PM PST 24
Peak memory 215500 kb
Host smart-16a80f2a-d412-4133-aa43-4f906743a1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951820956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.951820956
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.219510091
Short name T927
Test name
Test status
Simulation time 58940194 ps
CPU time 0.99 seconds
Started Feb 04 04:23:30 PM PST 24
Finished Feb 04 04:23:37 PM PST 24
Peak memory 215404 kb
Host smart-0079b474-c511-4b15-af41-670a3b919a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219510091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.219510091
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.2005390317
Short name T621
Test name
Test status
Simulation time 25036214 ps
CPU time 1.35 seconds
Started Feb 04 04:23:30 PM PST 24
Finished Feb 04 04:23:38 PM PST 24
Peak memory 215520 kb
Host smart-5ff419fd-ca6e-4e32-ad5a-f18495895ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005390317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2005390317
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.2652321112
Short name T321
Test name
Test status
Simulation time 105697869 ps
CPU time 1.14 seconds
Started Feb 04 04:23:35 PM PST 24
Finished Feb 04 04:23:41 PM PST 24
Peak memory 215336 kb
Host smart-166d7f55-e2e2-4736-8b31-15842e4591be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652321112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2652321112
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.62000635
Short name T764
Test name
Test status
Simulation time 24281834 ps
CPU time 1.18 seconds
Started Feb 04 04:23:33 PM PST 24
Finished Feb 04 04:23:38 PM PST 24
Peak memory 215420 kb
Host smart-a0d2448e-b6cf-4ae6-a9fb-5d667e94f6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62000635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.62000635
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.3977985122
Short name T73
Test name
Test status
Simulation time 20038037 ps
CPU time 1.14 seconds
Started Feb 04 04:23:31 PM PST 24
Finished Feb 04 04:23:38 PM PST 24
Peak memory 215428 kb
Host smart-a444ab80-ee31-413c-963f-07988d44926c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977985122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3977985122
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.3817536528
Short name T601
Test name
Test status
Simulation time 35534837 ps
CPU time 1.13 seconds
Started Feb 04 04:23:29 PM PST 24
Finished Feb 04 04:23:36 PM PST 24
Peak memory 215432 kb
Host smart-57bd8a18-2a5b-45de-9162-f407b36e78ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817536528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3817536528
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.3795048482
Short name T497
Test name
Test status
Simulation time 18221789 ps
CPU time 1.17 seconds
Started Feb 04 04:23:31 PM PST 24
Finished Feb 04 04:23:38 PM PST 24
Peak memory 215212 kb
Host smart-773fe199-b241-471d-833c-29911dd7e836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795048482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.3795048482
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.3315949113
Short name T706
Test name
Test status
Simulation time 33761360 ps
CPU time 1.09 seconds
Started Feb 04 04:23:35 PM PST 24
Finished Feb 04 04:23:40 PM PST 24
Peak memory 216548 kb
Host smart-a2f68be8-04d0-4789-8a87-08de1cf0909d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315949113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3315949113
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.4257144412
Short name T292
Test name
Test status
Simulation time 261699386 ps
CPU time 1.26 seconds
Started Feb 04 04:20:19 PM PST 24
Finished Feb 04 04:20:22 PM PST 24
Peak memory 205912 kb
Host smart-b42ce59f-13b9-4b39-a930-7362b2996cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257144412 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.4257144412
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2332260537
Short name T948
Test name
Test status
Simulation time 30346418 ps
CPU time 0.97 seconds
Started Feb 04 04:20:30 PM PST 24
Finished Feb 04 04:20:36 PM PST 24
Peak memory 205400 kb
Host smart-816b230e-a293-4057-92f0-15410e090fa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332260537 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2332260537
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.1621468718
Short name T166
Test name
Test status
Simulation time 40366010 ps
CPU time 0.89 seconds
Started Feb 04 04:20:21 PM PST 24
Finished Feb 04 04:20:24 PM PST 24
Peak memory 215020 kb
Host smart-da012533-feb8-4bf2-97c2-85a1cd5210b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621468718 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.1621468718
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_genbits.3683363092
Short name T658
Test name
Test status
Simulation time 292537860 ps
CPU time 4.1 seconds
Started Feb 04 04:20:20 PM PST 24
Finished Feb 04 04:20:25 PM PST 24
Peak memory 215380 kb
Host smart-14939592-49fa-4d2d-8554-121ce7ff64a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683363092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3683363092
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3079771282
Short name T70
Test name
Test status
Simulation time 67632033 ps
CPU time 1.05 seconds
Started Feb 04 04:20:21 PM PST 24
Finished Feb 04 04:20:24 PM PST 24
Peak memory 222580 kb
Host smart-a8eff3e2-20ce-4d4b-8fad-2f81e46661a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079771282 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3079771282
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.4015352250
Short name T903
Test name
Test status
Simulation time 15536203 ps
CPU time 1.05 seconds
Started Feb 04 04:20:18 PM PST 24
Finished Feb 04 04:20:21 PM PST 24
Peak memory 214932 kb
Host smart-5e0f5137-bed8-4e5a-be87-fefd9da3ac68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015352250 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.4015352250
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.291229095
Short name T947
Test name
Test status
Simulation time 224754932 ps
CPU time 4.27 seconds
Started Feb 04 04:20:20 PM PST 24
Finished Feb 04 04:20:25 PM PST 24
Peak memory 215244 kb
Host smart-7f85917b-4de9-4bc4-a4e3-62e6e8ca9867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291229095 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.291229095
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1232007344
Short name T895
Test name
Test status
Simulation time 16474540173 ps
CPU time 247.49 seconds
Started Feb 04 04:20:17 PM PST 24
Finished Feb 04 04:24:27 PM PST 24
Peak memory 216788 kb
Host smart-d5ff1de4-a54a-4c96-9523-38de596137b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232007344 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1232007344
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.1205689177
Short name T454
Test name
Test status
Simulation time 63960583 ps
CPU time 1.05 seconds
Started Feb 04 04:23:28 PM PST 24
Finished Feb 04 04:23:30 PM PST 24
Peak memory 215680 kb
Host smart-6178ffb9-3a98-4911-9aa6-b7b70d68336e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205689177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1205689177
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.1515479363
Short name T709
Test name
Test status
Simulation time 149035824 ps
CPU time 1.85 seconds
Started Feb 04 04:23:30 PM PST 24
Finished Feb 04 04:23:38 PM PST 24
Peak memory 218280 kb
Host smart-239dde70-1dcc-440e-88e7-6e5146eeb126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515479363 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1515479363
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.2726459640
Short name T761
Test name
Test status
Simulation time 51032225 ps
CPU time 1.13 seconds
Started Feb 04 04:23:36 PM PST 24
Finished Feb 04 04:23:41 PM PST 24
Peak memory 215216 kb
Host smart-7e273533-193a-426f-af71-670aa4563c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726459640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2726459640
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.752389161
Short name T468
Test name
Test status
Simulation time 26272045 ps
CPU time 1.24 seconds
Started Feb 04 04:23:36 PM PST 24
Finished Feb 04 04:23:41 PM PST 24
Peak memory 216524 kb
Host smart-59b7e200-1374-48e2-bd32-9322d2e4c4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752389161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.752389161
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.2041604886
Short name T705
Test name
Test status
Simulation time 22976952 ps
CPU time 0.96 seconds
Started Feb 04 04:23:37 PM PST 24
Finished Feb 04 04:23:41 PM PST 24
Peak memory 215308 kb
Host smart-df0ed4dd-2475-4def-a1d6-a611fad5fffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041604886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2041604886
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.3685387235
Short name T445
Test name
Test status
Simulation time 20852003 ps
CPU time 1.33 seconds
Started Feb 04 04:23:36 PM PST 24
Finished Feb 04 04:23:41 PM PST 24
Peak memory 215448 kb
Host smart-cd3af9a6-5033-4fac-bc3d-ecd4314291c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685387235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3685387235
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.2186834960
Short name T943
Test name
Test status
Simulation time 31092418 ps
CPU time 1.06 seconds
Started Feb 04 04:23:39 PM PST 24
Finished Feb 04 04:23:43 PM PST 24
Peak memory 215440 kb
Host smart-9ab6e350-ec1b-4429-8fd1-4c5cdb92e68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186834960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2186834960
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.1376695906
Short name T509
Test name
Test status
Simulation time 17242134 ps
CPU time 1.07 seconds
Started Feb 04 04:23:34 PM PST 24
Finished Feb 04 04:23:38 PM PST 24
Peak memory 215428 kb
Host smart-b45b5d9e-298d-4ae1-9cde-3a5d3339e7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376695906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.1376695906
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.2339939487
Short name T500
Test name
Test status
Simulation time 91440599 ps
CPU time 2.38 seconds
Started Feb 04 04:23:38 PM PST 24
Finished Feb 04 04:23:44 PM PST 24
Peak memory 215728 kb
Host smart-5bb59a8b-91d7-4b38-927b-a86fd3b2e26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339939487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.2339939487
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.3189481374
Short name T686
Test name
Test status
Simulation time 51707527 ps
CPU time 0.93 seconds
Started Feb 04 04:20:31 PM PST 24
Finished Feb 04 04:20:36 PM PST 24
Peak memory 205876 kb
Host smart-450f62b5-43f1-4170-9eb2-be557851c500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189481374 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.3189481374
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3069561841
Short name T463
Test name
Test status
Simulation time 29521105 ps
CPU time 0.88 seconds
Started Feb 04 04:20:30 PM PST 24
Finished Feb 04 04:20:36 PM PST 24
Peak memory 205320 kb
Host smart-4cb69863-d460-41a0-bdc6-b58e665ad830
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069561841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3069561841
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.911441138
Short name T184
Test name
Test status
Simulation time 58218138 ps
CPU time 0.83 seconds
Started Feb 04 04:20:31 PM PST 24
Finished Feb 04 04:20:36 PM PST 24
Peak memory 215144 kb
Host smart-eaf38e53-1a91-4d17-a3f3-84f4469bacae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911441138 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.911441138
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.3473918085
Short name T827
Test name
Test status
Simulation time 33149358 ps
CPU time 0.93 seconds
Started Feb 04 04:20:41 PM PST 24
Finished Feb 04 04:20:43 PM PST 24
Peak memory 216328 kb
Host smart-96c59fa3-9ca9-4f73-91e5-436cff48e111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473918085 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3473918085
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1792345246
Short name T537
Test name
Test status
Simulation time 42164241 ps
CPU time 1.2 seconds
Started Feb 04 04:20:19 PM PST 24
Finished Feb 04 04:20:22 PM PST 24
Peak memory 215456 kb
Host smart-671811e1-376c-48e5-a4ca-16ea37bd57c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792345246 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1792345246
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1722880276
Short name T576
Test name
Test status
Simulation time 28042830 ps
CPU time 0.96 seconds
Started Feb 04 04:20:33 PM PST 24
Finished Feb 04 04:20:36 PM PST 24
Peak memory 215040 kb
Host smart-224fa732-f448-401e-9809-1451578c540a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722880276 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1722880276
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.1317896048
Short name T71
Test name
Test status
Simulation time 49391214 ps
CPU time 0.94 seconds
Started Feb 04 04:20:31 PM PST 24
Finished Feb 04 04:20:36 PM PST 24
Peak memory 214968 kb
Host smart-7cc041e7-3f10-45f1-aa98-ed9f9732ca8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317896048 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1317896048
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3369546114
Short name T491
Test name
Test status
Simulation time 286695674 ps
CPU time 3.29 seconds
Started Feb 04 04:20:35 PM PST 24
Finished Feb 04 04:20:39 PM PST 24
Peak memory 215116 kb
Host smart-130ff49b-3892-4020-ae02-f53dbc97094b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369546114 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3369546114
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2826382822
Short name T806
Test name
Test status
Simulation time 154543873041 ps
CPU time 798.61 seconds
Started Feb 04 04:20:36 PM PST 24
Finished Feb 04 04:33:56 PM PST 24
Peak memory 219420 kb
Host smart-d75ecf97-996e-48f5-8a80-da1447bfcfa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826382822 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2826382822
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.561275666
Short name T597
Test name
Test status
Simulation time 190845503 ps
CPU time 1.09 seconds
Started Feb 04 04:23:36 PM PST 24
Finished Feb 04 04:23:41 PM PST 24
Peak memory 216736 kb
Host smart-821ebb85-ce69-495d-9c07-293f531f8591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561275666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.561275666
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.72681455
Short name T501
Test name
Test status
Simulation time 27907279 ps
CPU time 1.33 seconds
Started Feb 04 04:23:37 PM PST 24
Finished Feb 04 04:23:42 PM PST 24
Peak memory 218008 kb
Host smart-6756fa01-10b3-452e-b1b8-d8665bfcbc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72681455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.72681455
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.1167625280
Short name T306
Test name
Test status
Simulation time 24138678 ps
CPU time 1.11 seconds
Started Feb 04 04:23:35 PM PST 24
Finished Feb 04 04:23:40 PM PST 24
Peak memory 215632 kb
Host smart-35aa68b6-08b7-4ab7-8833-fe282616a641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167625280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1167625280
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.323858467
Short name T894
Test name
Test status
Simulation time 78626762 ps
CPU time 1.05 seconds
Started Feb 04 04:23:38 PM PST 24
Finished Feb 04 04:23:42 PM PST 24
Peak memory 215420 kb
Host smart-589279c1-58d6-485c-a3d3-285ab7f10317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323858467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.323858467
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.1745526848
Short name T815
Test name
Test status
Simulation time 35483680 ps
CPU time 1.06 seconds
Started Feb 04 04:23:46 PM PST 24
Finished Feb 04 04:23:49 PM PST 24
Peak memory 215516 kb
Host smart-e7e00971-74c1-41f1-a778-8d4bdddb5082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745526848 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1745526848
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.581650931
Short name T651
Test name
Test status
Simulation time 49359082 ps
CPU time 1 seconds
Started Feb 04 04:23:47 PM PST 24
Finished Feb 04 04:23:49 PM PST 24
Peak memory 215184 kb
Host smart-5f48ae78-ad8d-47c9-8991-1ea2f478a210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581650931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.581650931
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.3159982327
Short name T582
Test name
Test status
Simulation time 66388271 ps
CPU time 0.97 seconds
Started Feb 04 04:23:49 PM PST 24
Finished Feb 04 04:23:51 PM PST 24
Peak memory 215272 kb
Host smart-57ff1410-3d58-458c-aebd-b3ae7bfb2c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159982327 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3159982327
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.707476728
Short name T741
Test name
Test status
Simulation time 161294324 ps
CPU time 0.97 seconds
Started Feb 04 04:23:49 PM PST 24
Finished Feb 04 04:23:51 PM PST 24
Peak memory 215272 kb
Host smart-66203dd9-a87a-4cd6-a5c2-7d9f5bf0daef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707476728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.707476728
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.3425005288
Short name T839
Test name
Test status
Simulation time 12782821 ps
CPU time 1.06 seconds
Started Feb 04 04:23:49 PM PST 24
Finished Feb 04 04:23:51 PM PST 24
Peak memory 215384 kb
Host smart-33f23caa-c799-416e-92c4-22ba8140d822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425005288 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3425005288
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.3752319767
Short name T36
Test name
Test status
Simulation time 172541331 ps
CPU time 1.17 seconds
Started Feb 04 04:23:48 PM PST 24
Finished Feb 04 04:23:52 PM PST 24
Peak memory 216592 kb
Host smart-30a563eb-a8f8-430d-984c-65ff571ab385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752319767 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.3752319767
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert_test.611081382
Short name T498
Test name
Test status
Simulation time 73485119 ps
CPU time 1.04 seconds
Started Feb 04 04:20:45 PM PST 24
Finished Feb 04 04:20:47 PM PST 24
Peak memory 205800 kb
Host smart-15827797-5bc6-4b9c-ae6a-c6d57bdc676c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611081382 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.611081382
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.3998683115
Short name T514
Test name
Test status
Simulation time 87457412 ps
CPU time 0.93 seconds
Started Feb 04 04:20:46 PM PST 24
Finished Feb 04 04:20:48 PM PST 24
Peak memory 215044 kb
Host smart-818ee9cd-480c-4ae6-9cd7-efba7be25ea0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998683115 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3998683115
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.1801993480
Short name T732
Test name
Test status
Simulation time 29004872 ps
CPU time 0.82 seconds
Started Feb 04 04:20:35 PM PST 24
Finished Feb 04 04:20:37 PM PST 24
Peak memory 216180 kb
Host smart-6d8c45c7-c79c-40bd-8a37-1bd56d4eaae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801993480 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.1801993480
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_intr.1176380145
Short name T725
Test name
Test status
Simulation time 19427274 ps
CPU time 1.08 seconds
Started Feb 04 04:20:39 PM PST 24
Finished Feb 04 04:20:41 PM PST 24
Peak memory 215016 kb
Host smart-90efa875-7f4e-4f27-8cb3-c60b2f486b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176380145 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1176380145
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1379856100
Short name T842
Test name
Test status
Simulation time 85724177 ps
CPU time 0.94 seconds
Started Feb 04 04:20:31 PM PST 24
Finished Feb 04 04:20:36 PM PST 24
Peak memory 214888 kb
Host smart-fa8e335c-584a-4836-adae-220755056a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379856100 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1379856100
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2513498686
Short name T805
Test name
Test status
Simulation time 98537846 ps
CPU time 2.75 seconds
Started Feb 04 04:20:28 PM PST 24
Finished Feb 04 04:20:32 PM PST 24
Peak memory 215480 kb
Host smart-9906cc82-8947-4c02-8410-b602a6d9d34c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513498686 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2513498686
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2134822691
Short name T881
Test name
Test status
Simulation time 299715106442 ps
CPU time 1297.28 seconds
Started Feb 04 04:20:33 PM PST 24
Finished Feb 04 04:42:13 PM PST 24
Peak memory 221300 kb
Host smart-85afc562-7b4e-412d-bbde-0aedead473e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134822691 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2134822691
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.833995464
Short name T481
Test name
Test status
Simulation time 49699358 ps
CPU time 1.06 seconds
Started Feb 04 04:23:45 PM PST 24
Finished Feb 04 04:23:49 PM PST 24
Peak memory 216640 kb
Host smart-385eb0f3-1a69-42e1-8d6f-6f7395cb4211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833995464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.833995464
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.1254285619
Short name T303
Test name
Test status
Simulation time 63343011 ps
CPU time 1.09 seconds
Started Feb 04 04:23:46 PM PST 24
Finished Feb 04 04:23:49 PM PST 24
Peak memory 216744 kb
Host smart-abbf5e9b-fcfd-475d-af4e-d5f7f147e329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254285619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1254285619
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.4186964066
Short name T768
Test name
Test status
Simulation time 31419318 ps
CPU time 1.09 seconds
Started Feb 04 04:23:44 PM PST 24
Finished Feb 04 04:23:49 PM PST 24
Peak memory 216708 kb
Host smart-68ec687f-5cca-4759-90d9-e7f0d9019af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186964066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.4186964066
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3514825233
Short name T269
Test name
Test status
Simulation time 15869700 ps
CPU time 1.1 seconds
Started Feb 04 04:23:46 PM PST 24
Finished Feb 04 04:23:49 PM PST 24
Peak memory 215628 kb
Host smart-5df8f925-03e5-46a1-9076-03d3a0f67917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514825233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3514825233
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.2949829231
Short name T634
Test name
Test status
Simulation time 29011234 ps
CPU time 1.01 seconds
Started Feb 04 04:23:52 PM PST 24
Finished Feb 04 04:23:54 PM PST 24
Peak memory 215204 kb
Host smart-c907e786-2c58-4855-bc77-c9805dfbeb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949829231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2949829231
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.3397172140
Short name T322
Test name
Test status
Simulation time 81001603 ps
CPU time 1.21 seconds
Started Feb 04 04:23:46 PM PST 24
Finished Feb 04 04:23:49 PM PST 24
Peak memory 215388 kb
Host smart-d7c3ea98-1fb8-40b5-8183-249884aa3738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397172140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3397172140
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.3707558191
Short name T539
Test name
Test status
Simulation time 62903086 ps
CPU time 0.94 seconds
Started Feb 04 04:23:42 PM PST 24
Finished Feb 04 04:23:48 PM PST 24
Peak memory 215224 kb
Host smart-2af93fdc-21ee-4b64-8a69-2e6c9117ccdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707558191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3707558191
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.1051712257
Short name T745
Test name
Test status
Simulation time 64940573 ps
CPU time 1.05 seconds
Started Feb 04 04:23:43 PM PST 24
Finished Feb 04 04:23:49 PM PST 24
Peak memory 215356 kb
Host smart-e6b5cf7e-c138-41bb-8c95-d338a7039b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051712257 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1051712257
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert_test.272102071
Short name T765
Test name
Test status
Simulation time 47009572 ps
CPU time 1.02 seconds
Started Feb 04 04:19:05 PM PST 24
Finished Feb 04 04:19:09 PM PST 24
Peak memory 205352 kb
Host smart-f48bd825-386e-4dfb-8b2d-682f79131f18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272102071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.272102071
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.1745108277
Short name T730
Test name
Test status
Simulation time 39885672 ps
CPU time 0.87 seconds
Started Feb 04 04:19:03 PM PST 24
Finished Feb 04 04:19:09 PM PST 24
Peak memory 215052 kb
Host smart-3959b1b4-4e5c-4f9d-b5ce-cc591af40678
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745108277 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.1745108277
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.1487223566
Short name T612
Test name
Test status
Simulation time 49523288 ps
CPU time 1 seconds
Started Feb 04 04:19:09 PM PST 24
Finished Feb 04 04:19:11 PM PST 24
Peak memory 216916 kb
Host smart-403c852d-baf0-42fb-a5cc-2e423b0512c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487223566 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1487223566
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.2305217554
Short name T467
Test name
Test status
Simulation time 50762168 ps
CPU time 2.1 seconds
Started Feb 04 04:19:05 PM PST 24
Finished Feb 04 04:19:10 PM PST 24
Peak memory 218268 kb
Host smart-3143909f-e4b3-4e21-9c46-047a461c2b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305217554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2305217554
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.797078022
Short name T618
Test name
Test status
Simulation time 38357492 ps
CPU time 0.85 seconds
Started Feb 04 04:19:03 PM PST 24
Finished Feb 04 04:19:09 PM PST 24
Peak memory 214912 kb
Host smart-19d59a9b-330f-40c9-b900-9ec88e6b098b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797078022 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.797078022
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2321798611
Short name T22
Test name
Test status
Simulation time 825611145 ps
CPU time 3.79 seconds
Started Feb 04 04:19:04 PM PST 24
Finished Feb 04 04:19:12 PM PST 24
Peak memory 233748 kb
Host smart-6087bced-4af5-4f40-a18f-112ddfaebfee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321798611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2321798611
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.1431008759
Short name T664
Test name
Test status
Simulation time 22074956 ps
CPU time 1.03 seconds
Started Feb 04 04:19:10 PM PST 24
Finished Feb 04 04:19:12 PM PST 24
Peak memory 214876 kb
Host smart-5f2cccd4-426d-4065-9720-ddfb9bdfd4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431008759 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1431008759
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2469691990
Short name T750
Test name
Test status
Simulation time 444740117 ps
CPU time 3.14 seconds
Started Feb 04 04:19:10 PM PST 24
Finished Feb 04 04:19:15 PM PST 24
Peak memory 215248 kb
Host smart-8692d94d-f8cf-4307-a8d4-c7f0642266a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469691990 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2469691990
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.525407086
Short name T265
Test name
Test status
Simulation time 43455610973 ps
CPU time 1117.04 seconds
Started Feb 04 04:19:05 PM PST 24
Finished Feb 04 04:37:45 PM PST 24
Peak memory 219716 kb
Host smart-21a67350-7a0c-4aa1-8976-6a34ad13e2fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525407086 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.525407086
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1049790194
Short name T252
Test name
Test status
Simulation time 64891352 ps
CPU time 1.06 seconds
Started Feb 04 04:20:41 PM PST 24
Finished Feb 04 04:20:43 PM PST 24
Peak memory 206684 kb
Host smart-53c95d20-8738-4dd2-abe0-1335f813e402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049790194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1049790194
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.2636245853
Short name T438
Test name
Test status
Simulation time 41699069 ps
CPU time 0.92 seconds
Started Feb 04 04:20:43 PM PST 24
Finished Feb 04 04:20:45 PM PST 24
Peak memory 206044 kb
Host smart-26a70594-4a98-4e8a-a265-f14421ed7533
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636245853 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.2636245853
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1158145781
Short name T687
Test name
Test status
Simulation time 113787701 ps
CPU time 0.94 seconds
Started Feb 04 04:20:43 PM PST 24
Finished Feb 04 04:20:45 PM PST 24
Peak memory 215064 kb
Host smart-de7981cd-b378-44bf-a061-7a6c335a187a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158145781 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1158145781
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.2398225957
Short name T929
Test name
Test status
Simulation time 58519637 ps
CPU time 1.18 seconds
Started Feb 04 04:20:36 PM PST 24
Finished Feb 04 04:20:38 PM PST 24
Peak memory 215232 kb
Host smart-461cfa56-7c05-4f22-b5c5-943c51979037
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398225957 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.2398225957
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.739372184
Short name T852
Test name
Test status
Simulation time 23733443 ps
CPU time 0.93 seconds
Started Feb 04 04:20:44 PM PST 24
Finished Feb 04 04:20:46 PM PST 24
Peak memory 216444 kb
Host smart-1f6565a8-c2ce-4f71-b4ac-1e9dfb3472d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739372184 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.739372184
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2772324901
Short name T838
Test name
Test status
Simulation time 28690800 ps
CPU time 1.07 seconds
Started Feb 04 04:20:46 PM PST 24
Finished Feb 04 04:20:48 PM PST 24
Peak memory 216544 kb
Host smart-8a060d09-1273-4d64-96c8-8ce9934f6c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772324901 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2772324901
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3075649983
Short name T80
Test name
Test status
Simulation time 20814316 ps
CPU time 1.15 seconds
Started Feb 04 04:20:44 PM PST 24
Finished Feb 04 04:20:47 PM PST 24
Peak memory 215312 kb
Host smart-a9ae5920-5ad9-45ab-969d-079021ddbe82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075649983 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3075649983
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1812749747
Short name T605
Test name
Test status
Simulation time 37638954 ps
CPU time 0.89 seconds
Started Feb 04 04:20:37 PM PST 24
Finished Feb 04 04:20:39 PM PST 24
Peak memory 214948 kb
Host smart-a4ece78e-972c-4566-92a9-1e8ee0dc1943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812749747 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1812749747
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1313038029
Short name T535
Test name
Test status
Simulation time 315444355 ps
CPU time 3.78 seconds
Started Feb 04 04:20:39 PM PST 24
Finished Feb 04 04:20:43 PM PST 24
Peak memory 215276 kb
Host smart-a796cb1e-d972-4b27-b5c9-4973fe98911c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313038029 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1313038029
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1275894674
Short name T786
Test name
Test status
Simulation time 87865953287 ps
CPU time 593.31 seconds
Started Feb 04 04:20:43 PM PST 24
Finished Feb 04 04:30:37 PM PST 24
Peak memory 218372 kb
Host smart-2e371a5e-6213-4646-a5af-488fad2715ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275894674 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1275894674
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2604335046
Short name T767
Test name
Test status
Simulation time 19411775 ps
CPU time 1.27 seconds
Started Feb 04 04:23:45 PM PST 24
Finished Feb 04 04:23:49 PM PST 24
Peak memory 215600 kb
Host smart-d4077580-2322-4e4d-8281-20fa5b055fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604335046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2604335046
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2537670738
Short name T810
Test name
Test status
Simulation time 404070011 ps
CPU time 4.44 seconds
Started Feb 04 04:23:46 PM PST 24
Finished Feb 04 04:23:52 PM PST 24
Peak memory 215624 kb
Host smart-3222946f-3559-49e9-989c-61797f4154b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537670738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2537670738
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.54819764
Short name T923
Test name
Test status
Simulation time 278345309 ps
CPU time 4.02 seconds
Started Feb 04 04:23:47 PM PST 24
Finished Feb 04 04:23:53 PM PST 24
Peak memory 215588 kb
Host smart-8d259286-4a73-43b1-8a17-bf477dce459a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54819764 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.54819764
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2901111158
Short name T494
Test name
Test status
Simulation time 53616600 ps
CPU time 1.21 seconds
Started Feb 04 04:23:47 PM PST 24
Finished Feb 04 04:23:49 PM PST 24
Peak memory 216760 kb
Host smart-75272b15-7adf-47ec-906a-8be2ba81e447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901111158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2901111158
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3013037451
Short name T719
Test name
Test status
Simulation time 31846094 ps
CPU time 1.38 seconds
Started Feb 04 04:23:46 PM PST 24
Finished Feb 04 04:23:49 PM PST 24
Peak memory 214896 kb
Host smart-e4724f41-246b-40da-b8d4-f83378910da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013037451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3013037451
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.4156309224
Short name T473
Test name
Test status
Simulation time 18921138 ps
CPU time 1.11 seconds
Started Feb 04 04:23:45 PM PST 24
Finished Feb 04 04:23:49 PM PST 24
Peak memory 215448 kb
Host smart-b5ba3571-f274-423e-b0d5-aacbe67b9771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156309224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.4156309224
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.4153160831
Short name T711
Test name
Test status
Simulation time 25584311 ps
CPU time 1.32 seconds
Started Feb 04 04:23:46 PM PST 24
Finished Feb 04 04:23:49 PM PST 24
Peak memory 215648 kb
Host smart-70780f1f-ab49-45c9-936d-ebe9c76bd707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153160831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.4153160831
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3742079911
Short name T90
Test name
Test status
Simulation time 19564225 ps
CPU time 1.07 seconds
Started Feb 04 04:23:52 PM PST 24
Finished Feb 04 04:23:54 PM PST 24
Peak memory 215392 kb
Host smart-fc94799d-6bc7-48c6-9e19-b196cb3573b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742079911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3742079911
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.993245783
Short name T31
Test name
Test status
Simulation time 20749317 ps
CPU time 1.11 seconds
Started Feb 04 04:23:54 PM PST 24
Finished Feb 04 04:23:56 PM PST 24
Peak memory 215436 kb
Host smart-fffed1f9-3c90-4c80-88c8-f68cfd28f31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993245783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.993245783
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.731991977
Short name T668
Test name
Test status
Simulation time 19165635 ps
CPU time 1.19 seconds
Started Feb 04 04:23:55 PM PST 24
Finished Feb 04 04:23:57 PM PST 24
Peak memory 215424 kb
Host smart-dcae9939-44f3-438f-aac4-f13fa54472b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731991977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.731991977
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3062811579
Short name T18
Test name
Test status
Simulation time 27899934 ps
CPU time 1 seconds
Started Feb 04 04:20:42 PM PST 24
Finished Feb 04 04:20:45 PM PST 24
Peak memory 206660 kb
Host smart-26c14910-7c45-4960-bd4b-232d930cfc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062811579 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3062811579
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3196655396
Short name T558
Test name
Test status
Simulation time 18400423 ps
CPU time 0.97 seconds
Started Feb 04 04:20:43 PM PST 24
Finished Feb 04 04:20:45 PM PST 24
Peak memory 205340 kb
Host smart-2c65cac7-8db6-456b-8bad-5a717689c7f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196655396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3196655396
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.2108311860
Short name T125
Test name
Test status
Simulation time 19203052 ps
CPU time 0.86 seconds
Started Feb 04 04:20:45 PM PST 24
Finished Feb 04 04:20:47 PM PST 24
Peak memory 215024 kb
Host smart-dbd12aa5-9a24-49c2-8390-73e8614a5af7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108311860 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.2108311860
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3486120657
Short name T557
Test name
Test status
Simulation time 185212455 ps
CPU time 1.22 seconds
Started Feb 04 04:20:49 PM PST 24
Finished Feb 04 04:20:53 PM PST 24
Peak memory 215364 kb
Host smart-0a82c25b-6914-4261-8188-214b3d42ae6a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486120657 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3486120657
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3710033292
Short name T142
Test name
Test status
Simulation time 25623207 ps
CPU time 1.07 seconds
Started Feb 04 04:20:49 PM PST 24
Finished Feb 04 04:20:52 PM PST 24
Peak memory 222800 kb
Host smart-9026a582-1b06-4b6a-aa51-9b24a7ad3bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710033292 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3710033292
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3403002875
Short name T318
Test name
Test status
Simulation time 45790032 ps
CPU time 1.08 seconds
Started Feb 04 04:20:39 PM PST 24
Finished Feb 04 04:20:41 PM PST 24
Peak memory 214864 kb
Host smart-ff907d60-2b52-49f7-865c-93289186dc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403002875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3403002875
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.3213796222
Short name T674
Test name
Test status
Simulation time 30783576 ps
CPU time 1.06 seconds
Started Feb 04 04:20:47 PM PST 24
Finished Feb 04 04:20:50 PM PST 24
Peak memory 222640 kb
Host smart-09b7dd65-6405-4339-824f-843a262bcb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213796222 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.3213796222
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.1632034711
Short name T690
Test name
Test status
Simulation time 26446686 ps
CPU time 0.96 seconds
Started Feb 04 04:20:37 PM PST 24
Finished Feb 04 04:20:39 PM PST 24
Peak memory 214944 kb
Host smart-73daacbf-4354-4fdb-b4e6-493becbcd10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632034711 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.1632034711
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.1259330663
Short name T910
Test name
Test status
Simulation time 113026959 ps
CPU time 1.95 seconds
Started Feb 04 04:20:43 PM PST 24
Finished Feb 04 04:20:46 PM PST 24
Peak memory 215220 kb
Host smart-feed66b5-cb7a-4213-9f29-27241f9e8137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259330663 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.1259330663
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2880302344
Short name T763
Test name
Test status
Simulation time 110813779095 ps
CPU time 1261.21 seconds
Started Feb 04 04:20:42 PM PST 24
Finished Feb 04 04:41:44 PM PST 24
Peak memory 221964 kb
Host smart-22a16c86-61e5-4185-8fe0-f24a860cdf50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880302344 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2880302344
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.2629063823
Short name T13
Test name
Test status
Simulation time 66756354 ps
CPU time 1.21 seconds
Started Feb 04 04:23:54 PM PST 24
Finished Feb 04 04:23:57 PM PST 24
Peak memory 215412 kb
Host smart-796d3f9c-3e18-43fb-8194-43f695a78869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629063823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.2629063823
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3711973837
Short name T967
Test name
Test status
Simulation time 135912498 ps
CPU time 2.05 seconds
Started Feb 04 04:23:47 PM PST 24
Finished Feb 04 04:23:50 PM PST 24
Peak memory 215504 kb
Host smart-88c02ae7-7eaf-4332-9f25-3c7e52a93e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711973837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3711973837
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3083622680
Short name T930
Test name
Test status
Simulation time 66483943 ps
CPU time 1.1 seconds
Started Feb 04 04:23:58 PM PST 24
Finished Feb 04 04:24:00 PM PST 24
Peak memory 216752 kb
Host smart-8855d683-4a3f-4e2d-8300-1c86575f272b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083622680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3083622680
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.1620590395
Short name T506
Test name
Test status
Simulation time 86162704 ps
CPU time 1.33 seconds
Started Feb 04 04:23:48 PM PST 24
Finished Feb 04 04:23:50 PM PST 24
Peak memory 215384 kb
Host smart-1f87b956-f40b-49b7-98c8-339057c30f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620590395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1620590395
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.254092977
Short name T896
Test name
Test status
Simulation time 37787059 ps
CPU time 1.7 seconds
Started Feb 04 04:23:47 PM PST 24
Finished Feb 04 04:23:50 PM PST 24
Peak memory 215604 kb
Host smart-eadb3708-1545-40a6-9ba5-78a9728a80b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254092977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.254092977
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2118009977
Short name T758
Test name
Test status
Simulation time 27441359 ps
CPU time 1.06 seconds
Started Feb 04 04:23:51 PM PST 24
Finished Feb 04 04:23:53 PM PST 24
Peak memory 216768 kb
Host smart-bba12a61-5e71-4a31-99c4-d68573c6ce3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118009977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2118009977
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3574871119
Short name T957
Test name
Test status
Simulation time 32052903 ps
CPU time 1.33 seconds
Started Feb 04 04:23:58 PM PST 24
Finished Feb 04 04:24:00 PM PST 24
Peak memory 216828 kb
Host smart-1c37e8a6-9743-4b13-98cf-f709e1d16b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574871119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3574871119
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.76809577
Short name T656
Test name
Test status
Simulation time 93081209 ps
CPU time 1.03 seconds
Started Feb 04 04:23:54 PM PST 24
Finished Feb 04 04:23:55 PM PST 24
Peak memory 216600 kb
Host smart-27ca4daf-c480-4e25-b8b3-9f723f19183d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76809577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.76809577
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1089350248
Short name T914
Test name
Test status
Simulation time 121625945 ps
CPU time 1.18 seconds
Started Feb 04 04:23:58 PM PST 24
Finished Feb 04 04:24:00 PM PST 24
Peak memory 215596 kb
Host smart-b6bce3b1-9742-4ab0-a864-ffb82cc56f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089350248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1089350248
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.794612160
Short name T287
Test name
Test status
Simulation time 59403611 ps
CPU time 0.99 seconds
Started Feb 04 04:20:43 PM PST 24
Finished Feb 04 04:20:45 PM PST 24
Peak memory 206644 kb
Host smart-33894d19-5a34-4dd1-b918-6d7db8cb89b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794612160 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.794612160
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.1466849759
Short name T585
Test name
Test status
Simulation time 15494382 ps
CPU time 0.96 seconds
Started Feb 04 04:20:43 PM PST 24
Finished Feb 04 04:20:45 PM PST 24
Peak memory 206208 kb
Host smart-4808637c-0663-4db1-b0f1-20c362435a69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466849759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1466849759
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1092509246
Short name T645
Test name
Test status
Simulation time 10759607 ps
CPU time 0.92 seconds
Started Feb 04 04:20:44 PM PST 24
Finished Feb 04 04:20:46 PM PST 24
Peak memory 215068 kb
Host smart-fab6ca6b-462e-4997-b0f7-e7a726a51c40
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092509246 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1092509246
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.342532837
Short name T97
Test name
Test status
Simulation time 73657373 ps
CPU time 1.13 seconds
Started Feb 04 04:20:47 PM PST 24
Finished Feb 04 04:20:51 PM PST 24
Peak memory 215292 kb
Host smart-4da9b360-f303-4d80-9dcf-bd9ea3cfd228
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342532837 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_di
sable_auto_req_mode.342532837
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.1856445457
Short name T7
Test name
Test status
Simulation time 51971740 ps
CPU time 1.04 seconds
Started Feb 04 04:20:45 PM PST 24
Finished Feb 04 04:20:47 PM PST 24
Peak memory 216992 kb
Host smart-f9a8eac0-62bd-4882-9cad-294f1ea9c38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856445457 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1856445457
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2785174604
Short name T270
Test name
Test status
Simulation time 37082827 ps
CPU time 1.19 seconds
Started Feb 04 04:20:49 PM PST 24
Finished Feb 04 04:20:53 PM PST 24
Peak memory 215896 kb
Host smart-85c4bb54-4f33-42be-9389-32a8ce1fb24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785174604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2785174604
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.2584925258
Short name T546
Test name
Test status
Simulation time 31744214 ps
CPU time 0.86 seconds
Started Feb 04 04:20:44 PM PST 24
Finished Feb 04 04:20:46 PM PST 24
Peak memory 215128 kb
Host smart-a3987e66-3a25-4645-b60c-c456c8facd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584925258 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2584925258
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3635860917
Short name T870
Test name
Test status
Simulation time 10793251 ps
CPU time 0.96 seconds
Started Feb 04 04:20:46 PM PST 24
Finished Feb 04 04:20:49 PM PST 24
Peak memory 214924 kb
Host smart-763baf11-2a61-42f9-948b-c6fcb95d6115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635860917 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3635860917
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.35250342
Short name T792
Test name
Test status
Simulation time 118288593 ps
CPU time 1.78 seconds
Started Feb 04 04:20:49 PM PST 24
Finished Feb 04 04:20:54 PM PST 24
Peak memory 215248 kb
Host smart-9759e0d7-a755-4dd5-8638-5288b6fde980
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35250342 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.35250342
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.1743557051
Short name T266
Test name
Test status
Simulation time 107055339770 ps
CPU time 1201.19 seconds
Started Feb 04 04:20:42 PM PST 24
Finished Feb 04 04:40:44 PM PST 24
Peak memory 219948 kb
Host smart-2b06948e-46db-43cd-83b4-7ece17e79977
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743557051 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.1743557051
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1842438691
Short name T185
Test name
Test status
Simulation time 70714867 ps
CPU time 1.1 seconds
Started Feb 04 04:24:02 PM PST 24
Finished Feb 04 04:24:04 PM PST 24
Peak memory 215144 kb
Host smart-7dc4795b-af42-4931-b09e-6f31f723f2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842438691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1842438691
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.2624723117
Short name T962
Test name
Test status
Simulation time 45106892 ps
CPU time 1.49 seconds
Started Feb 04 04:23:55 PM PST 24
Finished Feb 04 04:23:58 PM PST 24
Peak memory 215528 kb
Host smart-ca318450-d1aa-4b9a-b253-58c05bc18c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624723117 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.2624723117
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3312413928
Short name T602
Test name
Test status
Simulation time 63654812 ps
CPU time 2.69 seconds
Started Feb 04 04:23:56 PM PST 24
Finished Feb 04 04:24:00 PM PST 24
Peak memory 216576 kb
Host smart-758fcbb2-656e-426e-b814-6c2b86141ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312413928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3312413928
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3826990951
Short name T486
Test name
Test status
Simulation time 94517270 ps
CPU time 1.12 seconds
Started Feb 04 04:23:53 PM PST 24
Finished Feb 04 04:23:55 PM PST 24
Peak memory 216968 kb
Host smart-abcd6597-b1de-4849-8514-ab839ca713d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826990951 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3826990951
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.1993844859
Short name T181
Test name
Test status
Simulation time 70013945 ps
CPU time 1.44 seconds
Started Feb 04 04:23:55 PM PST 24
Finished Feb 04 04:23:58 PM PST 24
Peak memory 216812 kb
Host smart-2b3d959e-dfa5-4130-a9d0-d8fb7f495664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993844859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.1993844859
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.666801626
Short name T504
Test name
Test status
Simulation time 52976742 ps
CPU time 1.03 seconds
Started Feb 04 04:23:51 PM PST 24
Finished Feb 04 04:23:53 PM PST 24
Peak memory 215448 kb
Host smart-d4e5780a-8cdd-4ee0-ac4f-c653733ff7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666801626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.666801626
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.778045231
Short name T584
Test name
Test status
Simulation time 30649929 ps
CPU time 1.03 seconds
Started Feb 04 04:23:47 PM PST 24
Finished Feb 04 04:23:50 PM PST 24
Peak memory 215404 kb
Host smart-74044ff7-9096-4c0a-abbc-3ce123984c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778045231 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.778045231
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3734410890
Short name T12
Test name
Test status
Simulation time 46651811 ps
CPU time 1.24 seconds
Started Feb 04 04:23:50 PM PST 24
Finished Feb 04 04:23:53 PM PST 24
Peak memory 215672 kb
Host smart-191b48ed-7ea6-4de5-9799-3de350463f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734410890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3734410890
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1260542183
Short name T523
Test name
Test status
Simulation time 69103031 ps
CPU time 1.03 seconds
Started Feb 04 04:24:01 PM PST 24
Finished Feb 04 04:24:03 PM PST 24
Peak memory 215488 kb
Host smart-513b00c9-c4d9-493f-bfa3-7f79e3c157ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260542183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1260542183
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1288576911
Short name T867
Test name
Test status
Simulation time 34081909 ps
CPU time 1.12 seconds
Started Feb 04 04:23:55 PM PST 24
Finished Feb 04 04:23:57 PM PST 24
Peak memory 215204 kb
Host smart-3de252db-a369-4e83-b726-bb5652738e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288576911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1288576911
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.777185308
Short name T286
Test name
Test status
Simulation time 63913064 ps
CPU time 0.99 seconds
Started Feb 04 04:20:50 PM PST 24
Finished Feb 04 04:20:54 PM PST 24
Peak memory 205844 kb
Host smart-7f2a01b8-4b41-48d0-ac2c-c9135a7ab3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777185308 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.777185308
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1940969844
Short name T430
Test name
Test status
Simulation time 11168195 ps
CPU time 0.85 seconds
Started Feb 04 04:20:44 PM PST 24
Finished Feb 04 04:20:45 PM PST 24
Peak memory 205164 kb
Host smart-c57c43c8-b823-4b82-9678-60002ae90b3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940969844 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1940969844
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.4056842143
Short name T571
Test name
Test status
Simulation time 53176344 ps
CPU time 0.99 seconds
Started Feb 04 04:20:51 PM PST 24
Finished Feb 04 04:20:54 PM PST 24
Peak memory 215112 kb
Host smart-f3763619-8de0-4576-aa08-b0590fbef7cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056842143 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.4056842143
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.890861725
Short name T861
Test name
Test status
Simulation time 19216904 ps
CPU time 1.08 seconds
Started Feb 04 04:20:50 PM PST 24
Finished Feb 04 04:20:54 PM PST 24
Peak memory 216788 kb
Host smart-83c35a16-d737-436f-967b-db15b6ba4bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890861725 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.890861725
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.1590920711
Short name T640
Test name
Test status
Simulation time 23002446 ps
CPU time 0.98 seconds
Started Feb 04 04:20:47 PM PST 24
Finished Feb 04 04:20:49 PM PST 24
Peak memory 215408 kb
Host smart-92342e1e-0d44-4923-b7f2-1f9c549c070a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590920711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.1590920711
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.204382359
Short name T939
Test name
Test status
Simulation time 52923519 ps
CPU time 0.85 seconds
Started Feb 04 04:20:45 PM PST 24
Finished Feb 04 04:20:47 PM PST 24
Peak memory 215112 kb
Host smart-4e0117dd-4c91-431f-96d5-a640a0e63e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204382359 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.204382359
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1194533666
Short name T565
Test name
Test status
Simulation time 43587042 ps
CPU time 0.9 seconds
Started Feb 04 04:20:49 PM PST 24
Finished Feb 04 04:20:53 PM PST 24
Peak memory 215064 kb
Host smart-b98ac157-f819-4725-a175-7497651a7bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194533666 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1194533666
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.1034774464
Short name T443
Test name
Test status
Simulation time 104079293 ps
CPU time 2.54 seconds
Started Feb 04 04:20:49 PM PST 24
Finished Feb 04 04:20:54 PM PST 24
Peak memory 214352 kb
Host smart-7ac5409e-f485-4a70-81cd-b643c1e65662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034774464 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.1034774464
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2183690869
Short name T570
Test name
Test status
Simulation time 119745955983 ps
CPU time 1422.48 seconds
Started Feb 04 04:20:47 PM PST 24
Finished Feb 04 04:44:32 PM PST 24
Peak memory 224744 kb
Host smart-797171e6-d2bd-44ef-9205-636566ddebf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183690869 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2183690869
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2281262746
Short name T692
Test name
Test status
Simulation time 18719243 ps
CPU time 1.05 seconds
Started Feb 04 04:23:55 PM PST 24
Finished Feb 04 04:23:58 PM PST 24
Peak memory 215236 kb
Host smart-08f4244a-6c4f-4b98-8fb4-d56755355b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281262746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2281262746
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.143414900
Short name T820
Test name
Test status
Simulation time 667562553 ps
CPU time 5.92 seconds
Started Feb 04 04:23:57 PM PST 24
Finished Feb 04 04:24:04 PM PST 24
Peak memory 215272 kb
Host smart-6b7cf8dd-7855-4fc8-9759-578f3f5e12a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143414900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.143414900
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.4241469148
Short name T648
Test name
Test status
Simulation time 44751969 ps
CPU time 1.22 seconds
Started Feb 04 04:23:53 PM PST 24
Finished Feb 04 04:23:55 PM PST 24
Peak memory 216776 kb
Host smart-1a51397d-33b2-42c8-8c09-9a796b7d29f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241469148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.4241469148
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1812958165
Short name T803
Test name
Test status
Simulation time 285640613 ps
CPU time 4.22 seconds
Started Feb 04 04:24:02 PM PST 24
Finished Feb 04 04:24:07 PM PST 24
Peak memory 215664 kb
Host smart-6b216423-a935-4341-8639-ac377591ee14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812958165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1812958165
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.2491231659
Short name T886
Test name
Test status
Simulation time 26755652 ps
CPU time 1.01 seconds
Started Feb 04 04:23:57 PM PST 24
Finished Feb 04 04:23:59 PM PST 24
Peak memory 215460 kb
Host smart-2f11ab62-f584-4922-95f4-dd60654d10b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491231659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.2491231659
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2133254605
Short name T811
Test name
Test status
Simulation time 15690335 ps
CPU time 1.11 seconds
Started Feb 04 04:23:59 PM PST 24
Finished Feb 04 04:24:01 PM PST 24
Peak memory 215276 kb
Host smart-9ad36353-2157-4cff-9516-68a1fae76aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133254605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2133254605
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3076827207
Short name T643
Test name
Test status
Simulation time 18485215 ps
CPU time 1.15 seconds
Started Feb 04 04:23:55 PM PST 24
Finished Feb 04 04:23:58 PM PST 24
Peak memory 215624 kb
Host smart-b1050a4d-547a-48fa-81e6-a0d8de399381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076827207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3076827207
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3386300962
Short name T801
Test name
Test status
Simulation time 60292098 ps
CPU time 0.98 seconds
Started Feb 04 04:23:55 PM PST 24
Finished Feb 04 04:23:57 PM PST 24
Peak memory 215076 kb
Host smart-20330fb8-1127-48f0-aaeb-a5ce841969db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386300962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3386300962
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3469875829
Short name T925
Test name
Test status
Simulation time 25339664 ps
CPU time 1.04 seconds
Started Feb 04 04:24:02 PM PST 24
Finished Feb 04 04:24:04 PM PST 24
Peak memory 215292 kb
Host smart-b7d729a3-a556-44d4-92ef-4843ce79039a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469875829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3469875829
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.3216590251
Short name T878
Test name
Test status
Simulation time 22165609 ps
CPU time 0.99 seconds
Started Feb 04 04:24:02 PM PST 24
Finished Feb 04 04:24:04 PM PST 24
Peak memory 215148 kb
Host smart-1323b3f3-54c2-4488-9e2d-1f865675662d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216590251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.3216590251
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1038147197
Short name T890
Test name
Test status
Simulation time 180574557 ps
CPU time 1.06 seconds
Started Feb 04 04:20:58 PM PST 24
Finished Feb 04 04:21:00 PM PST 24
Peak memory 206640 kb
Host smart-36a91a60-d2cc-44b2-87b2-bed247ec7466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038147197 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1038147197
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.266998802
Short name T626
Test name
Test status
Simulation time 112357577 ps
CPU time 0.95 seconds
Started Feb 04 04:20:54 PM PST 24
Finished Feb 04 04:21:00 PM PST 24
Peak memory 205360 kb
Host smart-7bc10330-2994-42a3-9dee-e5e4cc83d986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266998802 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.266998802
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1162322296
Short name T177
Test name
Test status
Simulation time 379195917 ps
CPU time 1.16 seconds
Started Feb 04 04:20:48 PM PST 24
Finished Feb 04 04:20:52 PM PST 24
Peak memory 215220 kb
Host smart-06da729c-d379-44d0-aba4-5327ecd30722
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162322296 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1162322296
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.2330383536
Short name T622
Test name
Test status
Simulation time 18869927 ps
CPU time 1.05 seconds
Started Feb 04 04:20:58 PM PST 24
Finished Feb 04 04:21:00 PM PST 24
Peak memory 216348 kb
Host smart-05560b59-69dc-4e88-a6c2-498f34972cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330383536 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2330383536
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.4131495996
Short name T566
Test name
Test status
Simulation time 90138699 ps
CPU time 1.03 seconds
Started Feb 04 04:20:58 PM PST 24
Finished Feb 04 04:21:00 PM PST 24
Peak memory 215388 kb
Host smart-6ddd8960-9ac9-4417-878b-6c77a48894f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131495996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.4131495996
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.4000866518
Short name T16
Test name
Test status
Simulation time 40274580 ps
CPU time 1.05 seconds
Started Feb 04 04:20:47 PM PST 24
Finished Feb 04 04:20:50 PM PST 24
Peak memory 222564 kb
Host smart-e974149f-4a26-448f-b10d-6070dd35e7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000866518 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.4000866518
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1903210061
Short name T52
Test name
Test status
Simulation time 12195326 ps
CPU time 0.89 seconds
Started Feb 04 04:20:49 PM PST 24
Finished Feb 04 04:20:53 PM PST 24
Peak memory 214932 kb
Host smart-3779c1e0-ab23-46ce-b008-805d3be77761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903210061 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1903210061
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2662907760
Short name T762
Test name
Test status
Simulation time 2028531012 ps
CPU time 5.35 seconds
Started Feb 04 04:20:45 PM PST 24
Finished Feb 04 04:20:52 PM PST 24
Peak memory 217928 kb
Host smart-e3038540-1048-4c03-8b51-6f52034fbe3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662907760 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2662907760
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1610929707
Short name T818
Test name
Test status
Simulation time 56990613264 ps
CPU time 833.34 seconds
Started Feb 04 04:20:46 PM PST 24
Finished Feb 04 04:34:40 PM PST 24
Peak memory 223416 kb
Host smart-07686e8a-2932-46f2-8453-4fae49e0fbb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610929707 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1610929707
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.335789207
Short name T326
Test name
Test status
Simulation time 82237287 ps
CPU time 2.87 seconds
Started Feb 04 04:23:56 PM PST 24
Finished Feb 04 04:24:00 PM PST 24
Peak memory 216640 kb
Host smart-5d4cce24-81fc-40a3-864a-4711948d56c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335789207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.335789207
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.759324027
Short name T746
Test name
Test status
Simulation time 20902056 ps
CPU time 1.24 seconds
Started Feb 04 04:23:55 PM PST 24
Finished Feb 04 04:23:57 PM PST 24
Peak memory 215504 kb
Host smart-fccaa751-6891-4662-b201-226389d1a0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759324027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.759324027
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1537727459
Short name T313
Test name
Test status
Simulation time 23120319 ps
CPU time 1.2 seconds
Started Feb 04 04:23:57 PM PST 24
Finished Feb 04 04:24:00 PM PST 24
Peak memory 217904 kb
Host smart-71935ee2-a02c-4692-8923-618983a96c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537727459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1537727459
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.806422860
Short name T960
Test name
Test status
Simulation time 17732066 ps
CPU time 1.12 seconds
Started Feb 04 04:23:59 PM PST 24
Finished Feb 04 04:24:01 PM PST 24
Peak memory 215420 kb
Host smart-14d9eb7b-f42c-4202-be94-69da6bc028bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806422860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.806422860
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.2699350514
Short name T694
Test name
Test status
Simulation time 42200680 ps
CPU time 1.13 seconds
Started Feb 04 04:24:07 PM PST 24
Finished Feb 04 04:24:10 PM PST 24
Peak memory 215468 kb
Host smart-f870060d-df5c-48ec-adce-948baaba3e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699350514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.2699350514
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.957146396
Short name T505
Test name
Test status
Simulation time 18873087 ps
CPU time 1.13 seconds
Started Feb 04 04:24:08 PM PST 24
Finished Feb 04 04:24:11 PM PST 24
Peak memory 215324 kb
Host smart-dbe0d826-d79c-4374-8469-f998bdf02560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957146396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.957146396
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3837909211
Short name T630
Test name
Test status
Simulation time 57036633 ps
CPU time 1.32 seconds
Started Feb 04 04:24:10 PM PST 24
Finished Feb 04 04:24:17 PM PST 24
Peak memory 215324 kb
Host smart-5dd78d66-870a-4221-a20f-67c46cd449b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837909211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3837909211
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.780304991
Short name T472
Test name
Test status
Simulation time 118071022 ps
CPU time 1.02 seconds
Started Feb 04 04:24:06 PM PST 24
Finished Feb 04 04:24:10 PM PST 24
Peak memory 215316 kb
Host smart-bbcf728a-8457-415f-89b1-9d4515e25fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780304991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.780304991
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.4142650159
Short name T846
Test name
Test status
Simulation time 25721205 ps
CPU time 1.14 seconds
Started Feb 04 04:24:08 PM PST 24
Finished Feb 04 04:24:11 PM PST 24
Peak memory 215496 kb
Host smart-2149f7c7-c819-4575-a93e-777b58abf62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142650159 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.4142650159
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.917838260
Short name T273
Test name
Test status
Simulation time 21169886 ps
CPU time 1.21 seconds
Started Feb 04 04:24:07 PM PST 24
Finished Feb 04 04:24:10 PM PST 24
Peak memory 214936 kb
Host smart-12c25111-8485-4f02-8f6a-41777084e7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917838260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.917838260
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.33480312
Short name T675
Test name
Test status
Simulation time 36359348 ps
CPU time 1 seconds
Started Feb 04 04:20:56 PM PST 24
Finished Feb 04 04:21:00 PM PST 24
Peak memory 206708 kb
Host smart-a116962f-6d7f-4d45-a483-3c90e06e7d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33480312 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.33480312
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3464032721
Short name T583
Test name
Test status
Simulation time 29180331 ps
CPU time 0.94 seconds
Started Feb 04 04:20:54 PM PST 24
Finished Feb 04 04:21:00 PM PST 24
Peak memory 205880 kb
Host smart-ac7a891b-d45c-4e49-af28-6e0be12fc79a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464032721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3464032721
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.377269380
Short name T130
Test name
Test status
Simulation time 23994419 ps
CPU time 0.9 seconds
Started Feb 04 04:20:54 PM PST 24
Finished Feb 04 04:21:00 PM PST 24
Peak memory 215080 kb
Host smart-7e980ce4-7a77-4451-a80a-79c200539ae2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377269380 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.377269380
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.3977579472
Short name T804
Test name
Test status
Simulation time 18152901 ps
CPU time 0.99 seconds
Started Feb 04 04:20:59 PM PST 24
Finished Feb 04 04:21:02 PM PST 24
Peak memory 215284 kb
Host smart-4d981dd6-1bf5-4301-9bc7-b21f16fd0dab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977579472 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.3977579472
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.1516874794
Short name T872
Test name
Test status
Simulation time 30133555 ps
CPU time 1 seconds
Started Feb 04 04:20:55 PM PST 24
Finished Feb 04 04:21:00 PM PST 24
Peak memory 222440 kb
Host smart-8ca8c24a-6a79-45e3-a2e3-e9506cd5b99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516874794 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1516874794
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_intr.699684591
Short name T81
Test name
Test status
Simulation time 25069947 ps
CPU time 0.95 seconds
Started Feb 04 04:20:55 PM PST 24
Finished Feb 04 04:21:00 PM PST 24
Peak memory 215328 kb
Host smart-0daae17b-16c1-409b-af9b-4046d8ab188a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699684591 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.699684591
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.3246784271
Short name T887
Test name
Test status
Simulation time 45774583 ps
CPU time 0.97 seconds
Started Feb 04 04:20:56 PM PST 24
Finished Feb 04 04:21:00 PM PST 24
Peak memory 214920 kb
Host smart-51c2402c-ff87-4973-8b90-11710a760a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246784271 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.3246784271
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3673569093
Short name T781
Test name
Test status
Simulation time 33972209 ps
CPU time 1.38 seconds
Started Feb 04 04:20:53 PM PST 24
Finished Feb 04 04:21:00 PM PST 24
Peak memory 215232 kb
Host smart-bd20fa84-6995-43a5-8c81-a3d90d6c4626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673569093 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3673569093
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2061906656
Short name T459
Test name
Test status
Simulation time 296618478181 ps
CPU time 660.61 seconds
Started Feb 04 04:20:56 PM PST 24
Finished Feb 04 04:32:00 PM PST 24
Peak memory 218920 kb
Host smart-465173a2-e921-4033-b148-3b19f938ce5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061906656 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2061906656
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3688509309
Short name T482
Test name
Test status
Simulation time 205421458 ps
CPU time 2.99 seconds
Started Feb 04 04:24:09 PM PST 24
Finished Feb 04 04:24:18 PM PST 24
Peak memory 218204 kb
Host smart-e557f2de-eef2-4062-b62d-f9215241957e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688509309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3688509309
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1088119822
Short name T496
Test name
Test status
Simulation time 56644510 ps
CPU time 2.51 seconds
Started Feb 04 04:24:08 PM PST 24
Finished Feb 04 04:24:12 PM PST 24
Peak memory 215576 kb
Host smart-319543ea-8510-4a30-99c0-0b2c1d626722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088119822 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1088119822
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2803650938
Short name T572
Test name
Test status
Simulation time 23545256 ps
CPU time 1.24 seconds
Started Feb 04 04:24:06 PM PST 24
Finished Feb 04 04:24:09 PM PST 24
Peak memory 218116 kb
Host smart-a9f2b648-14be-41ed-873a-9c0133fb2ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803650938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2803650938
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1824899136
Short name T636
Test name
Test status
Simulation time 23651380 ps
CPU time 1.02 seconds
Started Feb 04 04:24:07 PM PST 24
Finished Feb 04 04:24:10 PM PST 24
Peak memory 216564 kb
Host smart-2ca6ca7f-150d-4928-ab5c-61c9bf1455a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824899136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1824899136
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.880682452
Short name T276
Test name
Test status
Simulation time 20127614 ps
CPU time 1.27 seconds
Started Feb 04 04:24:08 PM PST 24
Finished Feb 04 04:24:11 PM PST 24
Peak memory 216800 kb
Host smart-d1767887-f8d5-4d26-9bfd-0fe23e0a697f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880682452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.880682452
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2397924699
Short name T489
Test name
Test status
Simulation time 16428240 ps
CPU time 1.04 seconds
Started Feb 04 04:24:06 PM PST 24
Finished Feb 04 04:24:10 PM PST 24
Peak memory 215016 kb
Host smart-7d1130af-409f-455d-99d2-05ac3facc402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397924699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2397924699
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.4196830727
Short name T688
Test name
Test status
Simulation time 128794548 ps
CPU time 2.16 seconds
Started Feb 04 04:24:06 PM PST 24
Finished Feb 04 04:24:11 PM PST 24
Peak memory 216664 kb
Host smart-e97c891b-9529-411f-b6b5-d11daf5d6565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196830727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.4196830727
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3755417708
Short name T617
Test name
Test status
Simulation time 13592210 ps
CPU time 1.11 seconds
Started Feb 04 04:24:06 PM PST 24
Finished Feb 04 04:24:09 PM PST 24
Peak memory 216752 kb
Host smart-b9121e98-3c19-4edc-9ec7-6331b7940772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755417708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3755417708
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.88057886
Short name T908
Test name
Test status
Simulation time 55331868 ps
CPU time 1.05 seconds
Started Feb 04 04:24:07 PM PST 24
Finished Feb 04 04:24:10 PM PST 24
Peak memory 215484 kb
Host smart-aaf14e1e-db47-495e-b891-156336e4b348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88057886 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.88057886
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert_test.2989122686
Short name T596
Test name
Test status
Simulation time 69300773 ps
CPU time 1.06 seconds
Started Feb 04 04:20:55 PM PST 24
Finished Feb 04 04:21:00 PM PST 24
Peak memory 205336 kb
Host smart-c90e355a-a50a-4e99-990a-a0310eba842c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989122686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2989122686
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1787096948
Short name T146
Test name
Test status
Simulation time 76459331 ps
CPU time 0.82 seconds
Started Feb 04 04:21:01 PM PST 24
Finished Feb 04 04:21:03 PM PST 24
Peak memory 215052 kb
Host smart-84da6a2f-ebdb-4031-a421-a2abbc72f2e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787096948 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1787096948
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1575130858
Short name T966
Test name
Test status
Simulation time 31459560 ps
CPU time 1.11 seconds
Started Feb 04 04:21:01 PM PST 24
Finished Feb 04 04:21:03 PM PST 24
Peak memory 214804 kb
Host smart-fd0ee0b9-81d0-4ae4-b7ad-be66914293ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575130858 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1575130858
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1893527528
Short name T507
Test name
Test status
Simulation time 39814325 ps
CPU time 1.03 seconds
Started Feb 04 04:21:01 PM PST 24
Finished Feb 04 04:21:03 PM PST 24
Peak memory 222684 kb
Host smart-66d4a751-8264-435c-902b-5083c2a2ce2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893527528 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1893527528
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1434795636
Short name T824
Test name
Test status
Simulation time 48137692 ps
CPU time 1.35 seconds
Started Feb 04 04:20:57 PM PST 24
Finished Feb 04 04:21:00 PM PST 24
Peak memory 215584 kb
Host smart-1f9647d1-3c0e-4bb2-9019-99cd97b34136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434795636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1434795636
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.33551204
Short name T751
Test name
Test status
Simulation time 35149049 ps
CPU time 0.93 seconds
Started Feb 04 04:20:56 PM PST 24
Finished Feb 04 04:21:00 PM PST 24
Peak memory 214892 kb
Host smart-76cfc0b6-22d9-47eb-b84e-177722f43243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33551204 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.33551204
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3557652849
Short name T915
Test name
Test status
Simulation time 45537426 ps
CPU time 0.91 seconds
Started Feb 04 04:20:58 PM PST 24
Finished Feb 04 04:21:00 PM PST 24
Peak memory 214876 kb
Host smart-a7e88900-6d49-4216-a1c1-67693c596dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557652849 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3557652849
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.76510615
Short name T444
Test name
Test status
Simulation time 186349774 ps
CPU time 2.83 seconds
Started Feb 04 04:20:58 PM PST 24
Finished Feb 04 04:21:02 PM PST 24
Peak memory 215264 kb
Host smart-bcedc666-83ac-4e97-b0eb-16e363be1101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76510615 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.76510615
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1844933171
Short name T802
Test name
Test status
Simulation time 88921444746 ps
CPU time 1996.39 seconds
Started Feb 04 04:20:56 PM PST 24
Finished Feb 04 04:54:15 PM PST 24
Peak memory 225180 kb
Host smart-34ef3853-a497-48e6-a50e-085391a564e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844933171 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1844933171
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1775284753
Short name T905
Test name
Test status
Simulation time 17026462 ps
CPU time 1.26 seconds
Started Feb 04 04:24:07 PM PST 24
Finished Feb 04 04:24:10 PM PST 24
Peak memory 216732 kb
Host smart-b947049f-4003-4d83-aaf2-cba7046eed56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775284753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1775284753
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.90362044
Short name T483
Test name
Test status
Simulation time 22254533 ps
CPU time 1.23 seconds
Started Feb 04 04:24:09 PM PST 24
Finished Feb 04 04:24:16 PM PST 24
Peak memory 216700 kb
Host smart-ba5f59fa-5b08-4a7e-b354-b4c2bded2e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90362044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.90362044
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1493880626
Short name T527
Test name
Test status
Simulation time 49477055 ps
CPU time 0.96 seconds
Started Feb 04 04:24:10 PM PST 24
Finished Feb 04 04:24:16 PM PST 24
Peak memory 215276 kb
Host smart-1b7f7d56-9318-4f82-886b-3d89e4b1110f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493880626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1493880626
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3615213601
Short name T544
Test name
Test status
Simulation time 62601956 ps
CPU time 1.2 seconds
Started Feb 04 04:24:15 PM PST 24
Finished Feb 04 04:24:18 PM PST 24
Peak memory 215316 kb
Host smart-2ad473d4-bdf0-4538-9a9f-840555835295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615213601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3615213601
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.427210105
Short name T606
Test name
Test status
Simulation time 51953772 ps
CPU time 0.99 seconds
Started Feb 04 04:24:15 PM PST 24
Finished Feb 04 04:24:19 PM PST 24
Peak memory 215288 kb
Host smart-fe57412b-528e-4611-9b2a-cccc2fc1c93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427210105 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.427210105
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3223661912
Short name T828
Test name
Test status
Simulation time 209649780 ps
CPU time 1.24 seconds
Started Feb 04 04:24:15 PM PST 24
Finished Feb 04 04:24:19 PM PST 24
Peak memory 216740 kb
Host smart-2ae54949-6661-431d-ae29-1610635d02ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223661912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3223661912
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.315655599
Short name T518
Test name
Test status
Simulation time 16734708 ps
CPU time 1.07 seconds
Started Feb 04 04:24:17 PM PST 24
Finished Feb 04 04:24:20 PM PST 24
Peak memory 215588 kb
Host smart-54e5f366-b5c1-446c-9a07-1b476559f668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315655599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.315655599
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1839497653
Short name T667
Test name
Test status
Simulation time 48241673 ps
CPU time 1.33 seconds
Started Feb 04 04:24:20 PM PST 24
Finished Feb 04 04:24:23 PM PST 24
Peak memory 215388 kb
Host smart-622f7b3b-7897-4a81-b0f8-d8003c6cd75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839497653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1839497653
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2679343144
Short name T953
Test name
Test status
Simulation time 78953585 ps
CPU time 1.15 seconds
Started Feb 04 04:24:15 PM PST 24
Finished Feb 04 04:24:19 PM PST 24
Peak memory 217340 kb
Host smart-7e2e8dfc-e075-4bd8-b435-4b883cb37747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679343144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2679343144
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.696220252
Short name T522
Test name
Test status
Simulation time 73718951 ps
CPU time 1.32 seconds
Started Feb 04 04:24:10 PM PST 24
Finished Feb 04 04:24:17 PM PST 24
Peak memory 215096 kb
Host smart-14cfdb11-9bfd-40bf-a4b0-e41d614c9d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696220252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.696220252
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1682328203
Short name T825
Test name
Test status
Simulation time 50955756 ps
CPU time 1.02 seconds
Started Feb 04 04:21:07 PM PST 24
Finished Feb 04 04:21:09 PM PST 24
Peak memory 206656 kb
Host smart-3ce2bab0-63cf-4ab3-b008-bd845ac1ef38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682328203 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1682328203
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2031962284
Short name T747
Test name
Test status
Simulation time 13873123 ps
CPU time 1 seconds
Started Feb 04 04:21:12 PM PST 24
Finished Feb 04 04:21:16 PM PST 24
Peak memory 205932 kb
Host smart-a6fbb287-470c-489c-9005-03d28ddd40e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031962284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2031962284
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3767682104
Short name T834
Test name
Test status
Simulation time 78435140 ps
CPU time 0.97 seconds
Started Feb 04 04:21:10 PM PST 24
Finished Feb 04 04:21:12 PM PST 24
Peak memory 215184 kb
Host smart-a452c195-92b0-4156-bbb7-921cc70aa6e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767682104 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3767682104
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_intr.1448386204
Short name T934
Test name
Test status
Simulation time 53431275 ps
CPU time 1.55 seconds
Started Feb 04 04:21:10 PM PST 24
Finished Feb 04 04:21:13 PM PST 24
Peak memory 215016 kb
Host smart-e9e6512b-f4a1-48b5-b3ce-3786456efca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448386204 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1448386204
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.659978124
Short name T879
Test name
Test status
Simulation time 23279796 ps
CPU time 0.97 seconds
Started Feb 04 04:21:10 PM PST 24
Finished Feb 04 04:21:12 PM PST 24
Peak memory 214948 kb
Host smart-69c24920-e53a-4bb3-a294-fb818c9270b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659978124 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.659978124
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3461690530
Short name T639
Test name
Test status
Simulation time 52897562 ps
CPU time 0.92 seconds
Started Feb 04 04:21:10 PM PST 24
Finished Feb 04 04:21:12 PM PST 24
Peak memory 214936 kb
Host smart-7eef48ec-0378-4ffa-be0e-c70529f811af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461690530 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3461690530
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2762028446
Short name T782
Test name
Test status
Simulation time 22266336522 ps
CPU time 219.59 seconds
Started Feb 04 04:21:16 PM PST 24
Finished Feb 04 04:24:59 PM PST 24
Peak memory 223364 kb
Host smart-293cc2dd-306a-49eb-a12e-0f0c5551872b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762028446 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2762028446
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.78764408
Short name T45
Test name
Test status
Simulation time 248809652 ps
CPU time 1.26 seconds
Started Feb 04 04:24:17 PM PST 24
Finished Feb 04 04:24:20 PM PST 24
Peak memory 215036 kb
Host smart-721513c5-5497-448a-9d7c-969dc7888a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78764408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.78764408
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3482267280
Short name T461
Test name
Test status
Simulation time 78404400 ps
CPU time 1.37 seconds
Started Feb 04 04:24:15 PM PST 24
Finished Feb 04 04:24:19 PM PST 24
Peak memory 215468 kb
Host smart-7477b309-a9ee-472d-85c0-89690eecee07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482267280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3482267280
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1186138628
Short name T816
Test name
Test status
Simulation time 33183760 ps
CPU time 1.17 seconds
Started Feb 04 04:24:10 PM PST 24
Finished Feb 04 04:24:17 PM PST 24
Peak memory 214800 kb
Host smart-be28745f-8b10-4d84-b47d-aab208581345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186138628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1186138628
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.3471742689
Short name T455
Test name
Test status
Simulation time 52336796 ps
CPU time 0.95 seconds
Started Feb 04 04:24:19 PM PST 24
Finished Feb 04 04:24:21 PM PST 24
Peak memory 215160 kb
Host smart-63d673cd-804a-47c0-9755-2161db8ff630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471742689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.3471742689
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.174741384
Short name T652
Test name
Test status
Simulation time 14987822 ps
CPU time 1.04 seconds
Started Feb 04 04:24:14 PM PST 24
Finished Feb 04 04:24:17 PM PST 24
Peak memory 215208 kb
Host smart-97bbb4cf-759b-4126-9451-e355fc9870e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174741384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.174741384
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2429586299
Short name T44
Test name
Test status
Simulation time 23467788 ps
CPU time 1.27 seconds
Started Feb 04 04:24:17 PM PST 24
Finished Feb 04 04:24:20 PM PST 24
Peak memory 215316 kb
Host smart-75fb3507-c2dc-406c-aec7-f490c5631335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429586299 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2429586299
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1055981058
Short name T733
Test name
Test status
Simulation time 52178733 ps
CPU time 1.32 seconds
Started Feb 04 04:24:15 PM PST 24
Finished Feb 04 04:24:19 PM PST 24
Peak memory 216724 kb
Host smart-fd157f69-3094-42d8-ad55-f9ab30bf3014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055981058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1055981058
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.96256793
Short name T841
Test name
Test status
Simulation time 29628507 ps
CPU time 1.2 seconds
Started Feb 04 04:24:06 PM PST 24
Finished Feb 04 04:24:09 PM PST 24
Peak memory 216496 kb
Host smart-153a1ddc-f318-428e-9fde-7f339db8f6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96256793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.96256793
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1152686325
Short name T717
Test name
Test status
Simulation time 43311299 ps
CPU time 0.97 seconds
Started Feb 04 04:24:12 PM PST 24
Finished Feb 04 04:24:17 PM PST 24
Peak memory 215416 kb
Host smart-07140f4e-73b9-4f25-aefb-ace7fb4c11a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152686325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1152686325
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2911234697
Short name T875
Test name
Test status
Simulation time 28153033 ps
CPU time 1.46 seconds
Started Feb 04 04:24:14 PM PST 24
Finished Feb 04 04:24:17 PM PST 24
Peak memory 217764 kb
Host smart-845c995c-29bc-42d7-90bc-bed15e5763e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911234697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2911234697
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.796295101
Short name T613
Test name
Test status
Simulation time 59844244 ps
CPU time 1 seconds
Started Feb 04 04:21:16 PM PST 24
Finished Feb 04 04:21:20 PM PST 24
Peak memory 206632 kb
Host smart-99c65fd1-78e8-4723-9839-6d44b69170d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796295101 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.796295101
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3719940094
Short name T552
Test name
Test status
Simulation time 42076689 ps
CPU time 0.84 seconds
Started Feb 04 04:21:11 PM PST 24
Finished Feb 04 04:21:16 PM PST 24
Peak memory 205164 kb
Host smart-a6d23c17-e9cf-48b4-8f69-6ade07ad84e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719940094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3719940094
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1351125672
Short name T169
Test name
Test status
Simulation time 34503491 ps
CPU time 0.83 seconds
Started Feb 04 04:21:13 PM PST 24
Finished Feb 04 04:21:17 PM PST 24
Peak memory 215040 kb
Host smart-e569b1d8-75dc-4bf5-aab3-cee9d6960142
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351125672 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1351125672
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3674686250
Short name T625
Test name
Test status
Simulation time 23893757 ps
CPU time 1.08 seconds
Started Feb 04 04:21:21 PM PST 24
Finished Feb 04 04:21:29 PM PST 24
Peak memory 216380 kb
Host smart-6e2b39f1-3f34-4aef-a201-7fd4a7273870
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674686250 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3674686250
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.3510323544
Short name T109
Test name
Test status
Simulation time 43635751 ps
CPU time 1.17 seconds
Started Feb 04 04:21:14 PM PST 24
Finished Feb 04 04:21:17 PM PST 24
Peak memory 222684 kb
Host smart-13aa2651-e6b6-476d-8903-3a22a6effe6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510323544 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3510323544
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.4227833708
Short name T888
Test name
Test status
Simulation time 96829868 ps
CPU time 1.16 seconds
Started Feb 04 04:21:16 PM PST 24
Finished Feb 04 04:21:20 PM PST 24
Peak memory 216616 kb
Host smart-7e2fa8a6-78bb-47e0-a38d-cc65e915e33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227833708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.4227833708
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.724097769
Short name T961
Test name
Test status
Simulation time 49560791 ps
CPU time 0.81 seconds
Started Feb 04 04:21:17 PM PST 24
Finished Feb 04 04:21:21 PM PST 24
Peak memory 215048 kb
Host smart-51111b92-f9fc-4876-b8f4-c1588b3e1d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724097769 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.724097769
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2448369823
Short name T448
Test name
Test status
Simulation time 18228178 ps
CPU time 0.99 seconds
Started Feb 04 04:21:07 PM PST 24
Finished Feb 04 04:21:09 PM PST 24
Peak memory 214928 kb
Host smart-72260e37-a8a6-4d2c-81f0-3b5ded6b181c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448369823 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2448369823
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2141406063
Short name T822
Test name
Test status
Simulation time 1871744348 ps
CPU time 3.4 seconds
Started Feb 04 04:21:17 PM PST 24
Finished Feb 04 04:21:23 PM PST 24
Peak memory 215356 kb
Host smart-8f75552d-2834-4474-90b8-169148be8b5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141406063 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2141406063
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2819424727
Short name T857
Test name
Test status
Simulation time 44899434972 ps
CPU time 562.95 seconds
Started Feb 04 04:21:18 PM PST 24
Finished Feb 04 04:30:43 PM PST 24
Peak memory 217448 kb
Host smart-82c16eb5-dd05-48ca-bb0c-64a596116b60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819424727 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2819424727
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.415776935
Short name T295
Test name
Test status
Simulation time 35434686 ps
CPU time 1.02 seconds
Started Feb 04 04:24:16 PM PST 24
Finished Feb 04 04:24:19 PM PST 24
Peak memory 215328 kb
Host smart-4b25e510-1b5a-4fc9-986c-ec422fa51d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415776935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.415776935
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2618293298
Short name T274
Test name
Test status
Simulation time 21526160 ps
CPU time 1.19 seconds
Started Feb 04 04:24:11 PM PST 24
Finished Feb 04 04:24:17 PM PST 24
Peak memory 215564 kb
Host smart-261dcc9c-e5de-4a8d-ba9e-bde83da00708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618293298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2618293298
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.2022147961
Short name T944
Test name
Test status
Simulation time 39706390 ps
CPU time 1.11 seconds
Started Feb 04 04:24:22 PM PST 24
Finished Feb 04 04:24:24 PM PST 24
Peak memory 215516 kb
Host smart-1996f795-f759-4f72-96d9-14014805460d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022147961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.2022147961
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2779933884
Short name T642
Test name
Test status
Simulation time 38421296 ps
CPU time 1.36 seconds
Started Feb 04 04:24:13 PM PST 24
Finished Feb 04 04:24:17 PM PST 24
Peak memory 215272 kb
Host smart-338d97eb-b69f-40e7-a712-cf61226d6a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779933884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2779933884
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1024301639
Short name T799
Test name
Test status
Simulation time 17356063 ps
CPU time 1.22 seconds
Started Feb 04 04:24:15 PM PST 24
Finished Feb 04 04:24:19 PM PST 24
Peak memory 216732 kb
Host smart-1e22e5f6-a17a-460b-8218-fb2cc861cdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024301639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1024301639
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1402287190
Short name T301
Test name
Test status
Simulation time 60731490 ps
CPU time 1.09 seconds
Started Feb 04 04:24:15 PM PST 24
Finished Feb 04 04:24:18 PM PST 24
Peak memory 215248 kb
Host smart-1cc985e7-f3e7-4f75-b642-a4847d364113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402287190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1402287190
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2068532900
Short name T697
Test name
Test status
Simulation time 53748117 ps
CPU time 1.09 seconds
Started Feb 04 04:24:08 PM PST 24
Finished Feb 04 04:24:10 PM PST 24
Peak memory 215040 kb
Host smart-526d37c0-29c8-47e5-8b1c-45a44dbd19e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068532900 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2068532900
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.536519484
Short name T819
Test name
Test status
Simulation time 41026692 ps
CPU time 1.25 seconds
Started Feb 04 04:24:11 PM PST 24
Finished Feb 04 04:24:17 PM PST 24
Peak memory 216680 kb
Host smart-1b0efa05-5ce4-44d0-96a5-dbceffb0cccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536519484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.536519484
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.1418633963
Short name T279
Test name
Test status
Simulation time 57874765 ps
CPU time 1.16 seconds
Started Feb 04 04:24:16 PM PST 24
Finished Feb 04 04:24:19 PM PST 24
Peak memory 218108 kb
Host smart-34733f11-8a29-4837-b7ee-a5b911c12fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418633963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1418633963
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2461094092
Short name T883
Test name
Test status
Simulation time 127164585 ps
CPU time 1.15 seconds
Started Feb 04 04:24:12 PM PST 24
Finished Feb 04 04:24:17 PM PST 24
Peak memory 216848 kb
Host smart-021c083f-2044-4160-88ab-d53623c1b57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461094092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2461094092
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.1651045310
Short name T726
Test name
Test status
Simulation time 27810196 ps
CPU time 0.98 seconds
Started Feb 04 04:21:13 PM PST 24
Finished Feb 04 04:21:17 PM PST 24
Peak memory 206056 kb
Host smart-f74f00d7-a0b9-4e9b-a03e-45333ab61446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651045310 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.1651045310
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1521874866
Short name T94
Test name
Test status
Simulation time 15233084 ps
CPU time 0.91 seconds
Started Feb 04 04:21:13 PM PST 24
Finished Feb 04 04:21:17 PM PST 24
Peak memory 205320 kb
Host smart-854c6d4c-62c9-4423-b7e9-15b6660dd6bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521874866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1521874866
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2127179925
Short name T152
Test name
Test status
Simulation time 12750789 ps
CPU time 0.94 seconds
Started Feb 04 04:21:12 PM PST 24
Finished Feb 04 04:21:17 PM PST 24
Peak memory 215012 kb
Host smart-53960886-9786-4972-8dbf-9c96d93bc2f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127179925 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2127179925
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3657555759
Short name T701
Test name
Test status
Simulation time 23768235 ps
CPU time 1.08 seconds
Started Feb 04 04:21:21 PM PST 24
Finished Feb 04 04:21:28 PM PST 24
Peak memory 215256 kb
Host smart-237cb831-44be-4c22-8a07-ad8cf61d4503
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657555759 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3657555759
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3983863908
Short name T860
Test name
Test status
Simulation time 45893543 ps
CPU time 1.11 seconds
Started Feb 04 04:21:21 PM PST 24
Finished Feb 04 04:21:28 PM PST 24
Peak memory 217680 kb
Host smart-b74fc6e8-eb0f-422f-90ca-834ffc1f7aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983863908 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3983863908
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1278643531
Short name T469
Test name
Test status
Simulation time 16629835 ps
CPU time 0.96 seconds
Started Feb 04 04:21:16 PM PST 24
Finished Feb 04 04:21:20 PM PST 24
Peak memory 214936 kb
Host smart-42fb2eaa-58df-424e-a5dd-ee07696910cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278643531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1278643531
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.3351495896
Short name T755
Test name
Test status
Simulation time 34739834 ps
CPU time 0.96 seconds
Started Feb 04 04:21:12 PM PST 24
Finished Feb 04 04:21:17 PM PST 24
Peak memory 214880 kb
Host smart-2a6d6328-4c2f-415f-ab33-4130cd478113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351495896 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.3351495896
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.2069631063
Short name T50
Test name
Test status
Simulation time 71504687 ps
CPU time 0.91 seconds
Started Feb 04 04:21:10 PM PST 24
Finished Feb 04 04:21:12 PM PST 24
Peak memory 206740 kb
Host smart-34d4d989-5bf2-4080-bf88-c25a53c5edc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069631063 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.2069631063
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.309851199
Short name T734
Test name
Test status
Simulation time 74848942 ps
CPU time 2.11 seconds
Started Feb 04 04:21:11 PM PST 24
Finished Feb 04 04:21:14 PM PST 24
Peak memory 215256 kb
Host smart-f3b66c43-e6d0-4a00-a03b-cf79648295ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309851199 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.309851199
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3583773538
Short name T940
Test name
Test status
Simulation time 53089601957 ps
CPU time 1276.27 seconds
Started Feb 04 04:21:12 PM PST 24
Finished Feb 04 04:42:32 PM PST 24
Peak memory 221464 kb
Host smart-010fdbae-48eb-4842-80b7-7c3b8f519ce2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583773538 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3583773538
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/291.edn_genbits.1529386891
Short name T278
Test name
Test status
Simulation time 75542044 ps
CPU time 1.95 seconds
Started Feb 04 04:24:15 PM PST 24
Finished Feb 04 04:24:18 PM PST 24
Peak memory 214892 kb
Host smart-bac2069a-9415-46a7-8e5b-838bce78dc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529386891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.1529386891
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1277114999
Short name T264
Test name
Test status
Simulation time 15948750 ps
CPU time 1.02 seconds
Started Feb 04 04:24:07 PM PST 24
Finished Feb 04 04:24:10 PM PST 24
Peak memory 215320 kb
Host smart-ca304d7c-7c51-4f4d-b7b4-88d2cd007f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277114999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1277114999
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2385047469
Short name T676
Test name
Test status
Simulation time 33552368 ps
CPU time 1.11 seconds
Started Feb 04 04:24:20 PM PST 24
Finished Feb 04 04:24:23 PM PST 24
Peak memory 216544 kb
Host smart-cfc95fb5-d93b-4d17-af2b-271d58df9598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385047469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2385047469
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3331009827
Short name T302
Test name
Test status
Simulation time 18908380 ps
CPU time 1.07 seconds
Started Feb 04 04:24:13 PM PST 24
Finished Feb 04 04:24:17 PM PST 24
Peak memory 215384 kb
Host smart-e999355c-508d-4216-80ca-06742329bb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331009827 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3331009827
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2635350551
Short name T526
Test name
Test status
Simulation time 21717634 ps
CPU time 1.24 seconds
Started Feb 04 04:24:11 PM PST 24
Finished Feb 04 04:24:17 PM PST 24
Peak memory 215352 kb
Host smart-cc45b2a7-4c38-4b27-aa5a-bace7cf267b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635350551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2635350551
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1013333823
Short name T942
Test name
Test status
Simulation time 61070434 ps
CPU time 1.11 seconds
Started Feb 04 04:24:15 PM PST 24
Finished Feb 04 04:24:19 PM PST 24
Peak memory 215676 kb
Host smart-19814e84-9971-4554-a3bf-f174845c655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013333823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1013333823
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.332919832
Short name T519
Test name
Test status
Simulation time 92989799 ps
CPU time 1.05 seconds
Started Feb 04 04:24:20 PM PST 24
Finished Feb 04 04:24:22 PM PST 24
Peak memory 216616 kb
Host smart-1f448a94-d816-440e-9477-276fd55a082f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332919832 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.332919832
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2185672371
Short name T880
Test name
Test status
Simulation time 27215003 ps
CPU time 1.07 seconds
Started Feb 04 04:24:15 PM PST 24
Finished Feb 04 04:24:18 PM PST 24
Peak memory 215412 kb
Host smart-009c3194-163a-4e5c-805d-51646018cdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185672371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2185672371
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.651379771
Short name T884
Test name
Test status
Simulation time 17081453 ps
CPU time 0.99 seconds
Started Feb 04 04:24:17 PM PST 24
Finished Feb 04 04:24:20 PM PST 24
Peak memory 215244 kb
Host smart-a65a2f22-f16e-4aeb-bf0a-327ba6ac432e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651379771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.651379771
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.4081720412
Short name T848
Test name
Test status
Simulation time 31939544 ps
CPU time 1.07 seconds
Started Feb 04 04:19:13 PM PST 24
Finished Feb 04 04:19:15 PM PST 24
Peak memory 206648 kb
Host smart-c755db21-c20f-42ce-a3bf-4324a84c44b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081720412 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.4081720412
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.918892110
Short name T619
Test name
Test status
Simulation time 59810132 ps
CPU time 0.96 seconds
Started Feb 04 04:19:17 PM PST 24
Finished Feb 04 04:19:20 PM PST 24
Peak memory 205860 kb
Host smart-a60d1d04-4b9b-4997-ae88-6f592263c0c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918892110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.918892110
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1897026173
Short name T129
Test name
Test status
Simulation time 9965395 ps
CPU time 0.9 seconds
Started Feb 04 04:19:11 PM PST 24
Finished Feb 04 04:19:13 PM PST 24
Peak memory 215032 kb
Host smart-679acfa9-560d-4e11-89f0-8fa546d37dc3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897026173 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1897026173
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_err.3347581582
Short name T100
Test name
Test status
Simulation time 42557883 ps
CPU time 1.08 seconds
Started Feb 04 04:19:11 PM PST 24
Finished Feb 04 04:19:13 PM PST 24
Peak memory 216912 kb
Host smart-8c541509-4aba-4e6c-876e-96b828258f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347581582 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.3347581582
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1470272017
Short name T297
Test name
Test status
Simulation time 48910655 ps
CPU time 1.79 seconds
Started Feb 04 04:19:09 PM PST 24
Finished Feb 04 04:19:12 PM PST 24
Peak memory 215608 kb
Host smart-8c64f702-080a-435c-9847-2eec1c1072d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470272017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1470272017
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1366508668
Short name T788
Test name
Test status
Simulation time 48221975 ps
CPU time 0.9 seconds
Started Feb 04 04:19:14 PM PST 24
Finished Feb 04 04:19:17 PM PST 24
Peak memory 215116 kb
Host smart-fb2c3d94-17f2-4c59-b1bc-27dc376b724d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366508668 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1366508668
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.3580679614
Short name T288
Test name
Test status
Simulation time 28563115 ps
CPU time 0.96 seconds
Started Feb 04 04:19:06 PM PST 24
Finished Feb 04 04:19:09 PM PST 24
Peak memory 206656 kb
Host smart-985b104c-f4ec-435d-8232-e60ab90546c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580679614 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3580679614
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.618637757
Short name T62
Test name
Test status
Simulation time 536466680 ps
CPU time 8.77 seconds
Started Feb 04 04:19:09 PM PST 24
Finished Feb 04 04:19:19 PM PST 24
Peak memory 233996 kb
Host smart-af959f59-44b4-4d04-89e5-697cb79b0b8d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618637757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.618637757
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.1242205691
Short name T3
Test name
Test status
Simulation time 20811706 ps
CPU time 0.93 seconds
Started Feb 04 04:19:03 PM PST 24
Finished Feb 04 04:19:09 PM PST 24
Peak memory 214948 kb
Host smart-1b450dbf-ff2a-467d-aa87-037ded36545f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242205691 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1242205691
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.125419558
Short name T904
Test name
Test status
Simulation time 167662672 ps
CPU time 3.57 seconds
Started Feb 04 04:19:11 PM PST 24
Finished Feb 04 04:19:16 PM PST 24
Peak memory 215372 kb
Host smart-97b4d402-3ed4-4ef4-b873-6a44c09e62be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125419558 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.125419558
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3295557820
Short name T89
Test name
Test status
Simulation time 23344996610 ps
CPU time 538.55 seconds
Started Feb 04 04:19:16 PM PST 24
Finished Feb 04 04:28:17 PM PST 24
Peak memory 217052 kb
Host smart-adb07246-4a0e-45dc-a044-96d49cfa1f2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295557820 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3295557820
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2486707858
Short name T245
Test name
Test status
Simulation time 70158859 ps
CPU time 0.95 seconds
Started Feb 04 04:21:16 PM PST 24
Finished Feb 04 04:21:20 PM PST 24
Peak memory 206588 kb
Host smart-18fa3d89-2b92-44ac-bdd9-3890b059fc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486707858 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2486707858
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.3993415466
Short name T427
Test name
Test status
Simulation time 17990030 ps
CPU time 0.83 seconds
Started Feb 04 04:21:22 PM PST 24
Finished Feb 04 04:21:28 PM PST 24
Peak memory 205028 kb
Host smart-c982eff8-26ad-4831-b71c-bcad56342edd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993415466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.3993415466
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.4145195721
Short name T780
Test name
Test status
Simulation time 26008578 ps
CPU time 0.87 seconds
Started Feb 04 04:21:25 PM PST 24
Finished Feb 04 04:21:29 PM PST 24
Peak memory 215176 kb
Host smart-2d1fac7a-c1ff-407e-bb26-6a2c3b625235
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145195721 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.4145195721
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.746713120
Short name T119
Test name
Test status
Simulation time 105041780 ps
CPU time 1.17 seconds
Started Feb 04 04:21:20 PM PST 24
Finished Feb 04 04:21:22 PM PST 24
Peak memory 215276 kb
Host smart-6063cd52-bfa1-483b-a40c-724f48815a25
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746713120 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.746713120
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1575626479
Short name T869
Test name
Test status
Simulation time 18921674 ps
CPU time 0.99 seconds
Started Feb 04 04:21:19 PM PST 24
Finished Feb 04 04:21:22 PM PST 24
Peak memory 216444 kb
Host smart-6dfff24a-04c9-42ce-bafe-ddca4ef4b3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575626479 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1575626479
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1459204926
Short name T736
Test name
Test status
Simulation time 77190844 ps
CPU time 1.14 seconds
Started Feb 04 04:21:17 PM PST 24
Finished Feb 04 04:21:21 PM PST 24
Peak memory 215132 kb
Host smart-d71260af-737b-44a2-93fd-87a4ec8d2242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459204926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1459204926
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1101167375
Short name T77
Test name
Test status
Simulation time 33448325 ps
CPU time 0.94 seconds
Started Feb 04 04:21:13 PM PST 24
Finished Feb 04 04:21:17 PM PST 24
Peak memory 215136 kb
Host smart-634c9829-0d44-41ea-bc62-b87721494d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101167375 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1101167375
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1845302465
Short name T633
Test name
Test status
Simulation time 19383211 ps
CPU time 1.04 seconds
Started Feb 04 04:21:10 PM PST 24
Finished Feb 04 04:21:12 PM PST 24
Peak memory 214916 kb
Host smart-d53a1567-aae3-4465-bcb5-b318f2e7359c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845302465 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1845302465
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3143438491
Short name T51
Test name
Test status
Simulation time 334903957 ps
CPU time 3.72 seconds
Started Feb 04 04:21:09 PM PST 24
Finished Feb 04 04:21:14 PM PST 24
Peak memory 215452 kb
Host smart-236e09bb-7cb0-4f9f-87d5-ec897b4496ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143438491 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3143438491
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.457490110
Short name T702
Test name
Test status
Simulation time 36401004362 ps
CPU time 804.8 seconds
Started Feb 04 04:21:27 PM PST 24
Finished Feb 04 04:34:53 PM PST 24
Peak memory 216888 kb
Host smart-d3c9abf2-8b5b-42fa-838d-080a861d6b6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457490110 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.457490110
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.3606035382
Short name T968
Test name
Test status
Simulation time 19788408 ps
CPU time 1.08 seconds
Started Feb 04 04:21:26 PM PST 24
Finished Feb 04 04:21:29 PM PST 24
Peak memory 206620 kb
Host smart-f63c0efc-5215-4321-b00b-9a35f241a399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606035382 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.3606035382
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3923153549
Short name T59
Test name
Test status
Simulation time 14628080 ps
CPU time 0.99 seconds
Started Feb 04 04:21:27 PM PST 24
Finished Feb 04 04:21:29 PM PST 24
Peak memory 205356 kb
Host smart-20e499b0-80bb-474c-92b7-185f8fc5aa42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923153549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3923153549
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2448436451
Short name T179
Test name
Test status
Simulation time 11591356 ps
CPU time 0.91 seconds
Started Feb 04 04:21:21 PM PST 24
Finished Feb 04 04:21:28 PM PST 24
Peak memory 215064 kb
Host smart-345500e4-d25f-4892-ad7d-ae780c0263dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448436451 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2448436451
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.2345822778
Short name T919
Test name
Test status
Simulation time 22366415 ps
CPU time 1.09 seconds
Started Feb 04 04:21:27 PM PST 24
Finished Feb 04 04:21:29 PM PST 24
Peak memory 216556 kb
Host smart-137b8777-792a-4f3e-bd88-d3dbe8ec88e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345822778 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.2345822778
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2500585566
Short name T829
Test name
Test status
Simulation time 17864351 ps
CPU time 1.12 seconds
Started Feb 04 04:21:29 PM PST 24
Finished Feb 04 04:21:31 PM PST 24
Peak memory 215004 kb
Host smart-3f4e757c-dd7d-449b-a792-5837d5b003f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500585566 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2500585566
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3169857324
Short name T814
Test name
Test status
Simulation time 55475449 ps
CPU time 1.13 seconds
Started Feb 04 04:21:25 PM PST 24
Finished Feb 04 04:21:29 PM PST 24
Peak memory 216516 kb
Host smart-8218a2f4-ba1b-470f-a7b2-e16851337fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169857324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3169857324
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.717087929
Short name T76
Test name
Test status
Simulation time 20621047 ps
CPU time 0.92 seconds
Started Feb 04 04:21:26 PM PST 24
Finished Feb 04 04:21:29 PM PST 24
Peak memory 215308 kb
Host smart-01bd5365-4511-403b-b332-e3e1ba44ee77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717087929 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.717087929
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2345297146
Short name T666
Test name
Test status
Simulation time 34905270 ps
CPU time 0.85 seconds
Started Feb 04 04:21:26 PM PST 24
Finished Feb 04 04:21:29 PM PST 24
Peak memory 214764 kb
Host smart-fc998059-6cc4-42c9-9483-5aa690eb8696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345297146 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2345297146
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.614291613
Short name T534
Test name
Test status
Simulation time 1926303419 ps
CPU time 3.88 seconds
Started Feb 04 04:21:19 PM PST 24
Finished Feb 04 04:21:25 PM PST 24
Peak memory 215428 kb
Host smart-1f4d4d09-5db3-4363-98cf-ccab06c7f0cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614291613 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.614291613
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.497564040
Short name T65
Test name
Test status
Simulation time 30071821743 ps
CPU time 363.53 seconds
Started Feb 04 04:21:28 PM PST 24
Finished Feb 04 04:27:33 PM PST 24
Peak memory 216120 kb
Host smart-b1aee01d-722b-4da3-aa85-347c9466d767
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497564040 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.497564040
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.699188969
Short name T946
Test name
Test status
Simulation time 22528757 ps
CPU time 1.05 seconds
Started Feb 04 04:21:25 PM PST 24
Finished Feb 04 04:21:29 PM PST 24
Peak memory 206656 kb
Host smart-8a76766d-dfda-4fd8-a4d0-3a813343369b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699188969 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.699188969
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3486644824
Short name T963
Test name
Test status
Simulation time 39605551 ps
CPU time 0.93 seconds
Started Feb 04 04:21:30 PM PST 24
Finished Feb 04 04:21:32 PM PST 24
Peak memory 205268 kb
Host smart-a8e84d96-8a00-4999-baeb-b8b5b13503da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486644824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3486644824
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2517419519
Short name T141
Test name
Test status
Simulation time 24079647 ps
CPU time 0.9 seconds
Started Feb 04 04:21:28 PM PST 24
Finished Feb 04 04:21:31 PM PST 24
Peak memory 215056 kb
Host smart-70d418d6-a62f-4ca3-abef-3fa733957048
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517419519 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2517419519
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.2349095864
Short name T103
Test name
Test status
Simulation time 65033461 ps
CPU time 1.23 seconds
Started Feb 04 04:21:28 PM PST 24
Finished Feb 04 04:21:31 PM PST 24
Peak memory 216352 kb
Host smart-6cc3b955-2167-473e-87db-516af7f4cbb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349095864 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.2349095864
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_genbits.1810463084
Short name T309
Test name
Test status
Simulation time 31468907 ps
CPU time 1.13 seconds
Started Feb 04 04:21:31 PM PST 24
Finished Feb 04 04:21:35 PM PST 24
Peak memory 216540 kb
Host smart-6d8329ac-1b09-4cd1-9323-5ae671eb3a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810463084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1810463084
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.312031856
Short name T54
Test name
Test status
Simulation time 22452087 ps
CPU time 1.03 seconds
Started Feb 04 04:21:19 PM PST 24
Finished Feb 04 04:21:22 PM PST 24
Peak memory 222580 kb
Host smart-096aa49c-67c7-4e1d-abd0-7b240e469e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312031856 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.312031856
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3030306921
Short name T586
Test name
Test status
Simulation time 12979660 ps
CPU time 0.95 seconds
Started Feb 04 04:21:25 PM PST 24
Finished Feb 04 04:21:29 PM PST 24
Peak memory 214932 kb
Host smart-6ee501ca-9c82-4bdb-866a-ba712210fe6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030306921 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3030306921
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3545799848
Short name T510
Test name
Test status
Simulation time 159857244 ps
CPU time 4.39 seconds
Started Feb 04 04:21:26 PM PST 24
Finished Feb 04 04:21:32 PM PST 24
Peak memory 215008 kb
Host smart-46c5c6c6-7b9e-4f50-8f6e-3b5cbf03d77f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545799848 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3545799848
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_alert.3313326650
Short name T784
Test name
Test status
Simulation time 55079355 ps
CPU time 1.03 seconds
Started Feb 04 04:21:29 PM PST 24
Finished Feb 04 04:21:31 PM PST 24
Peak memory 206596 kb
Host smart-8a7fac1f-14a1-47f6-8fd9-64e21883bf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313326650 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3313326650
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.963786857
Short name T951
Test name
Test status
Simulation time 35661704 ps
CPU time 0.96 seconds
Started Feb 04 04:21:38 PM PST 24
Finished Feb 04 04:21:40 PM PST 24
Peak memory 205296 kb
Host smart-60861bef-d16f-42ca-9aae-4c440a4f4468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963786857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.963786857
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.854692034
Short name T900
Test name
Test status
Simulation time 27897554 ps
CPU time 1.16 seconds
Started Feb 04 04:21:36 PM PST 24
Finished Feb 04 04:21:39 PM PST 24
Peak memory 217644 kb
Host smart-00ef7a57-6409-4aa0-a8ff-b26b11528a68
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854692034 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.854692034
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1115483594
Short name T854
Test name
Test status
Simulation time 26182812 ps
CPU time 1.09 seconds
Started Feb 04 04:21:35 PM PST 24
Finished Feb 04 04:21:38 PM PST 24
Peak memory 215380 kb
Host smart-e35218f9-50af-49b3-bc09-9f9195220462
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115483594 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1115483594
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.4172176247
Short name T156
Test name
Test status
Simulation time 29653361 ps
CPU time 0.98 seconds
Started Feb 04 04:21:31 PM PST 24
Finished Feb 04 04:21:36 PM PST 24
Peak memory 216788 kb
Host smart-1187abf7-4d6e-4716-9ab5-94a78579f7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172176247 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.4172176247
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1986459503
Short name T920
Test name
Test status
Simulation time 146722124 ps
CPU time 1.2 seconds
Started Feb 04 04:21:30 PM PST 24
Finished Feb 04 04:21:32 PM PST 24
Peak memory 215224 kb
Host smart-0e25088f-f0da-4e64-a5ca-663e2007f50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986459503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1986459503
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.993759504
Short name T83
Test name
Test status
Simulation time 27937762 ps
CPU time 0.9 seconds
Started Feb 04 04:21:29 PM PST 24
Finished Feb 04 04:21:31 PM PST 24
Peak memory 215124 kb
Host smart-625bf644-df74-479c-89e9-11d78a2bc440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993759504 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.993759504
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1173993424
Short name T434
Test name
Test status
Simulation time 15683743 ps
CPU time 1.04 seconds
Started Feb 04 04:21:31 PM PST 24
Finished Feb 04 04:21:34 PM PST 24
Peak memory 214968 kb
Host smart-704b8718-e656-4b50-a3a1-8673a20649a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173993424 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1173993424
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3868139310
Short name T435
Test name
Test status
Simulation time 78219355 ps
CPU time 1.12 seconds
Started Feb 04 04:21:28 PM PST 24
Finished Feb 04 04:21:31 PM PST 24
Peak memory 215000 kb
Host smart-93e83fed-1d9c-4775-974c-e0d910cd7729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868139310 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3868139310
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1347099144
Short name T308
Test name
Test status
Simulation time 82895499293 ps
CPU time 1891 seconds
Started Feb 04 04:21:30 PM PST 24
Finished Feb 04 04:53:04 PM PST 24
Peak memory 224120 kb
Host smart-47f8843e-4c17-446b-976a-0c8e97e5170e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347099144 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1347099144
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2870787854
Short name T244
Test name
Test status
Simulation time 43655934 ps
CPU time 1.01 seconds
Started Feb 04 04:21:36 PM PST 24
Finished Feb 04 04:21:38 PM PST 24
Peak memory 206776 kb
Host smart-75f49041-c25a-4219-9c25-e741b8e2f0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870787854 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2870787854
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.4024311334
Short name T579
Test name
Test status
Simulation time 22042750 ps
CPU time 1.01 seconds
Started Feb 04 04:21:35 PM PST 24
Finished Feb 04 04:21:37 PM PST 24
Peak memory 205384 kb
Host smart-aa388cdf-2b2d-4694-985a-4831db38de0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024311334 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.4024311334
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2493574066
Short name T88
Test name
Test status
Simulation time 38756537 ps
CPU time 0.85 seconds
Started Feb 04 04:21:38 PM PST 24
Finished Feb 04 04:21:40 PM PST 24
Peak memory 215000 kb
Host smart-4c04ac3b-afca-4572-b627-a53100da6874
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493574066 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2493574066
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.3532981312
Short name T106
Test name
Test status
Simulation time 115579044 ps
CPU time 1.14 seconds
Started Feb 04 04:21:42 PM PST 24
Finished Feb 04 04:21:43 PM PST 24
Peak memory 215216 kb
Host smart-949abfc3-aaeb-4d27-a8fd-227e57199d77
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532981312 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.3532981312
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3046286296
Short name T111
Test name
Test status
Simulation time 23184698 ps
CPU time 1.16 seconds
Started Feb 04 04:21:40 PM PST 24
Finished Feb 04 04:21:42 PM PST 24
Peak memory 216900 kb
Host smart-0cb95421-ea44-4035-b393-f10638234557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046286296 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3046286296
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_intr.3095803497
Short name T436
Test name
Test status
Simulation time 19949540 ps
CPU time 1.06 seconds
Started Feb 04 04:21:34 PM PST 24
Finished Feb 04 04:21:37 PM PST 24
Peak memory 215192 kb
Host smart-3fab6da5-6772-438f-b5d0-f15d3bc9bc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095803497 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3095803497
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3784694111
Short name T589
Test name
Test status
Simulation time 33024324 ps
CPU time 0.85 seconds
Started Feb 04 04:21:38 PM PST 24
Finished Feb 04 04:21:40 PM PST 24
Peak memory 214740 kb
Host smart-16fea7ec-c2e4-4008-8995-a35cfc6edcb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784694111 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3784694111
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.3144886452
Short name T433
Test name
Test status
Simulation time 150923378 ps
CPU time 3.7 seconds
Started Feb 04 04:21:39 PM PST 24
Finished Feb 04 04:21:43 PM PST 24
Peak memory 215220 kb
Host smart-4e31ec0d-bad5-4aec-930c-9f599628785f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144886452 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.3144886452
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.3614969129
Short name T876
Test name
Test status
Simulation time 68271881191 ps
CPU time 918.48 seconds
Started Feb 04 04:21:33 PM PST 24
Finished Feb 04 04:36:55 PM PST 24
Peak memory 220512 kb
Host smart-b556319f-7803-4a36-a6c4-84ba1050e300
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614969129 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.3614969129
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3851121313
Short name T807
Test name
Test status
Simulation time 209929104 ps
CPU time 0.99 seconds
Started Feb 04 04:21:37 PM PST 24
Finished Feb 04 04:21:39 PM PST 24
Peak memory 206660 kb
Host smart-68df2dfe-8ab9-4823-b420-e3cb4820d41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851121313 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3851121313
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2663447874
Short name T61
Test name
Test status
Simulation time 25226487 ps
CPU time 0.85 seconds
Started Feb 04 04:21:36 PM PST 24
Finished Feb 04 04:21:38 PM PST 24
Peak memory 205292 kb
Host smart-6df9cdb7-b8ff-48da-b62c-5289c2c71564
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663447874 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2663447874
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1039115935
Short name T918
Test name
Test status
Simulation time 17148184 ps
CPU time 0.83 seconds
Started Feb 04 04:21:36 PM PST 24
Finished Feb 04 04:21:38 PM PST 24
Peak memory 215068 kb
Host smart-bcfd1240-8471-44dd-b299-8cb6e4ecf73a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039115935 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1039115935
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.2083255336
Short name T683
Test name
Test status
Simulation time 43122582 ps
CPU time 1.03 seconds
Started Feb 04 04:21:38 PM PST 24
Finished Feb 04 04:21:40 PM PST 24
Peak memory 215304 kb
Host smart-fc324c0b-1802-49fc-8908-ef01ebf4c486
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083255336 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.2083255336
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.4035459839
Short name T60
Test name
Test status
Simulation time 21248065 ps
CPU time 0.92 seconds
Started Feb 04 04:21:38 PM PST 24
Finished Feb 04 04:21:40 PM PST 24
Peak memory 216524 kb
Host smart-7b26a502-1cd8-40c3-b4b4-ddceaaf7c45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035459839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.4035459839
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1576947938
Short name T813
Test name
Test status
Simulation time 44023987 ps
CPU time 1.08 seconds
Started Feb 04 04:21:38 PM PST 24
Finished Feb 04 04:21:40 PM PST 24
Peak memory 216652 kb
Host smart-481c4d75-d831-46e0-bb8c-4e401205927f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576947938 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1576947938
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3470679745
Short name T922
Test name
Test status
Simulation time 26239566 ps
CPU time 1 seconds
Started Feb 04 04:21:38 PM PST 24
Finished Feb 04 04:21:40 PM PST 24
Peak memory 222488 kb
Host smart-ffe12517-1cec-4bb8-9f55-f064cc07e7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470679745 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3470679745
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.4073520484
Short name T722
Test name
Test status
Simulation time 14416525 ps
CPU time 0.97 seconds
Started Feb 04 04:21:39 PM PST 24
Finished Feb 04 04:21:41 PM PST 24
Peak memory 214892 kb
Host smart-1124b812-ed96-4512-81e2-50fbabfd85bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073520484 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.4073520484
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.4137661146
Short name T682
Test name
Test status
Simulation time 145647612 ps
CPU time 1.05 seconds
Started Feb 04 04:21:37 PM PST 24
Finished Feb 04 04:21:40 PM PST 24
Peak memory 215032 kb
Host smart-5fa1e869-6580-4f92-9728-3c797a22c0f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137661146 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.4137661146
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3895998864
Short name T296
Test name
Test status
Simulation time 158595021677 ps
CPU time 1527.01 seconds
Started Feb 04 04:21:38 PM PST 24
Finished Feb 04 04:47:06 PM PST 24
Peak memory 222656 kb
Host smart-79e4ea3f-e704-4c53-bf3b-61ccce53ba02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895998864 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3895998864
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1323516102
Short name T581
Test name
Test status
Simulation time 23970128 ps
CPU time 1.06 seconds
Started Feb 04 04:21:54 PM PST 24
Finished Feb 04 04:22:00 PM PST 24
Peak memory 206704 kb
Host smart-44041ea2-63e9-4711-aa1a-57c1a70ddf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323516102 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1323516102
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1617919015
Short name T941
Test name
Test status
Simulation time 16917554 ps
CPU time 1.02 seconds
Started Feb 04 04:21:49 PM PST 24
Finished Feb 04 04:21:51 PM PST 24
Peak memory 205328 kb
Host smart-4ea81885-bcb1-4f5b-96dd-d4bd4cb0e346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617919015 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1617919015
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2386501080
Short name T145
Test name
Test status
Simulation time 13974859 ps
CPU time 0.9 seconds
Started Feb 04 04:21:46 PM PST 24
Finished Feb 04 04:21:47 PM PST 24
Peak memory 215060 kb
Host smart-f701e09c-4dce-4802-97f7-b105a8a31e50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386501080 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2386501080
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1019025329
Short name T174
Test name
Test status
Simulation time 25284653 ps
CPU time 1.14 seconds
Started Feb 04 04:21:50 PM PST 24
Finished Feb 04 04:21:53 PM PST 24
Peak memory 215432 kb
Host smart-b81cc680-bc56-4e50-a46d-efef6611620d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019025329 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1019025329
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_genbits.2245208799
Short name T520
Test name
Test status
Simulation time 40267939 ps
CPU time 0.99 seconds
Started Feb 04 04:21:38 PM PST 24
Finished Feb 04 04:21:40 PM PST 24
Peak memory 215196 kb
Host smart-020f9a2f-3352-4dc8-8c01-a56f644f57ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245208799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2245208799
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2843154795
Short name T945
Test name
Test status
Simulation time 23951260 ps
CPU time 1.12 seconds
Started Feb 04 04:22:09 PM PST 24
Finished Feb 04 04:22:11 PM PST 24
Peak memory 215192 kb
Host smart-95db671e-7900-4662-be00-61e58fd51d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843154795 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2843154795
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1911038507
Short name T899
Test name
Test status
Simulation time 29957370 ps
CPU time 1 seconds
Started Feb 04 04:21:39 PM PST 24
Finished Feb 04 04:21:41 PM PST 24
Peak memory 214908 kb
Host smart-b98eb4b7-5224-4452-bf55-728f1f51cd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911038507 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1911038507
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1070358095
Short name T707
Test name
Test status
Simulation time 133248429 ps
CPU time 3.21 seconds
Started Feb 04 04:21:54 PM PST 24
Finished Feb 04 04:22:02 PM PST 24
Peak memory 215388 kb
Host smart-42069725-e06e-4224-b05c-e4e7dc56ccf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070358095 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1070358095
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2375932187
Short name T902
Test name
Test status
Simulation time 144697989624 ps
CPU time 235.93 seconds
Started Feb 04 04:21:51 PM PST 24
Finished Feb 04 04:25:48 PM PST 24
Peak memory 216784 kb
Host smart-ca047524-251d-43bc-bc65-810da23aef8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375932187 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2375932187
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1244233954
Short name T247
Test name
Test status
Simulation time 37934594 ps
CPU time 1 seconds
Started Feb 04 04:22:09 PM PST 24
Finished Feb 04 04:22:11 PM PST 24
Peak memory 205844 kb
Host smart-0acc3ccc-bc49-4fdf-bece-4c8803eb14a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244233954 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1244233954
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.555976464
Short name T610
Test name
Test status
Simulation time 38077855 ps
CPU time 0.9 seconds
Started Feb 04 04:21:51 PM PST 24
Finished Feb 04 04:21:53 PM PST 24
Peak memory 205340 kb
Host smart-0479fd0c-b094-4a8d-bee8-cb150874af24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555976464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.555976464
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.57393138
Short name T37
Test name
Test status
Simulation time 16036967 ps
CPU time 0.85 seconds
Started Feb 04 04:21:52 PM PST 24
Finished Feb 04 04:21:54 PM PST 24
Peak memory 215052 kb
Host smart-ea72a8e9-d968-4d85-bcb7-666e7eb74591
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57393138 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.57393138
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1672331674
Short name T118
Test name
Test status
Simulation time 37003273 ps
CPU time 1.03 seconds
Started Feb 04 04:21:48 PM PST 24
Finished Feb 04 04:21:51 PM PST 24
Peak memory 215236 kb
Host smart-21356bcf-e589-4891-90f7-a89285fb6a1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672331674 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1672331674
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.2521542518
Short name T431
Test name
Test status
Simulation time 18274604 ps
CPU time 1.07 seconds
Started Feb 04 04:21:48 PM PST 24
Finished Feb 04 04:21:50 PM PST 24
Peak memory 216560 kb
Host smart-dcbd26d9-fd5e-43a4-b453-b5482597f9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521542518 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2521542518
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1759585677
Short name T324
Test name
Test status
Simulation time 20768111 ps
CPU time 1.12 seconds
Started Feb 04 04:21:49 PM PST 24
Finished Feb 04 04:21:51 PM PST 24
Peak memory 215248 kb
Host smart-bf6facdb-cee5-454e-b988-df85702f10e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759585677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1759585677
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.750222310
Short name T608
Test name
Test status
Simulation time 29526876 ps
CPU time 0.98 seconds
Started Feb 04 04:21:47 PM PST 24
Finished Feb 04 04:21:48 PM PST 24
Peak memory 222540 kb
Host smart-b420f41d-4b76-4eac-a64d-81517031f551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750222310 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.750222310
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1281163732
Short name T798
Test name
Test status
Simulation time 15130864 ps
CPU time 0.98 seconds
Started Feb 04 04:21:56 PM PST 24
Finished Feb 04 04:22:00 PM PST 24
Peak memory 214892 kb
Host smart-27af6a75-b17b-4594-b51c-26b21fd4eb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281163732 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1281163732
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3775943104
Short name T170
Test name
Test status
Simulation time 442657097 ps
CPU time 1.97 seconds
Started Feb 04 04:21:51 PM PST 24
Finished Feb 04 04:21:54 PM PST 24
Peak memory 206760 kb
Host smart-2af3ba96-7cfb-4d37-b5a3-beef2a4507d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775943104 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3775943104
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3822548938
Short name T956
Test name
Test status
Simulation time 99518772650 ps
CPU time 715.52 seconds
Started Feb 04 04:21:48 PM PST 24
Finished Feb 04 04:33:45 PM PST 24
Peak memory 219328 kb
Host smart-2c723956-ab75-415d-be67-706a19e962b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822548938 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3822548938
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.112027894
Short name T293
Test name
Test status
Simulation time 22648805 ps
CPU time 1.02 seconds
Started Feb 04 04:21:55 PM PST 24
Finished Feb 04 04:22:00 PM PST 24
Peak memory 206672 kb
Host smart-34b1187e-525e-4dda-87be-e60d3036b1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112027894 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.112027894
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2279289590
Short name T756
Test name
Test status
Simulation time 24619099 ps
CPU time 0.88 seconds
Started Feb 04 04:21:56 PM PST 24
Finished Feb 04 04:22:00 PM PST 24
Peak memory 205320 kb
Host smart-15597995-2a22-498c-a348-87df46b3f65a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279289590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2279289590
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2023984017
Short name T183
Test name
Test status
Simulation time 34554944 ps
CPU time 0.92 seconds
Started Feb 04 04:21:55 PM PST 24
Finished Feb 04 04:22:00 PM PST 24
Peak memory 215056 kb
Host smart-7f09b135-82fe-4dca-ac59-9d234a23bd9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023984017 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2023984017
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.2783015322
Short name T101
Test name
Test status
Simulation time 22412463 ps
CPU time 1.23 seconds
Started Feb 04 04:21:54 PM PST 24
Finished Feb 04 04:22:00 PM PST 24
Peak memory 217104 kb
Host smart-883349a0-8308-4a97-97e3-8d92d1f79dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783015322 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2783015322
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1538283713
Short name T952
Test name
Test status
Simulation time 31996523 ps
CPU time 1.11 seconds
Started Feb 04 04:21:57 PM PST 24
Finished Feb 04 04:22:00 PM PST 24
Peak memory 215116 kb
Host smart-c5ea8df5-6e9c-43cf-b8fe-36f0e014aebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538283713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1538283713
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_smoke.104484371
Short name T817
Test name
Test status
Simulation time 42616959 ps
CPU time 0.9 seconds
Started Feb 04 04:21:47 PM PST 24
Finished Feb 04 04:21:48 PM PST 24
Peak memory 214920 kb
Host smart-da658348-65dd-460f-b9fa-377ac92bec3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104484371 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.104484371
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.4211832751
Short name T317
Test name
Test status
Simulation time 113909104 ps
CPU time 1.85 seconds
Started Feb 04 04:21:57 PM PST 24
Finished Feb 04 04:22:01 PM PST 24
Peak memory 215264 kb
Host smart-81462133-bbe4-46b9-8a5c-a18b5f94e497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211832751 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.4211832751
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.135000501
Short name T673
Test name
Test status
Simulation time 39987324780 ps
CPU time 453.28 seconds
Started Feb 04 04:21:54 PM PST 24
Finished Feb 04 04:29:32 PM PST 24
Peak memory 216352 kb
Host smart-e4e5fa16-ba19-472c-ad65-4742928d6953
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135000501 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.135000501
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.942176447
Short name T769
Test name
Test status
Simulation time 32290274 ps
CPU time 1.02 seconds
Started Feb 04 04:21:56 PM PST 24
Finished Feb 04 04:22:00 PM PST 24
Peak memory 206484 kb
Host smart-4f3557df-2c92-40ba-9916-ad19feb9ec27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942176447 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.942176447
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2417385471
Short name T428
Test name
Test status
Simulation time 60702129 ps
CPU time 0.83 seconds
Started Feb 04 04:21:54 PM PST 24
Finished Feb 04 04:22:00 PM PST 24
Peak memory 206012 kb
Host smart-8850b22c-4924-4cb2-a2c2-9fe10144318e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417385471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2417385471
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.4164345635
Short name T771
Test name
Test status
Simulation time 29292641 ps
CPU time 0.87 seconds
Started Feb 04 04:21:59 PM PST 24
Finished Feb 04 04:22:02 PM PST 24
Peak memory 215188 kb
Host smart-55b17451-6be9-4519-bf1a-cf687d81f7b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164345635 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.4164345635
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.2939193431
Short name T95
Test name
Test status
Simulation time 25387795 ps
CPU time 1.01 seconds
Started Feb 04 04:21:56 PM PST 24
Finished Feb 04 04:22:00 PM PST 24
Peak memory 215300 kb
Host smart-194760d0-6671-4e39-bc70-0f95a4f64e4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939193431 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.2939193431
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.2572354594
Short name T933
Test name
Test status
Simulation time 33030499 ps
CPU time 0.98 seconds
Started Feb 04 04:21:59 PM PST 24
Finished Feb 04 04:22:02 PM PST 24
Peak memory 217040 kb
Host smart-0bd849fd-f4fc-4326-89bc-7db653ceb7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572354594 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2572354594
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2848904056
Short name T307
Test name
Test status
Simulation time 238650801 ps
CPU time 1.17 seconds
Started Feb 04 04:22:09 PM PST 24
Finished Feb 04 04:22:11 PM PST 24
Peak memory 215464 kb
Host smart-cc73245f-23c3-4e55-8d8e-42a595d249ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848904056 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2848904056
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.3506715839
Short name T528
Test name
Test status
Simulation time 23621408 ps
CPU time 0.98 seconds
Started Feb 04 04:21:57 PM PST 24
Finished Feb 04 04:22:00 PM PST 24
Peak memory 215300 kb
Host smart-4d0a09ec-05fa-481f-802d-432a1f1fe7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506715839 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3506715839
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1639376123
Short name T653
Test name
Test status
Simulation time 18666473 ps
CPU time 1.04 seconds
Started Feb 04 04:21:56 PM PST 24
Finished Feb 04 04:22:00 PM PST 24
Peak memory 214916 kb
Host smart-b00fc6f5-7842-4ffc-8f07-8658f0b4b140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639376123 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1639376123
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.886827016
Short name T759
Test name
Test status
Simulation time 96235914 ps
CPU time 2.15 seconds
Started Feb 04 04:21:57 PM PST 24
Finished Feb 04 04:22:01 PM PST 24
Peak memory 215000 kb
Host smart-f4584453-e615-4535-a0cb-aef11822a8ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886827016 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.886827016
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2850462210
Short name T760
Test name
Test status
Simulation time 464063398966 ps
CPU time 2557.1 seconds
Started Feb 04 04:22:09 PM PST 24
Finished Feb 04 05:04:47 PM PST 24
Peak memory 227980 kb
Host smart-553921a5-a826-49e2-a17d-92331dd83d81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850462210 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2850462210
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.4114066704
Short name T662
Test name
Test status
Simulation time 49463706 ps
CPU time 0.95 seconds
Started Feb 04 04:19:12 PM PST 24
Finished Feb 04 04:19:14 PM PST 24
Peak memory 206664 kb
Host smart-f440b877-cc3e-4bbc-bdf2-c360f2242a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114066704 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.4114066704
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.4289842318
Short name T490
Test name
Test status
Simulation time 14557965 ps
CPU time 0.92 seconds
Started Feb 04 04:19:13 PM PST 24
Finished Feb 04 04:19:16 PM PST 24
Peak memory 205276 kb
Host smart-f8185962-fdb5-41cd-8541-110d2f46c815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289842318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.4289842318
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3812648039
Short name T34
Test name
Test status
Simulation time 33544222 ps
CPU time 0.92 seconds
Started Feb 04 04:19:15 PM PST 24
Finished Feb 04 04:19:19 PM PST 24
Peak memory 215040 kb
Host smart-a23005b7-4091-4f16-80cb-3aa4dd83c60c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812648039 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3812648039
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_err.1658041745
Short name T659
Test name
Test status
Simulation time 40036357 ps
CPU time 0.98 seconds
Started Feb 04 04:19:14 PM PST 24
Finished Feb 04 04:19:17 PM PST 24
Peak memory 222016 kb
Host smart-ddf81f42-ea58-4782-b713-0049008b1e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658041745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.1658041745
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3339045869
Short name T32
Test name
Test status
Simulation time 124959202 ps
CPU time 1.16 seconds
Started Feb 04 04:19:13 PM PST 24
Finished Feb 04 04:19:15 PM PST 24
Peak memory 216688 kb
Host smart-5e610bc2-c82e-4312-8e4d-5e2c48b1fb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339045869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3339045869
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.5883600
Short name T789
Test name
Test status
Simulation time 18563933 ps
CPU time 1.15 seconds
Started Feb 04 04:19:09 PM PST 24
Finished Feb 04 04:19:11 PM PST 24
Peak memory 215160 kb
Host smart-96978a14-e0eb-4a0c-b9ac-76c8548c9229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5883600 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.5883600
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.2400046963
Short name T253
Test name
Test status
Simulation time 40033193 ps
CPU time 0.92 seconds
Started Feb 04 04:19:15 PM PST 24
Finished Feb 04 04:19:17 PM PST 24
Peak memory 206752 kb
Host smart-bcf68327-b100-4625-ae95-f9d9e6c82e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400046963 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.2400046963
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.3295191251
Short name T567
Test name
Test status
Simulation time 13501448 ps
CPU time 0.99 seconds
Started Feb 04 04:19:12 PM PST 24
Finished Feb 04 04:19:15 PM PST 24
Peak memory 214940 kb
Host smart-6e55ba4b-20cf-4558-942e-b6078f2f88c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295191251 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.3295191251
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1202654346
Short name T737
Test name
Test status
Simulation time 336498096 ps
CPU time 3 seconds
Started Feb 04 04:19:17 PM PST 24
Finished Feb 04 04:19:22 PM PST 24
Peak memory 215464 kb
Host smart-79adde74-bb3a-409c-b362-880c69844e8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202654346 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1202654346
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1952610751
Short name T92
Test name
Test status
Simulation time 112643522358 ps
CPU time 2769.61 seconds
Started Feb 04 04:19:10 PM PST 24
Finished Feb 04 05:05:21 PM PST 24
Peak memory 232436 kb
Host smart-7bf9f6ea-7079-47ff-b73f-5d22c2bfff16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952610751 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1952610751
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.2297550065
Short name T17
Test name
Test status
Simulation time 34350611 ps
CPU time 1.04 seconds
Started Feb 04 04:21:58 PM PST 24
Finished Feb 04 04:22:00 PM PST 24
Peak memory 206772 kb
Host smart-8434acb2-b0e5-47f4-ae60-56a29288d788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297550065 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.2297550065
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.919558506
Short name T441
Test name
Test status
Simulation time 70965253 ps
CPU time 0.88 seconds
Started Feb 04 04:21:52 PM PST 24
Finished Feb 04 04:21:58 PM PST 24
Peak memory 206200 kb
Host smart-731051f1-0c50-45b1-b557-7c8ae0601f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919558506 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.919558506
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.1010249729
Short name T144
Test name
Test status
Simulation time 43459233 ps
CPU time 0.87 seconds
Started Feb 04 04:21:58 PM PST 24
Finished Feb 04 04:22:02 PM PST 24
Peak memory 215032 kb
Host smart-3892cfec-49ae-427e-9797-1c0b57abb54e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010249729 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.1010249729
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.2305121913
Short name T616
Test name
Test status
Simulation time 16927322 ps
CPU time 0.96 seconds
Started Feb 04 04:21:58 PM PST 24
Finished Feb 04 04:22:00 PM PST 24
Peak memory 216288 kb
Host smart-433247cc-12bc-4255-aac1-4d56a164d8b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305121913 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.2305121913
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1957736756
Short name T832
Test name
Test status
Simulation time 38746674 ps
CPU time 0.94 seconds
Started Feb 04 04:21:56 PM PST 24
Finished Feb 04 04:22:00 PM PST 24
Peak memory 216532 kb
Host smart-24b72d18-348b-4678-8bd0-1c93408df6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957736756 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1957736756
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.354998448
Short name T64
Test name
Test status
Simulation time 163635547 ps
CPU time 1.5 seconds
Started Feb 04 04:21:58 PM PST 24
Finished Feb 04 04:22:02 PM PST 24
Peak memory 215440 kb
Host smart-be70227e-8b3f-4be2-a0ec-db8d13d41e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354998448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.354998448
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2099126278
Short name T901
Test name
Test status
Simulation time 55614698 ps
CPU time 1 seconds
Started Feb 04 04:21:55 PM PST 24
Finished Feb 04 04:22:00 PM PST 24
Peak memory 222524 kb
Host smart-6a936cb2-1a74-4838-b5b6-9296225a14f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099126278 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2099126278
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1983845597
Short name T835
Test name
Test status
Simulation time 22167782 ps
CPU time 0.9 seconds
Started Feb 04 04:21:57 PM PST 24
Finished Feb 04 04:22:00 PM PST 24
Peak memory 214964 kb
Host smart-cb95781a-db8e-48d7-bc5f-b7baefc4a1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983845597 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1983845597
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2122751157
Short name T699
Test name
Test status
Simulation time 194880201 ps
CPU time 4.35 seconds
Started Feb 04 04:21:58 PM PST 24
Finished Feb 04 04:22:04 PM PST 24
Peak memory 215376 kb
Host smart-83fa9525-e6b6-4183-a887-7aa5c4ac26d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122751157 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2122751157
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.941189675
Short name T660
Test name
Test status
Simulation time 59574725822 ps
CPU time 1376.39 seconds
Started Feb 04 04:21:55 PM PST 24
Finished Feb 04 04:44:55 PM PST 24
Peak memory 220700 kb
Host smart-768c4f4c-ecaf-4f30-9589-3da95963e16a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941189675 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.941189675
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3736176425
Short name T891
Test name
Test status
Simulation time 56232693 ps
CPU time 1.01 seconds
Started Feb 04 04:22:05 PM PST 24
Finished Feb 04 04:22:07 PM PST 24
Peak memory 206700 kb
Host smart-1fe84c86-26af-4190-8783-4b093d321e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736176425 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3736176425
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.143868902
Short name T847
Test name
Test status
Simulation time 241357769 ps
CPU time 0.95 seconds
Started Feb 04 04:22:01 PM PST 24
Finished Feb 04 04:22:03 PM PST 24
Peak memory 205860 kb
Host smart-3aa7b130-31af-4419-8cd0-820bd57914d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143868902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.143868902
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.1173532485
Short name T42
Test name
Test status
Simulation time 32880106 ps
CPU time 1.61 seconds
Started Feb 04 04:22:04 PM PST 24
Finished Feb 04 04:22:06 PM PST 24
Peak memory 215224 kb
Host smart-e28edb2a-3684-4e6c-92ce-9e372786175b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173532485 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.1173532485
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_genbits.1311160065
Short name T937
Test name
Test status
Simulation time 56152438 ps
CPU time 1.11 seconds
Started Feb 04 04:22:09 PM PST 24
Finished Feb 04 04:22:11 PM PST 24
Peak memory 215644 kb
Host smart-9fc6ba4e-ec7a-4a42-a987-2cb213c91ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311160065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1311160065
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1752034425
Short name T536
Test name
Test status
Simulation time 19154146 ps
CPU time 1.05 seconds
Started Feb 04 04:22:03 PM PST 24
Finished Feb 04 04:22:05 PM PST 24
Peak memory 215184 kb
Host smart-001cc074-946a-425f-ad14-e2a8002629ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752034425 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1752034425
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.2210236448
Short name T949
Test name
Test status
Simulation time 64289324 ps
CPU time 1.11 seconds
Started Feb 04 04:21:55 PM PST 24
Finished Feb 04 04:22:00 PM PST 24
Peak memory 214916 kb
Host smart-5f0852fe-cb96-4b50-a0f5-e0d264c3553b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210236448 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.2210236448
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.726202462
Short name T826
Test name
Test status
Simulation time 229934957 ps
CPU time 2.85 seconds
Started Feb 04 04:22:01 PM PST 24
Finished Feb 04 04:22:04 PM PST 24
Peak memory 215004 kb
Host smart-a195d2be-bbcd-49c6-acc2-7b7f6fc45b47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726202462 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.726202462
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.513520830
Short name T665
Test name
Test status
Simulation time 178909849959 ps
CPU time 1621.84 seconds
Started Feb 04 04:22:11 PM PST 24
Finished Feb 04 04:49:14 PM PST 24
Peak memory 225944 kb
Host smart-c1d793cb-20c8-4012-a600-12ea09daeac1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513520830 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.513520830
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.1913963417
Short name T290
Test name
Test status
Simulation time 57368912 ps
CPU time 1.07 seconds
Started Feb 04 04:22:12 PM PST 24
Finished Feb 04 04:22:14 PM PST 24
Peak memory 206636 kb
Host smart-a53f4f55-240c-4d6e-b4df-2a6b532d31ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913963417 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.1913963417
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2637772869
Short name T452
Test name
Test status
Simulation time 21315184 ps
CPU time 0.81 seconds
Started Feb 04 04:22:03 PM PST 24
Finished Feb 04 04:22:04 PM PST 24
Peak memory 205020 kb
Host smart-ee4962e5-fcd2-4d51-8bba-86eb6aa82e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637772869 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2637772869
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.491991034
Short name T164
Test name
Test status
Simulation time 19038846 ps
CPU time 0.88 seconds
Started Feb 04 04:22:11 PM PST 24
Finished Feb 04 04:22:13 PM PST 24
Peak memory 215056 kb
Host smart-802ae597-a213-4c2b-af27-792fee48a249
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491991034 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.491991034
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1019199380
Short name T40
Test name
Test status
Simulation time 114493091 ps
CPU time 1.17 seconds
Started Feb 04 04:22:18 PM PST 24
Finished Feb 04 04:22:24 PM PST 24
Peak memory 217912 kb
Host smart-5c6e31a6-5e5f-4358-9be1-bbbbf08e19d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019199380 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1019199380
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.2617037886
Short name T533
Test name
Test status
Simulation time 30519519 ps
CPU time 1.32 seconds
Started Feb 04 04:22:16 PM PST 24
Finished Feb 04 04:22:19 PM PST 24
Peak memory 217716 kb
Host smart-636aa150-0b65-41c2-ac4a-8e05c280cd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617037886 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2617037886
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3593513707
Short name T632
Test name
Test status
Simulation time 308969745 ps
CPU time 1.54 seconds
Started Feb 04 04:22:01 PM PST 24
Finished Feb 04 04:22:04 PM PST 24
Peak memory 215436 kb
Host smart-766c4bfc-cdf9-42e8-8e24-3945b497f056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593513707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3593513707
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.994725613
Short name T628
Test name
Test status
Simulation time 81421133 ps
CPU time 0.83 seconds
Started Feb 04 04:22:09 PM PST 24
Finished Feb 04 04:22:11 PM PST 24
Peak memory 215120 kb
Host smart-a975a5d2-ac87-44f6-853a-65b2710e2fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994725613 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.994725613
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.1527047076
Short name T661
Test name
Test status
Simulation time 34787760 ps
CPU time 0.93 seconds
Started Feb 04 04:22:09 PM PST 24
Finished Feb 04 04:22:10 PM PST 24
Peak memory 214960 kb
Host smart-e7f94687-cf2c-47b9-a193-defb1ae81eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527047076 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.1527047076
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.393256234
Short name T512
Test name
Test status
Simulation time 701445667 ps
CPU time 3.65 seconds
Started Feb 04 04:22:12 PM PST 24
Finished Feb 04 04:22:17 PM PST 24
Peak memory 215352 kb
Host smart-9f68c82e-07f1-40e4-bc3d-c2004a14c340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393256234 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.393256234
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3444582268
Short name T261
Test name
Test status
Simulation time 19508895712 ps
CPU time 427.51 seconds
Started Feb 04 04:22:19 PM PST 24
Finished Feb 04 04:29:32 PM PST 24
Peak memory 217328 kb
Host smart-89f683f9-203c-4842-b33d-8e56162b83a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444582268 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3444582268
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2157224756
Short name T283
Test name
Test status
Simulation time 64365199 ps
CPU time 0.96 seconds
Started Feb 04 04:22:16 PM PST 24
Finished Feb 04 04:22:19 PM PST 24
Peak memory 206640 kb
Host smart-f59c9458-e40d-4072-8abe-cdae0f68a18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157224756 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2157224756
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1107690006
Short name T453
Test name
Test status
Simulation time 19632046 ps
CPU time 1 seconds
Started Feb 04 04:22:24 PM PST 24
Finished Feb 04 04:22:27 PM PST 24
Peak memory 205804 kb
Host smart-c8c5096b-9fbe-465a-85be-2a40ed1b87c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107690006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1107690006
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.3842880217
Short name T556
Test name
Test status
Simulation time 16958626 ps
CPU time 0.83 seconds
Started Feb 04 04:22:24 PM PST 24
Finished Feb 04 04:22:27 PM PST 24
Peak memory 215024 kb
Host smart-8f1e4e24-da0b-442c-9119-40a541c95592
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842880217 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3842880217
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.819169212
Short name T116
Test name
Test status
Simulation time 153045644 ps
CPU time 1.02 seconds
Started Feb 04 04:22:20 PM PST 24
Finished Feb 04 04:22:25 PM PST 24
Peak memory 215228 kb
Host smart-e8b04cf4-2970-4813-82e1-84e373951cef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819169212 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.819169212
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_genbits.1149202601
Short name T588
Test name
Test status
Simulation time 34026620 ps
CPU time 1.09 seconds
Started Feb 04 04:22:07 PM PST 24
Finished Feb 04 04:22:09 PM PST 24
Peak memory 215336 kb
Host smart-010eacc5-d8d0-44a8-974d-bffb2a5732b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149202601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1149202601
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.352278850
Short name T889
Test name
Test status
Simulation time 38919978 ps
CPU time 0.99 seconds
Started Feb 04 04:22:16 PM PST 24
Finished Feb 04 04:22:19 PM PST 24
Peak memory 222560 kb
Host smart-eb84cc73-e213-40dc-8b77-0d7593cea1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352278850 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.352278850
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.2468694472
Short name T779
Test name
Test status
Simulation time 25516039 ps
CPU time 1.01 seconds
Started Feb 04 04:22:13 PM PST 24
Finished Feb 04 04:22:16 PM PST 24
Peak memory 214936 kb
Host smart-2ddb8884-1898-4fdc-ab33-d59d7be4c7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468694472 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.2468694472
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3378162186
Short name T748
Test name
Test status
Simulation time 132409675 ps
CPU time 3.02 seconds
Started Feb 04 04:22:10 PM PST 24
Finished Feb 04 04:22:14 PM PST 24
Peak memory 214960 kb
Host smart-c35a8711-bfed-49c9-b84b-9fe6fa151f1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378162186 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3378162186
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2646766730
Short name T718
Test name
Test status
Simulation time 93364903502 ps
CPU time 1058.91 seconds
Started Feb 04 04:22:17 PM PST 24
Finished Feb 04 04:39:57 PM PST 24
Peak memory 219724 kb
Host smart-72e07334-0e70-42c8-aeaa-1d041cff85bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646766730 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2646766730
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2952049880
Short name T710
Test name
Test status
Simulation time 193522107 ps
CPU time 1 seconds
Started Feb 04 04:22:18 PM PST 24
Finished Feb 04 04:22:24 PM PST 24
Peak memory 206660 kb
Host smart-411b45df-0a81-44c5-92ca-805530ba7dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952049880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2952049880
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1763652710
Short name T845
Test name
Test status
Simulation time 20065918 ps
CPU time 0.88 seconds
Started Feb 04 04:22:27 PM PST 24
Finished Feb 04 04:22:29 PM PST 24
Peak memory 205320 kb
Host smart-df403abe-7ee8-4666-b4c0-0e4151536442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763652710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1763652710
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2887208361
Short name T785
Test name
Test status
Simulation time 23441739 ps
CPU time 0.87 seconds
Started Feb 04 04:22:22 PM PST 24
Finished Feb 04 04:22:25 PM PST 24
Peak memory 215116 kb
Host smart-856633e6-4962-4c8e-a8c4-d9108bf1cb64
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887208361 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2887208361
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.378719674
Short name T151
Test name
Test status
Simulation time 28364020 ps
CPU time 0.99 seconds
Started Feb 04 04:22:23 PM PST 24
Finished Feb 04 04:22:27 PM PST 24
Peak memory 215384 kb
Host smart-109f68cd-823c-4c1f-9aca-62bf6c0f9ead
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378719674 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.378719674
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.4153989270
Short name T911
Test name
Test status
Simulation time 122681795 ps
CPU time 1.15 seconds
Started Feb 04 04:22:26 PM PST 24
Finished Feb 04 04:22:29 PM PST 24
Peak memory 218064 kb
Host smart-98929ff6-c0fb-47fe-abf0-a9eac6a4150b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153989270 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.4153989270
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1893146399
Short name T580
Test name
Test status
Simulation time 22879996 ps
CPU time 1.15 seconds
Started Feb 04 04:22:19 PM PST 24
Finished Feb 04 04:22:25 PM PST 24
Peak memory 215480 kb
Host smart-df2289ad-ff84-4aa6-940f-85748b35814b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893146399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1893146399
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3447573254
Short name T82
Test name
Test status
Simulation time 22401067 ps
CPU time 0.9 seconds
Started Feb 04 04:22:22 PM PST 24
Finished Feb 04 04:22:25 PM PST 24
Peak memory 215352 kb
Host smart-b3507485-f112-4996-9beb-8dd7e9e4f08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447573254 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3447573254
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.2804032532
Short name T93
Test name
Test status
Simulation time 17931989 ps
CPU time 0.87 seconds
Started Feb 04 04:22:23 PM PST 24
Finished Feb 04 04:22:26 PM PST 24
Peak memory 214936 kb
Host smart-76a39c84-0b74-47a7-aabc-af200039eb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804032532 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.2804032532
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3353069194
Short name T812
Test name
Test status
Simulation time 353627705 ps
CPU time 4.7 seconds
Started Feb 04 04:22:26 PM PST 24
Finished Feb 04 04:22:32 PM PST 24
Peak memory 215348 kb
Host smart-f5145500-4f2b-4bf5-b332-39e0097836d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353069194 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3353069194
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1889631039
Short name T744
Test name
Test status
Simulation time 153625548952 ps
CPU time 875.4 seconds
Started Feb 04 04:22:26 PM PST 24
Finished Feb 04 04:37:03 PM PST 24
Peak memory 219816 kb
Host smart-98cd769f-09ea-44c7-8d89-861e9fa50766
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889631039 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1889631039
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3448396655
Short name T774
Test name
Test status
Simulation time 20382441 ps
CPU time 1.04 seconds
Started Feb 04 04:22:26 PM PST 24
Finished Feb 04 04:22:28 PM PST 24
Peak memory 205900 kb
Host smart-adc0b9a7-6d5a-4329-bcf0-9ca1929754a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448396655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3448396655
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3890789551
Short name T425
Test name
Test status
Simulation time 19083314 ps
CPU time 0.98 seconds
Started Feb 04 04:22:19 PM PST 24
Finished Feb 04 04:22:25 PM PST 24
Peak memory 205360 kb
Host smart-d516f6ad-7339-40e5-b27f-06f01a8256f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890789551 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3890789551
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1489465297
Short name T123
Test name
Test status
Simulation time 40255626 ps
CPU time 0.9 seconds
Started Feb 04 04:22:17 PM PST 24
Finished Feb 04 04:22:19 PM PST 24
Peak memory 215036 kb
Host smart-1f7920ac-f2e9-4881-bcac-0ec517b81e9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489465297 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1489465297
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.2563634432
Short name T186
Test name
Test status
Simulation time 18976169 ps
CPU time 1.03 seconds
Started Feb 04 04:22:17 PM PST 24
Finished Feb 04 04:22:19 PM PST 24
Peak memory 215420 kb
Host smart-4f1004e4-14e9-4acf-9247-042c30a688dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563634432 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.2563634432
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.681517078
Short name T515
Test name
Test status
Simulation time 70116105 ps
CPU time 0.93 seconds
Started Feb 04 04:22:23 PM PST 24
Finished Feb 04 04:22:27 PM PST 24
Peak memory 222396 kb
Host smart-a272b6f3-b51c-4e37-a09d-0fb33795e403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681517078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.681517078
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.1460400038
Short name T593
Test name
Test status
Simulation time 60698327 ps
CPU time 1.21 seconds
Started Feb 04 04:22:19 PM PST 24
Finished Feb 04 04:22:25 PM PST 24
Peak memory 216624 kb
Host smart-c195527e-60aa-48e3-a03e-893eb4837f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460400038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.1460400038
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.468069558
Short name T797
Test name
Test status
Simulation time 21034747 ps
CPU time 1.05 seconds
Started Feb 04 04:22:26 PM PST 24
Finished Feb 04 04:22:28 PM PST 24
Peak memory 215096 kb
Host smart-b3405575-9898-4353-83da-2937839719a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468069558 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.468069558
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.470225484
Short name T713
Test name
Test status
Simulation time 28258734 ps
CPU time 0.93 seconds
Started Feb 04 04:22:16 PM PST 24
Finished Feb 04 04:22:19 PM PST 24
Peak memory 214932 kb
Host smart-69548454-eef9-4a18-9554-e25365b67847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470225484 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.470225484
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.209890542
Short name T669
Test name
Test status
Simulation time 363581886 ps
CPU time 2.84 seconds
Started Feb 04 04:22:24 PM PST 24
Finished Feb 04 04:22:29 PM PST 24
Peak memory 214928 kb
Host smart-48b6f8fb-385e-4338-8475-f42e59b29708
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209890542 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.209890542
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.467558332
Short name T853
Test name
Test status
Simulation time 79064184350 ps
CPU time 528.42 seconds
Started Feb 04 04:22:16 PM PST 24
Finished Feb 04 04:31:06 PM PST 24
Peak memory 223392 kb
Host smart-3cecfea9-da1d-437b-a4cf-5b8fba7d9a59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467558332 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.467558332
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1641930482
Short name T958
Test name
Test status
Simulation time 73944072 ps
CPU time 0.99 seconds
Started Feb 04 04:22:17 PM PST 24
Finished Feb 04 04:22:19 PM PST 24
Peak memory 206708 kb
Host smart-4dc2d743-7cc1-4271-898e-b13e906096e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641930482 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1641930482
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1013824728
Short name T776
Test name
Test status
Simulation time 54291623 ps
CPU time 0.96 seconds
Started Feb 04 04:22:23 PM PST 24
Finished Feb 04 04:22:27 PM PST 24
Peak memory 205356 kb
Host smart-38e082d3-ceeb-4c12-a781-be418701e779
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013824728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1013824728
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.401487718
Short name T950
Test name
Test status
Simulation time 27895261 ps
CPU time 0.89 seconds
Started Feb 04 04:22:22 PM PST 24
Finished Feb 04 04:22:25 PM PST 24
Peak memory 215040 kb
Host smart-1a8bf731-a010-449b-8067-808ca843c5ff
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401487718 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.401487718
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.2136551730
Short name T114
Test name
Test status
Simulation time 113608484 ps
CPU time 1.16 seconds
Started Feb 04 04:22:27 PM PST 24
Finished Feb 04 04:22:29 PM PST 24
Peak memory 215220 kb
Host smart-a3d65d2c-dad5-4fda-a46d-effad9456619
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136551730 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.2136551730
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_genbits.529300217
Short name T753
Test name
Test status
Simulation time 115203545 ps
CPU time 1.63 seconds
Started Feb 04 04:22:24 PM PST 24
Finished Feb 04 04:22:28 PM PST 24
Peak memory 216600 kb
Host smart-b7b429ad-b8c7-4bf9-9cfc-dbce12dd2ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529300217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.529300217
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1476709250
Short name T590
Test name
Test status
Simulation time 23207667 ps
CPU time 1.14 seconds
Started Feb 04 04:22:15 PM PST 24
Finished Feb 04 04:22:19 PM PST 24
Peak memory 222720 kb
Host smart-aeda7ade-8a10-4b31-97df-bf4ebe51214c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476709250 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1476709250
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.2369454042
Short name T508
Test name
Test status
Simulation time 27994125 ps
CPU time 0.95 seconds
Started Feb 04 04:22:21 PM PST 24
Finished Feb 04 04:22:25 PM PST 24
Peak memory 214972 kb
Host smart-32887a6a-393c-45d1-9de7-3dcfb0ff8c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369454042 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.2369454042
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3728586612
Short name T695
Test name
Test status
Simulation time 481131496 ps
CPU time 3.5 seconds
Started Feb 04 04:22:24 PM PST 24
Finished Feb 04 04:22:30 PM PST 24
Peak memory 218264 kb
Host smart-b5a278bc-136d-48aa-8b60-80d5cf90fcf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728586612 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3728586612
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.4083115273
Short name T578
Test name
Test status
Simulation time 121624804223 ps
CPU time 1646.17 seconds
Started Feb 04 04:22:20 PM PST 24
Finished Feb 04 04:49:51 PM PST 24
Peak memory 223076 kb
Host smart-b4c1ca48-f3bd-4634-b997-b1d00c87159c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083115273 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.4083115273
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1374158176
Short name T282
Test name
Test status
Simulation time 18222041 ps
CPU time 0.99 seconds
Started Feb 04 04:22:31 PM PST 24
Finished Feb 04 04:22:34 PM PST 24
Peak memory 206704 kb
Host smart-d937259e-fd0f-4ac8-9cfb-14cf0e407270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374158176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1374158176
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.16315472
Short name T954
Test name
Test status
Simulation time 34195178 ps
CPU time 0.81 seconds
Started Feb 04 04:22:27 PM PST 24
Finished Feb 04 04:22:29 PM PST 24
Peak memory 205132 kb
Host smart-2470bf95-3a16-4a20-90fa-252277bd8459
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16315472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.16315472
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1988339696
Short name T677
Test name
Test status
Simulation time 17612532 ps
CPU time 0.92 seconds
Started Feb 04 04:22:27 PM PST 24
Finished Feb 04 04:22:29 PM PST 24
Peak memory 215252 kb
Host smart-a95aeb80-a01a-44c0-8bb1-e98154f4994f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988339696 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1988339696
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.162974211
Short name T115
Test name
Test status
Simulation time 16241012 ps
CPU time 0.98 seconds
Started Feb 04 04:22:29 PM PST 24
Finished Feb 04 04:22:31 PM PST 24
Peak memory 215252 kb
Host smart-c4d06d5a-b297-4c14-90a3-15a7ad19576f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162974211 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.162974211
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.9089831
Short name T56
Test name
Test status
Simulation time 48647206 ps
CPU time 1.18 seconds
Started Feb 04 04:22:32 PM PST 24
Finished Feb 04 04:22:35 PM PST 24
Peak memory 222676 kb
Host smart-9c88c9d9-16ef-438c-b21d-cc458885235a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9089831 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.9089831
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3580200660
Short name T598
Test name
Test status
Simulation time 76302225 ps
CPU time 1.25 seconds
Started Feb 04 04:22:21 PM PST 24
Finished Feb 04 04:22:26 PM PST 24
Peak memory 217260 kb
Host smart-77f75393-e9a2-4441-b639-5ffc73f97afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580200660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3580200660
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1403999853
Short name T795
Test name
Test status
Simulation time 19286487 ps
CPU time 1.05 seconds
Started Feb 04 04:22:32 PM PST 24
Finished Feb 04 04:22:35 PM PST 24
Peak memory 215036 kb
Host smart-4374aba3-e706-482c-9cde-42731cdae5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403999853 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1403999853
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2118041815
Short name T466
Test name
Test status
Simulation time 15175200 ps
CPU time 0.97 seconds
Started Feb 04 04:22:28 PM PST 24
Finished Feb 04 04:22:29 PM PST 24
Peak memory 214948 kb
Host smart-11e766c8-18d1-4bec-9607-904ef726d014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118041815 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2118041815
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3993920904
Short name T525
Test name
Test status
Simulation time 270021326 ps
CPU time 2.98 seconds
Started Feb 04 04:22:21 PM PST 24
Finished Feb 04 04:22:27 PM PST 24
Peak memory 215196 kb
Host smart-1a045b4a-c8ef-401b-a243-aadd3b999b29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993920904 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3993920904
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3322971675
Short name T263
Test name
Test status
Simulation time 93433525113 ps
CPU time 516.09 seconds
Started Feb 04 04:22:32 PM PST 24
Finished Feb 04 04:31:10 PM PST 24
Peak memory 218256 kb
Host smart-f2b1118b-984d-456c-94f2-698d8b514226
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322971675 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3322971675
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.27496994
Short name T250
Test name
Test status
Simulation time 118928752 ps
CPU time 0.99 seconds
Started Feb 04 04:22:32 PM PST 24
Finished Feb 04 04:22:34 PM PST 24
Peak memory 206028 kb
Host smart-064fe901-5fb4-4755-a2d4-0ce3427007e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27496994 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.27496994
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.789684269
Short name T704
Test name
Test status
Simulation time 42607714 ps
CPU time 1.38 seconds
Started Feb 04 04:22:32 PM PST 24
Finished Feb 04 04:22:36 PM PST 24
Peak memory 205856 kb
Host smart-1a26fefd-1f54-457e-aea3-bc8f48ba0863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789684269 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.789684269
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.2360144329
Short name T165
Test name
Test status
Simulation time 213530779 ps
CPU time 1.05 seconds
Started Feb 04 04:22:29 PM PST 24
Finished Feb 04 04:22:31 PM PST 24
Peak memory 215348 kb
Host smart-4616b69f-45f9-49b8-9f97-812d2886d2ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360144329 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.2360144329
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.4106577383
Short name T740
Test name
Test status
Simulation time 67774643 ps
CPU time 1.09 seconds
Started Feb 04 04:22:30 PM PST 24
Finished Feb 04 04:22:32 PM PST 24
Peak memory 217828 kb
Host smart-160f8e44-db01-4a3c-8ad8-debcf731fc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106577383 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.4106577383
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.946321575
Short name T532
Test name
Test status
Simulation time 21767318 ps
CPU time 1.1 seconds
Started Feb 04 04:22:34 PM PST 24
Finished Feb 04 04:22:37 PM PST 24
Peak memory 215348 kb
Host smart-f10e0392-26fa-400f-b3af-45f45d0af814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946321575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.946321575
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2729479664
Short name T78
Test name
Test status
Simulation time 18051283 ps
CPU time 1.07 seconds
Started Feb 04 04:22:28 PM PST 24
Finished Feb 04 04:22:30 PM PST 24
Peak memory 215452 kb
Host smart-395f14f6-f41a-4de2-8f33-15691f226823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729479664 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2729479664
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.4243290416
Short name T426
Test name
Test status
Simulation time 23259197 ps
CPU time 0.95 seconds
Started Feb 04 04:22:26 PM PST 24
Finished Feb 04 04:22:28 PM PST 24
Peak memory 214948 kb
Host smart-37201b0e-8dd3-4555-8f02-429df783733e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243290416 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.4243290416
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.4192154248
Short name T830
Test name
Test status
Simulation time 118586124 ps
CPU time 2.89 seconds
Started Feb 04 04:22:28 PM PST 24
Finished Feb 04 04:22:32 PM PST 24
Peak memory 215492 kb
Host smart-bf9cf94f-a4ac-498d-9f0f-d7bdc0b6646d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192154248 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.4192154248
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.4206236329
Short name T495
Test name
Test status
Simulation time 138488876446 ps
CPU time 1592.13 seconds
Started Feb 04 04:22:29 PM PST 24
Finished Feb 04 04:49:02 PM PST 24
Peak memory 222348 kb
Host smart-f2c5b721-f45e-42fe-be74-04946d702004
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206236329 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.4206236329
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1957523678
Short name T246
Test name
Test status
Simulation time 33045640 ps
CPU time 0.98 seconds
Started Feb 04 04:22:30 PM PST 24
Finished Feb 04 04:22:31 PM PST 24
Peak memory 206656 kb
Host smart-d894e974-627b-45ff-b57f-27c4513324c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957523678 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1957523678
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.4088365527
Short name T446
Test name
Test status
Simulation time 16861352 ps
CPU time 0.96 seconds
Started Feb 04 04:22:31 PM PST 24
Finished Feb 04 04:22:34 PM PST 24
Peak memory 205288 kb
Host smart-2964e9cb-1e27-4bc7-964d-48ce321f00f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088365527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.4088365527
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.942789029
Short name T897
Test name
Test status
Simulation time 13083936 ps
CPU time 0.93 seconds
Started Feb 04 04:22:34 PM PST 24
Finished Feb 04 04:22:37 PM PST 24
Peak memory 215188 kb
Host smart-ef82ff38-c36f-413c-97f5-a1fc6b703cbc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942789029 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.942789029
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.2385573621
Short name T120
Test name
Test status
Simulation time 113215648 ps
CPU time 1.2 seconds
Started Feb 04 04:22:32 PM PST 24
Finished Feb 04 04:22:34 PM PST 24
Peak memory 215260 kb
Host smart-0e86c5f9-0784-4358-98ba-7500b003adb6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385573621 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.2385573621
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.1421669915
Short name T679
Test name
Test status
Simulation time 23680535 ps
CPU time 0.93 seconds
Started Feb 04 04:22:34 PM PST 24
Finished Feb 04 04:22:37 PM PST 24
Peak memory 216556 kb
Host smart-b46c06e8-b505-4108-b83b-fc035c3978be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421669915 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1421669915
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2363062869
Short name T724
Test name
Test status
Simulation time 94386400 ps
CPU time 2.32 seconds
Started Feb 04 04:22:33 PM PST 24
Finished Feb 04 04:22:38 PM PST 24
Peak memory 215548 kb
Host smart-6ac85089-7d9f-4f96-9da3-c253c4cbf0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363062869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2363062869
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.2662728973
Short name T87
Test name
Test status
Simulation time 34281229 ps
CPU time 0.9 seconds
Started Feb 04 04:22:33 PM PST 24
Finished Feb 04 04:22:37 PM PST 24
Peak memory 215132 kb
Host smart-2098a743-7087-4441-9511-fbd4b700bf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662728973 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.2662728973
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3247779111
Short name T503
Test name
Test status
Simulation time 86110733 ps
CPU time 0.97 seconds
Started Feb 04 04:22:30 PM PST 24
Finished Feb 04 04:22:33 PM PST 24
Peak memory 214944 kb
Host smart-2355fc1e-2eac-4092-bf01-f7cf71747847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247779111 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3247779111
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.2557313958
Short name T862
Test name
Test status
Simulation time 60740895 ps
CPU time 1.99 seconds
Started Feb 04 04:22:33 PM PST 24
Finished Feb 04 04:22:38 PM PST 24
Peak memory 215284 kb
Host smart-1327d45c-e293-40e9-8288-5d406f81a638
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557313958 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.2557313958
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1321356446
Short name T864
Test name
Test status
Simulation time 89557203623 ps
CPU time 1866.78 seconds
Started Feb 04 04:22:32 PM PST 24
Finished Feb 04 04:53:41 PM PST 24
Peak memory 224112 kb
Host smart-092ac440-3d58-4b6f-ac26-bb59b109c426
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321356446 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1321356446
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3698101176
Short name T611
Test name
Test status
Simulation time 20031114 ps
CPU time 0.98 seconds
Started Feb 04 04:19:18 PM PST 24
Finished Feb 04 04:19:20 PM PST 24
Peak memory 206280 kb
Host smart-c2b63025-e01f-4b2c-a7f0-6356ead6181b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698101176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3698101176
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2735914023
Short name T844
Test name
Test status
Simulation time 37368420 ps
CPU time 0.92 seconds
Started Feb 04 04:19:19 PM PST 24
Finished Feb 04 04:19:26 PM PST 24
Peak memory 205332 kb
Host smart-b1e4b972-fc4d-41b1-be4f-d55a7e2a69bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735914023 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2735914023
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1165114006
Short name T727
Test name
Test status
Simulation time 14795652 ps
CPU time 0.86 seconds
Started Feb 04 04:19:23 PM PST 24
Finished Feb 04 04:19:27 PM PST 24
Peak memory 215008 kb
Host smart-bb8a58ea-1342-41c2-8630-03bb772cfc7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165114006 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1165114006
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1802857249
Short name T105
Test name
Test status
Simulation time 32270646 ps
CPU time 1.01 seconds
Started Feb 04 04:19:23 PM PST 24
Finished Feb 04 04:19:27 PM PST 24
Peak memory 215260 kb
Host smart-f0aee61e-bfdc-410e-9f49-da5f8cb537d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802857249 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1802857249
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2439099458
Short name T121
Test name
Test status
Simulation time 21122658 ps
CPU time 1.02 seconds
Started Feb 04 04:19:16 PM PST 24
Finished Feb 04 04:19:20 PM PST 24
Peak memory 216820 kb
Host smart-fcf866ec-4f23-468f-a2fe-f2f6da219686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439099458 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2439099458
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2016434545
Short name T267
Test name
Test status
Simulation time 17713229 ps
CPU time 1.05 seconds
Started Feb 04 04:19:18 PM PST 24
Finished Feb 04 04:19:20 PM PST 24
Peak memory 215524 kb
Host smart-e9b4e0f5-524f-421f-adf6-4abff52c24c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016434545 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2016434545
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3020610145
Short name T85
Test name
Test status
Simulation time 59264884 ps
CPU time 0.96 seconds
Started Feb 04 04:19:21 PM PST 24
Finished Feb 04 04:19:27 PM PST 24
Peak memory 225496 kb
Host smart-55eef0ad-8a9e-4ec3-a518-8672af5ad536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020610145 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3020610145
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.536933685
Short name T793
Test name
Test status
Simulation time 15519263 ps
CPU time 0.95 seconds
Started Feb 04 04:19:20 PM PST 24
Finished Feb 04 04:19:27 PM PST 24
Peak memory 206760 kb
Host smart-65f9c299-c5db-471c-9cb8-68b5b3fae2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536933685 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.536933685
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.2384473227
Short name T591
Test name
Test status
Simulation time 22430089 ps
CPU time 0.97 seconds
Started Feb 04 04:19:15 PM PST 24
Finished Feb 04 04:19:18 PM PST 24
Peak memory 214912 kb
Host smart-6a207d4f-c41f-4ab8-912a-407dd53acebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384473227 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.2384473227
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2093491894
Short name T449
Test name
Test status
Simulation time 225172982 ps
CPU time 3.18 seconds
Started Feb 04 04:19:23 PM PST 24
Finished Feb 04 04:19:29 PM PST 24
Peak memory 214996 kb
Host smart-9bc4114b-e890-4c11-adce-fd905af793f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093491894 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2093491894
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.3846724918
Short name T931
Test name
Test status
Simulation time 218823967143 ps
CPU time 622.49 seconds
Started Feb 04 04:19:28 PM PST 24
Finished Feb 04 04:29:51 PM PST 24
Peak memory 218676 kb
Host smart-b0dfce7c-2946-4f6d-b7df-a6a15ba86b4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846724918 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.3846724918
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.777620144
Short name T135
Test name
Test status
Simulation time 29550406 ps
CPU time 1.22 seconds
Started Feb 04 04:22:32 PM PST 24
Finished Feb 04 04:22:35 PM PST 24
Peak memory 217808 kb
Host smart-6d8f4e18-eb6a-40b1-a190-a028c8381017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777620144 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.777620144
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3113764648
Short name T790
Test name
Test status
Simulation time 68710168 ps
CPU time 1.14 seconds
Started Feb 04 04:22:31 PM PST 24
Finished Feb 04 04:22:34 PM PST 24
Peak memory 215748 kb
Host smart-abe7e4d8-9302-4011-a5f0-68e6f324bfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113764648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3113764648
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.1234167548
Short name T484
Test name
Test status
Simulation time 18804652 ps
CPU time 1.09 seconds
Started Feb 04 04:22:37 PM PST 24
Finished Feb 04 04:22:43 PM PST 24
Peak memory 216784 kb
Host smart-0935faa8-a8af-4c13-8f84-b25af032b537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234167548 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1234167548
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/52.edn_err.843684986
Short name T856
Test name
Test status
Simulation time 22904915 ps
CPU time 0.93 seconds
Started Feb 04 04:22:39 PM PST 24
Finished Feb 04 04:22:44 PM PST 24
Peak memory 216676 kb
Host smart-274ea2f6-38af-473d-9d17-57a6dfd50946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843684986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.843684986
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3967832884
Short name T629
Test name
Test status
Simulation time 68003094 ps
CPU time 1.69 seconds
Started Feb 04 04:22:38 PM PST 24
Finished Feb 04 04:22:44 PM PST 24
Peak memory 217972 kb
Host smart-83b28531-319c-4189-9620-99cbd8cf7fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967832884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3967832884
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.157545650
Short name T112
Test name
Test status
Simulation time 57558264 ps
CPU time 1.13 seconds
Started Feb 04 04:22:38 PM PST 24
Finished Feb 04 04:22:44 PM PST 24
Peak memory 222672 kb
Host smart-5bf848a7-aef2-43de-9edf-f6c9b05c9dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157545650 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.157545650
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3731804108
Short name T909
Test name
Test status
Simulation time 82511315 ps
CPU time 1.07 seconds
Started Feb 04 04:22:36 PM PST 24
Finished Feb 04 04:22:38 PM PST 24
Peak memory 215568 kb
Host smart-010686dd-7286-4b9e-b489-c7672017507d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731804108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3731804108
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.2679010813
Short name T74
Test name
Test status
Simulation time 27282938 ps
CPU time 0.88 seconds
Started Feb 04 04:22:38 PM PST 24
Finished Feb 04 04:22:44 PM PST 24
Peak memory 216232 kb
Host smart-69d616fe-6450-4f1f-a579-744cc05b85e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679010813 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.2679010813
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3219837770
Short name T938
Test name
Test status
Simulation time 147922837 ps
CPU time 1.1 seconds
Started Feb 04 04:22:39 PM PST 24
Finished Feb 04 04:22:44 PM PST 24
Peak memory 215344 kb
Host smart-a1ae7d72-28de-46d7-aff8-b2c47e163e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219837770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3219837770
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_genbits.1422747282
Short name T298
Test name
Test status
Simulation time 101806790 ps
CPU time 1.15 seconds
Started Feb 04 04:22:37 PM PST 24
Finished Feb 04 04:22:43 PM PST 24
Peak memory 216692 kb
Host smart-958f2033-bdb0-40ad-8126-e58d77b3c0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422747282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1422747282
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.2075308467
Short name T58
Test name
Test status
Simulation time 28066179 ps
CPU time 0.99 seconds
Started Feb 04 04:22:46 PM PST 24
Finished Feb 04 04:22:48 PM PST 24
Peak memory 216444 kb
Host smart-b4178df4-98dd-40e6-ab12-186461786045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075308467 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2075308467
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.906303954
Short name T773
Test name
Test status
Simulation time 15925725 ps
CPU time 1.18 seconds
Started Feb 04 04:22:39 PM PST 24
Finished Feb 04 04:22:44 PM PST 24
Peak memory 215412 kb
Host smart-98e42e9e-88ee-474a-876b-8926920fc871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906303954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.906303954
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.688428230
Short name T485
Test name
Test status
Simulation time 19110592 ps
CPU time 1.02 seconds
Started Feb 04 04:22:42 PM PST 24
Finished Feb 04 04:22:44 PM PST 24
Peak memory 216524 kb
Host smart-271e4dfd-8110-4380-8575-b08eee4679d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688428230 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.688428230
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1941250449
Short name T696
Test name
Test status
Simulation time 27807401 ps
CPU time 1.03 seconds
Started Feb 04 04:22:47 PM PST 24
Finished Feb 04 04:22:49 PM PST 24
Peak memory 215244 kb
Host smart-39321c2d-3f3e-4e8d-beba-6e02cc5104b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941250449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1941250449
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.889420695
Short name T850
Test name
Test status
Simulation time 165435739 ps
CPU time 0.92 seconds
Started Feb 04 04:22:43 PM PST 24
Finished Feb 04 04:22:46 PM PST 24
Peak memory 216732 kb
Host smart-5f553a06-1387-476f-93a9-fce606662db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889420695 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.889420695
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2354352108
Short name T866
Test name
Test status
Simulation time 252011872 ps
CPU time 1.21 seconds
Started Feb 04 04:22:39 PM PST 24
Finished Feb 04 04:22:44 PM PST 24
Peak memory 216532 kb
Host smart-9ab4c871-8890-4dcc-b9d8-a6427aea6fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354352108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2354352108
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.2539396059
Short name T700
Test name
Test status
Simulation time 135656010 ps
CPU time 1.04 seconds
Started Feb 04 04:22:47 PM PST 24
Finished Feb 04 04:22:49 PM PST 24
Peak memory 217744 kb
Host smart-b680a7fe-3997-4554-afc0-3a5c5d71798d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539396059 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2539396059
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.1212844038
Short name T310
Test name
Test status
Simulation time 50308403 ps
CPU time 1.22 seconds
Started Feb 04 04:22:45 PM PST 24
Finished Feb 04 04:22:47 PM PST 24
Peak memory 216668 kb
Host smart-54d42640-6b0a-4040-9265-59fca7d8f20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212844038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.1212844038
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3026457942
Short name T772
Test name
Test status
Simulation time 19952053 ps
CPU time 1.08 seconds
Started Feb 04 04:19:40 PM PST 24
Finished Feb 04 04:19:44 PM PST 24
Peak memory 206616 kb
Host smart-376345b4-239a-48e4-8634-0a870924bec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026457942 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3026457942
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3937880195
Short name T729
Test name
Test status
Simulation time 18902775 ps
CPU time 0.96 seconds
Started Feb 04 04:19:40 PM PST 24
Finished Feb 04 04:19:44 PM PST 24
Peak memory 205328 kb
Host smart-b51e4e5a-397a-4fbe-8c1a-07cd4032f3b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937880195 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3937880195
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.792763685
Short name T160
Test name
Test status
Simulation time 14077530 ps
CPU time 0.96 seconds
Started Feb 04 04:19:41 PM PST 24
Finished Feb 04 04:19:45 PM PST 24
Peak memory 215216 kb
Host smart-d2c45fda-d509-41b0-a3b3-664e14185a57
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792763685 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.792763685
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2240848890
Short name T885
Test name
Test status
Simulation time 19331254 ps
CPU time 1.03 seconds
Started Feb 04 04:19:42 PM PST 24
Finished Feb 04 04:19:45 PM PST 24
Peak memory 215196 kb
Host smart-a1dd60c4-7088-4f24-a3b5-ea04c42b3076
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240848890 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2240848890
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.229371442
Short name T464
Test name
Test status
Simulation time 20314214 ps
CPU time 1.09 seconds
Started Feb 04 04:19:37 PM PST 24
Finished Feb 04 04:19:40 PM PST 24
Peak memory 216516 kb
Host smart-c21bc5fe-fabb-4061-a5aa-3bfa35a9a689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229371442 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.229371442
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3361234386
Short name T540
Test name
Test status
Simulation time 27415136 ps
CPU time 1.25 seconds
Started Feb 04 04:19:20 PM PST 24
Finished Feb 04 04:19:27 PM PST 24
Peak memory 216716 kb
Host smart-f43608b9-6d25-4e28-acb9-9180b4466826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361234386 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3361234386
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.199746106
Short name T698
Test name
Test status
Simulation time 28157367 ps
CPU time 1.01 seconds
Started Feb 04 04:19:17 PM PST 24
Finished Feb 04 04:19:20 PM PST 24
Peak memory 215196 kb
Host smart-e5f7d6d8-6ed2-4f2d-8ca8-b5bf51d5b51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199746106 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.199746106
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.82999360
Short name T254
Test name
Test status
Simulation time 13742520 ps
CPU time 0.88 seconds
Started Feb 04 04:19:18 PM PST 24
Finished Feb 04 04:19:20 PM PST 24
Peak memory 206328 kb
Host smart-826c6106-8ff9-48aa-88e6-e8a07023eaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82999360 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.82999360
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.548626944
Short name T809
Test name
Test status
Simulation time 13479985 ps
CPU time 0.91 seconds
Started Feb 04 04:19:23 PM PST 24
Finished Feb 04 04:19:27 PM PST 24
Peak memory 214900 kb
Host smart-5ea442e6-7e7d-475c-a3b4-0bc49da98740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548626944 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.548626944
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.2999759059
Short name T907
Test name
Test status
Simulation time 35344862 ps
CPU time 1.42 seconds
Started Feb 04 04:19:20 PM PST 24
Finished Feb 04 04:19:28 PM PST 24
Peak memory 215168 kb
Host smart-dc14085b-d265-4f38-8295-aa33feb04018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999759059 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.2999759059
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1131291375
Short name T575
Test name
Test status
Simulation time 8695747538 ps
CPU time 212.37 seconds
Started Feb 04 04:19:23 PM PST 24
Finished Feb 04 04:22:59 PM PST 24
Peak memory 216892 kb
Host smart-4e5a6ae1-5c95-4044-afa5-de7307383261
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131291375 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1131291375
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.3845164184
Short name T529
Test name
Test status
Simulation time 19138495 ps
CPU time 1.13 seconds
Started Feb 04 04:22:45 PM PST 24
Finished Feb 04 04:22:47 PM PST 24
Peak memory 216556 kb
Host smart-d047e110-2f3d-4e1f-b66c-3d5c24d1ac2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845164184 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3845164184
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3029595540
Short name T14
Test name
Test status
Simulation time 60868223 ps
CPU time 1.22 seconds
Started Feb 04 04:22:45 PM PST 24
Finished Feb 04 04:22:47 PM PST 24
Peak memory 215632 kb
Host smart-a03a09e2-76d6-4a6b-a6ab-0aab36ff245e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029595540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3029595540
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.134477419
Short name T133
Test name
Test status
Simulation time 18074641 ps
CPU time 1.08 seconds
Started Feb 04 04:22:42 PM PST 24
Finished Feb 04 04:22:44 PM PST 24
Peak memory 216696 kb
Host smart-9c8046cc-a3c4-4809-9278-8ec17a301702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134477419 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.134477419
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3547598102
Short name T554
Test name
Test status
Simulation time 33168812 ps
CPU time 1.1 seconds
Started Feb 04 04:22:42 PM PST 24
Finished Feb 04 04:22:44 PM PST 24
Peak memory 215544 kb
Host smart-7fb26989-5cec-46c3-a30b-1a617a700028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547598102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3547598102
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.2346755321
Short name T559
Test name
Test status
Simulation time 22923321 ps
CPU time 0.95 seconds
Started Feb 04 04:22:52 PM PST 24
Finished Feb 04 04:22:53 PM PST 24
Peak memory 216620 kb
Host smart-8330d6ec-e4b9-475c-866d-871c306c077f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346755321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2346755321
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.235356403
Short name T564
Test name
Test status
Simulation time 15833774 ps
CPU time 1.17 seconds
Started Feb 04 04:22:51 PM PST 24
Finished Feb 04 04:22:53 PM PST 24
Peak memory 215236 kb
Host smart-8b618aad-8b40-4656-bb2a-6713a6056319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235356403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.235356403
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.1035826161
Short name T131
Test name
Test status
Simulation time 50282708 ps
CPU time 0.89 seconds
Started Feb 04 04:22:59 PM PST 24
Finished Feb 04 04:23:03 PM PST 24
Peak memory 216664 kb
Host smart-0d26621a-ff33-4cc5-a425-decf5c6470bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035826161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1035826161
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.3542530375
Short name T30
Test name
Test status
Simulation time 44881252 ps
CPU time 1.25 seconds
Started Feb 04 04:22:48 PM PST 24
Finished Feb 04 04:22:51 PM PST 24
Peak memory 216780 kb
Host smart-de9c408c-f69a-4cc9-824d-af69e15591ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542530375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.3542530375
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.1775904440
Short name T110
Test name
Test status
Simulation time 53353325 ps
CPU time 1.13 seconds
Started Feb 04 04:22:51 PM PST 24
Finished Feb 04 04:22:53 PM PST 24
Peak memory 230868 kb
Host smart-afd18840-240c-429c-aab9-0e588701760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775904440 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.1775904440
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.1970981916
Short name T646
Test name
Test status
Simulation time 72002513 ps
CPU time 1.17 seconds
Started Feb 04 04:22:48 PM PST 24
Finished Feb 04 04:22:51 PM PST 24
Peak memory 216700 kb
Host smart-13dba7d9-c16a-4fd5-8198-b1db7363b6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970981916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.1970981916
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.3996646055
Short name T325
Test name
Test status
Simulation time 50742900 ps
CPU time 1.26 seconds
Started Feb 04 04:22:53 PM PST 24
Finished Feb 04 04:22:55 PM PST 24
Peak memory 217892 kb
Host smart-6f96e244-42a2-404e-88b4-38eea3b9c47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996646055 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3996646055
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2023334624
Short name T917
Test name
Test status
Simulation time 44209985 ps
CPU time 1.01 seconds
Started Feb 04 04:22:52 PM PST 24
Finished Feb 04 04:22:54 PM PST 24
Peak memory 215380 kb
Host smart-9dab3f02-1d0b-43bc-aced-6035105def52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023334624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2023334624
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.1284624163
Short name T138
Test name
Test status
Simulation time 22671586 ps
CPU time 1.03 seconds
Started Feb 04 04:22:52 PM PST 24
Finished Feb 04 04:22:54 PM PST 24
Peak memory 222640 kb
Host smart-affa37b3-6daf-4f27-bab5-eb1984e21d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284624163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1284624163
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.2930170939
Short name T766
Test name
Test status
Simulation time 127322052 ps
CPU time 2.93 seconds
Started Feb 04 04:22:51 PM PST 24
Finished Feb 04 04:22:55 PM PST 24
Peak memory 216780 kb
Host smart-39bf22e4-7028-4c84-a4b9-1880fbcd51b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930170939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.2930170939
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.2663629131
Short name T155
Test name
Test status
Simulation time 23394163 ps
CPU time 0.97 seconds
Started Feb 04 04:22:52 PM PST 24
Finished Feb 04 04:22:54 PM PST 24
Peak memory 216320 kb
Host smart-30054388-11d2-4743-9fe4-994d69d43cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663629131 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2663629131
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2817582834
Short name T451
Test name
Test status
Simulation time 31602191 ps
CPU time 1.06 seconds
Started Feb 04 04:22:51 PM PST 24
Finished Feb 04 04:22:53 PM PST 24
Peak memory 213900 kb
Host smart-561b979f-204b-4924-82f6-4cb91bfd86d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817582834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2817582834
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_genbits.1400658835
Short name T712
Test name
Test status
Simulation time 62342583 ps
CPU time 2.61 seconds
Started Feb 04 04:22:52 PM PST 24
Finished Feb 04 04:22:55 PM PST 24
Peak memory 218380 kb
Host smart-fa0aa43b-9d0d-4b7a-acb6-2c269bc0956d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400658835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1400658835
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.1409079793
Short name T84
Test name
Test status
Simulation time 57835598 ps
CPU time 1.22 seconds
Started Feb 04 04:22:56 PM PST 24
Finished Feb 04 04:22:59 PM PST 24
Peak memory 222780 kb
Host smart-ed58625f-ee95-4a5d-bc39-5f64200dbb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409079793 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1409079793
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.4076703707
Short name T304
Test name
Test status
Simulation time 116002359 ps
CPU time 1.3 seconds
Started Feb 04 04:22:53 PM PST 24
Finished Feb 04 04:22:55 PM PST 24
Peak memory 214960 kb
Host smart-b51541e2-fd36-4b2f-b3b1-fcf67f439600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076703707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.4076703707
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.4165311917
Short name T723
Test name
Test status
Simulation time 19748040 ps
CPU time 1.05 seconds
Started Feb 04 04:19:35 PM PST 24
Finished Feb 04 04:19:37 PM PST 24
Peak memory 206648 kb
Host smart-3edb2d35-d4e9-4854-9104-08ccb0356df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165311917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.4165311917
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.694334017
Short name T735
Test name
Test status
Simulation time 29007502 ps
CPU time 0.85 seconds
Started Feb 04 04:19:41 PM PST 24
Finished Feb 04 04:19:45 PM PST 24
Peak memory 204932 kb
Host smart-b1fe39e8-137e-407d-92e5-208b21e3d793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694334017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.694334017
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.4167769304
Short name T548
Test name
Test status
Simulation time 11226240 ps
CPU time 0.88 seconds
Started Feb 04 04:19:46 PM PST 24
Finished Feb 04 04:19:53 PM PST 24
Peak memory 215020 kb
Host smart-e73c7c23-c7c8-4e39-a868-63812a4d53f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167769304 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.4167769304
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.19221834
Short name T743
Test name
Test status
Simulation time 28996888 ps
CPU time 1.16 seconds
Started Feb 04 04:19:38 PM PST 24
Finished Feb 04 04:19:42 PM PST 24
Peak memory 217628 kb
Host smart-22767f69-b477-480c-87b4-da5388639e59
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19221834 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disa
ble_auto_req_mode.19221834
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_genbits.3762700353
Short name T551
Test name
Test status
Simulation time 101073614 ps
CPU time 1.26 seconds
Started Feb 04 04:19:39 PM PST 24
Finished Feb 04 04:19:44 PM PST 24
Peak memory 216720 kb
Host smart-ee86afe1-ed90-421e-bd6b-8411475be78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762700353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3762700353
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.497045914
Short name T524
Test name
Test status
Simulation time 22792152 ps
CPU time 0.99 seconds
Started Feb 04 04:19:39 PM PST 24
Finished Feb 04 04:19:44 PM PST 24
Peak memory 215412 kb
Host smart-636f31b6-f581-4cef-a08e-b58bfccb3d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497045914 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.497045914
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3479724801
Short name T72
Test name
Test status
Simulation time 12577828 ps
CPU time 0.94 seconds
Started Feb 04 04:19:34 PM PST 24
Finished Feb 04 04:19:35 PM PST 24
Peak memory 206748 kb
Host smart-e5adec3d-363b-4328-b082-a880b63c12d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479724801 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3479724801
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.3255578896
Short name T684
Test name
Test status
Simulation time 20176358 ps
CPU time 0.96 seconds
Started Feb 04 04:19:35 PM PST 24
Finished Feb 04 04:19:37 PM PST 24
Peak memory 214976 kb
Host smart-13e5d0d8-1464-4dfb-96d5-aac939ba6eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255578896 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.3255578896
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.4042682468
Short name T893
Test name
Test status
Simulation time 548197001 ps
CPU time 3.58 seconds
Started Feb 04 04:19:37 PM PST 24
Finished Feb 04 04:19:41 PM PST 24
Peak memory 214984 kb
Host smart-5bcdd130-8729-49a9-9439-5d46665bcb3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042682468 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.4042682468
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1480583030
Short name T470
Test name
Test status
Simulation time 64868032944 ps
CPU time 1706.27 seconds
Started Feb 04 04:19:37 PM PST 24
Finished Feb 04 04:48:04 PM PST 24
Peak memory 224200 kb
Host smart-be0d87eb-e78c-4bc3-880b-58e6fdc92c1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480583030 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1480583030
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.85473655
Short name T8
Test name
Test status
Simulation time 33560286 ps
CPU time 1.66 seconds
Started Feb 04 04:22:52 PM PST 24
Finished Feb 04 04:22:54 PM PST 24
Peak memory 222780 kb
Host smart-ba2d9ad7-d129-497c-8e1d-be676a329b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85473655 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.85473655
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2879319742
Short name T462
Test name
Test status
Simulation time 59730822 ps
CPU time 1.07 seconds
Started Feb 04 04:22:51 PM PST 24
Finished Feb 04 04:22:53 PM PST 24
Peak memory 216760 kb
Host smart-f338fe5c-606c-4142-97ee-43c1b476f6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879319742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2879319742
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.3702303778
Short name T149
Test name
Test status
Simulation time 29658017 ps
CPU time 0.99 seconds
Started Feb 04 04:22:50 PM PST 24
Finished Feb 04 04:22:51 PM PST 24
Peak memory 216572 kb
Host smart-efcfd5ab-a983-4405-8322-94e39a1d7d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702303778 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3702303778
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1369827235
Short name T319
Test name
Test status
Simulation time 22216063 ps
CPU time 1.42 seconds
Started Feb 04 04:22:59 PM PST 24
Finished Feb 04 04:23:04 PM PST 24
Peak memory 215676 kb
Host smart-c9957853-7bfa-48e1-891f-c398d2145e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369827235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1369827235
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.23647448
Short name T720
Test name
Test status
Simulation time 30606951 ps
CPU time 1.49 seconds
Started Feb 04 04:22:56 PM PST 24
Finished Feb 04 04:23:00 PM PST 24
Peak memory 222688 kb
Host smart-da5a7d65-bf08-474c-a0f2-74189ffa051f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23647448 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.23647448
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.4013485097
Short name T493
Test name
Test status
Simulation time 35948507 ps
CPU time 1.09 seconds
Started Feb 04 04:22:57 PM PST 24
Finished Feb 04 04:23:01 PM PST 24
Peak memory 215760 kb
Host smart-54ec78c5-153d-4b79-9694-66f6e6585ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013485097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.4013485097
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.2001919877
Short name T139
Test name
Test status
Simulation time 18159180 ps
CPU time 1.18 seconds
Started Feb 04 04:22:52 PM PST 24
Finished Feb 04 04:22:54 PM PST 24
Peak memory 222628 kb
Host smart-0abce99a-fe10-45dd-a126-f784c97eca5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001919877 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.2001919877
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.4039470236
Short name T912
Test name
Test status
Simulation time 41703348 ps
CPU time 1.14 seconds
Started Feb 04 04:22:57 PM PST 24
Finished Feb 04 04:23:02 PM PST 24
Peak memory 215112 kb
Host smart-4e7fcafa-ef33-4ee3-b79c-48be2eec1a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039470236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.4039470236
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.2386838001
Short name T162
Test name
Test status
Simulation time 69652945 ps
CPU time 1.07 seconds
Started Feb 04 04:22:57 PM PST 24
Finished Feb 04 04:23:02 PM PST 24
Peak memory 217272 kb
Host smart-b2b0df34-f39e-4e0a-8448-5c377ee979f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386838001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2386838001
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/75.edn_err.776968625
Short name T113
Test name
Test status
Simulation time 53353181 ps
CPU time 1.2 seconds
Started Feb 04 04:22:56 PM PST 24
Finished Feb 04 04:22:59 PM PST 24
Peak memory 222656 kb
Host smart-6ed7749c-29f1-4f3d-8050-c8a392e1e000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776968625 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.776968625
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3677395350
Short name T547
Test name
Test status
Simulation time 181774588 ps
CPU time 1.37 seconds
Started Feb 04 04:22:56 PM PST 24
Finished Feb 04 04:23:00 PM PST 24
Peak memory 215428 kb
Host smart-8b53608e-3935-4810-a401-d450ba652f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677395350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3677395350
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_genbits.2476085620
Short name T560
Test name
Test status
Simulation time 86652247 ps
CPU time 1.14 seconds
Started Feb 04 04:22:57 PM PST 24
Finished Feb 04 04:23:02 PM PST 24
Peak memory 216796 kb
Host smart-09b18ddc-3fb9-45ee-8197-bc3f4b12d9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476085620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2476085620
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.2591231383
Short name T600
Test name
Test status
Simulation time 88606893 ps
CPU time 0.83 seconds
Started Feb 04 04:23:05 PM PST 24
Finished Feb 04 04:23:10 PM PST 24
Peak memory 216488 kb
Host smart-1d28b972-2bdc-4ad8-a3de-3ec05555e72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591231383 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2591231383
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.1013590425
Short name T624
Test name
Test status
Simulation time 50488879 ps
CPU time 0.99 seconds
Started Feb 04 04:22:57 PM PST 24
Finished Feb 04 04:23:01 PM PST 24
Peak memory 216748 kb
Host smart-26851b09-70a2-41f0-9afc-70f2602da18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013590425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1013590425
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.4044967471
Short name T858
Test name
Test status
Simulation time 64201521 ps
CPU time 0.93 seconds
Started Feb 04 04:22:56 PM PST 24
Finished Feb 04 04:23:00 PM PST 24
Peak memory 216828 kb
Host smart-a14225d6-fa25-47d8-b5e8-3c757c87f331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044967471 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.4044967471
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3207575700
Short name T877
Test name
Test status
Simulation time 106314072 ps
CPU time 1.13 seconds
Started Feb 04 04:22:57 PM PST 24
Finished Feb 04 04:23:02 PM PST 24
Peak memory 215112 kb
Host smart-7a10cb65-7890-4030-afed-e16d8fa821af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207575700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3207575700
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.2934341983
Short name T108
Test name
Test status
Simulation time 52291295 ps
CPU time 1.12 seconds
Started Feb 04 04:23:00 PM PST 24
Finished Feb 04 04:23:03 PM PST 24
Peak memory 217080 kb
Host smart-eba7bd61-562d-4326-a6c7-d05454420c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934341983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2934341983
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3551324114
Short name T777
Test name
Test status
Simulation time 20751178 ps
CPU time 1.13 seconds
Started Feb 04 04:22:58 PM PST 24
Finished Feb 04 04:23:03 PM PST 24
Peak memory 215228 kb
Host smart-2c6b9b8f-d2dc-49f5-bd4d-45fb1a9e3427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551324114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3551324114
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2327107244
Short name T823
Test name
Test status
Simulation time 32353746 ps
CPU time 1.04 seconds
Started Feb 04 04:19:38 PM PST 24
Finished Feb 04 04:19:41 PM PST 24
Peak memory 206772 kb
Host smart-aaab0f2a-5723-459a-9ec0-47cff6a290ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327107244 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2327107244
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2123011504
Short name T637
Test name
Test status
Simulation time 56298868 ps
CPU time 0.94 seconds
Started Feb 04 04:19:44 PM PST 24
Finished Feb 04 04:19:46 PM PST 24
Peak memory 205376 kb
Host smart-bddda7c0-5fcb-47bd-aca6-1591627d0e43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123011504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2123011504
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2584978891
Short name T107
Test name
Test status
Simulation time 64623734 ps
CPU time 1 seconds
Started Feb 04 04:19:43 PM PST 24
Finished Feb 04 04:19:46 PM PST 24
Peak memory 215248 kb
Host smart-0950fb7a-0cb0-4171-a905-5a2c69f817b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584978891 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2584978891
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.1041924734
Short name T127
Test name
Test status
Simulation time 52111407 ps
CPU time 1.21 seconds
Started Feb 04 04:19:45 PM PST 24
Finished Feb 04 04:19:52 PM PST 24
Peak memory 222764 kb
Host smart-7a899349-b134-47f6-a406-145f4ffd6f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041924734 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1041924734
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.772849225
Short name T476
Test name
Test status
Simulation time 34598476 ps
CPU time 1.24 seconds
Started Feb 04 04:19:49 PM PST 24
Finished Feb 04 04:19:53 PM PST 24
Peak memory 215452 kb
Host smart-8ba8b3c0-b82f-4d23-9c1c-9c3f75afeecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772849225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.772849225
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3793684566
Short name T57
Test name
Test status
Simulation time 26968297 ps
CPU time 1.05 seconds
Started Feb 04 04:19:41 PM PST 24
Finished Feb 04 04:19:45 PM PST 24
Peak memory 222796 kb
Host smart-060e1aa6-1326-45e5-ae3a-6091ebfab3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793684566 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3793684566
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_smoke.1089741367
Short name T794
Test name
Test status
Simulation time 13417285 ps
CPU time 0.95 seconds
Started Feb 04 04:19:40 PM PST 24
Finished Feb 04 04:19:44 PM PST 24
Peak memory 214948 kb
Host smart-5f570fd3-b753-4a76-8e96-d9157aa3917c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089741367 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1089741367
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.4094990792
Short name T752
Test name
Test status
Simulation time 391528094 ps
CPU time 2.14 seconds
Started Feb 04 04:19:44 PM PST 24
Finished Feb 04 04:19:47 PM PST 24
Peak memory 214876 kb
Host smart-8837d201-19af-47a3-a6dc-410e055614cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094990792 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.4094990792
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3449046243
Short name T91
Test name
Test status
Simulation time 178599376571 ps
CPU time 635.47 seconds
Started Feb 04 04:19:50 PM PST 24
Finished Feb 04 04:30:28 PM PST 24
Peak memory 223396 kb
Host smart-b205b918-98a2-4e8a-a2d1-f1baed0ba9f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449046243 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3449046243
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.1923751453
Short name T140
Test name
Test status
Simulation time 28182497 ps
CPU time 0.83 seconds
Started Feb 04 04:23:00 PM PST 24
Finished Feb 04 04:23:03 PM PST 24
Peak memory 216324 kb
Host smart-bbd6c3ab-d35e-406d-953b-2c17b6050662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923751453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1923751453
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2157224323
Short name T821
Test name
Test status
Simulation time 45074920 ps
CPU time 1.05 seconds
Started Feb 04 04:23:00 PM PST 24
Finished Feb 04 04:23:03 PM PST 24
Peak memory 214932 kb
Host smart-a374dad6-e698-4519-a611-e95ef5896bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157224323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2157224323
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.1081520936
Short name T439
Test name
Test status
Simulation time 35528568 ps
CPU time 1.05 seconds
Started Feb 04 04:23:01 PM PST 24
Finished Feb 04 04:23:05 PM PST 24
Peak memory 216724 kb
Host smart-72857d63-7be2-4c56-99b3-0bd56611559c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081520936 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1081520936
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.2726544543
Short name T66
Test name
Test status
Simulation time 15128014 ps
CPU time 1.11 seconds
Started Feb 04 04:22:59 PM PST 24
Finished Feb 04 04:23:03 PM PST 24
Peak memory 216584 kb
Host smart-9ba40719-69ab-445d-a7c0-87498e987c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726544543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.2726544543
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.4212788618
Short name T892
Test name
Test status
Simulation time 30257097 ps
CPU time 1.09 seconds
Started Feb 04 04:23:00 PM PST 24
Finished Feb 04 04:23:03 PM PST 24
Peak memory 216876 kb
Host smart-cbbdaba0-a9b1-4237-96a5-3c105d2b6904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212788618 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.4212788618
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.528877026
Short name T936
Test name
Test status
Simulation time 24970877 ps
CPU time 1.02 seconds
Started Feb 04 04:23:00 PM PST 24
Finished Feb 04 04:23:05 PM PST 24
Peak memory 215512 kb
Host smart-0d31a806-6107-4968-a5c4-abf2e43bef36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528877026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.528877026
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.1516309517
Short name T516
Test name
Test status
Simulation time 19101771 ps
CPU time 1.11 seconds
Started Feb 04 04:23:10 PM PST 24
Finished Feb 04 04:23:12 PM PST 24
Peak memory 216584 kb
Host smart-20edc564-e522-48f5-b2e9-908fa96b5a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516309517 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.1516309517
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.983178243
Short name T873
Test name
Test status
Simulation time 138131917 ps
CPU time 1.35 seconds
Started Feb 04 04:23:08 PM PST 24
Finished Feb 04 04:23:11 PM PST 24
Peak memory 216576 kb
Host smart-194ccea1-e94c-460d-8a47-7ede6aa98430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983178243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.983178243
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.2267736039
Short name T132
Test name
Test status
Simulation time 21961070 ps
CPU time 0.92 seconds
Started Feb 04 04:22:59 PM PST 24
Finished Feb 04 04:23:03 PM PST 24
Peak memory 216556 kb
Host smart-9a91f4ec-dd14-408b-a245-7184171525be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267736039 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2267736039
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2156536835
Short name T631
Test name
Test status
Simulation time 29178020 ps
CPU time 1.38 seconds
Started Feb 04 04:23:14 PM PST 24
Finished Feb 04 04:23:16 PM PST 24
Peak memory 217612 kb
Host smart-62d554ae-b9f3-498e-b2be-bdd47d155217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156536835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2156536835
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_genbits.2043530674
Short name T311
Test name
Test status
Simulation time 35950706 ps
CPU time 1.28 seconds
Started Feb 04 04:23:03 PM PST 24
Finished Feb 04 04:23:10 PM PST 24
Peak memory 215328 kb
Host smart-0d870a8b-1bc4-4dd6-baa3-261dd0f18c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043530674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2043530674
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.1783767523
Short name T440
Test name
Test status
Simulation time 59582056 ps
CPU time 0.84 seconds
Started Feb 04 04:23:14 PM PST 24
Finished Feb 04 04:23:15 PM PST 24
Peak memory 216540 kb
Host smart-38d1364f-f96b-4d4b-8c18-cee08133558c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783767523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1783767523
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.2895584019
Short name T615
Test name
Test status
Simulation time 63131939 ps
CPU time 1.26 seconds
Started Feb 04 04:23:10 PM PST 24
Finished Feb 04 04:23:12 PM PST 24
Peak memory 216756 kb
Host smart-d7873abf-8abb-473c-ac09-111bbcf578eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895584019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2895584019
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1668751182
Short name T55
Test name
Test status
Simulation time 24703848 ps
CPU time 1.12 seconds
Started Feb 04 04:23:08 PM PST 24
Finished Feb 04 04:23:11 PM PST 24
Peak memory 222668 kb
Host smart-3389c83d-05a8-4b40-bf84-d11d34df47f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668751182 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1668751182
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.1277958646
Short name T749
Test name
Test status
Simulation time 64626651 ps
CPU time 1.15 seconds
Started Feb 04 04:23:03 PM PST 24
Finished Feb 04 04:23:10 PM PST 24
Peak memory 215392 kb
Host smart-c7244e86-6678-4e42-a251-866aef8d78fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277958646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.1277958646
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.1520898491
Short name T693
Test name
Test status
Simulation time 178153236 ps
CPU time 1.05 seconds
Started Feb 04 04:23:10 PM PST 24
Finished Feb 04 04:23:12 PM PST 24
Peak memory 222776 kb
Host smart-ee39b27b-d63a-48fb-810d-b0d0d8c6e3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520898491 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.1520898491
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.84254177
Short name T268
Test name
Test status
Simulation time 37830598 ps
CPU time 1.1 seconds
Started Feb 04 04:23:09 PM PST 24
Finished Feb 04 04:23:12 PM PST 24
Peak memory 215440 kb
Host smart-fa6e269f-4d5b-414a-987b-f8c66e9764ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84254177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.84254177
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.2694851415
Short name T716
Test name
Test status
Simulation time 32655052 ps
CPU time 0.9 seconds
Started Feb 04 04:23:12 PM PST 24
Finished Feb 04 04:23:14 PM PST 24
Peak memory 217008 kb
Host smart-14586fae-08db-45a6-9637-dfd4b1a64055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694851415 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2694851415
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.3346615458
Short name T691
Test name
Test status
Simulation time 343644604 ps
CPU time 1.16 seconds
Started Feb 04 04:23:09 PM PST 24
Finished Feb 04 04:23:11 PM PST 24
Peak memory 216648 kb
Host smart-03af5362-1242-4e84-9a28-818cac1c09bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346615458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.3346615458
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.3933593061
Short name T19
Test name
Test status
Simulation time 19560135 ps
CPU time 1.05 seconds
Started Feb 04 04:19:49 PM PST 24
Finished Feb 04 04:19:53 PM PST 24
Peak memory 206652 kb
Host smart-255b0dcd-6fc6-4409-95a9-f52ac59a63f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933593061 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3933593061
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.122827605
Short name T635
Test name
Test status
Simulation time 17932780 ps
CPU time 0.99 seconds
Started Feb 04 04:19:43 PM PST 24
Finished Feb 04 04:19:46 PM PST 24
Peak memory 205316 kb
Host smart-8ef46ca8-023e-4052-b98d-2dbcf8e1579a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122827605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.122827605
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.422628322
Short name T172
Test name
Test status
Simulation time 21454877 ps
CPU time 0.89 seconds
Started Feb 04 04:19:49 PM PST 24
Finished Feb 04 04:19:53 PM PST 24
Peak memory 215052 kb
Host smart-89ed56a0-0cf0-4c71-afac-5eebabe84d09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422628322 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.422628322
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3854964223
Short name T153
Test name
Test status
Simulation time 53866638 ps
CPU time 1.08 seconds
Started Feb 04 04:19:47 PM PST 24
Finished Feb 04 04:19:53 PM PST 24
Peak memory 215316 kb
Host smart-93e81705-8c9c-44ad-8691-75bc3d3586c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854964223 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3854964223
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1916520680
Short name T15
Test name
Test status
Simulation time 18918830 ps
CPU time 1.19 seconds
Started Feb 04 04:19:46 PM PST 24
Finished Feb 04 04:19:53 PM PST 24
Peak memory 222660 kb
Host smart-20b412fe-4ab5-4d02-bd8f-62a435003ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916520680 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1916520680
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2415107188
Short name T657
Test name
Test status
Simulation time 69848118 ps
CPU time 1.16 seconds
Started Feb 04 04:19:41 PM PST 24
Finished Feb 04 04:19:45 PM PST 24
Peak memory 215008 kb
Host smart-7946f4a2-3f3e-4349-9965-625a1f309154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415107188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2415107188
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1086593988
Short name T23
Test name
Test status
Simulation time 19871852 ps
CPU time 1 seconds
Started Feb 04 04:19:41 PM PST 24
Finished Feb 04 04:19:45 PM PST 24
Peak memory 215320 kb
Host smart-205bf660-b8dd-4d5f-8244-1d86180df374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086593988 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1086593988
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_smoke.4011357485
Short name T731
Test name
Test status
Simulation time 97368339 ps
CPU time 1.05 seconds
Started Feb 04 04:19:40 PM PST 24
Finished Feb 04 04:19:45 PM PST 24
Peak memory 214928 kb
Host smart-b709597e-4583-423a-a7e4-92c405ae25f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011357485 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.4011357485
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3905634767
Short name T882
Test name
Test status
Simulation time 96299372 ps
CPU time 1.69 seconds
Started Feb 04 04:19:41 PM PST 24
Finished Feb 04 04:19:46 PM PST 24
Peak memory 214928 kb
Host smart-a2897377-a6e8-4ec4-b0bb-83f5e4ad9e95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905634767 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3905634767
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.2224143220
Short name T721
Test name
Test status
Simulation time 260978295559 ps
CPU time 1703.04 seconds
Started Feb 04 04:19:42 PM PST 24
Finished Feb 04 04:48:08 PM PST 24
Peak memory 222304 kb
Host smart-019ddd60-f424-4e8a-a93c-d8b5421db7c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224143220 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.2224143220
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.383565434
Short name T158
Test name
Test status
Simulation time 30125817 ps
CPU time 1.02 seconds
Started Feb 04 04:23:08 PM PST 24
Finished Feb 04 04:23:11 PM PST 24
Peak memory 222544 kb
Host smart-901800ec-337b-4392-9613-aea5088190e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383565434 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.383565434
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1661617388
Short name T471
Test name
Test status
Simulation time 26524412 ps
CPU time 1.12 seconds
Started Feb 04 04:23:11 PM PST 24
Finished Feb 04 04:23:13 PM PST 24
Peak memory 216732 kb
Host smart-b4f55c71-8994-4a01-b5ec-1ce60e502a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661617388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1661617388
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.3037255425
Short name T126
Test name
Test status
Simulation time 44581372 ps
CPU time 1.3 seconds
Started Feb 04 04:23:13 PM PST 24
Finished Feb 04 04:23:16 PM PST 24
Peak memory 222756 kb
Host smart-44f958bb-40c8-4a5f-8c0e-aad54e8917bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037255425 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3037255425
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1755632904
Short name T272
Test name
Test status
Simulation time 34155567 ps
CPU time 1.05 seconds
Started Feb 04 04:23:12 PM PST 24
Finished Feb 04 04:23:14 PM PST 24
Peak memory 215452 kb
Host smart-dc16cf47-ada2-46f9-90cc-24dd5080f0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755632904 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1755632904
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.3591570812
Short name T787
Test name
Test status
Simulation time 23284355 ps
CPU time 1.22 seconds
Started Feb 04 04:23:11 PM PST 24
Finished Feb 04 04:23:14 PM PST 24
Peak memory 216748 kb
Host smart-82b0d063-39f5-44ba-8ebe-f6283a3e2c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591570812 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3591570812
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2988631517
Short name T840
Test name
Test status
Simulation time 1129047706 ps
CPU time 8.62 seconds
Started Feb 04 04:23:14 PM PST 24
Finished Feb 04 04:23:23 PM PST 24
Peak memory 215468 kb
Host smart-60cf4de6-0888-44ab-9d2c-88e842f623f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988631517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2988631517
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.3712154318
Short name T148
Test name
Test status
Simulation time 19191439 ps
CPU time 1.08 seconds
Started Feb 04 04:23:12 PM PST 24
Finished Feb 04 04:23:14 PM PST 24
Peak memory 216752 kb
Host smart-edc5d2aa-b1a2-4c15-b569-48eb7d42ffec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712154318 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.3712154318
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2788629949
Short name T521
Test name
Test status
Simulation time 69897075 ps
CPU time 1.81 seconds
Started Feb 04 04:23:09 PM PST 24
Finished Feb 04 04:23:12 PM PST 24
Peak memory 215472 kb
Host smart-bc80ff4a-29d2-489c-bf74-619775588924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788629949 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2788629949
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.3614437949
Short name T122
Test name
Test status
Simulation time 34706267 ps
CPU time 0.9 seconds
Started Feb 04 04:23:12 PM PST 24
Finished Feb 04 04:23:14 PM PST 24
Peak memory 216556 kb
Host smart-040049a6-f802-498f-aa3a-8773ce543b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614437949 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3614437949
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.4257544919
Short name T599
Test name
Test status
Simulation time 28918168 ps
CPU time 1.14 seconds
Started Feb 04 04:23:08 PM PST 24
Finished Feb 04 04:23:11 PM PST 24
Peak memory 216780 kb
Host smart-3969258c-8a8c-4fb6-99e5-b98f46056bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257544919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.4257544919
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.1370735590
Short name T24
Test name
Test status
Simulation time 26338559 ps
CPU time 0.88 seconds
Started Feb 04 04:23:11 PM PST 24
Finished Feb 04 04:23:13 PM PST 24
Peak memory 216272 kb
Host smart-b1eb0c3b-77d8-4c6c-87e8-d6141d8b4d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370735590 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1370735590
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2607467806
Short name T614
Test name
Test status
Simulation time 51132323 ps
CPU time 1.02 seconds
Started Feb 04 04:23:11 PM PST 24
Finished Feb 04 04:23:13 PM PST 24
Peak memory 215248 kb
Host smart-3b5ef296-4769-4f7e-b4ce-5efd9f57a1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607467806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2607467806
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3503840550
Short name T447
Test name
Test status
Simulation time 51174351 ps
CPU time 1.08 seconds
Started Feb 04 04:23:10 PM PST 24
Finished Feb 04 04:23:12 PM PST 24
Peak memory 217932 kb
Host smart-6414c23f-0954-4082-a589-e11a77afc791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503840550 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3503840550
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.408489765
Short name T315
Test name
Test status
Simulation time 127666668 ps
CPU time 3.06 seconds
Started Feb 04 04:23:10 PM PST 24
Finished Feb 04 04:23:14 PM PST 24
Peak memory 217780 kb
Host smart-05b47289-6498-4668-8154-b6621b914aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408489765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.408489765
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.2715826284
Short name T128
Test name
Test status
Simulation time 58005507 ps
CPU time 1.6 seconds
Started Feb 04 04:23:13 PM PST 24
Finished Feb 04 04:23:16 PM PST 24
Peak memory 231104 kb
Host smart-9de98049-181d-4be9-96bd-f8adb2c050ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715826284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2715826284
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3006406594
Short name T531
Test name
Test status
Simulation time 16860174 ps
CPU time 1.09 seconds
Started Feb 04 04:23:09 PM PST 24
Finished Feb 04 04:23:12 PM PST 24
Peak memory 216856 kb
Host smart-e8860ac9-5b66-40ad-8b4f-f97c56d02c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006406594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3006406594
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.4013893485
Short name T154
Test name
Test status
Simulation time 19356092 ps
CPU time 1.27 seconds
Started Feb 04 04:23:13 PM PST 24
Finished Feb 04 04:23:16 PM PST 24
Peak memory 222652 kb
Host smart-9e19cf46-88af-4d88-999d-2546465fe580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013893485 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.4013893485
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.1721945149
Short name T9
Test name
Test status
Simulation time 32172456 ps
CPU time 1.04 seconds
Started Feb 04 04:23:13 PM PST 24
Finished Feb 04 04:23:15 PM PST 24
Peak memory 215616 kb
Host smart-236f89a5-49d2-4399-b866-40aa249e6648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721945149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.1721945149
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.2275460123
Short name T53
Test name
Test status
Simulation time 19932619 ps
CPU time 1.11 seconds
Started Feb 04 04:23:09 PM PST 24
Finished Feb 04 04:23:11 PM PST 24
Peak memory 222664 kb
Host smart-8d268084-94ea-48f4-b007-5611d0b32330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275460123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.2275460123
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2375438167
Short name T280
Test name
Test status
Simulation time 15558771 ps
CPU time 1.09 seconds
Started Feb 04 04:23:11 PM PST 24
Finished Feb 04 04:23:13 PM PST 24
Peak memory 215040 kb
Host smart-a0706793-a11e-4b17-8fc9-c97fc8409f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375438167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2375438167
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%