Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.80 98.27 93.63 96.79 81.50 96.87 96.58 92.95


Total test records in report: 968
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T794 /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2858538314 Feb 18 03:16:17 PM PST 24 Feb 18 03:48:37 PM PST 24 311667008852 ps
T795 /workspace/coverage/default/14.edn_stress_all.1255713268 Feb 18 03:15:07 PM PST 24 Feb 18 03:15:18 PM PST 24 403970946 ps
T796 /workspace/coverage/default/27.edn_disable_auto_req_mode.3587998817 Feb 18 03:15:48 PM PST 24 Feb 18 03:15:57 PM PST 24 30536850 ps
T797 /workspace/coverage/default/166.edn_genbits.1515244316 Feb 18 03:17:27 PM PST 24 Feb 18 03:17:35 PM PST 24 66321189 ps
T798 /workspace/coverage/default/196.edn_genbits.2690568201 Feb 18 03:17:24 PM PST 24 Feb 18 03:17:33 PM PST 24 56132357 ps
T799 /workspace/coverage/default/32.edn_smoke.2028799496 Feb 18 03:16:03 PM PST 24 Feb 18 03:16:12 PM PST 24 18294012 ps
T800 /workspace/coverage/default/102.edn_genbits.1432936333 Feb 18 03:17:13 PM PST 24 Feb 18 03:17:17 PM PST 24 67685921 ps
T801 /workspace/coverage/default/31.edn_genbits.1114339227 Feb 18 03:15:50 PM PST 24 Feb 18 03:15:58 PM PST 24 43716593 ps
T802 /workspace/coverage/default/89.edn_genbits.1581471955 Feb 18 03:16:59 PM PST 24 Feb 18 03:17:05 PM PST 24 50943516 ps
T803 /workspace/coverage/default/179.edn_genbits.323036599 Feb 18 03:17:34 PM PST 24 Feb 18 03:17:42 PM PST 24 35018051 ps
T43 /workspace/coverage/default/4.edn_sec_cm.3334805773 Feb 18 03:14:17 PM PST 24 Feb 18 03:14:31 PM PST 24 319370775 ps
T804 /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3449841760 Feb 18 03:16:24 PM PST 24 Feb 18 03:28:12 PM PST 24 101455075099 ps
T805 /workspace/coverage/default/144.edn_genbits.3442312650 Feb 18 03:17:18 PM PST 24 Feb 18 03:17:25 PM PST 24 60077612 ps
T806 /workspace/coverage/default/13.edn_alert_test.2641750021 Feb 18 03:15:07 PM PST 24 Feb 18 03:15:17 PM PST 24 31918024 ps
T807 /workspace/coverage/default/183.edn_genbits.2055076100 Feb 18 03:17:33 PM PST 24 Feb 18 03:17:43 PM PST 24 75085396 ps
T808 /workspace/coverage/default/168.edn_genbits.1788982125 Feb 18 03:17:19 PM PST 24 Feb 18 03:17:27 PM PST 24 75380492 ps
T809 /workspace/coverage/default/38.edn_intr.1168956835 Feb 18 03:16:16 PM PST 24 Feb 18 03:16:25 PM PST 24 21213190 ps
T810 /workspace/coverage/default/52.edn_err.3710878868 Feb 18 03:16:40 PM PST 24 Feb 18 03:16:46 PM PST 24 51238295 ps
T811 /workspace/coverage/default/86.edn_genbits.2977745806 Feb 18 03:17:01 PM PST 24 Feb 18 03:17:05 PM PST 24 85558353 ps
T812 /workspace/coverage/default/259.edn_genbits.2006348233 Feb 18 03:17:40 PM PST 24 Feb 18 03:17:48 PM PST 24 186855221 ps
T813 /workspace/coverage/default/222.edn_genbits.567636297 Feb 18 03:17:25 PM PST 24 Feb 18 03:17:34 PM PST 24 40881740 ps
T814 /workspace/coverage/default/36.edn_disable.2247213442 Feb 18 03:16:05 PM PST 24 Feb 18 03:16:16 PM PST 24 61821782 ps
T815 /workspace/coverage/default/14.edn_genbits.2323095485 Feb 18 03:15:05 PM PST 24 Feb 18 03:15:14 PM PST 24 54054634 ps
T157 /workspace/coverage/default/24.edn_disable.2534512929 Feb 18 03:15:34 PM PST 24 Feb 18 03:15:44 PM PST 24 93474319 ps
T816 /workspace/coverage/default/19.edn_genbits.2815762892 Feb 18 03:15:16 PM PST 24 Feb 18 03:15:29 PM PST 24 57653037 ps
T817 /workspace/coverage/default/15.edn_genbits.1890998729 Feb 18 03:15:10 PM PST 24 Feb 18 03:15:24 PM PST 24 119267054 ps
T818 /workspace/coverage/default/244.edn_genbits.3340889813 Feb 18 03:17:41 PM PST 24 Feb 18 03:17:49 PM PST 24 146870799 ps
T202 /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1466704378 Feb 18 03:16:30 PM PST 24 Feb 18 03:28:24 PM PST 24 134308315067 ps
T819 /workspace/coverage/default/32.edn_alert_test.4100324973 Feb 18 03:15:54 PM PST 24 Feb 18 03:16:01 PM PST 24 49507057 ps
T820 /workspace/coverage/default/276.edn_genbits.437367559 Feb 18 03:17:51 PM PST 24 Feb 18 03:17:58 PM PST 24 311793826 ps
T821 /workspace/coverage/default/31.edn_stress_all.3827210861 Feb 18 03:15:50 PM PST 24 Feb 18 03:15:58 PM PST 24 99327825 ps
T158 /workspace/coverage/default/33.edn_disable.2194980726 Feb 18 03:16:05 PM PST 24 Feb 18 03:16:16 PM PST 24 11053148 ps
T822 /workspace/coverage/default/23.edn_alert.3322322550 Feb 18 03:15:28 PM PST 24 Feb 18 03:15:39 PM PST 24 29336535 ps
T203 /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3420789190 Feb 18 03:14:18 PM PST 24 Feb 18 03:42:41 PM PST 24 956241419313 ps
T823 /workspace/coverage/default/221.edn_genbits.930691000 Feb 18 03:17:42 PM PST 24 Feb 18 03:17:49 PM PST 24 31569209 ps
T824 /workspace/coverage/default/255.edn_genbits.2669256989 Feb 18 03:17:34 PM PST 24 Feb 18 03:17:43 PM PST 24 45866703 ps
T825 /workspace/coverage/default/230.edn_genbits.2697521786 Feb 18 03:17:34 PM PST 24 Feb 18 03:17:43 PM PST 24 42432057 ps
T826 /workspace/coverage/default/51.edn_genbits.1653309434 Feb 18 03:16:45 PM PST 24 Feb 18 03:16:50 PM PST 24 121576130 ps
T827 /workspace/coverage/default/22.edn_alert.4064020271 Feb 18 03:15:25 PM PST 24 Feb 18 03:15:36 PM PST 24 70092699 ps
T828 /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3983480343 Feb 18 03:16:05 PM PST 24 Feb 18 03:30:24 PM PST 24 68668106804 ps
T204 /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3272292697 Feb 18 03:15:40 PM PST 24 Feb 18 03:31:55 PM PST 24 87897346440 ps
T829 /workspace/coverage/default/21.edn_intr.2545582644 Feb 18 03:15:24 PM PST 24 Feb 18 03:15:36 PM PST 24 22436195 ps
T282 /workspace/coverage/default/118.edn_genbits.3087943554 Feb 18 03:17:11 PM PST 24 Feb 18 03:17:14 PM PST 24 93359205 ps
T830 /workspace/coverage/default/31.edn_smoke.304723273 Feb 18 03:15:52 PM PST 24 Feb 18 03:16:00 PM PST 24 22030057 ps
T81 /workspace/coverage/default/17.edn_disable_auto_req_mode.3306734974 Feb 18 03:15:09 PM PST 24 Feb 18 03:15:22 PM PST 24 36823317 ps
T831 /workspace/coverage/default/40.edn_alert_test.2884058039 Feb 18 03:16:14 PM PST 24 Feb 18 03:16:23 PM PST 24 108577508 ps
T832 /workspace/coverage/default/7.edn_err.3315819792 Feb 18 03:14:31 PM PST 24 Feb 18 03:14:44 PM PST 24 48503991 ps
T833 /workspace/coverage/default/140.edn_genbits.2212262985 Feb 18 03:17:21 PM PST 24 Feb 18 03:17:33 PM PST 24 399480365 ps
T834 /workspace/coverage/default/291.edn_genbits.2649408173 Feb 18 03:17:52 PM PST 24 Feb 18 03:17:57 PM PST 24 71822764 ps
T835 /workspace/coverage/default/30.edn_err.1189139081 Feb 18 03:15:51 PM PST 24 Feb 18 03:16:00 PM PST 24 29740619 ps
T836 /workspace/coverage/default/19.edn_alert.4056397609 Feb 18 03:15:24 PM PST 24 Feb 18 03:15:36 PM PST 24 23754654 ps
T837 /workspace/coverage/default/17.edn_genbits.1512359958 Feb 18 03:15:08 PM PST 24 Feb 18 03:15:19 PM PST 24 265378253 ps
T838 /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2788987615 Feb 18 03:16:03 PM PST 24 Feb 18 03:46:16 PM PST 24 450483378358 ps
T839 /workspace/coverage/cover_reg_top/46.edn_intr_test.4267183202 Feb 18 12:34:01 PM PST 24 Feb 18 12:34:04 PM PST 24 42631041 ps
T226 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1697544411 Feb 18 12:33:36 PM PST 24 Feb 18 12:33:39 PM PST 24 46628158 ps
T218 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1471715688 Feb 18 12:33:55 PM PST 24 Feb 18 12:33:59 PM PST 24 23685541 ps
T227 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1270619543 Feb 18 12:33:30 PM PST 24 Feb 18 12:33:40 PM PST 24 223727826 ps
T250 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1100250573 Feb 18 12:33:31 PM PST 24 Feb 18 12:33:37 PM PST 24 90071733 ps
T251 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3388447736 Feb 18 12:33:30 PM PST 24 Feb 18 12:33:36 PM PST 24 65205896 ps
T248 /workspace/coverage/cover_reg_top/16.edn_csr_rw.159721058 Feb 18 12:33:52 PM PST 24 Feb 18 12:33:56 PM PST 24 46019682 ps
T840 /workspace/coverage/cover_reg_top/16.edn_tl_errors.1340393926 Feb 18 12:33:52 PM PST 24 Feb 18 12:33:57 PM PST 24 32747580 ps
T841 /workspace/coverage/cover_reg_top/19.edn_intr_test.3095169648 Feb 18 12:33:53 PM PST 24 Feb 18 12:33:56 PM PST 24 31699945 ps
T842 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2820930811 Feb 18 12:33:50 PM PST 24 Feb 18 12:33:57 PM PST 24 197788937 ps
T228 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3599129850 Feb 18 12:33:27 PM PST 24 Feb 18 12:33:32 PM PST 24 20522184 ps
T843 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.249446689 Feb 18 12:33:38 PM PST 24 Feb 18 12:33:41 PM PST 24 35927355 ps
T844 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1821500222 Feb 18 12:34:00 PM PST 24 Feb 18 12:34:03 PM PST 24 74516244 ps
T249 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3352955962 Feb 18 12:33:36 PM PST 24 Feb 18 12:33:39 PM PST 24 18205796 ps
T845 /workspace/coverage/cover_reg_top/12.edn_intr_test.3087288904 Feb 18 12:33:39 PM PST 24 Feb 18 12:33:41 PM PST 24 12441950 ps
T205 /workspace/coverage/cover_reg_top/14.edn_tl_errors.1545211862 Feb 18 12:33:46 PM PST 24 Feb 18 12:33:52 PM PST 24 81725124 ps
T213 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.34854824 Feb 18 12:33:32 PM PST 24 Feb 18 12:33:36 PM PST 24 151702065 ps
T846 /workspace/coverage/cover_reg_top/41.edn_intr_test.237494223 Feb 18 12:34:10 PM PST 24 Feb 18 12:34:13 PM PST 24 53407844 ps
T847 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2841877577 Feb 18 12:33:32 PM PST 24 Feb 18 12:33:38 PM PST 24 32508752 ps
T848 /workspace/coverage/cover_reg_top/4.edn_intr_test.3289435904 Feb 18 12:33:32 PM PST 24 Feb 18 12:33:36 PM PST 24 22901980 ps
T242 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.511324708 Feb 18 12:33:32 PM PST 24 Feb 18 12:33:36 PM PST 24 35745157 ps
T252 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3105765929 Feb 18 12:33:48 PM PST 24 Feb 18 12:33:53 PM PST 24 176457333 ps
T849 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2459060369 Feb 18 12:33:35 PM PST 24 Feb 18 12:33:41 PM PST 24 98695096 ps
T243 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1939745559 Feb 18 12:33:51 PM PST 24 Feb 18 12:33:55 PM PST 24 57984707 ps
T244 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1283087860 Feb 18 12:33:45 PM PST 24 Feb 18 12:33:49 PM PST 24 13107873 ps
T850 /workspace/coverage/cover_reg_top/7.edn_intr_test.412424187 Feb 18 12:33:38 PM PST 24 Feb 18 12:33:41 PM PST 24 24543119 ps
T245 /workspace/coverage/cover_reg_top/1.edn_csr_rw.1418852470 Feb 18 12:33:28 PM PST 24 Feb 18 12:33:33 PM PST 24 33233220 ps
T851 /workspace/coverage/cover_reg_top/28.edn_intr_test.3444367620 Feb 18 12:33:59 PM PST 24 Feb 18 12:34:02 PM PST 24 15646556 ps
T246 /workspace/coverage/cover_reg_top/4.edn_csr_rw.3847181260 Feb 18 12:33:34 PM PST 24 Feb 18 12:33:37 PM PST 24 28991764 ps
T852 /workspace/coverage/cover_reg_top/22.edn_intr_test.889744266 Feb 18 12:33:50 PM PST 24 Feb 18 12:33:52 PM PST 24 44509536 ps
T853 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.848930113 Feb 18 12:33:46 PM PST 24 Feb 18 12:33:51 PM PST 24 103964946 ps
T854 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1579783273 Feb 18 12:33:34 PM PST 24 Feb 18 12:33:40 PM PST 24 209382275 ps
T855 /workspace/coverage/cover_reg_top/0.edn_intr_test.1201579063 Feb 18 12:33:27 PM PST 24 Feb 18 12:33:31 PM PST 24 15518521 ps
T856 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.4115184351 Feb 18 12:33:35 PM PST 24 Feb 18 12:33:40 PM PST 24 22455990 ps
T857 /workspace/coverage/cover_reg_top/11.edn_intr_test.2234862293 Feb 18 12:33:42 PM PST 24 Feb 18 12:33:45 PM PST 24 36995694 ps
T858 /workspace/coverage/cover_reg_top/10.edn_intr_test.588001796 Feb 18 12:33:39 PM PST 24 Feb 18 12:33:41 PM PST 24 19580922 ps
T859 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2987274464 Feb 18 12:33:44 PM PST 24 Feb 18 12:33:49 PM PST 24 47596135 ps
T860 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1793212329 Feb 18 12:33:29 PM PST 24 Feb 18 12:33:37 PM PST 24 215895290 ps
T247 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.901927970 Feb 18 12:33:40 PM PST 24 Feb 18 12:33:42 PM PST 24 24287130 ps
T861 /workspace/coverage/cover_reg_top/26.edn_intr_test.4050640905 Feb 18 12:33:50 PM PST 24 Feb 18 12:33:54 PM PST 24 18063906 ps
T862 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3211309174 Feb 18 12:33:43 PM PST 24 Feb 18 12:33:46 PM PST 24 78655717 ps
T229 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2753251499 Feb 18 12:33:22 PM PST 24 Feb 18 12:33:27 PM PST 24 33853263 ps
T230 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1150137685 Feb 18 12:33:23 PM PST 24 Feb 18 12:33:30 PM PST 24 410703166 ps
T863 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.747228302 Feb 18 12:33:45 PM PST 24 Feb 18 12:33:49 PM PST 24 99156133 ps
T864 /workspace/coverage/cover_reg_top/21.edn_intr_test.3426508150 Feb 18 12:33:54 PM PST 24 Feb 18 12:33:57 PM PST 24 24008874 ps
T865 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1078908410 Feb 18 12:33:27 PM PST 24 Feb 18 12:33:33 PM PST 24 43009595 ps
T866 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3192334007 Feb 18 12:33:46 PM PST 24 Feb 18 12:33:53 PM PST 24 165910646 ps
T261 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3543354547 Feb 18 12:33:34 PM PST 24 Feb 18 12:33:38 PM PST 24 63083010 ps
T867 /workspace/coverage/cover_reg_top/5.edn_intr_test.1299181112 Feb 18 12:33:36 PM PST 24 Feb 18 12:33:39 PM PST 24 39974669 ps
T258 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3717249349 Feb 18 12:33:44 PM PST 24 Feb 18 12:33:47 PM PST 24 321628423 ps
T231 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1104465729 Feb 18 12:33:53 PM PST 24 Feb 18 12:33:56 PM PST 24 28834369 ps
T259 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1003480311 Feb 18 12:33:51 PM PST 24 Feb 18 12:33:57 PM PST 24 150633183 ps
T868 /workspace/coverage/cover_reg_top/49.edn_intr_test.1645649524 Feb 18 12:34:00 PM PST 24 Feb 18 12:34:02 PM PST 24 33261210 ps
T232 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3214955533 Feb 18 12:33:49 PM PST 24 Feb 18 12:33:52 PM PST 24 39721442 ps
T233 /workspace/coverage/cover_reg_top/2.edn_csr_rw.3236670355 Feb 18 12:33:28 PM PST 24 Feb 18 12:33:33 PM PST 24 26823356 ps
T869 /workspace/coverage/cover_reg_top/44.edn_intr_test.712842173 Feb 18 12:33:58 PM PST 24 Feb 18 12:34:00 PM PST 24 37621409 ps
T870 /workspace/coverage/cover_reg_top/9.edn_intr_test.2646649661 Feb 18 12:33:47 PM PST 24 Feb 18 12:33:51 PM PST 24 16028086 ps
T871 /workspace/coverage/cover_reg_top/3.edn_intr_test.282215546 Feb 18 12:33:29 PM PST 24 Feb 18 12:33:33 PM PST 24 15195114 ps
T872 /workspace/coverage/cover_reg_top/27.edn_intr_test.2413969687 Feb 18 12:33:54 PM PST 24 Feb 18 12:33:58 PM PST 24 29308302 ps
T234 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2407964060 Feb 18 12:33:33 PM PST 24 Feb 18 12:33:37 PM PST 24 33198183 ps
T873 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2408088230 Feb 18 12:33:45 PM PST 24 Feb 18 12:33:48 PM PST 24 33666168 ps
T874 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1780533863 Feb 18 12:33:32 PM PST 24 Feb 18 12:33:37 PM PST 24 182917193 ps
T875 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2371747682 Feb 18 12:33:44 PM PST 24 Feb 18 12:33:49 PM PST 24 80539570 ps
T876 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.135885555 Feb 18 12:33:47 PM PST 24 Feb 18 12:33:52 PM PST 24 117834763 ps
T877 /workspace/coverage/cover_reg_top/0.edn_tl_errors.836835961 Feb 18 12:33:30 PM PST 24 Feb 18 12:33:39 PM PST 24 2317007133 ps
T878 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1117461799 Feb 18 12:33:45 PM PST 24 Feb 18 12:33:49 PM PST 24 19594309 ps
T879 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3534870649 Feb 18 12:33:32 PM PST 24 Feb 18 12:33:37 PM PST 24 29877852 ps
T880 /workspace/coverage/cover_reg_top/34.edn_intr_test.4095589504 Feb 18 12:33:51 PM PST 24 Feb 18 12:33:56 PM PST 24 22083768 ps
T881 /workspace/coverage/cover_reg_top/13.edn_intr_test.3061633330 Feb 18 12:33:43 PM PST 24 Feb 18 12:33:46 PM PST 24 54024836 ps
T882 /workspace/coverage/cover_reg_top/39.edn_intr_test.4036286120 Feb 18 12:34:00 PM PST 24 Feb 18 12:34:03 PM PST 24 39549962 ps
T883 /workspace/coverage/cover_reg_top/40.edn_intr_test.2016045625 Feb 18 12:34:03 PM PST 24 Feb 18 12:34:05 PM PST 24 27423870 ps
T884 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3679711054 Feb 18 12:33:35 PM PST 24 Feb 18 12:33:39 PM PST 24 65889781 ps
T885 /workspace/coverage/cover_reg_top/24.edn_intr_test.504665584 Feb 18 12:33:53 PM PST 24 Feb 18 12:33:57 PM PST 24 26873837 ps
T886 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.231846603 Feb 18 12:33:32 PM PST 24 Feb 18 12:33:41 PM PST 24 262131039 ps
T887 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1453365605 Feb 18 12:33:34 PM PST 24 Feb 18 12:33:37 PM PST 24 23999127 ps
T888 /workspace/coverage/cover_reg_top/8.edn_tl_errors.804277078 Feb 18 12:33:37 PM PST 24 Feb 18 12:33:43 PM PST 24 256934228 ps
T889 /workspace/coverage/cover_reg_top/36.edn_intr_test.3811469450 Feb 18 12:34:02 PM PST 24 Feb 18 12:34:05 PM PST 24 42350506 ps
T890 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1843467031 Feb 18 12:33:51 PM PST 24 Feb 18 12:33:56 PM PST 24 140844902 ps
T891 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1583582118 Feb 18 12:33:50 PM PST 24 Feb 18 12:33:56 PM PST 24 67179435 ps
T892 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2319348115 Feb 18 12:33:39 PM PST 24 Feb 18 12:33:41 PM PST 24 100525087 ps
T893 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.4035908783 Feb 18 12:33:43 PM PST 24 Feb 18 12:33:47 PM PST 24 110417404 ps
T235 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3372870076 Feb 18 12:33:43 PM PST 24 Feb 18 12:33:46 PM PST 24 46493802 ps
T894 /workspace/coverage/cover_reg_top/15.edn_intr_test.3571239902 Feb 18 12:33:48 PM PST 24 Feb 18 12:33:51 PM PST 24 39752255 ps
T895 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2039971032 Feb 18 12:33:28 PM PST 24 Feb 18 12:33:33 PM PST 24 109686736 ps
T896 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2863851993 Feb 18 12:33:29 PM PST 24 Feb 18 12:33:35 PM PST 24 14850088 ps
T897 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2177943176 Feb 18 12:33:43 PM PST 24 Feb 18 12:33:46 PM PST 24 88349653 ps
T898 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2287866486 Feb 18 12:33:34 PM PST 24 Feb 18 12:33:37 PM PST 24 31733719 ps
T899 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3292038330 Feb 18 12:33:53 PM PST 24 Feb 18 12:33:57 PM PST 24 48763771 ps
T900 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1872441680 Feb 18 12:33:25 PM PST 24 Feb 18 12:33:30 PM PST 24 65221588 ps
T901 /workspace/coverage/cover_reg_top/38.edn_intr_test.1950154434 Feb 18 12:33:59 PM PST 24 Feb 18 12:34:02 PM PST 24 12572114 ps
T902 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2239341613 Feb 18 12:33:22 PM PST 24 Feb 18 12:33:27 PM PST 24 42264155 ps
T903 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2936831824 Feb 18 12:33:31 PM PST 24 Feb 18 12:33:36 PM PST 24 21985893 ps
T904 /workspace/coverage/cover_reg_top/0.edn_csr_rw.1253954171 Feb 18 12:33:29 PM PST 24 Feb 18 12:33:34 PM PST 24 24222094 ps
T905 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2140516488 Feb 18 12:33:28 PM PST 24 Feb 18 12:33:34 PM PST 24 131964772 ps
T906 /workspace/coverage/cover_reg_top/1.edn_tl_errors.2763268917 Feb 18 12:33:25 PM PST 24 Feb 18 12:33:31 PM PST 24 263310397 ps
T907 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.313508416 Feb 18 12:33:23 PM PST 24 Feb 18 12:33:28 PM PST 24 35182725 ps
T908 /workspace/coverage/cover_reg_top/2.edn_intr_test.1882951757 Feb 18 12:33:27 PM PST 24 Feb 18 12:33:32 PM PST 24 26695553 ps
T909 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1103159956 Feb 18 12:33:54 PM PST 24 Feb 18 12:33:59 PM PST 24 118039889 ps
T910 /workspace/coverage/cover_reg_top/43.edn_intr_test.3540593338 Feb 18 12:33:55 PM PST 24 Feb 18 12:33:59 PM PST 24 19576800 ps
T911 /workspace/coverage/cover_reg_top/19.edn_csr_rw.1663926449 Feb 18 12:33:52 PM PST 24 Feb 18 12:33:56 PM PST 24 26122779 ps
T912 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1361627144 Feb 18 12:33:40 PM PST 24 Feb 18 12:33:42 PM PST 24 151107143 ps
T262 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2961007072 Feb 18 12:33:38 PM PST 24 Feb 18 12:33:42 PM PST 24 150036322 ps
T913 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1252298961 Feb 18 12:33:29 PM PST 24 Feb 18 12:33:37 PM PST 24 529944898 ps
T914 /workspace/coverage/cover_reg_top/7.edn_tl_errors.774927423 Feb 18 12:33:38 PM PST 24 Feb 18 12:33:42 PM PST 24 69032157 ps
T915 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2740938037 Feb 18 12:33:46 PM PST 24 Feb 18 12:33:50 PM PST 24 15029531 ps
T916 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.920041682 Feb 18 12:33:41 PM PST 24 Feb 18 12:33:45 PM PST 24 411200864 ps
T240 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2955642140 Feb 18 12:33:28 PM PST 24 Feb 18 12:33:35 PM PST 24 307971726 ps
T917 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3503632230 Feb 18 12:33:50 PM PST 24 Feb 18 12:33:55 PM PST 24 49728339 ps
T918 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1273091146 Feb 18 12:33:43 PM PST 24 Feb 18 12:33:47 PM PST 24 463005715 ps
T236 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.333380124 Feb 18 12:33:32 PM PST 24 Feb 18 12:33:36 PM PST 24 66256460 ps
T919 /workspace/coverage/cover_reg_top/20.edn_intr_test.1869628366 Feb 18 12:33:50 PM PST 24 Feb 18 12:33:55 PM PST 24 76761969 ps
T237 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1203532916 Feb 18 12:33:41 PM PST 24 Feb 18 12:33:42 PM PST 24 53187350 ps
T920 /workspace/coverage/cover_reg_top/37.edn_intr_test.2898911894 Feb 18 12:33:57 PM PST 24 Feb 18 12:34:00 PM PST 24 22390479 ps
T921 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.924670694 Feb 18 12:33:30 PM PST 24 Feb 18 12:33:36 PM PST 24 40696910 ps
T922 /workspace/coverage/cover_reg_top/15.edn_tl_errors.3322442138 Feb 18 12:33:56 PM PST 24 Feb 18 12:34:01 PM PST 24 57331020 ps
T923 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2197767986 Feb 18 12:33:38 PM PST 24 Feb 18 12:33:44 PM PST 24 503445830 ps
T238 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4201189543 Feb 18 12:33:25 PM PST 24 Feb 18 12:33:31 PM PST 24 41590575 ps
T924 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.236319493 Feb 18 12:33:32 PM PST 24 Feb 18 12:33:39 PM PST 24 108166097 ps
T925 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1852539265 Feb 18 12:33:25 PM PST 24 Feb 18 12:33:33 PM PST 24 922347574 ps
T926 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3043324377 Feb 18 12:33:50 PM PST 24 Feb 18 12:33:55 PM PST 24 27154680 ps
T927 /workspace/coverage/cover_reg_top/31.edn_intr_test.2531702626 Feb 18 12:33:51 PM PST 24 Feb 18 12:33:56 PM PST 24 13990312 ps
T928 /workspace/coverage/cover_reg_top/16.edn_intr_test.3043305175 Feb 18 12:33:59 PM PST 24 Feb 18 12:34:02 PM PST 24 24293015 ps
T929 /workspace/coverage/cover_reg_top/13.edn_csr_rw.2887665949 Feb 18 12:33:45 PM PST 24 Feb 18 12:33:48 PM PST 24 126942898 ps
T930 /workspace/coverage/cover_reg_top/13.edn_tl_errors.2114262830 Feb 18 12:33:44 PM PST 24 Feb 18 12:33:48 PM PST 24 104482787 ps
T931 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1623699102 Feb 18 12:33:48 PM PST 24 Feb 18 12:33:51 PM PST 24 51299760 ps
T239 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1147719732 Feb 18 12:33:28 PM PST 24 Feb 18 12:33:33 PM PST 24 29334292 ps
T932 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3004187141 Feb 18 12:33:45 PM PST 24 Feb 18 12:33:50 PM PST 24 168219253 ps
T933 /workspace/coverage/cover_reg_top/5.edn_tl_errors.3646417641 Feb 18 12:33:32 PM PST 24 Feb 18 12:33:39 PM PST 24 198613300 ps
T934 /workspace/coverage/cover_reg_top/11.edn_tl_errors.2196058976 Feb 18 12:33:46 PM PST 24 Feb 18 12:33:52 PM PST 24 55382718 ps
T935 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1327943922 Feb 18 12:33:40 PM PST 24 Feb 18 12:33:43 PM PST 24 33686633 ps
T936 /workspace/coverage/cover_reg_top/35.edn_intr_test.1718570771 Feb 18 12:34:00 PM PST 24 Feb 18 12:34:02 PM PST 24 20689935 ps
T937 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.466527508 Feb 18 12:33:26 PM PST 24 Feb 18 12:33:31 PM PST 24 78927785 ps
T241 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.559515401 Feb 18 12:33:25 PM PST 24 Feb 18 12:33:30 PM PST 24 23294922 ps
T260 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3758705494 Feb 18 12:33:30 PM PST 24 Feb 18 12:33:37 PM PST 24 306907588 ps
T938 /workspace/coverage/cover_reg_top/17.edn_tl_errors.276494965 Feb 18 12:33:50 PM PST 24 Feb 18 12:33:55 PM PST 24 45042015 ps
T939 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.964367936 Feb 18 12:33:50 PM PST 24 Feb 18 12:33:55 PM PST 24 73335785 ps
T940 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1292803995 Feb 18 12:33:50 PM PST 24 Feb 18 12:33:54 PM PST 24 249133019 ps
T941 /workspace/coverage/cover_reg_top/2.edn_tl_errors.3051123953 Feb 18 12:33:25 PM PST 24 Feb 18 12:33:31 PM PST 24 206351245 ps
T942 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.4150127504 Feb 18 12:33:34 PM PST 24 Feb 18 12:33:38 PM PST 24 23436497 ps
T943 /workspace/coverage/cover_reg_top/11.edn_csr_rw.895900225 Feb 18 12:33:43 PM PST 24 Feb 18 12:33:45 PM PST 24 15469859 ps
T944 /workspace/coverage/cover_reg_top/45.edn_intr_test.3961058852 Feb 18 12:33:59 PM PST 24 Feb 18 12:34:02 PM PST 24 10866255 ps
T945 /workspace/coverage/cover_reg_top/25.edn_intr_test.921170855 Feb 18 12:33:53 PM PST 24 Feb 18 12:33:57 PM PST 24 23315283 ps
T946 /workspace/coverage/cover_reg_top/23.edn_intr_test.2428500252 Feb 18 12:33:52 PM PST 24 Feb 18 12:33:56 PM PST 24 15187893 ps
T947 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1053739885 Feb 18 12:33:29 PM PST 24 Feb 18 12:33:34 PM PST 24 32757388 ps
T948 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.634730969 Feb 18 12:33:50 PM PST 24 Feb 18 12:33:53 PM PST 24 29015192 ps
T949 /workspace/coverage/cover_reg_top/29.edn_intr_test.1015635801 Feb 18 12:33:51 PM PST 24 Feb 18 12:33:56 PM PST 24 69180232 ps
T950 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1342544369 Feb 18 12:33:30 PM PST 24 Feb 18 12:33:37 PM PST 24 263933942 ps
T951 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.877332640 Feb 18 12:33:33 PM PST 24 Feb 18 12:33:37 PM PST 24 18748846 ps
T952 /workspace/coverage/cover_reg_top/14.edn_intr_test.3263824568 Feb 18 12:33:41 PM PST 24 Feb 18 12:33:43 PM PST 24 82129232 ps
T953 /workspace/coverage/cover_reg_top/17.edn_intr_test.544762653 Feb 18 12:33:50 PM PST 24 Feb 18 12:33:53 PM PST 24 12599938 ps
T954 /workspace/coverage/cover_reg_top/8.edn_intr_test.2200815754 Feb 18 12:33:32 PM PST 24 Feb 18 12:33:36 PM PST 24 17382721 ps
T955 /workspace/coverage/cover_reg_top/33.edn_intr_test.772815017 Feb 18 12:33:50 PM PST 24 Feb 18 12:33:54 PM PST 24 25062202 ps
T956 /workspace/coverage/cover_reg_top/48.edn_intr_test.2209486203 Feb 18 12:34:00 PM PST 24 Feb 18 12:34:02 PM PST 24 14418179 ps
T957 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3064789918 Feb 18 12:33:34 PM PST 24 Feb 18 12:33:40 PM PST 24 353686867 ps
T958 /workspace/coverage/cover_reg_top/32.edn_intr_test.312927630 Feb 18 12:33:50 PM PST 24 Feb 18 12:33:55 PM PST 24 111120442 ps
T959 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1528203868 Feb 18 12:33:28 PM PST 24 Feb 18 12:33:34 PM PST 24 119512466 ps
T960 /workspace/coverage/cover_reg_top/42.edn_intr_test.604270130 Feb 18 12:33:56 PM PST 24 Feb 18 12:34:00 PM PST 24 56068614 ps
T961 /workspace/coverage/cover_reg_top/6.edn_intr_test.4181893840 Feb 18 12:33:32 PM PST 24 Feb 18 12:33:36 PM PST 24 13452620 ps
T962 /workspace/coverage/cover_reg_top/18.edn_intr_test.1596773156 Feb 18 12:33:59 PM PST 24 Feb 18 12:34:02 PM PST 24 20626000 ps
T963 /workspace/coverage/cover_reg_top/30.edn_intr_test.3509226408 Feb 18 12:33:55 PM PST 24 Feb 18 12:33:59 PM PST 24 35756833 ps
T964 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3587560204 Feb 18 12:33:50 PM PST 24 Feb 18 12:33:55 PM PST 24 53646022 ps
T965 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1964044532 Feb 18 12:33:56 PM PST 24 Feb 18 12:34:00 PM PST 24 21868889 ps
T966 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1594592166 Feb 18 12:33:49 PM PST 24 Feb 18 12:33:54 PM PST 24 53436255 ps
T967 /workspace/coverage/cover_reg_top/1.edn_intr_test.3045292496 Feb 18 12:33:31 PM PST 24 Feb 18 12:33:35 PM PST 24 138484651 ps
T968 /workspace/coverage/cover_reg_top/47.edn_intr_test.1898971024 Feb 18 12:34:06 PM PST 24 Feb 18 12:34:08 PM PST 24 18222746 ps

Test location /workspace/coverage/default/292.edn_genbits.2218861407
Short name T2
Test name
Test status
Simulation time 46704215 ps
CPU time 1.58 seconds
Started Feb 18 03:17:50 PM PST 24
Finished Feb 18 03:17:56 PM PST 24
Peak memory 217604 kb
Host smart-4c4c4ab9-cd6b-4077-97e5-89f595b9bba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218861407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2218861407
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.2524955554
Short name T5
Test name
Test status
Simulation time 51238987 ps
CPU time 1.08 seconds
Started Feb 18 03:16:55 PM PST 24
Finished Feb 18 03:17:00 PM PST 24
Peak memory 229236 kb
Host smart-23c28160-d929-4c50-8006-2e45f8392ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524955554 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2524955554
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.709714673
Short name T22
Test name
Test status
Simulation time 34729798539 ps
CPU time 442.23 seconds
Started Feb 18 03:15:24 PM PST 24
Finished Feb 18 03:22:57 PM PST 24
Peak memory 217268 kb
Host smart-c66a3729-22d7-42e6-89db-7e502579336a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709714673 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.709714673
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.edn_sec_cm.780161677
Short name T17
Test name
Test status
Simulation time 1339254428 ps
CPU time 8.09 seconds
Started Feb 18 03:14:14 PM PST 24
Finished Feb 18 03:14:32 PM PST 24
Peak memory 236116 kb
Host smart-552df2c8-23bd-4b41-98e5-c3e8c48e0414
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780161677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.780161677
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/7.edn_alert.1976812694
Short name T8
Test name
Test status
Simulation time 24095362 ps
CPU time 1.28 seconds
Started Feb 18 03:14:30 PM PST 24
Finished Feb 18 03:14:44 PM PST 24
Peak memory 215044 kb
Host smart-79c89a69-6f81-4837-9cb9-230ec739f033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976812694 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1976812694
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/205.edn_genbits.2776918855
Short name T13
Test name
Test status
Simulation time 55809407 ps
CPU time 1.28 seconds
Started Feb 18 03:17:31 PM PST 24
Finished Feb 18 03:17:39 PM PST 24
Peak memory 218480 kb
Host smart-2d89645e-621c-40c1-aa41-e7f571a65a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776918855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.2776918855
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3000558145
Short name T160
Test name
Test status
Simulation time 47726859 ps
CPU time 1.1 seconds
Started Feb 18 03:16:34 PM PST 24
Finished Feb 18 03:16:39 PM PST 24
Peak memory 216956 kb
Host smart-346b2e9e-e3d8-40bf-98b0-a3a76caaeae5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000558145 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3000558145
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_alert.2313411623
Short name T14
Test name
Test status
Simulation time 86187124 ps
CPU time 1.22 seconds
Started Feb 18 03:16:33 PM PST 24
Finished Feb 18 03:16:38 PM PST 24
Peak memory 215056 kb
Host smart-79b5a89f-097d-4271-9ba8-c4f009d5cae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313411623 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2313411623
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/18.edn_intr.2111330823
Short name T36
Test name
Test status
Simulation time 22388395 ps
CPU time 1.11 seconds
Started Feb 18 03:15:15 PM PST 24
Finished Feb 18 03:15:27 PM PST 24
Peak memory 215172 kb
Host smart-58608c4d-f2c7-4466-80e8-d29a294ba935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111330823 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2111330823
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.797712249
Short name T24
Test name
Test status
Simulation time 14266286236 ps
CPU time 339.79 seconds
Started Feb 18 03:16:34 PM PST 24
Finished Feb 18 03:22:18 PM PST 24
Peak memory 217496 kb
Host smart-8b8c8d22-8d4b-44be-874e-bd0eb9631448
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797712249 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.797712249
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_regwen.2227834260
Short name T121
Test name
Test status
Simulation time 17080637 ps
CPU time 0.99 seconds
Started Feb 18 03:14:10 PM PST 24
Finished Feb 18 03:14:22 PM PST 24
Peak memory 206508 kb
Host smart-c9b8e8ca-1768-4664-add2-e8e87ca99f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227834260 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2227834260
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/23.edn_disable.1712986537
Short name T21
Test name
Test status
Simulation time 36136225 ps
CPU time 0.84 seconds
Started Feb 18 03:15:24 PM PST 24
Finished Feb 18 03:15:35 PM PST 24
Peak memory 215224 kb
Host smart-0bbe39fc-a0ea-4a00-a824-381180bbf2c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712986537 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1712986537
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1003480311
Short name T259
Test name
Test status
Simulation time 150633183 ps
CPU time 2.04 seconds
Started Feb 18 12:33:51 PM PST 24
Finished Feb 18 12:33:57 PM PST 24
Peak memory 205444 kb
Host smart-e33e3310-de86-4275-9c84-2bc0f2c234ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003480311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1003480311
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3599129850
Short name T228
Test name
Test status
Simulation time 20522184 ps
CPU time 1.28 seconds
Started Feb 18 12:33:27 PM PST 24
Finished Feb 18 12:33:32 PM PST 24
Peak memory 205476 kb
Host smart-ea2c9630-eb43-4fbb-a850-617fb026ca51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599129850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3599129850
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/default/34.edn_genbits.1866274661
Short name T11
Test name
Test status
Simulation time 23774132 ps
CPU time 1.26 seconds
Started Feb 18 03:15:59 PM PST 24
Finished Feb 18 03:16:09 PM PST 24
Peak memory 218604 kb
Host smart-f4b3c4b4-1085-42e7-8664-c17a6bdf2cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866274661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1866274661
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.4056397609
Short name T836
Test name
Test status
Simulation time 23754654 ps
CPU time 1.19 seconds
Started Feb 18 03:15:24 PM PST 24
Finished Feb 18 03:15:36 PM PST 24
Peak memory 215124 kb
Host smart-87fee4ce-f41d-40d6-b190-4ed59dd3893c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056397609 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.4056397609
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3306734974
Short name T81
Test name
Test status
Simulation time 36823317 ps
CPU time 1.3 seconds
Started Feb 18 03:15:09 PM PST 24
Finished Feb 18 03:15:22 PM PST 24
Peak memory 215652 kb
Host smart-fc26b5cd-fd47-4380-8c2b-f91a5c07f9e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306734974 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3306734974
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_disable.2933454481
Short name T156
Test name
Test status
Simulation time 10922760 ps
CPU time 0.85 seconds
Started Feb 18 03:15:14 PM PST 24
Finished Feb 18 03:15:27 PM PST 24
Peak memory 215080 kb
Host smart-133d4283-8b64-4ab8-825d-9ea0621f1737
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933454481 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2933454481
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable.3495042582
Short name T186
Test name
Test status
Simulation time 13735690 ps
CPU time 0.94 seconds
Started Feb 18 03:15:59 PM PST 24
Finished Feb 18 03:16:09 PM PST 24
Peak memory 215316 kb
Host smart-a8bed66b-dc4f-4e8f-ba80-2a3e3dff375a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495042582 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.3495042582
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable.2354712351
Short name T159
Test name
Test status
Simulation time 43436022 ps
CPU time 0.9 seconds
Started Feb 18 03:15:19 PM PST 24
Finished Feb 18 03:15:30 PM PST 24
Peak memory 215092 kb
Host smart-c855b5f1-b362-423b-9de7-93af56a242df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354712351 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.2354712351
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.3587998817
Short name T796
Test name
Test status
Simulation time 30536850 ps
CPU time 1.14 seconds
Started Feb 18 03:15:48 PM PST 24
Finished Feb 18 03:15:57 PM PST 24
Peak memory 217020 kb
Host smart-79826167-8540-42d3-9f43-82ca1877551a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587998817 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.3587998817
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_intr.1444053467
Short name T123
Test name
Test status
Simulation time 29753974 ps
CPU time 0.86 seconds
Started Feb 18 03:14:30 PM PST 24
Finished Feb 18 03:14:44 PM PST 24
Peak memory 215168 kb
Host smart-2f6c9971-1dd1-4122-9945-60eb0ed875a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444053467 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1444053467
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/10.edn_alert.1414147891
Short name T300
Test name
Test status
Simulation time 63297752 ps
CPU time 1.27 seconds
Started Feb 18 03:14:44 PM PST 24
Finished Feb 18 03:14:52 PM PST 24
Peak memory 215048 kb
Host smart-c28d4a19-0cd7-484a-b909-9d6a215802da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414147891 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1414147891
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1373991386
Short name T48
Test name
Test status
Simulation time 37849638 ps
CPU time 1.32 seconds
Started Feb 18 03:14:04 PM PST 24
Finished Feb 18 03:14:16 PM PST 24
Peak memory 215680 kb
Host smart-18d9c3c0-c066-4c7f-b4b0-7dac64961627
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373991386 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1373991386
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_alert.340284952
Short name T15
Test name
Test status
Simulation time 43613877 ps
CPU time 1.19 seconds
Started Feb 18 03:14:48 PM PST 24
Finished Feb 18 03:14:57 PM PST 24
Peak memory 215048 kb
Host smart-4d74b8d5-61cb-41b1-bcd4-4e3562b385f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340284952 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.340284952
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/3.edn_err.2720078087
Short name T55
Test name
Test status
Simulation time 31424031 ps
CPU time 0.84 seconds
Started Feb 18 03:14:15 PM PST 24
Finished Feb 18 03:14:26 PM PST 24
Peak memory 216760 kb
Host smart-47bba758-02e2-4ed2-a19a-190a4b2e5842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720078087 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2720078087
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.3553924595
Short name T361
Test name
Test status
Simulation time 40454117 ps
CPU time 1 seconds
Started Feb 18 03:16:03 PM PST 24
Finished Feb 18 03:16:13 PM PST 24
Peak memory 217172 kb
Host smart-8af253fd-e378-482c-bf85-95aec148cf36
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553924595 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.3553924595
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/175.edn_genbits.3206137472
Short name T208
Test name
Test status
Simulation time 65685138 ps
CPU time 1.21 seconds
Started Feb 18 03:17:34 PM PST 24
Finished Feb 18 03:17:42 PM PST 24
Peak memory 218860 kb
Host smart-9b92bc59-f879-42ee-9cf9-0450049308f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206137472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.3206137472
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.1638186093
Short name T278
Test name
Test status
Simulation time 53899474 ps
CPU time 1.22 seconds
Started Feb 18 03:17:27 PM PST 24
Finished Feb 18 03:17:35 PM PST 24
Peak memory 216360 kb
Host smart-5f123d15-c664-45b1-a217-c9d688df5a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638186093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.1638186093
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.4096727080
Short name T139
Test name
Test status
Simulation time 369292191575 ps
CPU time 2333.43 seconds
Started Feb 18 03:15:40 PM PST 24
Finished Feb 18 03:54:41 PM PST 24
Peak memory 229444 kb
Host smart-17af1d8f-0b14-4501-bc17-802da8dc8d0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096727080 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.4096727080
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_disable.1660867768
Short name T89
Test name
Test status
Simulation time 21540686 ps
CPU time 0.86 seconds
Started Feb 18 03:14:11 PM PST 24
Finished Feb 18 03:14:22 PM PST 24
Peak memory 214836 kb
Host smart-14881f98-c2ba-4c8b-bb83-0601fc33197a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660867768 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1660867768
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.1240845248
Short name T86
Test name
Test status
Simulation time 66657920 ps
CPU time 1.15 seconds
Started Feb 18 03:15:06 PM PST 24
Finished Feb 18 03:15:16 PM PST 24
Peak memory 215712 kb
Host smart-6d14a32e-ca72-48aa-a81c-fed5e5710aa9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240845248 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.1240845248
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_disable.3386942045
Short name T109
Test name
Test status
Simulation time 109886879 ps
CPU time 0.78 seconds
Started Feb 18 03:15:10 PM PST 24
Finished Feb 18 03:15:23 PM PST 24
Peak memory 215092 kb
Host smart-c493f871-0bdc-4f53-b722-cbe9edc07451
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386942045 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3386942045
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable.691014946
Short name T173
Test name
Test status
Simulation time 25277204 ps
CPU time 0.89 seconds
Started Feb 18 03:14:14 PM PST 24
Finished Feb 18 03:14:25 PM PST 24
Peak memory 215056 kb
Host smart-1d46866a-d943-4a1a-b3fa-011e9b6845b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691014946 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.691014946
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable.2194980726
Short name T158
Test name
Test status
Simulation time 11053148 ps
CPU time 0.87 seconds
Started Feb 18 03:16:05 PM PST 24
Finished Feb 18 03:16:16 PM PST 24
Peak memory 215100 kb
Host smart-6583c915-7a30-42e9-ae2a-a72b4d70dcd4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194980726 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2194980726
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.1724377982
Short name T66
Test name
Test status
Simulation time 45754002 ps
CPU time 1.3 seconds
Started Feb 18 03:16:12 PM PST 24
Finished Feb 18 03:16:23 PM PST 24
Peak memory 215820 kb
Host smart-e2408e6d-de4e-4ee2-bbb6-c85e4794009b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724377982 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.1724377982
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_alert_test.1180035236
Short name T151
Test name
Test status
Simulation time 47080913 ps
CPU time 0.88 seconds
Started Feb 18 03:15:06 PM PST 24
Finished Feb 18 03:15:15 PM PST 24
Peak memory 205428 kb
Host smart-8b7bba2a-6d9f-4056-b6bc-e67079e967c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180035236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.1180035236
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/90.edn_genbits.1113480356
Short name T271
Test name
Test status
Simulation time 54378647 ps
CPU time 1.31 seconds
Started Feb 18 03:16:59 PM PST 24
Finished Feb 18 03:17:03 PM PST 24
Peak memory 218716 kb
Host smart-56b80675-9b91-4dcc-90b8-9848455584bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113480356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1113480356
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.2461677410
Short name T178
Test name
Test status
Simulation time 40483353 ps
CPU time 1.48 seconds
Started Feb 18 03:17:13 PM PST 24
Finished Feb 18 03:17:18 PM PST 24
Peak memory 216988 kb
Host smart-6ea8a9eb-0ad7-42b1-9b3a-73e3fa895877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461677410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.2461677410
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.1466643310
Short name T273
Test name
Test status
Simulation time 238239394 ps
CPU time 3.67 seconds
Started Feb 18 03:17:18 PM PST 24
Finished Feb 18 03:17:26 PM PST 24
Peak memory 216300 kb
Host smart-d44d9e08-6ff1-42dd-9605-1bfa9cbd1bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466643310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1466643310
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.919506816
Short name T295
Test name
Test status
Simulation time 138995063 ps
CPU time 0.94 seconds
Started Feb 18 03:14:11 PM PST 24
Finished Feb 18 03:14:23 PM PST 24
Peak memory 206532 kb
Host smart-1568ba56-2adc-4827-91a3-8eea0b2c5eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919506816 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.919506816
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_regwen.1805344722
Short name T296
Test name
Test status
Simulation time 44091367 ps
CPU time 0.93 seconds
Started Feb 18 03:14:12 PM PST 24
Finished Feb 18 03:14:23 PM PST 24
Peak memory 206536 kb
Host smart-be19a178-e069-4873-aeff-759a87203d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805344722 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1805344722
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_regwen.3153435503
Short name T297
Test name
Test status
Simulation time 30438323 ps
CPU time 0.98 seconds
Started Feb 18 03:14:23 PM PST 24
Finished Feb 18 03:14:34 PM PST 24
Peak memory 206524 kb
Host smart-ecf20117-8dbc-42d2-88b1-dc83e8984bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153435503 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3153435503
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2642087586
Short name T196
Test name
Test status
Simulation time 86459868982 ps
CPU time 452.33 seconds
Started Feb 18 03:16:12 PM PST 24
Finished Feb 18 03:23:54 PM PST 24
Peak memory 217940 kb
Host smart-2601ee5a-99d6-4e80-852b-36a18f338bfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642087586 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2642087586
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.edn_intr.2774528996
Short name T124
Test name
Test status
Simulation time 21276145 ps
CPU time 1.05 seconds
Started Feb 18 03:15:40 PM PST 24
Finished Feb 18 03:15:48 PM PST 24
Peak memory 215092 kb
Host smart-42a14312-6089-46cf-9662-7d5f3b1fdb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774528996 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2774528996
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/81.edn_genbits.442463872
Short name T209
Test name
Test status
Simulation time 198362337 ps
CPU time 3.2 seconds
Started Feb 18 03:17:04 PM PST 24
Finished Feb 18 03:17:11 PM PST 24
Peak memory 214744 kb
Host smart-cc60eb38-d04e-40de-b6f6-ee91be4fa515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442463872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.442463872
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.721878200
Short name T312
Test name
Test status
Simulation time 56611174 ps
CPU time 0.83 seconds
Started Feb 18 03:14:09 PM PST 24
Finished Feb 18 03:14:21 PM PST 24
Peak memory 214696 kb
Host smart-fb42a31f-047f-4221-9ac6-4ec9134a2c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721878200 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.721878200
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.1418852470
Short name T245
Test name
Test status
Simulation time 33233220 ps
CPU time 0.81 seconds
Started Feb 18 12:33:28 PM PST 24
Finished Feb 18 12:33:33 PM PST 24
Peak memory 205256 kb
Host smart-8df021e6-2640-47a4-84f3-f51184e9e693
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418852470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.1418852470
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3040723670
Short name T193
Test name
Test status
Simulation time 214692734164 ps
CPU time 1193.69 seconds
Started Feb 18 03:13:56 PM PST 24
Finished Feb 18 03:33:52 PM PST 24
Peak memory 220892 kb
Host smart-254b8ad0-d941-48b2-a992-a84b30cebca7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040723670 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3040723670
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/108.edn_genbits.3051957372
Short name T450
Test name
Test status
Simulation time 43344905 ps
CPU time 1.51 seconds
Started Feb 18 03:17:11 PM PST 24
Finished Feb 18 03:17:15 PM PST 24
Peak memory 217232 kb
Host smart-edab11ee-fc65-470a-a2cd-0b9bcd0871d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051957372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.3051957372
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3087943554
Short name T282
Test name
Test status
Simulation time 93359205 ps
CPU time 1.17 seconds
Started Feb 18 03:17:11 PM PST 24
Finished Feb 18 03:17:14 PM PST 24
Peak memory 217636 kb
Host smart-8ae3c787-38ab-4426-ac21-ef723e707e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087943554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3087943554
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.2829451650
Short name T102
Test name
Test status
Simulation time 49014948 ps
CPU time 1.06 seconds
Started Feb 18 03:15:06 PM PST 24
Finished Feb 18 03:15:16 PM PST 24
Peak memory 215100 kb
Host smart-0cb223d5-7156-4d9c-9a8a-c1c970f72e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829451650 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.2829451650
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/15.edn_genbits.1890998729
Short name T817
Test name
Test status
Simulation time 119267054 ps
CPU time 1.52 seconds
Started Feb 18 03:15:10 PM PST 24
Finished Feb 18 03:15:24 PM PST 24
Peak memory 217620 kb
Host smart-f4761aff-fc84-4fcb-8720-70073bb8ddbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890998729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1890998729
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1655532698
Short name T782
Test name
Test status
Simulation time 66135857440 ps
CPU time 1279.78 seconds
Started Feb 18 03:15:06 PM PST 24
Finished Feb 18 03:36:35 PM PST 24
Peak memory 222528 kb
Host smart-0d23dc62-a216-4d08-bc5e-317f5f937894
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655532698 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1655532698
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/187.edn_genbits.1529420959
Short name T257
Test name
Test status
Simulation time 58118425 ps
CPU time 1.54 seconds
Started Feb 18 03:17:31 PM PST 24
Finished Feb 18 03:17:39 PM PST 24
Peak memory 217228 kb
Host smart-ce8d9a7f-d134-4cd6-b8a3-9231640cbae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529420959 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1529420959
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2994412898
Short name T286
Test name
Test status
Simulation time 78348059640 ps
CPU time 936.14 seconds
Started Feb 18 03:15:13 PM PST 24
Finished Feb 18 03:31:02 PM PST 24
Peak memory 219260 kb
Host smart-3314424e-b788-4ef3-9d50-61c0336c8ce4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994412898 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2994412898
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.edn_regwen.1917046510
Short name T302
Test name
Test status
Simulation time 20270431 ps
CPU time 0.99 seconds
Started Feb 18 03:14:45 PM PST 24
Finished Feb 18 03:14:53 PM PST 24
Peak memory 206536 kb
Host smart-ea05b006-1ec5-476d-875a-c25264e828a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917046510 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1917046510
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/45.edn_intr.2985338740
Short name T129
Test name
Test status
Simulation time 27522672 ps
CPU time 0.94 seconds
Started Feb 18 03:16:28 PM PST 24
Finished Feb 18 03:16:35 PM PST 24
Peak memory 215184 kb
Host smart-94baac7f-d798-42c7-a8a1-424d2400492b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985338740 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.2985338740
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/0.edn_alert.3033559763
Short name T768
Test name
Test status
Simulation time 22694874 ps
CPU time 1.12 seconds
Started Feb 18 03:14:05 PM PST 24
Finished Feb 18 03:14:17 PM PST 24
Peak memory 215040 kb
Host smart-696597ef-ded3-4b4b-b974-4a2fb4c04cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033559763 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3033559763
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert.3553970392
Short name T116
Test name
Test status
Simulation time 41332738 ps
CPU time 1.1 seconds
Started Feb 18 03:15:17 PM PST 24
Finished Feb 18 03:15:29 PM PST 24
Peak memory 215064 kb
Host smart-0290fdb6-8d1c-4443-93c9-ffcaa96aa379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553970392 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3553970392
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/121.edn_genbits.1572330803
Short name T750
Test name
Test status
Simulation time 121592709 ps
CPU time 1.49 seconds
Started Feb 18 03:17:18 PM PST 24
Finished Feb 18 03:17:24 PM PST 24
Peak memory 216260 kb
Host smart-044c9384-df39-4d96-81c5-27b22c538e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572330803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1572330803
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1150137685
Short name T230
Test name
Test status
Simulation time 410703166 ps
CPU time 1.62 seconds
Started Feb 18 12:33:23 PM PST 24
Finished Feb 18 12:33:30 PM PST 24
Peak memory 205472 kb
Host smart-850228cc-1949-4a42-9ea2-1f95e2e8f4e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150137685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1150137685
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2955642140
Short name T240
Test name
Test status
Simulation time 307971726 ps
CPU time 3.28 seconds
Started Feb 18 12:33:28 PM PST 24
Finished Feb 18 12:33:35 PM PST 24
Peak memory 205488 kb
Host smart-69904305-2b15-4dff-b474-1663009cd957
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955642140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2955642140
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2753251499
Short name T229
Test name
Test status
Simulation time 33853263 ps
CPU time 0.88 seconds
Started Feb 18 12:33:22 PM PST 24
Finished Feb 18 12:33:27 PM PST 24
Peak memory 205396 kb
Host smart-f5b4a444-b089-4187-b368-ec96619f5a93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753251499 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2753251499
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1852539265
Short name T925
Test name
Test status
Simulation time 922347574 ps
CPU time 4.56 seconds
Started Feb 18 12:33:25 PM PST 24
Finished Feb 18 12:33:33 PM PST 24
Peak memory 213664 kb
Host smart-ab1fa691-e463-449f-a0d1-76f3b39bda7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852539265 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1852539265
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1253954171
Short name T904
Test name
Test status
Simulation time 24222094 ps
CPU time 0.96 seconds
Started Feb 18 12:33:29 PM PST 24
Finished Feb 18 12:33:34 PM PST 24
Peak memory 205372 kb
Host smart-7482e4c2-ae50-4b94-9c24-4e25b5618664
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253954171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1253954171
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.1201579063
Short name T855
Test name
Test status
Simulation time 15518521 ps
CPU time 0.87 seconds
Started Feb 18 12:33:27 PM PST 24
Finished Feb 18 12:33:31 PM PST 24
Peak memory 205332 kb
Host smart-a720c7fa-5b52-4d88-bd0c-0b256ec98057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201579063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.1201579063
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.924670694
Short name T921
Test name
Test status
Simulation time 40696910 ps
CPU time 1.48 seconds
Started Feb 18 12:33:30 PM PST 24
Finished Feb 18 12:33:36 PM PST 24
Peak memory 205332 kb
Host smart-a69b7a50-2619-4271-8ea1-59661433ef12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924670694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.924670694
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.836835961
Short name T877
Test name
Test status
Simulation time 2317007133 ps
CPU time 4.75 seconds
Started Feb 18 12:33:30 PM PST 24
Finished Feb 18 12:33:39 PM PST 24
Peak memory 213804 kb
Host smart-c8e68cb5-8d76-45cf-87d2-01776a36dfd2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836835961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.836835961
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.3758705494
Short name T260
Test name
Test status
Simulation time 306907588 ps
CPU time 2.34 seconds
Started Feb 18 12:33:30 PM PST 24
Finished Feb 18 12:33:37 PM PST 24
Peak memory 205556 kb
Host smart-cfc5a3f7-c4fb-4ca2-b0d7-ef33790951a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758705494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.3758705494
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1147719732
Short name T239
Test name
Test status
Simulation time 29334292 ps
CPU time 1.31 seconds
Started Feb 18 12:33:28 PM PST 24
Finished Feb 18 12:33:33 PM PST 24
Peak memory 205460 kb
Host smart-07dafa29-243b-4b20-a75f-d483fc45d672
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147719732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1147719732
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.1793212329
Short name T860
Test name
Test status
Simulation time 215895290 ps
CPU time 3.05 seconds
Started Feb 18 12:33:29 PM PST 24
Finished Feb 18 12:33:37 PM PST 24
Peak memory 205392 kb
Host smart-6e7f0d93-e074-457f-9632-ff3924554e43
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793212329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.1793212329
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.313508416
Short name T907
Test name
Test status
Simulation time 35182725 ps
CPU time 0.82 seconds
Started Feb 18 12:33:23 PM PST 24
Finished Feb 18 12:33:28 PM PST 24
Peak memory 205264 kb
Host smart-90223b80-8814-4047-931a-bb6c6861c691
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313508416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.313508416
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.1078908410
Short name T865
Test name
Test status
Simulation time 43009595 ps
CPU time 2.71 seconds
Started Feb 18 12:33:27 PM PST 24
Finished Feb 18 12:33:33 PM PST 24
Peak memory 213736 kb
Host smart-f1787ee0-9463-4d7f-a1b1-65f62a9544b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078908410 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.1078908410
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3045292496
Short name T967
Test name
Test status
Simulation time 138484651 ps
CPU time 0.77 seconds
Started Feb 18 12:33:31 PM PST 24
Finished Feb 18 12:33:35 PM PST 24
Peak memory 205276 kb
Host smart-d74f24e0-e9ff-4891-9e40-09fa6cdcaa42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045292496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3045292496
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2039971032
Short name T895
Test name
Test status
Simulation time 109686736 ps
CPU time 1.16 seconds
Started Feb 18 12:33:28 PM PST 24
Finished Feb 18 12:33:33 PM PST 24
Peak memory 205452 kb
Host smart-019a7cd8-f234-475b-8442-783d1fb5ca5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039971032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2039971032
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2763268917
Short name T906
Test name
Test status
Simulation time 263310397 ps
CPU time 2.39 seconds
Started Feb 18 12:33:25 PM PST 24
Finished Feb 18 12:33:31 PM PST 24
Peak memory 213776 kb
Host smart-29057fc7-73ab-4afb-a100-2c87d251ebfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763268917 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2763268917
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3388447736
Short name T251
Test name
Test status
Simulation time 65205896 ps
CPU time 1.83 seconds
Started Feb 18 12:33:30 PM PST 24
Finished Feb 18 12:33:36 PM PST 24
Peak memory 205380 kb
Host smart-7bf30f7f-e9be-45c1-b311-9f37257f73cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388447736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3388447736
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.3192334007
Short name T866
Test name
Test status
Simulation time 165910646 ps
CPU time 3.18 seconds
Started Feb 18 12:33:46 PM PST 24
Finished Feb 18 12:33:53 PM PST 24
Peak memory 213628 kb
Host smart-7fd0e953-738f-4baa-8398-c7f33b3c49f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192334007 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.3192334007
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1283087860
Short name T244
Test name
Test status
Simulation time 13107873 ps
CPU time 0.89 seconds
Started Feb 18 12:33:45 PM PST 24
Finished Feb 18 12:33:49 PM PST 24
Peak memory 205364 kb
Host smart-29b7a664-66b1-4f38-ac3b-8454a1017876
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283087860 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1283087860
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.588001796
Short name T858
Test name
Test status
Simulation time 19580922 ps
CPU time 0.81 seconds
Started Feb 18 12:33:39 PM PST 24
Finished Feb 18 12:33:41 PM PST 24
Peak memory 205408 kb
Host smart-ed73a92b-82cf-408d-a7c1-9c633a36d78c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588001796 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.588001796
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.901927970
Short name T247
Test name
Test status
Simulation time 24287130 ps
CPU time 1.11 seconds
Started Feb 18 12:33:40 PM PST 24
Finished Feb 18 12:33:42 PM PST 24
Peak memory 205424 kb
Host smart-394a6d92-055a-4a55-939a-b891394f2cb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901927970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.901927970
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3211309174
Short name T862
Test name
Test status
Simulation time 78655717 ps
CPU time 1.57 seconds
Started Feb 18 12:33:43 PM PST 24
Finished Feb 18 12:33:46 PM PST 24
Peak memory 213712 kb
Host smart-645b9415-8344-4356-8e3a-e7528d361db3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211309174 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3211309174
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.4035908783
Short name T893
Test name
Test status
Simulation time 110417404 ps
CPU time 2.41 seconds
Started Feb 18 12:33:43 PM PST 24
Finished Feb 18 12:33:47 PM PST 24
Peak memory 205464 kb
Host smart-f8c2f023-e186-415b-a68f-892774c2077a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035908783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.4035908783
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.2987274464
Short name T859
Test name
Test status
Simulation time 47596135 ps
CPU time 3.04 seconds
Started Feb 18 12:33:44 PM PST 24
Finished Feb 18 12:33:49 PM PST 24
Peak memory 213596 kb
Host smart-121f8927-ba55-4d98-a40f-5628bb2615ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987274464 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.2987274464
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.895900225
Short name T943
Test name
Test status
Simulation time 15469859 ps
CPU time 0.9 seconds
Started Feb 18 12:33:43 PM PST 24
Finished Feb 18 12:33:45 PM PST 24
Peak memory 205356 kb
Host smart-e6f82d34-b7b2-40fb-991a-6adc474171a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895900225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.895900225
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2234862293
Short name T857
Test name
Test status
Simulation time 36995694 ps
CPU time 0.82 seconds
Started Feb 18 12:33:42 PM PST 24
Finished Feb 18 12:33:45 PM PST 24
Peak memory 205364 kb
Host smart-4f1465a7-e9dd-4ca2-929c-33a1382c8888
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234862293 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2234862293
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.1327943922
Short name T935
Test name
Test status
Simulation time 33686633 ps
CPU time 1.45 seconds
Started Feb 18 12:33:40 PM PST 24
Finished Feb 18 12:33:43 PM PST 24
Peak memory 205524 kb
Host smart-642eca68-1f94-421b-8f2d-d7af5f6d7ed2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327943922 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.1327943922
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.2196058976
Short name T934
Test name
Test status
Simulation time 55382718 ps
CPU time 2.35 seconds
Started Feb 18 12:33:46 PM PST 24
Finished Feb 18 12:33:52 PM PST 24
Peak memory 213728 kb
Host smart-9db9d88f-0873-4c41-8538-d2f507aacdc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196058976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.2196058976
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.848930113
Short name T853
Test name
Test status
Simulation time 103964946 ps
CPU time 1.98 seconds
Started Feb 18 12:33:46 PM PST 24
Finished Feb 18 12:33:51 PM PST 24
Peak memory 213640 kb
Host smart-c354cd69-0be1-4c84-bbba-6cabdaf2b900
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848930113 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.848930113
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2740938037
Short name T915
Test name
Test status
Simulation time 15029531 ps
CPU time 0.93 seconds
Started Feb 18 12:33:46 PM PST 24
Finished Feb 18 12:33:50 PM PST 24
Peak memory 205340 kb
Host smart-f9bee2a3-70ef-4495-8905-9c37109b0462
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740938037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2740938037
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.3087288904
Short name T845
Test name
Test status
Simulation time 12441950 ps
CPU time 0.82 seconds
Started Feb 18 12:33:39 PM PST 24
Finished Feb 18 12:33:41 PM PST 24
Peak memory 205332 kb
Host smart-ec84907f-bec5-4cd1-963f-061910d54683
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087288904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.3087288904
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.2408088230
Short name T873
Test name
Test status
Simulation time 33666168 ps
CPU time 1 seconds
Started Feb 18 12:33:45 PM PST 24
Finished Feb 18 12:33:48 PM PST 24
Peak memory 205408 kb
Host smart-05fc9218-07c9-458e-a171-3f0c4a381d3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408088230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.2408088230
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1273091146
Short name T918
Test name
Test status
Simulation time 463005715 ps
CPU time 2.12 seconds
Started Feb 18 12:33:43 PM PST 24
Finished Feb 18 12:33:47 PM PST 24
Peak memory 213752 kb
Host smart-72cad804-19ac-4966-876d-4fdf5dbd1bc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273091146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1273091146
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2371747682
Short name T875
Test name
Test status
Simulation time 80539570 ps
CPU time 1.57 seconds
Started Feb 18 12:33:44 PM PST 24
Finished Feb 18 12:33:49 PM PST 24
Peak memory 205452 kb
Host smart-6d0780f9-8fc6-4811-b17c-0f30c11ce8d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371747682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2371747682
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.135885555
Short name T876
Test name
Test status
Simulation time 117834763 ps
CPU time 2.24 seconds
Started Feb 18 12:33:47 PM PST 24
Finished Feb 18 12:33:52 PM PST 24
Peak memory 213632 kb
Host smart-875348f1-337c-4d94-a91e-74d9b1968e55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135885555 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.135885555
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2887665949
Short name T929
Test name
Test status
Simulation time 126942898 ps
CPU time 0.95 seconds
Started Feb 18 12:33:45 PM PST 24
Finished Feb 18 12:33:48 PM PST 24
Peak memory 205388 kb
Host smart-78cb1f32-0c42-4a36-85fb-3ccf21700555
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887665949 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2887665949
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.3061633330
Short name T881
Test name
Test status
Simulation time 54024836 ps
CPU time 0.89 seconds
Started Feb 18 12:33:43 PM PST 24
Finished Feb 18 12:33:46 PM PST 24
Peak memory 205312 kb
Host smart-aef63650-475e-4ab0-a48e-6d0773ebd440
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061633330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.3061633330
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.1361627144
Short name T912
Test name
Test status
Simulation time 151107143 ps
CPU time 1.39 seconds
Started Feb 18 12:33:40 PM PST 24
Finished Feb 18 12:33:42 PM PST 24
Peak memory 205244 kb
Host smart-6f3dead3-a87f-484c-90cc-9ff6012fbcb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361627144 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.1361627144
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.2114262830
Short name T930
Test name
Test status
Simulation time 104482787 ps
CPU time 1.94 seconds
Started Feb 18 12:33:44 PM PST 24
Finished Feb 18 12:33:48 PM PST 24
Peak memory 213756 kb
Host smart-8de194fb-aa82-426d-916c-f5b548b5f25e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114262830 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.2114262830
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3717249349
Short name T258
Test name
Test status
Simulation time 321628423 ps
CPU time 1.5 seconds
Started Feb 18 12:33:44 PM PST 24
Finished Feb 18 12:33:47 PM PST 24
Peak memory 205404 kb
Host smart-8e6c23e0-68eb-4bbb-a2eb-7cf495bdaafc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717249349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3717249349
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.747228302
Short name T863
Test name
Test status
Simulation time 99156133 ps
CPU time 1.98 seconds
Started Feb 18 12:33:45 PM PST 24
Finished Feb 18 12:33:49 PM PST 24
Peak memory 213640 kb
Host smart-b9070a1e-e212-4a48-878d-c2303e73e3a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747228302 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.747228302
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1203532916
Short name T237
Test name
Test status
Simulation time 53187350 ps
CPU time 0.89 seconds
Started Feb 18 12:33:41 PM PST 24
Finished Feb 18 12:33:42 PM PST 24
Peak memory 205432 kb
Host smart-42bba300-8cfd-4722-81f9-925a2ced7ca1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203532916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1203532916
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3263824568
Short name T952
Test name
Test status
Simulation time 82129232 ps
CPU time 0.82 seconds
Started Feb 18 12:33:41 PM PST 24
Finished Feb 18 12:33:43 PM PST 24
Peak memory 205156 kb
Host smart-50ab1200-457b-46b1-aed9-61516e2f94d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263824568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3263824568
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2319348115
Short name T892
Test name
Test status
Simulation time 100525087 ps
CPU time 1.1 seconds
Started Feb 18 12:33:39 PM PST 24
Finished Feb 18 12:33:41 PM PST 24
Peak memory 205356 kb
Host smart-9efb2db6-dbdb-4630-9cb1-2e6b3fec2789
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319348115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2319348115
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.1545211862
Short name T205
Test name
Test status
Simulation time 81725124 ps
CPU time 2.63 seconds
Started Feb 18 12:33:46 PM PST 24
Finished Feb 18 12:33:52 PM PST 24
Peak memory 216732 kb
Host smart-c7f4b2e2-5f2a-47c4-b5f9-41ac77639a9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545211862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.1545211862
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3004187141
Short name T932
Test name
Test status
Simulation time 168219253 ps
CPU time 1.45 seconds
Started Feb 18 12:33:45 PM PST 24
Finished Feb 18 12:33:50 PM PST 24
Peak memory 205452 kb
Host smart-b2a7a057-cb0b-4f82-991e-c9e3625cf197
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004187141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3004187141
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1594592166
Short name T966
Test name
Test status
Simulation time 53436255 ps
CPU time 2.03 seconds
Started Feb 18 12:33:49 PM PST 24
Finished Feb 18 12:33:54 PM PST 24
Peak memory 213656 kb
Host smart-3b574fb2-ad1c-4181-a9a1-6e8ec0feb2b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594592166 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1594592166
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1104465729
Short name T231
Test name
Test status
Simulation time 28834369 ps
CPU time 0.87 seconds
Started Feb 18 12:33:53 PM PST 24
Finished Feb 18 12:33:56 PM PST 24
Peak memory 205268 kb
Host smart-bb7503e7-2995-41d3-b45d-274e3a9b045c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104465729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1104465729
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3571239902
Short name T894
Test name
Test status
Simulation time 39752255 ps
CPU time 0.83 seconds
Started Feb 18 12:33:48 PM PST 24
Finished Feb 18 12:33:51 PM PST 24
Peak memory 205204 kb
Host smart-54742c0f-d199-48b5-82e7-eb491f00dcce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571239902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3571239902
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1964044532
Short name T965
Test name
Test status
Simulation time 21868889 ps
CPU time 1.09 seconds
Started Feb 18 12:33:56 PM PST 24
Finished Feb 18 12:34:00 PM PST 24
Peak memory 205456 kb
Host smart-cf55f1d9-c165-474d-8d92-8a3954712475
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964044532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1964044532
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3322442138
Short name T922
Test name
Test status
Simulation time 57331020 ps
CPU time 2.29 seconds
Started Feb 18 12:33:56 PM PST 24
Finished Feb 18 12:34:01 PM PST 24
Peak memory 213632 kb
Host smart-72f6ea89-15e7-4a0c-875f-f917a8980d59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322442138 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3322442138
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1843467031
Short name T890
Test name
Test status
Simulation time 140844902 ps
CPU time 1.4 seconds
Started Feb 18 12:33:51 PM PST 24
Finished Feb 18 12:33:56 PM PST 24
Peak memory 205396 kb
Host smart-1917e33c-131b-47c2-b21f-6a1887e2a5a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843467031 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1843467031
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2820930811
Short name T842
Test name
Test status
Simulation time 197788937 ps
CPU time 3.34 seconds
Started Feb 18 12:33:50 PM PST 24
Finished Feb 18 12:33:57 PM PST 24
Peak memory 213612 kb
Host smart-e6a20933-64e1-4cb4-904a-e9204668b595
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820930811 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2820930811
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.159721058
Short name T248
Test name
Test status
Simulation time 46019682 ps
CPU time 0.88 seconds
Started Feb 18 12:33:52 PM PST 24
Finished Feb 18 12:33:56 PM PST 24
Peak memory 205408 kb
Host smart-df77167a-b194-427d-97d9-854597586ec4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159721058 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.159721058
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3043305175
Short name T928
Test name
Test status
Simulation time 24293015 ps
CPU time 0.84 seconds
Started Feb 18 12:33:59 PM PST 24
Finished Feb 18 12:34:02 PM PST 24
Peak memory 205320 kb
Host smart-7fcd198b-e9e7-49ba-a588-04db51df7e58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043305175 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3043305175
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3587560204
Short name T964
Test name
Test status
Simulation time 53646022 ps
CPU time 1.1 seconds
Started Feb 18 12:33:50 PM PST 24
Finished Feb 18 12:33:55 PM PST 24
Peak memory 205408 kb
Host smart-ce7ea851-3755-4dca-9a88-30af8e46dc15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587560204 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3587560204
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.1340393926
Short name T840
Test name
Test status
Simulation time 32747580 ps
CPU time 2.4 seconds
Started Feb 18 12:33:52 PM PST 24
Finished Feb 18 12:33:57 PM PST 24
Peak memory 213704 kb
Host smart-bd552459-1f23-451d-87f2-639b41473a5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340393926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.1340393926
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.964367936
Short name T939
Test name
Test status
Simulation time 73335785 ps
CPU time 1.86 seconds
Started Feb 18 12:33:50 PM PST 24
Finished Feb 18 12:33:55 PM PST 24
Peak memory 205460 kb
Host smart-adf59f20-1c24-4be5-88f0-28519c24d185
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964367936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.964367936
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3503632230
Short name T917
Test name
Test status
Simulation time 49728339 ps
CPU time 1.87 seconds
Started Feb 18 12:33:50 PM PST 24
Finished Feb 18 12:33:55 PM PST 24
Peak memory 213668 kb
Host smart-c324c4cd-87e3-414d-ad00-2cefa83b966c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503632230 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3503632230
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1471715688
Short name T218
Test name
Test status
Simulation time 23685541 ps
CPU time 0.85 seconds
Started Feb 18 12:33:55 PM PST 24
Finished Feb 18 12:33:59 PM PST 24
Peak memory 205388 kb
Host smart-99842afe-c99e-40e2-bb8e-d7cf83873673
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471715688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1471715688
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.544762653
Short name T953
Test name
Test status
Simulation time 12599938 ps
CPU time 0.87 seconds
Started Feb 18 12:33:50 PM PST 24
Finished Feb 18 12:33:53 PM PST 24
Peak memory 205340 kb
Host smart-7fe4deaa-7b78-49f9-8685-9abe7da429cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544762653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.544762653
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1939745559
Short name T243
Test name
Test status
Simulation time 57984707 ps
CPU time 1.33 seconds
Started Feb 18 12:33:51 PM PST 24
Finished Feb 18 12:33:55 PM PST 24
Peak memory 205376 kb
Host smart-0a8ac355-5f3a-4708-a56a-fb489edd1070
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939745559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1939745559
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.276494965
Short name T938
Test name
Test status
Simulation time 45042015 ps
CPU time 1.82 seconds
Started Feb 18 12:33:50 PM PST 24
Finished Feb 18 12:33:55 PM PST 24
Peak memory 213700 kb
Host smart-e57657fa-76bc-49ee-bfdd-946fe2ed56a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276494965 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.276494965
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1292803995
Short name T940
Test name
Test status
Simulation time 249133019 ps
CPU time 2.09 seconds
Started Feb 18 12:33:50 PM PST 24
Finished Feb 18 12:33:54 PM PST 24
Peak memory 205468 kb
Host smart-4e77e537-66a9-4984-906e-d4ff214e5682
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292803995 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1292803995
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.1103159956
Short name T909
Test name
Test status
Simulation time 118039889 ps
CPU time 2.34 seconds
Started Feb 18 12:33:54 PM PST 24
Finished Feb 18 12:33:59 PM PST 24
Peak memory 213724 kb
Host smart-f2b66925-445b-4897-9091-3a477a8b0404
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103159956 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.1103159956
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1623699102
Short name T931
Test name
Test status
Simulation time 51299760 ps
CPU time 0.79 seconds
Started Feb 18 12:33:48 PM PST 24
Finished Feb 18 12:33:51 PM PST 24
Peak memory 205300 kb
Host smart-76d58953-5bb5-40a5-9d3e-5b868abb6ddb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623699102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1623699102
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1596773156
Short name T962
Test name
Test status
Simulation time 20626000 ps
CPU time 0.91 seconds
Started Feb 18 12:33:59 PM PST 24
Finished Feb 18 12:34:02 PM PST 24
Peak memory 205320 kb
Host smart-46e74e20-4bb7-41b4-80f1-3cefb04edd61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596773156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1596773156
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.634730969
Short name T948
Test name
Test status
Simulation time 29015192 ps
CPU time 1.25 seconds
Started Feb 18 12:33:50 PM PST 24
Finished Feb 18 12:33:53 PM PST 24
Peak memory 205492 kb
Host smart-e38631de-f75c-4ea8-ab1b-6a146bfcd00c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634730969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.634730969
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3043324377
Short name T926
Test name
Test status
Simulation time 27154680 ps
CPU time 1.7 seconds
Started Feb 18 12:33:50 PM PST 24
Finished Feb 18 12:33:55 PM PST 24
Peak memory 213660 kb
Host smart-bc5c7b87-31fc-4ef5-9a8f-31041527ef8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043324377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3043324377
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3292038330
Short name T899
Test name
Test status
Simulation time 48763771 ps
CPU time 1.64 seconds
Started Feb 18 12:33:53 PM PST 24
Finished Feb 18 12:33:57 PM PST 24
Peak memory 205304 kb
Host smart-d5dd6b52-2bee-4e60-a5d7-5f86dedd19a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292038330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3292038330
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1821500222
Short name T844
Test name
Test status
Simulation time 74516244 ps
CPU time 1.76 seconds
Started Feb 18 12:34:00 PM PST 24
Finished Feb 18 12:34:03 PM PST 24
Peak memory 213724 kb
Host smart-083a61b0-7690-4f9c-b52e-c77b08b7f457
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821500222 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1821500222
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.1663926449
Short name T911
Test name
Test status
Simulation time 26122779 ps
CPU time 0.89 seconds
Started Feb 18 12:33:52 PM PST 24
Finished Feb 18 12:33:56 PM PST 24
Peak memory 205408 kb
Host smart-9bf0ce71-0bec-4769-a10a-d6fbf71fc7ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663926449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.1663926449
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.3095169648
Short name T841
Test name
Test status
Simulation time 31699945 ps
CPU time 0.83 seconds
Started Feb 18 12:33:53 PM PST 24
Finished Feb 18 12:33:56 PM PST 24
Peak memory 205036 kb
Host smart-e34447df-8b83-4694-a366-2c1b47f56f25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095169648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.3095169648
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3214955533
Short name T232
Test name
Test status
Simulation time 39721442 ps
CPU time 0.91 seconds
Started Feb 18 12:33:49 PM PST 24
Finished Feb 18 12:33:52 PM PST 24
Peak memory 205504 kb
Host smart-a24ff3c3-1477-418e-8f53-d432bb93c588
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214955533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3214955533
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1583582118
Short name T891
Test name
Test status
Simulation time 67179435 ps
CPU time 2.72 seconds
Started Feb 18 12:33:50 PM PST 24
Finished Feb 18 12:33:56 PM PST 24
Peak memory 213728 kb
Host smart-87229d00-1f6e-4397-a72d-5fb41e35646b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583582118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1583582118
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3105765929
Short name T252
Test name
Test status
Simulation time 176457333 ps
CPU time 2.27 seconds
Started Feb 18 12:33:48 PM PST 24
Finished Feb 18 12:33:53 PM PST 24
Peak memory 205364 kb
Host smart-3d64374d-5a8f-4a43-b05e-c21cbbd79e79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105765929 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3105765929
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.4201189543
Short name T238
Test name
Test status
Simulation time 41590575 ps
CPU time 1.59 seconds
Started Feb 18 12:33:25 PM PST 24
Finished Feb 18 12:33:31 PM PST 24
Peak memory 205472 kb
Host smart-8943c576-2b71-4788-9c3c-544a21501bf0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201189543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.4201189543
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1270619543
Short name T227
Test name
Test status
Simulation time 223727826 ps
CPU time 5.99 seconds
Started Feb 18 12:33:30 PM PST 24
Finished Feb 18 12:33:40 PM PST 24
Peak memory 205484 kb
Host smart-0f6d0ec4-da11-424a-a36d-200ffd7601da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270619543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1270619543
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.559515401
Short name T241
Test name
Test status
Simulation time 23294922 ps
CPU time 0.96 seconds
Started Feb 18 12:33:25 PM PST 24
Finished Feb 18 12:33:30 PM PST 24
Peak memory 205468 kb
Host smart-cc16a7f1-f2db-4087-b25d-58dbc6f2f33a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559515401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.559515401
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.1053739885
Short name T947
Test name
Test status
Simulation time 32757388 ps
CPU time 1.75 seconds
Started Feb 18 12:33:29 PM PST 24
Finished Feb 18 12:33:34 PM PST 24
Peak memory 213640 kb
Host smart-600577f2-755f-42a3-b28e-70eebcbafd6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053739885 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.1053739885
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.3236670355
Short name T233
Test name
Test status
Simulation time 26823356 ps
CPU time 0.83 seconds
Started Feb 18 12:33:28 PM PST 24
Finished Feb 18 12:33:33 PM PST 24
Peak memory 205444 kb
Host smart-2585827b-64f7-40a5-bd97-8a7c6ceb4b71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236670355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.3236670355
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.1882951757
Short name T908
Test name
Test status
Simulation time 26695553 ps
CPU time 0.87 seconds
Started Feb 18 12:33:27 PM PST 24
Finished Feb 18 12:33:32 PM PST 24
Peak memory 205288 kb
Host smart-c6b0cec3-0f2c-4952-8686-17086511cde8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882951757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.1882951757
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.511324708
Short name T242
Test name
Test status
Simulation time 35745157 ps
CPU time 1.02 seconds
Started Feb 18 12:33:32 PM PST 24
Finished Feb 18 12:33:36 PM PST 24
Peak memory 205484 kb
Host smart-36fc9219-6f99-4d4e-80e6-3e8dbd74f024
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511324708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_out
standing.511324708
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.3051123953
Short name T941
Test name
Test status
Simulation time 206351245 ps
CPU time 2.1 seconds
Started Feb 18 12:33:25 PM PST 24
Finished Feb 18 12:33:31 PM PST 24
Peak memory 215956 kb
Host smart-dbcc8961-1bc1-4160-9542-4cb7d709869d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051123953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.3051123953
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1342544369
Short name T950
Test name
Test status
Simulation time 263933942 ps
CPU time 2.33 seconds
Started Feb 18 12:33:30 PM PST 24
Finished Feb 18 12:33:37 PM PST 24
Peak memory 205376 kb
Host smart-7bc3b199-46e7-4687-978c-235174580e41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342544369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1342544369
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1869628366
Short name T919
Test name
Test status
Simulation time 76761969 ps
CPU time 0.78 seconds
Started Feb 18 12:33:50 PM PST 24
Finished Feb 18 12:33:55 PM PST 24
Peak memory 205192 kb
Host smart-3bea61b5-751a-4fd3-abcd-b8dc9f81deeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869628366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1869628366
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.3426508150
Short name T864
Test name
Test status
Simulation time 24008874 ps
CPU time 0.86 seconds
Started Feb 18 12:33:54 PM PST 24
Finished Feb 18 12:33:57 PM PST 24
Peak memory 205396 kb
Host smart-d13f85a1-83e5-442a-ae1c-3aee6e23e806
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426508150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.3426508150
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.889744266
Short name T852
Test name
Test status
Simulation time 44509536 ps
CPU time 0.81 seconds
Started Feb 18 12:33:50 PM PST 24
Finished Feb 18 12:33:52 PM PST 24
Peak memory 205320 kb
Host smart-00a77eb8-bb98-4b73-a94a-f9e0633392c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889744266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.889744266
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.2428500252
Short name T946
Test name
Test status
Simulation time 15187893 ps
CPU time 0.88 seconds
Started Feb 18 12:33:52 PM PST 24
Finished Feb 18 12:33:56 PM PST 24
Peak memory 205332 kb
Host smart-8f05fdb5-8629-48ab-8e20-f93f494f69f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428500252 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.2428500252
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.504665584
Short name T885
Test name
Test status
Simulation time 26873837 ps
CPU time 0.82 seconds
Started Feb 18 12:33:53 PM PST 24
Finished Feb 18 12:33:57 PM PST 24
Peak memory 205324 kb
Host smart-d290832c-9b6a-4ebd-a4be-357712657ae7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504665584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.504665584
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.921170855
Short name T945
Test name
Test status
Simulation time 23315283 ps
CPU time 0.87 seconds
Started Feb 18 12:33:53 PM PST 24
Finished Feb 18 12:33:57 PM PST 24
Peak memory 205396 kb
Host smart-31acd752-f3d4-47e0-b133-416f0b73a1ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921170855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.921170855
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.4050640905
Short name T861
Test name
Test status
Simulation time 18063906 ps
CPU time 0.79 seconds
Started Feb 18 12:33:50 PM PST 24
Finished Feb 18 12:33:54 PM PST 24
Peak memory 205188 kb
Host smart-e82a66c9-38b7-4648-b9d6-05dff5ae2d1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050640905 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.4050640905
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2413969687
Short name T872
Test name
Test status
Simulation time 29308302 ps
CPU time 0.92 seconds
Started Feb 18 12:33:54 PM PST 24
Finished Feb 18 12:33:58 PM PST 24
Peak memory 205308 kb
Host smart-ff68beba-0b8f-4e4a-8875-907476ecd4b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413969687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2413969687
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3444367620
Short name T851
Test name
Test status
Simulation time 15646556 ps
CPU time 0.86 seconds
Started Feb 18 12:33:59 PM PST 24
Finished Feb 18 12:34:02 PM PST 24
Peak memory 205320 kb
Host smart-324d3690-4909-4750-ae3c-7f25add0a8a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444367620 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3444367620
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1015635801
Short name T949
Test name
Test status
Simulation time 69180232 ps
CPU time 0.8 seconds
Started Feb 18 12:33:51 PM PST 24
Finished Feb 18 12:33:56 PM PST 24
Peak memory 205372 kb
Host smart-b6750e7f-94ab-4ea7-ab69-11093f046037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015635801 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1015635801
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.231846603
Short name T886
Test name
Test status
Simulation time 262131039 ps
CPU time 6.17 seconds
Started Feb 18 12:33:32 PM PST 24
Finished Feb 18 12:33:41 PM PST 24
Peak memory 205464 kb
Host smart-a7c9e14d-fc02-4572-a085-f664f04d83eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231846603 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.231846603
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2239341613
Short name T902
Test name
Test status
Simulation time 42264155 ps
CPU time 0.82 seconds
Started Feb 18 12:33:22 PM PST 24
Finished Feb 18 12:33:27 PM PST 24
Peak memory 205276 kb
Host smart-ac71b8b3-e7ac-462f-b516-b506a77634c7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239341613 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2239341613
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2140516488
Short name T905
Test name
Test status
Simulation time 131964772 ps
CPU time 1.97 seconds
Started Feb 18 12:33:28 PM PST 24
Finished Feb 18 12:33:34 PM PST 24
Peak memory 221788 kb
Host smart-117948c0-d992-4c59-a943-4acd25570e5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140516488 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2140516488
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2863851993
Short name T896
Test name
Test status
Simulation time 14850088 ps
CPU time 0.85 seconds
Started Feb 18 12:33:29 PM PST 24
Finished Feb 18 12:33:35 PM PST 24
Peak memory 205396 kb
Host smart-8f546d05-4a42-4554-8dda-77047c4c2541
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863851993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2863851993
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.282215546
Short name T871
Test name
Test status
Simulation time 15195114 ps
CPU time 0.93 seconds
Started Feb 18 12:33:29 PM PST 24
Finished Feb 18 12:33:33 PM PST 24
Peak memory 205288 kb
Host smart-61b5d858-59eb-45bc-824d-a3238395ebef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282215546 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.282215546
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1872441680
Short name T900
Test name
Test status
Simulation time 65221588 ps
CPU time 1.31 seconds
Started Feb 18 12:33:25 PM PST 24
Finished Feb 18 12:33:30 PM PST 24
Peak memory 205428 kb
Host smart-1de73f8c-ca4f-423a-8a5e-b585e18cd803
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872441680 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1872441680
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1252298961
Short name T913
Test name
Test status
Simulation time 529944898 ps
CPU time 2.69 seconds
Started Feb 18 12:33:29 PM PST 24
Finished Feb 18 12:33:37 PM PST 24
Peak memory 213656 kb
Host smart-f4d2c329-e385-4f74-8ac3-2978e6f29ed5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252298961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1252298961
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1528203868
Short name T959
Test name
Test status
Simulation time 119512466 ps
CPU time 1.65 seconds
Started Feb 18 12:33:28 PM PST 24
Finished Feb 18 12:33:34 PM PST 24
Peak memory 205452 kb
Host smart-8effffea-d566-4f55-957d-6cbddc6dac82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528203868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1528203868
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.3509226408
Short name T963
Test name
Test status
Simulation time 35756833 ps
CPU time 0.82 seconds
Started Feb 18 12:33:55 PM PST 24
Finished Feb 18 12:33:59 PM PST 24
Peak memory 205192 kb
Host smart-660fb146-72c8-4fab-a027-6435f54905a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509226408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.3509226408
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2531702626
Short name T927
Test name
Test status
Simulation time 13990312 ps
CPU time 0.83 seconds
Started Feb 18 12:33:51 PM PST 24
Finished Feb 18 12:33:56 PM PST 24
Peak memory 205300 kb
Host smart-afc442a6-5610-4926-a4f5-f6b40733d1a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531702626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2531702626
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.312927630
Short name T958
Test name
Test status
Simulation time 111120442 ps
CPU time 0.84 seconds
Started Feb 18 12:33:50 PM PST 24
Finished Feb 18 12:33:55 PM PST 24
Peak memory 205228 kb
Host smart-72015fa8-9f30-47d1-9fa5-5ac0d7a3cc31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312927630 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.312927630
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.772815017
Short name T955
Test name
Test status
Simulation time 25062202 ps
CPU time 0.84 seconds
Started Feb 18 12:33:50 PM PST 24
Finished Feb 18 12:33:54 PM PST 24
Peak memory 205328 kb
Host smart-6c12820f-260c-4ef4-aebb-b5009c11efe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772815017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.772815017
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.4095589504
Short name T880
Test name
Test status
Simulation time 22083768 ps
CPU time 0.83 seconds
Started Feb 18 12:33:51 PM PST 24
Finished Feb 18 12:33:56 PM PST 24
Peak memory 205344 kb
Host smart-c50b3199-aaa7-4074-9afd-80ce24b9a81f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095589504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.4095589504
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.1718570771
Short name T936
Test name
Test status
Simulation time 20689935 ps
CPU time 0.83 seconds
Started Feb 18 12:34:00 PM PST 24
Finished Feb 18 12:34:02 PM PST 24
Peak memory 205188 kb
Host smart-3cc65afa-6d05-4c44-b7ba-34c3b4fd285a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718570771 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.1718570771
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3811469450
Short name T889
Test name
Test status
Simulation time 42350506 ps
CPU time 0.85 seconds
Started Feb 18 12:34:02 PM PST 24
Finished Feb 18 12:34:05 PM PST 24
Peak memory 205324 kb
Host smart-df360101-5a4d-4b2b-a736-f0744f22e64d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811469450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3811469450
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2898911894
Short name T920
Test name
Test status
Simulation time 22390479 ps
CPU time 0.82 seconds
Started Feb 18 12:33:57 PM PST 24
Finished Feb 18 12:34:00 PM PST 24
Peak memory 205288 kb
Host smart-87092171-ef5c-4578-b437-30bd8bda2c52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898911894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2898911894
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1950154434
Short name T901
Test name
Test status
Simulation time 12572114 ps
CPU time 0.85 seconds
Started Feb 18 12:33:59 PM PST 24
Finished Feb 18 12:34:02 PM PST 24
Peak memory 205324 kb
Host smart-2966100d-08ec-4caa-b587-63645a8c73ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950154434 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1950154434
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.4036286120
Short name T882
Test name
Test status
Simulation time 39549962 ps
CPU time 0.88 seconds
Started Feb 18 12:34:00 PM PST 24
Finished Feb 18 12:34:03 PM PST 24
Peak memory 205312 kb
Host smart-8e7998e3-0654-4782-97e9-ebacc6219137
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036286120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.4036286120
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.877332640
Short name T951
Test name
Test status
Simulation time 18748846 ps
CPU time 1.25 seconds
Started Feb 18 12:33:33 PM PST 24
Finished Feb 18 12:33:37 PM PST 24
Peak memory 205468 kb
Host smart-aedea535-d57e-4971-ae67-4330ce77a348
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877332640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.877332640
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2459060369
Short name T849
Test name
Test status
Simulation time 98695096 ps
CPU time 3.06 seconds
Started Feb 18 12:33:35 PM PST 24
Finished Feb 18 12:33:41 PM PST 24
Peak memory 205480 kb
Host smart-729b0ab8-d192-4a6b-87ba-d38eea6c9d2e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459060369 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2459060369
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.333380124
Short name T236
Test name
Test status
Simulation time 66256460 ps
CPU time 1.01 seconds
Started Feb 18 12:33:32 PM PST 24
Finished Feb 18 12:33:36 PM PST 24
Peak memory 205404 kb
Host smart-6606131d-2152-4c67-a953-74c7052d57ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333380124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.333380124
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3064789918
Short name T957
Test name
Test status
Simulation time 353686867 ps
CPU time 2.97 seconds
Started Feb 18 12:33:34 PM PST 24
Finished Feb 18 12:33:40 PM PST 24
Peak memory 213628 kb
Host smart-7472b502-87ce-42a9-8ca7-207a976a3d0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064789918 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3064789918
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.3847181260
Short name T246
Test name
Test status
Simulation time 28991764 ps
CPU time 0.82 seconds
Started Feb 18 12:33:34 PM PST 24
Finished Feb 18 12:33:37 PM PST 24
Peak memory 205328 kb
Host smart-dac25b19-78a7-4bc2-af28-ecf7d3151f06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847181260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.3847181260
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3289435904
Short name T848
Test name
Test status
Simulation time 22901980 ps
CPU time 0.91 seconds
Started Feb 18 12:33:32 PM PST 24
Finished Feb 18 12:33:36 PM PST 24
Peak memory 204880 kb
Host smart-375e03c2-9beb-4bec-9028-4c8197be9938
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289435904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3289435904
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.34854824
Short name T213
Test name
Test status
Simulation time 151702065 ps
CPU time 1.11 seconds
Started Feb 18 12:33:32 PM PST 24
Finished Feb 18 12:33:36 PM PST 24
Peak memory 205468 kb
Host smart-39ed02dd-f069-4c26-a293-5bfc75daa67f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34854824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_outs
tanding.34854824
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3534870649
Short name T879
Test name
Test status
Simulation time 29877852 ps
CPU time 1.97 seconds
Started Feb 18 12:33:32 PM PST 24
Finished Feb 18 12:33:37 PM PST 24
Peak memory 213748 kb
Host smart-0ab1ab63-77f3-4f25-98b4-52514bffa87c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534870649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3534870649
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.466527508
Short name T937
Test name
Test status
Simulation time 78927785 ps
CPU time 1.52 seconds
Started Feb 18 12:33:26 PM PST 24
Finished Feb 18 12:33:31 PM PST 24
Peak memory 205348 kb
Host smart-54bf60ad-dbcb-47ce-924d-29b6f8dd99fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466527508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.466527508
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2016045625
Short name T883
Test name
Test status
Simulation time 27423870 ps
CPU time 0.87 seconds
Started Feb 18 12:34:03 PM PST 24
Finished Feb 18 12:34:05 PM PST 24
Peak memory 205304 kb
Host smart-1cc98b7f-540a-4c55-99c1-6392056fa418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016045625 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2016045625
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.237494223
Short name T846
Test name
Test status
Simulation time 53407844 ps
CPU time 0.84 seconds
Started Feb 18 12:34:10 PM PST 24
Finished Feb 18 12:34:13 PM PST 24
Peak memory 205304 kb
Host smart-cb9548a4-10e8-40ff-8642-e8ccc53fa6f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237494223 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.237494223
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.604270130
Short name T960
Test name
Test status
Simulation time 56068614 ps
CPU time 0.92 seconds
Started Feb 18 12:33:56 PM PST 24
Finished Feb 18 12:34:00 PM PST 24
Peak memory 205336 kb
Host smart-c731fd3c-b87e-4752-81e9-a7380272dec0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604270130 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.604270130
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.3540593338
Short name T910
Test name
Test status
Simulation time 19576800 ps
CPU time 0.78 seconds
Started Feb 18 12:33:55 PM PST 24
Finished Feb 18 12:33:59 PM PST 24
Peak memory 205220 kb
Host smart-a6e21b0f-98cb-42ca-921e-3e9ea66dc087
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540593338 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.3540593338
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.712842173
Short name T869
Test name
Test status
Simulation time 37621409 ps
CPU time 0.8 seconds
Started Feb 18 12:33:58 PM PST 24
Finished Feb 18 12:34:00 PM PST 24
Peak memory 205328 kb
Host smart-d69655f6-34be-4495-9b79-2b37ebe8944c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712842173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.712842173
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3961058852
Short name T944
Test name
Test status
Simulation time 10866255 ps
CPU time 0.87 seconds
Started Feb 18 12:33:59 PM PST 24
Finished Feb 18 12:34:02 PM PST 24
Peak memory 205284 kb
Host smart-007fb613-13f6-475f-841e-facdda7c7634
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961058852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3961058852
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.4267183202
Short name T839
Test name
Test status
Simulation time 42631041 ps
CPU time 0.85 seconds
Started Feb 18 12:34:01 PM PST 24
Finished Feb 18 12:34:04 PM PST 24
Peak memory 205276 kb
Host smart-918449a6-8696-4dc8-a5e5-ac46c2d4c09b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267183202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.4267183202
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1898971024
Short name T968
Test name
Test status
Simulation time 18222746 ps
CPU time 0.93 seconds
Started Feb 18 12:34:06 PM PST 24
Finished Feb 18 12:34:08 PM PST 24
Peak memory 205340 kb
Host smart-4161ed94-a263-4c6d-9a9e-9f5ac698f1bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898971024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1898971024
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2209486203
Short name T956
Test name
Test status
Simulation time 14418179 ps
CPU time 0.83 seconds
Started Feb 18 12:34:00 PM PST 24
Finished Feb 18 12:34:02 PM PST 24
Peak memory 205168 kb
Host smart-42060875-69b5-45b4-9f15-89cb06ac7da9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209486203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2209486203
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1645649524
Short name T868
Test name
Test status
Simulation time 33261210 ps
CPU time 0.83 seconds
Started Feb 18 12:34:00 PM PST 24
Finished Feb 18 12:34:02 PM PST 24
Peak memory 205200 kb
Host smart-1b7d9162-ee82-4673-8ce7-4fa6122e437a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645649524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1645649524
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.236319493
Short name T924
Test name
Test status
Simulation time 108166097 ps
CPU time 3.74 seconds
Started Feb 18 12:33:32 PM PST 24
Finished Feb 18 12:33:39 PM PST 24
Peak memory 213800 kb
Host smart-2e8f064d-185e-4c23-8ff4-085c57d2d0e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236319493 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.236319493
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2936831824
Short name T903
Test name
Test status
Simulation time 21985893 ps
CPU time 0.98 seconds
Started Feb 18 12:33:31 PM PST 24
Finished Feb 18 12:33:36 PM PST 24
Peak memory 205488 kb
Host smart-1ea792ab-17a6-4e05-a179-0b8e6178805c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936831824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2936831824
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.1299181112
Short name T867
Test name
Test status
Simulation time 39974669 ps
CPU time 0.78 seconds
Started Feb 18 12:33:36 PM PST 24
Finished Feb 18 12:33:39 PM PST 24
Peak memory 205200 kb
Host smart-b9741fde-66e7-4d22-bdb6-0094ce57880c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299181112 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.1299181112
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.4150127504
Short name T942
Test name
Test status
Simulation time 23436497 ps
CPU time 0.91 seconds
Started Feb 18 12:33:34 PM PST 24
Finished Feb 18 12:33:38 PM PST 24
Peak memory 205400 kb
Host smart-3a5ee218-06e3-49bb-8315-5aabbd9df32e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150127504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.4150127504
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.3646417641
Short name T933
Test name
Test status
Simulation time 198613300 ps
CPU time 3.59 seconds
Started Feb 18 12:33:32 PM PST 24
Finished Feb 18 12:33:39 PM PST 24
Peak memory 213648 kb
Host smart-63fc3f3e-7e66-41a2-bd2b-24e8ba76872a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646417641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.3646417641
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2961007072
Short name T262
Test name
Test status
Simulation time 150036322 ps
CPU time 2.09 seconds
Started Feb 18 12:33:38 PM PST 24
Finished Feb 18 12:33:42 PM PST 24
Peak memory 205420 kb
Host smart-9cbd206d-dbc2-4455-92d6-8a6bc71ada09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961007072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2961007072
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1579783273
Short name T854
Test name
Test status
Simulation time 209382275 ps
CPU time 3.76 seconds
Started Feb 18 12:33:34 PM PST 24
Finished Feb 18 12:33:40 PM PST 24
Peak memory 213708 kb
Host smart-c0227c6f-6aba-4b18-ad5b-0e1ecd5bd12f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579783273 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1579783273
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2407964060
Short name T234
Test name
Test status
Simulation time 33198183 ps
CPU time 0.89 seconds
Started Feb 18 12:33:33 PM PST 24
Finished Feb 18 12:33:37 PM PST 24
Peak memory 205356 kb
Host smart-f4cc7392-ec7c-4a4e-ae94-8563d0546f6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407964060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2407964060
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.4181893840
Short name T961
Test name
Test status
Simulation time 13452620 ps
CPU time 0.87 seconds
Started Feb 18 12:33:32 PM PST 24
Finished Feb 18 12:33:36 PM PST 24
Peak memory 204784 kb
Host smart-aeb8e934-f6b2-4762-b74f-e8f63b4ed734
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181893840 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.4181893840
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1453365605
Short name T887
Test name
Test status
Simulation time 23999127 ps
CPU time 1.12 seconds
Started Feb 18 12:33:34 PM PST 24
Finished Feb 18 12:33:37 PM PST 24
Peak memory 205468 kb
Host smart-84ea71ed-2efc-4894-9d59-f5937e49fd57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453365605 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1453365605
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2841877577
Short name T847
Test name
Test status
Simulation time 32508752 ps
CPU time 2.28 seconds
Started Feb 18 12:33:32 PM PST 24
Finished Feb 18 12:33:38 PM PST 24
Peak memory 213540 kb
Host smart-ee2c6b8c-a968-4d28-971a-f188fe19b263
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841877577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2841877577
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3543354547
Short name T261
Test name
Test status
Simulation time 63083010 ps
CPU time 1.77 seconds
Started Feb 18 12:33:34 PM PST 24
Finished Feb 18 12:33:38 PM PST 24
Peak memory 205384 kb
Host smart-1cc6b605-3b1d-4b2b-af41-b5832c478d52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543354547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3543354547
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.249446689
Short name T843
Test name
Test status
Simulation time 35927355 ps
CPU time 1.84 seconds
Started Feb 18 12:33:38 PM PST 24
Finished Feb 18 12:33:41 PM PST 24
Peak memory 213724 kb
Host smart-0393177b-fe12-4262-8d83-2282f95c1317
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249446689 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.249446689
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1697544411
Short name T226
Test name
Test status
Simulation time 46628158 ps
CPU time 0.85 seconds
Started Feb 18 12:33:36 PM PST 24
Finished Feb 18 12:33:39 PM PST 24
Peak memory 205400 kb
Host smart-1da8a032-8db2-4cc2-bdde-8758b07ce5ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697544411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1697544411
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.412424187
Short name T850
Test name
Test status
Simulation time 24543119 ps
CPU time 0.89 seconds
Started Feb 18 12:33:38 PM PST 24
Finished Feb 18 12:33:41 PM PST 24
Peak memory 205396 kb
Host smart-bf007e8d-a2c0-4a39-96b6-b07f4ee99d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412424187 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.412424187
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.3679711054
Short name T884
Test name
Test status
Simulation time 65889781 ps
CPU time 1.15 seconds
Started Feb 18 12:33:35 PM PST 24
Finished Feb 18 12:33:39 PM PST 24
Peak memory 205476 kb
Host smart-3e7f09a6-674b-4a4f-9416-aa0e489bac8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679711054 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.3679711054
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.774927423
Short name T914
Test name
Test status
Simulation time 69032157 ps
CPU time 2.31 seconds
Started Feb 18 12:33:38 PM PST 24
Finished Feb 18 12:33:42 PM PST 24
Peak memory 213684 kb
Host smart-4794f2fe-aa58-4ea6-8e6c-19529cf4410e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774927423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.774927423
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1780533863
Short name T874
Test name
Test status
Simulation time 182917193 ps
CPU time 2.23 seconds
Started Feb 18 12:33:32 PM PST 24
Finished Feb 18 12:33:37 PM PST 24
Peak memory 205392 kb
Host smart-0f9118f3-c4d3-45a7-8df8-96d448017aa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780533863 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1780533863
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.4115184351
Short name T856
Test name
Test status
Simulation time 22455990 ps
CPU time 1.66 seconds
Started Feb 18 12:33:35 PM PST 24
Finished Feb 18 12:33:40 PM PST 24
Peak memory 213728 kb
Host smart-966f3706-4076-4ebf-bb32-bf59ecb0cc72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115184351 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.4115184351
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3352955962
Short name T249
Test name
Test status
Simulation time 18205796 ps
CPU time 0.79 seconds
Started Feb 18 12:33:36 PM PST 24
Finished Feb 18 12:33:39 PM PST 24
Peak memory 205280 kb
Host smart-3bfbd15f-4b6b-4a92-8f5d-34e2621ee064
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352955962 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3352955962
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2200815754
Short name T954
Test name
Test status
Simulation time 17382721 ps
CPU time 0.93 seconds
Started Feb 18 12:33:32 PM PST 24
Finished Feb 18 12:33:36 PM PST 24
Peak memory 205332 kb
Host smart-67e45364-800c-4a53-a071-75e4fc5af721
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200815754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2200815754
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2287866486
Short name T898
Test name
Test status
Simulation time 31733719 ps
CPU time 1.11 seconds
Started Feb 18 12:33:34 PM PST 24
Finished Feb 18 12:33:37 PM PST 24
Peak memory 205496 kb
Host smart-3964f0fb-79da-43f0-8b17-14811f404292
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287866486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2287866486
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.804277078
Short name T888
Test name
Test status
Simulation time 256934228 ps
CPU time 3.2 seconds
Started Feb 18 12:33:37 PM PST 24
Finished Feb 18 12:33:43 PM PST 24
Peak memory 213784 kb
Host smart-acfe6e79-da57-453b-a913-c203aa498cbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804277078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.804277078
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1100250573
Short name T250
Test name
Test status
Simulation time 90071733 ps
CPU time 2.4 seconds
Started Feb 18 12:33:31 PM PST 24
Finished Feb 18 12:33:37 PM PST 24
Peak memory 205504 kb
Host smart-51a0bfe6-5f80-4c05-93c8-fb4a9f860ed2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100250573 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1100250573
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.920041682
Short name T916
Test name
Test status
Simulation time 411200864 ps
CPU time 3.44 seconds
Started Feb 18 12:33:41 PM PST 24
Finished Feb 18 12:33:45 PM PST 24
Peak memory 213632 kb
Host smart-e482a0c5-800b-4fef-8415-6d66587c3fd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920041682 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.920041682
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3372870076
Short name T235
Test name
Test status
Simulation time 46493802 ps
CPU time 0.85 seconds
Started Feb 18 12:33:43 PM PST 24
Finished Feb 18 12:33:46 PM PST 24
Peak memory 205264 kb
Host smart-7c460dc9-3b36-45e7-9849-d4eb8a0f6f93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372870076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3372870076
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2646649661
Short name T870
Test name
Test status
Simulation time 16028086 ps
CPU time 0.8 seconds
Started Feb 18 12:33:47 PM PST 24
Finished Feb 18 12:33:51 PM PST 24
Peak memory 205316 kb
Host smart-7a659a99-ca26-4049-ac93-f87e546f035b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646649661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2646649661
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1117461799
Short name T878
Test name
Test status
Simulation time 19594309 ps
CPU time 1.18 seconds
Started Feb 18 12:33:45 PM PST 24
Finished Feb 18 12:33:49 PM PST 24
Peak memory 205408 kb
Host smart-2a1c0be6-78fd-4be7-9620-bd0ff15bbb74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117461799 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1117461799
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2197767986
Short name T923
Test name
Test status
Simulation time 503445830 ps
CPU time 4.95 seconds
Started Feb 18 12:33:38 PM PST 24
Finished Feb 18 12:33:44 PM PST 24
Peak memory 213804 kb
Host smart-b07b92d5-de78-4443-a613-8a72967fd845
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197767986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2197767986
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2177943176
Short name T897
Test name
Test status
Simulation time 88349653 ps
CPU time 2.28 seconds
Started Feb 18 12:33:43 PM PST 24
Finished Feb 18 12:33:46 PM PST 24
Peak memory 205456 kb
Host smart-4261305e-6d4b-4f4f-af78-d6abbbf4202c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177943176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2177943176
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.1127205339
Short name T430
Test name
Test status
Simulation time 15903342 ps
CPU time 0.94 seconds
Started Feb 18 03:14:00 PM PST 24
Finished Feb 18 03:14:05 PM PST 24
Peak memory 206256 kb
Host smart-bc93e2b9-7235-4f39-b292-2d7c8c1da1d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127205339 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1127205339
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.1729823671
Short name T114
Test name
Test status
Simulation time 87693916 ps
CPU time 0.84 seconds
Started Feb 18 03:14:02 PM PST 24
Finished Feb 18 03:14:08 PM PST 24
Peak memory 215252 kb
Host smart-177d8e3e-0a3b-4849-bb4a-ed97110ced41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729823671 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.1729823671
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.2750850893
Short name T115
Test name
Test status
Simulation time 45740742 ps
CPU time 1.15 seconds
Started Feb 18 03:14:02 PM PST 24
Finished Feb 18 03:14:10 PM PST 24
Peak memory 218620 kb
Host smart-3655b463-21db-46bc-a6a3-9185244a1cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750850893 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2750850893
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.3529333811
Short name T598
Test name
Test status
Simulation time 35070679 ps
CPU time 1.3 seconds
Started Feb 18 03:14:01 PM PST 24
Finished Feb 18 03:14:07 PM PST 24
Peak memory 216360 kb
Host smart-e7daf2a4-58ce-4e89-87c7-774e30567521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529333811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3529333811
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.1949797072
Short name T119
Test name
Test status
Simulation time 35813553 ps
CPU time 0.89 seconds
Started Feb 18 03:14:03 PM PST 24
Finished Feb 18 03:14:14 PM PST 24
Peak memory 214884 kb
Host smart-ec65f1f7-0d15-4eb5-bf8f-ce3aba7318be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949797072 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1949797072
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.2402455757
Short name T299
Test name
Test status
Simulation time 15698553 ps
CPU time 1 seconds
Started Feb 18 03:14:02 PM PST 24
Finished Feb 18 03:14:08 PM PST 24
Peak memory 206536 kb
Host smart-d1aca2d2-2534-421e-96ea-f7edaf3d6eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402455757 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2402455757
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2009843752
Short name T42
Test name
Test status
Simulation time 532855723 ps
CPU time 8.38 seconds
Started Feb 18 03:14:05 PM PST 24
Finished Feb 18 03:14:24 PM PST 24
Peak memory 234520 kb
Host smart-2012771d-ff20-4139-851f-e46d1231c122
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009843752 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2009843752
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.4261099184
Short name T311
Test name
Test status
Simulation time 133823241 ps
CPU time 0.88 seconds
Started Feb 18 03:14:01 PM PST 24
Finished Feb 18 03:14:05 PM PST 24
Peak memory 214528 kb
Host smart-e658fb9e-39f8-49ad-b7ed-523b1974ceec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261099184 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.4261099184
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.669321832
Short name T334
Test name
Test status
Simulation time 347041065 ps
CPU time 4.12 seconds
Started Feb 18 03:14:01 PM PST 24
Finished Feb 18 03:14:10 PM PST 24
Peak memory 215840 kb
Host smart-80debc49-14ba-4f46-8256-d17d6f11d135
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669321832 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.669321832
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert.1754482823
Short name T620
Test name
Test status
Simulation time 103512599 ps
CPU time 1.24 seconds
Started Feb 18 03:14:02 PM PST 24
Finished Feb 18 03:14:11 PM PST 24
Peak memory 215020 kb
Host smart-2959a421-e0f6-41cb-bad1-46e9e681d259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754482823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1754482823
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1807215855
Short name T540
Test name
Test status
Simulation time 26364869 ps
CPU time 1.05 seconds
Started Feb 18 03:14:05 PM PST 24
Finished Feb 18 03:14:18 PM PST 24
Peak memory 206268 kb
Host smart-ab49ba12-498f-41f7-9eb2-46a9d5f2c012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807215855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1807215855
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_err.2526851327
Short name T530
Test name
Test status
Simulation time 18947229 ps
CPU time 1.05 seconds
Started Feb 18 03:14:07 PM PST 24
Finished Feb 18 03:14:20 PM PST 24
Peak memory 217552 kb
Host smart-fb2f6f92-8b37-45b1-b251-dbcb580283c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526851327 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2526851327
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3081924342
Short name T143
Test name
Test status
Simulation time 24712018 ps
CPU time 1.13 seconds
Started Feb 18 03:14:02 PM PST 24
Finished Feb 18 03:14:08 PM PST 24
Peak memory 216008 kb
Host smart-fe832cd0-b2c3-42ea-b348-b1badd4ee8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081924342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3081924342
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.998332091
Short name T636
Test name
Test status
Simulation time 22616949 ps
CPU time 1.1 seconds
Started Feb 18 03:14:04 PM PST 24
Finished Feb 18 03:14:16 PM PST 24
Peak memory 215168 kb
Host smart-213d5851-8622-4af4-bc25-440156331749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998332091 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.998332091
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.908953400
Short name T18
Test name
Test status
Simulation time 1444602830 ps
CPU time 6.29 seconds
Started Feb 18 03:14:10 PM PST 24
Finished Feb 18 03:14:27 PM PST 24
Peak memory 236024 kb
Host smart-bd96936f-719d-4c1b-8bbd-944f4d5539f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908953400 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.908953400
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.190751172
Short name T211
Test name
Test status
Simulation time 22304324 ps
CPU time 1.04 seconds
Started Feb 18 03:14:04 PM PST 24
Finished Feb 18 03:14:16 PM PST 24
Peak memory 214664 kb
Host smart-fe0cec40-448f-4788-8c4d-4ce9c8ccc07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190751172 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.190751172
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.600460512
Short name T371
Test name
Test status
Simulation time 166448001 ps
CPU time 3.62 seconds
Started Feb 18 03:14:02 PM PST 24
Finished Feb 18 03:14:13 PM PST 24
Peak memory 218620 kb
Host smart-28b31fdd-6515-4330-b408-e16906e97869
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600460512 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.600460512
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1425835313
Short name T199
Test name
Test status
Simulation time 343951075381 ps
CPU time 1981.46 seconds
Started Feb 18 03:14:03 PM PST 24
Finished Feb 18 03:47:13 PM PST 24
Peak memory 224504 kb
Host smart-3e27edd0-1040-459e-96ef-ec0de699b542
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425835313 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1425835313
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.2336485198
Short name T668
Test name
Test status
Simulation time 23023422 ps
CPU time 0.88 seconds
Started Feb 18 03:14:52 PM PST 24
Finished Feb 18 03:15:02 PM PST 24
Peak memory 206248 kb
Host smart-9056e0bc-7806-4b8a-b387-18fea853c976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336485198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2336485198
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.1541134899
Short name T740
Test name
Test status
Simulation time 18438235 ps
CPU time 0.84 seconds
Started Feb 18 03:14:44 PM PST 24
Finished Feb 18 03:14:53 PM PST 24
Peak memory 214964 kb
Host smart-54635212-e85d-4740-93d3-1dd9a11e5dcf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541134899 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.1541134899
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1210817035
Short name T73
Test name
Test status
Simulation time 93547823 ps
CPU time 1.07 seconds
Started Feb 18 03:15:06 PM PST 24
Finished Feb 18 03:15:15 PM PST 24
Peak memory 217472 kb
Host smart-f97d036e-825b-4c0c-96dc-cf65226243e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210817035 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1210817035
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.3829116115
Short name T169
Test name
Test status
Simulation time 258616847 ps
CPU time 1.11 seconds
Started Feb 18 03:14:43 PM PST 24
Finished Feb 18 03:14:52 PM PST 24
Peak memory 218800 kb
Host smart-2896cd00-307a-431e-937f-22d3161b8a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829116115 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3829116115
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1651835360
Short name T280
Test name
Test status
Simulation time 35207033 ps
CPU time 1.32 seconds
Started Feb 18 03:14:43 PM PST 24
Finished Feb 18 03:14:52 PM PST 24
Peak memory 214708 kb
Host smart-661e5381-29ff-441a-ab8c-1e2c28c2cc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651835360 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1651835360
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.1647823924
Short name T27
Test name
Test status
Simulation time 62068709 ps
CPU time 0.97 seconds
Started Feb 18 03:14:49 PM PST 24
Finished Feb 18 03:14:57 PM PST 24
Peak memory 222368 kb
Host smart-58c5e216-fc00-4801-9b46-6697b3c389b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647823924 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1647823924
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2193243053
Short name T318
Test name
Test status
Simulation time 17667116 ps
CPU time 1.09 seconds
Started Feb 18 03:14:44 PM PST 24
Finished Feb 18 03:14:52 PM PST 24
Peak memory 214732 kb
Host smart-5251a36a-370e-4472-baf7-e361d55a1692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193243053 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2193243053
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.4102206240
Short name T423
Test name
Test status
Simulation time 714271198 ps
CPU time 4.04 seconds
Started Feb 18 03:14:43 PM PST 24
Finished Feb 18 03:14:55 PM PST 24
Peak memory 218612 kb
Host smart-624d468a-d7e2-4b04-82f8-b348d27098b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102206240 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.4102206240
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.736502402
Short name T603
Test name
Test status
Simulation time 218058135337 ps
CPU time 2097.01 seconds
Started Feb 18 03:14:43 PM PST 24
Finished Feb 18 03:49:48 PM PST 24
Peak memory 226472 kb
Host smart-1c0a9ecd-0083-4833-9445-7cfac04b6ad3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736502402 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.736502402
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.3625489970
Short name T690
Test name
Test status
Simulation time 26774032 ps
CPU time 1.22 seconds
Started Feb 18 03:17:15 PM PST 24
Finished Feb 18 03:17:20 PM PST 24
Peak memory 217168 kb
Host smart-e45c159e-60b0-4ce1-a3b7-a7cdf1426067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625489970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.3625489970
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.508245497
Short name T488
Test name
Test status
Simulation time 69518393 ps
CPU time 2.46 seconds
Started Feb 18 03:17:15 PM PST 24
Finished Feb 18 03:17:21 PM PST 24
Peak memory 218844 kb
Host smart-5e92c1e6-e015-480c-8cba-a532979d0ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508245497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.508245497
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.1432936333
Short name T800
Test name
Test status
Simulation time 67685921 ps
CPU time 1.17 seconds
Started Feb 18 03:17:13 PM PST 24
Finished Feb 18 03:17:17 PM PST 24
Peak memory 217796 kb
Host smart-bcf380e9-a31e-41e3-94fc-87331fb54d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432936333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1432936333
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3687913324
Short name T654
Test name
Test status
Simulation time 52077102 ps
CPU time 1.37 seconds
Started Feb 18 03:17:14 PM PST 24
Finished Feb 18 03:17:19 PM PST 24
Peak memory 217456 kb
Host smart-53b45318-78cf-473b-97a7-10fe4c92e8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687913324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3687913324
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.943024710
Short name T714
Test name
Test status
Simulation time 54732780 ps
CPU time 1.39 seconds
Started Feb 18 03:17:15 PM PST 24
Finished Feb 18 03:17:20 PM PST 24
Peak memory 217068 kb
Host smart-7386a638-9a60-441b-ab6e-2bd97ff9d4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943024710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.943024710
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.2141623458
Short name T770
Test name
Test status
Simulation time 47970873 ps
CPU time 1.15 seconds
Started Feb 18 03:17:13 PM PST 24
Finished Feb 18 03:17:17 PM PST 24
Peak memory 215948 kb
Host smart-c5f12ee7-fb1a-4d03-ad6f-274aca6445de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141623458 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.2141623458
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1866720894
Short name T523
Test name
Test status
Simulation time 36464988 ps
CPU time 1.18 seconds
Started Feb 18 03:17:16 PM PST 24
Finished Feb 18 03:17:22 PM PST 24
Peak memory 216044 kb
Host smart-a55dcc49-b57b-4c3f-9cea-10456e02e33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866720894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1866720894
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.3749067964
Short name T713
Test name
Test status
Simulation time 55785426 ps
CPU time 1.32 seconds
Started Feb 18 03:17:11 PM PST 24
Finished Feb 18 03:17:14 PM PST 24
Peak memory 216444 kb
Host smart-c9588f6c-03d6-4ad0-9706-6b07d84b488e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749067964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.3749067964
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.1019030354
Short name T708
Test name
Test status
Simulation time 132503644 ps
CPU time 1.63 seconds
Started Feb 18 03:17:16 PM PST 24
Finished Feb 18 03:17:22 PM PST 24
Peak memory 218900 kb
Host smart-a34489a5-9040-4b40-a363-f1846047b037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019030354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1019030354
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.2261066863
Short name T46
Test name
Test status
Simulation time 43881357 ps
CPU time 1.06 seconds
Started Feb 18 03:15:03 PM PST 24
Finished Feb 18 03:15:12 PM PST 24
Peak memory 205456 kb
Host smart-9341d3bb-7d25-4d5d-adb9-77cf083ba7b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261066863 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2261066863
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.296005047
Short name T91
Test name
Test status
Simulation time 37594057 ps
CPU time 0.87 seconds
Started Feb 18 03:14:52 PM PST 24
Finished Feb 18 03:15:03 PM PST 24
Peak memory 214832 kb
Host smart-a629ffce-d398-48df-afad-884af5a0977f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296005047 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.296005047
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.1733497706
Short name T372
Test name
Test status
Simulation time 99433870 ps
CPU time 1.14 seconds
Started Feb 18 03:15:03 PM PST 24
Finished Feb 18 03:15:12 PM PST 24
Peak memory 216940 kb
Host smart-de842f16-ab70-40d2-bd0c-a68185923b53
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733497706 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.1733497706
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.2819663552
Short name T100
Test name
Test status
Simulation time 45042542 ps
CPU time 1.15 seconds
Started Feb 18 03:14:57 PM PST 24
Finished Feb 18 03:15:07 PM PST 24
Peak memory 218576 kb
Host smart-733c1d6f-803c-44f0-a06f-61495bac76c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819663552 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2819663552
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.2562859321
Short name T724
Test name
Test status
Simulation time 69535767 ps
CPU time 1.2 seconds
Started Feb 18 03:15:04 PM PST 24
Finished Feb 18 03:15:13 PM PST 24
Peak memory 217392 kb
Host smart-4472cf79-e5cc-4a3e-8b84-7ec2adc998ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562859321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2562859321
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.575950379
Short name T752
Test name
Test status
Simulation time 20826215 ps
CPU time 1.03 seconds
Started Feb 18 03:14:47 PM PST 24
Finished Feb 18 03:14:55 PM PST 24
Peak memory 214856 kb
Host smart-703719e5-2825-43c3-839c-46ba81927617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575950379 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.575950379
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.4283061294
Short name T435
Test name
Test status
Simulation time 17098533 ps
CPU time 1.02 seconds
Started Feb 18 03:14:55 PM PST 24
Finished Feb 18 03:15:06 PM PST 24
Peak memory 214708 kb
Host smart-0b5f091d-7619-4080-a9a6-59efff38fb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283061294 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.4283061294
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2928244671
Short name T466
Test name
Test status
Simulation time 268717182 ps
CPU time 3.19 seconds
Started Feb 18 03:14:53 PM PST 24
Finished Feb 18 03:15:06 PM PST 24
Peak memory 214736 kb
Host smart-b1054ddd-cd33-4b69-9168-fcbe9dd20ee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928244671 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2928244671
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2006443508
Short name T791
Test name
Test status
Simulation time 38173326305 ps
CPU time 860.03 seconds
Started Feb 18 03:14:51 PM PST 24
Finished Feb 18 03:29:20 PM PST 24
Peak memory 217624 kb
Host smart-25a67c24-4ac1-4421-a63c-bcbab7ab86a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006443508 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2006443508
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.3788282280
Short name T427
Test name
Test status
Simulation time 32348717 ps
CPU time 1.36 seconds
Started Feb 18 03:17:16 PM PST 24
Finished Feb 18 03:17:23 PM PST 24
Peak memory 217640 kb
Host smart-18a0d97e-10ae-474f-8688-4b3284dad970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788282280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3788282280
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.1061652128
Short name T696
Test name
Test status
Simulation time 38571313 ps
CPU time 1.3 seconds
Started Feb 18 03:17:06 PM PST 24
Finished Feb 18 03:17:11 PM PST 24
Peak memory 215792 kb
Host smart-8413f0a2-6545-4e3f-b113-0c7a9ec14255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061652128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1061652128
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2164828355
Short name T179
Test name
Test status
Simulation time 103348645 ps
CPU time 1.43 seconds
Started Feb 18 03:17:14 PM PST 24
Finished Feb 18 03:17:19 PM PST 24
Peak memory 217172 kb
Host smart-568ed83c-8cce-4b81-a67e-4444a212a150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164828355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2164828355
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.4071495278
Short name T363
Test name
Test status
Simulation time 41917374 ps
CPU time 1.23 seconds
Started Feb 18 03:17:16 PM PST 24
Finished Feb 18 03:17:23 PM PST 24
Peak memory 218220 kb
Host smart-7475835b-af5e-400d-b6ca-97c5aa334c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071495278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.4071495278
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.3091872342
Short name T694
Test name
Test status
Simulation time 102877441 ps
CPU time 1.48 seconds
Started Feb 18 03:17:06 PM PST 24
Finished Feb 18 03:17:12 PM PST 24
Peak memory 217420 kb
Host smart-3266846f-702e-4f32-9d8d-88eda5458a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091872342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3091872342
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.1832003750
Short name T683
Test name
Test status
Simulation time 40054823 ps
CPU time 1.51 seconds
Started Feb 18 03:17:13 PM PST 24
Finished Feb 18 03:17:17 PM PST 24
Peak memory 215992 kb
Host smart-20bb075c-929a-41be-993b-c41f3433fbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832003750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1832003750
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.852374380
Short name T275
Test name
Test status
Simulation time 55361984 ps
CPU time 1.24 seconds
Started Feb 18 03:17:13 PM PST 24
Finished Feb 18 03:17:17 PM PST 24
Peak memory 217332 kb
Host smart-d7f5fa71-5889-46ed-8cfb-df4ab94e56d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852374380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.852374380
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.2259384187
Short name T476
Test name
Test status
Simulation time 347602808 ps
CPU time 3.52 seconds
Started Feb 18 03:17:14 PM PST 24
Finished Feb 18 03:17:21 PM PST 24
Peak memory 217356 kb
Host smart-4da50634-661b-4884-951a-d14d62367887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259384187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2259384187
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.2146328206
Short name T330
Test name
Test status
Simulation time 236764942 ps
CPU time 1.08 seconds
Started Feb 18 03:17:13 PM PST 24
Finished Feb 18 03:17:18 PM PST 24
Peak memory 215800 kb
Host smart-11c8fc92-9c82-4e13-93df-89152a758334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146328206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.2146328206
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.2184358532
Short name T181
Test name
Test status
Simulation time 97415496 ps
CPU time 1.21 seconds
Started Feb 18 03:15:08 PM PST 24
Finished Feb 18 03:15:21 PM PST 24
Peak memory 215060 kb
Host smart-aefe061f-6a62-432c-88c8-40eb278aaace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184358532 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.2184358532
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3868822728
Short name T584
Test name
Test status
Simulation time 32943401 ps
CPU time 0.91 seconds
Started Feb 18 03:14:54 PM PST 24
Finished Feb 18 03:15:05 PM PST 24
Peak memory 206220 kb
Host smart-be96181b-784e-4dc1-afeb-7908a72b67dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868822728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3868822728
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.1184684559
Short name T189
Test name
Test status
Simulation time 37731061 ps
CPU time 0.85 seconds
Started Feb 18 03:15:02 PM PST 24
Finished Feb 18 03:15:11 PM PST 24
Peak memory 214896 kb
Host smart-e7918f8b-1bf6-4242-a514-47fab100ac1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184684559 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1184684559
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.2976537422
Short name T339
Test name
Test status
Simulation time 115649708 ps
CPU time 1.17 seconds
Started Feb 18 03:15:00 PM PST 24
Finished Feb 18 03:15:09 PM PST 24
Peak memory 215864 kb
Host smart-025459aa-26f0-4b2d-8ff4-aeca8daf1ba5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976537422 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.2976537422
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.2578361010
Short name T465
Test name
Test status
Simulation time 21119732 ps
CPU time 1.05 seconds
Started Feb 18 03:15:06 PM PST 24
Finished Feb 18 03:15:15 PM PST 24
Peak memory 217208 kb
Host smart-3574fd67-09d7-4c5e-a6c2-5306b6b4dcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578361010 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2578361010
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2120266065
Short name T524
Test name
Test status
Simulation time 242106826 ps
CPU time 1.47 seconds
Started Feb 18 03:15:05 PM PST 24
Finished Feb 18 03:15:15 PM PST 24
Peak memory 217788 kb
Host smart-6e652556-3f3e-4004-92e4-03fb4c10f9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120266065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2120266065
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3912626557
Short name T529
Test name
Test status
Simulation time 27942034 ps
CPU time 1.06 seconds
Started Feb 18 03:15:05 PM PST 24
Finished Feb 18 03:15:14 PM PST 24
Peak memory 222548 kb
Host smart-0d9cb54c-55e6-476c-ad2f-5048755e1fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912626557 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3912626557
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.2909845373
Short name T753
Test name
Test status
Simulation time 18220922 ps
CPU time 1 seconds
Started Feb 18 03:14:57 PM PST 24
Finished Feb 18 03:15:08 PM PST 24
Peak memory 214744 kb
Host smart-3524cac0-71b7-4d55-8078-2b47ef4c987f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909845373 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.2909845373
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.1560839118
Short name T4
Test name
Test status
Simulation time 115257869 ps
CPU time 2.68 seconds
Started Feb 18 03:15:05 PM PST 24
Finished Feb 18 03:15:15 PM PST 24
Peak memory 216096 kb
Host smart-d05add61-42e9-456f-8af2-296d19ed319f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560839118 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.1560839118
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.501318142
Short name T426
Test name
Test status
Simulation time 63167229482 ps
CPU time 463.86 seconds
Started Feb 18 03:15:07 PM PST 24
Finished Feb 18 03:23:00 PM PST 24
Peak memory 218488 kb
Host smart-d99b18d8-c4c0-493a-a72b-5d39a9cb2a1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501318142 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.501318142
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.1463960004
Short name T503
Test name
Test status
Simulation time 86254904 ps
CPU time 1.23 seconds
Started Feb 18 03:17:18 PM PST 24
Finished Feb 18 03:17:23 PM PST 24
Peak memory 218180 kb
Host smart-c0b17627-3530-476f-b2a3-0f60b83ab2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463960004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1463960004
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.1273509191
Short name T393
Test name
Test status
Simulation time 47451365 ps
CPU time 1.16 seconds
Started Feb 18 03:17:18 PM PST 24
Finished Feb 18 03:17:23 PM PST 24
Peak memory 217396 kb
Host smart-285413e4-8cf5-4adb-a242-d78ea45c0d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273509191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.1273509191
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2913626980
Short name T602
Test name
Test status
Simulation time 66856732 ps
CPU time 1.31 seconds
Started Feb 18 03:17:07 PM PST 24
Finished Feb 18 03:17:11 PM PST 24
Peak memory 217424 kb
Host smart-7c99ec65-d2d4-46bc-8741-f1e4339000f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913626980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2913626980
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.1553565793
Short name T793
Test name
Test status
Simulation time 72497120 ps
CPU time 2.11 seconds
Started Feb 18 03:17:16 PM PST 24
Finished Feb 18 03:17:22 PM PST 24
Peak memory 219016 kb
Host smart-e30f45f5-5cb2-4167-b208-65dc5ccb2338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553565793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1553565793
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.1595156932
Short name T421
Test name
Test status
Simulation time 72704275 ps
CPU time 1.12 seconds
Started Feb 18 03:17:14 PM PST 24
Finished Feb 18 03:17:19 PM PST 24
Peak memory 216980 kb
Host smart-66484bf6-d49f-4d34-ad03-23b842e3cd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595156932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1595156932
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.1396683071
Short name T732
Test name
Test status
Simulation time 49217860 ps
CPU time 1.42 seconds
Started Feb 18 03:17:16 PM PST 24
Finished Feb 18 03:17:23 PM PST 24
Peak memory 217096 kb
Host smart-8904c427-519d-4942-b3c0-8f642c4a0dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396683071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1396683071
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.1545819952
Short name T491
Test name
Test status
Simulation time 72514254 ps
CPU time 1.14 seconds
Started Feb 18 03:17:11 PM PST 24
Finished Feb 18 03:17:14 PM PST 24
Peak memory 215948 kb
Host smart-3d36e416-83ec-462c-8b26-0370e5492af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545819952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1545819952
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.4244365626
Short name T531
Test name
Test status
Simulation time 76200897 ps
CPU time 1.27 seconds
Started Feb 18 03:17:19 PM PST 24
Finished Feb 18 03:17:28 PM PST 24
Peak memory 218700 kb
Host smart-f531c90c-279e-4925-99ac-cd10c1e3918c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244365626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.4244365626
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1318814167
Short name T498
Test name
Test status
Simulation time 27286520 ps
CPU time 1.34 seconds
Started Feb 18 03:15:00 PM PST 24
Finished Feb 18 03:15:09 PM PST 24
Peak memory 215076 kb
Host smart-e1658f7b-1ed8-427d-b95c-dd3b9c022148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318814167 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1318814167
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.2641750021
Short name T806
Test name
Test status
Simulation time 31918024 ps
CPU time 0.99 seconds
Started Feb 18 03:15:07 PM PST 24
Finished Feb 18 03:15:17 PM PST 24
Peak memory 206252 kb
Host smart-7e768e9a-0b75-4f27-8ad8-860632a9b4c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641750021 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2641750021
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.2166777427
Short name T727
Test name
Test status
Simulation time 21374115 ps
CPU time 0.87 seconds
Started Feb 18 03:15:11 PM PST 24
Finished Feb 18 03:15:24 PM PST 24
Peak memory 214840 kb
Host smart-09eb25e7-d44e-49bd-b926-d8002c3c5390
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166777427 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2166777427
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.224704898
Short name T415
Test name
Test status
Simulation time 77480703 ps
CPU time 1.08 seconds
Started Feb 18 03:15:01 PM PST 24
Finished Feb 18 03:15:11 PM PST 24
Peak memory 217196 kb
Host smart-e7244c8c-7c53-49c0-9d4a-4c17b9ec6e6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224704898 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.224704898
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1814679263
Short name T622
Test name
Test status
Simulation time 57985659 ps
CPU time 0.95 seconds
Started Feb 18 03:15:10 PM PST 24
Finished Feb 18 03:15:23 PM PST 24
Peak memory 217448 kb
Host smart-3d7db50e-cd9f-4605-b9f0-dcf0da25bfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814679263 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1814679263
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1471662736
Short name T353
Test name
Test status
Simulation time 68296762 ps
CPU time 1.05 seconds
Started Feb 18 03:15:01 PM PST 24
Finished Feb 18 03:15:11 PM PST 24
Peak memory 215964 kb
Host smart-0569fdc3-aef4-4f7c-a82d-7d5cf8169001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471662736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1471662736
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3137796346
Short name T774
Test name
Test status
Simulation time 31275771 ps
CPU time 0.91 seconds
Started Feb 18 03:15:06 PM PST 24
Finished Feb 18 03:15:15 PM PST 24
Peak memory 214784 kb
Host smart-0d171c1a-07c7-4d3e-8930-526d4f6941d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137796346 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3137796346
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.910710542
Short name T756
Test name
Test status
Simulation time 31342134 ps
CPU time 1.04 seconds
Started Feb 18 03:15:05 PM PST 24
Finished Feb 18 03:15:14 PM PST 24
Peak memory 214704 kb
Host smart-535eda6a-7a03-45fb-994e-6e7490bb9e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910710542 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.910710542
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.450903967
Short name T479
Test name
Test status
Simulation time 75534520 ps
CPU time 0.99 seconds
Started Feb 18 03:15:06 PM PST 24
Finished Feb 18 03:15:16 PM PST 24
Peak memory 205280 kb
Host smart-08413646-a2bf-4d28-8851-a7a44f614b2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450903967 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.450903967
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.724734836
Short name T482
Test name
Test status
Simulation time 64753529081 ps
CPU time 1480.23 seconds
Started Feb 18 03:15:06 PM PST 24
Finished Feb 18 03:39:55 PM PST 24
Peak memory 222456 kb
Host smart-6724a0e4-fbc8-43ed-ad7b-8626edc5dad5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724734836 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.724734836
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.2257174619
Short name T720
Test name
Test status
Simulation time 32210411 ps
CPU time 1.13 seconds
Started Feb 18 03:17:24 PM PST 24
Finished Feb 18 03:17:33 PM PST 24
Peak memory 215916 kb
Host smart-a5d71ea4-72f4-44dd-b2d2-2a78c5306615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257174619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2257174619
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.259617634
Short name T477
Test name
Test status
Simulation time 32992861 ps
CPU time 1.24 seconds
Started Feb 18 03:17:18 PM PST 24
Finished Feb 18 03:17:23 PM PST 24
Peak memory 214748 kb
Host smart-e430e6c7-25b5-4a46-87d3-8fc708378b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259617634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.259617634
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.1204285055
Short name T659
Test name
Test status
Simulation time 94329413 ps
CPU time 1.25 seconds
Started Feb 18 03:17:15 PM PST 24
Finished Feb 18 03:17:20 PM PST 24
Peak memory 217152 kb
Host smart-dc59f570-197e-4883-aca4-74bdefb0134e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204285055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.1204285055
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.791090374
Short name T611
Test name
Test status
Simulation time 109337670 ps
CPU time 1.58 seconds
Started Feb 18 03:17:19 PM PST 24
Finished Feb 18 03:17:27 PM PST 24
Peak memory 217100 kb
Host smart-079ba942-0663-4239-9463-39999a540e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791090374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.791090374
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.771693677
Short name T606
Test name
Test status
Simulation time 49031389 ps
CPU time 1.38 seconds
Started Feb 18 03:17:21 PM PST 24
Finished Feb 18 03:17:31 PM PST 24
Peak memory 214708 kb
Host smart-888c7398-651a-4adc-a177-5b11b3ff2514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771693677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.771693677
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.1974723173
Short name T397
Test name
Test status
Simulation time 61176265 ps
CPU time 1.28 seconds
Started Feb 18 03:17:15 PM PST 24
Finished Feb 18 03:17:20 PM PST 24
Peak memory 218148 kb
Host smart-e2cd0860-bd6b-436e-bd99-b0b5dd3c444d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974723173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.1974723173
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1517458629
Short name T596
Test name
Test status
Simulation time 74688593 ps
CPU time 1.3 seconds
Started Feb 18 03:17:16 PM PST 24
Finished Feb 18 03:17:22 PM PST 24
Peak memory 217664 kb
Host smart-badd8018-88e0-49f3-99c5-90ec4a572600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517458629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1517458629
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.1794478227
Short name T665
Test name
Test status
Simulation time 88552816 ps
CPU time 1.75 seconds
Started Feb 18 03:17:17 PM PST 24
Finished Feb 18 03:17:23 PM PST 24
Peak memory 218072 kb
Host smart-f6067461-aa9d-4561-a6f1-6104ea3dd464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794478227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1794478227
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.1785038488
Short name T322
Test name
Test status
Simulation time 100379784 ps
CPU time 1.36 seconds
Started Feb 18 03:17:20 PM PST 24
Finished Feb 18 03:17:30 PM PST 24
Peak memory 217224 kb
Host smart-cba0e6ca-4939-436b-8724-7765c434c7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785038488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1785038488
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert_test.2152930097
Short name T509
Test name
Test status
Simulation time 38776340 ps
CPU time 0.86 seconds
Started Feb 18 03:14:59 PM PST 24
Finished Feb 18 03:15:08 PM PST 24
Peak memory 205688 kb
Host smart-261e068f-8373-42ad-af2f-ac8d04255d66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152930097 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2152930097
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.831230187
Short name T187
Test name
Test status
Simulation time 38858962 ps
CPU time 0.82 seconds
Started Feb 18 03:14:55 PM PST 24
Finished Feb 18 03:15:06 PM PST 24
Peak memory 215228 kb
Host smart-8456dafa-6f3d-4d47-bfd7-c019a09b1a2e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831230187 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.831230187
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.983065167
Short name T647
Test name
Test status
Simulation time 19143289 ps
CPU time 0.99 seconds
Started Feb 18 03:15:06 PM PST 24
Finished Feb 18 03:15:15 PM PST 24
Peak memory 217568 kb
Host smart-f2e7e5a6-ff5d-4fa0-ba15-7108668e961f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983065167 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.983065167
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2323095485
Short name T815
Test name
Test status
Simulation time 54054634 ps
CPU time 1.95 seconds
Started Feb 18 03:15:05 PM PST 24
Finished Feb 18 03:15:14 PM PST 24
Peak memory 217508 kb
Host smart-e4cae5bf-983d-4acb-aab1-0efb24cdab37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323095485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2323095485
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2974148262
Short name T784
Test name
Test status
Simulation time 62567572 ps
CPU time 0.83 seconds
Started Feb 18 03:15:08 PM PST 24
Finished Feb 18 03:15:18 PM PST 24
Peak memory 214988 kb
Host smart-d4e5036f-cc18-49ad-a0c7-9cb3a2f2dc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974148262 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2974148262
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2423016348
Short name T685
Test name
Test status
Simulation time 46117812 ps
CPU time 0.94 seconds
Started Feb 18 03:15:11 PM PST 24
Finished Feb 18 03:15:24 PM PST 24
Peak memory 214740 kb
Host smart-53c4953d-25a1-46dc-bf9a-d11bc5dfb445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423016348 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2423016348
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1255713268
Short name T795
Test name
Test status
Simulation time 403970946 ps
CPU time 1.79 seconds
Started Feb 18 03:15:07 PM PST 24
Finished Feb 18 03:15:18 PM PST 24
Peak memory 215804 kb
Host smart-348a72d8-f4fc-41e5-b748-eeef64970e4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255713268 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1255713268
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3015212396
Short name T468
Test name
Test status
Simulation time 31421415859 ps
CPU time 816.21 seconds
Started Feb 18 03:14:58 PM PST 24
Finished Feb 18 03:28:43 PM PST 24
Peak memory 216644 kb
Host smart-2d4d1887-5472-429b-a3da-19d4c9d09e5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015212396 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3015212396
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.2212262985
Short name T833
Test name
Test status
Simulation time 399480365 ps
CPU time 4.4 seconds
Started Feb 18 03:17:21 PM PST 24
Finished Feb 18 03:17:33 PM PST 24
Peak memory 218928 kb
Host smart-fe6ce077-a049-4236-89ac-bfbc5e71f884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212262985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2212262985
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.878274726
Short name T264
Test name
Test status
Simulation time 35654952 ps
CPU time 1.36 seconds
Started Feb 18 03:17:15 PM PST 24
Finished Feb 18 03:17:21 PM PST 24
Peak memory 218268 kb
Host smart-c7e56fe1-dbc6-4e00-a5e9-5b597628a824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878274726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.878274726
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.3700330947
Short name T781
Test name
Test status
Simulation time 248284272 ps
CPU time 3.77 seconds
Started Feb 18 03:17:16 PM PST 24
Finished Feb 18 03:17:24 PM PST 24
Peak memory 216280 kb
Host smart-520240b2-564f-48ca-8686-e783182b2279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700330947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3700330947
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.1018532823
Short name T44
Test name
Test status
Simulation time 39891260 ps
CPU time 1.71 seconds
Started Feb 18 03:17:18 PM PST 24
Finished Feb 18 03:17:26 PM PST 24
Peak memory 217344 kb
Host smart-d5d66dd8-83a0-487f-b00c-f09d4ce5fd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018532823 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.1018532823
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.3442312650
Short name T805
Test name
Test status
Simulation time 60077612 ps
CPU time 1.42 seconds
Started Feb 18 03:17:18 PM PST 24
Finished Feb 18 03:17:25 PM PST 24
Peak memory 218676 kb
Host smart-e56b6eae-00bc-4812-aa2c-b814c857a615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442312650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3442312650
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.1589956561
Short name T678
Test name
Test status
Simulation time 106619304 ps
CPU time 1.11 seconds
Started Feb 18 03:17:17 PM PST 24
Finished Feb 18 03:17:22 PM PST 24
Peak memory 216132 kb
Host smart-f4384321-fe01-406e-bfda-73827124a3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589956561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.1589956561
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.782686703
Short name T532
Test name
Test status
Simulation time 57040383 ps
CPU time 1.84 seconds
Started Feb 18 03:17:18 PM PST 24
Finished Feb 18 03:17:25 PM PST 24
Peak memory 216116 kb
Host smart-ecfc5b75-b098-44eb-85e9-47ad26972302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782686703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.782686703
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.2271474979
Short name T314
Test name
Test status
Simulation time 224162064 ps
CPU time 1.46 seconds
Started Feb 18 03:17:13 PM PST 24
Finished Feb 18 03:17:17 PM PST 24
Peak memory 217472 kb
Host smart-cf6b3b79-6cfa-4615-bec0-a80565ade106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271474979 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2271474979
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.1101023409
Short name T736
Test name
Test status
Simulation time 91599518 ps
CPU time 2.42 seconds
Started Feb 18 03:17:24 PM PST 24
Finished Feb 18 03:17:34 PM PST 24
Peak memory 216264 kb
Host smart-f7f7b7e7-6531-483f-9a5d-57baaad7d2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101023409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1101023409
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1463044534
Short name T407
Test name
Test status
Simulation time 62208948 ps
CPU time 1.2 seconds
Started Feb 18 03:17:16 PM PST 24
Finished Feb 18 03:17:22 PM PST 24
Peak memory 217168 kb
Host smart-36516a3f-efb8-4c9c-95cf-cba5b9bc7b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463044534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1463044534
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.392160256
Short name T149
Test name
Test status
Simulation time 38374405 ps
CPU time 1.14 seconds
Started Feb 18 03:15:06 PM PST 24
Finished Feb 18 03:15:16 PM PST 24
Peak memory 214964 kb
Host smart-3fa5e865-ae34-4d53-a8cb-9bf9404fd0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392160256 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.392160256
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable.3417090172
Short name T165
Test name
Test status
Simulation time 50952356 ps
CPU time 0.83 seconds
Started Feb 18 03:15:06 PM PST 24
Finished Feb 18 03:15:16 PM PST 24
Peak memory 215092 kb
Host smart-6584b963-3edc-4de0-be5b-109724252bbc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417090172 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3417090172
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1461068256
Short name T85
Test name
Test status
Simulation time 123453369 ps
CPU time 1.35 seconds
Started Feb 18 03:15:07 PM PST 24
Finished Feb 18 03:15:18 PM PST 24
Peak memory 215864 kb
Host smart-526cde06-de84-41a2-94a8-ec669689d8d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461068256 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1461068256
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.4181160718
Short name T74
Test name
Test status
Simulation time 54397673 ps
CPU time 1 seconds
Started Feb 18 03:15:07 PM PST 24
Finished Feb 18 03:15:18 PM PST 24
Peak memory 217244 kb
Host smart-fcd88def-b745-4b0a-9526-f0a82439e0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181160718 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.4181160718
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_intr.2242981434
Short name T726
Test name
Test status
Simulation time 25025085 ps
CPU time 1.03 seconds
Started Feb 18 03:15:09 PM PST 24
Finished Feb 18 03:15:22 PM PST 24
Peak memory 214852 kb
Host smart-d4d0d3a8-6297-4809-90b3-981502d045eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242981434 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2242981434
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1699209269
Short name T687
Test name
Test status
Simulation time 16237567 ps
CPU time 0.96 seconds
Started Feb 18 03:15:07 PM PST 24
Finished Feb 18 03:15:18 PM PST 24
Peak memory 214732 kb
Host smart-2c7eadcb-32ad-4fd1-bc50-251cb6e01f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699209269 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1699209269
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1337945104
Short name T569
Test name
Test status
Simulation time 289967791 ps
CPU time 3.49 seconds
Started Feb 18 03:15:08 PM PST 24
Finished Feb 18 03:15:21 PM PST 24
Peak memory 206596 kb
Host smart-02b6cfd4-3ce6-45e2-b311-070549858c2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337945104 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1337945104
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/150.edn_genbits.55494131
Short name T514
Test name
Test status
Simulation time 66487630 ps
CPU time 1.02 seconds
Started Feb 18 03:17:18 PM PST 24
Finished Feb 18 03:17:24 PM PST 24
Peak memory 215928 kb
Host smart-448ec1bd-7d9b-4ccb-b498-28882d0d2ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55494131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.55494131
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.295992368
Short name T522
Test name
Test status
Simulation time 37895378 ps
CPU time 1.39 seconds
Started Feb 18 03:17:16 PM PST 24
Finished Feb 18 03:17:23 PM PST 24
Peak memory 218044 kb
Host smart-cef6b54d-727c-4118-a435-2cc3004bd0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295992368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.295992368
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.427150227
Short name T564
Test name
Test status
Simulation time 65987639 ps
CPU time 1.33 seconds
Started Feb 18 03:17:15 PM PST 24
Finished Feb 18 03:17:21 PM PST 24
Peak memory 217528 kb
Host smart-a23ca25b-95e2-495c-800f-85871b67910c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427150227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.427150227
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.2749857153
Short name T792
Test name
Test status
Simulation time 39827216 ps
CPU time 1.38 seconds
Started Feb 18 03:17:25 PM PST 24
Finished Feb 18 03:17:33 PM PST 24
Peak memory 217504 kb
Host smart-19dde2fc-33a7-485a-a9b7-c0144b052ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749857153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2749857153
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.3951310273
Short name T316
Test name
Test status
Simulation time 35106502 ps
CPU time 1.41 seconds
Started Feb 18 03:17:17 PM PST 24
Finished Feb 18 03:17:23 PM PST 24
Peak memory 217456 kb
Host smart-7a003025-98b5-4bdd-b1b0-064501ab93a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951310273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3951310273
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.2716233598
Short name T557
Test name
Test status
Simulation time 70069493 ps
CPU time 1.3 seconds
Started Feb 18 03:17:21 PM PST 24
Finished Feb 18 03:17:30 PM PST 24
Peak memory 217468 kb
Host smart-a0246b49-10c4-4fb6-a37b-9cf6b85b44d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716233598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2716233598
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.2958176244
Short name T396
Test name
Test status
Simulation time 248762286 ps
CPU time 1.59 seconds
Started Feb 18 03:17:19 PM PST 24
Finished Feb 18 03:17:27 PM PST 24
Peak memory 218872 kb
Host smart-708c4b08-8f1c-4d42-83c1-8fdc11171500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958176244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2958176244
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.3688843388
Short name T220
Test name
Test status
Simulation time 57737635 ps
CPU time 1.55 seconds
Started Feb 18 03:17:24 PM PST 24
Finished Feb 18 03:17:34 PM PST 24
Peak memory 217488 kb
Host smart-1054ef0c-a977-403f-961d-3d86e4365ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688843388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3688843388
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.3509136107
Short name T651
Test name
Test status
Simulation time 60952288 ps
CPU time 1.66 seconds
Started Feb 18 03:17:25 PM PST 24
Finished Feb 18 03:17:34 PM PST 24
Peak memory 217196 kb
Host smart-7946d8b1-4e3d-41ea-a76a-46a2f5e1c1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509136107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3509136107
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.4088968937
Short name T609
Test name
Test status
Simulation time 24096724 ps
CPU time 1.16 seconds
Started Feb 18 03:17:17 PM PST 24
Finished Feb 18 03:17:23 PM PST 24
Peak memory 216076 kb
Host smart-3b4cb771-38df-40da-90d6-833983c050b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088968937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.4088968937
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3589750873
Short name T599
Test name
Test status
Simulation time 25168329 ps
CPU time 1.16 seconds
Started Feb 18 03:15:06 PM PST 24
Finished Feb 18 03:15:15 PM PST 24
Peak memory 215020 kb
Host smart-111076b3-8830-4d9e-a605-ccb13d24843b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589750873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3589750873
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.3694232865
Short name T224
Test name
Test status
Simulation time 50234900 ps
CPU time 0.92 seconds
Started Feb 18 03:15:15 PM PST 24
Finished Feb 18 03:15:27 PM PST 24
Peak memory 206228 kb
Host smart-ab332720-54e1-46f2-8992-7c8dfa64585f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694232865 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.3694232865
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.4022369645
Short name T368
Test name
Test status
Simulation time 10857779 ps
CPU time 0.89 seconds
Started Feb 18 03:15:07 PM PST 24
Finished Feb 18 03:15:17 PM PST 24
Peak memory 214952 kb
Host smart-2c417326-7a2e-4de9-890c-f8b368ade120
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022369645 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.4022369645
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2252849193
Short name T59
Test name
Test status
Simulation time 121462858 ps
CPU time 1.16 seconds
Started Feb 18 03:15:08 PM PST 24
Finished Feb 18 03:15:21 PM PST 24
Peak memory 215668 kb
Host smart-bd3094b0-5162-4160-88a9-4ec4a31cb256
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252849193 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2252849193
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1832769180
Short name T111
Test name
Test status
Simulation time 31002798 ps
CPU time 0.98 seconds
Started Feb 18 03:15:05 PM PST 24
Finished Feb 18 03:15:14 PM PST 24
Peak memory 222348 kb
Host smart-6cc75d97-fa8e-4941-8d5c-d59382963017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832769180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1832769180
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.3117886025
Short name T662
Test name
Test status
Simulation time 28846690 ps
CPU time 1.15 seconds
Started Feb 18 03:15:07 PM PST 24
Finished Feb 18 03:15:18 PM PST 24
Peak memory 215904 kb
Host smart-fe680c2d-a05d-4b92-a04f-7c201b6d7151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117886025 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3117886025
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.2178370175
Short name T429
Test name
Test status
Simulation time 43148520 ps
CPU time 0.94 seconds
Started Feb 18 03:15:11 PM PST 24
Finished Feb 18 03:15:24 PM PST 24
Peak memory 222388 kb
Host smart-184b2c37-1bcf-474b-8f66-c3b948e5c0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178370175 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2178370175
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.883384147
Short name T348
Test name
Test status
Simulation time 19081239 ps
CPU time 0.98 seconds
Started Feb 18 03:14:59 PM PST 24
Finished Feb 18 03:15:08 PM PST 24
Peak memory 206500 kb
Host smart-32c3f4e7-1fd1-4530-84a7-8a7743ff2914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883384147 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.883384147
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2216880258
Short name T566
Test name
Test status
Simulation time 508167553 ps
CPU time 3.26 seconds
Started Feb 18 03:15:02 PM PST 24
Finished Feb 18 03:15:13 PM PST 24
Peak memory 215860 kb
Host smart-eaedc090-a153-4561-b9bc-6a74a39e4986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216880258 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2216880258
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.445630649
Short name T629
Test name
Test status
Simulation time 46520453504 ps
CPU time 1118.23 seconds
Started Feb 18 03:15:02 PM PST 24
Finished Feb 18 03:33:48 PM PST 24
Peak memory 220632 kb
Host smart-2f717162-460a-4cfd-8248-d332e0b92285
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445630649 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.445630649
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.1289057567
Short name T190
Test name
Test status
Simulation time 50497684 ps
CPU time 1.32 seconds
Started Feb 18 03:17:18 PM PST 24
Finished Feb 18 03:17:26 PM PST 24
Peak memory 217444 kb
Host smart-04b96bbe-ede1-4584-9ec0-0c21e0863193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289057567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1289057567
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.442247071
Short name T535
Test name
Test status
Simulation time 72936155 ps
CPU time 1.36 seconds
Started Feb 18 03:17:23 PM PST 24
Finished Feb 18 03:17:32 PM PST 24
Peak memory 217424 kb
Host smart-d3b654a8-832d-4fcf-8a45-90395f9f5b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442247071 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.442247071
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.1655318367
Short name T485
Test name
Test status
Simulation time 64449791 ps
CPU time 1.25 seconds
Started Feb 18 03:17:19 PM PST 24
Finished Feb 18 03:17:28 PM PST 24
Peak memory 217376 kb
Host smart-ac6cf8e4-8915-4ad2-b9ef-5737d811a175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655318367 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1655318367
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.145866887
Short name T418
Test name
Test status
Simulation time 155343370 ps
CPU time 1.65 seconds
Started Feb 18 03:17:25 PM PST 24
Finished Feb 18 03:17:34 PM PST 24
Peak memory 217504 kb
Host smart-a642bc58-b9a3-41c5-b5a5-05aa5d194575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145866887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.145866887
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.2352220087
Short name T604
Test name
Test status
Simulation time 43015033 ps
CPU time 1.38 seconds
Started Feb 18 03:17:24 PM PST 24
Finished Feb 18 03:17:33 PM PST 24
Peak memory 215880 kb
Host smart-a8dcf02d-65e0-44ae-b718-9291a8f62208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352220087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2352220087
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.3946840957
Short name T623
Test name
Test status
Simulation time 52298470 ps
CPU time 1.61 seconds
Started Feb 18 03:17:17 PM PST 24
Finished Feb 18 03:17:24 PM PST 24
Peak memory 216148 kb
Host smart-64317a08-e6d9-4128-8cdd-98b663e65a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946840957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3946840957
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.1515244316
Short name T797
Test name
Test status
Simulation time 66321189 ps
CPU time 1.34 seconds
Started Feb 18 03:17:27 PM PST 24
Finished Feb 18 03:17:35 PM PST 24
Peak memory 217048 kb
Host smart-22a4bf0d-816c-4197-b84c-3ecfbf98432d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515244316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.1515244316
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.4006032449
Short name T294
Test name
Test status
Simulation time 93624993 ps
CPU time 1.3 seconds
Started Feb 18 03:17:18 PM PST 24
Finished Feb 18 03:17:25 PM PST 24
Peak memory 216124 kb
Host smart-39f141d2-bdff-4097-9d8b-5be9e25fa370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006032449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.4006032449
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.1788982125
Short name T808
Test name
Test status
Simulation time 75380492 ps
CPU time 1.41 seconds
Started Feb 18 03:17:19 PM PST 24
Finished Feb 18 03:17:27 PM PST 24
Peak memory 217496 kb
Host smart-6926dd49-27e7-4b8c-9d5f-7cfed1707d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788982125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1788982125
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.1138136944
Short name T471
Test name
Test status
Simulation time 218475209 ps
CPU time 3.29 seconds
Started Feb 18 03:17:18 PM PST 24
Finished Feb 18 03:17:26 PM PST 24
Peak memory 218620 kb
Host smart-f86ed153-2ee5-4f0e-bbb6-4127a3a2318f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138136944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.1138136944
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1939405152
Short name T117
Test name
Test status
Simulation time 98662057 ps
CPU time 1.29 seconds
Started Feb 18 03:15:13 PM PST 24
Finished Feb 18 03:15:27 PM PST 24
Peak memory 215068 kb
Host smart-61f8179c-a80d-484d-acf8-cdeff146b8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939405152 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1939405152
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2038761602
Short name T447
Test name
Test status
Simulation time 16787041 ps
CPU time 0.98 seconds
Started Feb 18 03:15:13 PM PST 24
Finished Feb 18 03:15:26 PM PST 24
Peak memory 206252 kb
Host smart-365c7ce6-47ec-4052-a210-66afc1386d63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038761602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2038761602
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_err.3882493180
Short name T1
Test name
Test status
Simulation time 21421653 ps
CPU time 1.08 seconds
Started Feb 18 03:15:11 PM PST 24
Finished Feb 18 03:15:24 PM PST 24
Peak memory 222552 kb
Host smart-2032bcc0-fff7-4ba8-8580-eb85c5b28e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882493180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.3882493180
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.1512359958
Short name T837
Test name
Test status
Simulation time 265378253 ps
CPU time 1.11 seconds
Started Feb 18 03:15:08 PM PST 24
Finished Feb 18 03:15:19 PM PST 24
Peak memory 215988 kb
Host smart-866cb56f-76af-4b16-8c19-8a56b9577e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512359958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.1512359958
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1285298900
Short name T358
Test name
Test status
Simulation time 22682942 ps
CPU time 1.08 seconds
Started Feb 18 03:15:14 PM PST 24
Finished Feb 18 03:15:27 PM PST 24
Peak memory 214952 kb
Host smart-3a50b509-e235-4639-928d-0ce85884f203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285298900 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1285298900
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.325742051
Short name T769
Test name
Test status
Simulation time 19846153 ps
CPU time 0.99 seconds
Started Feb 18 03:15:12 PM PST 24
Finished Feb 18 03:15:25 PM PST 24
Peak memory 214728 kb
Host smart-cf6e3e0f-3975-46bd-89ff-2941c6b77279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325742051 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.325742051
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.910587739
Short name T588
Test name
Test status
Simulation time 198141782 ps
CPU time 3.8 seconds
Started Feb 18 03:15:06 PM PST 24
Finished Feb 18 03:15:18 PM PST 24
Peak memory 215704 kb
Host smart-020ba48b-46c4-4bec-8551-c66f421556ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910587739 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.910587739
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1292324353
Short name T23
Test name
Test status
Simulation time 427562561888 ps
CPU time 2623.2 seconds
Started Feb 18 03:15:06 PM PST 24
Finished Feb 18 03:58:58 PM PST 24
Peak memory 231660 kb
Host smart-f3f3ddcb-a3a4-4222-81f5-53a5360c4164
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292324353 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1292324353
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.200783911
Short name T306
Test name
Test status
Simulation time 35783934 ps
CPU time 1.38 seconds
Started Feb 18 03:17:17 PM PST 24
Finished Feb 18 03:17:23 PM PST 24
Peak memory 216392 kb
Host smart-e9249459-fa21-4795-872d-429b913598f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200783911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.200783911
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.1032175617
Short name T19
Test name
Test status
Simulation time 111602477 ps
CPU time 1.45 seconds
Started Feb 18 03:17:16 PM PST 24
Finished Feb 18 03:17:23 PM PST 24
Peak memory 217608 kb
Host smart-19c1474f-b9e0-473b-aea3-8f32ca88408e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032175617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1032175617
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.1761374141
Short name T676
Test name
Test status
Simulation time 47050127 ps
CPU time 1.86 seconds
Started Feb 18 03:17:17 PM PST 24
Finished Feb 18 03:17:23 PM PST 24
Peak memory 217196 kb
Host smart-fbb9d149-40d1-4535-a281-fe729d80ba7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761374141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.1761374141
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.2795962873
Short name T362
Test name
Test status
Simulation time 76293952 ps
CPU time 1.67 seconds
Started Feb 18 03:17:18 PM PST 24
Finished Feb 18 03:17:26 PM PST 24
Peak memory 217424 kb
Host smart-e30c38ee-b193-4d29-ab79-5ee6f0b2a4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795962873 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2795962873
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.388203219
Short name T365
Test name
Test status
Simulation time 67654486 ps
CPU time 1.03 seconds
Started Feb 18 03:17:19 PM PST 24
Finished Feb 18 03:17:26 PM PST 24
Peak memory 216016 kb
Host smart-841f1307-2421-4f67-8d00-cdcc59a1f43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388203219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.388203219
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.259082715
Short name T289
Test name
Test status
Simulation time 250849053 ps
CPU time 3.31 seconds
Started Feb 18 03:17:21 PM PST 24
Finished Feb 18 03:17:33 PM PST 24
Peak memory 216088 kb
Host smart-3e5822b5-1dec-4317-866d-c8b7b89678cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259082715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.259082715
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.2387919883
Short name T645
Test name
Test status
Simulation time 42663707 ps
CPU time 1.48 seconds
Started Feb 18 03:17:19 PM PST 24
Finished Feb 18 03:17:28 PM PST 24
Peak memory 217008 kb
Host smart-f995aac2-127e-4187-80cb-7538096e19ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387919883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2387919883
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.3629015255
Short name T664
Test name
Test status
Simulation time 54024800 ps
CPU time 1.31 seconds
Started Feb 18 03:17:34 PM PST 24
Finished Feb 18 03:17:42 PM PST 24
Peak memory 216136 kb
Host smart-acbc4298-8746-40d4-8f17-52e7a7e8f9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629015255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3629015255
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.323036599
Short name T803
Test name
Test status
Simulation time 35018051 ps
CPU time 1.32 seconds
Started Feb 18 03:17:34 PM PST 24
Finished Feb 18 03:17:42 PM PST 24
Peak memory 217056 kb
Host smart-23837afe-6fd8-4f2c-8ff8-6c95247f6734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323036599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.323036599
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.2926842899
Short name T148
Test name
Test status
Simulation time 335789262 ps
CPU time 1.68 seconds
Started Feb 18 03:15:16 PM PST 24
Finished Feb 18 03:15:29 PM PST 24
Peak memory 214612 kb
Host smart-372ba48e-4ef1-4b77-a407-4dfa279aa8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926842899 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2926842899
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.1137443316
Short name T624
Test name
Test status
Simulation time 12146107 ps
CPU time 0.85 seconds
Started Feb 18 03:15:13 PM PST 24
Finished Feb 18 03:15:27 PM PST 24
Peak memory 205216 kb
Host smart-f5aa00f5-4bcb-40d5-84c3-08a6cd9e3a84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137443316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1137443316
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.4068473236
Short name T755
Test name
Test status
Simulation time 14204486 ps
CPU time 0.88 seconds
Started Feb 18 03:15:08 PM PST 24
Finished Feb 18 03:15:20 PM PST 24
Peak memory 215424 kb
Host smart-3255588a-2ee5-463a-820f-ad2f50cc2aee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068473236 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.4068473236
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.2546533222
Short name T445
Test name
Test status
Simulation time 33738026 ps
CPU time 0.92 seconds
Started Feb 18 03:15:16 PM PST 24
Finished Feb 18 03:15:28 PM PST 24
Peak memory 217036 kb
Host smart-10746895-e1b8-4651-a862-ff228a42d0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546533222 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2546533222
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1521622906
Short name T605
Test name
Test status
Simulation time 70506288 ps
CPU time 1.14 seconds
Started Feb 18 03:15:13 PM PST 24
Finished Feb 18 03:15:26 PM PST 24
Peak memory 215980 kb
Host smart-d901681e-de33-4eb6-ad37-180c0e709873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521622906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1521622906
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_smoke.629786110
Short name T630
Test name
Test status
Simulation time 47958200 ps
CPU time 0.95 seconds
Started Feb 18 03:15:09 PM PST 24
Finished Feb 18 03:15:21 PM PST 24
Peak memory 214752 kb
Host smart-41983444-9ac2-4aa2-b9bf-6407c5d5b1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629786110 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.629786110
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2463211468
Short name T785
Test name
Test status
Simulation time 124163869 ps
CPU time 2.75 seconds
Started Feb 18 03:15:09 PM PST 24
Finished Feb 18 03:15:23 PM PST 24
Peak memory 215908 kb
Host smart-ef64ec8d-ebe4-4a82-8671-f37f71409e9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463211468 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2463211468
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2117522709
Short name T747
Test name
Test status
Simulation time 43170204887 ps
CPU time 1098.66 seconds
Started Feb 18 03:15:06 PM PST 24
Finished Feb 18 03:33:34 PM PST 24
Peak memory 219048 kb
Host smart-1de19d45-0a1e-4105-a2a9-be593f7e7bcd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117522709 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2117522709
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.654111425
Short name T635
Test name
Test status
Simulation time 39559966 ps
CPU time 1.49 seconds
Started Feb 18 03:17:25 PM PST 24
Finished Feb 18 03:17:34 PM PST 24
Peak memory 215924 kb
Host smart-b5e82fa2-ef09-4480-98a0-07e6ebb5e2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654111425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.654111425
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.2319884000
Short name T695
Test name
Test status
Simulation time 52546468 ps
CPU time 1.59 seconds
Started Feb 18 03:17:19 PM PST 24
Finished Feb 18 03:17:28 PM PST 24
Peak memory 216932 kb
Host smart-4964590e-038a-4de6-af80-e56d113a2478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319884000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.2319884000
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.2055076100
Short name T807
Test name
Test status
Simulation time 75085396 ps
CPU time 2.69 seconds
Started Feb 18 03:17:33 PM PST 24
Finished Feb 18 03:17:43 PM PST 24
Peak memory 218856 kb
Host smart-dd232558-50c3-4810-bd1d-f6ade7bea297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055076100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2055076100
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.3762994097
Short name T385
Test name
Test status
Simulation time 48246288 ps
CPU time 1.04 seconds
Started Feb 18 03:17:27 PM PST 24
Finished Feb 18 03:17:35 PM PST 24
Peak memory 216096 kb
Host smart-dee04356-17aa-4f21-ac06-3aa9b6c17400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762994097 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3762994097
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.4001066224
Short name T737
Test name
Test status
Simulation time 34391729 ps
CPU time 1.57 seconds
Started Feb 18 03:17:20 PM PST 24
Finished Feb 18 03:17:30 PM PST 24
Peak memory 217428 kb
Host smart-bde42c1a-dbc5-47e7-b601-9b527db5af4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001066224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.4001066224
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.350927957
Short name T10
Test name
Test status
Simulation time 93868903 ps
CPU time 1.28 seconds
Started Feb 18 03:17:28 PM PST 24
Finished Feb 18 03:17:36 PM PST 24
Peak memory 218432 kb
Host smart-beae1e4d-4630-4f15-bf75-3e707a0544f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350927957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.350927957
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1953067357
Short name T425
Test name
Test status
Simulation time 110183895 ps
CPU time 1.44 seconds
Started Feb 18 03:17:31 PM PST 24
Finished Feb 18 03:17:40 PM PST 24
Peak memory 217144 kb
Host smart-947590c2-b7be-4e48-a27c-9596c609e3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953067357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1953067357
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.800451095
Short name T459
Test name
Test status
Simulation time 37383339 ps
CPU time 1.29 seconds
Started Feb 18 03:17:29 PM PST 24
Finished Feb 18 03:17:37 PM PST 24
Peak memory 216112 kb
Host smart-e627d83a-5ff3-4de4-88b2-c186fc712256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800451095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.800451095
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert_test.3489326406
Short name T771
Test name
Test status
Simulation time 48160868 ps
CPU time 0.86 seconds
Started Feb 18 03:15:14 PM PST 24
Finished Feb 18 03:15:28 PM PST 24
Peak memory 206252 kb
Host smart-a73a53b7-8a8e-4d8d-821e-fb88508db7cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489326406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3489326406
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1077935510
Short name T671
Test name
Test status
Simulation time 60782241 ps
CPU time 1.02 seconds
Started Feb 18 03:15:16 PM PST 24
Finished Feb 18 03:15:28 PM PST 24
Peak memory 215560 kb
Host smart-0cb9f300-9539-4107-b4b9-3783b58f511e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077935510 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1077935510
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2795883058
Short name T105
Test name
Test status
Simulation time 19361847 ps
CPU time 1.04 seconds
Started Feb 18 03:15:14 PM PST 24
Finished Feb 18 03:15:27 PM PST 24
Peak memory 217264 kb
Host smart-452d0ae7-4d9b-4649-91a8-2ad255c07d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795883058 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2795883058
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2815762892
Short name T816
Test name
Test status
Simulation time 57653037 ps
CPU time 1.45 seconds
Started Feb 18 03:15:16 PM PST 24
Finished Feb 18 03:15:29 PM PST 24
Peak memory 217364 kb
Host smart-41b76e09-ea1d-48f7-8044-d785775282c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815762892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2815762892
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2398239304
Short name T621
Test name
Test status
Simulation time 40490748 ps
CPU time 0.92 seconds
Started Feb 18 03:15:14 PM PST 24
Finished Feb 18 03:15:27 PM PST 24
Peak memory 214792 kb
Host smart-bb4eacce-bee5-4e87-9364-954bbd9e9926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398239304 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2398239304
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2492130999
Short name T484
Test name
Test status
Simulation time 16613958 ps
CPU time 0.98 seconds
Started Feb 18 03:15:16 PM PST 24
Finished Feb 18 03:15:28 PM PST 24
Peak memory 214656 kb
Host smart-3e93a9ed-87c2-4073-b8a9-460663d58c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492130999 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2492130999
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.3796266553
Short name T601
Test name
Test status
Simulation time 293114175 ps
CPU time 5.96 seconds
Started Feb 18 03:15:14 PM PST 24
Finished Feb 18 03:15:33 PM PST 24
Peak memory 218832 kb
Host smart-cce1119e-da89-4601-8228-21f4d6787dea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796266553 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.3796266553
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/190.edn_genbits.4110150270
Short name T389
Test name
Test status
Simulation time 37874364 ps
CPU time 1.49 seconds
Started Feb 18 03:17:25 PM PST 24
Finished Feb 18 03:17:34 PM PST 24
Peak memory 218432 kb
Host smart-abb76121-7838-4f2e-ba5e-e6e5ec4f76bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110150270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.4110150270
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.934074683
Short name T56
Test name
Test status
Simulation time 114743013 ps
CPU time 2.42 seconds
Started Feb 18 03:17:32 PM PST 24
Finished Feb 18 03:17:41 PM PST 24
Peak memory 218496 kb
Host smart-91de814e-5c0b-4f60-a1b1-23017adc12f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934074683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.934074683
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.4125970270
Short name T221
Test name
Test status
Simulation time 86193445 ps
CPU time 1.77 seconds
Started Feb 18 03:17:42 PM PST 24
Finished Feb 18 03:17:50 PM PST 24
Peak memory 217636 kb
Host smart-d26fab6f-a354-4d57-a40d-bd8f394caeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125970270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.4125970270
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.523246530
Short name T375
Test name
Test status
Simulation time 266655193 ps
CPU time 3.76 seconds
Started Feb 18 03:17:25 PM PST 24
Finished Feb 18 03:17:36 PM PST 24
Peak memory 217888 kb
Host smart-1b6bd173-51a1-4488-842f-3d9b5e562d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523246530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.523246530
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.2967524235
Short name T317
Test name
Test status
Simulation time 78111665 ps
CPU time 1.14 seconds
Started Feb 18 03:17:24 PM PST 24
Finished Feb 18 03:17:33 PM PST 24
Peak memory 215948 kb
Host smart-c2347e1f-ca86-438c-82ef-75a52d667106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967524235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.2967524235
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.1995397748
Short name T731
Test name
Test status
Simulation time 35165996 ps
CPU time 1.03 seconds
Started Feb 18 03:17:35 PM PST 24
Finished Feb 18 03:17:43 PM PST 24
Peak memory 216052 kb
Host smart-27222b81-03ea-44ba-ab59-94e73017e469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995397748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1995397748
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.2690568201
Short name T798
Test name
Test status
Simulation time 56132357 ps
CPU time 1.22 seconds
Started Feb 18 03:17:24 PM PST 24
Finished Feb 18 03:17:33 PM PST 24
Peak memory 217952 kb
Host smart-cb13e483-6672-44fb-a7d4-14759ffc0174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690568201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2690568201
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.2428281740
Short name T291
Test name
Test status
Simulation time 83274970 ps
CPU time 1.13 seconds
Started Feb 18 03:17:26 PM PST 24
Finished Feb 18 03:17:34 PM PST 24
Peak memory 216140 kb
Host smart-09a1c317-563e-4354-ab0c-9c5ded606dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428281740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2428281740
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.1004426725
Short name T600
Test name
Test status
Simulation time 68970346 ps
CPU time 1.44 seconds
Started Feb 18 03:17:33 PM PST 24
Finished Feb 18 03:17:42 PM PST 24
Peak memory 216096 kb
Host smart-ea0a3210-b36b-40fa-b1a6-3f3a614a04f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004426725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1004426725
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.4056155072
Short name T290
Test name
Test status
Simulation time 35447376 ps
CPU time 1.38 seconds
Started Feb 18 03:17:28 PM PST 24
Finished Feb 18 03:17:36 PM PST 24
Peak memory 217308 kb
Host smart-52d224a4-4659-448e-891f-5914f8719142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056155072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.4056155072
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2087267531
Short name T710
Test name
Test status
Simulation time 29348430 ps
CPU time 1.25 seconds
Started Feb 18 03:14:08 PM PST 24
Finished Feb 18 03:14:21 PM PST 24
Peak memory 215040 kb
Host smart-e25563fa-f540-4e73-9d2b-ad0ac5fa6ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087267531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2087267531
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.1798691447
Short name T500
Test name
Test status
Simulation time 26769981 ps
CPU time 0.91 seconds
Started Feb 18 03:14:11 PM PST 24
Finished Feb 18 03:14:22 PM PST 24
Peak memory 205888 kb
Host smart-6c3e6d2e-62d1-4bd6-8b90-5141777acf0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798691447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.1798691447
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.418655222
Short name T436
Test name
Test status
Simulation time 34608418 ps
CPU time 1.25 seconds
Started Feb 18 03:14:09 PM PST 24
Finished Feb 18 03:14:22 PM PST 24
Peak memory 217172 kb
Host smart-8d9154d6-ee26-45d0-b285-8c894fb0eebb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418655222 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.418655222
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.2275568913
Short name T153
Test name
Test status
Simulation time 27814042 ps
CPU time 0.87 seconds
Started Feb 18 03:14:09 PM PST 24
Finished Feb 18 03:14:21 PM PST 24
Peak memory 217216 kb
Host smart-ed53968e-0a99-4fb8-a309-4944845f428c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275568913 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2275568913
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.133860079
Short name T332
Test name
Test status
Simulation time 35584826 ps
CPU time 1.37 seconds
Started Feb 18 03:14:05 PM PST 24
Finished Feb 18 03:14:18 PM PST 24
Peak memory 215952 kb
Host smart-4db6b3e6-2948-45c8-98bf-99fc12eb96f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133860079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.133860079
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_sec_cm.3778821670
Short name T16
Test name
Test status
Simulation time 637962355 ps
CPU time 5.46 seconds
Started Feb 18 03:14:10 PM PST 24
Finished Feb 18 03:14:26 PM PST 24
Peak memory 235084 kb
Host smart-61109d39-c006-4914-a091-754dc0ad7b50
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778821670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.3778821670
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3185134392
Short name T555
Test name
Test status
Simulation time 16476396 ps
CPU time 0.94 seconds
Started Feb 18 03:14:09 PM PST 24
Finished Feb 18 03:14:21 PM PST 24
Peak memory 214708 kb
Host smart-aa787324-7acd-4682-b2d9-17b19e9dd027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185134392 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3185134392
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3863730450
Short name T285
Test name
Test status
Simulation time 298348315 ps
CPU time 3.39 seconds
Started Feb 18 03:14:06 PM PST 24
Finished Feb 18 03:14:21 PM PST 24
Peak memory 214760 kb
Host smart-7889e6f7-aa1c-428b-b901-d2ee1884660e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863730450 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3863730450
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1076461820
Short name T192
Test name
Test status
Simulation time 80812083302 ps
CPU time 1156.93 seconds
Started Feb 18 03:14:08 PM PST 24
Finished Feb 18 03:33:37 PM PST 24
Peak memory 220916 kb
Host smart-609cc5f4-fee7-48fa-aa3a-8bd2f0928ddf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076461820 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1076461820
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.747573531
Short name T597
Test name
Test status
Simulation time 132444967 ps
CPU time 1.16 seconds
Started Feb 18 03:15:24 PM PST 24
Finished Feb 18 03:15:36 PM PST 24
Peak memory 215056 kb
Host smart-68d2f5be-67cb-46dc-b65a-f3963bd10518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747573531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.747573531
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.4172847000
Short name T730
Test name
Test status
Simulation time 60191504 ps
CPU time 0.93 seconds
Started Feb 18 03:15:17 PM PST 24
Finished Feb 18 03:15:29 PM PST 24
Peak memory 205872 kb
Host smart-a09e447d-3541-4bcf-a186-3c07e000d5be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172847000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.4172847000
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.4170557940
Short name T163
Test name
Test status
Simulation time 101679258 ps
CPU time 0.83 seconds
Started Feb 18 03:15:16 PM PST 24
Finished Feb 18 03:15:28 PM PST 24
Peak memory 215092 kb
Host smart-668f9d72-b9a1-44eb-a08c-b0454c6fff64
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170557940 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.4170557940
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3830742456
Short name T347
Test name
Test status
Simulation time 37946633 ps
CPU time 1.31 seconds
Started Feb 18 03:15:21 PM PST 24
Finished Feb 18 03:15:33 PM PST 24
Peak memory 215844 kb
Host smart-20118952-9a39-4590-aa5d-7a159ae1f423
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830742456 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3830742456
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.152633100
Short name T382
Test name
Test status
Simulation time 23283616 ps
CPU time 0.91 seconds
Started Feb 18 03:15:17 PM PST 24
Finished Feb 18 03:15:29 PM PST 24
Peak memory 217180 kb
Host smart-6b972509-dbfa-40cf-80f9-b8587efde8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152633100 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.152633100
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.939579399
Short name T288
Test name
Test status
Simulation time 30816063 ps
CPU time 1.23 seconds
Started Feb 18 03:15:12 PM PST 24
Finished Feb 18 03:15:26 PM PST 24
Peak memory 217456 kb
Host smart-ddec5612-6cb4-4f2e-9d74-e3e9b7d3dfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939579399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.939579399
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.1618268209
Short name T709
Test name
Test status
Simulation time 21620415 ps
CPU time 1.01 seconds
Started Feb 18 03:15:17 PM PST 24
Finished Feb 18 03:15:29 PM PST 24
Peak memory 214984 kb
Host smart-189aa7f8-1e27-46c0-92a0-b67ee7d40a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618268209 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1618268209
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.1468665914
Short name T357
Test name
Test status
Simulation time 17346256 ps
CPU time 0.96 seconds
Started Feb 18 03:15:24 PM PST 24
Finished Feb 18 03:15:35 PM PST 24
Peak memory 214756 kb
Host smart-659f843c-c157-498f-89f5-936ba1233c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468665914 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.1468665914
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.1824034092
Short name T472
Test name
Test status
Simulation time 61875619 ps
CPU time 1.72 seconds
Started Feb 18 03:15:24 PM PST 24
Finished Feb 18 03:15:36 PM PST 24
Peak memory 214644 kb
Host smart-07226fce-baf2-4c98-b126-5ed9276c3d3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824034092 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.1824034092
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.3056494165
Short name T198
Test name
Test status
Simulation time 87662598692 ps
CPU time 997.03 seconds
Started Feb 18 03:15:11 PM PST 24
Finished Feb 18 03:32:00 PM PST 24
Peak memory 220156 kb
Host smart-43da0261-159e-4f95-b25b-5c776cf9997b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056494165 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.3056494165
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.1521596928
Short name T510
Test name
Test status
Simulation time 75718327 ps
CPU time 1.62 seconds
Started Feb 18 03:17:25 PM PST 24
Finished Feb 18 03:17:34 PM PST 24
Peak memory 219016 kb
Host smart-855d5098-6ffb-436c-9455-a80efab329cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521596928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1521596928
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1214756411
Short name T373
Test name
Test status
Simulation time 52877940 ps
CPU time 1.32 seconds
Started Feb 18 03:17:33 PM PST 24
Finished Feb 18 03:17:41 PM PST 24
Peak memory 218948 kb
Host smart-94ac4ad0-f6eb-4182-b380-e807d19d8402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214756411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1214756411
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2922848199
Short name T680
Test name
Test status
Simulation time 141180033 ps
CPU time 3.05 seconds
Started Feb 18 03:17:25 PM PST 24
Finished Feb 18 03:17:36 PM PST 24
Peak memory 217240 kb
Host smart-08592965-ea8d-48b4-81de-2513f5aa4b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922848199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2922848199
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.3184916383
Short name T293
Test name
Test status
Simulation time 31828578 ps
CPU time 1.67 seconds
Started Feb 18 03:17:31 PM PST 24
Finished Feb 18 03:17:39 PM PST 24
Peak memory 217180 kb
Host smart-9729857c-8159-4c49-b8e8-42c43e57f24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184916383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.3184916383
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2434586977
Short name T292
Test name
Test status
Simulation time 91908978 ps
CPU time 1.17 seconds
Started Feb 18 03:17:24 PM PST 24
Finished Feb 18 03:17:33 PM PST 24
Peak memory 215944 kb
Host smart-3d337425-8418-48cc-a208-b5f01c8ab34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434586977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2434586977
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1394142104
Short name T272
Test name
Test status
Simulation time 36991021 ps
CPU time 1.6 seconds
Started Feb 18 03:17:33 PM PST 24
Finished Feb 18 03:17:41 PM PST 24
Peak memory 217396 kb
Host smart-3c752329-590e-4c20-8231-9e3dbeb80612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394142104 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1394142104
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.1351157199
Short name T501
Test name
Test status
Simulation time 38328276 ps
CPU time 1.42 seconds
Started Feb 18 03:17:29 PM PST 24
Finished Feb 18 03:17:37 PM PST 24
Peak memory 215740 kb
Host smart-9d593d92-0f36-42a1-837b-b1acf0f75ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351157199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.1351157199
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.4177697370
Short name T788
Test name
Test status
Simulation time 73661228 ps
CPU time 1.43 seconds
Started Feb 18 03:17:29 PM PST 24
Finished Feb 18 03:17:37 PM PST 24
Peak memory 217472 kb
Host smart-8326b4cb-de8d-4b71-a845-b037fad01cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177697370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.4177697370
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2295605731
Short name T633
Test name
Test status
Simulation time 68495231 ps
CPU time 1.17 seconds
Started Feb 18 03:17:33 PM PST 24
Finished Feb 18 03:17:41 PM PST 24
Peak memory 216084 kb
Host smart-b31ba4d2-10bd-42cb-865f-4e7e0ed8dd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295605731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2295605731
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert_test.1406802150
Short name T364
Test name
Test status
Simulation time 22782148 ps
CPU time 0.83 seconds
Started Feb 18 03:15:20 PM PST 24
Finished Feb 18 03:15:31 PM PST 24
Peak memory 206032 kb
Host smart-c0f9f82a-59c6-48d7-8de3-e0cec2438cfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406802150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1406802150
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1363321459
Short name T542
Test name
Test status
Simulation time 57140075 ps
CPU time 0.81 seconds
Started Feb 18 03:15:23 PM PST 24
Finished Feb 18 03:15:34 PM PST 24
Peak memory 215096 kb
Host smart-c85b0024-2523-4ac6-b34a-56db8047e172
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363321459 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1363321459
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3276711064
Short name T383
Test name
Test status
Simulation time 55032686 ps
CPU time 1.11 seconds
Started Feb 18 03:15:20 PM PST 24
Finished Feb 18 03:15:31 PM PST 24
Peak memory 216992 kb
Host smart-a0da32eb-5014-4ad1-865f-a53d24fbfcba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276711064 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3276711064
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.730614484
Short name T434
Test name
Test status
Simulation time 19496111 ps
CPU time 1.04 seconds
Started Feb 18 03:15:18 PM PST 24
Finished Feb 18 03:15:29 PM PST 24
Peak memory 217520 kb
Host smart-bf163e17-c344-4782-977a-2cad375609a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730614484 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.730614484
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3086524884
Short name T508
Test name
Test status
Simulation time 26065168 ps
CPU time 1.31 seconds
Started Feb 18 03:15:19 PM PST 24
Finished Feb 18 03:15:30 PM PST 24
Peak memory 215984 kb
Host smart-b910a324-a948-41b1-aa08-7a3641facb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086524884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3086524884
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2545582644
Short name T829
Test name
Test status
Simulation time 22436195 ps
CPU time 1.21 seconds
Started Feb 18 03:15:24 PM PST 24
Finished Feb 18 03:15:36 PM PST 24
Peak memory 223476 kb
Host smart-4406c2d8-312c-41b6-a923-3f73a0c23c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545582644 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2545582644
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3946922559
Short name T649
Test name
Test status
Simulation time 150863793 ps
CPU time 0.87 seconds
Started Feb 18 03:15:17 PM PST 24
Finished Feb 18 03:15:29 PM PST 24
Peak memory 214724 kb
Host smart-14e9f27a-d466-49d5-857d-dac15b4112bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946922559 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3946922559
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2117705082
Short name T653
Test name
Test status
Simulation time 337924209 ps
CPU time 2.5 seconds
Started Feb 18 03:15:18 PM PST 24
Finished Feb 18 03:15:31 PM PST 24
Peak memory 214660 kb
Host smart-21b5c218-788e-41e9-b709-2ee3159e4b3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117705082 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2117705082
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.2281774379
Short name T453
Test name
Test status
Simulation time 108185587915 ps
CPU time 1044.86 seconds
Started Feb 18 03:15:21 PM PST 24
Finished Feb 18 03:32:56 PM PST 24
Peak memory 220452 kb
Host smart-2ee84d40-f7ee-427b-8362-b3c2bfe7b4a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281774379 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.2281774379
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3259884927
Short name T51
Test name
Test status
Simulation time 191635732 ps
CPU time 2.63 seconds
Started Feb 18 03:17:42 PM PST 24
Finished Feb 18 03:17:51 PM PST 24
Peak memory 219192 kb
Host smart-423b6359-c81a-48a9-957f-1ddcede95c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259884927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3259884927
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3775240396
Short name T270
Test name
Test status
Simulation time 32349358 ps
CPU time 1.27 seconds
Started Feb 18 03:17:36 PM PST 24
Finished Feb 18 03:17:44 PM PST 24
Peak memory 217092 kb
Host smart-8cfe6274-0821-4f5b-af3c-9ac6b0d1fe74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775240396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3775240396
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2407201813
Short name T315
Test name
Test status
Simulation time 39951952 ps
CPU time 1.13 seconds
Started Feb 18 03:17:30 PM PST 24
Finished Feb 18 03:17:38 PM PST 24
Peak memory 218364 kb
Host smart-32a80fd1-e2a0-4cd5-8061-8c8dd12eef78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407201813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2407201813
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3530530340
Short name T679
Test name
Test status
Simulation time 31843509 ps
CPU time 1.34 seconds
Started Feb 18 03:17:26 PM PST 24
Finished Feb 18 03:17:34 PM PST 24
Peak memory 215880 kb
Host smart-214e305b-e420-4622-9607-b76e080ad3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530530340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3530530340
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1880390243
Short name T49
Test name
Test status
Simulation time 61187270 ps
CPU time 1.26 seconds
Started Feb 18 03:17:41 PM PST 24
Finished Feb 18 03:17:49 PM PST 24
Peak memory 215992 kb
Host smart-562ff1bd-2626-4f67-84a1-f91af8357e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880390243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1880390243
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.750387324
Short name T333
Test name
Test status
Simulation time 150481317 ps
CPU time 2.57 seconds
Started Feb 18 03:17:31 PM PST 24
Finished Feb 18 03:17:41 PM PST 24
Peak memory 219104 kb
Host smart-88d6f924-a056-4439-ba6d-f7ecd8d8c52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750387324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.750387324
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.1087817957
Short name T307
Test name
Test status
Simulation time 36472207 ps
CPU time 1.06 seconds
Started Feb 18 03:17:29 PM PST 24
Finished Feb 18 03:17:36 PM PST 24
Peak memory 217188 kb
Host smart-d7b08e31-bd59-4e3b-b3eb-7feaa0736396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087817957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.1087817957
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.3038333926
Short name T398
Test name
Test status
Simulation time 107015856 ps
CPU time 1.38 seconds
Started Feb 18 03:17:30 PM PST 24
Finished Feb 18 03:17:38 PM PST 24
Peak memory 216072 kb
Host smart-1681c1f1-94c1-48f9-a143-bb065b3f2baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038333926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.3038333926
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2132836279
Short name T470
Test name
Test status
Simulation time 43353778 ps
CPU time 1.13 seconds
Started Feb 18 03:17:42 PM PST 24
Finished Feb 18 03:17:49 PM PST 24
Peak memory 216048 kb
Host smart-f1791ccc-3473-4b13-8898-ec0a769774e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132836279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2132836279
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1482058477
Short name T269
Test name
Test status
Simulation time 220511717 ps
CPU time 1.21 seconds
Started Feb 18 03:17:26 PM PST 24
Finished Feb 18 03:17:34 PM PST 24
Peak memory 215900 kb
Host smart-cd00e4ec-b06a-4c13-a17a-7ced76f855bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482058477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1482058477
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.4064020271
Short name T827
Test name
Test status
Simulation time 70092699 ps
CPU time 1.15 seconds
Started Feb 18 03:15:25 PM PST 24
Finished Feb 18 03:15:36 PM PST 24
Peak memory 215036 kb
Host smart-aa31a16d-c01f-4d11-8cba-32d1f9b277fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064020271 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.4064020271
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.330289684
Short name T340
Test name
Test status
Simulation time 38700829 ps
CPU time 0.95 seconds
Started Feb 18 03:15:20 PM PST 24
Finished Feb 18 03:15:31 PM PST 24
Peak memory 206268 kb
Host smart-424d52fa-15fd-4f3f-915f-99f6c8099f04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330289684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.330289684
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_err.17812782
Short name T78
Test name
Test status
Simulation time 32515360 ps
CPU time 0.91 seconds
Started Feb 18 03:15:21 PM PST 24
Finished Feb 18 03:15:32 PM PST 24
Peak memory 218684 kb
Host smart-f69fa499-363f-4184-8f24-d7454295e690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17812782 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.17812782
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.832288457
Short name T132
Test name
Test status
Simulation time 110831296 ps
CPU time 2.35 seconds
Started Feb 18 03:15:24 PM PST 24
Finished Feb 18 03:15:36 PM PST 24
Peak memory 218464 kb
Host smart-64044610-5e5a-4e82-9c0a-b43dbbe8eca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832288457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.832288457
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.4044034047
Short name T136
Test name
Test status
Simulation time 30261579 ps
CPU time 0.91 seconds
Started Feb 18 03:15:20 PM PST 24
Finished Feb 18 03:15:31 PM PST 24
Peak memory 215164 kb
Host smart-f9696582-d4c2-4824-9e02-3a76f0cc4110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044034047 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.4044034047
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.1672408883
Short name T47
Test name
Test status
Simulation time 19850391 ps
CPU time 0.96 seconds
Started Feb 18 03:15:25 PM PST 24
Finished Feb 18 03:15:36 PM PST 24
Peak memory 214672 kb
Host smart-b39a2bfc-3b6a-4250-9ad2-ba90c458169f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672408883 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.1672408883
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.216993855
Short name T762
Test name
Test status
Simulation time 220274624 ps
CPU time 4.78 seconds
Started Feb 18 03:15:19 PM PST 24
Finished Feb 18 03:15:34 PM PST 24
Peak memory 214764 kb
Host smart-a711e2dd-bfe4-433d-beca-fa5862a8bdc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216993855 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.216993855
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/220.edn_genbits.3540722201
Short name T767
Test name
Test status
Simulation time 51285232 ps
CPU time 1.44 seconds
Started Feb 18 03:17:41 PM PST 24
Finished Feb 18 03:17:49 PM PST 24
Peak memory 217332 kb
Host smart-6cf9a5c4-e864-4949-b1e4-6cbe57f2fb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540722201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3540722201
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.930691000
Short name T823
Test name
Test status
Simulation time 31569209 ps
CPU time 1.37 seconds
Started Feb 18 03:17:42 PM PST 24
Finished Feb 18 03:17:49 PM PST 24
Peak memory 216132 kb
Host smart-405aaf67-0b2b-4a50-806a-4cd320c82bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930691000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.930691000
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.567636297
Short name T813
Test name
Test status
Simulation time 40881740 ps
CPU time 1.51 seconds
Started Feb 18 03:17:25 PM PST 24
Finished Feb 18 03:17:34 PM PST 24
Peak memory 217052 kb
Host smart-9a4bda92-e3d6-43be-b133-50dec5b5cdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567636297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.567636297
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.471819677
Short name T646
Test name
Test status
Simulation time 43473918 ps
CPU time 1.41 seconds
Started Feb 18 03:17:30 PM PST 24
Finished Feb 18 03:17:38 PM PST 24
Peak memory 216040 kb
Host smart-cd921bee-3844-4e88-9fa6-3645f6f1ff45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471819677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.471819677
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.4169792051
Short name T388
Test name
Test status
Simulation time 86441755 ps
CPU time 1.2 seconds
Started Feb 18 03:17:36 PM PST 24
Finished Feb 18 03:17:44 PM PST 24
Peak memory 217284 kb
Host smart-d012752f-71f0-4d66-ada7-aeedca851305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169792051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.4169792051
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2124237500
Short name T582
Test name
Test status
Simulation time 106592639 ps
CPU time 1.13 seconds
Started Feb 18 03:17:34 PM PST 24
Finished Feb 18 03:17:43 PM PST 24
Peak memory 218304 kb
Host smart-edfe6102-55b9-4685-8721-89c61ae3b1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124237500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2124237500
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3545440238
Short name T28
Test name
Test status
Simulation time 41413951 ps
CPU time 1.71 seconds
Started Feb 18 03:17:27 PM PST 24
Finished Feb 18 03:17:35 PM PST 24
Peak memory 217308 kb
Host smart-a51a9218-cdf0-43c0-aefe-f0412e738370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545440238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3545440238
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2957706330
Short name T32
Test name
Test status
Simulation time 705878761 ps
CPU time 4.14 seconds
Started Feb 18 03:17:32 PM PST 24
Finished Feb 18 03:17:43 PM PST 24
Peak memory 217656 kb
Host smart-a8fecef8-0278-471e-868a-5f1a3a1b64dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957706330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2957706330
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.2748115312
Short name T30
Test name
Test status
Simulation time 60475936 ps
CPU time 1.05 seconds
Started Feb 18 03:17:31 PM PST 24
Finished Feb 18 03:17:39 PM PST 24
Peak memory 215936 kb
Host smart-6c07cc81-8c58-4609-801c-1f2b270fc1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748115312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.2748115312
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.2713518083
Short name T133
Test name
Test status
Simulation time 48952896 ps
CPU time 1.18 seconds
Started Feb 18 03:17:30 PM PST 24
Finished Feb 18 03:17:38 PM PST 24
Peak memory 217300 kb
Host smart-a495df4a-69e5-4d1f-b9b5-fceb29ecc051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713518083 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2713518083
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3322322550
Short name T822
Test name
Test status
Simulation time 29336535 ps
CPU time 1.28 seconds
Started Feb 18 03:15:28 PM PST 24
Finished Feb 18 03:15:39 PM PST 24
Peak memory 215060 kb
Host smart-1b1db9e2-890a-4a75-ad06-3dee66df65cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322322550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3322322550
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1692107309
Short name T661
Test name
Test status
Simulation time 13652339 ps
CPU time 0.92 seconds
Started Feb 18 03:15:24 PM PST 24
Finished Feb 18 03:15:35 PM PST 24
Peak memory 205868 kb
Host smart-3aae2d02-292c-4cd2-9dc6-ff9363b0fb14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692107309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1692107309
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3106024013
Short name T182
Test name
Test status
Simulation time 35576580 ps
CPU time 1.34 seconds
Started Feb 18 03:15:27 PM PST 24
Finished Feb 18 03:15:39 PM PST 24
Peak memory 216076 kb
Host smart-24ec12f9-7798-4763-b537-e48a918a93b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106024013 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3106024013
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.3301898443
Short name T547
Test name
Test status
Simulation time 22044363 ps
CPU time 1.2 seconds
Started Feb 18 03:15:26 PM PST 24
Finished Feb 18 03:15:38 PM PST 24
Peak memory 217520 kb
Host smart-6d9a677f-6c66-4eb4-8bc0-9ec0916261f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301898443 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.3301898443
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3228533350
Short name T486
Test name
Test status
Simulation time 45655568 ps
CPU time 1.3 seconds
Started Feb 18 03:15:27 PM PST 24
Finished Feb 18 03:15:39 PM PST 24
Peak memory 217248 kb
Host smart-91d7614e-adab-4449-ac56-35a02e95d390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228533350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3228533350
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.4075185429
Short name T378
Test name
Test status
Simulation time 24355845 ps
CPU time 0.97 seconds
Started Feb 18 03:15:32 PM PST 24
Finished Feb 18 03:15:43 PM PST 24
Peak memory 214924 kb
Host smart-fa26b081-4397-4d07-a4b9-34371ede4907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075185429 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.4075185429
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.319393282
Short name T777
Test name
Test status
Simulation time 17566697 ps
CPU time 1 seconds
Started Feb 18 03:15:20 PM PST 24
Finished Feb 18 03:15:32 PM PST 24
Peak memory 206640 kb
Host smart-a491824b-b823-42fd-90b0-ebefaa8f7190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319393282 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.319393282
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.4126834084
Short name T35
Test name
Test status
Simulation time 194598547 ps
CPU time 2.32 seconds
Started Feb 18 03:15:26 PM PST 24
Finished Feb 18 03:15:38 PM PST 24
Peak memory 215948 kb
Host smart-635034f1-e634-410d-8d5f-36e812970849
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126834084 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.4126834084
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.363680238
Short name T384
Test name
Test status
Simulation time 50400941685 ps
CPU time 577.46 seconds
Started Feb 18 03:15:29 PM PST 24
Finished Feb 18 03:25:17 PM PST 24
Peak memory 221264 kb
Host smart-1c751836-f55a-4af7-860f-cd279424d4b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363680238 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.363680238
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.2697521786
Short name T825
Test name
Test status
Simulation time 42432057 ps
CPU time 1.61 seconds
Started Feb 18 03:17:34 PM PST 24
Finished Feb 18 03:17:43 PM PST 24
Peak memory 215800 kb
Host smart-a28fd2d4-9e48-41f2-a087-18f2266469c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697521786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.2697521786
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1316930870
Short name T408
Test name
Test status
Simulation time 111545735 ps
CPU time 1.3 seconds
Started Feb 18 03:17:42 PM PST 24
Finished Feb 18 03:17:49 PM PST 24
Peak memory 217084 kb
Host smart-dd50af3d-a98a-4302-b433-e32cadb6c945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316930870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1316930870
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2766393302
Short name T323
Test name
Test status
Simulation time 31896718 ps
CPU time 1.32 seconds
Started Feb 18 03:17:42 PM PST 24
Finished Feb 18 03:17:49 PM PST 24
Peak memory 217252 kb
Host smart-10c54720-25f7-4cb3-b1ec-feedad0c6ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766393302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2766393302
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.663610828
Short name T310
Test name
Test status
Simulation time 145001201 ps
CPU time 1.16 seconds
Started Feb 18 03:17:35 PM PST 24
Finished Feb 18 03:17:43 PM PST 24
Peak memory 215832 kb
Host smart-e1d527ac-2862-496b-bce1-4092664e20d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663610828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.663610828
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1641531438
Short name T699
Test name
Test status
Simulation time 50249814 ps
CPU time 1.73 seconds
Started Feb 18 03:17:35 PM PST 24
Finished Feb 18 03:17:44 PM PST 24
Peak memory 217020 kb
Host smart-60fcf9ec-d3b3-45de-9799-3a10b265551d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641531438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1641531438
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.932909482
Short name T489
Test name
Test status
Simulation time 189232836 ps
CPU time 2.27 seconds
Started Feb 18 03:17:34 PM PST 24
Finished Feb 18 03:17:43 PM PST 24
Peak memory 216240 kb
Host smart-d62ca1e1-7174-4009-80c7-08c86abb900c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932909482 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.932909482
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.106241691
Short name T284
Test name
Test status
Simulation time 51063501 ps
CPU time 1.66 seconds
Started Feb 18 03:17:31 PM PST 24
Finished Feb 18 03:17:40 PM PST 24
Peak memory 218716 kb
Host smart-7b8595a7-8a93-4dcd-ad9f-c1dda5e56395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106241691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.106241691
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.4160031758
Short name T263
Test name
Test status
Simulation time 177373631 ps
CPU time 1 seconds
Started Feb 18 03:17:35 PM PST 24
Finished Feb 18 03:17:43 PM PST 24
Peak memory 215996 kb
Host smart-1bfcd7f5-576a-4da7-93dd-a30459d42cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160031758 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.4160031758
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.373358891
Short name T268
Test name
Test status
Simulation time 256277810 ps
CPU time 1.12 seconds
Started Feb 18 03:17:42 PM PST 24
Finished Feb 18 03:17:49 PM PST 24
Peak memory 216032 kb
Host smart-94f7d93e-4876-4b58-a0b0-e4b3dd75ad6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373358891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.373358891
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2214615372
Short name T738
Test name
Test status
Simulation time 59775066 ps
CPU time 1.44 seconds
Started Feb 18 03:17:42 PM PST 24
Finished Feb 18 03:17:49 PM PST 24
Peak memory 216048 kb
Host smart-51a7bb9e-5315-4b85-ad2f-bd8464f152cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214615372 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2214615372
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.1023793147
Short name T253
Test name
Test status
Simulation time 30840258 ps
CPU time 1.16 seconds
Started Feb 18 03:15:31 PM PST 24
Finished Feb 18 03:15:42 PM PST 24
Peak memory 215120 kb
Host smart-6d17d970-108c-4e4c-b2ba-bcb53d862ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023793147 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.1023793147
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.1175398773
Short name T528
Test name
Test status
Simulation time 24427594 ps
CPU time 0.91 seconds
Started Feb 18 03:15:29 PM PST 24
Finished Feb 18 03:15:40 PM PST 24
Peak memory 206216 kb
Host smart-0f86ac61-64bd-4d23-9de9-22b4fb7a87c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175398773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1175398773
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2534512929
Short name T157
Test name
Test status
Simulation time 93474319 ps
CPU time 0.79 seconds
Started Feb 18 03:15:34 PM PST 24
Finished Feb 18 03:15:44 PM PST 24
Peak memory 215032 kb
Host smart-5070b86e-a26f-41b7-8259-935fd866c2e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534512929 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2534512929
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_err.1125027556
Short name T670
Test name
Test status
Simulation time 29607934 ps
CPU time 1.3 seconds
Started Feb 18 03:15:30 PM PST 24
Finished Feb 18 03:15:41 PM PST 24
Peak memory 218432 kb
Host smart-dde2e330-e6c4-44e6-90c3-e434115f69b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125027556 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.1125027556
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.1778779710
Short name T734
Test name
Test status
Simulation time 168555938 ps
CPU time 1.45 seconds
Started Feb 18 03:15:27 PM PST 24
Finished Feb 18 03:15:39 PM PST 24
Peak memory 217676 kb
Host smart-c5d4c0a0-761f-46fb-b192-b3bb757ae74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778779710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.1778779710
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.4018352484
Short name T533
Test name
Test status
Simulation time 21731891 ps
CPU time 1.06 seconds
Started Feb 18 03:15:31 PM PST 24
Finished Feb 18 03:15:42 PM PST 24
Peak memory 215184 kb
Host smart-4d8a15b8-d36f-4ce2-8897-c840e3836386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018352484 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.4018352484
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.702496925
Short name T590
Test name
Test status
Simulation time 18691910 ps
CPU time 0.99 seconds
Started Feb 18 03:15:27 PM PST 24
Finished Feb 18 03:15:39 PM PST 24
Peak memory 214664 kb
Host smart-f7e47439-c729-4491-8723-975cba485c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702496925 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.702496925
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3138751123
Short name T693
Test name
Test status
Simulation time 917664896 ps
CPU time 4.69 seconds
Started Feb 18 03:15:28 PM PST 24
Finished Feb 18 03:15:43 PM PST 24
Peak memory 214772 kb
Host smart-a3205875-0afd-47ac-9b96-f7c1d0d329f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138751123 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3138751123
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.313013764
Short name T392
Test name
Test status
Simulation time 123456940170 ps
CPU time 1190.46 seconds
Started Feb 18 03:15:33 PM PST 24
Finished Feb 18 03:35:33 PM PST 24
Peak memory 223716 kb
Host smart-9652d346-2537-4da0-98ae-79b16947d3ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313013764 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.313013764
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.580845512
Short name T279
Test name
Test status
Simulation time 90590025 ps
CPU time 1.13 seconds
Started Feb 18 03:17:34 PM PST 24
Finished Feb 18 03:17:42 PM PST 24
Peak memory 218640 kb
Host smart-5fd48a29-e2df-4af7-a81a-1aa8bf280d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580845512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.580845512
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.1395690171
Short name T416
Test name
Test status
Simulation time 44414637 ps
CPU time 1.14 seconds
Started Feb 18 03:17:32 PM PST 24
Finished Feb 18 03:17:40 PM PST 24
Peak memory 215868 kb
Host smart-47548c65-d09b-40ba-9405-e4272183c134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395690171 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.1395690171
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3732512841
Short name T255
Test name
Test status
Simulation time 58429670 ps
CPU time 1.26 seconds
Started Feb 18 03:17:35 PM PST 24
Finished Feb 18 03:17:43 PM PST 24
Peak memory 216868 kb
Host smart-07e196de-ecf6-485c-83aa-0941e988cb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732512841 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3732512841
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.324592197
Short name T432
Test name
Test status
Simulation time 71226100 ps
CPU time 2.49 seconds
Started Feb 18 03:17:41 PM PST 24
Finished Feb 18 03:17:50 PM PST 24
Peak memory 218480 kb
Host smart-60b9d688-0878-4744-8c5a-280c434b7600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324592197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.324592197
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3340889813
Short name T818
Test name
Test status
Simulation time 146870799 ps
CPU time 1.45 seconds
Started Feb 18 03:17:41 PM PST 24
Finished Feb 18 03:17:49 PM PST 24
Peak memory 217412 kb
Host smart-28974b97-574c-4ebe-bc95-92f992722762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340889813 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3340889813
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.3037419584
Short name T577
Test name
Test status
Simulation time 39548330 ps
CPU time 1.38 seconds
Started Feb 18 03:17:38 PM PST 24
Finished Feb 18 03:17:46 PM PST 24
Peak memory 215964 kb
Host smart-6de94741-79ad-483c-b6b9-39c97251c679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037419584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.3037419584
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1093268880
Short name T698
Test name
Test status
Simulation time 130435845 ps
CPU time 1.36 seconds
Started Feb 18 03:17:35 PM PST 24
Finished Feb 18 03:17:43 PM PST 24
Peak memory 217428 kb
Host smart-becf775f-bf72-498a-b213-b072882eb94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093268880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1093268880
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.1387608424
Short name T283
Test name
Test status
Simulation time 443683520 ps
CPU time 4.02 seconds
Started Feb 18 03:17:35 PM PST 24
Finished Feb 18 03:17:46 PM PST 24
Peak memory 216364 kb
Host smart-6cb2fc8f-87a2-4ca1-a09a-a9471f8c7984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387608424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.1387608424
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1882388014
Short name T554
Test name
Test status
Simulation time 48446210 ps
CPU time 1.37 seconds
Started Feb 18 03:17:40 PM PST 24
Finished Feb 18 03:17:48 PM PST 24
Peak memory 216088 kb
Host smart-02792f24-56b6-4e81-9d74-ea7b9d576f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882388014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1882388014
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3873127113
Short name T329
Test name
Test status
Simulation time 38520963 ps
CPU time 1.58 seconds
Started Feb 18 03:17:35 PM PST 24
Finished Feb 18 03:17:44 PM PST 24
Peak memory 217208 kb
Host smart-d86a673d-9ccf-41ab-aaf3-80a2830d06f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873127113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3873127113
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3945461980
Short name T254
Test name
Test status
Simulation time 385197509 ps
CPU time 1.37 seconds
Started Feb 18 03:15:32 PM PST 24
Finished Feb 18 03:15:43 PM PST 24
Peak memory 215064 kb
Host smart-8615e71d-4795-4e34-a728-0c910ae1e5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945461980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3945461980
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2404508051
Short name T325
Test name
Test status
Simulation time 34759372 ps
CPU time 0.86 seconds
Started Feb 18 03:15:33 PM PST 24
Finished Feb 18 03:15:43 PM PST 24
Peak memory 205408 kb
Host smart-e8d0bc95-f5e2-4cdb-ae65-7c5c5f8dbe59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404508051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2404508051
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3790526777
Short name T576
Test name
Test status
Simulation time 10881150 ps
CPU time 0.88 seconds
Started Feb 18 03:15:32 PM PST 24
Finished Feb 18 03:15:42 PM PST 24
Peak memory 214828 kb
Host smart-2c35d058-c80a-4a03-bb51-7237f003d415
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790526777 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3790526777
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1689241925
Short name T441
Test name
Test status
Simulation time 39598866 ps
CPU time 1.25 seconds
Started Feb 18 03:15:30 PM PST 24
Finished Feb 18 03:15:41 PM PST 24
Peak memory 215988 kb
Host smart-988917f2-f947-4d7e-b90b-62ff59fad4a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689241925 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1689241925
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2958722235
Short name T6
Test name
Test status
Simulation time 110984379 ps
CPU time 1.04 seconds
Started Feb 18 03:15:30 PM PST 24
Finished Feb 18 03:15:41 PM PST 24
Peak memory 230744 kb
Host smart-901577c3-beb7-4875-9a12-820c8697fbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958722235 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2958722235
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.363420407
Short name T386
Test name
Test status
Simulation time 46042642 ps
CPU time 1.19 seconds
Started Feb 18 03:15:30 PM PST 24
Finished Feb 18 03:15:41 PM PST 24
Peak memory 216152 kb
Host smart-20962d9d-276c-4d80-8283-81734e192556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363420407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.363420407
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1637588371
Short name T728
Test name
Test status
Simulation time 21559070 ps
CPU time 1.16 seconds
Started Feb 18 03:15:31 PM PST 24
Finished Feb 18 03:15:42 PM PST 24
Peak memory 223500 kb
Host smart-5a020109-a576-401f-8951-c2234160a167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637588371 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1637588371
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2833617107
Short name T789
Test name
Test status
Simulation time 16393698 ps
CPU time 0.99 seconds
Started Feb 18 03:15:28 PM PST 24
Finished Feb 18 03:15:40 PM PST 24
Peak memory 214708 kb
Host smart-99170bff-484b-4ce8-b272-1dde659132b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833617107 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2833617107
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3057118567
Short name T215
Test name
Test status
Simulation time 831317759 ps
CPU time 4.45 seconds
Started Feb 18 03:15:30 PM PST 24
Finished Feb 18 03:15:44 PM PST 24
Peak memory 215816 kb
Host smart-08034119-b487-40f9-9951-30fef357dee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057118567 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3057118567
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.510298767
Short name T140
Test name
Test status
Simulation time 23987943821 ps
CPU time 544.88 seconds
Started Feb 18 03:15:33 PM PST 24
Finished Feb 18 03:24:48 PM PST 24
Peak memory 219904 kb
Host smart-205f0525-bd39-4fcd-a6fa-baa71ce53e12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510298767 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.510298767
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.18340966
Short name T490
Test name
Test status
Simulation time 27402127 ps
CPU time 1.15 seconds
Started Feb 18 03:17:37 PM PST 24
Finished Feb 18 03:17:45 PM PST 24
Peak memory 215968 kb
Host smart-e119f411-547e-4072-8e2c-37f31f8ec855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18340966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.18340966
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2193860218
Short name T474
Test name
Test status
Simulation time 141659122 ps
CPU time 1.18 seconds
Started Feb 18 03:17:33 PM PST 24
Finished Feb 18 03:17:42 PM PST 24
Peak memory 214716 kb
Host smart-97963251-90fc-4be5-bdee-eb86dc41ce62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193860218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2193860218
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1998878712
Short name T627
Test name
Test status
Simulation time 111350607 ps
CPU time 1.35 seconds
Started Feb 18 03:17:34 PM PST 24
Finished Feb 18 03:17:42 PM PST 24
Peak memory 218480 kb
Host smart-8d5149fe-8d27-4202-a14e-83c4d8127b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998878712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1998878712
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.4234063449
Short name T354
Test name
Test status
Simulation time 21201326 ps
CPU time 1.07 seconds
Started Feb 18 03:17:37 PM PST 24
Finished Feb 18 03:17:45 PM PST 24
Peak memory 215952 kb
Host smart-595f2cb7-01e7-4eab-bbce-a0948c8786c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234063449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.4234063449
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.2361573568
Short name T550
Test name
Test status
Simulation time 102790343 ps
CPU time 1.12 seconds
Started Feb 18 03:17:34 PM PST 24
Finished Feb 18 03:17:43 PM PST 24
Peak memory 217308 kb
Host smart-c83e419b-8309-4a24-9cca-e6248ff043b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361573568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.2361573568
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2669256989
Short name T824
Test name
Test status
Simulation time 45866703 ps
CPU time 1.47 seconds
Started Feb 18 03:17:34 PM PST 24
Finished Feb 18 03:17:43 PM PST 24
Peak memory 217600 kb
Host smart-20f1a52b-61ce-487d-a0d2-e0d199a8fdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669256989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2669256989
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.1432927793
Short name T570
Test name
Test status
Simulation time 35768473 ps
CPU time 1.46 seconds
Started Feb 18 03:17:36 PM PST 24
Finished Feb 18 03:17:45 PM PST 24
Peak memory 218148 kb
Host smart-315dfede-1d43-4b8a-8666-34fc89a37f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432927793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.1432927793
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1301098453
Short name T516
Test name
Test status
Simulation time 61059378 ps
CPU time 1.09 seconds
Started Feb 18 03:17:38 PM PST 24
Finished Feb 18 03:17:46 PM PST 24
Peak memory 215992 kb
Host smart-d1ab8d3f-794f-477d-a18b-6b64ef13b1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301098453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1301098453
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.4218698588
Short name T631
Test name
Test status
Simulation time 44187693 ps
CPU time 1.46 seconds
Started Feb 18 03:17:35 PM PST 24
Finished Feb 18 03:17:43 PM PST 24
Peak memory 217208 kb
Host smart-3bf40686-1782-413e-808a-67cc17db605e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218698588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.4218698588
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.2006348233
Short name T812
Test name
Test status
Simulation time 186855221 ps
CPU time 1.47 seconds
Started Feb 18 03:17:40 PM PST 24
Finished Feb 18 03:17:48 PM PST 24
Peak memory 218584 kb
Host smart-9e2665a1-e79b-4dce-b990-22cdf68481d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006348233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.2006348233
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3072149875
Short name T97
Test name
Test status
Simulation time 60422549 ps
CPU time 1.19 seconds
Started Feb 18 03:15:40 PM PST 24
Finished Feb 18 03:15:48 PM PST 24
Peak memory 215012 kb
Host smart-cb0da33b-7e11-486c-82be-44f261d650aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072149875 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3072149875
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1300383963
Short name T783
Test name
Test status
Simulation time 14822847 ps
CPU time 0.89 seconds
Started Feb 18 03:15:42 PM PST 24
Finished Feb 18 03:15:49 PM PST 24
Peak memory 205844 kb
Host smart-28138a4a-32b7-4085-bc12-e7f109b8f145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300383963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1300383963
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2030297512
Short name T145
Test name
Test status
Simulation time 70825418 ps
CPU time 0.82 seconds
Started Feb 18 03:15:38 PM PST 24
Finished Feb 18 03:15:47 PM PST 24
Peak memory 215108 kb
Host smart-65d39cd1-f494-441f-821e-2a99ced66fb4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030297512 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2030297512
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.979353504
Short name T712
Test name
Test status
Simulation time 41525293 ps
CPU time 1.38 seconds
Started Feb 18 03:15:40 PM PST 24
Finished Feb 18 03:15:49 PM PST 24
Peak memory 215976 kb
Host smart-291d2476-8850-42b7-9eb3-be0743bf3fcb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979353504 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_di
sable_auto_req_mode.979353504
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.1019253046
Short name T67
Test name
Test status
Simulation time 37937800 ps
CPU time 0.96 seconds
Started Feb 18 03:15:39 PM PST 24
Finished Feb 18 03:15:48 PM PST 24
Peak memory 218836 kb
Host smart-38f15a17-4728-43c4-b800-2427ec0cb891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019253046 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1019253046
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1776442558
Short name T135
Test name
Test status
Simulation time 58306329 ps
CPU time 1.95 seconds
Started Feb 18 03:15:33 PM PST 24
Finished Feb 18 03:15:44 PM PST 24
Peak memory 218076 kb
Host smart-b5434058-eba6-48a0-ba42-a93c073b20d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776442558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1776442558
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_smoke.4035596498
Short name T341
Test name
Test status
Simulation time 48152858 ps
CPU time 0.9 seconds
Started Feb 18 03:15:44 PM PST 24
Finished Feb 18 03:15:51 PM PST 24
Peak memory 214740 kb
Host smart-1ac0988a-cdb1-44bb-ad06-4042138ad6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035596498 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.4035596498
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.4166505321
Short name T619
Test name
Test status
Simulation time 260914995 ps
CPU time 5.51 seconds
Started Feb 18 03:15:38 PM PST 24
Finished Feb 18 03:15:51 PM PST 24
Peak memory 214804 kb
Host smart-95293831-7dd1-40df-be47-0c3fae79d04b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166505321 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.4166505321
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/260.edn_genbits.2055863966
Short name T704
Test name
Test status
Simulation time 52575172 ps
CPU time 1.26 seconds
Started Feb 18 03:17:42 PM PST 24
Finished Feb 18 03:17:49 PM PST 24
Peak memory 217124 kb
Host smart-a0385311-fdd6-4ae0-a4cd-e7c585e51ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055863966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2055863966
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.4043302975
Short name T778
Test name
Test status
Simulation time 58633348 ps
CPU time 1.77 seconds
Started Feb 18 03:17:40 PM PST 24
Finished Feb 18 03:17:49 PM PST 24
Peak memory 217232 kb
Host smart-1917eafe-67d7-4fba-b6b5-225061860213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043302975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.4043302975
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.969189934
Short name T449
Test name
Test status
Simulation time 89919097 ps
CPU time 1.19 seconds
Started Feb 18 03:17:40 PM PST 24
Finished Feb 18 03:17:48 PM PST 24
Peak memory 215812 kb
Host smart-bdbe0ee0-60ea-46d2-9bfd-80333033767d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969189934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.969189934
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2376097196
Short name T342
Test name
Test status
Simulation time 107134276 ps
CPU time 1.01 seconds
Started Feb 18 03:17:38 PM PST 24
Finished Feb 18 03:17:46 PM PST 24
Peak memory 215900 kb
Host smart-4925065a-e128-4cea-b88c-66d2d928ffea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376097196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2376097196
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.4010365154
Short name T615
Test name
Test status
Simulation time 98137757 ps
CPU time 1.25 seconds
Started Feb 18 03:17:41 PM PST 24
Finished Feb 18 03:17:49 PM PST 24
Peak memory 218676 kb
Host smart-68e829de-5555-48ff-a226-95c016d8e2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010365154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.4010365154
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3170398684
Short name T351
Test name
Test status
Simulation time 74050107 ps
CPU time 1.11 seconds
Started Feb 18 03:17:39 PM PST 24
Finished Feb 18 03:17:47 PM PST 24
Peak memory 217152 kb
Host smart-3606b219-11af-4797-96a3-a996c3e27093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170398684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3170398684
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3448816688
Short name T131
Test name
Test status
Simulation time 69199999 ps
CPU time 1.16 seconds
Started Feb 18 03:17:47 PM PST 24
Finished Feb 18 03:17:53 PM PST 24
Peak memory 217352 kb
Host smart-c521ed74-2240-4ec5-97af-a6353034e9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448816688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3448816688
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.257604622
Short name T499
Test name
Test status
Simulation time 26985659 ps
CPU time 1.29 seconds
Started Feb 18 03:17:55 PM PST 24
Finished Feb 18 03:17:59 PM PST 24
Peak memory 216180 kb
Host smart-8d86131e-9d47-4a54-bcfc-9171816d88fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257604622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.257604622
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.766495305
Short name T544
Test name
Test status
Simulation time 98816910 ps
CPU time 2.15 seconds
Started Feb 18 03:17:51 PM PST 24
Finished Feb 18 03:17:57 PM PST 24
Peak memory 218916 kb
Host smart-61b88bd7-b25a-469b-ab6e-ae2777186751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766495305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.766495305
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3097634693
Short name T493
Test name
Test status
Simulation time 80769478 ps
CPU time 1.42 seconds
Started Feb 18 03:17:57 PM PST 24
Finished Feb 18 03:18:01 PM PST 24
Peak memory 217812 kb
Host smart-2aa48ac0-5b82-4b48-98d4-901edcba5c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097634693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3097634693
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.552559679
Short name T103
Test name
Test status
Simulation time 47718081 ps
CPU time 1.15 seconds
Started Feb 18 03:15:50 PM PST 24
Finished Feb 18 03:15:58 PM PST 24
Peak memory 215012 kb
Host smart-20afe595-6f18-4f7c-904c-9dfcea69279e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552559679 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.552559679
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.1704217395
Short name T551
Test name
Test status
Simulation time 18735078 ps
CPU time 0.78 seconds
Started Feb 18 03:15:47 PM PST 24
Finished Feb 18 03:15:55 PM PST 24
Peak memory 204940 kb
Host smart-b43a913b-5d61-4118-9b89-3bcb6e93b21b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704217395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.1704217395
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3959190285
Short name T188
Test name
Test status
Simulation time 29616905 ps
CPU time 0.8 seconds
Started Feb 18 03:15:50 PM PST 24
Finished Feb 18 03:15:58 PM PST 24
Peak memory 214836 kb
Host smart-e507c971-073e-4e52-9fe5-fb275898e539
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959190285 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3959190285
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.1289066299
Short name T164
Test name
Test status
Simulation time 24517008 ps
CPU time 0.92 seconds
Started Feb 18 03:15:51 PM PST 24
Finished Feb 18 03:15:59 PM PST 24
Peak memory 217180 kb
Host smart-6ea7c619-fef9-444c-be6c-546799daf0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289066299 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1289066299
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.1850713529
Short name T390
Test name
Test status
Simulation time 32830137 ps
CPU time 1.22 seconds
Started Feb 18 03:15:43 PM PST 24
Finished Feb 18 03:15:50 PM PST 24
Peak memory 217196 kb
Host smart-070e0c4c-55b5-4c53-9d91-f68f32266bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850713529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.1850713529
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.1360049158
Short name T350
Test name
Test status
Simulation time 22653775 ps
CPU time 1.24 seconds
Started Feb 18 03:15:42 PM PST 24
Finished Feb 18 03:15:50 PM PST 24
Peak memory 222628 kb
Host smart-e7d59b16-6ea8-4314-bf55-e6a2cf4c114f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360049158 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.1360049158
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1527989922
Short name T457
Test name
Test status
Simulation time 15730838 ps
CPU time 0.97 seconds
Started Feb 18 03:15:40 PM PST 24
Finished Feb 18 03:15:48 PM PST 24
Peak memory 214680 kb
Host smart-b473a55e-83f2-46bb-a8cf-74688dc30889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527989922 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1527989922
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.3350373488
Short name T511
Test name
Test status
Simulation time 463701610 ps
CPU time 5.06 seconds
Started Feb 18 03:15:40 PM PST 24
Finished Feb 18 03:15:52 PM PST 24
Peak memory 215920 kb
Host smart-9c12cc04-1f1d-4ff9-82af-31f5d3fd79d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350373488 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.3350373488
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.3272292697
Short name T204
Test name
Test status
Simulation time 87897346440 ps
CPU time 967.92 seconds
Started Feb 18 03:15:40 PM PST 24
Finished Feb 18 03:31:55 PM PST 24
Peak memory 223220 kb
Host smart-97933886-0338-4760-8fc2-cf1ff47773dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272292697 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.3272292697
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1503255987
Short name T360
Test name
Test status
Simulation time 76696492 ps
CPU time 1.19 seconds
Started Feb 18 03:17:47 PM PST 24
Finished Feb 18 03:17:53 PM PST 24
Peak memory 217492 kb
Host smart-ce8fdf56-67bb-45bd-8f65-1a3a031e79bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503255987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1503255987
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2128904666
Short name T749
Test name
Test status
Simulation time 48963424 ps
CPU time 1.44 seconds
Started Feb 18 03:17:52 PM PST 24
Finished Feb 18 03:17:58 PM PST 24
Peak memory 217520 kb
Host smart-cce5a3e2-08b4-40a6-91ed-9429806e2ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128904666 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2128904666
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.4009112381
Short name T650
Test name
Test status
Simulation time 101145028 ps
CPU time 2.33 seconds
Started Feb 18 03:17:49 PM PST 24
Finished Feb 18 03:17:55 PM PST 24
Peak memory 216212 kb
Host smart-bccc4f94-3576-495c-8a47-7fc6bac68abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009112381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.4009112381
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.706062084
Short name T438
Test name
Test status
Simulation time 26217907 ps
CPU time 1.16 seconds
Started Feb 18 03:17:52 PM PST 24
Finished Feb 18 03:17:57 PM PST 24
Peak memory 215680 kb
Host smart-a88c328d-69f2-442b-ae48-074fbc3c0a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706062084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.706062084
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.1744585678
Short name T758
Test name
Test status
Simulation time 198225356 ps
CPU time 3.21 seconds
Started Feb 18 03:17:48 PM PST 24
Finished Feb 18 03:17:56 PM PST 24
Peak memory 217280 kb
Host smart-978fcbe0-2838-450e-b2b6-14e2a29503fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744585678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.1744585678
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.75865796
Short name T12
Test name
Test status
Simulation time 93808202 ps
CPU time 1.25 seconds
Started Feb 18 03:17:45 PM PST 24
Finished Feb 18 03:17:52 PM PST 24
Peak memory 218792 kb
Host smart-d63c58b3-0b9a-44a1-8cbf-93e7d1057b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75865796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.75865796
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.437367559
Short name T820
Test name
Test status
Simulation time 311793826 ps
CPU time 3.2 seconds
Started Feb 18 03:17:51 PM PST 24
Finished Feb 18 03:17:58 PM PST 24
Peak memory 218536 kb
Host smart-c0d3faea-aa34-49fa-8ea1-791b9dbef037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437367559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.437367559
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.1600830591
Short name T642
Test name
Test status
Simulation time 180852404 ps
CPU time 1.24 seconds
Started Feb 18 03:17:49 PM PST 24
Finished Feb 18 03:17:55 PM PST 24
Peak memory 215988 kb
Host smart-096e2019-472f-4302-ab4d-ecd562ee2b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600830591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.1600830591
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.993044863
Short name T574
Test name
Test status
Simulation time 43952224 ps
CPU time 1.47 seconds
Started Feb 18 03:17:47 PM PST 24
Finished Feb 18 03:17:53 PM PST 24
Peak memory 217340 kb
Host smart-a70de606-2c36-476c-abed-ab46ed28dcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993044863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.993044863
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.860396628
Short name T634
Test name
Test status
Simulation time 25793255 ps
CPU time 1.31 seconds
Started Feb 18 03:17:47 PM PST 24
Finished Feb 18 03:17:53 PM PST 24
Peak memory 217184 kb
Host smart-eb0751e2-a068-4ed3-9903-bd2012569d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860396628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.860396628
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1256838130
Short name T558
Test name
Test status
Simulation time 29203729 ps
CPU time 1.36 seconds
Started Feb 18 03:15:48 PM PST 24
Finished Feb 18 03:15:56 PM PST 24
Peak memory 215048 kb
Host smart-55a8f561-5fe9-4517-9f81-2b31029dfa6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256838130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1256838130
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3102747476
Short name T395
Test name
Test status
Simulation time 76823142 ps
CPU time 1 seconds
Started Feb 18 03:15:50 PM PST 24
Finished Feb 18 03:15:58 PM PST 24
Peak memory 206244 kb
Host smart-0eb7b5f2-74fb-4a3e-828a-195d1218508d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102747476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3102747476
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.691832629
Short name T744
Test name
Test status
Simulation time 35693326 ps
CPU time 0.81 seconds
Started Feb 18 03:15:45 PM PST 24
Finished Feb 18 03:15:52 PM PST 24
Peak memory 215116 kb
Host smart-2f434e24-48be-4698-97f6-27a8c020c0af
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691832629 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.691832629
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.974960460
Short name T104
Test name
Test status
Simulation time 34110229 ps
CPU time 0.84 seconds
Started Feb 18 03:15:50 PM PST 24
Finished Feb 18 03:15:58 PM PST 24
Peak memory 217224 kb
Host smart-1f2e8824-0271-4517-9a5f-ae4a76da5583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974960460 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.974960460
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.1866307292
Short name T374
Test name
Test status
Simulation time 121412337 ps
CPU time 1.21 seconds
Started Feb 18 03:15:47 PM PST 24
Finished Feb 18 03:15:55 PM PST 24
Peak memory 214804 kb
Host smart-c295aae8-0ae6-4908-9df9-4f4f520b2b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866307292 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1866307292
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2337661943
Short name T703
Test name
Test status
Simulation time 26301232 ps
CPU time 0.96 seconds
Started Feb 18 03:15:48 PM PST 24
Finished Feb 18 03:15:56 PM PST 24
Peak memory 214972 kb
Host smart-f8fcf952-e250-4077-9c0c-a972522bf52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337661943 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2337661943
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1177245994
Short name T607
Test name
Test status
Simulation time 17406944 ps
CPU time 1.02 seconds
Started Feb 18 03:15:42 PM PST 24
Finished Feb 18 03:15:49 PM PST 24
Peak memory 214752 kb
Host smart-3518d2cc-1e02-41ea-97ee-dbc0b3b21ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177245994 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1177245994
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2090290520
Short name T214
Test name
Test status
Simulation time 29552762 ps
CPU time 1.01 seconds
Started Feb 18 03:15:43 PM PST 24
Finished Feb 18 03:15:50 PM PST 24
Peak memory 205320 kb
Host smart-0cd531d2-43f6-4d03-9bdf-ece6133082ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090290520 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2090290520
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.776750090
Short name T512
Test name
Test status
Simulation time 203795734704 ps
CPU time 357.55 seconds
Started Feb 18 03:15:50 PM PST 24
Finished Feb 18 03:21:54 PM PST 24
Peak memory 223300 kb
Host smart-ba7e17f9-e93c-4baa-b1de-d333bd633fe8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776750090 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.776750090
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3744295857
Short name T707
Test name
Test status
Simulation time 59501821 ps
CPU time 1.51 seconds
Started Feb 18 03:17:47 PM PST 24
Finished Feb 18 03:17:53 PM PST 24
Peak memory 217292 kb
Host smart-ccfab490-8ea7-45e8-b77f-5c84a444023a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744295857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3744295857
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3635015484
Short name T281
Test name
Test status
Simulation time 39602720 ps
CPU time 1.63 seconds
Started Feb 18 03:17:48 PM PST 24
Finished Feb 18 03:17:54 PM PST 24
Peak memory 217236 kb
Host smart-17758260-d8d2-41fc-a626-68de94cb052b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635015484 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3635015484
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1006074334
Short name T33
Test name
Test status
Simulation time 61466285 ps
CPU time 1.35 seconds
Started Feb 18 03:17:48 PM PST 24
Finished Feb 18 03:17:54 PM PST 24
Peak memory 217196 kb
Host smart-c92c3450-18ea-4c45-8c34-8d5185463921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006074334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1006074334
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2766361503
Short name T428
Test name
Test status
Simulation time 42339394 ps
CPU time 1.1 seconds
Started Feb 18 03:17:59 PM PST 24
Finished Feb 18 03:18:02 PM PST 24
Peak memory 215928 kb
Host smart-84da134f-7fde-435f-b467-b6404cdd1fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766361503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2766361503
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.1909279807
Short name T207
Test name
Test status
Simulation time 37471428 ps
CPU time 1.39 seconds
Started Feb 18 03:17:51 PM PST 24
Finished Feb 18 03:17:57 PM PST 24
Peak memory 215860 kb
Host smart-6a43d810-9c1a-4a02-8f14-8542722c8e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909279807 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.1909279807
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.983229302
Short name T632
Test name
Test status
Simulation time 65387144 ps
CPU time 1.47 seconds
Started Feb 18 03:17:47 PM PST 24
Finished Feb 18 03:17:53 PM PST 24
Peak memory 216416 kb
Host smart-c210f7f1-8b5d-4751-aeb7-b638c07a44cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983229302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.983229302
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2290772191
Short name T442
Test name
Test status
Simulation time 23630218 ps
CPU time 1.18 seconds
Started Feb 18 03:17:50 PM PST 24
Finished Feb 18 03:17:55 PM PST 24
Peak memory 218200 kb
Host smart-8c552d6b-b16e-47a9-87ba-2613c982d766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290772191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2290772191
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.367133528
Short name T369
Test name
Test status
Simulation time 48378381 ps
CPU time 1.67 seconds
Started Feb 18 03:17:50 PM PST 24
Finished Feb 18 03:17:55 PM PST 24
Peak memory 218612 kb
Host smart-44cfa887-5d74-42af-b9e5-1e2e74b59ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367133528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.367133528
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3883555564
Short name T748
Test name
Test status
Simulation time 69396227 ps
CPU time 1.19 seconds
Started Feb 18 03:17:48 PM PST 24
Finished Feb 18 03:17:53 PM PST 24
Peak memory 217384 kb
Host smart-3f958649-9172-417b-bf39-5e4cecb89c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883555564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3883555564
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.930330324
Short name T787
Test name
Test status
Simulation time 38860131 ps
CPU time 1.2 seconds
Started Feb 18 03:17:48 PM PST 24
Finished Feb 18 03:17:54 PM PST 24
Peak memory 216148 kb
Host smart-0f4e8685-78ec-478c-8aeb-9ef00d9cd19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930330324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.930330324
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.359539223
Short name T98
Test name
Test status
Simulation time 84797077 ps
CPU time 1.15 seconds
Started Feb 18 03:15:49 PM PST 24
Finished Feb 18 03:15:57 PM PST 24
Peak memory 215004 kb
Host smart-e9a26dd2-940b-4cfb-9ab0-27631609d0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359539223 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.359539223
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1012326088
Short name T521
Test name
Test status
Simulation time 29351619 ps
CPU time 1 seconds
Started Feb 18 03:16:01 PM PST 24
Finished Feb 18 03:16:11 PM PST 24
Peak memory 205932 kb
Host smart-fc2e6689-dd46-46dc-898a-05b5cf771bfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012326088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1012326088
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2159503913
Short name T324
Test name
Test status
Simulation time 34510217 ps
CPU time 0.86 seconds
Started Feb 18 03:15:49 PM PST 24
Finished Feb 18 03:15:57 PM PST 24
Peak memory 214800 kb
Host smart-3fadb502-2fca-4c74-80c2-97efd53cec0d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159503913 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2159503913
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.913385727
Short name T58
Test name
Test status
Simulation time 78072663 ps
CPU time 1.02 seconds
Started Feb 18 03:16:01 PM PST 24
Finished Feb 18 03:16:11 PM PST 24
Peak memory 217328 kb
Host smart-c78c8fb0-6d38-40d1-b48b-bfdb92edb218
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913385727 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.913385727
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1066461455
Short name T75
Test name
Test status
Simulation time 24300658 ps
CPU time 1.16 seconds
Started Feb 18 03:16:02 PM PST 24
Finished Feb 18 03:16:12 PM PST 24
Peak memory 214856 kb
Host smart-8cd45dd7-cd60-4267-8fce-16d8e14e1484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066461455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1066461455
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.4240831578
Short name T144
Test name
Test status
Simulation time 45670087 ps
CPU time 1.59 seconds
Started Feb 18 03:15:48 PM PST 24
Finished Feb 18 03:15:57 PM PST 24
Peak memory 217316 kb
Host smart-ebe52d23-2957-42a3-917a-ce53b71ed562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240831578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.4240831578
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.1476072014
Short name T460
Test name
Test status
Simulation time 25282363 ps
CPU time 1.04 seconds
Started Feb 18 03:15:50 PM PST 24
Finished Feb 18 03:15:58 PM PST 24
Peak memory 222616 kb
Host smart-02c0afea-65d2-4431-9a5b-332b8f7e4542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476072014 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.1476072014
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3682273707
Short name T155
Test name
Test status
Simulation time 18015113 ps
CPU time 1.1 seconds
Started Feb 18 03:15:48 PM PST 24
Finished Feb 18 03:15:56 PM PST 24
Peak memory 214752 kb
Host smart-e94cabdc-9730-4141-b275-36e1b5380ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682273707 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3682273707
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3585937113
Short name T578
Test name
Test status
Simulation time 248246360 ps
CPU time 4.92 seconds
Started Feb 18 03:15:46 PM PST 24
Finished Feb 18 03:15:57 PM PST 24
Peak memory 214788 kb
Host smart-48666417-9ddb-4873-8a9a-9c3f74270f56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585937113 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3585937113
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.51121625
Short name T380
Test name
Test status
Simulation time 15835572018 ps
CPU time 385.5 seconds
Started Feb 18 03:15:48 PM PST 24
Finished Feb 18 03:22:21 PM PST 24
Peak memory 218132 kb
Host smart-0a22145a-af3b-4764-aea7-544de22f337a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51121625 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.51121625
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.3877278235
Short name T580
Test name
Test status
Simulation time 134932003 ps
CPU time 1.56 seconds
Started Feb 18 03:17:59 PM PST 24
Finished Feb 18 03:18:02 PM PST 24
Peak memory 217464 kb
Host smart-ebe699af-93b6-4dd1-be76-1b2e779f504a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877278235 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3877278235
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2649408173
Short name T834
Test name
Test status
Simulation time 71822764 ps
CPU time 1.35 seconds
Started Feb 18 03:17:52 PM PST 24
Finished Feb 18 03:17:57 PM PST 24
Peak memory 215992 kb
Host smart-1cea2c1c-faa0-4f0b-a928-cecd250599c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649408173 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2649408173
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1510970150
Short name T505
Test name
Test status
Simulation time 35080684 ps
CPU time 1.47 seconds
Started Feb 18 03:17:47 PM PST 24
Finished Feb 18 03:17:53 PM PST 24
Peak memory 217048 kb
Host smart-39800568-8d8e-4a62-89a6-02f189c3b432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510970150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1510970150
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.926446675
Short name T560
Test name
Test status
Simulation time 71405327 ps
CPU time 1.64 seconds
Started Feb 18 03:17:57 PM PST 24
Finished Feb 18 03:18:01 PM PST 24
Peak memory 217440 kb
Host smart-674914ff-fff3-45ce-a0fe-b77190703ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926446675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.926446675
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2925112596
Short name T401
Test name
Test status
Simulation time 69800766 ps
CPU time 1.08 seconds
Started Feb 18 03:17:57 PM PST 24
Finished Feb 18 03:18:01 PM PST 24
Peak memory 216008 kb
Host smart-a31e69d4-b689-414c-91ed-52ef7bc5599c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925112596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2925112596
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.682238445
Short name T328
Test name
Test status
Simulation time 97957848 ps
CPU time 1.58 seconds
Started Feb 18 03:17:58 PM PST 24
Finished Feb 18 03:18:02 PM PST 24
Peak memory 217624 kb
Host smart-29e6d887-fedd-405c-99f8-e3ba86555496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682238445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.682238445
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1791975477
Short name T691
Test name
Test status
Simulation time 47708121 ps
CPU time 1.71 seconds
Started Feb 18 03:17:58 PM PST 24
Finished Feb 18 03:18:02 PM PST 24
Peak memory 216124 kb
Host smart-5ac294bb-6ec7-4327-9fe7-e06139365ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791975477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1791975477
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1313013761
Short name T495
Test name
Test status
Simulation time 42831871 ps
CPU time 1.48 seconds
Started Feb 18 03:17:50 PM PST 24
Finished Feb 18 03:17:56 PM PST 24
Peak memory 216920 kb
Host smart-83c81697-f5ab-464b-8eee-87a77f2aabfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313013761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1313013761
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.2090004106
Short name T437
Test name
Test status
Simulation time 147518988 ps
CPU time 1.33 seconds
Started Feb 18 03:17:57 PM PST 24
Finished Feb 18 03:18:01 PM PST 24
Peak memory 218120 kb
Host smart-e50312ca-c70b-4613-927f-1ca709204248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090004106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.2090004106
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1986524231
Short name T60
Test name
Test status
Simulation time 121781914 ps
CPU time 1.24 seconds
Started Feb 18 03:14:13 PM PST 24
Finished Feb 18 03:14:25 PM PST 24
Peak memory 215024 kb
Host smart-775a9a8c-22b6-45af-bc9c-5596cf359486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986524231 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1986524231
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.1352532500
Short name T772
Test name
Test status
Simulation time 34925775 ps
CPU time 0.99 seconds
Started Feb 18 03:14:16 PM PST 24
Finished Feb 18 03:14:27 PM PST 24
Peak memory 206284 kb
Host smart-b008eeed-ff95-4caf-abfc-1b199d6648f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352532500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.1352532500
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.4125481322
Short name T406
Test name
Test status
Simulation time 133828688 ps
CPU time 0.85 seconds
Started Feb 18 03:14:15 PM PST 24
Finished Feb 18 03:14:26 PM PST 24
Peak memory 214840 kb
Host smart-ac2bbd5c-1802-4a05-adb4-022638aa8623
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125481322 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.4125481322
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.4227088891
Short name T72
Test name
Test status
Simulation time 40280089 ps
CPU time 1.25 seconds
Started Feb 18 03:14:14 PM PST 24
Finished Feb 18 03:14:26 PM PST 24
Peak memory 217100 kb
Host smart-0bb763e0-25d8-4a1e-8cca-173e4b2df5c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227088891 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.4227088891
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_genbits.420348581
Short name T403
Test name
Test status
Simulation time 62824767 ps
CPU time 2.31 seconds
Started Feb 18 03:14:12 PM PST 24
Finished Feb 18 03:14:25 PM PST 24
Peak memory 218492 kb
Host smart-d23fc4d5-014d-4355-b2a1-7a2af79a6be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420348581 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.420348581
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.18794775
Short name T126
Test name
Test status
Simulation time 33408555 ps
CPU time 0.86 seconds
Started Feb 18 03:14:19 PM PST 24
Finished Feb 18 03:14:31 PM PST 24
Peak memory 214984 kb
Host smart-cf24a0bc-1f86-406a-9e8d-1b3b5030e98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18794775 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.18794775
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_smoke.3419258124
Short name T589
Test name
Test status
Simulation time 27023586 ps
CPU time 0.99 seconds
Started Feb 18 03:14:12 PM PST 24
Finished Feb 18 03:14:23 PM PST 24
Peak memory 214752 kb
Host smart-0308cd2f-619d-42d0-b659-be6a1dfc1091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419258124 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3419258124
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1817001318
Short name T424
Test name
Test status
Simulation time 185037439 ps
CPU time 3.76 seconds
Started Feb 18 03:14:11 PM PST 24
Finished Feb 18 03:14:25 PM PST 24
Peak memory 215804 kb
Host smart-f9fc4af3-85cd-401e-a98b-943844cbbf36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817001318 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1817001318
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.1616190434
Short name T701
Test name
Test status
Simulation time 28884001031 ps
CPU time 726.92 seconds
Started Feb 18 03:14:09 PM PST 24
Finished Feb 18 03:26:27 PM PST 24
Peak memory 223264 kb
Host smart-fd8d178b-4472-462d-9437-ed5e79540343
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616190434 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.1616190434
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3349570661
Short name T616
Test name
Test status
Simulation time 27333570 ps
CPU time 1.24 seconds
Started Feb 18 03:16:02 PM PST 24
Finished Feb 18 03:16:12 PM PST 24
Peak memory 215196 kb
Host smart-a24c858e-f80d-43a0-aace-9dd5183779aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349570661 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3349570661
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.2331893000
Short name T475
Test name
Test status
Simulation time 18359978 ps
CPU time 0.94 seconds
Started Feb 18 03:15:57 PM PST 24
Finished Feb 18 03:16:06 PM PST 24
Peak memory 206200 kb
Host smart-6a0a74f6-8fb8-4ab7-a833-41cebfa420fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331893000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.2331893000
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.2419158969
Short name T161
Test name
Test status
Simulation time 17933976 ps
CPU time 0.81 seconds
Started Feb 18 03:16:00 PM PST 24
Finished Feb 18 03:16:09 PM PST 24
Peak memory 215304 kb
Host smart-a0231003-19c7-4df5-92b6-f71402e6cb6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419158969 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.2419158969
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.647229046
Short name T684
Test name
Test status
Simulation time 289775764 ps
CPU time 1.18 seconds
Started Feb 18 03:15:49 PM PST 24
Finished Feb 18 03:15:57 PM PST 24
Peak memory 217152 kb
Host smart-adc2c1f8-e5ac-437f-8031-905a51e752b7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647229046 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.647229046
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1189139081
Short name T835
Test name
Test status
Simulation time 29740619 ps
CPU time 1.37 seconds
Started Feb 18 03:15:51 PM PST 24
Finished Feb 18 03:16:00 PM PST 24
Peak memory 223496 kb
Host smart-3a076aae-0fdf-4e2d-a4f1-596005cd9f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189139081 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1189139081
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3668116757
Short name T641
Test name
Test status
Simulation time 44060959 ps
CPU time 1.53 seconds
Started Feb 18 03:15:55 PM PST 24
Finished Feb 18 03:16:03 PM PST 24
Peak memory 216924 kb
Host smart-b3aa4d2d-cc29-4cb1-aff4-41437797a8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668116757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3668116757
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.1586797016
Short name T717
Test name
Test status
Simulation time 21729417 ps
CPU time 1.25 seconds
Started Feb 18 03:16:02 PM PST 24
Finished Feb 18 03:16:12 PM PST 24
Peak memory 222748 kb
Host smart-8cc7edad-4244-432f-a3c4-632b1bdaf207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586797016 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.1586797016
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.898266831
Short name T763
Test name
Test status
Simulation time 30744189 ps
CPU time 1.06 seconds
Started Feb 18 03:15:55 PM PST 24
Finished Feb 18 03:16:03 PM PST 24
Peak memory 214652 kb
Host smart-6c2abbdf-b67a-4a6a-846b-bb19bc55baeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898266831 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.898266831
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.188052855
Short name T343
Test name
Test status
Simulation time 175664530 ps
CPU time 3.88 seconds
Started Feb 18 03:15:50 PM PST 24
Finished Feb 18 03:16:01 PM PST 24
Peak memory 216048 kb
Host smart-462401b9-fd07-4934-a805-a64a3d1fc35d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188052855 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.188052855
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3374404470
Short name T274
Test name
Test status
Simulation time 357537452224 ps
CPU time 2241.08 seconds
Started Feb 18 03:16:01 PM PST 24
Finished Feb 18 03:53:30 PM PST 24
Peak memory 225976 kb
Host smart-23f7b5ca-4945-4346-9b6c-fff7b0b66136
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374404470 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3374404470
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2199285330
Short name T579
Test name
Test status
Simulation time 44742746 ps
CPU time 1.18 seconds
Started Feb 18 03:15:49 PM PST 24
Finished Feb 18 03:15:57 PM PST 24
Peak memory 214964 kb
Host smart-f3e9348e-4492-41b3-b8ed-7abb48ed4612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199285330 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2199285330
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3931613372
Short name T52
Test name
Test status
Simulation time 53624698 ps
CPU time 0.94 seconds
Started Feb 18 03:15:52 PM PST 24
Finished Feb 18 03:15:59 PM PST 24
Peak memory 205896 kb
Host smart-77c10f2a-0ccc-4138-96db-e3374c5a3170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931613372 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3931613372
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.1760042
Short name T502
Test name
Test status
Simulation time 23640936 ps
CPU time 0.79 seconds
Started Feb 18 03:15:48 PM PST 24
Finished Feb 18 03:15:56 PM PST 24
Peak memory 215232 kb
Host smart-2cc89ea0-c187-40c3-acbd-63e3085ddb7c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760042 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1760042
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.1155764533
Short name T68
Test name
Test status
Simulation time 110849383 ps
CPU time 1.21 seconds
Started Feb 18 03:15:51 PM PST 24
Finished Feb 18 03:16:00 PM PST 24
Peak memory 215964 kb
Host smart-633f3ac8-a4cf-433b-938a-22d33a28658f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155764533 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.1155764533
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.3866324708
Short name T77
Test name
Test status
Simulation time 27269767 ps
CPU time 1.21 seconds
Started Feb 18 03:15:56 PM PST 24
Finished Feb 18 03:16:05 PM PST 24
Peak memory 216104 kb
Host smart-777f6c03-eb63-43ce-9121-dd36f9af5562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866324708 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.3866324708
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1114339227
Short name T801
Test name
Test status
Simulation time 43716593 ps
CPU time 1.43 seconds
Started Feb 18 03:15:50 PM PST 24
Finished Feb 18 03:15:58 PM PST 24
Peak memory 218208 kb
Host smart-c3fe8750-0cc9-4449-83f7-84e32883f504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114339227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1114339227
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.820720149
Short name T721
Test name
Test status
Simulation time 21793160 ps
CPU time 1.18 seconds
Started Feb 18 03:15:52 PM PST 24
Finished Feb 18 03:16:00 PM PST 24
Peak memory 222604 kb
Host smart-b1ba1ad5-2429-40a7-af5f-532edc5bf238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820720149 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.820720149
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.304723273
Short name T830
Test name
Test status
Simulation time 22030057 ps
CPU time 0.91 seconds
Started Feb 18 03:15:52 PM PST 24
Finished Feb 18 03:16:00 PM PST 24
Peak memory 214696 kb
Host smart-67ff8913-20b9-4787-9080-d4f89c6b67b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304723273 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.304723273
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.3827210861
Short name T821
Test name
Test status
Simulation time 99327825 ps
CPU time 1.39 seconds
Started Feb 18 03:15:50 PM PST 24
Finished Feb 18 03:15:58 PM PST 24
Peak memory 215812 kb
Host smart-171e427a-64f7-4f10-b022-e459199b53d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827210861 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.3827210861
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1941364682
Short name T440
Test name
Test status
Simulation time 98956581178 ps
CPU time 980.76 seconds
Started Feb 18 03:15:49 PM PST 24
Finished Feb 18 03:32:17 PM PST 24
Peak memory 221272 kb
Host smart-d605bc10-a357-4637-b8f1-8e9a6ad3f275
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941364682 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1941364682
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3703917445
Short name T739
Test name
Test status
Simulation time 27819688 ps
CPU time 1.37 seconds
Started Feb 18 03:15:58 PM PST 24
Finished Feb 18 03:16:08 PM PST 24
Peak memory 215052 kb
Host smart-07d93414-8a28-47ec-a89a-3d215d74de0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703917445 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3703917445
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.4100324973
Short name T819
Test name
Test status
Simulation time 49507057 ps
CPU time 0.79 seconds
Started Feb 18 03:15:54 PM PST 24
Finished Feb 18 03:16:01 PM PST 24
Peak memory 204920 kb
Host smart-14482e76-1a56-4e70-94e6-857e2afcb5fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100324973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.4100324973
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.693978046
Short name T638
Test name
Test status
Simulation time 14878856 ps
CPU time 0.93 seconds
Started Feb 18 03:15:53 PM PST 24
Finished Feb 18 03:16:01 PM PST 24
Peak memory 215104 kb
Host smart-8c1d2626-b923-4dd3-a67a-3346b149e5bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693978046 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.693978046
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.4165290467
Short name T526
Test name
Test status
Simulation time 35727994 ps
CPU time 1.02 seconds
Started Feb 18 03:15:53 PM PST 24
Finished Feb 18 03:16:01 PM PST 24
Peak memory 215876 kb
Host smart-76d3e1fe-e495-475c-8a9d-76b230192532
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165290467 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.4165290467
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.1947151983
Short name T409
Test name
Test status
Simulation time 30612768 ps
CPU time 0.87 seconds
Started Feb 18 03:16:03 PM PST 24
Finished Feb 18 03:16:13 PM PST 24
Peak memory 217376 kb
Host smart-adaccabb-e4d8-4e22-a4e5-41a98ea43822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947151983 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1947151983
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.1374158431
Short name T134
Test name
Test status
Simulation time 41517956 ps
CPU time 1.14 seconds
Started Feb 18 03:15:56 PM PST 24
Finished Feb 18 03:16:05 PM PST 24
Peak memory 216284 kb
Host smart-2fd69077-6f7b-4b08-acd7-d035bb3426ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374158431 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.1374158431
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.982545458
Short name T657
Test name
Test status
Simulation time 21295572 ps
CPU time 1.2 seconds
Started Feb 18 03:15:53 PM PST 24
Finished Feb 18 03:16:01 PM PST 24
Peak memory 222544 kb
Host smart-5766cdd6-4c5f-4988-9220-6fc98fc5f0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982545458 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.982545458
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2028799496
Short name T799
Test name
Test status
Simulation time 18294012 ps
CPU time 1.02 seconds
Started Feb 18 03:16:03 PM PST 24
Finished Feb 18 03:16:12 PM PST 24
Peak memory 214760 kb
Host smart-3744bfb2-7cd0-4f05-ac37-8fdded4e4eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028799496 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2028799496
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2662598091
Short name T591
Test name
Test status
Simulation time 330011495 ps
CPU time 2.37 seconds
Started Feb 18 03:15:53 PM PST 24
Finished Feb 18 03:16:02 PM PST 24
Peak memory 215948 kb
Host smart-5068e2d9-dae9-4dc7-ab9c-b11adb5f3ef7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662598091 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2662598091
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1276324363
Short name T548
Test name
Test status
Simulation time 108862115763 ps
CPU time 1442.46 seconds
Started Feb 18 03:15:54 PM PST 24
Finished Feb 18 03:40:03 PM PST 24
Peak memory 223984 kb
Host smart-c7f822a3-6e32-4249-8189-6ad77d197083
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276324363 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1276324363
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3846382009
Short name T658
Test name
Test status
Simulation time 44298201 ps
CPU time 1.24 seconds
Started Feb 18 03:15:57 PM PST 24
Finished Feb 18 03:16:07 PM PST 24
Peak memory 215040 kb
Host smart-93a84f0c-8ff6-4430-a5f7-b960de211737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846382009 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3846382009
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.442072818
Short name T741
Test name
Test status
Simulation time 11707480 ps
CPU time 0.83 seconds
Started Feb 18 03:16:03 PM PST 24
Finished Feb 18 03:16:13 PM PST 24
Peak memory 205000 kb
Host smart-9ea4affb-4f34-4b7a-899f-95d697cd33fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442072818 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.442072818
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_err.2804396598
Short name T404
Test name
Test status
Simulation time 27165787 ps
CPU time 0.87 seconds
Started Feb 18 03:16:03 PM PST 24
Finished Feb 18 03:16:13 PM PST 24
Peak memory 217112 kb
Host smart-c04e51e7-942c-40b8-ab2b-3e72e8c4c438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804396598 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2804396598
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2400948637
Short name T494
Test name
Test status
Simulation time 38368647 ps
CPU time 1.52 seconds
Started Feb 18 03:15:54 PM PST 24
Finished Feb 18 03:16:02 PM PST 24
Peak memory 218624 kb
Host smart-2c7d2aed-c461-472b-ba29-6cbac8d24358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400948637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2400948637
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.4201367739
Short name T656
Test name
Test status
Simulation time 26518798 ps
CPU time 1.06 seconds
Started Feb 18 03:15:53 PM PST 24
Finished Feb 18 03:16:01 PM PST 24
Peak memory 223476 kb
Host smart-19ad75d3-8cee-44d8-8d7a-8a3bb197f860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201367739 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.4201367739
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.560651596
Short name T552
Test name
Test status
Simulation time 26526366 ps
CPU time 0.95 seconds
Started Feb 18 03:16:02 PM PST 24
Finished Feb 18 03:16:12 PM PST 24
Peak memory 214724 kb
Host smart-e5bc0e1f-ef0f-4917-9562-388e379bd6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560651596 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.560651596
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.893766850
Short name T780
Test name
Test status
Simulation time 2953137808 ps
CPU time 4.89 seconds
Started Feb 18 03:15:57 PM PST 24
Finished Feb 18 03:16:11 PM PST 24
Peak memory 214816 kb
Host smart-6d8fcc87-9062-496d-9b84-8805c0b15147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893766850 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.893766850
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1594009596
Short name T764
Test name
Test status
Simulation time 46229600056 ps
CPU time 1032.46 seconds
Started Feb 18 03:15:56 PM PST 24
Finished Feb 18 03:33:15 PM PST 24
Peak memory 219208 kb
Host smart-572d8107-6f10-4e01-bb14-559de24ddb6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594009596 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1594009596
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.4078874499
Short name T757
Test name
Test status
Simulation time 37722847 ps
CPU time 1.18 seconds
Started Feb 18 03:16:02 PM PST 24
Finished Feb 18 03:16:12 PM PST 24
Peak memory 215036 kb
Host smart-4ea2c43a-9503-43f0-a041-f2b2a51eb9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078874499 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.4078874499
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1209409639
Short name T411
Test name
Test status
Simulation time 63425784 ps
CPU time 0.86 seconds
Started Feb 18 03:16:05 PM PST 24
Finished Feb 18 03:16:16 PM PST 24
Peak memory 205396 kb
Host smart-fa02576d-79e2-4cd4-930d-d6ff97448d90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209409639 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1209409639
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_err.3269873489
Short name T62
Test name
Test status
Simulation time 32987797 ps
CPU time 0.97 seconds
Started Feb 18 03:16:03 PM PST 24
Finished Feb 18 03:16:12 PM PST 24
Peak memory 218644 kb
Host smart-5653c588-e827-4649-ab27-a2720fe352a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269873489 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3269873489
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_intr.3821492214
Short name T336
Test name
Test status
Simulation time 40984971 ps
CPU time 0.93 seconds
Started Feb 18 03:16:04 PM PST 24
Finished Feb 18 03:16:14 PM PST 24
Peak memory 214856 kb
Host smart-eb389805-955b-41ec-86af-ff041c9db363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821492214 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3821492214
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1274658247
Short name T405
Test name
Test status
Simulation time 38809838 ps
CPU time 0.88 seconds
Started Feb 18 03:15:59 PM PST 24
Finished Feb 18 03:16:09 PM PST 24
Peak memory 214740 kb
Host smart-131c56d5-bad7-4bf3-bda2-1c039f75cdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274658247 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1274658247
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2590373490
Short name T212
Test name
Test status
Simulation time 205632214 ps
CPU time 3.08 seconds
Started Feb 18 03:15:58 PM PST 24
Finished Feb 18 03:16:09 PM PST 24
Peak memory 215768 kb
Host smart-c7485a2a-da47-46c1-a0ce-8adc11725960
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590373490 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2590373490
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2990788370
Short name T410
Test name
Test status
Simulation time 28895470190 ps
CPU time 740.97 seconds
Started Feb 18 03:16:04 PM PST 24
Finished Feb 18 03:28:34 PM PST 24
Peak memory 216800 kb
Host smart-2b54a210-31f9-4c9f-94f7-2f11b6f61db6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990788370 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2990788370
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.22562062
Short name T689
Test name
Test status
Simulation time 24208979 ps
CPU time 1.2 seconds
Started Feb 18 03:16:08 PM PST 24
Finished Feb 18 03:16:20 PM PST 24
Peak memory 215084 kb
Host smart-0dbf2fdf-fae9-435a-be1c-cdb65a37c482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22562062 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.22562062
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.737284240
Short name T331
Test name
Test status
Simulation time 27034452 ps
CPU time 0.95 seconds
Started Feb 18 03:15:59 PM PST 24
Finished Feb 18 03:16:09 PM PST 24
Peak memory 205872 kb
Host smart-7cbc2a5d-bbe9-431a-96ed-c10bc992bfb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737284240 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.737284240
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.2350486321
Short name T174
Test name
Test status
Simulation time 36928364 ps
CPU time 0.83 seconds
Started Feb 18 03:16:03 PM PST 24
Finished Feb 18 03:16:13 PM PST 24
Peak memory 215108 kb
Host smart-77277052-6894-468d-89e9-f2ab86c66668
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350486321 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.2350486321
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3139182189
Short name T69
Test name
Test status
Simulation time 64780547 ps
CPU time 1.15 seconds
Started Feb 18 03:16:00 PM PST 24
Finished Feb 18 03:16:09 PM PST 24
Peak memory 215804 kb
Host smart-c059e8de-81b8-4aab-ac3f-b2c4e8be9873
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139182189 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3139182189
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2746422955
Short name T53
Test name
Test status
Simulation time 18626072 ps
CPU time 1.21 seconds
Started Feb 18 03:16:06 PM PST 24
Finished Feb 18 03:16:17 PM PST 24
Peak memory 217488 kb
Host smart-7dd66510-cab5-48b9-9768-c3a2a00017f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746422955 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2746422955
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.245819090
Short name T345
Test name
Test status
Simulation time 65321663 ps
CPU time 1.11 seconds
Started Feb 18 03:15:58 PM PST 24
Finished Feb 18 03:16:08 PM PST 24
Peak memory 216028 kb
Host smart-c93d3dfc-f68e-4155-923d-ee3642513e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245819090 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.245819090
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.3721486440
Short name T394
Test name
Test status
Simulation time 29909452 ps
CPU time 1.06 seconds
Started Feb 18 03:16:07 PM PST 24
Finished Feb 18 03:16:19 PM PST 24
Peak memory 222624 kb
Host smart-8cd1cc74-2ee2-40ac-ba4e-6558f0b13bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721486440 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.3721486440
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2447937213
Short name T321
Test name
Test status
Simulation time 47604954 ps
CPU time 0.89 seconds
Started Feb 18 03:16:00 PM PST 24
Finished Feb 18 03:16:09 PM PST 24
Peak memory 214744 kb
Host smart-ad1b5799-3937-4d77-9720-2b01b16c4308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447937213 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2447937213
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.1428939306
Short name T614
Test name
Test status
Simulation time 1571540937 ps
CPU time 2.52 seconds
Started Feb 18 03:15:59 PM PST 24
Finished Feb 18 03:16:10 PM PST 24
Peak memory 215968 kb
Host smart-95cee718-658d-4c97-9f46-c5e7861083ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428939306 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.1428939306
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.111694918
Short name T201
Test name
Test status
Simulation time 284741913546 ps
CPU time 3451.83 seconds
Started Feb 18 03:15:57 PM PST 24
Finished Feb 18 04:13:38 PM PST 24
Peak memory 230512 kb
Host smart-5106f7a7-7771-43ac-b2e5-64b70806586f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111694918 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.111694918
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2540092112
Short name T304
Test name
Test status
Simulation time 34999265 ps
CPU time 1.26 seconds
Started Feb 18 03:16:05 PM PST 24
Finished Feb 18 03:16:15 PM PST 24
Peak memory 215048 kb
Host smart-39ef13a0-4f73-4bc4-ae8a-3fc9f95270d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540092112 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2540092112
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2423818297
Short name T344
Test name
Test status
Simulation time 15671184 ps
CPU time 0.96 seconds
Started Feb 18 03:16:03 PM PST 24
Finished Feb 18 03:16:13 PM PST 24
Peak memory 205832 kb
Host smart-2d622bc5-cf89-40d8-9da1-6721fd74ea27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423818297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2423818297
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2247213442
Short name T814
Test name
Test status
Simulation time 61821782 ps
CPU time 0.82 seconds
Started Feb 18 03:16:05 PM PST 24
Finished Feb 18 03:16:16 PM PST 24
Peak memory 214852 kb
Host smart-926b6552-380a-4d04-894f-d270cc81cd3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247213442 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2247213442
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1878094109
Short name T716
Test name
Test status
Simulation time 108053248 ps
CPU time 1.11 seconds
Started Feb 18 03:16:05 PM PST 24
Finished Feb 18 03:16:16 PM PST 24
Peak memory 215868 kb
Host smart-d74b735c-59a2-41f8-8f04-208860e031a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878094109 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1878094109
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1046190495
Short name T20
Test name
Test status
Simulation time 19940801 ps
CPU time 1.06 seconds
Started Feb 18 03:16:04 PM PST 24
Finished Feb 18 03:16:14 PM PST 24
Peak memory 217600 kb
Host smart-8bf79104-64f1-4a5a-9ae0-4bc6a2dc16aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046190495 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1046190495
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3875766882
Short name T26
Test name
Test status
Simulation time 41672059 ps
CPU time 1.7 seconds
Started Feb 18 03:16:01 PM PST 24
Finished Feb 18 03:16:12 PM PST 24
Peak memory 216040 kb
Host smart-024c8630-f530-4d5d-97a5-9586954e0675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875766882 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3875766882
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.95071077
Short name T128
Test name
Test status
Simulation time 25742712 ps
CPU time 0.91 seconds
Started Feb 18 03:16:06 PM PST 24
Finished Feb 18 03:16:17 PM PST 24
Peak memory 215200 kb
Host smart-553dd2ef-5424-4adf-a48c-bad614d8078a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95071077 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.95071077
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1474022393
Short name T414
Test name
Test status
Simulation time 71222705 ps
CPU time 0.9 seconds
Started Feb 18 03:16:01 PM PST 24
Finished Feb 18 03:16:11 PM PST 24
Peak memory 214448 kb
Host smart-154dc218-3185-41f5-b040-810b07cb0fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474022393 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1474022393
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.304930484
Short name T686
Test name
Test status
Simulation time 153862438 ps
CPU time 3.66 seconds
Started Feb 18 03:16:05 PM PST 24
Finished Feb 18 03:16:18 PM PST 24
Peak memory 214680 kb
Host smart-9fd6f691-910d-4421-9d83-eecb0ebea8ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304930484 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.304930484
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2788987615
Short name T838
Test name
Test status
Simulation time 450483378358 ps
CPU time 1803.4 seconds
Started Feb 18 03:16:03 PM PST 24
Finished Feb 18 03:46:16 PM PST 24
Peak memory 226896 kb
Host smart-3ac8733f-411f-42a6-a388-87cf51a271e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788987615 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2788987615
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1738132341
Short name T150
Test name
Test status
Simulation time 48274679 ps
CPU time 1.18 seconds
Started Feb 18 03:16:02 PM PST 24
Finished Feb 18 03:16:12 PM PST 24
Peak memory 215032 kb
Host smart-50d38ee6-c638-4f3a-90d0-c971dea58f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738132341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1738132341
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2547152930
Short name T663
Test name
Test status
Simulation time 41887856 ps
CPU time 0.87 seconds
Started Feb 18 03:16:05 PM PST 24
Finished Feb 18 03:16:15 PM PST 24
Peak memory 206236 kb
Host smart-51c546df-f4a4-4965-9ca8-bc6137f8fe1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547152930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2547152930
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.3950941917
Short name T448
Test name
Test status
Simulation time 11357739 ps
CPU time 0.9 seconds
Started Feb 18 03:16:03 PM PST 24
Finished Feb 18 03:16:13 PM PST 24
Peak memory 214796 kb
Host smart-1db68a3c-b700-46f3-8593-79aefc0df25d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950941917 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3950941917
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_err.2097316360
Short name T376
Test name
Test status
Simulation time 29777524 ps
CPU time 1.2 seconds
Started Feb 18 03:16:03 PM PST 24
Finished Feb 18 03:16:13 PM PST 24
Peak memory 230652 kb
Host smart-8834fd34-7e26-4999-890e-d72945c5a482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097316360 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.2097316360
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1342114017
Short name T359
Test name
Test status
Simulation time 37575680 ps
CPU time 1.3 seconds
Started Feb 18 03:16:04 PM PST 24
Finished Feb 18 03:16:14 PM PST 24
Peak memory 216992 kb
Host smart-0e6ea352-20c4-4e12-879d-cbe93310a224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342114017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1342114017
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2100757531
Short name T38
Test name
Test status
Simulation time 29727776 ps
CPU time 1.06 seconds
Started Feb 18 03:16:05 PM PST 24
Finished Feb 18 03:16:15 PM PST 24
Peak memory 222560 kb
Host smart-b566e5b6-3135-4d2b-a5c6-511d150d5c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100757531 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2100757531
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1659290752
Short name T573
Test name
Test status
Simulation time 34627092 ps
CPU time 0.86 seconds
Started Feb 18 03:16:03 PM PST 24
Finished Feb 18 03:16:13 PM PST 24
Peak memory 214712 kb
Host smart-b99ccb25-1cea-42dc-a6d7-f6fbf930bd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659290752 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1659290752
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.3609858860
Short name T370
Test name
Test status
Simulation time 399700194 ps
CPU time 4.45 seconds
Started Feb 18 03:16:02 PM PST 24
Finished Feb 18 03:16:15 PM PST 24
Peak memory 215828 kb
Host smart-1b9a9daa-7ba9-4885-9a75-4977f5bd55d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609858860 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.3609858860
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.3983480343
Short name T828
Test name
Test status
Simulation time 68668106804 ps
CPU time 849.67 seconds
Started Feb 18 03:16:05 PM PST 24
Finished Feb 18 03:30:24 PM PST 24
Peak memory 219208 kb
Host smart-a580f812-34af-48b0-b950-dedda3e0e77e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983480343 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.3983480343
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.3392185187
Short name T381
Test name
Test status
Simulation time 80246204 ps
CPU time 1.15 seconds
Started Feb 18 03:16:19 PM PST 24
Finished Feb 18 03:16:28 PM PST 24
Peak memory 215020 kb
Host smart-77db0d7b-afad-4803-9029-e3ce2771bca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392185187 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.3392185187
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.2689854284
Short name T34
Test name
Test status
Simulation time 13743387 ps
CPU time 0.9 seconds
Started Feb 18 03:16:11 PM PST 24
Finished Feb 18 03:16:21 PM PST 24
Peak memory 206252 kb
Host smart-3485916f-c5ec-4eaa-916a-357fc3038a8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689854284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.2689854284
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2741949219
Short name T175
Test name
Test status
Simulation time 21028686 ps
CPU time 0.87 seconds
Started Feb 18 03:16:08 PM PST 24
Finished Feb 18 03:16:19 PM PST 24
Peak memory 215240 kb
Host smart-851f4709-82d4-4369-91fb-ca3bfe28741b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741949219 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2741949219
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1615299667
Short name T80
Test name
Test status
Simulation time 35794521 ps
CPU time 1.24 seconds
Started Feb 18 03:16:14 PM PST 24
Finished Feb 18 03:16:24 PM PST 24
Peak memory 215708 kb
Host smart-702401fa-2ac4-46f0-b8ab-72c04c28819c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615299667 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1615299667
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3674103789
Short name T93
Test name
Test status
Simulation time 21804289 ps
CPU time 0.95 seconds
Started Feb 18 03:16:08 PM PST 24
Finished Feb 18 03:16:19 PM PST 24
Peak memory 217352 kb
Host smart-17ab8c9b-dc13-4265-963d-15d188796cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674103789 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3674103789
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3359701672
Short name T256
Test name
Test status
Simulation time 202624256 ps
CPU time 1.27 seconds
Started Feb 18 03:16:05 PM PST 24
Finished Feb 18 03:16:15 PM PST 24
Peak memory 215968 kb
Host smart-27969444-f55f-49ca-8f3e-531ccd5e90bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359701672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3359701672
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1168956835
Short name T809
Test name
Test status
Simulation time 21213190 ps
CPU time 1.14 seconds
Started Feb 18 03:16:16 PM PST 24
Finished Feb 18 03:16:25 PM PST 24
Peak memory 222672 kb
Host smart-0ef77c81-0df5-4c83-8eca-02d7eecec5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168956835 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1168956835
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.4093259638
Short name T652
Test name
Test status
Simulation time 26233861 ps
CPU time 0.91 seconds
Started Feb 18 03:16:03 PM PST 24
Finished Feb 18 03:16:13 PM PST 24
Peak memory 214728 kb
Host smart-a1612eda-e47a-4690-908c-c9dd73d4b49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093259638 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.4093259638
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.295086096
Short name T549
Test name
Test status
Simulation time 447973209 ps
CPU time 4.77 seconds
Started Feb 18 03:16:03 PM PST 24
Finished Feb 18 03:16:17 PM PST 24
Peak memory 214740 kb
Host smart-baf04d2b-5588-4c6a-bc50-f00366e7d554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295086096 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.295086096
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_alert.3067561514
Short name T626
Test name
Test status
Simulation time 82134299 ps
CPU time 1.13 seconds
Started Feb 18 03:16:13 PM PST 24
Finished Feb 18 03:16:23 PM PST 24
Peak memory 214976 kb
Host smart-f854893c-e397-4ac8-8129-76b9770edfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067561514 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3067561514
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3820089393
Short name T639
Test name
Test status
Simulation time 13649562 ps
CPU time 0.87 seconds
Started Feb 18 03:16:05 PM PST 24
Finished Feb 18 03:16:15 PM PST 24
Peak memory 206248 kb
Host smart-70b6a83e-4f6d-4941-8b10-8fc2e2136dcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820089393 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3820089393
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.1204873394
Short name T718
Test name
Test status
Simulation time 70524963 ps
CPU time 0.86 seconds
Started Feb 18 03:16:14 PM PST 24
Finished Feb 18 03:16:24 PM PST 24
Peak memory 215084 kb
Host smart-1dc2ce1c-85de-4568-bb98-8898798f4f87
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204873394 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1204873394
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_err.1680389800
Short name T515
Test name
Test status
Simulation time 57302597 ps
CPU time 1.3 seconds
Started Feb 18 03:16:23 PM PST 24
Finished Feb 18 03:16:31 PM PST 24
Peak memory 218568 kb
Host smart-59d976f9-cb72-4d42-b494-86b0064914d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680389800 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1680389800
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2903491731
Short name T725
Test name
Test status
Simulation time 84121530 ps
CPU time 1.14 seconds
Started Feb 18 03:16:11 PM PST 24
Finished Feb 18 03:16:22 PM PST 24
Peak memory 215840 kb
Host smart-3139b7e2-d861-4871-844d-e11b9c1b78b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903491731 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2903491731
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1175317316
Short name T585
Test name
Test status
Simulation time 34122304 ps
CPU time 0.87 seconds
Started Feb 18 03:16:08 PM PST 24
Finished Feb 18 03:16:20 PM PST 24
Peak memory 214888 kb
Host smart-820214b2-609f-417f-9db1-8ac0ffd3cb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175317316 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1175317316
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.3945853764
Short name T461
Test name
Test status
Simulation time 28083119 ps
CPU time 0.95 seconds
Started Feb 18 03:16:16 PM PST 24
Finished Feb 18 03:16:25 PM PST 24
Peak memory 214800 kb
Host smart-8a5b95c0-aa64-4726-8c5d-dfb8c44eee96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945853764 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3945853764
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.124618974
Short name T539
Test name
Test status
Simulation time 120550258 ps
CPU time 2.78 seconds
Started Feb 18 03:16:14 PM PST 24
Finished Feb 18 03:16:25 PM PST 24
Peak memory 214748 kb
Host smart-aac0ca31-de15-4185-9bec-4096086b75e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124618974 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.124618974
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.1472731003
Short name T586
Test name
Test status
Simulation time 215995987851 ps
CPU time 1349.12 seconds
Started Feb 18 03:16:14 PM PST 24
Finished Feb 18 03:38:52 PM PST 24
Peak memory 223428 kb
Host smart-bb051871-1a88-48fc-8144-822067e4dc1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472731003 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.1472731003
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3634227184
Short name T154
Test name
Test status
Simulation time 51398966 ps
CPU time 1.22 seconds
Started Feb 18 03:14:22 PM PST 24
Finished Feb 18 03:14:33 PM PST 24
Peak memory 215032 kb
Host smart-33ba5c68-3d1e-4c14-a9b8-5d494b3650be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634227184 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3634227184
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.403202866
Short name T496
Test name
Test status
Simulation time 46220391 ps
CPU time 0.93 seconds
Started Feb 18 03:14:21 PM PST 24
Finished Feb 18 03:14:32 PM PST 24
Peak memory 206208 kb
Host smart-e2ba6572-57c3-4641-81f0-5ef4f05dcbcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403202866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.403202866
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.274193136
Short name T222
Test name
Test status
Simulation time 38565839 ps
CPU time 0.86 seconds
Started Feb 18 03:14:19 PM PST 24
Finished Feb 18 03:14:30 PM PST 24
Peak memory 215136 kb
Host smart-38a65a1b-b0a8-4f7c-bbc4-f09658871c1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274193136 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.274193136
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.1057737960
Short name T57
Test name
Test status
Simulation time 25783110 ps
CPU time 1.08 seconds
Started Feb 18 03:14:19 PM PST 24
Finished Feb 18 03:14:30 PM PST 24
Peak memory 217008 kb
Host smart-72891bd6-0cdf-4892-b9f2-3cf00faa0793
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057737960 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.1057737960
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.4035157180
Short name T556
Test name
Test status
Simulation time 27371175 ps
CPU time 0.88 seconds
Started Feb 18 03:14:20 PM PST 24
Finished Feb 18 03:14:31 PM PST 24
Peak memory 217020 kb
Host smart-dfedbcdb-7a25-4eb2-8226-9040593726ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035157180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.4035157180
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1626093062
Short name T481
Test name
Test status
Simulation time 89380488 ps
CPU time 1.19 seconds
Started Feb 18 03:14:20 PM PST 24
Finished Feb 18 03:14:31 PM PST 24
Peak memory 218424 kb
Host smart-ed950bab-c6c6-4f93-9869-18154b854487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626093062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1626093062
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1428324116
Short name T451
Test name
Test status
Simulation time 71859735 ps
CPU time 0.98 seconds
Started Feb 18 03:14:20 PM PST 24
Finished Feb 18 03:14:31 PM PST 24
Peak memory 222268 kb
Host smart-b48dbfb5-957e-4e07-a613-1437d2e8e565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428324116 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1428324116
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.4250044301
Short name T120
Test name
Test status
Simulation time 27882528 ps
CPU time 0.96 seconds
Started Feb 18 03:14:15 PM PST 24
Finished Feb 18 03:14:26 PM PST 24
Peak memory 206540 kb
Host smart-e9cbdbe1-6218-4a26-8301-7a1d2c59880a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250044301 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.4250044301
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3334805773
Short name T43
Test name
Test status
Simulation time 319370775 ps
CPU time 3.07 seconds
Started Feb 18 03:14:17 PM PST 24
Finished Feb 18 03:14:31 PM PST 24
Peak memory 234904 kb
Host smart-8eac78ab-21fb-4a68-9352-2f7b0f16eb0e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334805773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3334805773
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.5843092
Short name T571
Test name
Test status
Simulation time 42207707 ps
CPU time 0.91 seconds
Started Feb 18 03:14:14 PM PST 24
Finished Feb 18 03:14:25 PM PST 24
Peak memory 214608 kb
Host smart-b1ddb732-68f3-4361-8585-b61e67630f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5843092 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.5843092
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2525608913
Short name T761
Test name
Test status
Simulation time 322897502 ps
CPU time 3.61 seconds
Started Feb 18 03:14:19 PM PST 24
Finished Feb 18 03:14:33 PM PST 24
Peak memory 216056 kb
Host smart-d394b3e9-43c8-4f55-a148-cad75d54d106
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525608913 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2525608913
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3420789190
Short name T203
Test name
Test status
Simulation time 956241419313 ps
CPU time 1692.81 seconds
Started Feb 18 03:14:18 PM PST 24
Finished Feb 18 03:42:41 PM PST 24
Peak memory 223304 kb
Host smart-69af7407-2917-4252-823f-098b2718e50f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420789190 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3420789190
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1079124453
Short name T180
Test name
Test status
Simulation time 31398643 ps
CPU time 1.21 seconds
Started Feb 18 03:16:20 PM PST 24
Finished Feb 18 03:16:29 PM PST 24
Peak memory 215100 kb
Host smart-4ffb0912-ae35-47d0-bdf3-9166b1a1ca8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079124453 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1079124453
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2884058039
Short name T831
Test name
Test status
Simulation time 108577508 ps
CPU time 0.97 seconds
Started Feb 18 03:16:14 PM PST 24
Finished Feb 18 03:16:23 PM PST 24
Peak memory 206236 kb
Host smart-8be32f17-310c-4159-a35e-fe79e632122e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884058039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2884058039
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.134031630
Short name T487
Test name
Test status
Simulation time 12375686 ps
CPU time 0.9 seconds
Started Feb 18 03:16:13 PM PST 24
Finished Feb 18 03:16:23 PM PST 24
Peak memory 214976 kb
Host smart-3406cd71-b47c-4b5c-8104-e222475fb2e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134031630 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.134031630
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3974897273
Short name T87
Test name
Test status
Simulation time 44970037 ps
CPU time 1.38 seconds
Started Feb 18 03:16:12 PM PST 24
Finished Feb 18 03:16:23 PM PST 24
Peak memory 215864 kb
Host smart-ae643d33-5e50-44f1-800d-4dfbd5a2eac7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974897273 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3974897273
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.258603478
Short name T719
Test name
Test status
Simulation time 28909030 ps
CPU time 1.35 seconds
Started Feb 18 03:16:12 PM PST 24
Finished Feb 18 03:16:23 PM PST 24
Peak memory 223464 kb
Host smart-f4f05ab9-4d75-41bd-9b90-ce90b89f8c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258603478 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.258603478
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.4099070010
Short name T581
Test name
Test status
Simulation time 215442518 ps
CPU time 1.11 seconds
Started Feb 18 03:16:12 PM PST 24
Finished Feb 18 03:16:22 PM PST 24
Peak memory 215976 kb
Host smart-e28ee544-9ce7-44b9-b4d7-11bc714951da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099070010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.4099070010
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.2248183131
Short name T562
Test name
Test status
Simulation time 51255193 ps
CPU time 0.79 seconds
Started Feb 18 03:16:16 PM PST 24
Finished Feb 18 03:16:25 PM PST 24
Peak memory 214972 kb
Host smart-01101560-d0e8-4650-9dab-65b5450ce736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248183131 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.2248183131
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3325745577
Short name T513
Test name
Test status
Simulation time 88985719 ps
CPU time 0.91 seconds
Started Feb 18 03:16:20 PM PST 24
Finished Feb 18 03:16:29 PM PST 24
Peak memory 214716 kb
Host smart-1ad30e5c-3d6c-44ab-8a26-3c78e745b00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325745577 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3325745577
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.2465366842
Short name T786
Test name
Test status
Simulation time 941706137 ps
CPU time 5.45 seconds
Started Feb 18 03:16:19 PM PST 24
Finished Feb 18 03:16:32 PM PST 24
Peak memory 219092 kb
Host smart-906d5dff-b82c-461a-8122-2df71545a560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465366842 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.2465366842
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3869547710
Short name T519
Test name
Test status
Simulation time 125527805941 ps
CPU time 626.42 seconds
Started Feb 18 03:16:22 PM PST 24
Finished Feb 18 03:26:56 PM PST 24
Peak memory 220624 kb
Host smart-6fe0320f-7848-446c-9902-47a92a51e947
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869547710 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3869547710
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1736445489
Short name T301
Test name
Test status
Simulation time 34342941 ps
CPU time 1.28 seconds
Started Feb 18 03:16:12 PM PST 24
Finished Feb 18 03:16:23 PM PST 24
Peak memory 215036 kb
Host smart-6b21b7bf-5460-4da1-b511-11c470367494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736445489 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1736445489
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1505722337
Short name T776
Test name
Test status
Simulation time 40274856 ps
CPU time 0.95 seconds
Started Feb 18 03:16:27 PM PST 24
Finished Feb 18 03:16:33 PM PST 24
Peak memory 206304 kb
Host smart-b8eedd73-4efd-4441-9675-f105593a6649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505722337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1505722337
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.1895104659
Short name T170
Test name
Test status
Simulation time 20456508 ps
CPU time 0.97 seconds
Started Feb 18 03:16:22 PM PST 24
Finished Feb 18 03:16:30 PM PST 24
Peak memory 215292 kb
Host smart-f79f0f50-6c94-4c87-8a1c-7bda4f55cb2f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895104659 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.1895104659
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.3170527963
Short name T644
Test name
Test status
Simulation time 31621045 ps
CPU time 1.2 seconds
Started Feb 18 03:16:18 PM PST 24
Finished Feb 18 03:16:27 PM PST 24
Peak memory 215824 kb
Host smart-abb7ab51-bedd-459b-ad66-7ca17fb99c04
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170527963 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.3170527963
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.38415096
Short name T387
Test name
Test status
Simulation time 28227683 ps
CPU time 1.12 seconds
Started Feb 18 03:16:11 PM PST 24
Finished Feb 18 03:16:22 PM PST 24
Peak memory 230684 kb
Host smart-eb00839d-6f07-473a-bb84-1990dbe8c986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38415096 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.38415096
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2252980303
Short name T754
Test name
Test status
Simulation time 59393291 ps
CPU time 2.07 seconds
Started Feb 18 03:16:16 PM PST 24
Finished Feb 18 03:16:26 PM PST 24
Peak memory 217072 kb
Host smart-b07e168c-72bc-4f96-9c2e-02440d1ce6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252980303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2252980303
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.2318056902
Short name T480
Test name
Test status
Simulation time 20435542 ps
CPU time 1.02 seconds
Started Feb 18 03:16:16 PM PST 24
Finished Feb 18 03:16:25 PM PST 24
Peak memory 215164 kb
Host smart-9752a410-4d20-41fd-a475-204c51b389e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318056902 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.2318056902
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1671444032
Short name T391
Test name
Test status
Simulation time 21496193 ps
CPU time 0.88 seconds
Started Feb 18 03:16:12 PM PST 24
Finished Feb 18 03:16:22 PM PST 24
Peak memory 214772 kb
Host smart-c617056e-d7a8-4154-9d31-1c1a6ec3f71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671444032 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1671444032
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1408853198
Short name T648
Test name
Test status
Simulation time 324576354 ps
CPU time 5.76 seconds
Started Feb 18 03:16:18 PM PST 24
Finished Feb 18 03:16:32 PM PST 24
Peak memory 214756 kb
Host smart-50a510f2-692b-4fdb-85c0-4f9a6007569f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408853198 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1408853198
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.1326667824
Short name T195
Test name
Test status
Simulation time 40475207480 ps
CPU time 277.66 seconds
Started Feb 18 03:16:13 PM PST 24
Finished Feb 18 03:21:00 PM PST 24
Peak memory 217748 kb
Host smart-bc99665a-9287-465a-8633-36265dd2d713
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326667824 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.1326667824
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3486624341
Short name T733
Test name
Test status
Simulation time 91888936 ps
CPU time 1.26 seconds
Started Feb 18 03:16:25 PM PST 24
Finished Feb 18 03:16:32 PM PST 24
Peak memory 215032 kb
Host smart-f884cea5-6a7d-4b7e-a8b3-7740d97c9f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486624341 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3486624341
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2170300216
Short name T349
Test name
Test status
Simulation time 17900395 ps
CPU time 0.98 seconds
Started Feb 18 03:16:26 PM PST 24
Finished Feb 18 03:16:33 PM PST 24
Peak memory 206152 kb
Host smart-8ade2673-fe92-4652-bb9d-8dbb20c7073d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170300216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2170300216
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3132953440
Short name T106
Test name
Test status
Simulation time 15847501 ps
CPU time 0.83 seconds
Started Feb 18 03:16:17 PM PST 24
Finished Feb 18 03:16:26 PM PST 24
Peak memory 215088 kb
Host smart-277ee248-bd6c-4f8a-b159-ec2b4657f94f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132953440 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3132953440
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.3438541323
Short name T64
Test name
Test status
Simulation time 42324491 ps
CPU time 1.4 seconds
Started Feb 18 03:16:19 PM PST 24
Finished Feb 18 03:16:28 PM PST 24
Peak memory 215708 kb
Host smart-61c53f8b-dc6e-4c80-a277-af2a9abb612c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438541323 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.3438541323
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.425408863
Short name T101
Test name
Test status
Simulation time 49707672 ps
CPU time 1.02 seconds
Started Feb 18 03:16:27 PM PST 24
Finished Feb 18 03:16:33 PM PST 24
Peak memory 230496 kb
Host smart-defb49c0-2052-455f-bb29-3da5e8b0c057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425408863 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.425408863
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3854871402
Short name T592
Test name
Test status
Simulation time 26102925 ps
CPU time 1.41 seconds
Started Feb 18 03:16:27 PM PST 24
Finished Feb 18 03:16:33 PM PST 24
Peak memory 216468 kb
Host smart-4e96064c-2d14-4ddf-856f-327451ce9b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854871402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3854871402
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.280985786
Short name T692
Test name
Test status
Simulation time 30895582 ps
CPU time 0.94 seconds
Started Feb 18 03:16:19 PM PST 24
Finished Feb 18 03:16:28 PM PST 24
Peak memory 214760 kb
Host smart-277f762b-68bc-4513-84c0-f67f9dd6ec3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280985786 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.280985786
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3091475596
Short name T458
Test name
Test status
Simulation time 42648007 ps
CPU time 0.94 seconds
Started Feb 18 03:16:17 PM PST 24
Finished Feb 18 03:16:26 PM PST 24
Peak memory 214716 kb
Host smart-4792376e-496d-40ee-a5a1-7a8b48fc5660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091475596 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3091475596
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2065478738
Short name T419
Test name
Test status
Simulation time 1209426657 ps
CPU time 4.99 seconds
Started Feb 18 03:16:31 PM PST 24
Finished Feb 18 03:16:41 PM PST 24
Peak memory 216056 kb
Host smart-b2c60245-8725-4f37-a142-f55a1f850a78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065478738 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2065478738
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2858538314
Short name T794
Test name
Test status
Simulation time 311667008852 ps
CPU time 1932.23 seconds
Started Feb 18 03:16:17 PM PST 24
Finished Feb 18 03:48:37 PM PST 24
Peak memory 227856 kb
Host smart-445171c4-db84-41df-b045-87826b3cfa36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858538314 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2858538314
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1942384430
Short name T184
Test name
Test status
Simulation time 104345508 ps
CPU time 1.41 seconds
Started Feb 18 03:16:18 PM PST 24
Finished Feb 18 03:16:27 PM PST 24
Peak memory 215036 kb
Host smart-01b955cc-c8ae-45e9-bd37-b9db3fd1321f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942384430 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1942384430
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3758857224
Short name T443
Test name
Test status
Simulation time 82127907 ps
CPU time 0.91 seconds
Started Feb 18 03:16:23 PM PST 24
Finished Feb 18 03:16:31 PM PST 24
Peak memory 206252 kb
Host smart-548102b0-a5c7-4cde-a976-f625a192cf60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758857224 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3758857224
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.781038019
Short name T700
Test name
Test status
Simulation time 12635805 ps
CPU time 0.91 seconds
Started Feb 18 03:16:31 PM PST 24
Finished Feb 18 03:16:37 PM PST 24
Peak memory 215432 kb
Host smart-e8e3d248-3b70-4d36-896c-3761630105c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781038019 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.781038019
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_err.704590117
Short name T84
Test name
Test status
Simulation time 42957273 ps
CPU time 1.07 seconds
Started Feb 18 03:16:20 PM PST 24
Finished Feb 18 03:16:29 PM PST 24
Peak memory 229072 kb
Host smart-1268b3dc-51a3-4038-820b-c1af74f8a06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704590117 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.704590117
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.4030546992
Short name T594
Test name
Test status
Simulation time 38985201 ps
CPU time 1.07 seconds
Started Feb 18 03:16:14 PM PST 24
Finished Feb 18 03:16:24 PM PST 24
Peak memory 215972 kb
Host smart-eb77b26f-8e0f-4fe8-8564-9eda629bfb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030546992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.4030546992
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.100963208
Short name T462
Test name
Test status
Simulation time 27980293 ps
CPU time 1 seconds
Started Feb 18 03:16:15 PM PST 24
Finished Feb 18 03:16:24 PM PST 24
Peak memory 214960 kb
Host smart-33bfe6a8-f070-4b83-a648-8f55943b280a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100963208 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.100963208
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3486289266
Short name T335
Test name
Test status
Simulation time 134063968 ps
CPU time 0.98 seconds
Started Feb 18 03:16:22 PM PST 24
Finished Feb 18 03:16:30 PM PST 24
Peak memory 214712 kb
Host smart-c061fe31-42b0-4383-a2fc-686f30b56722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486289266 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3486289266
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1368939822
Short name T745
Test name
Test status
Simulation time 549939331 ps
CPU time 3.64 seconds
Started Feb 18 03:16:18 PM PST 24
Finished Feb 18 03:16:30 PM PST 24
Peak memory 216116 kb
Host smart-93bd8018-0004-4c4c-840f-e2cf2e9ada54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368939822 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1368939822
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3449841760
Short name T804
Test name
Test status
Simulation time 101455075099 ps
CPU time 701.7 seconds
Started Feb 18 03:16:24 PM PST 24
Finished Feb 18 03:28:12 PM PST 24
Peak memory 219268 kb
Host smart-d6ee8eb8-e4de-422e-a5a8-9709098396c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449841760 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3449841760
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.487700590
Short name T617
Test name
Test status
Simulation time 80252302 ps
CPU time 1.29 seconds
Started Feb 18 03:16:27 PM PST 24
Finished Feb 18 03:16:33 PM PST 24
Peak memory 215040 kb
Host smart-5fe8d9af-c06d-48ae-abe3-fcdf071e390b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487700590 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.487700590
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1125338371
Short name T463
Test name
Test status
Simulation time 13731616 ps
CPU time 0.88 seconds
Started Feb 18 03:16:24 PM PST 24
Finished Feb 18 03:16:32 PM PST 24
Peak memory 205848 kb
Host smart-17544e2f-6397-43e2-8e92-1df551edd1e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125338371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1125338371
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2229069033
Short name T113
Test name
Test status
Simulation time 13352010 ps
CPU time 0.95 seconds
Started Feb 18 03:16:26 PM PST 24
Finished Feb 18 03:16:33 PM PST 24
Peak memory 215272 kb
Host smart-89565c7a-d846-4609-b8df-f5d17457cacb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229069033 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2229069033
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.1543760196
Short name T176
Test name
Test status
Simulation time 41557698 ps
CPU time 1.22 seconds
Started Feb 18 03:16:29 PM PST 24
Finished Feb 18 03:16:36 PM PST 24
Peak memory 215928 kb
Host smart-479d759b-a177-47f3-8b3b-9410d52e716f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543760196 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.1543760196
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2022300014
Short name T583
Test name
Test status
Simulation time 25671284 ps
CPU time 1.2 seconds
Started Feb 18 03:16:22 PM PST 24
Finished Feb 18 03:16:31 PM PST 24
Peak memory 216048 kb
Host smart-dc63080a-4856-4b79-b6dc-be102d439d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022300014 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2022300014
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.768160594
Short name T702
Test name
Test status
Simulation time 51254416 ps
CPU time 1.22 seconds
Started Feb 18 03:16:22 PM PST 24
Finished Feb 18 03:16:31 PM PST 24
Peak memory 215960 kb
Host smart-4c051533-d38b-4cc5-95cb-a917cf77739f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768160594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.768160594
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2737091191
Short name T705
Test name
Test status
Simulation time 22198369 ps
CPU time 1.03 seconds
Started Feb 18 03:16:30 PM PST 24
Finished Feb 18 03:16:36 PM PST 24
Peak memory 214872 kb
Host smart-98c37d40-09c8-4da6-9495-9b007e96a4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737091191 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2737091191
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3969818142
Short name T379
Test name
Test status
Simulation time 16782700 ps
CPU time 1.03 seconds
Started Feb 18 03:16:25 PM PST 24
Finished Feb 18 03:16:32 PM PST 24
Peak memory 214708 kb
Host smart-3fe7cfbd-334b-46ae-a643-7fe5072ae745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969818142 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3969818142
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2059520582
Short name T137
Test name
Test status
Simulation time 552173249 ps
CPU time 5.19 seconds
Started Feb 18 03:16:31 PM PST 24
Finished Feb 18 03:16:41 PM PST 24
Peak memory 218172 kb
Host smart-d139e2b6-007a-4ea4-a4c0-ce24c076a3ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059520582 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2059520582
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1466704378
Short name T202
Test name
Test status
Simulation time 134308315067 ps
CPU time 708.61 seconds
Started Feb 18 03:16:30 PM PST 24
Finished Feb 18 03:28:24 PM PST 24
Peak memory 219108 kb
Host smart-e5518671-6847-4437-9921-7c68d194779a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466704378 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1466704378
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3320121727
Short name T147
Test name
Test status
Simulation time 28195753 ps
CPU time 1.26 seconds
Started Feb 18 03:16:23 PM PST 24
Finished Feb 18 03:16:31 PM PST 24
Peak memory 215000 kb
Host smart-a43cd4cf-dd33-4cd5-9dbc-e50d2976ef65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320121727 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3320121727
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2585942628
Short name T308
Test name
Test status
Simulation time 32020015 ps
CPU time 0.91 seconds
Started Feb 18 03:16:28 PM PST 24
Finished Feb 18 03:16:35 PM PST 24
Peak memory 205876 kb
Host smart-b1537c3b-ce1e-47d0-acb5-ce8ad32df5fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585942628 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2585942628
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1674273317
Short name T183
Test name
Test status
Simulation time 23186866 ps
CPU time 0.88 seconds
Started Feb 18 03:16:25 PM PST 24
Finished Feb 18 03:16:32 PM PST 24
Peak memory 215068 kb
Host smart-9ecf22d0-c371-48f2-86ed-a163bbe3218c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674273317 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1674273317
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.507749645
Short name T537
Test name
Test status
Simulation time 61007554 ps
CPU time 1.13 seconds
Started Feb 18 03:16:30 PM PST 24
Finished Feb 18 03:16:36 PM PST 24
Peak memory 217044 kb
Host smart-9c192926-fbff-4185-95ad-8679782ed20d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507749645 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.507749645
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.340602563
Short name T39
Test name
Test status
Simulation time 39929562 ps
CPU time 0.95 seconds
Started Feb 18 03:16:28 PM PST 24
Finished Feb 18 03:16:35 PM PST 24
Peak memory 222228 kb
Host smart-c90c8a9b-2583-4015-a646-ea71ed544e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340602563 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.340602563
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.2617477635
Short name T276
Test name
Test status
Simulation time 50772617 ps
CPU time 1.42 seconds
Started Feb 18 03:16:24 PM PST 24
Finished Feb 18 03:16:32 PM PST 24
Peak memory 217480 kb
Host smart-e8d3ac6e-61da-4432-8cfc-c472f9c6dee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617477635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2617477635
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_smoke.892286328
Short name T319
Test name
Test status
Simulation time 66349759 ps
CPU time 0.86 seconds
Started Feb 18 03:16:30 PM PST 24
Finished Feb 18 03:16:36 PM PST 24
Peak memory 214748 kb
Host smart-f50f4d13-2b0c-44f2-9f4c-a6e4ab5935a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892286328 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.892286328
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1623038673
Short name T216
Test name
Test status
Simulation time 257124624 ps
CPU time 3.56 seconds
Started Feb 18 03:16:25 PM PST 24
Finished Feb 18 03:16:35 PM PST 24
Peak memory 215668 kb
Host smart-d994afa3-4c00-48b2-8c04-e7ce39a3514f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623038673 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1623038673
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_alert.876346168
Short name T96
Test name
Test status
Simulation time 72125130 ps
CPU time 1.11 seconds
Started Feb 18 03:16:28 PM PST 24
Finished Feb 18 03:16:35 PM PST 24
Peak memory 214984 kb
Host smart-cb302dea-95ed-4c78-8b84-f4cdb217a707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876346168 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.876346168
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3312151077
Short name T610
Test name
Test status
Simulation time 20772909 ps
CPU time 1 seconds
Started Feb 18 03:16:29 PM PST 24
Finished Feb 18 03:16:35 PM PST 24
Peak memory 206236 kb
Host smart-60c5987c-0328-4f0c-85df-50e5cfb0ece2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312151077 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3312151077
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1752103712
Short name T538
Test name
Test status
Simulation time 13277072 ps
CPU time 0.88 seconds
Started Feb 18 03:16:29 PM PST 24
Finished Feb 18 03:16:35 PM PST 24
Peak memory 206820 kb
Host smart-a5682382-ae6c-4205-93b9-2121412a37ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752103712 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1752103712
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3674476089
Short name T65
Test name
Test status
Simulation time 146300965 ps
CPU time 1.09 seconds
Started Feb 18 03:16:31 PM PST 24
Finished Feb 18 03:16:37 PM PST 24
Peak memory 215896 kb
Host smart-ade27d8a-6932-4f8e-8203-8e4550d6a16f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674476089 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3674476089
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.2439450908
Short name T356
Test name
Test status
Simulation time 41154744 ps
CPU time 1.12 seconds
Started Feb 18 03:16:28 PM PST 24
Finished Feb 18 03:16:35 PM PST 24
Peak memory 218384 kb
Host smart-eebcd29a-5c62-4833-9c90-dc89a5c29027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439450908 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.2439450908
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2926059119
Short name T439
Test name
Test status
Simulation time 85759106 ps
CPU time 1.51 seconds
Started Feb 18 03:16:31 PM PST 24
Finished Feb 18 03:16:37 PM PST 24
Peak memory 217896 kb
Host smart-b2bb360a-7143-4c97-a431-568d38d010b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926059119 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2926059119
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.1129479108
Short name T666
Test name
Test status
Simulation time 27322471 ps
CPU time 0.98 seconds
Started Feb 18 03:16:31 PM PST 24
Finished Feb 18 03:16:37 PM PST 24
Peak memory 215008 kb
Host smart-09d32e81-5be4-4147-80ef-5ac648fe1a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129479108 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.1129479108
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1614740215
Short name T469
Test name
Test status
Simulation time 17251958 ps
CPU time 1.01 seconds
Started Feb 18 03:16:37 PM PST 24
Finished Feb 18 03:16:43 PM PST 24
Peak memory 214788 kb
Host smart-0e9bd90a-1d9b-46ef-9119-6655a97b28e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614740215 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1614740215
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1496392304
Short name T141
Test name
Test status
Simulation time 1115321198 ps
CPU time 4.12 seconds
Started Feb 18 03:16:35 PM PST 24
Finished Feb 18 03:16:44 PM PST 24
Peak memory 214752 kb
Host smart-fba7aa40-940e-40ee-9e5c-6a2754ee5aae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496392304 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1496392304
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1635966367
Short name T219
Test name
Test status
Simulation time 22651188758 ps
CPU time 298.16 seconds
Started Feb 18 03:16:31 PM PST 24
Finished Feb 18 03:21:34 PM PST 24
Peak memory 219132 kb
Host smart-dc866473-7b1b-45f5-ab48-92415a6051dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635966367 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1635966367
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.405825635
Short name T303
Test name
Test status
Simulation time 78677055 ps
CPU time 1.21 seconds
Started Feb 18 03:16:34 PM PST 24
Finished Feb 18 03:16:40 PM PST 24
Peak memory 215048 kb
Host smart-6cfd7ccd-5c2e-456b-983c-d681e253ab25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405825635 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.405825635
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.4082513723
Short name T152
Test name
Test status
Simulation time 70462235 ps
CPU time 1.02 seconds
Started Feb 18 03:16:34 PM PST 24
Finished Feb 18 03:16:39 PM PST 24
Peak memory 205860 kb
Host smart-2bc86020-7754-40d2-b275-009ea6857ef0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082513723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.4082513723
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.4082701521
Short name T108
Test name
Test status
Simulation time 49852813 ps
CPU time 0.82 seconds
Started Feb 18 03:16:33 PM PST 24
Finished Feb 18 03:16:39 PM PST 24
Peak memory 215132 kb
Host smart-93c24fa3-087f-4b8b-8de8-316e9a441abe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082701521 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.4082701521
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_err.541207789
Short name T625
Test name
Test status
Simulation time 160346708 ps
CPU time 0.93 seconds
Started Feb 18 03:16:36 PM PST 24
Finished Feb 18 03:16:43 PM PST 24
Peak memory 217192 kb
Host smart-9e6945bc-1dcf-4bbb-bf19-d7e35e9e6c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541207789 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.541207789
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.857763264
Short name T431
Test name
Test status
Simulation time 80320825 ps
CPU time 1.91 seconds
Started Feb 18 03:16:38 PM PST 24
Finished Feb 18 03:16:45 PM PST 24
Peak memory 217668 kb
Host smart-64e1a0c8-76a3-48b2-94b9-f4ffe7b2b8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857763264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.857763264
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.836071982
Short name T130
Test name
Test status
Simulation time 21365542 ps
CPU time 1.09 seconds
Started Feb 18 03:16:33 PM PST 24
Finished Feb 18 03:16:38 PM PST 24
Peak memory 215180 kb
Host smart-1b06b1d7-b869-4236-be74-08df04302390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836071982 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.836071982
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.4165500717
Short name T352
Test name
Test status
Simulation time 45723198 ps
CPU time 0.92 seconds
Started Feb 18 03:16:36 PM PST 24
Finished Feb 18 03:16:42 PM PST 24
Peak memory 214696 kb
Host smart-b2929ecc-cf50-490c-b02a-13d478210179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165500717 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.4165500717
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.2983590322
Short name T655
Test name
Test status
Simulation time 546348006 ps
CPU time 1.79 seconds
Started Feb 18 03:16:32 PM PST 24
Finished Feb 18 03:16:39 PM PST 24
Peak memory 215956 kb
Host smart-7d843d6a-38bd-403f-86fa-f1752e3af323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983590322 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.2983590322
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.536933578
Short name T455
Test name
Test status
Simulation time 79440478840 ps
CPU time 1874.29 seconds
Started Feb 18 03:16:33 PM PST 24
Finished Feb 18 03:47:52 PM PST 24
Peak memory 224668 kb
Host smart-29fbb598-4aa9-4a7c-bce5-0545b9c3b5b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536933578 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.536933578
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert_test.659882403
Short name T575
Test name
Test status
Simulation time 15411283 ps
CPU time 0.97 seconds
Started Feb 18 03:16:32 PM PST 24
Finished Feb 18 03:16:38 PM PST 24
Peak memory 206248 kb
Host smart-433b3dc9-d0fc-450b-b3b8-666d05601be6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659882403 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.659882403
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2667740004
Short name T162
Test name
Test status
Simulation time 16250290 ps
CPU time 0.86 seconds
Started Feb 18 03:16:38 PM PST 24
Finished Feb 18 03:16:44 PM PST 24
Peak memory 215088 kb
Host smart-6fb5f375-2806-4d81-8b67-1ba55d664b32
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667740004 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2667740004
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_err.1979719409
Short name T177
Test name
Test status
Simulation time 21762652 ps
CPU time 0.98 seconds
Started Feb 18 03:16:35 PM PST 24
Finished Feb 18 03:16:41 PM PST 24
Peak memory 218900 kb
Host smart-0a8c811f-5dd1-4cfb-8e1b-afe41df21ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979719409 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1979719409
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1028060259
Short name T760
Test name
Test status
Simulation time 68084431 ps
CPU time 2.29 seconds
Started Feb 18 03:16:34 PM PST 24
Finished Feb 18 03:16:41 PM PST 24
Peak memory 216136 kb
Host smart-05ec8563-6b63-400a-95a5-f25efe0c9108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028060259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1028060259
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.127509625
Short name T766
Test name
Test status
Simulation time 25762511 ps
CPU time 1 seconds
Started Feb 18 03:16:34 PM PST 24
Finished Feb 18 03:16:40 PM PST 24
Peak memory 214972 kb
Host smart-5aff2232-6e27-482f-a583-493e61ca792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127509625 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.127509625
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.667847337
Short name T225
Test name
Test status
Simulation time 16293303 ps
CPU time 1 seconds
Started Feb 18 03:16:34 PM PST 24
Finished Feb 18 03:16:40 PM PST 24
Peak memory 214740 kb
Host smart-36fc3906-449c-4b2c-a823-2450f86ecda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667847337 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.667847337
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.3873572427
Short name T545
Test name
Test status
Simulation time 259669994 ps
CPU time 5.37 seconds
Started Feb 18 03:16:36 PM PST 24
Finished Feb 18 03:16:46 PM PST 24
Peak memory 214784 kb
Host smart-e2c30215-e9be-468b-b747-4bfc97089dbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873572427 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.3873572427
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3673864789
Short name T565
Test name
Test status
Simulation time 314049265081 ps
CPU time 2531.97 seconds
Started Feb 18 03:16:33 PM PST 24
Finished Feb 18 03:58:49 PM PST 24
Peak memory 227132 kb
Host smart-a027412e-e303-4b41-a875-89ab8b4bdfd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673864789 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3673864789
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2325928240
Short name T672
Test name
Test status
Simulation time 71695078 ps
CPU time 1.23 seconds
Started Feb 18 03:16:35 PM PST 24
Finished Feb 18 03:16:41 PM PST 24
Peak memory 215028 kb
Host smart-369c707f-3c6b-42a4-a758-92d524736963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325928240 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2325928240
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1631648576
Short name T420
Test name
Test status
Simulation time 52370089 ps
CPU time 0.89 seconds
Started Feb 18 03:16:36 PM PST 24
Finished Feb 18 03:16:42 PM PST 24
Peak memory 206212 kb
Host smart-50b8defa-794b-4334-9156-a90bdd4c3ba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631648576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1631648576
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2576322610
Short name T110
Test name
Test status
Simulation time 15077274 ps
CPU time 0.86 seconds
Started Feb 18 03:16:34 PM PST 24
Finished Feb 18 03:16:40 PM PST 24
Peak memory 215076 kb
Host smart-99743772-9085-402e-9571-7730db0df6f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576322610 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2576322610
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_err.1806186207
Short name T536
Test name
Test status
Simulation time 73180292 ps
CPU time 0.94 seconds
Started Feb 18 03:16:35 PM PST 24
Finished Feb 18 03:16:41 PM PST 24
Peak memory 222384 kb
Host smart-e61b32cb-9358-41ce-8550-94c0caa0f7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806186207 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1806186207
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3778724915
Short name T667
Test name
Test status
Simulation time 119614144 ps
CPU time 1.14 seconds
Started Feb 18 03:16:36 PM PST 24
Finished Feb 18 03:16:42 PM PST 24
Peak memory 216168 kb
Host smart-b2eeb16e-f1f8-4e88-94b6-99402e8af7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778724915 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3778724915
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1234074500
Short name T355
Test name
Test status
Simulation time 32154555 ps
CPU time 0.94 seconds
Started Feb 18 03:16:34 PM PST 24
Finished Feb 18 03:16:40 PM PST 24
Peak memory 222740 kb
Host smart-9631dba1-be3b-4fbe-838d-0a75a10a7497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234074500 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1234074500
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.1355051560
Short name T711
Test name
Test status
Simulation time 25348200 ps
CPU time 0.87 seconds
Started Feb 18 03:16:35 PM PST 24
Finished Feb 18 03:16:40 PM PST 24
Peak memory 214724 kb
Host smart-df6d8733-6b89-4547-acc1-ae83dc8b81e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355051560 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.1355051560
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.463564655
Short name T660
Test name
Test status
Simulation time 117587483 ps
CPU time 2.86 seconds
Started Feb 18 03:16:45 PM PST 24
Finished Feb 18 03:16:52 PM PST 24
Peak memory 217116 kb
Host smart-26a231ce-33d7-4797-b7e5-25772a5c7df0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463564655 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.463564655
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3160856714
Short name T200
Test name
Test status
Simulation time 30663191028 ps
CPU time 662.01 seconds
Started Feb 18 03:16:30 PM PST 24
Finished Feb 18 03:27:37 PM PST 24
Peak memory 223240 kb
Host smart-5f965846-ec4f-4678-846d-6ca9b31f6cb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160856714 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3160856714
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3368812115
Short name T146
Test name
Test status
Simulation time 56900605 ps
CPU time 1.22 seconds
Started Feb 18 03:14:22 PM PST 24
Finished Feb 18 03:14:33 PM PST 24
Peak memory 215040 kb
Host smart-920d8f12-2332-4cf4-975e-c1881802e850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368812115 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3368812115
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.2421920791
Short name T417
Test name
Test status
Simulation time 18274587 ps
CPU time 0.94 seconds
Started Feb 18 03:14:23 PM PST 24
Finished Feb 18 03:14:35 PM PST 24
Peak memory 206236 kb
Host smart-805faf20-ae68-4399-8988-c4ccdc5214ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421920791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.2421920791
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1806885330
Short name T172
Test name
Test status
Simulation time 14002407 ps
CPU time 0.89 seconds
Started Feb 18 03:14:24 PM PST 24
Finished Feb 18 03:14:35 PM PST 24
Peak memory 215292 kb
Host smart-48c2dd86-6589-4526-a875-9369f9160366
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806885330 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1806885330
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_err.3224396171
Short name T593
Test name
Test status
Simulation time 20409300 ps
CPU time 0.97 seconds
Started Feb 18 03:14:24 PM PST 24
Finished Feb 18 03:14:36 PM PST 24
Peak memory 217568 kb
Host smart-d0afdb21-1e49-49c6-86c1-214864bbd000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224396171 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3224396171
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.963067135
Short name T402
Test name
Test status
Simulation time 39050570 ps
CPU time 1.25 seconds
Started Feb 18 03:14:22 PM PST 24
Finished Feb 18 03:14:33 PM PST 24
Peak memory 214664 kb
Host smart-096a2223-4051-4431-b59f-d23d2a7a8fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963067135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.963067135
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.940569038
Short name T452
Test name
Test status
Simulation time 20786880 ps
CPU time 1.06 seconds
Started Feb 18 03:14:32 PM PST 24
Finished Feb 18 03:14:45 PM PST 24
Peak memory 215192 kb
Host smart-349e729f-20a8-407d-aaa2-dcae4f943317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940569038 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.940569038
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_smoke.3604560761
Short name T674
Test name
Test status
Simulation time 17898740 ps
CPU time 1.03 seconds
Started Feb 18 03:14:21 PM PST 24
Finished Feb 18 03:14:32 PM PST 24
Peak memory 214720 kb
Host smart-599b3505-5891-486f-aac0-7ecab1870684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604560761 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3604560761
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.556013171
Short name T142
Test name
Test status
Simulation time 309715678 ps
CPU time 5.95 seconds
Started Feb 18 03:14:22 PM PST 24
Finished Feb 18 03:14:38 PM PST 24
Peak memory 214728 kb
Host smart-5000f8d0-c601-4bb1-acb0-43d967b96755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556013171 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.556013171
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.224910408
Short name T194
Test name
Test status
Simulation time 31048943752 ps
CPU time 365.73 seconds
Started Feb 18 03:14:22 PM PST 24
Finished Feb 18 03:20:38 PM PST 24
Peak memory 219792 kb
Host smart-84d2536e-f432-4701-b6de-3e6d66b6e1f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224910408 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.224910408
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.897369981
Short name T527
Test name
Test status
Simulation time 22242995 ps
CPU time 0.93 seconds
Started Feb 18 03:16:35 PM PST 24
Finished Feb 18 03:16:40 PM PST 24
Peak memory 217528 kb
Host smart-e104d2e6-de35-4549-abb6-9ef07398b305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897369981 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.897369981
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.4088780626
Short name T561
Test name
Test status
Simulation time 127205126 ps
CPU time 1.06 seconds
Started Feb 18 03:16:35 PM PST 24
Finished Feb 18 03:16:41 PM PST 24
Peak memory 216140 kb
Host smart-8a3cbedd-818d-4d6e-a7d2-e6d23b726f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088780626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.4088780626
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.1838130456
Short name T765
Test name
Test status
Simulation time 35109677 ps
CPU time 1.31 seconds
Started Feb 18 03:16:45 PM PST 24
Finished Feb 18 03:16:50 PM PST 24
Peak memory 219460 kb
Host smart-e720eab5-8189-41a9-9b62-6e9caadf6596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838130456 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.1838130456
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1653309434
Short name T826
Test name
Test status
Simulation time 121576130 ps
CPU time 1.27 seconds
Started Feb 18 03:16:45 PM PST 24
Finished Feb 18 03:16:50 PM PST 24
Peak memory 217616 kb
Host smart-4c213a42-e4f1-4642-8ae3-eccfb9069322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653309434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1653309434
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.3710878868
Short name T810
Test name
Test status
Simulation time 51238295 ps
CPU time 0.92 seconds
Started Feb 18 03:16:40 PM PST 24
Finished Feb 18 03:16:46 PM PST 24
Peak memory 222232 kb
Host smart-c38d0a1d-6c05-4320-b821-4ffa4d60f387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710878868 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3710878868
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3241938325
Short name T688
Test name
Test status
Simulation time 68209715 ps
CPU time 1.18 seconds
Started Feb 18 03:16:35 PM PST 24
Finished Feb 18 03:16:41 PM PST 24
Peak memory 216076 kb
Host smart-9b7310df-9872-4e0f-80d3-3c95f5c02d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241938325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3241938325
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.1171273220
Short name T71
Test name
Test status
Simulation time 20598452 ps
CPU time 1.2 seconds
Started Feb 18 03:16:40 PM PST 24
Finished Feb 18 03:16:46 PM PST 24
Peak memory 218600 kb
Host smart-608814af-6f44-417b-9cce-cbb9db1fb3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171273220 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1171273220
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2751219799
Short name T367
Test name
Test status
Simulation time 36102729 ps
CPU time 1.48 seconds
Started Feb 18 03:16:43 PM PST 24
Finished Feb 18 03:16:48 PM PST 24
Peak memory 218916 kb
Host smart-89e72a33-9c3e-445c-adf1-f45955e12ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751219799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2751219799
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.3284517922
Short name T7
Test name
Test status
Simulation time 32537677 ps
CPU time 0.87 seconds
Started Feb 18 03:16:41 PM PST 24
Finished Feb 18 03:16:46 PM PST 24
Peak memory 216028 kb
Host smart-e7f23906-c13d-4b70-80ef-01d8e85bf14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284517922 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.3284517922
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1904263315
Short name T265
Test name
Test status
Simulation time 61472201 ps
CPU time 2.3 seconds
Started Feb 18 03:16:42 PM PST 24
Finished Feb 18 03:16:48 PM PST 24
Peak memory 217152 kb
Host smart-31278931-9264-40c2-ba5f-e66fbbfc8b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904263315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1904263315
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.1611703822
Short name T112
Test name
Test status
Simulation time 32123071 ps
CPU time 1.1 seconds
Started Feb 18 03:16:39 PM PST 24
Finished Feb 18 03:16:46 PM PST 24
Peak memory 230652 kb
Host smart-6ea5bf54-ea77-42e0-8e59-006ae7d7df6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611703822 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.1611703822
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.755638615
Short name T563
Test name
Test status
Simulation time 68903556 ps
CPU time 1.03 seconds
Started Feb 18 03:16:41 PM PST 24
Finished Feb 18 03:16:47 PM PST 24
Peak memory 215960 kb
Host smart-d5f7bd11-f5df-4512-add7-efa876c77b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755638615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.755638615
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.2847170950
Short name T94
Test name
Test status
Simulation time 31285497 ps
CPU time 0.89 seconds
Started Feb 18 03:16:42 PM PST 24
Finished Feb 18 03:16:46 PM PST 24
Peak memory 217204 kb
Host smart-86fb3240-73f5-49f9-8f62-960029fefb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847170950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.2847170950
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.4224673967
Short name T444
Test name
Test status
Simulation time 51383239 ps
CPU time 1.84 seconds
Started Feb 18 03:16:45 PM PST 24
Finished Feb 18 03:16:51 PM PST 24
Peak memory 217228 kb
Host smart-89dbb029-6455-4b67-b4f9-1155b454c9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224673967 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.4224673967
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.520368077
Short name T45
Test name
Test status
Simulation time 33839367 ps
CPU time 0.93 seconds
Started Feb 18 03:16:44 PM PST 24
Finished Feb 18 03:16:48 PM PST 24
Peak memory 222380 kb
Host smart-497410a7-bd54-480d-9e92-782af74a3825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520368077 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.520368077
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.218500249
Short name T377
Test name
Test status
Simulation time 64667075 ps
CPU time 1.09 seconds
Started Feb 18 03:16:43 PM PST 24
Finished Feb 18 03:16:47 PM PST 24
Peak memory 216092 kb
Host smart-3eec054c-02ee-4e88-9b4b-a018648b49f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218500249 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.218500249
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.2121966244
Short name T677
Test name
Test status
Simulation time 31354301 ps
CPU time 0.94 seconds
Started Feb 18 03:16:50 PM PST 24
Finished Feb 18 03:16:55 PM PST 24
Peak memory 217272 kb
Host smart-42b725f2-5b17-409a-aefa-372f8fba2a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121966244 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2121966244
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.3128595555
Short name T413
Test name
Test status
Simulation time 286484776 ps
CPU time 1.59 seconds
Started Feb 18 03:16:45 PM PST 24
Finished Feb 18 03:16:50 PM PST 24
Peak memory 218852 kb
Host smart-1b4b3890-3f42-4e78-ba0e-02b3a4a53324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128595555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.3128595555
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.3575485837
Short name T37
Test name
Test status
Simulation time 26094627 ps
CPU time 1.36 seconds
Started Feb 18 03:16:45 PM PST 24
Finished Feb 18 03:16:51 PM PST 24
Peak memory 228104 kb
Host smart-1ae4d718-28d3-4c3b-9441-6fc43c5500db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575485837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3575485837
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.3846664409
Short name T492
Test name
Test status
Simulation time 42182035 ps
CPU time 1.4 seconds
Started Feb 18 03:16:45 PM PST 24
Finished Feb 18 03:16:50 PM PST 24
Peak memory 217080 kb
Host smart-d4469917-342b-4119-a80a-b5820392e44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846664409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.3846664409
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2012282363
Short name T61
Test name
Test status
Simulation time 261882070 ps
CPU time 1.52 seconds
Started Feb 18 03:14:30 PM PST 24
Finished Feb 18 03:14:44 PM PST 24
Peak memory 215028 kb
Host smart-c7600529-37ea-4f2d-8484-f11ff934fae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012282363 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2012282363
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.903537866
Short name T595
Test name
Test status
Simulation time 24019611 ps
CPU time 0.83 seconds
Started Feb 18 03:14:34 PM PST 24
Finished Feb 18 03:14:46 PM PST 24
Peak memory 204964 kb
Host smart-767f9066-2ed2-4a70-9eea-4dce9ee52854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903537866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.903537866
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.234798978
Short name T185
Test name
Test status
Simulation time 23749766 ps
CPU time 0.84 seconds
Started Feb 18 03:14:26 PM PST 24
Finished Feb 18 03:14:38 PM PST 24
Peak memory 214844 kb
Host smart-d8721cb3-bbde-4bdb-bbfc-372e2b27fa30
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234798978 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.234798978
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3757211897
Short name T628
Test name
Test status
Simulation time 30133619 ps
CPU time 1.14 seconds
Started Feb 18 03:14:32 PM PST 24
Finished Feb 18 03:14:45 PM PST 24
Peak memory 216884 kb
Host smart-cdaa3a53-228a-4c73-bfb6-470072e4aea3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757211897 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3757211897
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.982100517
Short name T88
Test name
Test status
Simulation time 33808113 ps
CPU time 0.85 seconds
Started Feb 18 03:14:26 PM PST 24
Finished Feb 18 03:14:39 PM PST 24
Peak memory 217252 kb
Host smart-871a2ddd-5c52-454c-bfb2-c3578abf5246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982100517 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.982100517
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1474998459
Short name T422
Test name
Test status
Simulation time 62850169 ps
CPU time 1.41 seconds
Started Feb 18 03:14:30 PM PST 24
Finished Feb 18 03:14:44 PM PST 24
Peak memory 217384 kb
Host smart-c7599b56-0c27-498a-8672-05269e070bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474998459 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1474998459
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3736700878
Short name T125
Test name
Test status
Simulation time 27884602 ps
CPU time 0.94 seconds
Started Feb 18 03:14:26 PM PST 24
Finished Feb 18 03:14:39 PM PST 24
Peak memory 215212 kb
Host smart-713f4fff-5d00-4b3e-8d15-3cecb8f0ed0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736700878 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3736700878
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.1280483516
Short name T122
Test name
Test status
Simulation time 26053561 ps
CPU time 0.93 seconds
Started Feb 18 03:14:25 PM PST 24
Finished Feb 18 03:14:37 PM PST 24
Peak memory 206432 kb
Host smart-35723c01-ca82-4c78-9564-06c5a16e5844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280483516 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.1280483516
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.1421566797
Short name T400
Test name
Test status
Simulation time 24628736 ps
CPU time 0.95 seconds
Started Feb 18 03:14:26 PM PST 24
Finished Feb 18 03:14:39 PM PST 24
Peak memory 214748 kb
Host smart-83d25bcf-2692-4d31-88ac-59c7e3b9aea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421566797 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.1421566797
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.984798158
Short name T669
Test name
Test status
Simulation time 53884094 ps
CPU time 1.23 seconds
Started Feb 18 03:14:28 PM PST 24
Finished Feb 18 03:14:41 PM PST 24
Peak memory 215792 kb
Host smart-ae77b8b7-1094-4051-8e15-16158abebe55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984798158 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.984798158
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3150396348
Short name T543
Test name
Test status
Simulation time 44555857326 ps
CPU time 1166.48 seconds
Started Feb 18 03:14:32 PM PST 24
Finished Feb 18 03:34:10 PM PST 24
Peak memory 223176 kb
Host smart-bb7bffe3-8d65-4329-9c5a-3151889b4f7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150396348 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3150396348
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.2870059384
Short name T673
Test name
Test status
Simulation time 50925793 ps
CPU time 0.97 seconds
Started Feb 18 03:16:47 PM PST 24
Finished Feb 18 03:16:52 PM PST 24
Peak memory 217536 kb
Host smart-5f2cda0e-3136-44fc-9191-dd0889c88835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870059384 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.2870059384
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2432169261
Short name T337
Test name
Test status
Simulation time 47335997 ps
CPU time 1.23 seconds
Started Feb 18 03:16:52 PM PST 24
Finished Feb 18 03:16:57 PM PST 24
Peak memory 217316 kb
Host smart-e8d78781-b0b4-4ef4-a261-ef2646b09863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432169261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2432169261
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.1391886753
Short name T206
Test name
Test status
Simulation time 24878013 ps
CPU time 1.21 seconds
Started Feb 18 03:16:48 PM PST 24
Finished Feb 18 03:16:53 PM PST 24
Peak memory 217404 kb
Host smart-e894489e-de75-458f-9195-798042c9850d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391886753 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1391886753
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.180056894
Short name T309
Test name
Test status
Simulation time 99353806 ps
CPU time 3.07 seconds
Started Feb 18 03:16:52 PM PST 24
Finished Feb 18 03:16:58 PM PST 24
Peak memory 217444 kb
Host smart-90b925c4-8181-49cd-807e-69b53bbc8cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180056894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.180056894
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.404188174
Short name T618
Test name
Test status
Simulation time 18756970 ps
CPU time 1.17 seconds
Started Feb 18 03:16:49 PM PST 24
Finished Feb 18 03:16:54 PM PST 24
Peak memory 222440 kb
Host smart-5de35d75-35fc-4336-be36-7f01c72cf4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404188174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.404188174
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1152785144
Short name T399
Test name
Test status
Simulation time 46490835 ps
CPU time 1.75 seconds
Started Feb 18 03:16:45 PM PST 24
Finished Feb 18 03:16:51 PM PST 24
Peak memory 217276 kb
Host smart-ad69067b-f212-442a-b7bc-928bda68a34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152785144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1152785144
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.1051829377
Short name T99
Test name
Test status
Simulation time 18863730 ps
CPU time 1.16 seconds
Started Feb 18 03:16:48 PM PST 24
Finished Feb 18 03:16:52 PM PST 24
Peak memory 222420 kb
Host smart-ef663c9a-9056-420a-9536-9a57eb0e18b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051829377 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1051829377
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.2809674521
Short name T31
Test name
Test status
Simulation time 39975724 ps
CPU time 1.41 seconds
Started Feb 18 03:16:45 PM PST 24
Finished Feb 18 03:16:50 PM PST 24
Peak memory 217272 kb
Host smart-258256de-1303-45dc-a576-ddc29d0931ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809674521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.2809674521
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.2127947259
Short name T3
Test name
Test status
Simulation time 28108629 ps
CPU time 1.37 seconds
Started Feb 18 03:16:48 PM PST 24
Finished Feb 18 03:16:53 PM PST 24
Peak memory 223548 kb
Host smart-5509c903-53cc-4e4d-bc35-ee1200dea4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127947259 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2127947259
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.39977752
Short name T675
Test name
Test status
Simulation time 77977526 ps
CPU time 1.12 seconds
Started Feb 18 03:16:52 PM PST 24
Finished Feb 18 03:16:57 PM PST 24
Peak memory 216044 kb
Host smart-64ed6915-7c87-4bdd-9003-4f27684e84c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39977752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.39977752
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.1508374164
Short name T779
Test name
Test status
Simulation time 20323213 ps
CPU time 1.06 seconds
Started Feb 18 03:16:46 PM PST 24
Finished Feb 18 03:16:51 PM PST 24
Peak memory 217588 kb
Host smart-eb83ddcc-97c8-4ceb-a49d-075bf16ccb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508374164 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.1508374164
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1419002553
Short name T266
Test name
Test status
Simulation time 51437346 ps
CPU time 1.26 seconds
Started Feb 18 03:16:48 PM PST 24
Finished Feb 18 03:16:53 PM PST 24
Peak memory 215868 kb
Host smart-111c1d2d-2c7d-4dcd-8dd9-d23d6d1563de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419002553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1419002553
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.3070695276
Short name T40
Test name
Test status
Simulation time 161470238 ps
CPU time 1.23 seconds
Started Feb 18 03:16:45 PM PST 24
Finished Feb 18 03:16:50 PM PST 24
Peak memory 229112 kb
Host smart-386826bd-30cc-48e3-95f4-aab16f7c20c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070695276 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3070695276
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3813607726
Short name T506
Test name
Test status
Simulation time 34943160 ps
CPU time 1.46 seconds
Started Feb 18 03:16:43 PM PST 24
Finished Feb 18 03:16:48 PM PST 24
Peak memory 217072 kb
Host smart-f2776fe5-4831-4380-959a-46f01d710dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813607726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3813607726
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.2446359424
Short name T167
Test name
Test status
Simulation time 24770647 ps
CPU time 1.22 seconds
Started Feb 18 03:16:46 PM PST 24
Finished Feb 18 03:16:51 PM PST 24
Peak memory 216320 kb
Host smart-2e9c62c6-d337-4699-8608-0c5f42aa198d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446359424 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.2446359424
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1356958989
Short name T29
Test name
Test status
Simulation time 270666408 ps
CPU time 3.76 seconds
Started Feb 18 03:16:44 PM PST 24
Finished Feb 18 03:16:51 PM PST 24
Peak memory 219004 kb
Host smart-9c9a1077-64c8-4d6d-95ad-b451e943a383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356958989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1356958989
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1805472910
Short name T706
Test name
Test status
Simulation time 27777500 ps
CPU time 0.93 seconds
Started Feb 18 03:16:49 PM PST 24
Finished Feb 18 03:16:53 PM PST 24
Peak memory 222224 kb
Host smart-e3bafedd-5afc-45f7-9a4b-48f771df32a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805472910 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1805472910
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.592422023
Short name T191
Test name
Test status
Simulation time 36614950 ps
CPU time 1.58 seconds
Started Feb 18 03:16:49 PM PST 24
Finished Feb 18 03:16:54 PM PST 24
Peak memory 217464 kb
Host smart-34ef346f-6b12-4249-9e73-289399b38afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592422023 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.592422023
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.1797473484
Short name T478
Test name
Test status
Simulation time 25738063 ps
CPU time 1.29 seconds
Started Feb 18 03:16:51 PM PST 24
Finished Feb 18 03:16:56 PM PST 24
Peak memory 230668 kb
Host smart-f9548c05-53ff-4767-8806-673d90f888a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797473484 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1797473484
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2244705842
Short name T456
Test name
Test status
Simulation time 27249005 ps
CPU time 1.34 seconds
Started Feb 18 03:16:52 PM PST 24
Finished Feb 18 03:16:57 PM PST 24
Peak memory 218292 kb
Host smart-90381665-5274-4967-bef9-85b46345409f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244705842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2244705842
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert_test.4081934221
Short name T553
Test name
Test status
Simulation time 12313781 ps
CPU time 0.87 seconds
Started Feb 18 03:14:33 PM PST 24
Finished Feb 18 03:14:45 PM PST 24
Peak memory 205292 kb
Host smart-2e7c320d-ab9a-4aea-a4c1-e8a56cd191a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081934221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.4081934221
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.239126439
Short name T107
Test name
Test status
Simulation time 133154575 ps
CPU time 0.88 seconds
Started Feb 18 03:14:31 PM PST 24
Finished Feb 18 03:14:44 PM PST 24
Peak memory 215132 kb
Host smart-6653ae8a-f772-46fc-bd5c-c950bafcfe89
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239126439 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.239126439
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_err.3315819792
Short name T832
Test name
Test status
Simulation time 48503991 ps
CPU time 1.08 seconds
Started Feb 18 03:14:31 PM PST 24
Finished Feb 18 03:14:44 PM PST 24
Peak memory 230648 kb
Host smart-17be270a-3df6-4d39-978a-9132e2fda190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315819792 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3315819792
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3588112608
Short name T497
Test name
Test status
Simulation time 41090968 ps
CPU time 1.58 seconds
Started Feb 18 03:14:33 PM PST 24
Finished Feb 18 03:14:46 PM PST 24
Peak memory 217300 kb
Host smart-d3077769-4fc2-4a86-9e18-50bbefb410b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588112608 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3588112608
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_regwen.219664327
Short name T298
Test name
Test status
Simulation time 19230231 ps
CPU time 1.07 seconds
Started Feb 18 03:14:32 PM PST 24
Finished Feb 18 03:14:45 PM PST 24
Peak memory 206520 kb
Host smart-5ec75f0a-74bb-4ea3-987f-94ba5ec4aa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219664327 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.219664327
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2530666750
Short name T613
Test name
Test status
Simulation time 16629535 ps
CPU time 0.95 seconds
Started Feb 18 03:14:28 PM PST 24
Finished Feb 18 03:14:42 PM PST 24
Peak memory 214716 kb
Host smart-a01f4e2b-edc3-40c8-a8f1-38aaaa1e26f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530666750 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2530666750
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.4110728322
Short name T267
Test name
Test status
Simulation time 312325054 ps
CPU time 2.5 seconds
Started Feb 18 03:14:32 PM PST 24
Finished Feb 18 03:14:46 PM PST 24
Peak memory 215732 kb
Host smart-899b81d5-d4d5-48cf-9cfd-b6207d998d3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110728322 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.4110728322
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.572750447
Short name T483
Test name
Test status
Simulation time 69768664050 ps
CPU time 840.44 seconds
Started Feb 18 03:14:32 PM PST 24
Finished Feb 18 03:28:45 PM PST 24
Peak memory 218476 kb
Host smart-27ce883e-27e5-4113-b994-3d403e26c996
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572750447 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.572750447
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.1936584596
Short name T76
Test name
Test status
Simulation time 27796818 ps
CPU time 1.24 seconds
Started Feb 18 03:16:51 PM PST 24
Finished Feb 18 03:16:56 PM PST 24
Peak memory 219508 kb
Host smart-6abe979a-e5b7-4b25-ab22-93d05784e14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936584596 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1936584596
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.511169597
Short name T715
Test name
Test status
Simulation time 135028399 ps
CPU time 1.82 seconds
Started Feb 18 03:16:56 PM PST 24
Finished Feb 18 03:17:01 PM PST 24
Peak memory 216232 kb
Host smart-179585b9-fb43-451b-9008-c0c96f991e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511169597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.511169597
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.3247522078
Short name T70
Test name
Test status
Simulation time 23472517 ps
CPU time 1.16 seconds
Started Feb 18 03:16:47 PM PST 24
Finished Feb 18 03:16:52 PM PST 24
Peak memory 229056 kb
Host smart-2030bfb4-17fa-45df-a45c-ef77d330d9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247522078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3247522078
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.3443697879
Short name T277
Test name
Test status
Simulation time 77553793 ps
CPU time 1.49 seconds
Started Feb 18 03:16:54 PM PST 24
Finished Feb 18 03:16:59 PM PST 24
Peak memory 217432 kb
Host smart-f9e7bd08-3e97-4efc-91c7-a56d634fc078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443697879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.3443697879
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.1424959693
Short name T735
Test name
Test status
Simulation time 54728253 ps
CPU time 1.11 seconds
Started Feb 18 03:16:52 PM PST 24
Finished Feb 18 03:16:57 PM PST 24
Peak memory 229180 kb
Host smart-8ed3ac2e-2b5a-49f5-b3b0-08b0120d241a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424959693 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1424959693
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3138523109
Short name T287
Test name
Test status
Simulation time 101340780 ps
CPU time 1.4 seconds
Started Feb 18 03:16:50 PM PST 24
Finished Feb 18 03:16:54 PM PST 24
Peak memory 217616 kb
Host smart-eba332ad-1271-4331-9f64-5a7b5ff7e8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138523109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3138523109
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.805635968
Short name T681
Test name
Test status
Simulation time 45836826 ps
CPU time 0.84 seconds
Started Feb 18 03:16:49 PM PST 24
Finished Feb 18 03:16:53 PM PST 24
Peak memory 217388 kb
Host smart-df7c4d2d-d2e8-47ff-9bbe-62604452498c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805635968 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.805635968
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.813813451
Short name T197
Test name
Test status
Simulation time 54754115 ps
CPU time 1.06 seconds
Started Feb 18 03:16:49 PM PST 24
Finished Feb 18 03:16:54 PM PST 24
Peak memory 217500 kb
Host smart-cededcdf-5f3e-43d9-a26a-dff2daacc710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813813451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.813813451
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.2472984993
Short name T608
Test name
Test status
Simulation time 34721441 ps
CPU time 1.48 seconds
Started Feb 18 03:17:04 PM PST 24
Finished Feb 18 03:17:09 PM PST 24
Peak memory 231664 kb
Host smart-c4215dde-d567-4e6c-b77f-1957647a0d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472984993 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2472984993
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.586970014
Short name T473
Test name
Test status
Simulation time 40481240 ps
CPU time 1.41 seconds
Started Feb 18 03:16:51 PM PST 24
Finished Feb 18 03:16:56 PM PST 24
Peak memory 215964 kb
Host smart-5bde9b42-5119-4195-8d65-fcd139324736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586970014 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.586970014
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.3917460720
Short name T83
Test name
Test status
Simulation time 25470172 ps
CPU time 1.15 seconds
Started Feb 18 03:16:59 PM PST 24
Finished Feb 18 03:17:03 PM PST 24
Peak memory 229152 kb
Host smart-73e96886-5a5c-4b40-bf61-d920d9940a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917460720 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3917460720
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.213293858
Short name T518
Test name
Test status
Simulation time 269587468 ps
CPU time 1.1 seconds
Started Feb 18 03:16:56 PM PST 24
Finished Feb 18 03:17:00 PM PST 24
Peak memory 216164 kb
Host smart-641c381c-a47b-4ec0-b953-fe14ff895115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213293858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.213293858
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3258671891
Short name T82
Test name
Test status
Simulation time 39293697 ps
CPU time 0.99 seconds
Started Feb 18 03:16:47 PM PST 24
Finished Feb 18 03:16:52 PM PST 24
Peak memory 216120 kb
Host smart-e44f65c9-23b0-4b03-9367-85a39028e8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258671891 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3258671891
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.2832821504
Short name T9
Test name
Test status
Simulation time 46517647 ps
CPU time 1.55 seconds
Started Feb 18 03:16:53 PM PST 24
Finished Feb 18 03:16:58 PM PST 24
Peak memory 218444 kb
Host smart-dd5f8d4f-6e18-42e8-9a0f-29eec47d59a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832821504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.2832821504
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_genbits.1018867383
Short name T446
Test name
Test status
Simulation time 40661684 ps
CPU time 1.57 seconds
Started Feb 18 03:16:57 PM PST 24
Finished Feb 18 03:17:01 PM PST 24
Peak memory 218152 kb
Host smart-aeed4101-f475-4fd7-998f-6f914f53ba21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018867383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.1018867383
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.3331418027
Short name T454
Test name
Test status
Simulation time 27293933 ps
CPU time 0.85 seconds
Started Feb 18 03:16:49 PM PST 24
Finished Feb 18 03:16:53 PM PST 24
Peak memory 217096 kb
Host smart-cb5ed3d3-ff79-4482-98a5-7dcb7a2a44dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331418027 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.3331418027
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1453742810
Short name T313
Test name
Test status
Simulation time 57664943 ps
CPU time 1.88 seconds
Started Feb 18 03:16:56 PM PST 24
Finished Feb 18 03:17:01 PM PST 24
Peak memory 217096 kb
Host smart-dbf8b591-002f-478c-8f91-d7598c12f52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453742810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1453742810
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.2506540498
Short name T95
Test name
Test status
Simulation time 30813179 ps
CPU time 0.96 seconds
Started Feb 18 03:16:52 PM PST 24
Finished Feb 18 03:16:57 PM PST 24
Peak memory 222320 kb
Host smart-1dae4a23-fe6c-4206-bfc3-c6c2d1276c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506540498 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.2506540498
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.1043059337
Short name T464
Test name
Test status
Simulation time 59116587 ps
CPU time 1.54 seconds
Started Feb 18 03:16:56 PM PST 24
Finished Feb 18 03:17:01 PM PST 24
Peak memory 217436 kb
Host smart-392f05bb-8369-452f-bb89-dcc61b55b9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043059337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.1043059337
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.1470065689
Short name T517
Test name
Test status
Simulation time 39674023 ps
CPU time 1.13 seconds
Started Feb 18 03:14:35 PM PST 24
Finished Feb 18 03:14:46 PM PST 24
Peak memory 215036 kb
Host smart-95a4a358-9184-4e11-ba5b-81e494b6b749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470065689 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1470065689
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3849276884
Short name T320
Test name
Test status
Simulation time 43987531 ps
CPU time 0.85 seconds
Started Feb 18 03:14:43 PM PST 24
Finished Feb 18 03:14:51 PM PST 24
Peak memory 206252 kb
Host smart-f7b15d2b-4f23-4d0a-aab4-4dbae4ce6024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849276884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3849276884
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.897454257
Short name T327
Test name
Test status
Simulation time 10919878 ps
CPU time 0.92 seconds
Started Feb 18 03:14:47 PM PST 24
Finished Feb 18 03:14:55 PM PST 24
Peak memory 214824 kb
Host smart-1f5dd175-e086-4192-a1d1-92f0a0956a5c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897454257 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.897454257
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.2374390007
Short name T326
Test name
Test status
Simulation time 29063148 ps
CPU time 1.1 seconds
Started Feb 18 03:14:45 PM PST 24
Finished Feb 18 03:14:53 PM PST 24
Peak memory 216968 kb
Host smart-d647c11b-f241-4d73-be81-936dc4531e61
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374390007 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.2374390007
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.144601523
Short name T90
Test name
Test status
Simulation time 23677084 ps
CPU time 0.94 seconds
Started Feb 18 03:14:46 PM PST 24
Finished Feb 18 03:14:54 PM PST 24
Peak memory 217552 kb
Host smart-8d724935-e7bb-43f2-a5a2-c6d0cafd215d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144601523 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.144601523
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3441514634
Short name T722
Test name
Test status
Simulation time 37892396 ps
CPU time 1.33 seconds
Started Feb 18 03:14:37 PM PST 24
Finished Feb 18 03:14:48 PM PST 24
Peak memory 217176 kb
Host smart-3a65821c-23ac-4b3f-9833-bc8acb1d094c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441514634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3441514634
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.734081393
Short name T127
Test name
Test status
Simulation time 35848608 ps
CPU time 0.88 seconds
Started Feb 18 03:14:37 PM PST 24
Finished Feb 18 03:14:47 PM PST 24
Peak memory 214988 kb
Host smart-959680cb-a108-470c-aaef-e077a2457aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734081393 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.734081393
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3912006570
Short name T223
Test name
Test status
Simulation time 39959477 ps
CPU time 0.93 seconds
Started Feb 18 03:14:38 PM PST 24
Finished Feb 18 03:14:48 PM PST 24
Peak memory 206532 kb
Host smart-7364eb6d-bf05-4092-838b-b46b3a9e043e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912006570 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3912006570
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.211537516
Short name T743
Test name
Test status
Simulation time 32842271 ps
CPU time 0.95 seconds
Started Feb 18 03:14:29 PM PST 24
Finished Feb 18 03:14:43 PM PST 24
Peak memory 214748 kb
Host smart-82016f07-bb69-4588-a1ba-7260da74105e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211537516 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.211537516
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3916461945
Short name T217
Test name
Test status
Simulation time 718270456 ps
CPU time 3.99 seconds
Started Feb 18 03:14:35 PM PST 24
Finished Feb 18 03:14:50 PM PST 24
Peak memory 214724 kb
Host smart-b8a47b3e-41a4-4135-972b-fb06a6a9f92a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916461945 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3916461945
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2768328923
Short name T568
Test name
Test status
Simulation time 94746165834 ps
CPU time 2440.93 seconds
Started Feb 18 03:14:35 PM PST 24
Finished Feb 18 03:55:26 PM PST 24
Peak memory 231012 kb
Host smart-956f081b-08af-4280-b9a2-4dff1ee1a94a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768328923 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2768328923
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.5112432
Short name T346
Test name
Test status
Simulation time 18820453 ps
CPU time 1.08 seconds
Started Feb 18 03:16:49 PM PST 24
Finished Feb 18 03:16:54 PM PST 24
Peak memory 217072 kb
Host smart-433daf70-3d0f-40c2-845e-576cc00db3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5112432 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.5112432
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.1049536051
Short name T587
Test name
Test status
Simulation time 62307875 ps
CPU time 1.44 seconds
Started Feb 18 03:16:52 PM PST 24
Finished Feb 18 03:16:56 PM PST 24
Peak memory 217272 kb
Host smart-39f877fc-d348-4459-acff-2d8cb4ff654f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049536051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.1049536051
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.3431458751
Short name T643
Test name
Test status
Simulation time 259935511 ps
CPU time 1.16 seconds
Started Feb 18 03:16:55 PM PST 24
Finished Feb 18 03:16:59 PM PST 24
Peak memory 218504 kb
Host smart-e714a419-09c2-4d17-8184-b7fd2cf278cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431458751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3431458751
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/82.edn_err.1709458117
Short name T567
Test name
Test status
Simulation time 33976631 ps
CPU time 0.85 seconds
Started Feb 18 03:16:53 PM PST 24
Finished Feb 18 03:16:58 PM PST 24
Peak memory 217112 kb
Host smart-bebf19e5-cfed-44b3-a36e-f5055d11420b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709458117 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1709458117
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.751919651
Short name T210
Test name
Test status
Simulation time 85332127 ps
CPU time 1.33 seconds
Started Feb 18 03:17:04 PM PST 24
Finished Feb 18 03:17:09 PM PST 24
Peak memory 217700 kb
Host smart-d8526531-bbc0-4f77-9915-a28b126bc6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751919651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.751919651
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.2767909369
Short name T63
Test name
Test status
Simulation time 20836103 ps
CPU time 1.17 seconds
Started Feb 18 03:16:56 PM PST 24
Finished Feb 18 03:17:00 PM PST 24
Peak memory 229128 kb
Host smart-3b49bf37-8db6-494b-91c3-4b9bd234386f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767909369 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2767909369
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.1282828355
Short name T138
Test name
Test status
Simulation time 44608166 ps
CPU time 1.66 seconds
Started Feb 18 03:16:53 PM PST 24
Finished Feb 18 03:16:58 PM PST 24
Peak memory 214732 kb
Host smart-bdd38b55-475d-411d-976b-d8955742b8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282828355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.1282828355
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.3991345971
Short name T775
Test name
Test status
Simulation time 28040466 ps
CPU time 0.84 seconds
Started Feb 18 03:17:04 PM PST 24
Finished Feb 18 03:17:08 PM PST 24
Peak memory 216864 kb
Host smart-c51839e6-e614-4172-8e94-031793678af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991345971 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3991345971
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2006465095
Short name T525
Test name
Test status
Simulation time 46447437 ps
CPU time 1.52 seconds
Started Feb 18 03:16:56 PM PST 24
Finished Feb 18 03:17:01 PM PST 24
Peak memory 217180 kb
Host smart-2a9da341-b8de-4cf1-8d35-9d7f5bbeb920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006465095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2006465095
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.3265498199
Short name T504
Test name
Test status
Simulation time 24778315 ps
CPU time 1.19 seconds
Started Feb 18 03:17:04 PM PST 24
Finished Feb 18 03:17:09 PM PST 24
Peak memory 216120 kb
Host smart-1d0111fb-c25d-4a43-9925-2be278358c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265498199 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3265498199
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.915057015
Short name T366
Test name
Test status
Simulation time 37412580 ps
CPU time 1.01 seconds
Started Feb 18 03:16:53 PM PST 24
Finished Feb 18 03:16:58 PM PST 24
Peak memory 216276 kb
Host smart-1fe02e4d-922c-455a-9bfe-a66e07d6bd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915057015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.915057015
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.3385656432
Short name T637
Test name
Test status
Simulation time 29242630 ps
CPU time 0.86 seconds
Started Feb 18 03:16:55 PM PST 24
Finished Feb 18 03:17:00 PM PST 24
Peak memory 217260 kb
Host smart-4346bc30-0356-46b3-8bea-1e3512315679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385656432 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3385656432
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.2977745806
Short name T811
Test name
Test status
Simulation time 85558353 ps
CPU time 1.11 seconds
Started Feb 18 03:17:01 PM PST 24
Finished Feb 18 03:17:05 PM PST 24
Peak memory 215880 kb
Host smart-0f207113-8876-4da9-ada8-eb280ae025f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977745806 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.2977745806
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.2695122224
Short name T171
Test name
Test status
Simulation time 45507693 ps
CPU time 1.16 seconds
Started Feb 18 03:17:08 PM PST 24
Finished Feb 18 03:17:13 PM PST 24
Peak memory 218764 kb
Host smart-d0dfd48c-4fbd-4392-9c6e-e9c3fdb63f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695122224 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.2695122224
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.220725687
Short name T729
Test name
Test status
Simulation time 102690729 ps
CPU time 1.47 seconds
Started Feb 18 03:16:55 PM PST 24
Finished Feb 18 03:17:00 PM PST 24
Peak memory 217248 kb
Host smart-63dc30ff-2ad7-40aa-bbeb-4120abcad4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220725687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.220725687
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.3092205192
Short name T682
Test name
Test status
Simulation time 23800884 ps
CPU time 0.98 seconds
Started Feb 18 03:17:03 PM PST 24
Finished Feb 18 03:17:08 PM PST 24
Peak memory 217176 kb
Host smart-1e928b52-fc85-42ba-bc1a-a114d16182fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092205192 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3092205192
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.2218018613
Short name T50
Test name
Test status
Simulation time 53847736 ps
CPU time 1.62 seconds
Started Feb 18 03:17:06 PM PST 24
Finished Feb 18 03:17:11 PM PST 24
Peak memory 217232 kb
Host smart-4b1ff4c3-35ab-45cf-bedf-c765018194de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218018613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.2218018613
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.4240384267
Short name T41
Test name
Test status
Simulation time 74876005 ps
CPU time 1.25 seconds
Started Feb 18 03:17:03 PM PST 24
Finished Feb 18 03:17:08 PM PST 24
Peak memory 223460 kb
Host smart-17f791e5-9671-4d3b-828d-27e2cd46105d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240384267 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.4240384267
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1581471955
Short name T802
Test name
Test status
Simulation time 50943516 ps
CPU time 1.93 seconds
Started Feb 18 03:16:59 PM PST 24
Finished Feb 18 03:17:05 PM PST 24
Peak memory 218508 kb
Host smart-783825d7-d79d-4e1b-94fe-7274b10158e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581471955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1581471955
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1617002723
Short name T305
Test name
Test status
Simulation time 28539941 ps
CPU time 1.29 seconds
Started Feb 18 03:14:47 PM PST 24
Finished Feb 18 03:14:55 PM PST 24
Peak memory 215052 kb
Host smart-c1f3f569-adbb-4c58-b7ae-c45d287d9ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617002723 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1617002723
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.1786473122
Short name T612
Test name
Test status
Simulation time 12972578 ps
CPU time 0.89 seconds
Started Feb 18 03:14:50 PM PST 24
Finished Feb 18 03:14:58 PM PST 24
Peak memory 206180 kb
Host smart-daaaee0d-ef13-44cb-b3e7-9ef7af4794c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786473122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.1786473122
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1542277905
Short name T433
Test name
Test status
Simulation time 41440646 ps
CPU time 0.86 seconds
Started Feb 18 03:14:43 PM PST 24
Finished Feb 18 03:14:51 PM PST 24
Peak memory 214828 kb
Host smart-8fe45a4c-fc33-4ff3-89fa-983970c6f1fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542277905 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1542277905
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1019080646
Short name T79
Test name
Test status
Simulation time 108799282 ps
CPU time 1.04 seconds
Started Feb 18 03:14:42 PM PST 24
Finished Feb 18 03:14:51 PM PST 24
Peak memory 218292 kb
Host smart-6f9b9143-d212-493f-8eb4-2d2075eaf848
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019080646 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1019080646
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1168552726
Short name T92
Test name
Test status
Simulation time 18847345 ps
CPU time 1.16 seconds
Started Feb 18 03:14:42 PM PST 24
Finished Feb 18 03:14:51 PM PST 24
Peak memory 230564 kb
Host smart-ff2d0335-fc76-4b87-9839-b6c21e29491e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168552726 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1168552726
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2139488272
Short name T751
Test name
Test status
Simulation time 35081987 ps
CPU time 1.42 seconds
Started Feb 18 03:14:45 PM PST 24
Finished Feb 18 03:14:54 PM PST 24
Peak memory 217320 kb
Host smart-94716f8d-71ed-453e-9189-75b8041d3b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139488272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2139488272
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2205976571
Short name T534
Test name
Test status
Simulation time 44107703 ps
CPU time 0.85 seconds
Started Feb 18 03:14:44 PM PST 24
Finished Feb 18 03:14:52 PM PST 24
Peak memory 214984 kb
Host smart-18d3a646-1bc7-491a-99d7-6d16e4f5a1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205976571 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2205976571
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_smoke.3667873091
Short name T412
Test name
Test status
Simulation time 26910539 ps
CPU time 0.92 seconds
Started Feb 18 03:14:42 PM PST 24
Finished Feb 18 03:14:51 PM PST 24
Peak memory 214720 kb
Host smart-0160d353-a21e-4c33-a1c5-b37565c066bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667873091 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.3667873091
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3578121767
Short name T773
Test name
Test status
Simulation time 183986887 ps
CPU time 2.41 seconds
Started Feb 18 03:14:44 PM PST 24
Finished Feb 18 03:14:53 PM PST 24
Peak memory 214740 kb
Host smart-fe8a6dab-844c-4df1-a5c2-d72a7c82267d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578121767 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3578121767
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.4095734078
Short name T546
Test name
Test status
Simulation time 384455905694 ps
CPU time 836.22 seconds
Started Feb 18 03:14:45 PM PST 24
Finished Feb 18 03:28:48 PM PST 24
Peak memory 220080 kb
Host smart-4e660e7e-d8f8-4ac6-b703-d99ddaa443fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095734078 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.4095734078
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.2290548137
Short name T723
Test name
Test status
Simulation time 24444770 ps
CPU time 0.93 seconds
Started Feb 18 03:16:59 PM PST 24
Finished Feb 18 03:17:04 PM PST 24
Peak memory 217208 kb
Host smart-b56c3c5d-09b1-4604-8773-c730c043a590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290548137 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2290548137
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/91.edn_err.3274246190
Short name T166
Test name
Test status
Simulation time 18370926 ps
CPU time 0.99 seconds
Started Feb 18 03:16:56 PM PST 24
Finished Feb 18 03:17:00 PM PST 24
Peak memory 217412 kb
Host smart-9aaa09ec-c32f-4e96-925f-c5244d28b7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274246190 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3274246190
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1536828259
Short name T742
Test name
Test status
Simulation time 234911957 ps
CPU time 3.25 seconds
Started Feb 18 03:17:06 PM PST 24
Finished Feb 18 03:17:13 PM PST 24
Peak memory 217252 kb
Host smart-bb1f8b83-8a9e-4ef1-89d5-a16e012e52eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536828259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1536828259
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.3569671573
Short name T54
Test name
Test status
Simulation time 18634040 ps
CPU time 1.06 seconds
Started Feb 18 03:17:00 PM PST 24
Finished Feb 18 03:17:05 PM PST 24
Peak memory 217284 kb
Host smart-993f9635-857f-4e6e-8be1-f48d3e1e0e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569671573 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3569671573
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.2646404155
Short name T572
Test name
Test status
Simulation time 62859162 ps
CPU time 1.21 seconds
Started Feb 18 03:17:06 PM PST 24
Finished Feb 18 03:17:11 PM PST 24
Peak memory 217016 kb
Host smart-663f05ff-f29a-4158-a4a3-996440cf0c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646404155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.2646404155
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.987389194
Short name T520
Test name
Test status
Simulation time 20630676 ps
CPU time 1.19 seconds
Started Feb 18 03:17:07 PM PST 24
Finished Feb 18 03:17:12 PM PST 24
Peak memory 222540 kb
Host smart-e4aa8be8-f40f-43f2-8f77-e01d733335fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987389194 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.987389194
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.3336271561
Short name T559
Test name
Test status
Simulation time 84284491 ps
CPU time 1.43 seconds
Started Feb 18 03:17:05 PM PST 24
Finished Feb 18 03:17:10 PM PST 24
Peak memory 217436 kb
Host smart-5dbd889b-24c4-4325-8dae-6454e873f55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336271561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.3336271561
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.3879995377
Short name T118
Test name
Test status
Simulation time 33138842 ps
CPU time 1.07 seconds
Started Feb 18 03:16:59 PM PST 24
Finished Feb 18 03:17:03 PM PST 24
Peak memory 216156 kb
Host smart-4f688958-dba1-4bdf-9304-3fbd6a1ac54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879995377 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3879995377
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.817644167
Short name T25
Test name
Test status
Simulation time 91402072 ps
CPU time 1.52 seconds
Started Feb 18 03:16:57 PM PST 24
Finished Feb 18 03:17:02 PM PST 24
Peak memory 217772 kb
Host smart-7141b3b0-52d0-4e6a-b62b-4b50dd469e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817644167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.817644167
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.207335813
Short name T759
Test name
Test status
Simulation time 32223081 ps
CPU time 1.11 seconds
Started Feb 18 03:17:06 PM PST 24
Finished Feb 18 03:17:11 PM PST 24
Peak memory 217568 kb
Host smart-5e89ea91-e7a4-4e9a-9a28-c04a98770bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207335813 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.207335813
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1604969621
Short name T790
Test name
Test status
Simulation time 80476378 ps
CPU time 1.39 seconds
Started Feb 18 03:17:04 PM PST 24
Finished Feb 18 03:17:09 PM PST 24
Peak memory 214768 kb
Host smart-8b0af361-7b4c-40ba-b6cf-2970fa9ba909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604969621 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1604969621
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3459259441
Short name T338
Test name
Test status
Simulation time 18915824 ps
CPU time 1.14 seconds
Started Feb 18 03:17:06 PM PST 24
Finished Feb 18 03:17:11 PM PST 24
Peak memory 222520 kb
Host smart-5cbe6337-e2ae-4d8a-b7f0-f413214d6737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459259441 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3459259441
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2835191269
Short name T697
Test name
Test status
Simulation time 70104722 ps
CPU time 2.57 seconds
Started Feb 18 03:17:07 PM PST 24
Finished Feb 18 03:17:13 PM PST 24
Peak memory 216168 kb
Host smart-59190c83-4642-4acc-9e30-9843f23fd78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835191269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2835191269
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.1451965335
Short name T541
Test name
Test status
Simulation time 43926159 ps
CPU time 1.01 seconds
Started Feb 18 03:17:16 PM PST 24
Finished Feb 18 03:17:22 PM PST 24
Peak memory 222504 kb
Host smart-bf3e1236-71c6-4140-a862-9ac2c9c2e2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451965335 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.1451965335
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2851710946
Short name T640
Test name
Test status
Simulation time 41266648 ps
CPU time 1.65 seconds
Started Feb 18 03:17:10 PM PST 24
Finished Feb 18 03:17:14 PM PST 24
Peak memory 216136 kb
Host smart-774eecb6-96d2-4846-9a44-e67e9050c2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851710946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2851710946
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.2106001650
Short name T168
Test name
Test status
Simulation time 90160741 ps
CPU time 1.12 seconds
Started Feb 18 03:17:13 PM PST 24
Finished Feb 18 03:17:17 PM PST 24
Peak memory 218616 kb
Host smart-61338a04-9457-4e59-bf30-0fc1cc0943ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106001650 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.2106001650
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2577829965
Short name T507
Test name
Test status
Simulation time 76804429 ps
CPU time 2.73 seconds
Started Feb 18 03:17:09 PM PST 24
Finished Feb 18 03:17:15 PM PST 24
Peak memory 218848 kb
Host smart-a7592972-4d09-4f68-ac9a-2fc70e919f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577829965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2577829965
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.681843348
Short name T467
Test name
Test status
Simulation time 79369746 ps
CPU time 0.92 seconds
Started Feb 18 03:17:17 PM PST 24
Finished Feb 18 03:17:23 PM PST 24
Peak memory 222248 kb
Host smart-976481a9-c104-43a3-b671-5582d08eb8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681843348 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.681843348
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3773151780
Short name T746
Test name
Test status
Simulation time 57574197 ps
CPU time 1.35 seconds
Started Feb 18 03:17:15 PM PST 24
Finished Feb 18 03:17:20 PM PST 24
Peak memory 217704 kb
Host smart-7e0ca4ac-1d00-4fbc-bf9b-392c9db5c852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773151780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3773151780
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%