Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.96 98.27 93.44 96.79 82.66 96.87 96.58 93.15


Total test records in report: 967
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T783 /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1639417160 Feb 25 01:30:03 PM PST 24 Feb 25 01:51:40 PM PST 24 735830066147 ps
T784 /workspace/coverage/default/11.edn_disable.684712100 Feb 25 01:29:19 PM PST 24 Feb 25 01:29:20 PM PST 24 21699465 ps
T785 /workspace/coverage/default/46.edn_genbits.2309894765 Feb 25 01:30:14 PM PST 24 Feb 25 01:30:16 PM PST 24 77327720 ps
T786 /workspace/coverage/default/33.edn_alert.3375262036 Feb 25 01:29:58 PM PST 24 Feb 25 01:29:59 PM PST 24 46415805 ps
T787 /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2045147522 Feb 25 01:30:14 PM PST 24 Feb 25 01:51:49 PM PST 24 106871739933 ps
T788 /workspace/coverage/default/116.edn_genbits.4284049075 Feb 25 01:30:57 PM PST 24 Feb 25 01:31:00 PM PST 24 91690029 ps
T789 /workspace/coverage/default/27.edn_genbits.912536027 Feb 25 01:29:35 PM PST 24 Feb 25 01:29:36 PM PST 24 399877443 ps
T790 /workspace/coverage/default/243.edn_genbits.1344653857 Feb 25 01:31:30 PM PST 24 Feb 25 01:31:32 PM PST 24 44915568 ps
T791 /workspace/coverage/default/251.edn_genbits.2703282604 Feb 25 01:31:20 PM PST 24 Feb 25 01:31:21 PM PST 24 89921647 ps
T54 /workspace/coverage/default/2.edn_sec_cm.2168980607 Feb 25 01:28:38 PM PST 24 Feb 25 01:28:41 PM PST 24 312237797 ps
T792 /workspace/coverage/default/44.edn_alert_test.2591096024 Feb 25 01:30:15 PM PST 24 Feb 25 01:30:16 PM PST 24 42109495 ps
T793 /workspace/coverage/default/288.edn_genbits.3593157417 Feb 25 01:31:37 PM PST 24 Feb 25 01:31:39 PM PST 24 65998148 ps
T794 /workspace/coverage/default/26.edn_alert.4041910413 Feb 25 01:29:34 PM PST 24 Feb 25 01:29:36 PM PST 24 30811277 ps
T795 /workspace/coverage/default/98.edn_genbits.2218600118 Feb 25 01:30:54 PM PST 24 Feb 25 01:30:57 PM PST 24 124336757 ps
T796 /workspace/coverage/default/48.edn_disable.3705517969 Feb 25 01:30:26 PM PST 24 Feb 25 01:30:28 PM PST 24 21576837 ps
T797 /workspace/coverage/default/44.edn_stress_all.674025913 Feb 25 01:30:18 PM PST 24 Feb 25 01:30:24 PM PST 24 570305904 ps
T798 /workspace/coverage/default/155.edn_genbits.1349602425 Feb 25 01:31:00 PM PST 24 Feb 25 01:31:01 PM PST 24 61881031 ps
T116 /workspace/coverage/default/6.edn_disable.3104697970 Feb 25 01:29:00 PM PST 24 Feb 25 01:29:02 PM PST 24 10177848 ps
T799 /workspace/coverage/default/9.edn_stress_all_with_rand_reset.800533103 Feb 25 01:29:14 PM PST 24 Feb 25 01:34:16 PM PST 24 13198554463 ps
T800 /workspace/coverage/default/245.edn_genbits.1324271773 Feb 25 01:31:36 PM PST 24 Feb 25 01:31:38 PM PST 24 60423606 ps
T801 /workspace/coverage/default/3.edn_intr.294882741 Feb 25 01:28:43 PM PST 24 Feb 25 01:28:44 PM PST 24 19914156 ps
T802 /workspace/coverage/default/1.edn_err.1433152928 Feb 25 01:28:36 PM PST 24 Feb 25 01:28:39 PM PST 24 37775135 ps
T803 /workspace/coverage/default/8.edn_alert_test.2526464756 Feb 25 01:29:12 PM PST 24 Feb 25 01:29:13 PM PST 24 44243413 ps
T804 /workspace/coverage/default/122.edn_genbits.2687887598 Feb 25 01:30:58 PM PST 24 Feb 25 01:30:59 PM PST 24 60058976 ps
T805 /workspace/coverage/default/278.edn_genbits.3739274984 Feb 25 01:31:31 PM PST 24 Feb 25 01:31:32 PM PST 24 39847075 ps
T806 /workspace/coverage/default/19.edn_disable_auto_req_mode.1831377154 Feb 25 01:29:30 PM PST 24 Feb 25 01:29:31 PM PST 24 120953433 ps
T807 /workspace/coverage/default/178.edn_genbits.314064425 Feb 25 01:31:03 PM PST 24 Feb 25 01:31:06 PM PST 24 84990752 ps
T808 /workspace/coverage/default/73.edn_err.4023534539 Feb 25 01:30:37 PM PST 24 Feb 25 01:30:39 PM PST 24 31255012 ps
T165 /workspace/coverage/default/30.edn_disable_auto_req_mode.3050566675 Feb 25 01:29:53 PM PST 24 Feb 25 01:29:55 PM PST 24 46346925 ps
T809 /workspace/coverage/default/22.edn_alert.2603696084 Feb 25 01:29:23 PM PST 24 Feb 25 01:29:25 PM PST 24 99001343 ps
T810 /workspace/coverage/default/164.edn_genbits.4162681659 Feb 25 01:31:03 PM PST 24 Feb 25 01:31:04 PM PST 24 95238554 ps
T811 /workspace/coverage/default/2.edn_alert.4176891768 Feb 25 01:28:50 PM PST 24 Feb 25 01:28:51 PM PST 24 44912113 ps
T812 /workspace/coverage/default/31.edn_smoke.2409994664 Feb 25 01:29:55 PM PST 24 Feb 25 01:29:56 PM PST 24 31361398 ps
T813 /workspace/coverage/default/33.edn_disable_auto_req_mode.3296951399 Feb 25 01:30:04 PM PST 24 Feb 25 01:30:06 PM PST 24 94215226 ps
T814 /workspace/coverage/default/274.edn_genbits.182623103 Feb 25 01:31:30 PM PST 24 Feb 25 01:31:31 PM PST 24 40946865 ps
T815 /workspace/coverage/default/3.edn_alert_test.2039645511 Feb 25 01:28:46 PM PST 24 Feb 25 01:28:48 PM PST 24 27809758 ps
T816 /workspace/coverage/default/284.edn_genbits.3194337346 Feb 25 01:31:33 PM PST 24 Feb 25 01:31:35 PM PST 24 125547256 ps
T817 /workspace/coverage/default/4.edn_genbits.324849908 Feb 25 01:28:51 PM PST 24 Feb 25 01:28:52 PM PST 24 88102724 ps
T818 /workspace/coverage/default/46.edn_alert_test.1382304757 Feb 25 01:30:22 PM PST 24 Feb 25 01:30:23 PM PST 24 33806376 ps
T819 /workspace/coverage/default/66.edn_err.1731815797 Feb 25 01:30:41 PM PST 24 Feb 25 01:30:42 PM PST 24 22743211 ps
T820 /workspace/coverage/default/68.edn_err.287370960 Feb 25 01:30:37 PM PST 24 Feb 25 01:30:38 PM PST 24 59299210 ps
T821 /workspace/coverage/default/40.edn_disable_auto_req_mode.497862750 Feb 25 01:30:13 PM PST 24 Feb 25 01:30:14 PM PST 24 334218188 ps
T822 /workspace/coverage/default/195.edn_genbits.2688268267 Feb 25 01:31:05 PM PST 24 Feb 25 01:31:06 PM PST 24 54863288 ps
T823 /workspace/coverage/default/78.edn_genbits.195935315 Feb 25 01:30:46 PM PST 24 Feb 25 01:30:48 PM PST 24 38230583 ps
T824 /workspace/coverage/default/29.edn_err.2053869961 Feb 25 01:29:48 PM PST 24 Feb 25 01:29:49 PM PST 24 19948602 ps
T825 /workspace/coverage/default/5.edn_alert.3349287764 Feb 25 01:29:07 PM PST 24 Feb 25 01:29:09 PM PST 24 86490510 ps
T826 /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1579515062 Feb 25 01:29:23 PM PST 24 Feb 25 01:44:34 PM PST 24 40087062465 ps
T827 /workspace/coverage/default/249.edn_genbits.3853068582 Feb 25 01:31:37 PM PST 24 Feb 25 01:31:39 PM PST 24 185524636 ps
T828 /workspace/coverage/default/281.edn_genbits.4221915436 Feb 25 01:31:34 PM PST 24 Feb 25 01:31:35 PM PST 24 148119043 ps
T829 /workspace/coverage/default/198.edn_genbits.1141178770 Feb 25 01:31:14 PM PST 24 Feb 25 01:31:16 PM PST 24 46890238 ps
T830 /workspace/coverage/default/12.edn_disable.1196738207 Feb 25 01:29:18 PM PST 24 Feb 25 01:29:19 PM PST 24 36052741 ps
T831 /workspace/coverage/default/17.edn_smoke.737838861 Feb 25 01:29:24 PM PST 24 Feb 25 01:29:25 PM PST 24 25367938 ps
T832 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1179190156 Feb 25 12:27:44 PM PST 24 Feb 25 12:27:47 PM PST 24 110382771 ps
T220 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2134533586 Feb 25 12:28:34 PM PST 24 Feb 25 12:28:35 PM PST 24 14765318 ps
T833 /workspace/coverage/cover_reg_top/16.edn_intr_test.2906914207 Feb 25 12:28:58 PM PST 24 Feb 25 12:28:59 PM PST 24 50085299 ps
T221 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2711732188 Feb 25 12:28:52 PM PST 24 Feb 25 12:28:53 PM PST 24 13949337 ps
T834 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.4016537528 Feb 25 12:27:48 PM PST 24 Feb 25 12:27:50 PM PST 24 23288467 ps
T222 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2478844723 Feb 25 12:28:59 PM PST 24 Feb 25 12:29:00 PM PST 24 41186088 ps
T835 /workspace/coverage/cover_reg_top/9.edn_tl_errors.845796663 Feb 25 12:28:43 PM PST 24 Feb 25 12:28:45 PM PST 24 47548653 ps
T223 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.179952005 Feb 25 12:28:52 PM PST 24 Feb 25 12:28:54 PM PST 24 79927962 ps
T836 /workspace/coverage/cover_reg_top/1.edn_intr_test.398814494 Feb 25 12:27:46 PM PST 24 Feb 25 12:27:47 PM PST 24 31421255 ps
T837 /workspace/coverage/cover_reg_top/42.edn_intr_test.2230076340 Feb 25 12:29:14 PM PST 24 Feb 25 12:29:15 PM PST 24 26711559 ps
T224 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2968045084 Feb 25 12:27:51 PM PST 24 Feb 25 12:27:53 PM PST 24 30792369 ps
T838 /workspace/coverage/cover_reg_top/19.edn_intr_test.433589969 Feb 25 12:29:01 PM PST 24 Feb 25 12:29:02 PM PST 24 22904187 ps
T839 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3767069886 Feb 25 12:27:44 PM PST 24 Feb 25 12:27:47 PM PST 24 143116506 ps
T234 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2575172184 Feb 25 12:28:48 PM PST 24 Feb 25 12:28:49 PM PST 24 123954492 ps
T840 /workspace/coverage/cover_reg_top/5.edn_intr_test.375675458 Feb 25 12:28:45 PM PST 24 Feb 25 12:28:46 PM PST 24 22323745 ps
T238 /workspace/coverage/cover_reg_top/8.edn_csr_rw.3939631210 Feb 25 12:28:47 PM PST 24 Feb 25 12:28:48 PM PST 24 36443012 ps
T841 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1171274064 Feb 25 12:27:44 PM PST 24 Feb 25 12:27:50 PM PST 24 224681556 ps
T842 /workspace/coverage/cover_reg_top/36.edn_intr_test.984136776 Feb 25 12:29:20 PM PST 24 Feb 25 12:29:21 PM PST 24 44133911 ps
T843 /workspace/coverage/cover_reg_top/5.edn_tl_errors.4212037529 Feb 25 12:27:49 PM PST 24 Feb 25 12:27:51 PM PST 24 324381184 ps
T844 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3697663028 Feb 25 12:27:49 PM PST 24 Feb 25 12:27:51 PM PST 24 88666473 ps
T845 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2763006945 Feb 25 12:29:15 PM PST 24 Feb 25 12:29:17 PM PST 24 109907430 ps
T239 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4197568883 Feb 25 12:29:12 PM PST 24 Feb 25 12:29:14 PM PST 24 140074203 ps
T846 /workspace/coverage/cover_reg_top/10.edn_intr_test.712481155 Feb 25 12:28:46 PM PST 24 Feb 25 12:28:48 PM PST 24 14414782 ps
T847 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2805917548 Feb 25 12:28:59 PM PST 24 Feb 25 12:29:00 PM PST 24 24738345 ps
T848 /workspace/coverage/cover_reg_top/0.edn_tl_errors.726100989 Feb 25 12:27:46 PM PST 24 Feb 25 12:27:50 PM PST 24 40412714 ps
T849 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3415551672 Feb 25 12:28:51 PM PST 24 Feb 25 12:28:52 PM PST 24 71116971 ps
T850 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.72172668 Feb 25 12:27:45 PM PST 24 Feb 25 12:27:46 PM PST 24 58113136 ps
T851 /workspace/coverage/cover_reg_top/41.edn_intr_test.3965191259 Feb 25 12:29:03 PM PST 24 Feb 25 12:29:04 PM PST 24 13263637 ps
T852 /workspace/coverage/cover_reg_top/23.edn_intr_test.546350305 Feb 25 12:28:58 PM PST 24 Feb 25 12:28:59 PM PST 24 11007030 ps
T240 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3743808413 Feb 25 12:28:50 PM PST 24 Feb 25 12:28:52 PM PST 24 115149906 ps
T241 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.4259551367 Feb 25 12:29:18 PM PST 24 Feb 25 12:29:21 PM PST 24 146980194 ps
T249 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.915525209 Feb 25 12:27:51 PM PST 24 Feb 25 12:27:54 PM PST 24 112205694 ps
T853 /workspace/coverage/cover_reg_top/40.edn_intr_test.2447176434 Feb 25 12:29:04 PM PST 24 Feb 25 12:29:05 PM PST 24 37174051 ps
T235 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1102389644 Feb 25 12:27:48 PM PST 24 Feb 25 12:27:50 PM PST 24 61847748 ps
T854 /workspace/coverage/cover_reg_top/0.edn_intr_test.3037818748 Feb 25 12:27:46 PM PST 24 Feb 25 12:27:47 PM PST 24 24303727 ps
T855 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3719090157 Feb 25 12:28:52 PM PST 24 Feb 25 12:28:54 PM PST 24 23969800 ps
T856 /workspace/coverage/cover_reg_top/2.edn_intr_test.484750596 Feb 25 12:27:44 PM PST 24 Feb 25 12:27:46 PM PST 24 87509842 ps
T857 /workspace/coverage/cover_reg_top/22.edn_intr_test.3659763816 Feb 25 12:28:51 PM PST 24 Feb 25 12:28:52 PM PST 24 39758686 ps
T858 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.4237084829 Feb 25 12:27:56 PM PST 24 Feb 25 12:27:58 PM PST 24 658592698 ps
T859 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2983101156 Feb 25 12:28:51 PM PST 24 Feb 25 12:28:52 PM PST 24 40816825 ps
T860 /workspace/coverage/cover_reg_top/27.edn_intr_test.3688543439 Feb 25 12:29:02 PM PST 24 Feb 25 12:29:03 PM PST 24 16533706 ps
T225 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.650142355 Feb 25 12:27:48 PM PST 24 Feb 25 12:27:50 PM PST 24 247042541 ps
T861 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3695346859 Feb 25 12:28:54 PM PST 24 Feb 25 12:28:56 PM PST 24 154081371 ps
T862 /workspace/coverage/cover_reg_top/1.edn_csr_rw.992010208 Feb 25 12:27:51 PM PST 24 Feb 25 12:27:52 PM PST 24 14515780 ps
T863 /workspace/coverage/cover_reg_top/7.edn_intr_test.2048656017 Feb 25 12:28:49 PM PST 24 Feb 25 12:28:50 PM PST 24 13834420 ps
T251 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.426814073 Feb 25 12:28:58 PM PST 24 Feb 25 12:29:01 PM PST 24 103851178 ps
T864 /workspace/coverage/cover_reg_top/15.edn_intr_test.2331603625 Feb 25 12:29:01 PM PST 24 Feb 25 12:29:02 PM PST 24 16091596 ps
T865 /workspace/coverage/cover_reg_top/45.edn_intr_test.2065906804 Feb 25 12:29:12 PM PST 24 Feb 25 12:29:13 PM PST 24 23113857 ps
T866 /workspace/coverage/cover_reg_top/10.edn_tl_errors.1306353048 Feb 25 12:28:49 PM PST 24 Feb 25 12:28:51 PM PST 24 35744237 ps
T254 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2547644532 Feb 25 12:28:47 PM PST 24 Feb 25 12:28:49 PM PST 24 99357190 ps
T250 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3159062980 Feb 25 12:29:01 PM PST 24 Feb 25 12:29:02 PM PST 24 75321263 ps
T867 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2601434220 Feb 25 12:27:44 PM PST 24 Feb 25 12:27:49 PM PST 24 134365842 ps
T226 /workspace/coverage/cover_reg_top/0.edn_csr_rw.1412919272 Feb 25 12:27:46 PM PST 24 Feb 25 12:27:47 PM PST 24 36560724 ps
T868 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1682828394 Feb 25 12:28:52 PM PST 24 Feb 25 12:28:53 PM PST 24 62475133 ps
T869 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1758351926 Feb 25 12:27:48 PM PST 24 Feb 25 12:27:51 PM PST 24 59304459 ps
T227 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2777607669 Feb 25 12:28:48 PM PST 24 Feb 25 12:28:49 PM PST 24 132446977 ps
T255 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1241066145 Feb 25 12:28:54 PM PST 24 Feb 25 12:28:57 PM PST 24 1259295130 ps
T870 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3628246907 Feb 25 12:28:59 PM PST 24 Feb 25 12:29:01 PM PST 24 30871027 ps
T871 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1454221482 Feb 25 12:28:53 PM PST 24 Feb 25 12:28:57 PM PST 24 119637920 ps
T228 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3633803383 Feb 25 12:29:07 PM PST 24 Feb 25 12:29:08 PM PST 24 23802011 ps
T872 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1412765985 Feb 25 12:29:20 PM PST 24 Feb 25 12:29:21 PM PST 24 20214263 ps
T873 /workspace/coverage/cover_reg_top/35.edn_intr_test.3527075294 Feb 25 12:28:50 PM PST 24 Feb 25 12:28:51 PM PST 24 14576959 ps
T229 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3360469555 Feb 25 12:27:44 PM PST 24 Feb 25 12:27:46 PM PST 24 26029334 ps
T874 /workspace/coverage/cover_reg_top/14.edn_intr_test.3791832958 Feb 25 12:28:56 PM PST 24 Feb 25 12:28:57 PM PST 24 14779321 ps
T875 /workspace/coverage/cover_reg_top/13.edn_intr_test.1821973415 Feb 25 12:28:31 PM PST 24 Feb 25 12:28:32 PM PST 24 16010521 ps
T876 /workspace/coverage/cover_reg_top/15.edn_csr_rw.92468966 Feb 25 12:28:45 PM PST 24 Feb 25 12:28:46 PM PST 24 23281783 ps
T877 /workspace/coverage/cover_reg_top/19.edn_tl_errors.142679215 Feb 25 12:28:55 PM PST 24 Feb 25 12:28:58 PM PST 24 266492576 ps
T878 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3335654304 Feb 25 12:28:43 PM PST 24 Feb 25 12:28:45 PM PST 24 64482828 ps
T879 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1589604039 Feb 25 12:28:48 PM PST 24 Feb 25 12:28:49 PM PST 24 45789270 ps
T236 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1510138246 Feb 25 12:28:45 PM PST 24 Feb 25 12:28:47 PM PST 24 177000732 ps
T230 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2289579727 Feb 25 12:28:55 PM PST 24 Feb 25 12:28:56 PM PST 24 13208432 ps
T880 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2649982003 Feb 25 12:27:52 PM PST 24 Feb 25 12:27:53 PM PST 24 48712187 ps
T881 /workspace/coverage/cover_reg_top/34.edn_intr_test.2339181989 Feb 25 12:28:59 PM PST 24 Feb 25 12:29:01 PM PST 24 28213568 ps
T231 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2201819385 Feb 25 12:27:50 PM PST 24 Feb 25 12:27:52 PM PST 24 49842594 ps
T882 /workspace/coverage/cover_reg_top/48.edn_intr_test.4064729203 Feb 25 12:29:16 PM PST 24 Feb 25 12:29:16 PM PST 24 55200841 ps
T883 /workspace/coverage/cover_reg_top/3.edn_intr_test.1341974309 Feb 25 12:27:49 PM PST 24 Feb 25 12:27:51 PM PST 24 25428510 ps
T884 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2095583206 Feb 25 12:27:51 PM PST 24 Feb 25 12:27:52 PM PST 24 50525960 ps
T885 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2998646303 Feb 25 12:29:01 PM PST 24 Feb 25 12:29:02 PM PST 24 72560709 ps
T256 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4111013515 Feb 25 12:29:12 PM PST 24 Feb 25 12:29:14 PM PST 24 188942064 ps
T232 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.919197698 Feb 25 12:27:53 PM PST 24 Feb 25 12:27:54 PM PST 24 16714199 ps
T886 /workspace/coverage/cover_reg_top/37.edn_intr_test.931228047 Feb 25 12:29:15 PM PST 24 Feb 25 12:29:17 PM PST 24 48606974 ps
T887 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2997000836 Feb 25 12:27:49 PM PST 24 Feb 25 12:27:53 PM PST 24 514498397 ps
T888 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3258511315 Feb 25 12:28:45 PM PST 24 Feb 25 12:28:51 PM PST 24 87387256 ps
T889 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3685821376 Feb 25 12:29:10 PM PST 24 Feb 25 12:29:12 PM PST 24 93390427 ps
T890 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2174248567 Feb 25 12:27:52 PM PST 24 Feb 25 12:27:54 PM PST 24 16474234 ps
T891 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.456409953 Feb 25 12:28:58 PM PST 24 Feb 25 12:29:00 PM PST 24 19130662 ps
T892 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3321707105 Feb 25 12:28:54 PM PST 24 Feb 25 12:28:56 PM PST 24 22800457 ps
T252 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2107084476 Feb 25 12:28:46 PM PST 24 Feb 25 12:28:48 PM PST 24 71750406 ps
T893 /workspace/coverage/cover_reg_top/30.edn_intr_test.2353863521 Feb 25 12:29:05 PM PST 24 Feb 25 12:29:06 PM PST 24 14027251 ps
T894 /workspace/coverage/cover_reg_top/12.edn_csr_rw.2644010692 Feb 25 12:28:39 PM PST 24 Feb 25 12:28:39 PM PST 24 65526856 ps
T253 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1858456888 Feb 25 12:28:58 PM PST 24 Feb 25 12:29:00 PM PST 24 113848096 ps
T895 /workspace/coverage/cover_reg_top/49.edn_intr_test.3587049696 Feb 25 12:29:05 PM PST 24 Feb 25 12:29:06 PM PST 24 12589409 ps
T896 /workspace/coverage/cover_reg_top/25.edn_intr_test.1149915502 Feb 25 12:28:57 PM PST 24 Feb 25 12:28:58 PM PST 24 26625800 ps
T897 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.4208220475 Feb 25 12:28:46 PM PST 24 Feb 25 12:28:47 PM PST 24 91566186 ps
T898 /workspace/coverage/cover_reg_top/33.edn_intr_test.3095952650 Feb 25 12:29:07 PM PST 24 Feb 25 12:29:09 PM PST 24 13040303 ps
T899 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1385522842 Feb 25 12:29:23 PM PST 24 Feb 25 12:29:24 PM PST 24 54300170 ps
T900 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2645491061 Feb 25 12:28:51 PM PST 24 Feb 25 12:28:53 PM PST 24 40469072 ps
T901 /workspace/coverage/cover_reg_top/43.edn_intr_test.4006550713 Feb 25 12:29:20 PM PST 24 Feb 25 12:29:21 PM PST 24 11982539 ps
T902 /workspace/coverage/cover_reg_top/28.edn_intr_test.3863978811 Feb 25 12:29:02 PM PST 24 Feb 25 12:29:04 PM PST 24 18742024 ps
T903 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2039874084 Feb 25 12:27:45 PM PST 24 Feb 25 12:27:46 PM PST 24 25176556 ps
T904 /workspace/coverage/cover_reg_top/47.edn_intr_test.3940444177 Feb 25 12:28:57 PM PST 24 Feb 25 12:28:58 PM PST 24 22266646 ps
T905 /workspace/coverage/cover_reg_top/8.edn_intr_test.1296141274 Feb 25 12:29:01 PM PST 24 Feb 25 12:29:02 PM PST 24 20387657 ps
T906 /workspace/coverage/cover_reg_top/18.edn_intr_test.2931815440 Feb 25 12:29:03 PM PST 24 Feb 25 12:29:04 PM PST 24 25872556 ps
T907 /workspace/coverage/cover_reg_top/44.edn_intr_test.4108606024 Feb 25 12:29:22 PM PST 24 Feb 25 12:29:23 PM PST 24 49462149 ps
T908 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2426545306 Feb 25 12:27:51 PM PST 24 Feb 25 12:27:52 PM PST 24 15936950 ps
T909 /workspace/coverage/cover_reg_top/21.edn_intr_test.1938889968 Feb 25 12:29:02 PM PST 24 Feb 25 12:29:03 PM PST 24 13134469 ps
T233 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2883663766 Feb 25 12:27:48 PM PST 24 Feb 25 12:27:50 PM PST 24 10842806 ps
T910 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2429550660 Feb 25 12:27:50 PM PST 24 Feb 25 12:27:52 PM PST 24 48941473 ps
T911 /workspace/coverage/cover_reg_top/38.edn_intr_test.2730796004 Feb 25 12:29:14 PM PST 24 Feb 25 12:29:15 PM PST 24 135691060 ps
T912 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3150846824 Feb 25 12:28:43 PM PST 24 Feb 25 12:28:44 PM PST 24 20843327 ps
T913 /workspace/coverage/cover_reg_top/13.edn_tl_errors.3206410859 Feb 25 12:28:44 PM PST 24 Feb 25 12:28:46 PM PST 24 106492757 ps
T914 /workspace/coverage/cover_reg_top/46.edn_intr_test.1486586686 Feb 25 12:29:12 PM PST 24 Feb 25 12:29:14 PM PST 24 33339467 ps
T915 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2891050273 Feb 25 12:28:57 PM PST 24 Feb 25 12:28:59 PM PST 24 56100432 ps
T916 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.99578584 Feb 25 12:27:48 PM PST 24 Feb 25 12:27:50 PM PST 24 46175995 ps
T917 /workspace/coverage/cover_reg_top/12.edn_intr_test.2549080871 Feb 25 12:28:52 PM PST 24 Feb 25 12:28:53 PM PST 24 104117300 ps
T918 /workspace/coverage/cover_reg_top/3.edn_csr_rw.943736695 Feb 25 12:27:51 PM PST 24 Feb 25 12:27:52 PM PST 24 13663273 ps
T919 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2192009295 Feb 25 12:28:59 PM PST 24 Feb 25 12:29:03 PM PST 24 368702646 ps
T920 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1149704701 Feb 25 12:27:49 PM PST 24 Feb 25 12:27:51 PM PST 24 236308853 ps
T921 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1888191198 Feb 25 12:28:59 PM PST 24 Feb 25 12:29:00 PM PST 24 44222917 ps
T922 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3805257342 Feb 25 12:29:01 PM PST 24 Feb 25 12:29:04 PM PST 24 295808292 ps
T923 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3659846947 Feb 25 12:28:58 PM PST 24 Feb 25 12:29:01 PM PST 24 263416213 ps
T924 /workspace/coverage/cover_reg_top/11.edn_intr_test.448895176 Feb 25 12:28:38 PM PST 24 Feb 25 12:28:41 PM PST 24 35555312 ps
T925 /workspace/coverage/cover_reg_top/7.edn_csr_rw.3763845316 Feb 25 12:28:55 PM PST 24 Feb 25 12:28:56 PM PST 24 40860722 ps
T926 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2112681696 Feb 25 12:27:48 PM PST 24 Feb 25 12:27:50 PM PST 24 103856398 ps
T927 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3008917310 Feb 25 12:28:46 PM PST 24 Feb 25 12:28:47 PM PST 24 43986093 ps
T928 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3861732051 Feb 25 12:27:54 PM PST 24 Feb 25 12:27:57 PM PST 24 98447459 ps
T929 /workspace/coverage/cover_reg_top/18.edn_csr_rw.152439969 Feb 25 12:28:50 PM PST 24 Feb 25 12:28:51 PM PST 24 15768150 ps
T930 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2314461088 Feb 25 12:28:58 PM PST 24 Feb 25 12:28:59 PM PST 24 17056805 ps
T931 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2707156991 Feb 25 12:27:44 PM PST 24 Feb 25 12:27:47 PM PST 24 620915039 ps
T932 /workspace/coverage/cover_reg_top/29.edn_intr_test.2909148515 Feb 25 12:29:05 PM PST 24 Feb 25 12:29:06 PM PST 24 135961848 ps
T933 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2021353074 Feb 25 12:27:50 PM PST 24 Feb 25 12:27:53 PM PST 24 220431816 ps
T934 /workspace/coverage/cover_reg_top/31.edn_intr_test.3536025410 Feb 25 12:29:07 PM PST 24 Feb 25 12:29:10 PM PST 24 22283834 ps
T935 /workspace/coverage/cover_reg_top/12.edn_tl_errors.679280815 Feb 25 12:28:54 PM PST 24 Feb 25 12:28:57 PM PST 24 79940695 ps
T936 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2741104931 Feb 25 12:27:47 PM PST 24 Feb 25 12:27:49 PM PST 24 28200314 ps
T937 /workspace/coverage/cover_reg_top/9.edn_intr_test.1533975059 Feb 25 12:28:46 PM PST 24 Feb 25 12:28:47 PM PST 24 32922866 ps
T938 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1924160957 Feb 25 12:28:55 PM PST 24 Feb 25 12:28:57 PM PST 24 168466755 ps
T939 /workspace/coverage/cover_reg_top/3.edn_tl_errors.376294841 Feb 25 12:27:44 PM PST 24 Feb 25 12:27:48 PM PST 24 336670655 ps
T940 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.304484172 Feb 25 12:29:04 PM PST 24 Feb 25 12:29:05 PM PST 24 211510280 ps
T941 /workspace/coverage/cover_reg_top/17.edn_intr_test.887077775 Feb 25 12:28:53 PM PST 24 Feb 25 12:28:54 PM PST 24 11035289 ps
T942 /workspace/coverage/cover_reg_top/39.edn_intr_test.4198237043 Feb 25 12:29:05 PM PST 24 Feb 25 12:29:06 PM PST 24 40254690 ps
T943 /workspace/coverage/cover_reg_top/4.edn_intr_test.3730785918 Feb 25 12:27:55 PM PST 24 Feb 25 12:27:56 PM PST 24 21552194 ps
T944 /workspace/coverage/cover_reg_top/26.edn_intr_test.876019812 Feb 25 12:28:47 PM PST 24 Feb 25 12:28:48 PM PST 24 49260864 ps
T945 /workspace/coverage/cover_reg_top/6.edn_intr_test.1061872312 Feb 25 12:28:51 PM PST 24 Feb 25 12:28:54 PM PST 24 25741757 ps
T946 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1193184901 Feb 25 12:27:54 PM PST 24 Feb 25 12:27:56 PM PST 24 42679741 ps
T947 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1099809566 Feb 25 12:28:44 PM PST 24 Feb 25 12:28:47 PM PST 24 168393344 ps
T948 /workspace/coverage/cover_reg_top/18.edn_tl_errors.1038272549 Feb 25 12:29:04 PM PST 24 Feb 25 12:29:06 PM PST 24 192129970 ps
T949 /workspace/coverage/cover_reg_top/15.edn_tl_errors.4257263803 Feb 25 12:28:57 PM PST 24 Feb 25 12:29:00 PM PST 24 34185558 ps
T950 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1317578301 Feb 25 12:27:53 PM PST 24 Feb 25 12:27:55 PM PST 24 28079745 ps
T951 /workspace/coverage/cover_reg_top/13.edn_csr_rw.2701256703 Feb 25 12:28:54 PM PST 24 Feb 25 12:28:55 PM PST 24 14852656 ps
T952 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2755720284 Feb 25 12:28:57 PM PST 24 Feb 25 12:28:58 PM PST 24 53471878 ps
T953 /workspace/coverage/cover_reg_top/32.edn_intr_test.1363972179 Feb 25 12:28:53 PM PST 24 Feb 25 12:28:54 PM PST 24 42120083 ps
T954 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1632942172 Feb 25 12:29:04 PM PST 24 Feb 25 12:29:05 PM PST 24 30177056 ps
T955 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3859378349 Feb 25 12:27:52 PM PST 24 Feb 25 12:27:54 PM PST 24 15705087 ps
T956 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3501239431 Feb 25 12:28:54 PM PST 24 Feb 25 12:28:58 PM PST 24 189005524 ps
T957 /workspace/coverage/cover_reg_top/6.edn_tl_errors.714129284 Feb 25 12:28:44 PM PST 24 Feb 25 12:28:48 PM PST 24 810128984 ps
T958 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3227415858 Feb 25 12:28:45 PM PST 24 Feb 25 12:28:46 PM PST 24 70654753 ps
T959 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.215766059 Feb 25 12:28:48 PM PST 24 Feb 25 12:28:50 PM PST 24 37650366 ps
T960 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3169023677 Feb 25 12:27:51 PM PST 24 Feb 25 12:27:52 PM PST 24 26914652 ps
T961 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2001476784 Feb 25 12:28:38 PM PST 24 Feb 25 12:28:41 PM PST 24 61300619 ps
T962 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2758639760 Feb 25 12:29:02 PM PST 24 Feb 25 12:29:04 PM PST 24 89194882 ps
T963 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.307043359 Feb 25 12:28:57 PM PST 24 Feb 25 12:28:59 PM PST 24 70767995 ps
T964 /workspace/coverage/cover_reg_top/9.edn_csr_rw.43586445 Feb 25 12:28:54 PM PST 24 Feb 25 12:28:55 PM PST 24 38344699 ps
T965 /workspace/coverage/cover_reg_top/20.edn_intr_test.804564420 Feb 25 12:29:02 PM PST 24 Feb 25 12:29:03 PM PST 24 16299584 ps
T966 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2552339139 Feb 25 12:27:50 PM PST 24 Feb 25 12:27:53 PM PST 24 191681464 ps
T967 /workspace/coverage/cover_reg_top/24.edn_intr_test.373895946 Feb 25 12:28:57 PM PST 24 Feb 25 12:28:58 PM PST 24 24041707 ps

Test location /workspace/coverage/default/106.edn_genbits.1574186407
Short name T22
Test name
Test status
Simulation time 109717412 ps
CPU time 1.23 seconds
Started Feb 25 01:30:51 PM PST 24
Finished Feb 25 01:30:53 PM PST 24
Peak memory 216172 kb
Host smart-cc9b1dc1-5ec0-4bd7-9894-103446f73a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574186407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1574186407
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2360319827
Short name T3
Test name
Test status
Simulation time 100636893 ps
CPU time 1.4 seconds
Started Feb 25 01:29:37 PM PST 24
Finished Feb 25 01:29:39 PM PST 24
Peak memory 215112 kb
Host smart-af2b50ae-08f2-4354-a51a-008944536aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360319827 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2360319827
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.2780919095
Short name T19
Test name
Test status
Simulation time 65104048264 ps
CPU time 820.4 seconds
Started Feb 25 01:30:13 PM PST 24
Finished Feb 25 01:43:54 PM PST 24
Peak memory 219180 kb
Host smart-06d4b84d-a478-4c25-b734-213170ed447c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780919095 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.2780919095
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/138.edn_genbits.1265496780
Short name T25
Test name
Test status
Simulation time 31379965 ps
CPU time 1.39 seconds
Started Feb 25 01:31:10 PM PST 24
Finished Feb 25 01:31:11 PM PST 24
Peak memory 217332 kb
Host smart-82ad11c2-40e6-484b-87c1-99337f0a672d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265496780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1265496780
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.236658080
Short name T2
Test name
Test status
Simulation time 31823555 ps
CPU time 1.01 seconds
Started Feb 25 01:30:42 PM PST 24
Finished Feb 25 01:30:44 PM PST 24
Peak memory 217560 kb
Host smart-e84d7b3f-1adc-422a-8a31-4611bebef501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236658080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.236658080
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1586045590
Short name T15
Test name
Test status
Simulation time 579994948 ps
CPU time 3.34 seconds
Started Feb 25 01:28:40 PM PST 24
Finished Feb 25 01:28:43 PM PST 24
Peak memory 233880 kb
Host smart-08189862-3cf5-4e51-ada0-cd699f2b3dce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586045590 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1586045590
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/53.edn_err.562850735
Short name T9
Test name
Test status
Simulation time 23477283 ps
CPU time 1.05 seconds
Started Feb 25 01:30:41 PM PST 24
Finished Feb 25 01:30:42 PM PST 24
Peak memory 222400 kb
Host smart-6d0118cf-7bd4-417f-8b3e-9c381480ba96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562850735 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.562850735
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/19.edn_stress_all.1913717525
Short name T41
Test name
Test status
Simulation time 442688234 ps
CPU time 5.3 seconds
Started Feb 25 01:29:21 PM PST 24
Finished Feb 25 01:29:26 PM PST 24
Peak memory 214732 kb
Host smart-972aec81-6a3e-4090-a9aa-64bf19269fcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913717525 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1913717525
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3337388250
Short name T70
Test name
Test status
Simulation time 81713039 ps
CPU time 1.07 seconds
Started Feb 25 01:29:11 PM PST 24
Finished Feb 25 01:29:13 PM PST 24
Peak memory 215604 kb
Host smart-6866cd3c-04f8-4b7b-9977-1a5b0e43d0dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337388250 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3337388250
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1625827254
Short name T195
Test name
Test status
Simulation time 44869772826 ps
CPU time 969.55 seconds
Started Feb 25 01:28:40 PM PST 24
Finished Feb 25 01:44:50 PM PST 24
Peak memory 223056 kb
Host smart-05b3046e-00a0-4f3c-a6b8-481a8ff3c604
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625827254 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1625827254
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.edn_alert.1822974200
Short name T104
Test name
Test status
Simulation time 91571154 ps
CPU time 1.18 seconds
Started Feb 25 01:29:16 PM PST 24
Finished Feb 25 01:29:17 PM PST 24
Peak memory 215112 kb
Host smart-0e10a7c6-c47c-4424-9e6e-ce0cb925f845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822974200 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1822974200
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/85.edn_genbits.1613257941
Short name T33
Test name
Test status
Simulation time 463026622 ps
CPU time 3.91 seconds
Started Feb 25 01:30:40 PM PST 24
Finished Feb 25 01:30:44 PM PST 24
Peak memory 218340 kb
Host smart-388a84f0-bf4a-4955-b3e2-0cca05f1477c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613257941 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1613257941
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.3687029676
Short name T288
Test name
Test status
Simulation time 25936557 ps
CPU time 0.88 seconds
Started Feb 25 01:28:38 PM PST 24
Finished Feb 25 01:28:39 PM PST 24
Peak memory 206472 kb
Host smart-b52cf89a-654b-41fa-8894-4c6b0b19b620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687029676 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3687029676
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/14.edn_intr.3002489541
Short name T35
Test name
Test status
Simulation time 31154090 ps
CPU time 0.83 seconds
Started Feb 25 01:29:17 PM PST 24
Finished Feb 25 01:29:18 PM PST 24
Peak memory 214596 kb
Host smart-4d7f1f41-02b7-44e0-9eb7-23eea73c0876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002489541 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3002489541
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_alert.3256991824
Short name T297
Test name
Test status
Simulation time 29093406 ps
CPU time 1.21 seconds
Started Feb 25 01:29:13 PM PST 24
Finished Feb 25 01:29:14 PM PST 24
Peak memory 215112 kb
Host smart-8fcf4d90-ce5e-4b0b-8a42-070260d66b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256991824 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3256991824
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1412919272
Short name T226
Test name
Test status
Simulation time 36560724 ps
CPU time 0.99 seconds
Started Feb 25 12:27:46 PM PST 24
Finished Feb 25 12:27:47 PM PST 24
Peak memory 204972 kb
Host smart-57850846-ca46-498d-89dc-5d6787d4a991
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412919272 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1412919272
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1241066145
Short name T255
Test name
Test status
Simulation time 1259295130 ps
CPU time 2.95 seconds
Started Feb 25 12:28:54 PM PST 24
Finished Feb 25 12:28:57 PM PST 24
Peak memory 205692 kb
Host smart-2a142b2c-e1a8-4e6c-a97c-2a13525f77fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241066145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1241066145
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/default/37.edn_alert.2770765176
Short name T106
Test name
Test status
Simulation time 66616472 ps
CPU time 1.14 seconds
Started Feb 25 01:30:01 PM PST 24
Finished Feb 25 01:30:03 PM PST 24
Peak memory 215108 kb
Host smart-14e0449f-1dd6-41fa-8993-b5406f088ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770765176 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2770765176
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/19.edn_disable.2305182392
Short name T119
Test name
Test status
Simulation time 65182789 ps
CPU time 0.82 seconds
Started Feb 25 01:29:22 PM PST 24
Finished Feb 25 01:29:23 PM PST 24
Peak memory 215116 kb
Host smart-aa1539c9-cbd9-417f-8e5d-03217c5a9270
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305182392 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2305182392
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable.684712100
Short name T784
Test name
Test status
Simulation time 21699465 ps
CPU time 0.88 seconds
Started Feb 25 01:29:19 PM PST 24
Finished Feb 25 01:29:20 PM PST 24
Peak memory 215232 kb
Host smart-91c8668a-8ba5-4933-9b8d-bcc632c3f93f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684712100 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.684712100
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3354774508
Short name T177
Test name
Test status
Simulation time 34982722 ps
CPU time 1.25 seconds
Started Feb 25 01:29:13 PM PST 24
Finished Feb 25 01:29:15 PM PST 24
Peak memory 215776 kb
Host smart-1d4af8d5-f2bd-4931-ae78-57b2dddf4481
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354774508 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3354774508
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_disable.561956451
Short name T109
Test name
Test status
Simulation time 15858461 ps
CPU time 0.83 seconds
Started Feb 25 01:29:23 PM PST 24
Finished Feb 25 01:29:24 PM PST 24
Peak memory 214968 kb
Host smart-e79cb75e-f011-4058-ab3b-0f688813129e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561956451 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.561956451
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/15.edn_intr.3431105928
Short name T131
Test name
Test status
Simulation time 34113304 ps
CPU time 0.91 seconds
Started Feb 25 01:29:21 PM PST 24
Finished Feb 25 01:29:22 PM PST 24
Peak memory 214980 kb
Host smart-505b7976-17e4-4970-b2b2-80e648b985c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431105928 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3431105928
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.302404149
Short name T72
Test name
Test status
Simulation time 54034436 ps
CPU time 1.18 seconds
Started Feb 25 01:29:33 PM PST 24
Finished Feb 25 01:29:35 PM PST 24
Peak memory 217340 kb
Host smart-09417ae9-56f5-4e22-9b56-db0d736f913e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302404149 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_di
sable_auto_req_mode.302404149
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_intr.2828005713
Short name T305
Test name
Test status
Simulation time 23196189 ps
CPU time 1 seconds
Started Feb 25 01:30:03 PM PST 24
Finished Feb 25 01:30:04 PM PST 24
Peak memory 214824 kb
Host smart-d3169148-e1f6-46b2-938e-f1f6bc8dce46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828005713 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2828005713
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/239.edn_genbits.1150716860
Short name T29
Test name
Test status
Simulation time 38377511 ps
CPU time 1.36 seconds
Started Feb 25 01:31:38 PM PST 24
Finished Feb 25 01:31:39 PM PST 24
Peak memory 215972 kb
Host smart-2b51e711-4bb7-4be8-8e2f-94fd5cc3edeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150716860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1150716860
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1667570848
Short name T80
Test name
Test status
Simulation time 98040895 ps
CPU time 1.13 seconds
Started Feb 25 01:30:17 PM PST 24
Finished Feb 25 01:30:19 PM PST 24
Peak memory 215888 kb
Host smart-8670a0f7-227d-47fd-bfa6-524bf8f9d551
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667570848 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1667570848
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/97.edn_genbits.705551069
Short name T265
Test name
Test status
Simulation time 82223641 ps
CPU time 1.26 seconds
Started Feb 25 01:30:39 PM PST 24
Finished Feb 25 01:30:40 PM PST 24
Peak memory 217424 kb
Host smart-3cea74d4-f71c-41f0-b548-b5c2776e3a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705551069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.705551069
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_disable.3221792871
Short name T97
Test name
Test status
Simulation time 33014549 ps
CPU time 0.86 seconds
Started Feb 25 01:28:34 PM PST 24
Finished Feb 25 01:28:35 PM PST 24
Peak memory 214760 kb
Host smart-c815e5bf-8863-48d9-afb3-b2691b597acd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221792871 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3221792871
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable.461867314
Short name T121
Test name
Test status
Simulation time 30700882 ps
CPU time 0.85 seconds
Started Feb 25 01:28:51 PM PST 24
Finished Feb 25 01:28:52 PM PST 24
Peak memory 215028 kb
Host smart-af26ebe7-9a1d-46fc-b230-8a2a63194221
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461867314 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.461867314
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable.3562617978
Short name T100
Test name
Test status
Simulation time 62613982 ps
CPU time 0.83 seconds
Started Feb 25 01:29:07 PM PST 24
Finished Feb 25 01:29:08 PM PST 24
Peak memory 215088 kb
Host smart-5b4698c4-0d02-4ac2-acb0-335ff037a8a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562617978 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3562617978
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3658753309
Short name T76
Test name
Test status
Simulation time 34180813 ps
CPU time 1.13 seconds
Started Feb 25 01:29:18 PM PST 24
Finished Feb 25 01:29:19 PM PST 24
Peak memory 215684 kb
Host smart-48ef505a-5141-442c-a25e-d5af7f33f70d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658753309 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3658753309
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_disable.715171531
Short name T114
Test name
Test status
Simulation time 31349022 ps
CPU time 0.79 seconds
Started Feb 25 01:29:24 PM PST 24
Finished Feb 25 01:29:25 PM PST 24
Peak memory 215072 kb
Host smart-4788c61d-14be-4d24-98dd-acd6e0abf104
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715171531 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.715171531
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable.3741859549
Short name T168
Test name
Test status
Simulation time 132634959 ps
CPU time 0.9 seconds
Started Feb 25 01:29:37 PM PST 24
Finished Feb 25 01:29:38 PM PST 24
Peak memory 214096 kb
Host smart-31061a86-3d9a-4b54-b609-28717e9ca678
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741859549 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.3741859549
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable.151890983
Short name T163
Test name
Test status
Simulation time 27599219 ps
CPU time 0.81 seconds
Started Feb 25 01:28:46 PM PST 24
Finished Feb 25 01:28:47 PM PST 24
Peak memory 215056 kb
Host smart-2dc1b593-8e92-4cc7-8a3c-85937f678843
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151890983 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.151890983
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable.1339046594
Short name T156
Test name
Test status
Simulation time 42660979 ps
CPU time 0.86 seconds
Started Feb 25 01:30:04 PM PST 24
Finished Feb 25 01:30:05 PM PST 24
Peak memory 215232 kb
Host smart-5ad8ba2a-5d03-4e33-81ee-2f8d16de489f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339046594 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1339046594
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/14.edn_alert_test.2377270556
Short name T314
Test name
Test status
Simulation time 53142973 ps
CPU time 1.01 seconds
Started Feb 25 01:29:21 PM PST 24
Finished Feb 25 01:29:22 PM PST 24
Peak memory 206276 kb
Host smart-213e2820-513c-45c9-8d99-080f014769d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377270556 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.2377270556
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/113.edn_genbits.365267547
Short name T17
Test name
Test status
Simulation time 56046934 ps
CPU time 1.17 seconds
Started Feb 25 01:30:55 PM PST 24
Finished Feb 25 01:30:56 PM PST 24
Peak memory 216104 kb
Host smart-fa9a7eaa-a9b5-4f3f-bd51-47d188a1f7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365267547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.365267547
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.164731885
Short name T31
Test name
Test status
Simulation time 79146423 ps
CPU time 2.91 seconds
Started Feb 25 01:31:10 PM PST 24
Finished Feb 25 01:31:13 PM PST 24
Peak memory 218852 kb
Host smart-8bc96728-88dc-408c-bde9-e813a0c144e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164731885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.164731885
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_regwen.3355811653
Short name T129
Test name
Test status
Simulation time 27171810 ps
CPU time 0.95 seconds
Started Feb 25 01:28:50 PM PST 24
Finished Feb 25 01:28:51 PM PST 24
Peak memory 206516 kb
Host smart-73b0e6e1-70de-4602-a82c-7d824ec8c8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355811653 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.3355811653
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/49.edn_genbits.496542311
Short name T272
Test name
Test status
Simulation time 61359498 ps
CPU time 2.02 seconds
Started Feb 25 01:30:21 PM PST 24
Finished Feb 25 01:30:23 PM PST 24
Peak memory 217588 kb
Host smart-ac0182c2-d31a-4b87-a6d2-6e5ff9089ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496542311 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.496542311
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3585199278
Short name T107
Test name
Test status
Simulation time 32095644 ps
CPU time 1.28 seconds
Started Feb 25 01:29:24 PM PST 24
Finished Feb 25 01:29:26 PM PST 24
Peak memory 215128 kb
Host smart-0003789c-8652-4361-ad40-c149751a2568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585199278 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3585199278
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/3.edn_regwen.931129424
Short name T701
Test name
Test status
Simulation time 26822425 ps
CPU time 0.92 seconds
Started Feb 25 01:28:56 PM PST 24
Finished Feb 25 01:28:58 PM PST 24
Peak memory 206472 kb
Host smart-d5934133-93c0-405b-adc9-7a6aac01abb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931129424 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.931129424
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_regwen.1678539012
Short name T127
Test name
Test status
Simulation time 30145498 ps
CPU time 0.99 seconds
Started Feb 25 01:29:09 PM PST 24
Finished Feb 25 01:29:10 PM PST 24
Peak memory 206528 kb
Host smart-56b36225-31d3-4261-b039-033f95ae69f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678539012 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1678539012
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/139.edn_genbits.3917021507
Short name T24
Test name
Test status
Simulation time 39392997 ps
CPU time 1.44 seconds
Started Feb 25 01:31:01 PM PST 24
Finished Feb 25 01:31:02 PM PST 24
Peak memory 217256 kb
Host smart-3fa439f6-6b0b-4c73-af9b-3612e8614786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917021507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.3917021507
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.368427278
Short name T138
Test name
Test status
Simulation time 21870823 ps
CPU time 1.1 seconds
Started Feb 25 01:29:09 PM PST 24
Finished Feb 25 01:29:10 PM PST 24
Peak memory 215288 kb
Host smart-12909f5f-cff3-4f12-80cb-203cc9498cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368427278 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.368427278
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/65.edn_genbits.1530268425
Short name T257
Test name
Test status
Simulation time 251396015 ps
CPU time 1.31 seconds
Started Feb 25 01:30:41 PM PST 24
Finished Feb 25 01:30:42 PM PST 24
Peak memory 216128 kb
Host smart-1b5c1373-b59d-4a13-b79f-8308cc2ef92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530268425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1530268425
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2711732188
Short name T221
Test name
Test status
Simulation time 13949337 ps
CPU time 1.01 seconds
Started Feb 25 12:28:52 PM PST 24
Finished Feb 25 12:28:53 PM PST 24
Peak memory 204996 kb
Host smart-027ca046-a6dc-43b7-92de-d2c5bf5b3a11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711732188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2711732188
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2107084476
Short name T252
Test name
Test status
Simulation time 71750406 ps
CPU time 1.44 seconds
Started Feb 25 12:28:46 PM PST 24
Finished Feb 25 12:28:48 PM PST 24
Peak memory 205700 kb
Host smart-76c64bb3-b631-45c3-8120-cdff461e34f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107084476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2107084476
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.254770732
Short name T542
Test name
Test status
Simulation time 280628082255 ps
CPU time 628.24 seconds
Started Feb 25 01:28:33 PM PST 24
Finished Feb 25 01:39:02 PM PST 24
Peak memory 226948 kb
Host smart-61898711-1ef8-4c86-a59c-e4c125c9202e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254770732 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.254770732
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.2014422026
Short name T57
Test name
Test status
Simulation time 26809259 ps
CPU time 1.23 seconds
Started Feb 25 01:28:44 PM PST 24
Finished Feb 25 01:28:45 PM PST 24
Peak memory 214748 kb
Host smart-f793d3f0-8132-41d1-8a39-c5cc87b5b482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014422026 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2014422026
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/10.edn_genbits.3444503169
Short name T213
Test name
Test status
Simulation time 36919828 ps
CPU time 1.63 seconds
Started Feb 25 01:29:05 PM PST 24
Finished Feb 25 01:29:06 PM PST 24
Peak memory 217500 kb
Host smart-629b1f67-044d-42a1-b8d9-fc3c7e6eb6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444503169 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.3444503169
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.1637278591
Short name T279
Test name
Test status
Simulation time 54971576 ps
CPU time 2.07 seconds
Started Feb 25 01:30:50 PM PST 24
Finished Feb 25 01:30:52 PM PST 24
Peak memory 217244 kb
Host smart-43bc21a2-e5ce-46cf-9b5d-129e108f12b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637278591 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1637278591
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.2435618039
Short name T283
Test name
Test status
Simulation time 279253128 ps
CPU time 2.77 seconds
Started Feb 25 01:30:51 PM PST 24
Finished Feb 25 01:30:54 PM PST 24
Peak memory 218876 kb
Host smart-7e3b29cb-7fca-4a8a-ac82-4a01e7045529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435618039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2435618039
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_stress_all.1470303611
Short name T276
Test name
Test status
Simulation time 278811512 ps
CPU time 5.31 seconds
Started Feb 25 01:29:16 PM PST 24
Finished Feb 25 01:29:21 PM PST 24
Peak memory 214772 kb
Host smart-45a8712b-0a72-4406-9f3f-c9d1fa6af230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470303611 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1470303611
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_genbits.742140733
Short name T271
Test name
Test status
Simulation time 39365170 ps
CPU time 1.47 seconds
Started Feb 25 01:29:24 PM PST 24
Finished Feb 25 01:29:26 PM PST 24
Peak memory 215968 kb
Host smart-67b48dcb-b630-43e9-9805-6221d1945fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742140733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.742140733
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.1042590042
Short name T210
Test name
Test status
Simulation time 44597399 ps
CPU time 1.07 seconds
Started Feb 25 01:31:03 PM PST 24
Finished Feb 25 01:31:04 PM PST 24
Peak memory 218260 kb
Host smart-94050183-cb27-4a6e-9e05-dde7b97577e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042590042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1042590042
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_genbits.488967627
Short name T183
Test name
Test status
Simulation time 74949928 ps
CPU time 1.29 seconds
Started Feb 25 01:29:56 PM PST 24
Finished Feb 25 01:29:58 PM PST 24
Peak memory 217308 kb
Host smart-5c2c016f-b831-4c0f-b403-02d4f94bd7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488967627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.488967627
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.605140147
Short name T189
Test name
Test status
Simulation time 138500726 ps
CPU time 1.21 seconds
Started Feb 25 01:29:27 PM PST 24
Finished Feb 25 01:29:28 PM PST 24
Peak memory 215104 kb
Host smart-2ff2aa93-fea3-4749-a7a2-a3526f2217e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605140147 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.605140147
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/124.edn_genbits.294375547
Short name T343
Test name
Test status
Simulation time 54965366 ps
CPU time 1.77 seconds
Started Feb 25 01:30:50 PM PST 24
Finished Feb 25 01:30:52 PM PST 24
Peak memory 217332 kb
Host smart-b831b868-2c4b-473a-9e94-07c1570ca030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294375547 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.294375547
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.2241033865
Short name T658
Test name
Test status
Simulation time 58960126 ps
CPU time 1.83 seconds
Started Feb 25 01:31:07 PM PST 24
Finished Feb 25 01:31:08 PM PST 24
Peak memory 214648 kb
Host smart-e7262122-5cd3-48f4-a6cc-05ce5d2b8797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241033865 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2241033865
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3372615998
Short name T6
Test name
Test status
Simulation time 100481968 ps
CPU time 1.23 seconds
Started Feb 25 01:31:32 PM PST 24
Finished Feb 25 01:31:33 PM PST 24
Peak memory 216296 kb
Host smart-04f2ef4a-fafc-460d-bd2e-3fee1cb4a1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372615998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3372615998
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3360469555
Short name T229
Test name
Test status
Simulation time 26029334 ps
CPU time 1.24 seconds
Started Feb 25 12:27:44 PM PST 24
Finished Feb 25 12:27:46 PM PST 24
Peak memory 204696 kb
Host smart-41cdc1ee-7295-417a-b067-83f7190040a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360469555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3360469555
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.2601434220
Short name T867
Test name
Test status
Simulation time 134365842 ps
CPU time 3.87 seconds
Started Feb 25 12:27:44 PM PST 24
Finished Feb 25 12:27:49 PM PST 24
Peak memory 205000 kb
Host smart-aed27e92-d344-4428-bcb7-7662294d3b79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601434220 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.2601434220
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.3859378349
Short name T955
Test name
Test status
Simulation time 15705087 ps
CPU time 0.96 seconds
Started Feb 25 12:27:52 PM PST 24
Finished Feb 25 12:27:54 PM PST 24
Peak memory 205000 kb
Host smart-7276d177-9c7b-44f3-ae6d-62f00b48071f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859378349 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.3859378349
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3169023677
Short name T960
Test name
Test status
Simulation time 26914652 ps
CPU time 0.97 seconds
Started Feb 25 12:27:51 PM PST 24
Finished Feb 25 12:27:52 PM PST 24
Peak memory 205640 kb
Host smart-0f446975-21a9-46e7-944c-11b3a45a1829
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169023677 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3169023677
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3037818748
Short name T854
Test name
Test status
Simulation time 24303727 ps
CPU time 0.89 seconds
Started Feb 25 12:27:46 PM PST 24
Finished Feb 25 12:27:47 PM PST 24
Peak memory 205416 kb
Host smart-45c07e12-be0b-421d-9896-68452bfd10d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037818748 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3037818748
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.99578584
Short name T916
Test name
Test status
Simulation time 46175995 ps
CPU time 0.94 seconds
Started Feb 25 12:27:48 PM PST 24
Finished Feb 25 12:27:50 PM PST 24
Peak memory 205064 kb
Host smart-583a6df0-a709-46cc-b6a7-f5e31acf59a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99578584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outs
tanding.99578584
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.726100989
Short name T848
Test name
Test status
Simulation time 40412714 ps
CPU time 2.84 seconds
Started Feb 25 12:27:46 PM PST 24
Finished Feb 25 12:27:50 PM PST 24
Peak memory 213264 kb
Host smart-fd4ba34a-b13b-44db-885e-05784b74e6f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726100989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.726100989
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.2707156991
Short name T931
Test name
Test status
Simulation time 620915039 ps
CPU time 2.54 seconds
Started Feb 25 12:27:44 PM PST 24
Finished Feb 25 12:27:47 PM PST 24
Peak memory 204484 kb
Host smart-6801f588-8621-4270-93e8-f5d648ac5a90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707156991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.2707156991
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2201819385
Short name T231
Test name
Test status
Simulation time 49842594 ps
CPU time 1.28 seconds
Started Feb 25 12:27:50 PM PST 24
Finished Feb 25 12:27:52 PM PST 24
Peak memory 205012 kb
Host smart-31dc9586-4e50-4771-9e8a-457d20ab26e7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201819385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2201819385
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2997000836
Short name T887
Test name
Test status
Simulation time 514498397 ps
CPU time 3.78 seconds
Started Feb 25 12:27:49 PM PST 24
Finished Feb 25 12:27:53 PM PST 24
Peak memory 205044 kb
Host smart-17e4f6e3-278b-4190-8161-7ac8fd030038
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997000836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2997000836
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1317578301
Short name T950
Test name
Test status
Simulation time 28079745 ps
CPU time 1.02 seconds
Started Feb 25 12:27:53 PM PST 24
Finished Feb 25 12:27:55 PM PST 24
Peak memory 205000 kb
Host smart-9911884b-a295-434b-8c1c-5809be86dde6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317578301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1317578301
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2174248567
Short name T890
Test name
Test status
Simulation time 16474234 ps
CPU time 1.04 seconds
Started Feb 25 12:27:52 PM PST 24
Finished Feb 25 12:27:54 PM PST 24
Peak memory 205748 kb
Host smart-29316dd2-e1e9-4240-a231-3d9109bc610e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174248567 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2174248567
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.992010208
Short name T862
Test name
Test status
Simulation time 14515780 ps
CPU time 0.91 seconds
Started Feb 25 12:27:51 PM PST 24
Finished Feb 25 12:27:52 PM PST 24
Peak memory 205540 kb
Host smart-d37b02d7-c947-477b-98e6-8320afb7f6d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992010208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.992010208
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.398814494
Short name T836
Test name
Test status
Simulation time 31421255 ps
CPU time 0.81 seconds
Started Feb 25 12:27:46 PM PST 24
Finished Feb 25 12:27:47 PM PST 24
Peak memory 205460 kb
Host smart-711bf786-af02-4e96-9fd4-b7d8c594d3cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398814494 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.398814494
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1149704701
Short name T920
Test name
Test status
Simulation time 236308853 ps
CPU time 1.54 seconds
Started Feb 25 12:27:49 PM PST 24
Finished Feb 25 12:27:51 PM PST 24
Peak memory 204848 kb
Host smart-3dcb0759-7770-49da-9075-3597e7c12ee5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149704701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1149704701
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3767069886
Short name T839
Test name
Test status
Simulation time 143116506 ps
CPU time 1.94 seconds
Started Feb 25 12:27:44 PM PST 24
Finished Feb 25 12:27:47 PM PST 24
Peak memory 212864 kb
Host smart-5c5fe30e-b432-4cc0-9249-85ea9a42c1ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767069886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3767069886
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.915525209
Short name T249
Test name
Test status
Simulation time 112205694 ps
CPU time 2.66 seconds
Started Feb 25 12:27:51 PM PST 24
Finished Feb 25 12:27:54 PM PST 24
Peak memory 205804 kb
Host smart-64aef6d4-03ad-4b60-8338-7d4f26a66916
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915525209 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.915525209
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.215766059
Short name T959
Test name
Test status
Simulation time 37650366 ps
CPU time 1.47 seconds
Started Feb 25 12:28:48 PM PST 24
Finished Feb 25 12:28:50 PM PST 24
Peak memory 213948 kb
Host smart-7ce10c3a-bcb5-4b41-be42-994b5e3557c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215766059 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.215766059
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.712481155
Short name T846
Test name
Test status
Simulation time 14414782 ps
CPU time 0.86 seconds
Started Feb 25 12:28:46 PM PST 24
Finished Feb 25 12:28:48 PM PST 24
Peak memory 204944 kb
Host smart-a23548ea-f4e2-4ff0-8cef-aa7d3da1b396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712481155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.712481155
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3227415858
Short name T958
Test name
Test status
Simulation time 70654753 ps
CPU time 1.08 seconds
Started Feb 25 12:28:45 PM PST 24
Finished Feb 25 12:28:46 PM PST 24
Peak memory 205748 kb
Host smart-a9c742a9-5bf6-4981-aaff-4a51163883d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227415858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3227415858
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.1306353048
Short name T866
Test name
Test status
Simulation time 35744237 ps
CPU time 1.58 seconds
Started Feb 25 12:28:49 PM PST 24
Finished Feb 25 12:28:51 PM PST 24
Peak memory 213944 kb
Host smart-995a9793-1a54-4d7b-8576-945145784bd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306353048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.1306353048
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3258511315
Short name T888
Test name
Test status
Simulation time 87387256 ps
CPU time 1.14 seconds
Started Feb 25 12:28:45 PM PST 24
Finished Feb 25 12:28:51 PM PST 24
Peak memory 213984 kb
Host smart-43859381-299e-431f-b5da-4fe6fc8c0a2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258511315 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3258511315
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3150846824
Short name T912
Test name
Test status
Simulation time 20843327 ps
CPU time 0.84 seconds
Started Feb 25 12:28:43 PM PST 24
Finished Feb 25 12:28:44 PM PST 24
Peak memory 204992 kb
Host smart-38c488fc-4513-4386-93bd-a88984958fd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150846824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3150846824
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.448895176
Short name T924
Test name
Test status
Simulation time 35555312 ps
CPU time 0.89 seconds
Started Feb 25 12:28:38 PM PST 24
Finished Feb 25 12:28:41 PM PST 24
Peak memory 204212 kb
Host smart-1d1d5f20-54e5-4d3c-884a-9991b353d149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448895176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.448895176
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2478844723
Short name T222
Test name
Test status
Simulation time 41186088 ps
CPU time 0.87 seconds
Started Feb 25 12:28:59 PM PST 24
Finished Feb 25 12:29:00 PM PST 24
Peak memory 205760 kb
Host smart-c49fe112-982c-40ea-ba67-d851478bc934
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478844723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2478844723
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1099809566
Short name T947
Test name
Test status
Simulation time 168393344 ps
CPU time 3.05 seconds
Started Feb 25 12:28:44 PM PST 24
Finished Feb 25 12:28:47 PM PST 24
Peak memory 214036 kb
Host smart-ae6a4e1a-37c4-49f5-948f-db473fffdd1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099809566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1099809566
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2547644532
Short name T254
Test name
Test status
Simulation time 99357190 ps
CPU time 2.17 seconds
Started Feb 25 12:28:47 PM PST 24
Finished Feb 25 12:28:49 PM PST 24
Peak memory 205744 kb
Host smart-6f74980d-94f9-420c-ae58-9176e8932ca4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547644532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2547644532
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3415551672
Short name T849
Test name
Test status
Simulation time 71116971 ps
CPU time 1.13 seconds
Started Feb 25 12:28:51 PM PST 24
Finished Feb 25 12:28:52 PM PST 24
Peak memory 214020 kb
Host smart-b17da6ba-bdcd-4dff-80ce-94b3ffb4ba96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415551672 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3415551672
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.2644010692
Short name T894
Test name
Test status
Simulation time 65526856 ps
CPU time 0.78 seconds
Started Feb 25 12:28:39 PM PST 24
Finished Feb 25 12:28:39 PM PST 24
Peak memory 205600 kb
Host smart-40d48970-c41b-41ef-a2b4-30ba0c2b4555
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644010692 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.2644010692
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2549080871
Short name T917
Test name
Test status
Simulation time 104117300 ps
CPU time 0.76 seconds
Started Feb 25 12:28:52 PM PST 24
Finished Feb 25 12:28:53 PM PST 24
Peak memory 205540 kb
Host smart-5c5f546d-7bac-472e-a315-601f61305a01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549080871 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2549080871
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1385522842
Short name T899
Test name
Test status
Simulation time 54300170 ps
CPU time 1.27 seconds
Started Feb 25 12:29:23 PM PST 24
Finished Feb 25 12:29:24 PM PST 24
Peak memory 205728 kb
Host smart-77978b07-f086-463d-a65c-655a49b25285
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385522842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1385522842
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.679280815
Short name T935
Test name
Test status
Simulation time 79940695 ps
CPU time 1.78 seconds
Started Feb 25 12:28:54 PM PST 24
Finished Feb 25 12:28:57 PM PST 24
Peak memory 213364 kb
Host smart-3c0469b1-1008-4552-b9df-2e1d3cc4a74c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679280815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.679280815
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3335654304
Short name T878
Test name
Test status
Simulation time 64482828 ps
CPU time 1.75 seconds
Started Feb 25 12:28:43 PM PST 24
Finished Feb 25 12:28:45 PM PST 24
Peak memory 205764 kb
Host smart-0482c87d-ad02-49bc-a72e-d4ae958a0fd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335654304 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3335654304
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.3695346859
Short name T861
Test name
Test status
Simulation time 154081371 ps
CPU time 1.46 seconds
Started Feb 25 12:28:54 PM PST 24
Finished Feb 25 12:28:56 PM PST 24
Peak memory 213948 kb
Host smart-8e84b2e3-51d6-41c2-9da0-aab299fd5158
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695346859 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.3695346859
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2701256703
Short name T951
Test name
Test status
Simulation time 14852656 ps
CPU time 0.91 seconds
Started Feb 25 12:28:54 PM PST 24
Finished Feb 25 12:28:55 PM PST 24
Peak memory 205676 kb
Host smart-f3a64ab2-4631-42e6-8c05-f170d270ff6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701256703 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2701256703
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.1821973415
Short name T875
Test name
Test status
Simulation time 16010521 ps
CPU time 0.88 seconds
Started Feb 25 12:28:31 PM PST 24
Finished Feb 25 12:28:32 PM PST 24
Peak memory 205608 kb
Host smart-91ff8b98-0f66-45a7-841c-73453ac63ba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821973415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.1821973415
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3008917310
Short name T927
Test name
Test status
Simulation time 43986093 ps
CPU time 1.01 seconds
Started Feb 25 12:28:46 PM PST 24
Finished Feb 25 12:28:47 PM PST 24
Peak memory 205780 kb
Host smart-26c20a8e-7f1e-48d7-9bcf-5df7846e010d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008917310 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3008917310
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3206410859
Short name T913
Test name
Test status
Simulation time 106492757 ps
CPU time 1.97 seconds
Started Feb 25 12:28:44 PM PST 24
Finished Feb 25 12:28:46 PM PST 24
Peak memory 213988 kb
Host smart-5ddce919-808d-43c0-a80f-51ea39339733
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206410859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3206410859
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.3159062980
Short name T250
Test name
Test status
Simulation time 75321263 ps
CPU time 1.51 seconds
Started Feb 25 12:29:01 PM PST 24
Finished Feb 25 12:29:02 PM PST 24
Peak memory 205692 kb
Host smart-3b23a809-9f96-4db3-b839-12b79349c845
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159062980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.3159062980
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.2758639760
Short name T962
Test name
Test status
Simulation time 89194882 ps
CPU time 1.54 seconds
Started Feb 25 12:29:02 PM PST 24
Finished Feb 25 12:29:04 PM PST 24
Peak memory 214020 kb
Host smart-30d9dc9d-59ba-4f61-8142-e7fb3bd8015f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758639760 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.2758639760
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2289579727
Short name T230
Test name
Test status
Simulation time 13208432 ps
CPU time 0.91 seconds
Started Feb 25 12:28:55 PM PST 24
Finished Feb 25 12:28:56 PM PST 24
Peak memory 205676 kb
Host smart-7cf05132-3d5d-429b-8cca-be40c3b7dd83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289579727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2289579727
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3791832958
Short name T874
Test name
Test status
Simulation time 14779321 ps
CPU time 0.89 seconds
Started Feb 25 12:28:56 PM PST 24
Finished Feb 25 12:28:57 PM PST 24
Peak memory 205608 kb
Host smart-c17c327f-6749-419e-8ed1-130785a8a952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791832958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3791832958
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3685821376
Short name T889
Test name
Test status
Simulation time 93390427 ps
CPU time 1.29 seconds
Started Feb 25 12:29:10 PM PST 24
Finished Feb 25 12:29:12 PM PST 24
Peak memory 205688 kb
Host smart-6fd44648-52e2-41f0-86c0-d0fa81c499e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685821376 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3685821376
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3659846947
Short name T923
Test name
Test status
Simulation time 263416213 ps
CPU time 2.48 seconds
Started Feb 25 12:28:58 PM PST 24
Finished Feb 25 12:29:01 PM PST 24
Peak memory 222108 kb
Host smart-f6eca847-d4fe-4b5d-99a4-59714fea86db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659846947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3659846947
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1682828394
Short name T868
Test name
Test status
Simulation time 62475133 ps
CPU time 1.22 seconds
Started Feb 25 12:28:52 PM PST 24
Finished Feb 25 12:28:53 PM PST 24
Peak memory 214008 kb
Host smart-97248df0-c6d5-4900-86c7-2151edc7ff85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682828394 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1682828394
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.92468966
Short name T876
Test name
Test status
Simulation time 23281783 ps
CPU time 0.84 seconds
Started Feb 25 12:28:45 PM PST 24
Finished Feb 25 12:28:46 PM PST 24
Peak memory 205648 kb
Host smart-490d9cd1-ff7e-46d3-a1c5-9f1fc0e6d803
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92468966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.92468966
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2331603625
Short name T864
Test name
Test status
Simulation time 16091596 ps
CPU time 0.94 seconds
Started Feb 25 12:29:01 PM PST 24
Finished Feb 25 12:29:02 PM PST 24
Peak memory 205612 kb
Host smart-814ba814-25c7-4bf2-a051-9b653f2880cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331603625 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2331603625
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2645491061
Short name T900
Test name
Test status
Simulation time 40469072 ps
CPU time 1.36 seconds
Started Feb 25 12:28:51 PM PST 24
Finished Feb 25 12:28:53 PM PST 24
Peak memory 205684 kb
Host smart-b9b118fd-6b62-4998-a415-481c744d9384
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645491061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2645491061
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.4257263803
Short name T949
Test name
Test status
Simulation time 34185558 ps
CPU time 2.34 seconds
Started Feb 25 12:28:57 PM PST 24
Finished Feb 25 12:29:00 PM PST 24
Peak memory 217144 kb
Host smart-7a85a311-af30-47dc-b973-a1fa7a94be15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257263803 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.4257263803
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.426814073
Short name T251
Test name
Test status
Simulation time 103851178 ps
CPU time 2.38 seconds
Started Feb 25 12:28:58 PM PST 24
Finished Feb 25 12:29:01 PM PST 24
Peak memory 205680 kb
Host smart-c6916ac3-1613-4093-94df-5b61e9ffc2ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426814073 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.426814073
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2805917548
Short name T847
Test name
Test status
Simulation time 24738345 ps
CPU time 1.15 seconds
Started Feb 25 12:28:59 PM PST 24
Finished Feb 25 12:29:00 PM PST 24
Peak memory 213908 kb
Host smart-dfc7a570-0a8f-49c2-aa3b-8bf58017743a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805917548 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2805917548
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1412765985
Short name T872
Test name
Test status
Simulation time 20214263 ps
CPU time 0.8 seconds
Started Feb 25 12:29:20 PM PST 24
Finished Feb 25 12:29:21 PM PST 24
Peak memory 205604 kb
Host smart-e33cc61f-1d8d-4208-9c1b-0ff38aaf3c82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412765985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1412765985
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.2906914207
Short name T833
Test name
Test status
Simulation time 50085299 ps
CPU time 0.83 seconds
Started Feb 25 12:28:58 PM PST 24
Finished Feb 25 12:28:59 PM PST 24
Peak memory 205608 kb
Host smart-2e6e59ff-5626-4a59-8352-cb4fc986ad6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906914207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.2906914207
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.1632942172
Short name T954
Test name
Test status
Simulation time 30177056 ps
CPU time 1.37 seconds
Started Feb 25 12:29:04 PM PST 24
Finished Feb 25 12:29:05 PM PST 24
Peak memory 205740 kb
Host smart-a9eaa941-a071-4f81-a5d6-6df56a1dfc33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632942172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.1632942172
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3628246907
Short name T870
Test name
Test status
Simulation time 30871027 ps
CPU time 2.01 seconds
Started Feb 25 12:28:59 PM PST 24
Finished Feb 25 12:29:01 PM PST 24
Peak memory 214124 kb
Host smart-6827f18b-9591-4968-b29a-121badf9a7b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628246907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3628246907
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4111013515
Short name T256
Test name
Test status
Simulation time 188942064 ps
CPU time 1.56 seconds
Started Feb 25 12:29:12 PM PST 24
Finished Feb 25 12:29:14 PM PST 24
Peak memory 205792 kb
Host smart-6409c97a-c4ac-426f-97ba-994817e86011
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111013515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.4111013515
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3719090157
Short name T855
Test name
Test status
Simulation time 23969800 ps
CPU time 1.56 seconds
Started Feb 25 12:28:52 PM PST 24
Finished Feb 25 12:28:54 PM PST 24
Peak memory 214032 kb
Host smart-6eb746ba-a1ba-4916-b271-420344d965de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719090157 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3719090157
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2314461088
Short name T930
Test name
Test status
Simulation time 17056805 ps
CPU time 0.95 seconds
Started Feb 25 12:28:58 PM PST 24
Finished Feb 25 12:28:59 PM PST 24
Peak memory 205656 kb
Host smart-04d61c67-5be2-406e-ad03-39c04085b7a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314461088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2314461088
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.887077775
Short name T941
Test name
Test status
Simulation time 11035289 ps
CPU time 0.82 seconds
Started Feb 25 12:28:53 PM PST 24
Finished Feb 25 12:28:54 PM PST 24
Peak memory 205624 kb
Host smart-e872ccbf-be70-43df-80de-bfdb51031e2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887077775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.887077775
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.2891050273
Short name T915
Test name
Test status
Simulation time 56100432 ps
CPU time 1.09 seconds
Started Feb 25 12:28:57 PM PST 24
Finished Feb 25 12:28:59 PM PST 24
Peak memory 205740 kb
Host smart-fd1aa4ef-86d4-4d1a-b3d8-b792310926a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891050273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.2891050273
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2192009295
Short name T919
Test name
Test status
Simulation time 368702646 ps
CPU time 3.4 seconds
Started Feb 25 12:28:59 PM PST 24
Finished Feb 25 12:29:03 PM PST 24
Peak memory 214196 kb
Host smart-c7f26c40-c31c-4502-8d6a-ca45d1214364
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192009295 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2192009295
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.4208220475
Short name T897
Test name
Test status
Simulation time 91566186 ps
CPU time 1.58 seconds
Started Feb 25 12:28:46 PM PST 24
Finished Feb 25 12:28:47 PM PST 24
Peak memory 205696 kb
Host smart-4f88ce76-3280-41ee-868e-4b97c6f0089d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208220475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.4208220475
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3321707105
Short name T892
Test name
Test status
Simulation time 22800457 ps
CPU time 1.51 seconds
Started Feb 25 12:28:54 PM PST 24
Finished Feb 25 12:28:56 PM PST 24
Peak memory 213988 kb
Host smart-40e53b50-11c4-45fd-bd74-423c1e9f6ad0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321707105 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3321707105
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.152439969
Short name T929
Test name
Test status
Simulation time 15768150 ps
CPU time 0.93 seconds
Started Feb 25 12:28:50 PM PST 24
Finished Feb 25 12:28:51 PM PST 24
Peak memory 205656 kb
Host smart-0b81c3f5-896f-4456-b605-ffc823ffc018
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152439969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.152439969
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2931815440
Short name T906
Test name
Test status
Simulation time 25872556 ps
CPU time 0.92 seconds
Started Feb 25 12:29:03 PM PST 24
Finished Feb 25 12:29:04 PM PST 24
Peak memory 205576 kb
Host smart-c526145e-bf96-4874-b486-4b5a191961fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931815440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2931815440
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.179952005
Short name T223
Test name
Test status
Simulation time 79927962 ps
CPU time 1.19 seconds
Started Feb 25 12:28:52 PM PST 24
Finished Feb 25 12:28:54 PM PST 24
Peak memory 205676 kb
Host smart-095cb521-9a63-482c-8fb7-70b49a25f07f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179952005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.179952005
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.1038272549
Short name T948
Test name
Test status
Simulation time 192129970 ps
CPU time 2.19 seconds
Started Feb 25 12:29:04 PM PST 24
Finished Feb 25 12:29:06 PM PST 24
Peak memory 214016 kb
Host smart-59627e68-8900-40a4-869b-5394d1f580c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038272549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.1038272549
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4197568883
Short name T239
Test name
Test status
Simulation time 140074203 ps
CPU time 1.47 seconds
Started Feb 25 12:29:12 PM PST 24
Finished Feb 25 12:29:14 PM PST 24
Peak memory 205712 kb
Host smart-3295e385-c996-4b77-8b94-a13992aa15fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197568883 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.4197568883
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1589604039
Short name T879
Test name
Test status
Simulation time 45789270 ps
CPU time 1.28 seconds
Started Feb 25 12:28:48 PM PST 24
Finished Feb 25 12:28:49 PM PST 24
Peak memory 213952 kb
Host smart-f152d08b-9ca8-4bcb-9055-e8071ac61f81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589604039 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1589604039
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3633803383
Short name T228
Test name
Test status
Simulation time 23802011 ps
CPU time 0.95 seconds
Started Feb 25 12:29:07 PM PST 24
Finished Feb 25 12:29:08 PM PST 24
Peak memory 205636 kb
Host smart-1db60d06-02f9-414c-b4e4-ebcb90dac406
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633803383 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3633803383
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.433589969
Short name T838
Test name
Test status
Simulation time 22904187 ps
CPU time 0.84 seconds
Started Feb 25 12:29:01 PM PST 24
Finished Feb 25 12:29:02 PM PST 24
Peak memory 205700 kb
Host smart-0255b52d-3f3d-46e0-9684-3999dba6139c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433589969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.433589969
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.304484172
Short name T940
Test name
Test status
Simulation time 211510280 ps
CPU time 1.21 seconds
Started Feb 25 12:29:04 PM PST 24
Finished Feb 25 12:29:05 PM PST 24
Peak memory 205680 kb
Host smart-a4c1dee5-0613-433c-8a91-cfe368a34338
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304484172 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.304484172
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.142679215
Short name T877
Test name
Test status
Simulation time 266492576 ps
CPU time 2.63 seconds
Started Feb 25 12:28:55 PM PST 24
Finished Feb 25 12:28:58 PM PST 24
Peak memory 214004 kb
Host smart-967f48f4-2c5b-4c1e-ae4c-ef1976830766
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142679215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.142679215
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.1858456888
Short name T253
Test name
Test status
Simulation time 113848096 ps
CPU time 1.74 seconds
Started Feb 25 12:28:58 PM PST 24
Finished Feb 25 12:29:00 PM PST 24
Peak memory 205752 kb
Host smart-866e7081-582f-44ab-ba39-3485fdc96b76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858456888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.1858456888
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2741104931
Short name T936
Test name
Test status
Simulation time 28200314 ps
CPU time 1.35 seconds
Started Feb 25 12:27:47 PM PST 24
Finished Feb 25 12:27:49 PM PST 24
Peak memory 205000 kb
Host smart-d8fed4fd-bb45-4599-b72d-dd444edc34d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741104931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2741104931
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1758351926
Short name T869
Test name
Test status
Simulation time 59304459 ps
CPU time 3.42 seconds
Started Feb 25 12:27:48 PM PST 24
Finished Feb 25 12:27:51 PM PST 24
Peak memory 205072 kb
Host smart-60d69a4b-fcf7-4093-8206-5d6a04715c8d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758351926 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1758351926
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2039874084
Short name T903
Test name
Test status
Simulation time 25176556 ps
CPU time 0.93 seconds
Started Feb 25 12:27:45 PM PST 24
Finished Feb 25 12:27:46 PM PST 24
Peak memory 205676 kb
Host smart-bbb69e50-94c6-437d-bb5d-5ca5de43bb6e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039874084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2039874084
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.72172668
Short name T850
Test name
Test status
Simulation time 58113136 ps
CPU time 1.01 seconds
Started Feb 25 12:27:45 PM PST 24
Finished Feb 25 12:27:46 PM PST 24
Peak memory 213940 kb
Host smart-6fc33282-ab66-4dec-81b6-1f176df36472
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72172668 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.72172668
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2429550660
Short name T910
Test name
Test status
Simulation time 48941473 ps
CPU time 0.91 seconds
Started Feb 25 12:27:50 PM PST 24
Finished Feb 25 12:27:52 PM PST 24
Peak memory 204988 kb
Host smart-384b280e-3ec4-4a77-9b2d-8379f0cf6e4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429550660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2429550660
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.484750596
Short name T856
Test name
Test status
Simulation time 87509842 ps
CPU time 0.97 seconds
Started Feb 25 12:27:44 PM PST 24
Finished Feb 25 12:27:46 PM PST 24
Peak memory 204860 kb
Host smart-6c42d467-0f5b-4cae-b60a-40e64eb14f55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484750596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.484750596
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1102389644
Short name T235
Test name
Test status
Simulation time 61847748 ps
CPU time 1.03 seconds
Started Feb 25 12:27:48 PM PST 24
Finished Feb 25 12:27:50 PM PST 24
Peak memory 204796 kb
Host smart-19a4970a-d886-4297-a5e3-7568ce7e0262
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102389644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1102389644
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1179190156
Short name T832
Test name
Test status
Simulation time 110382771 ps
CPU time 1.97 seconds
Started Feb 25 12:27:44 PM PST 24
Finished Feb 25 12:27:47 PM PST 24
Peak memory 213084 kb
Host smart-7185b182-758e-4cd8-9499-3d7a4c230130
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179190156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1179190156
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2112681696
Short name T926
Test name
Test status
Simulation time 103856398 ps
CPU time 1.87 seconds
Started Feb 25 12:27:48 PM PST 24
Finished Feb 25 12:27:50 PM PST 24
Peak memory 204784 kb
Host smart-9dc271c0-9d50-4950-a3ed-5c27131e4982
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112681696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2112681696
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.804564420
Short name T965
Test name
Test status
Simulation time 16299584 ps
CPU time 0.94 seconds
Started Feb 25 12:29:02 PM PST 24
Finished Feb 25 12:29:03 PM PST 24
Peak memory 205624 kb
Host smart-2ea99c77-fb1a-4a9c-b1df-696fec774bc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804564420 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.804564420
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1938889968
Short name T909
Test name
Test status
Simulation time 13134469 ps
CPU time 0.86 seconds
Started Feb 25 12:29:02 PM PST 24
Finished Feb 25 12:29:03 PM PST 24
Peak memory 205612 kb
Host smart-9746822f-0b11-40cd-aad7-a61ed17c4446
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938889968 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1938889968
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.3659763816
Short name T857
Test name
Test status
Simulation time 39758686 ps
CPU time 0.87 seconds
Started Feb 25 12:28:51 PM PST 24
Finished Feb 25 12:28:52 PM PST 24
Peak memory 205844 kb
Host smart-424082a4-3b34-4c0c-b40b-d270e3e7e672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659763816 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.3659763816
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.546350305
Short name T852
Test name
Test status
Simulation time 11007030 ps
CPU time 0.83 seconds
Started Feb 25 12:28:58 PM PST 24
Finished Feb 25 12:28:59 PM PST 24
Peak memory 205608 kb
Host smart-297f5e6a-e343-488f-90b9-e45d80e5436b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546350305 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.546350305
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.373895946
Short name T967
Test name
Test status
Simulation time 24041707 ps
CPU time 0.84 seconds
Started Feb 25 12:28:57 PM PST 24
Finished Feb 25 12:28:58 PM PST 24
Peak memory 205692 kb
Host smart-f41e8b18-05be-4f83-812b-f5f926c1fb2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373895946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.373895946
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1149915502
Short name T896
Test name
Test status
Simulation time 26625800 ps
CPU time 0.86 seconds
Started Feb 25 12:28:57 PM PST 24
Finished Feb 25 12:28:58 PM PST 24
Peak memory 205612 kb
Host smart-90716f2a-c5ed-40a6-bb41-f37abd463776
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149915502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1149915502
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.876019812
Short name T944
Test name
Test status
Simulation time 49260864 ps
CPU time 0.91 seconds
Started Feb 25 12:28:47 PM PST 24
Finished Feb 25 12:28:48 PM PST 24
Peak memory 204944 kb
Host smart-09d56e10-0933-4c19-81b6-1d2d0292712a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876019812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.876019812
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3688543439
Short name T860
Test name
Test status
Simulation time 16533706 ps
CPU time 0.9 seconds
Started Feb 25 12:29:02 PM PST 24
Finished Feb 25 12:29:03 PM PST 24
Peak memory 205592 kb
Host smart-2ab3ad49-0df3-42b6-be88-cedd02c92c16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688543439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3688543439
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.3863978811
Short name T902
Test name
Test status
Simulation time 18742024 ps
CPU time 0.9 seconds
Started Feb 25 12:29:02 PM PST 24
Finished Feb 25 12:29:04 PM PST 24
Peak memory 204864 kb
Host smart-1e805072-81dd-45d8-970d-b26ffe7323d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863978811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.3863978811
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.2909148515
Short name T932
Test name
Test status
Simulation time 135961848 ps
CPU time 0.9 seconds
Started Feb 25 12:29:05 PM PST 24
Finished Feb 25 12:29:06 PM PST 24
Peak memory 205516 kb
Host smart-f91f1b1c-9300-479c-8682-7e041405af5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909148515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.2909148515
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2649982003
Short name T880
Test name
Test status
Simulation time 48712187 ps
CPU time 1.14 seconds
Started Feb 25 12:27:52 PM PST 24
Finished Feb 25 12:27:53 PM PST 24
Peak memory 205748 kb
Host smart-3c1f4e41-54a1-41cf-8b56-cf362ee6f42b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649982003 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2649982003
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1171274064
Short name T841
Test name
Test status
Simulation time 224681556 ps
CPU time 6.31 seconds
Started Feb 25 12:27:44 PM PST 24
Finished Feb 25 12:27:50 PM PST 24
Peak memory 205684 kb
Host smart-09e04743-c284-4790-bdcf-4e7bba85becd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171274064 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1171274064
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2426545306
Short name T908
Test name
Test status
Simulation time 15936950 ps
CPU time 0.95 seconds
Started Feb 25 12:27:51 PM PST 24
Finished Feb 25 12:27:52 PM PST 24
Peak memory 204268 kb
Host smart-90b6f614-ec5e-485e-bee7-5f0052df43a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426545306 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2426545306
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.4016537528
Short name T834
Test name
Test status
Simulation time 23288467 ps
CPU time 1.35 seconds
Started Feb 25 12:27:48 PM PST 24
Finished Feb 25 12:27:50 PM PST 24
Peak memory 213332 kb
Host smart-4d1995a1-1614-4313-9620-3a0b6975e6c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016537528 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.4016537528
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.943736695
Short name T918
Test name
Test status
Simulation time 13663273 ps
CPU time 0.92 seconds
Started Feb 25 12:27:51 PM PST 24
Finished Feb 25 12:27:52 PM PST 24
Peak memory 204184 kb
Host smart-9a9eb473-0b61-4545-b54b-a744288a5cbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943736695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.943736695
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1341974309
Short name T883
Test name
Test status
Simulation time 25428510 ps
CPU time 0.99 seconds
Started Feb 25 12:27:49 PM PST 24
Finished Feb 25 12:27:51 PM PST 24
Peak memory 204948 kb
Host smart-30eda62d-2e5d-4985-9305-3bcae3d3acd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341974309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1341974309
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1193184901
Short name T946
Test name
Test status
Simulation time 42679741 ps
CPU time 0.94 seconds
Started Feb 25 12:27:54 PM PST 24
Finished Feb 25 12:27:56 PM PST 24
Peak memory 204976 kb
Host smart-e7b29a7e-9aa7-4c20-868d-fe7b2ea3e6ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193184901 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1193184901
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.376294841
Short name T939
Test name
Test status
Simulation time 336670655 ps
CPU time 3.52 seconds
Started Feb 25 12:27:44 PM PST 24
Finished Feb 25 12:27:48 PM PST 24
Peak memory 213264 kb
Host smart-9921c315-3b00-4b01-8ce4-f5a4da313b4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376294841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.376294841
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.4237084829
Short name T858
Test name
Test status
Simulation time 658592698 ps
CPU time 1.53 seconds
Started Feb 25 12:27:56 PM PST 24
Finished Feb 25 12:27:58 PM PST 24
Peak memory 205752 kb
Host smart-4acfe87a-1b10-4592-9263-ea4c0eede4c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237084829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.4237084829
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2353863521
Short name T893
Test name
Test status
Simulation time 14027251 ps
CPU time 0.86 seconds
Started Feb 25 12:29:05 PM PST 24
Finished Feb 25 12:29:06 PM PST 24
Peak memory 205608 kb
Host smart-c4da374e-6c5a-47ea-9a13-d4b90527730e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353863521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2353863521
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3536025410
Short name T934
Test name
Test status
Simulation time 22283834 ps
CPU time 0.82 seconds
Started Feb 25 12:29:07 PM PST 24
Finished Feb 25 12:29:10 PM PST 24
Peak memory 205548 kb
Host smart-c147c56f-66c3-4a38-ad8a-c5074c208df2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536025410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3536025410
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1363972179
Short name T953
Test name
Test status
Simulation time 42120083 ps
CPU time 0.82 seconds
Started Feb 25 12:28:53 PM PST 24
Finished Feb 25 12:28:54 PM PST 24
Peak memory 205544 kb
Host smart-9588afb1-b57b-4a81-a767-ad5c16e3e445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363972179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1363972179
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.3095952650
Short name T898
Test name
Test status
Simulation time 13040303 ps
CPU time 0.88 seconds
Started Feb 25 12:29:07 PM PST 24
Finished Feb 25 12:29:09 PM PST 24
Peak memory 205588 kb
Host smart-459a2ad2-2f2e-4cdd-8a80-a8bb3dd001b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095952650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.3095952650
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2339181989
Short name T881
Test name
Test status
Simulation time 28213568 ps
CPU time 0.94 seconds
Started Feb 25 12:28:59 PM PST 24
Finished Feb 25 12:29:01 PM PST 24
Peak memory 204932 kb
Host smart-4db726d5-62a0-48b9-9a2a-808f7b6e99e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339181989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2339181989
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3527075294
Short name T873
Test name
Test status
Simulation time 14576959 ps
CPU time 0.88 seconds
Started Feb 25 12:28:50 PM PST 24
Finished Feb 25 12:28:51 PM PST 24
Peak memory 205604 kb
Host smart-9243fa87-9bbd-482f-9689-b53eca454e96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527075294 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3527075294
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.984136776
Short name T842
Test name
Test status
Simulation time 44133911 ps
CPU time 0.8 seconds
Started Feb 25 12:29:20 PM PST 24
Finished Feb 25 12:29:21 PM PST 24
Peak memory 205620 kb
Host smart-5f683819-55bb-4aac-83ad-73b9dc369327
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984136776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.984136776
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.931228047
Short name T886
Test name
Test status
Simulation time 48606974 ps
CPU time 0.85 seconds
Started Feb 25 12:29:15 PM PST 24
Finished Feb 25 12:29:17 PM PST 24
Peak memory 205612 kb
Host smart-fbaeb210-7d5f-4d34-820f-af3c6f41115f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931228047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.931228047
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2730796004
Short name T911
Test name
Test status
Simulation time 135691060 ps
CPU time 0.81 seconds
Started Feb 25 12:29:14 PM PST 24
Finished Feb 25 12:29:15 PM PST 24
Peak memory 205700 kb
Host smart-ecb93b80-d823-48ce-a582-c004ab2253d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730796004 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2730796004
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.4198237043
Short name T942
Test name
Test status
Simulation time 40254690 ps
CPU time 0.92 seconds
Started Feb 25 12:29:05 PM PST 24
Finished Feb 25 12:29:06 PM PST 24
Peak memory 204860 kb
Host smart-4df2b4d4-174e-46cf-acd0-904e551db1ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198237043 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.4198237043
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.919197698
Short name T232
Test name
Test status
Simulation time 16714199 ps
CPU time 1.01 seconds
Started Feb 25 12:27:53 PM PST 24
Finished Feb 25 12:27:54 PM PST 24
Peak memory 205612 kb
Host smart-367695ec-ef74-4847-b62c-867105478d43
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919197698 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.919197698
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3861732051
Short name T928
Test name
Test status
Simulation time 98447459 ps
CPU time 2.76 seconds
Started Feb 25 12:27:54 PM PST 24
Finished Feb 25 12:27:57 PM PST 24
Peak memory 205756 kb
Host smart-7d009bc5-a270-4f00-a2b2-e0fa61a68fe1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861732051 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3861732051
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.650142355
Short name T225
Test name
Test status
Simulation time 247042541 ps
CPU time 1.1 seconds
Started Feb 25 12:27:48 PM PST 24
Finished Feb 25 12:27:50 PM PST 24
Peak memory 205004 kb
Host smart-d24b7af9-429e-4665-99c1-a288d3772268
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650142355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.650142355
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.2095583206
Short name T884
Test name
Test status
Simulation time 50525960 ps
CPU time 1 seconds
Started Feb 25 12:27:51 PM PST 24
Finished Feb 25 12:27:52 PM PST 24
Peak memory 213924 kb
Host smart-5077c431-ff68-4317-b598-f2db97ae5909
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095583206 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.2095583206
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2883663766
Short name T233
Test name
Test status
Simulation time 10842806 ps
CPU time 0.92 seconds
Started Feb 25 12:27:48 PM PST 24
Finished Feb 25 12:27:50 PM PST 24
Peak memory 204916 kb
Host smart-b27cf629-7f2c-49cc-b7be-e5ad301333a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883663766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2883663766
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.3730785918
Short name T943
Test name
Test status
Simulation time 21552194 ps
CPU time 0.79 seconds
Started Feb 25 12:27:55 PM PST 24
Finished Feb 25 12:27:56 PM PST 24
Peak memory 205292 kb
Host smart-c92bf672-4a48-42c5-8a6f-61febec2c98f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730785918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.3730785918
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2968045084
Short name T224
Test name
Test status
Simulation time 30792369 ps
CPU time 1.39 seconds
Started Feb 25 12:27:51 PM PST 24
Finished Feb 25 12:27:53 PM PST 24
Peak memory 204116 kb
Host smart-47ee6bc8-a6dc-4479-b5fc-8b52170f6520
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968045084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2968045084
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3697663028
Short name T844
Test name
Test status
Simulation time 88666473 ps
CPU time 2.12 seconds
Started Feb 25 12:27:49 PM PST 24
Finished Feb 25 12:27:51 PM PST 24
Peak memory 214316 kb
Host smart-20d747c6-532e-4abe-b8b1-c9fe3c6bb4bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697663028 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3697663028
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2021353074
Short name T933
Test name
Test status
Simulation time 220431816 ps
CPU time 1.47 seconds
Started Feb 25 12:27:50 PM PST 24
Finished Feb 25 12:27:53 PM PST 24
Peak memory 205064 kb
Host smart-fb5fbf63-ffbf-4dca-bcca-345112dcf47b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021353074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2021353074
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2447176434
Short name T853
Test name
Test status
Simulation time 37174051 ps
CPU time 0.86 seconds
Started Feb 25 12:29:04 PM PST 24
Finished Feb 25 12:29:05 PM PST 24
Peak memory 205540 kb
Host smart-a5dcd456-3b19-4aff-9b72-c515b9a7fb84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447176434 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2447176434
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3965191259
Short name T851
Test name
Test status
Simulation time 13263637 ps
CPU time 0.87 seconds
Started Feb 25 12:29:03 PM PST 24
Finished Feb 25 12:29:04 PM PST 24
Peak memory 205612 kb
Host smart-3d215f6d-4c7c-402a-974c-39e36e4c1a10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965191259 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3965191259
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2230076340
Short name T837
Test name
Test status
Simulation time 26711559 ps
CPU time 0.86 seconds
Started Feb 25 12:29:14 PM PST 24
Finished Feb 25 12:29:15 PM PST 24
Peak memory 205612 kb
Host smart-5cad26cb-d2f6-4e5f-9017-57f5e3ee7a5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230076340 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2230076340
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.4006550713
Short name T901
Test name
Test status
Simulation time 11982539 ps
CPU time 0.92 seconds
Started Feb 25 12:29:20 PM PST 24
Finished Feb 25 12:29:21 PM PST 24
Peak memory 204936 kb
Host smart-2541b722-4cba-45d5-a074-e70241ca1fce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006550713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.4006550713
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.4108606024
Short name T907
Test name
Test status
Simulation time 49462149 ps
CPU time 0.83 seconds
Started Feb 25 12:29:22 PM PST 24
Finished Feb 25 12:29:23 PM PST 24
Peak memory 205316 kb
Host smart-e6e7ec42-6608-48f3-808d-d90d126891be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108606024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.4108606024
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2065906804
Short name T865
Test name
Test status
Simulation time 23113857 ps
CPU time 0.82 seconds
Started Feb 25 12:29:12 PM PST 24
Finished Feb 25 12:29:13 PM PST 24
Peak memory 205612 kb
Host smart-c0075c22-811c-453b-8463-0abfdf9e20c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065906804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2065906804
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.1486586686
Short name T914
Test name
Test status
Simulation time 33339467 ps
CPU time 0.78 seconds
Started Feb 25 12:29:12 PM PST 24
Finished Feb 25 12:29:14 PM PST 24
Peak memory 204860 kb
Host smart-cf380bd1-91e6-49ea-a984-bbbc7a0c89f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486586686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.1486586686
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3940444177
Short name T904
Test name
Test status
Simulation time 22266646 ps
CPU time 0.84 seconds
Started Feb 25 12:28:57 PM PST 24
Finished Feb 25 12:28:58 PM PST 24
Peak memory 205608 kb
Host smart-0d548372-28fc-45a3-be15-473d197c3334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940444177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3940444177
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.4064729203
Short name T882
Test name
Test status
Simulation time 55200841 ps
CPU time 0.8 seconds
Started Feb 25 12:29:16 PM PST 24
Finished Feb 25 12:29:16 PM PST 24
Peak memory 205632 kb
Host smart-e9931754-a0b7-4099-b1df-9130fe69acdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064729203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.4064729203
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.3587049696
Short name T895
Test name
Test status
Simulation time 12589409 ps
CPU time 0.85 seconds
Started Feb 25 12:29:05 PM PST 24
Finished Feb 25 12:29:06 PM PST 24
Peak memory 205624 kb
Host smart-c241eb4d-8d19-4a84-927f-58eec5e586d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587049696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.3587049696
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.307043359
Short name T963
Test name
Test status
Simulation time 70767995 ps
CPU time 1.4 seconds
Started Feb 25 12:28:57 PM PST 24
Finished Feb 25 12:28:59 PM PST 24
Peak memory 214008 kb
Host smart-96e35f30-8f1a-464a-b1ef-905b9d0da8f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307043359 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.307043359
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2755720284
Short name T952
Test name
Test status
Simulation time 53471878 ps
CPU time 0.9 seconds
Started Feb 25 12:28:57 PM PST 24
Finished Feb 25 12:28:58 PM PST 24
Peak memory 205660 kb
Host smart-e95ae427-9b43-4878-8936-b3adc039efb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755720284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2755720284
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.375675458
Short name T840
Test name
Test status
Simulation time 22323745 ps
CPU time 0.83 seconds
Started Feb 25 12:28:45 PM PST 24
Finished Feb 25 12:28:46 PM PST 24
Peak memory 205616 kb
Host smart-c1dd5976-c4d3-4395-b01b-9dc8905ed352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375675458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.375675458
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2001476784
Short name T961
Test name
Test status
Simulation time 61300619 ps
CPU time 1.15 seconds
Started Feb 25 12:28:38 PM PST 24
Finished Feb 25 12:28:41 PM PST 24
Peak memory 204280 kb
Host smart-18ef038d-9abb-49d8-b44d-029336953e99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001476784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2001476784
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.4212037529
Short name T843
Test name
Test status
Simulation time 324381184 ps
CPU time 2.02 seconds
Started Feb 25 12:27:49 PM PST 24
Finished Feb 25 12:27:51 PM PST 24
Peak memory 213252 kb
Host smart-6d3203e9-c96b-43c2-91f9-844446308de6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212037529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.4212037529
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2552339139
Short name T966
Test name
Test status
Simulation time 191681464 ps
CPU time 2.68 seconds
Started Feb 25 12:27:50 PM PST 24
Finished Feb 25 12:27:53 PM PST 24
Peak memory 205756 kb
Host smart-33dea9f0-cf78-4a5d-ae09-96228b4785cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552339139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2552339139
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2763006945
Short name T845
Test name
Test status
Simulation time 109907430 ps
CPU time 1.34 seconds
Started Feb 25 12:29:15 PM PST 24
Finished Feb 25 12:29:17 PM PST 24
Peak memory 213284 kb
Host smart-5e10fdf3-3d04-4192-9ca6-2aa7f81c6426
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763006945 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2763006945
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2134533586
Short name T220
Test name
Test status
Simulation time 14765318 ps
CPU time 0.89 seconds
Started Feb 25 12:28:34 PM PST 24
Finished Feb 25 12:28:35 PM PST 24
Peak memory 205704 kb
Host smart-1bf4303e-9d55-4484-b9b0-bf9f64d4cf8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134533586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2134533586
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1061872312
Short name T945
Test name
Test status
Simulation time 25741757 ps
CPU time 1.01 seconds
Started Feb 25 12:28:51 PM PST 24
Finished Feb 25 12:28:54 PM PST 24
Peak memory 204912 kb
Host smart-115a4cf4-1e08-4886-80fb-2db63d178de3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061872312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1061872312
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1510138246
Short name T236
Test name
Test status
Simulation time 177000732 ps
CPU time 1.28 seconds
Started Feb 25 12:28:45 PM PST 24
Finished Feb 25 12:28:47 PM PST 24
Peak memory 205000 kb
Host smart-1083535f-898f-41fa-ab7e-aa10b4f44891
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510138246 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1510138246
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.714129284
Short name T957
Test name
Test status
Simulation time 810128984 ps
CPU time 4 seconds
Started Feb 25 12:28:44 PM PST 24
Finished Feb 25 12:28:48 PM PST 24
Peak memory 213996 kb
Host smart-fa6a06af-b176-4c64-9488-a3d05b9b4e07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714129284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.714129284
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.4259551367
Short name T241
Test name
Test status
Simulation time 146980194 ps
CPU time 2.25 seconds
Started Feb 25 12:29:18 PM PST 24
Finished Feb 25 12:29:21 PM PST 24
Peak memory 205104 kb
Host smart-34d86f7b-f6b4-4bb1-ae37-94c7991aa3c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259551367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.4259551367
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2998646303
Short name T885
Test name
Test status
Simulation time 72560709 ps
CPU time 1.2 seconds
Started Feb 25 12:29:01 PM PST 24
Finished Feb 25 12:29:02 PM PST 24
Peak memory 213952 kb
Host smart-cc9a0a45-b818-4ef0-9cc2-32f30a36f40e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998646303 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2998646303
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3763845316
Short name T925
Test name
Test status
Simulation time 40860722 ps
CPU time 0.98 seconds
Started Feb 25 12:28:55 PM PST 24
Finished Feb 25 12:28:56 PM PST 24
Peak memory 204988 kb
Host smart-e41b9169-f8ef-4eb2-b561-7596ced505ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763845316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3763845316
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.2048656017
Short name T863
Test name
Test status
Simulation time 13834420 ps
CPU time 0.97 seconds
Started Feb 25 12:28:49 PM PST 24
Finished Feb 25 12:28:50 PM PST 24
Peak memory 204944 kb
Host smart-6200faac-22c8-4fbd-a782-e4c30ba125a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048656017 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.2048656017
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1888191198
Short name T921
Test name
Test status
Simulation time 44222917 ps
CPU time 1.31 seconds
Started Feb 25 12:28:59 PM PST 24
Finished Feb 25 12:29:00 PM PST 24
Peak memory 205744 kb
Host smart-12d0afb0-9d53-4f2c-92e4-c46fc2e991ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888191198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1888191198
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3501239431
Short name T956
Test name
Test status
Simulation time 189005524 ps
CPU time 3.2 seconds
Started Feb 25 12:28:54 PM PST 24
Finished Feb 25 12:28:58 PM PST 24
Peak memory 213952 kb
Host smart-8a72f2dc-e0ab-4315-aaf4-384d19d789cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501239431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3501239431
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1924160957
Short name T938
Test name
Test status
Simulation time 168466755 ps
CPU time 1.66 seconds
Started Feb 25 12:28:55 PM PST 24
Finished Feb 25 12:28:57 PM PST 24
Peak memory 205684 kb
Host smart-c076991c-5bf7-4d82-8bec-bb7aa199dfa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924160957 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1924160957
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2983101156
Short name T859
Test name
Test status
Simulation time 40816825 ps
CPU time 1.18 seconds
Started Feb 25 12:28:51 PM PST 24
Finished Feb 25 12:28:52 PM PST 24
Peak memory 213952 kb
Host smart-31c0a320-f93a-471d-b899-7109ceee4708
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983101156 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2983101156
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.3939631210
Short name T238
Test name
Test status
Simulation time 36443012 ps
CPU time 0.8 seconds
Started Feb 25 12:28:47 PM PST 24
Finished Feb 25 12:28:48 PM PST 24
Peak memory 205592 kb
Host smart-a657be11-4f86-47b2-894c-3b33efa5affb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939631210 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.3939631210
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.1296141274
Short name T905
Test name
Test status
Simulation time 20387657 ps
CPU time 0.83 seconds
Started Feb 25 12:29:01 PM PST 24
Finished Feb 25 12:29:02 PM PST 24
Peak memory 205624 kb
Host smart-eda82317-8ca3-42b0-b54b-75536e76552b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296141274 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.1296141274
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.2575172184
Short name T234
Test name
Test status
Simulation time 123954492 ps
CPU time 1.35 seconds
Started Feb 25 12:28:48 PM PST 24
Finished Feb 25 12:28:49 PM PST 24
Peak memory 205752 kb
Host smart-e950d000-9d32-43f9-8895-3c30be4f851f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575172184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.2575172184
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1454221482
Short name T871
Test name
Test status
Simulation time 119637920 ps
CPU time 3.87 seconds
Started Feb 25 12:28:53 PM PST 24
Finished Feb 25 12:28:57 PM PST 24
Peak memory 213888 kb
Host smart-07e88c5d-4de0-42bf-a16b-66697e85b179
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454221482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1454221482
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.3805257342
Short name T922
Test name
Test status
Simulation time 295808292 ps
CPU time 2.32 seconds
Started Feb 25 12:29:01 PM PST 24
Finished Feb 25 12:29:04 PM PST 24
Peak memory 205072 kb
Host smart-f3264079-f4fa-4286-bb8f-9a462899fc38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805257342 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.3805257342
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.456409953
Short name T891
Test name
Test status
Simulation time 19130662 ps
CPU time 1.02 seconds
Started Feb 25 12:28:58 PM PST 24
Finished Feb 25 12:29:00 PM PST 24
Peak memory 205744 kb
Host smart-3f724125-afb8-43dc-95c8-9ebd2904c29c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456409953 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.456409953
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.43586445
Short name T964
Test name
Test status
Simulation time 38344699 ps
CPU time 0.85 seconds
Started Feb 25 12:28:54 PM PST 24
Finished Feb 25 12:28:55 PM PST 24
Peak memory 205608 kb
Host smart-9cfbb8f6-e238-453b-8c4e-a7ea317fa022
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43586445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.43586445
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1533975059
Short name T937
Test name
Test status
Simulation time 32922866 ps
CPU time 0.81 seconds
Started Feb 25 12:28:46 PM PST 24
Finished Feb 25 12:28:47 PM PST 24
Peak memory 205556 kb
Host smart-bf2beec3-aff6-493b-8aae-739dca03d0e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533975059 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1533975059
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2777607669
Short name T227
Test name
Test status
Simulation time 132446977 ps
CPU time 1.36 seconds
Started Feb 25 12:28:48 PM PST 24
Finished Feb 25 12:28:49 PM PST 24
Peak memory 205680 kb
Host smart-770782c5-9467-4fdb-a4de-5f5b483f00d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777607669 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2777607669
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.845796663
Short name T835
Test name
Test status
Simulation time 47548653 ps
CPU time 1.63 seconds
Started Feb 25 12:28:43 PM PST 24
Finished Feb 25 12:28:45 PM PST 24
Peak memory 213972 kb
Host smart-1776f102-3b82-415e-ab82-eff4701f26b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845796663 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.845796663
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.3743808413
Short name T240
Test name
Test status
Simulation time 115149906 ps
CPU time 1.88 seconds
Started Feb 25 12:28:50 PM PST 24
Finished Feb 25 12:28:52 PM PST 24
Peak memory 205624 kb
Host smart-1cc51dcd-f033-4402-aef7-2579cdf8da6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743808413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.3743808413
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.2181976832
Short name T184
Test name
Test status
Simulation time 26681924 ps
CPU time 1.21 seconds
Started Feb 25 01:28:32 PM PST 24
Finished Feb 25 01:28:34 PM PST 24
Peak memory 215116 kb
Host smart-60ee4fd0-3a22-49e9-a106-5afa6ba2c113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181976832 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2181976832
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.984756441
Short name T537
Test name
Test status
Simulation time 48428490 ps
CPU time 0.93 seconds
Started Feb 25 01:28:44 PM PST 24
Finished Feb 25 01:28:45 PM PST 24
Peak memory 205900 kb
Host smart-101559fb-035d-414a-a29d-4ed077e486f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984756441 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.984756441
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.2327927360
Short name T169
Test name
Test status
Simulation time 190975570 ps
CPU time 1.31 seconds
Started Feb 25 01:28:34 PM PST 24
Finished Feb 25 01:28:36 PM PST 24
Peak memory 215796 kb
Host smart-08624755-d417-46ca-8976-a00a949c14e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327927360 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.2327927360
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.2109318112
Short name T158
Test name
Test status
Simulation time 31636598 ps
CPU time 1.14 seconds
Started Feb 25 01:28:33 PM PST 24
Finished Feb 25 01:28:35 PM PST 24
Peak memory 218648 kb
Host smart-9432f076-6b32-4c9f-8447-3accd0a00cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109318112 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2109318112
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1158191769
Short name T532
Test name
Test status
Simulation time 45944109 ps
CPU time 1.66 seconds
Started Feb 25 01:28:33 PM PST 24
Finished Feb 25 01:28:35 PM PST 24
Peak memory 217308 kb
Host smart-dfa12416-dae6-4af7-9b63-3f86af1c5b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158191769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1158191769
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.4290051504
Short name T451
Test name
Test status
Simulation time 22061143 ps
CPU time 1.1 seconds
Started Feb 25 01:28:33 PM PST 24
Finished Feb 25 01:28:34 PM PST 24
Peak memory 215016 kb
Host smart-b4a60204-c9b9-4759-a719-a9c0a2110df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290051504 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.4290051504
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.4053613233
Short name T55
Test name
Test status
Simulation time 21526646 ps
CPU time 0.97 seconds
Started Feb 25 01:28:33 PM PST 24
Finished Feb 25 01:28:34 PM PST 24
Peak memory 206512 kb
Host smart-abb81a69-2fe9-4b47-9a53-66a93514fc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053613233 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.4053613233
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_smoke.894412845
Short name T637
Test name
Test status
Simulation time 91150447 ps
CPU time 0.9 seconds
Started Feb 25 01:28:33 PM PST 24
Finished Feb 25 01:28:34 PM PST 24
Peak memory 214800 kb
Host smart-85d71136-326e-4a6b-80dd-010e0c586c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894412845 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.894412845
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.432098846
Short name T548
Test name
Test status
Simulation time 672410296 ps
CPU time 6.46 seconds
Started Feb 25 01:28:33 PM PST 24
Finished Feb 25 01:28:40 PM PST 24
Peak memory 217136 kb
Host smart-2c1321ca-a888-42d3-abbb-0516b922c485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432098846 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.432098846
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_alert_test.1782593078
Short name T513
Test name
Test status
Simulation time 14201734 ps
CPU time 0.86 seconds
Started Feb 25 01:28:40 PM PST 24
Finished Feb 25 01:28:41 PM PST 24
Peak memory 204984 kb
Host smart-eabc3d19-986b-4dc3-b9bc-c1f141d04c8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782593078 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1782593078
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.3512733503
Short name T528
Test name
Test status
Simulation time 34737373 ps
CPU time 0.82 seconds
Started Feb 25 01:28:38 PM PST 24
Finished Feb 25 01:28:39 PM PST 24
Peak memory 214784 kb
Host smart-2568f682-7ade-433e-8cf4-46ae9d9ead09
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512733503 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3512733503
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1346971704
Short name T426
Test name
Test status
Simulation time 33314013 ps
CPU time 1.15 seconds
Started Feb 25 01:28:36 PM PST 24
Finished Feb 25 01:28:38 PM PST 24
Peak memory 215748 kb
Host smart-e608212e-5550-41ee-a5ec-d49d89fe96dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346971704 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1346971704
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.1433152928
Short name T802
Test name
Test status
Simulation time 37775135 ps
CPU time 1.59 seconds
Started Feb 25 01:28:36 PM PST 24
Finished Feb 25 01:28:39 PM PST 24
Peak memory 223592 kb
Host smart-4a1d513a-8d22-4fe6-991d-b6d5243ad58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433152928 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1433152928
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.3672673721
Short name T738
Test name
Test status
Simulation time 44243085 ps
CPU time 1.11 seconds
Started Feb 25 01:28:34 PM PST 24
Finished Feb 25 01:28:35 PM PST 24
Peak memory 215756 kb
Host smart-930a9e06-a117-4c76-9c9c-2afc368db5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672673721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.3672673721
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.1213718043
Short name T605
Test name
Test status
Simulation time 24961075 ps
CPU time 0.97 seconds
Started Feb 25 01:28:44 PM PST 24
Finished Feb 25 01:28:45 PM PST 24
Peak memory 214904 kb
Host smart-d85e5d9c-1935-41cf-aa82-8026865663dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213718043 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.1213718043
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_regwen.1427716037
Short name T295
Test name
Test status
Simulation time 18046364 ps
CPU time 0.94 seconds
Started Feb 25 01:28:40 PM PST 24
Finished Feb 25 01:28:41 PM PST 24
Peak memory 206476 kb
Host smart-775dd9fb-d8b7-47f7-b12a-2b4f34bd3f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427716037 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1427716037
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2986051565
Short name T16
Test name
Test status
Simulation time 731237020 ps
CPU time 5.9 seconds
Started Feb 25 01:28:37 PM PST 24
Finished Feb 25 01:28:43 PM PST 24
Peak memory 235976 kb
Host smart-4e3e5721-5a1b-49a7-b153-965f86570ca3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986051565 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2986051565
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.1365656613
Short name T635
Test name
Test status
Simulation time 17414726 ps
CPU time 0.98 seconds
Started Feb 25 01:28:34 PM PST 24
Finished Feb 25 01:28:35 PM PST 24
Peak memory 214744 kb
Host smart-5207b2af-b75a-446c-b978-7d4c55e603ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365656613 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.1365656613
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1389311924
Short name T596
Test name
Test status
Simulation time 179460629 ps
CPU time 2.27 seconds
Started Feb 25 01:28:43 PM PST 24
Finished Feb 25 01:28:46 PM PST 24
Peak memory 218520 kb
Host smart-65ebfa46-50b9-49a9-8a9e-87414e6d075f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389311924 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1389311924
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert.1353937774
Short name T108
Test name
Test status
Simulation time 76170760 ps
CPU time 1.12 seconds
Started Feb 25 01:29:12 PM PST 24
Finished Feb 25 01:29:14 PM PST 24
Peak memory 215116 kb
Host smart-7d683511-83c2-4936-bd27-c580d886ff0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353937774 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1353937774
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.3430831479
Short name T757
Test name
Test status
Simulation time 14830408 ps
CPU time 0.91 seconds
Started Feb 25 01:29:11 PM PST 24
Finished Feb 25 01:29:12 PM PST 24
Peak memory 205968 kb
Host smart-142aee7f-a976-4e68-b330-42da1ed3321e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430831479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.3430831479
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_err.4168245926
Short name T771
Test name
Test status
Simulation time 33924269 ps
CPU time 1.11 seconds
Started Feb 25 01:29:14 PM PST 24
Finished Feb 25 01:29:15 PM PST 24
Peak memory 219788 kb
Host smart-24f49879-cd37-43b7-9391-6eb4d0f3ee4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168245926 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.4168245926
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_intr.2939108395
Short name T344
Test name
Test status
Simulation time 30428257 ps
CPU time 0.88 seconds
Started Feb 25 01:29:10 PM PST 24
Finished Feb 25 01:29:11 PM PST 24
Peak memory 214836 kb
Host smart-43ec5e11-12f2-43a6-8830-3e71924b34af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939108395 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2939108395
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.3988133282
Short name T495
Test name
Test status
Simulation time 30016288 ps
CPU time 1.01 seconds
Started Feb 25 01:29:12 PM PST 24
Finished Feb 25 01:29:13 PM PST 24
Peak memory 206516 kb
Host smart-13a96530-3e64-42a3-9626-b33857664d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988133282 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.3988133282
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.120936704
Short name T582
Test name
Test status
Simulation time 866733327 ps
CPU time 4.84 seconds
Started Feb 25 01:29:09 PM PST 24
Finished Feb 25 01:29:14 PM PST 24
Peak memory 215708 kb
Host smart-74003d6b-daef-4879-bfa8-90942230b0d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120936704 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.120936704
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.964391431
Short name T198
Test name
Test status
Simulation time 114798605347 ps
CPU time 672.52 seconds
Started Feb 25 01:29:16 PM PST 24
Finished Feb 25 01:40:28 PM PST 24
Peak memory 218972 kb
Host smart-76fcb762-ade2-404b-b284-0aee00a07a93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964391431 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.964391431
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.1825294775
Short name T648
Test name
Test status
Simulation time 30305890 ps
CPU time 1.39 seconds
Started Feb 25 01:30:51 PM PST 24
Finished Feb 25 01:30:53 PM PST 24
Peak memory 216148 kb
Host smart-207b3a8d-076c-4dea-bbb5-14f92821ed16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825294775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1825294775
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.2813625535
Short name T350
Test name
Test status
Simulation time 69348680 ps
CPU time 1.56 seconds
Started Feb 25 01:30:52 PM PST 24
Finished Feb 25 01:30:54 PM PST 24
Peak memory 217268 kb
Host smart-879b33a7-b76d-4fbf-b42c-ae21396f96a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813625535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2813625535
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.3124136793
Short name T441
Test name
Test status
Simulation time 86645109 ps
CPU time 1.34 seconds
Started Feb 25 01:30:51 PM PST 24
Finished Feb 25 01:30:53 PM PST 24
Peak memory 217600 kb
Host smart-98934e86-9a27-4e95-a883-9509d2525e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124136793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3124136793
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.633341934
Short name T668
Test name
Test status
Simulation time 26784531 ps
CPU time 1.23 seconds
Started Feb 25 01:30:52 PM PST 24
Finished Feb 25 01:30:54 PM PST 24
Peak memory 216276 kb
Host smart-824f260b-d806-4a65-ac7b-b8a8a39ab829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633341934 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.633341934
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.3334274356
Short name T638
Test name
Test status
Simulation time 75425818 ps
CPU time 1.42 seconds
Started Feb 25 01:30:51 PM PST 24
Finished Feb 25 01:30:53 PM PST 24
Peak memory 215812 kb
Host smart-3fc46a90-78cc-4fb7-9342-b0513bc0f535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334274356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3334274356
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1814576672
Short name T526
Test name
Test status
Simulation time 62327253 ps
CPU time 1.21 seconds
Started Feb 25 01:30:50 PM PST 24
Finished Feb 25 01:30:51 PM PST 24
Peak memory 217960 kb
Host smart-0e0b8c47-22ba-46fa-a538-be02481aa061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814576672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1814576672
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.2520459127
Short name T313
Test name
Test status
Simulation time 63219793 ps
CPU time 1.19 seconds
Started Feb 25 01:30:50 PM PST 24
Finished Feb 25 01:30:51 PM PST 24
Peak memory 216164 kb
Host smart-29c7363d-1419-4dc3-a039-58a74b048ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520459127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2520459127
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.120798779
Short name T626
Test name
Test status
Simulation time 115279285 ps
CPU time 1.09 seconds
Started Feb 25 01:30:55 PM PST 24
Finished Feb 25 01:30:56 PM PST 24
Peak memory 216048 kb
Host smart-32c5e4dd-1cdb-42b7-a4de-aea5c52bc1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120798779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.120798779
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.1830071638
Short name T294
Test name
Test status
Simulation time 87356779 ps
CPU time 1.16 seconds
Started Feb 25 01:29:04 PM PST 24
Finished Feb 25 01:29:05 PM PST 24
Peak memory 215104 kb
Host smart-014cafb1-c0e8-4b92-a0d9-894d06187c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830071638 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1830071638
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.1969189486
Short name T388
Test name
Test status
Simulation time 21977171 ps
CPU time 1.04 seconds
Started Feb 25 01:29:13 PM PST 24
Finished Feb 25 01:29:15 PM PST 24
Peak memory 205948 kb
Host smart-99302b69-1a68-4319-b00a-deb0be90ad8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969189486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1969189486
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_err.1265740526
Short name T105
Test name
Test status
Simulation time 30446627 ps
CPU time 1.36 seconds
Started Feb 25 01:29:10 PM PST 24
Finished Feb 25 01:29:11 PM PST 24
Peak memory 223560 kb
Host smart-5f6fc469-2c58-4c3a-9a97-f7da3d5b7266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265740526 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1265740526
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1715951819
Short name T699
Test name
Test status
Simulation time 38985172 ps
CPU time 1.44 seconds
Started Feb 25 01:29:10 PM PST 24
Finished Feb 25 01:29:12 PM PST 24
Peak memory 217104 kb
Host smart-64922a93-d777-4f4c-83c0-f1b5f981ed54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715951819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1715951819
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.4278428011
Short name T317
Test name
Test status
Simulation time 17511452 ps
CPU time 1.01 seconds
Started Feb 25 01:29:08 PM PST 24
Finished Feb 25 01:29:10 PM PST 24
Peak memory 214656 kb
Host smart-df86e8e0-34e3-4ef2-ac9f-ff5f92d2799f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278428011 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.4278428011
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.4032924501
Short name T217
Test name
Test status
Simulation time 635063545 ps
CPU time 6.4 seconds
Started Feb 25 01:29:07 PM PST 24
Finished Feb 25 01:29:14 PM PST 24
Peak memory 217136 kb
Host smart-8c2c90d3-c78f-4b84-8da9-ae8e6dd45f3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032924501 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.4032924501
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2540193269
Short name T778
Test name
Test status
Simulation time 179036198567 ps
CPU time 491.7 seconds
Started Feb 25 01:29:10 PM PST 24
Finished Feb 25 01:37:22 PM PST 24
Peak memory 218100 kb
Host smart-15cdfec8-451d-4bf8-9f86-b9312640189e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540193269 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2540193269
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.3267445579
Short name T768
Test name
Test status
Simulation time 40294549 ps
CPU time 1.56 seconds
Started Feb 25 01:30:54 PM PST 24
Finished Feb 25 01:30:56 PM PST 24
Peak memory 216072 kb
Host smart-0cfb45d4-1438-418e-abf5-23a768a0bf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267445579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3267445579
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.2641925699
Short name T268
Test name
Test status
Simulation time 78076064 ps
CPU time 2.63 seconds
Started Feb 25 01:30:55 PM PST 24
Finished Feb 25 01:30:58 PM PST 24
Peak memory 218680 kb
Host smart-bb15deb3-9d85-4378-b224-f8ea43e6a15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641925699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2641925699
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.844633396
Short name T471
Test name
Test status
Simulation time 31089843 ps
CPU time 0.98 seconds
Started Feb 25 01:30:50 PM PST 24
Finished Feb 25 01:30:51 PM PST 24
Peak memory 215928 kb
Host smart-de848f30-b98a-4825-bba7-5668d770e00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844633396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.844633396
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.2944926041
Short name T639
Test name
Test status
Simulation time 72159683 ps
CPU time 1.35 seconds
Started Feb 25 01:30:50 PM PST 24
Finished Feb 25 01:30:52 PM PST 24
Peak memory 217308 kb
Host smart-30928150-4e0c-4259-b412-6b63358a40a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944926041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2944926041
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.4284049075
Short name T788
Test name
Test status
Simulation time 91690029 ps
CPU time 3.01 seconds
Started Feb 25 01:30:57 PM PST 24
Finished Feb 25 01:31:00 PM PST 24
Peak memory 214672 kb
Host smart-504c1e40-99a0-4d6f-98b2-9770af177c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284049075 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.4284049075
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.2459330228
Short name T610
Test name
Test status
Simulation time 90273903 ps
CPU time 1.44 seconds
Started Feb 25 01:30:49 PM PST 24
Finished Feb 25 01:30:50 PM PST 24
Peak memory 217204 kb
Host smart-2ab2a9bd-4b43-4384-9354-598156063c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459330228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2459330228
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.2358216016
Short name T666
Test name
Test status
Simulation time 94761599 ps
CPU time 1.21 seconds
Started Feb 25 01:30:55 PM PST 24
Finished Feb 25 01:30:56 PM PST 24
Peak memory 218128 kb
Host smart-3df30f7b-071f-46ff-a976-e449c6528bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358216016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2358216016
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3372841622
Short name T515
Test name
Test status
Simulation time 179735516 ps
CPU time 1.23 seconds
Started Feb 25 01:30:51 PM PST 24
Finished Feb 25 01:30:53 PM PST 24
Peak memory 216176 kb
Host smart-8fbd2cc1-d278-4985-8b42-fd674e3593de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372841622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3372841622
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.3323175443
Short name T291
Test name
Test status
Simulation time 111118833 ps
CPU time 1.23 seconds
Started Feb 25 01:29:17 PM PST 24
Finished Feb 25 01:29:18 PM PST 24
Peak memory 215104 kb
Host smart-b2cf7cb8-cbf5-40a0-887f-51c7c2211c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323175443 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.3323175443
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.3614352524
Short name T425
Test name
Test status
Simulation time 44795270 ps
CPU time 0.91 seconds
Started Feb 25 01:29:15 PM PST 24
Finished Feb 25 01:29:16 PM PST 24
Peak memory 205192 kb
Host smart-d522d9d9-ab2e-4001-afb0-67be50351fd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614352524 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.3614352524
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.1196738207
Short name T830
Test name
Test status
Simulation time 36052741 ps
CPU time 0.84 seconds
Started Feb 25 01:29:18 PM PST 24
Finished Feb 25 01:29:19 PM PST 24
Peak memory 215112 kb
Host smart-6303b331-e61e-4839-91a4-3b7e99988cd4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196738207 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1196738207
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1500667345
Short name T284
Test name
Test status
Simulation time 93132634 ps
CPU time 1.01 seconds
Started Feb 25 01:29:16 PM PST 24
Finished Feb 25 01:29:17 PM PST 24
Peak memory 215876 kb
Host smart-aaae2144-56e6-48d0-a2fd-ef34df5a5073
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500667345 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1500667345
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.1046442372
Short name T4
Test name
Test status
Simulation time 38020608 ps
CPU time 0.95 seconds
Started Feb 25 01:29:14 PM PST 24
Finished Feb 25 01:29:15 PM PST 24
Peak memory 216172 kb
Host smart-ab8f479e-252d-4d00-bd85-7682066d80e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046442372 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1046442372
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2466032072
Short name T402
Test name
Test status
Simulation time 34433101 ps
CPU time 1.53 seconds
Started Feb 25 01:29:23 PM PST 24
Finished Feb 25 01:29:25 PM PST 24
Peak memory 217040 kb
Host smart-755bfdcd-2141-4e46-a9eb-4524d4b87e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466032072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2466032072
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3191201406
Short name T367
Test name
Test status
Simulation time 20968106 ps
CPU time 1.22 seconds
Started Feb 25 01:29:21 PM PST 24
Finished Feb 25 01:29:22 PM PST 24
Peak memory 223404 kb
Host smart-0a9becd7-ed33-402b-a361-2d5ac48b354e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191201406 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3191201406
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.3266250097
Short name T717
Test name
Test status
Simulation time 27606037 ps
CPU time 0.94 seconds
Started Feb 25 01:29:18 PM PST 24
Finished Feb 25 01:29:19 PM PST 24
Peak memory 214728 kb
Host smart-9baa3425-9e2c-489f-a4cf-c754a38a7479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266250097 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.3266250097
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.3697963505
Short name T704
Test name
Test status
Simulation time 183675314 ps
CPU time 3.98 seconds
Started Feb 25 01:29:13 PM PST 24
Finished Feb 25 01:29:17 PM PST 24
Peak memory 215740 kb
Host smart-c9a9154d-655f-4711-b243-2a134738b6f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697963505 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.3697963505
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.43275803
Short name T409
Test name
Test status
Simulation time 29324143719 ps
CPU time 648.43 seconds
Started Feb 25 01:29:13 PM PST 24
Finished Feb 25 01:40:02 PM PST 24
Peak memory 217844 kb
Host smart-afa2d3fc-5333-4de6-bd61-9ff0397a9b77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43275803 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.43275803
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.1228184771
Short name T405
Test name
Test status
Simulation time 252778148 ps
CPU time 3.61 seconds
Started Feb 25 01:30:53 PM PST 24
Finished Feb 25 01:30:56 PM PST 24
Peak memory 216140 kb
Host smart-b8ed08bc-dd8c-4952-b25b-2d5b4933e378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228184771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.1228184771
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.359559116
Short name T322
Test name
Test status
Simulation time 65157856 ps
CPU time 1.04 seconds
Started Feb 25 01:30:51 PM PST 24
Finished Feb 25 01:30:53 PM PST 24
Peak memory 215936 kb
Host smart-af35224c-2047-414b-9c55-1bef134f6ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359559116 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.359559116
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.2687887598
Short name T804
Test name
Test status
Simulation time 60058976 ps
CPU time 1.22 seconds
Started Feb 25 01:30:58 PM PST 24
Finished Feb 25 01:30:59 PM PST 24
Peak memory 218116 kb
Host smart-1aa49db9-5a1d-493d-b485-f4e61c70715d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687887598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2687887598
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2546651792
Short name T267
Test name
Test status
Simulation time 37460138 ps
CPU time 1.51 seconds
Started Feb 25 01:30:51 PM PST 24
Finished Feb 25 01:30:53 PM PST 24
Peak memory 217176 kb
Host smart-f20e9f78-8069-4d08-bbde-136a5429291f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546651792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2546651792
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.2910703434
Short name T575
Test name
Test status
Simulation time 33326189 ps
CPU time 0.99 seconds
Started Feb 25 01:30:58 PM PST 24
Finished Feb 25 01:30:59 PM PST 24
Peak memory 216040 kb
Host smart-692a0172-0fe9-4936-b28e-26512cf86a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910703434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.2910703434
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.1273085760
Short name T747
Test name
Test status
Simulation time 41563631 ps
CPU time 1.62 seconds
Started Feb 25 01:30:51 PM PST 24
Finished Feb 25 01:30:53 PM PST 24
Peak memory 217064 kb
Host smart-460d0465-ed6a-44e1-a3cc-6bce6867d7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273085760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1273085760
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.3973446415
Short name T780
Test name
Test status
Simulation time 35280857 ps
CPU time 1.31 seconds
Started Feb 25 01:30:56 PM PST 24
Finished Feb 25 01:30:57 PM PST 24
Peak memory 216020 kb
Host smart-e9b472f7-38aa-4021-b924-886862d2c4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973446415 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3973446415
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.1548118942
Short name T373
Test name
Test status
Simulation time 55079316 ps
CPU time 1.19 seconds
Started Feb 25 01:30:51 PM PST 24
Finished Feb 25 01:30:52 PM PST 24
Peak memory 217228 kb
Host smart-b3c38fc5-3ac5-42ee-8f0a-1eee28edecd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548118942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1548118942
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.2126505185
Short name T500
Test name
Test status
Simulation time 49679860 ps
CPU time 1.15 seconds
Started Feb 25 01:30:51 PM PST 24
Finished Feb 25 01:30:53 PM PST 24
Peak memory 216024 kb
Host smart-adc1a1de-c9c1-421c-8f2b-efa40d7392f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126505185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.2126505185
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.252154822
Short name T391
Test name
Test status
Simulation time 17173311 ps
CPU time 0.95 seconds
Started Feb 25 01:29:23 PM PST 24
Finished Feb 25 01:29:24 PM PST 24
Peak memory 206376 kb
Host smart-80944db7-7454-44ad-a073-efa2c26095e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252154822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.252154822
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.998009463
Short name T509
Test name
Test status
Simulation time 14045627 ps
CPU time 0.95 seconds
Started Feb 25 01:29:18 PM PST 24
Finished Feb 25 01:29:20 PM PST 24
Peak memory 215292 kb
Host smart-0f2f6802-42ba-4ef2-9660-f4c89e3875de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998009463 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.998009463
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_err.2735644885
Short name T762
Test name
Test status
Simulation time 22187184 ps
CPU time 0.98 seconds
Started Feb 25 01:29:17 PM PST 24
Finished Feb 25 01:29:18 PM PST 24
Peak memory 217248 kb
Host smart-2ad9f6bc-577c-47c4-9139-3dcfb71440e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735644885 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2735644885
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1016961746
Short name T447
Test name
Test status
Simulation time 45563392 ps
CPU time 1.35 seconds
Started Feb 25 01:29:22 PM PST 24
Finished Feb 25 01:29:23 PM PST 24
Peak memory 215896 kb
Host smart-42f9d5ed-a89b-45b8-ac96-d9392a38fac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016961746 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1016961746
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.926391117
Short name T130
Test name
Test status
Simulation time 26827874 ps
CPU time 0.95 seconds
Started Feb 25 01:29:12 PM PST 24
Finished Feb 25 01:29:14 PM PST 24
Peak memory 215228 kb
Host smart-5659144b-a264-46d5-a2c3-b199db86366a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926391117 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.926391117
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.123516004
Short name T600
Test name
Test status
Simulation time 28241350 ps
CPU time 0.96 seconds
Started Feb 25 01:29:15 PM PST 24
Finished Feb 25 01:29:16 PM PST 24
Peak memory 214768 kb
Host smart-c268ab91-c8cb-4cd4-ba0e-3df608b6c919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123516004 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.123516004
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.874239200
Short name T763
Test name
Test status
Simulation time 74749337554 ps
CPU time 379.74 seconds
Started Feb 25 01:29:16 PM PST 24
Finished Feb 25 01:35:36 PM PST 24
Peak memory 217592 kb
Host smart-280136d3-507b-4e3d-8759-68a94ce1de65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874239200 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.874239200
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.1933335384
Short name T777
Test name
Test status
Simulation time 120146010 ps
CPU time 2.42 seconds
Started Feb 25 01:30:52 PM PST 24
Finished Feb 25 01:30:55 PM PST 24
Peak memory 218448 kb
Host smart-1cb63e54-ec5e-4504-bd3a-8225be32ecd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933335384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1933335384
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.4124504270
Short name T622
Test name
Test status
Simulation time 74155565 ps
CPU time 1.41 seconds
Started Feb 25 01:30:53 PM PST 24
Finished Feb 25 01:30:54 PM PST 24
Peak memory 217336 kb
Host smart-a0de2568-fe39-4129-9321-4bb3bc3f44ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124504270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.4124504270
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.3551950001
Short name T387
Test name
Test status
Simulation time 98216937 ps
CPU time 1.38 seconds
Started Feb 25 01:31:04 PM PST 24
Finished Feb 25 01:31:05 PM PST 24
Peak memory 218352 kb
Host smart-3f2ca027-68db-4d12-a6cb-afa5923d6b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551950001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3551950001
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.3489270446
Short name T524
Test name
Test status
Simulation time 89455613 ps
CPU time 1.19 seconds
Started Feb 25 01:31:03 PM PST 24
Finished Feb 25 01:31:04 PM PST 24
Peak memory 217456 kb
Host smart-4421969a-5b9a-4f8d-9bca-b03da6c4afb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489270446 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.3489270446
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.2237549391
Short name T337
Test name
Test status
Simulation time 72347209 ps
CPU time 1.05 seconds
Started Feb 25 01:31:03 PM PST 24
Finished Feb 25 01:31:04 PM PST 24
Peak memory 215804 kb
Host smart-45c4b63c-6e33-4600-a596-c13ddec381cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237549391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.2237549391
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.234213670
Short name T404
Test name
Test status
Simulation time 65430628 ps
CPU time 1.4 seconds
Started Feb 25 01:31:04 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 215892 kb
Host smart-cf9eb8de-9bdc-4d31-9c9a-471dea21d9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234213670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.234213670
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1731804974
Short name T347
Test name
Test status
Simulation time 182182798 ps
CPU time 1.14 seconds
Started Feb 25 01:31:05 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 216048 kb
Host smart-7a53ed67-40f2-4116-897e-3f38c029ccab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731804974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1731804974
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_disable.1688293990
Short name T157
Test name
Test status
Simulation time 12665358 ps
CPU time 0.88 seconds
Started Feb 25 01:29:21 PM PST 24
Finished Feb 25 01:29:22 PM PST 24
Peak memory 215324 kb
Host smart-da1a4296-b3e6-437a-8064-9909e534ef6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688293990 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1688293990
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.1753010370
Short name T98
Test name
Test status
Simulation time 23131154 ps
CPU time 0.93 seconds
Started Feb 25 01:29:22 PM PST 24
Finished Feb 25 01:29:23 PM PST 24
Peak memory 217380 kb
Host smart-6a3badb0-99e1-4206-8c63-7fbb5516a0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753010370 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1753010370
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2249899211
Short name T398
Test name
Test status
Simulation time 36808150 ps
CPU time 1.36 seconds
Started Feb 25 01:29:21 PM PST 24
Finished Feb 25 01:29:23 PM PST 24
Peak memory 217188 kb
Host smart-d75775cf-fbac-46f2-9793-aedd9d227c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249899211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2249899211
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_smoke.614066584
Short name T462
Test name
Test status
Simulation time 17178097 ps
CPU time 0.99 seconds
Started Feb 25 01:29:21 PM PST 24
Finished Feb 25 01:29:22 PM PST 24
Peak memory 214672 kb
Host smart-c4652f99-10e0-4501-aca4-e73364483895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614066584 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.614066584
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.2281821351
Short name T607
Test name
Test status
Simulation time 809661041 ps
CPU time 4.72 seconds
Started Feb 25 01:29:20 PM PST 24
Finished Feb 25 01:29:25 PM PST 24
Peak memory 215888 kb
Host smart-97f4fea6-0ac5-497d-b06b-8ad3125d3e2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281821351 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.2281821351
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.3146512154
Short name T468
Test name
Test status
Simulation time 25965584040 ps
CPU time 585.15 seconds
Started Feb 25 01:29:23 PM PST 24
Finished Feb 25 01:39:08 PM PST 24
Peak memory 218116 kb
Host smart-6d427dc4-9c6b-4060-bf2d-27fededc6a30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146512154 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.3146512154
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.3339558402
Short name T377
Test name
Test status
Simulation time 49069167 ps
CPU time 1.47 seconds
Started Feb 25 01:31:02 PM PST 24
Finished Feb 25 01:31:04 PM PST 24
Peak memory 217444 kb
Host smart-2aaabe8d-cb74-4912-9480-3eb3ad5181d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339558402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.3339558402
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.2131093699
Short name T508
Test name
Test status
Simulation time 69894251 ps
CPU time 1.64 seconds
Started Feb 25 01:31:00 PM PST 24
Finished Feb 25 01:31:01 PM PST 24
Peak memory 216332 kb
Host smart-95a192cb-1dfc-49c7-9a55-1a9ef4302347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131093699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.2131093699
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.3325804982
Short name T599
Test name
Test status
Simulation time 50173213 ps
CPU time 1.25 seconds
Started Feb 25 01:31:04 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 217364 kb
Host smart-fdca173a-d5ac-4362-9723-f02ecf332a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325804982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3325804982
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.640875985
Short name T281
Test name
Test status
Simulation time 168282066 ps
CPU time 2.38 seconds
Started Feb 25 01:31:00 PM PST 24
Finished Feb 25 01:31:02 PM PST 24
Peak memory 218980 kb
Host smart-73672b2b-a3ef-4a83-a80c-da9fc89484ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640875985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.640875985
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.56461001
Short name T684
Test name
Test status
Simulation time 166489078 ps
CPU time 1.21 seconds
Started Feb 25 01:31:04 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 216040 kb
Host smart-c3acdd5f-288a-4adf-b126-9a7d2b2f611f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56461001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.56461001
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.3179273821
Short name T539
Test name
Test status
Simulation time 71889884 ps
CPU time 1.1 seconds
Started Feb 25 01:31:05 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 217436 kb
Host smart-cdbd8560-5467-4dab-b61e-a4536cada16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179273821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.3179273821
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.1282804174
Short name T617
Test name
Test status
Simulation time 73325937 ps
CPU time 1.42 seconds
Started Feb 25 01:31:05 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 217364 kb
Host smart-e1d42c4a-9aae-4470-974c-2ec4af3cddd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282804174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1282804174
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.2589207936
Short name T449
Test name
Test status
Simulation time 216269962 ps
CPU time 1.78 seconds
Started Feb 25 01:31:03 PM PST 24
Finished Feb 25 01:31:05 PM PST 24
Peak memory 217368 kb
Host smart-7748c7c9-f9be-4491-9ed6-83bcda6e8997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589207936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2589207936
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.2572936744
Short name T714
Test name
Test status
Simulation time 56006244 ps
CPU time 1.09 seconds
Started Feb 25 01:31:10 PM PST 24
Finished Feb 25 01:31:11 PM PST 24
Peak memory 217180 kb
Host smart-7846ee47-3572-4651-bbdb-1d82ec20e92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572936744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2572936744
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.2977853525
Short name T469
Test name
Test status
Simulation time 45369219 ps
CPU time 1.22 seconds
Started Feb 25 01:30:59 PM PST 24
Finished Feb 25 01:31:00 PM PST 24
Peak memory 216232 kb
Host smart-bb1ab109-e968-47f1-9cf0-e8ea458f716a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977853525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.2977853525
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3889041828
Short name T300
Test name
Test status
Simulation time 79954653 ps
CPU time 1.06 seconds
Started Feb 25 01:29:23 PM PST 24
Finished Feb 25 01:29:25 PM PST 24
Peak memory 215196 kb
Host smart-4abed326-ea21-444d-92cc-e1999d311df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889041828 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3889041828
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2071752580
Short name T566
Test name
Test status
Simulation time 17433207 ps
CPU time 0.95 seconds
Started Feb 25 01:29:25 PM PST 24
Finished Feb 25 01:29:26 PM PST 24
Peak memory 206312 kb
Host smart-a51febd1-d147-4414-affc-7e3157a00010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071752580 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2071752580
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.4075052168
Short name T769
Test name
Test status
Simulation time 23371903 ps
CPU time 0.88 seconds
Started Feb 25 01:29:21 PM PST 24
Finished Feb 25 01:29:22 PM PST 24
Peak memory 206780 kb
Host smart-00cc9fb9-64f4-4b7b-be6d-c30fbff107f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075052168 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.4075052168
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.3895563416
Short name T113
Test name
Test status
Simulation time 18167724 ps
CPU time 1.14 seconds
Started Feb 25 01:29:28 PM PST 24
Finished Feb 25 01:29:29 PM PST 24
Peak memory 222472 kb
Host smart-8614fc18-b14e-42ca-ab1c-86ef0893c2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895563416 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3895563416
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.1555296648
Short name T561
Test name
Test status
Simulation time 28414374 ps
CPU time 1.23 seconds
Started Feb 25 01:29:20 PM PST 24
Finished Feb 25 01:29:22 PM PST 24
Peak memory 218220 kb
Host smart-8db19eb0-5895-452d-a480-28b1c6a154da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555296648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.1555296648
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.926705514
Short name T58
Test name
Test status
Simulation time 16152299 ps
CPU time 0.96 seconds
Started Feb 25 01:29:21 PM PST 24
Finished Feb 25 01:29:22 PM PST 24
Peak memory 214732 kb
Host smart-5c6b6398-7c49-40c5-8495-e59c13fd7d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926705514 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.926705514
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1812490796
Short name T643
Test name
Test status
Simulation time 278701785 ps
CPU time 5.67 seconds
Started Feb 25 01:29:21 PM PST 24
Finished Feb 25 01:29:27 PM PST 24
Peak memory 215856 kb
Host smart-9c1e2fef-0882-493e-89f1-100dad1a87da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812490796 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1812490796
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.379641133
Short name T544
Test name
Test status
Simulation time 64479504450 ps
CPU time 1656.14 seconds
Started Feb 25 01:29:18 PM PST 24
Finished Feb 25 01:56:54 PM PST 24
Peak memory 225064 kb
Host smart-3ba59675-fa8c-4eb9-99e0-6d4e83f058f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379641133 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.379641133
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.3328393066
Short name T351
Test name
Test status
Simulation time 76838897 ps
CPU time 1.56 seconds
Started Feb 25 01:31:06 PM PST 24
Finished Feb 25 01:31:08 PM PST 24
Peak memory 218744 kb
Host smart-ee8b6cfb-e348-4a32-8eb7-dd53a05ee485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328393066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3328393066
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.1521449943
Short name T531
Test name
Test status
Simulation time 38033778 ps
CPU time 1.49 seconds
Started Feb 25 01:31:03 PM PST 24
Finished Feb 25 01:31:05 PM PST 24
Peak memory 215960 kb
Host smart-a2446cbd-ef8c-476f-bb46-0c796a55b4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521449943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.1521449943
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.673767843
Short name T519
Test name
Test status
Simulation time 301694517 ps
CPU time 4 seconds
Started Feb 25 01:30:58 PM PST 24
Finished Feb 25 01:31:03 PM PST 24
Peak memory 217968 kb
Host smart-849a614a-f81f-44cd-a738-46a79dc4631a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673767843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.673767843
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.207400121
Short name T144
Test name
Test status
Simulation time 133837442 ps
CPU time 2.85 seconds
Started Feb 25 01:31:05 PM PST 24
Finished Feb 25 01:31:08 PM PST 24
Peak memory 218500 kb
Host smart-c263c445-0e07-4460-b29d-ff0a04f71f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207400121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.207400121
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.1349602425
Short name T798
Test name
Test status
Simulation time 61881031 ps
CPU time 1.34 seconds
Started Feb 25 01:31:00 PM PST 24
Finished Feb 25 01:31:01 PM PST 24
Peak memory 217012 kb
Host smart-124308ce-f571-4ee9-93e6-fafa09f92f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349602425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1349602425
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.839557473
Short name T147
Test name
Test status
Simulation time 42020172 ps
CPU time 1.87 seconds
Started Feb 25 01:31:04 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 216396 kb
Host smart-0cda9854-b9a8-4e82-a7e2-f2cb4a19ad7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839557473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.839557473
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.3980818224
Short name T677
Test name
Test status
Simulation time 374448268 ps
CPU time 4.53 seconds
Started Feb 25 01:31:04 PM PST 24
Finished Feb 25 01:31:09 PM PST 24
Peak memory 218996 kb
Host smart-02adc07e-a28d-42e2-87ad-f7b7e35b39c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980818224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3980818224
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.3891856402
Short name T361
Test name
Test status
Simulation time 47529959 ps
CPU time 1.56 seconds
Started Feb 25 01:31:06 PM PST 24
Finished Feb 25 01:31:08 PM PST 24
Peak memory 215976 kb
Host smart-e08c1cec-e7f8-454d-8712-dfba0da195d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891856402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3891856402
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.3341895995
Short name T60
Test name
Test status
Simulation time 22638223 ps
CPU time 1.3 seconds
Started Feb 25 01:31:04 PM PST 24
Finished Feb 25 01:31:05 PM PST 24
Peak memory 215996 kb
Host smart-672d7085-b1a9-429b-9df7-1598255044b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341895995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3341895995
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.1845572142
Short name T292
Test name
Test status
Simulation time 24131779 ps
CPU time 1.11 seconds
Started Feb 25 01:29:25 PM PST 24
Finished Feb 25 01:29:27 PM PST 24
Peak memory 215100 kb
Host smart-f2e9d91e-da91-43bb-aad3-dc8358693ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845572142 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1845572142
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.179958829
Short name T324
Test name
Test status
Simulation time 245063180 ps
CPU time 0.95 seconds
Started Feb 25 01:29:22 PM PST 24
Finished Feb 25 01:29:23 PM PST 24
Peak memory 206288 kb
Host smart-85ec7c0e-43c6-404a-8666-bba59705a379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179958829 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.179958829
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2166937155
Short name T473
Test name
Test status
Simulation time 26831686 ps
CPU time 0.87 seconds
Started Feb 25 01:29:22 PM PST 24
Finished Feb 25 01:29:23 PM PST 24
Peak memory 214832 kb
Host smart-ebdc6492-5f87-40fd-95bd-9f192246a49a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166937155 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2166937155
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1904992812
Short name T753
Test name
Test status
Simulation time 61647159 ps
CPU time 1.16 seconds
Started Feb 25 01:29:24 PM PST 24
Finished Feb 25 01:29:25 PM PST 24
Peak memory 215968 kb
Host smart-33e01f94-c6d1-41b6-83b9-b64b47d8aa4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904992812 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1904992812
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.1489690125
Short name T89
Test name
Test status
Simulation time 35838945 ps
CPU time 0.95 seconds
Started Feb 25 01:29:28 PM PST 24
Finished Feb 25 01:29:29 PM PST 24
Peak memory 218692 kb
Host smart-206fb04d-08c2-4e58-82e4-3152764e9ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489690125 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1489690125
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_intr.4128715683
Short name T642
Test name
Test status
Simulation time 20896928 ps
CPU time 1.1 seconds
Started Feb 25 01:29:28 PM PST 24
Finished Feb 25 01:29:29 PM PST 24
Peak memory 215052 kb
Host smart-eea23293-b44b-4b26-b1c5-a6a8427b5a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128715683 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.4128715683
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.2069607128
Short name T307
Test name
Test status
Simulation time 51356121 ps
CPU time 0.82 seconds
Started Feb 25 01:29:22 PM PST 24
Finished Feb 25 01:29:23 PM PST 24
Peak memory 214732 kb
Host smart-8ac27082-47e4-4784-9b9e-42e44d41276c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069607128 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.2069607128
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3405504407
Short name T491
Test name
Test status
Simulation time 325756774 ps
CPU time 3.26 seconds
Started Feb 25 01:29:25 PM PST 24
Finished Feb 25 01:29:29 PM PST 24
Peak memory 215916 kb
Host smart-d71b5611-de09-4c3a-a381-a060f0128c0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405504407 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3405504407
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.1579515062
Short name T826
Test name
Test status
Simulation time 40087062465 ps
CPU time 910.3 seconds
Started Feb 25 01:29:23 PM PST 24
Finished Feb 25 01:44:34 PM PST 24
Peak memory 223124 kb
Host smart-10a0d6ef-3d50-414e-8602-1e40c7470e0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579515062 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.1579515062
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.1865606667
Short name T380
Test name
Test status
Simulation time 261875476 ps
CPU time 1.55 seconds
Started Feb 25 01:31:02 PM PST 24
Finished Feb 25 01:31:04 PM PST 24
Peak memory 217776 kb
Host smart-066d6696-a96d-4055-a256-d19c50e20276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865606667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1865606667
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.3019614679
Short name T598
Test name
Test status
Simulation time 85731753 ps
CPU time 1.29 seconds
Started Feb 25 01:31:05 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 217612 kb
Host smart-5d4dd824-5670-4ccb-a7b4-e1925d2fc065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019614679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3019614679
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.3213892308
Short name T436
Test name
Test status
Simulation time 40357623 ps
CPU time 1.28 seconds
Started Feb 25 01:31:00 PM PST 24
Finished Feb 25 01:31:01 PM PST 24
Peak memory 216052 kb
Host smart-533a1bee-f953-4593-adc7-3c87491503b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213892308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.3213892308
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.4162681659
Short name T810
Test name
Test status
Simulation time 95238554 ps
CPU time 1.08 seconds
Started Feb 25 01:31:03 PM PST 24
Finished Feb 25 01:31:04 PM PST 24
Peak memory 215988 kb
Host smart-132ab0d4-1e0e-4f43-ab41-7f28009c0013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162681659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.4162681659
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.658055577
Short name T40
Test name
Test status
Simulation time 67422440 ps
CPU time 2.1 seconds
Started Feb 25 01:30:59 PM PST 24
Finished Feb 25 01:31:02 PM PST 24
Peak memory 217908 kb
Host smart-ce5d0bf5-599c-476f-a7d0-1ef12dc2c035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658055577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.658055577
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.3653023143
Short name T286
Test name
Test status
Simulation time 44022787 ps
CPU time 1.64 seconds
Started Feb 25 01:31:10 PM PST 24
Finished Feb 25 01:31:11 PM PST 24
Peak memory 217336 kb
Host smart-f6205203-27ba-4573-9ebe-45c83a5294ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653023143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.3653023143
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.1562555456
Short name T245
Test name
Test status
Simulation time 83280510 ps
CPU time 1.81 seconds
Started Feb 25 01:31:01 PM PST 24
Finished Feb 25 01:31:03 PM PST 24
Peak memory 218972 kb
Host smart-144d68fc-528b-4b88-bca4-fc402858fcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562555456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.1562555456
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.2737053183
Short name T341
Test name
Test status
Simulation time 79456213 ps
CPU time 1.21 seconds
Started Feb 25 01:31:05 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 217484 kb
Host smart-6345eb98-d213-4667-aa22-cb0252b3e41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737053183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.2737053183
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.1053669835
Short name T472
Test name
Test status
Simulation time 31516028 ps
CPU time 1.19 seconds
Started Feb 25 01:31:04 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 217372 kb
Host smart-6977841f-2cda-462c-a870-07bb2b63fdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053669835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.1053669835
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3986460845
Short name T289
Test name
Test status
Simulation time 27409959 ps
CPU time 1.2 seconds
Started Feb 25 01:29:37 PM PST 24
Finished Feb 25 01:29:39 PM PST 24
Peak memory 215000 kb
Host smart-ebf6299a-af4c-4f66-be88-a90d935a3246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986460845 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3986460845
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.3760793955
Short name T479
Test name
Test status
Simulation time 35676863 ps
CPU time 0.83 seconds
Started Feb 25 01:29:22 PM PST 24
Finished Feb 25 01:29:23 PM PST 24
Peak memory 206168 kb
Host smart-d7507f49-18fd-4e96-835a-0b4a27ac5480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760793955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.3760793955
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3614144518
Short name T431
Test name
Test status
Simulation time 101560227 ps
CPU time 1.09 seconds
Started Feb 25 01:29:24 PM PST 24
Finished Feb 25 01:29:25 PM PST 24
Peak memory 215936 kb
Host smart-0da9e9b7-85db-4aef-817a-e18b43ee91eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614144518 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3614144518
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.217299356
Short name T82
Test name
Test status
Simulation time 72916679 ps
CPU time 1.2 seconds
Started Feb 25 01:29:25 PM PST 24
Finished Feb 25 01:29:27 PM PST 24
Peak memory 229112 kb
Host smart-bff7f9b4-1982-4a0d-82b2-99667cefb066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217299356 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.217299356
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.440096019
Short name T396
Test name
Test status
Simulation time 77043185 ps
CPU time 1.03 seconds
Started Feb 25 01:29:25 PM PST 24
Finished Feb 25 01:29:27 PM PST 24
Peak memory 216060 kb
Host smart-7d745004-43f9-4924-9e40-bebb61f8dcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440096019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.440096019
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3926395554
Short name T682
Test name
Test status
Simulation time 24894738 ps
CPU time 0.92 seconds
Started Feb 25 01:29:23 PM PST 24
Finished Feb 25 01:29:24 PM PST 24
Peak memory 215292 kb
Host smart-2e816bbe-3045-40da-81bd-d32ac39372c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926395554 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3926395554
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.737838861
Short name T831
Test name
Test status
Simulation time 25367938 ps
CPU time 0.91 seconds
Started Feb 25 01:29:24 PM PST 24
Finished Feb 25 01:29:25 PM PST 24
Peak memory 214684 kb
Host smart-3e59b81c-f08a-44e8-addc-f438a9a18c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737838861 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.737838861
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.525918354
Short name T348
Test name
Test status
Simulation time 756480192 ps
CPU time 4.44 seconds
Started Feb 25 01:29:26 PM PST 24
Finished Feb 25 01:29:30 PM PST 24
Peak memory 216052 kb
Host smart-8fd55ab9-7c51-4247-829e-83a1c94893f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525918354 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.525918354
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.339451631
Short name T732
Test name
Test status
Simulation time 541441720050 ps
CPU time 1253.51 seconds
Started Feb 25 01:29:22 PM PST 24
Finished Feb 25 01:50:16 PM PST 24
Peak memory 223200 kb
Host smart-7f587e40-4216-45eb-8df4-e8f3b1883976
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339451631 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.339451631
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.116547212
Short name T365
Test name
Test status
Simulation time 87429192 ps
CPU time 1.79 seconds
Started Feb 25 01:31:02 PM PST 24
Finished Feb 25 01:31:04 PM PST 24
Peak memory 218036 kb
Host smart-aa9ef512-ecba-4380-8d90-44ee0b12bfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116547212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.116547212
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.2741605554
Short name T219
Test name
Test status
Simulation time 39201034 ps
CPU time 1.46 seconds
Started Feb 25 01:31:01 PM PST 24
Finished Feb 25 01:31:02 PM PST 24
Peak memory 217200 kb
Host smart-bfa78da3-af83-4ad1-bd14-b8dfd83ff218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741605554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2741605554
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.2440427298
Short name T37
Test name
Test status
Simulation time 48515162 ps
CPU time 1.32 seconds
Started Feb 25 01:31:04 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 217356 kb
Host smart-75e04dbe-fecd-4ea2-84d1-049ffec677be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440427298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.2440427298
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.267981101
Short name T688
Test name
Test status
Simulation time 139305984 ps
CPU time 2.35 seconds
Started Feb 25 01:31:02 PM PST 24
Finished Feb 25 01:31:05 PM PST 24
Peak memory 217380 kb
Host smart-5cdf6592-2e97-4f21-89d8-10ebb69fce35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267981101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.267981101
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.2177472443
Short name T673
Test name
Test status
Simulation time 42131366 ps
CPU time 1.69 seconds
Started Feb 25 01:31:03 PM PST 24
Finished Feb 25 01:31:05 PM PST 24
Peak memory 217712 kb
Host smart-f6909384-1415-4828-bd89-5e927646aab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177472443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2177472443
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.727973515
Short name T653
Test name
Test status
Simulation time 52263970 ps
CPU time 1.77 seconds
Started Feb 25 01:31:00 PM PST 24
Finished Feb 25 01:31:02 PM PST 24
Peak memory 216128 kb
Host smart-ad9ef77c-5886-48d4-b357-16d0a8d2ba3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727973515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.727973515
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.3020935385
Short name T455
Test name
Test status
Simulation time 48371844 ps
CPU time 1.53 seconds
Started Feb 25 01:31:05 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 215996 kb
Host smart-f9564d88-4a59-41f4-a051-875acaf3c654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020935385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.3020935385
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.788642644
Short name T395
Test name
Test status
Simulation time 82970183 ps
CPU time 1.07 seconds
Started Feb 25 01:31:02 PM PST 24
Finished Feb 25 01:31:03 PM PST 24
Peak memory 215856 kb
Host smart-8aae597b-027f-4765-94b2-b646f1b80b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788642644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.788642644
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.314064425
Short name T807
Test name
Test status
Simulation time 84990752 ps
CPU time 2.89 seconds
Started Feb 25 01:31:03 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 216164 kb
Host smart-43977bc6-4521-4282-b9cb-60d32dc3c22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314064425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.314064425
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.3406865519
Short name T662
Test name
Test status
Simulation time 157832120 ps
CPU time 1.11 seconds
Started Feb 25 01:31:04 PM PST 24
Finished Feb 25 01:31:05 PM PST 24
Peak memory 215788 kb
Host smart-d722aa66-f432-4652-a32d-01b2dc6469ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406865519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3406865519
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1870652314
Short name T613
Test name
Test status
Simulation time 76196089 ps
CPU time 1.1 seconds
Started Feb 25 01:29:23 PM PST 24
Finished Feb 25 01:29:24 PM PST 24
Peak memory 215112 kb
Host smart-83824b18-f0af-457a-873d-0181dba8b3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870652314 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1870652314
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.836790991
Short name T319
Test name
Test status
Simulation time 139271968 ps
CPU time 0.95 seconds
Started Feb 25 01:29:25 PM PST 24
Finished Feb 25 01:29:26 PM PST 24
Peak memory 205888 kb
Host smart-e7d1b2a2-cbe3-4fc4-a3c2-b1cab1fb2f68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836790991 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.836790991
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.127106230
Short name T422
Test name
Test status
Simulation time 14688292 ps
CPU time 1 seconds
Started Feb 25 01:29:37 PM PST 24
Finished Feb 25 01:29:38 PM PST 24
Peak memory 214896 kb
Host smart-77610e98-5165-4b23-8d98-c81bafafec34
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127106230 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.127106230
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.2433534513
Short name T772
Test name
Test status
Simulation time 37462354 ps
CPU time 0.92 seconds
Started Feb 25 01:29:24 PM PST 24
Finished Feb 25 01:29:25 PM PST 24
Peak memory 216376 kb
Host smart-7893c1b4-8ae0-4a0a-87e3-0bcc18161da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433534513 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2433534513
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.1508534031
Short name T264
Test name
Test status
Simulation time 222042928 ps
CPU time 1.14 seconds
Started Feb 25 01:29:25 PM PST 24
Finished Feb 25 01:29:26 PM PST 24
Peak memory 215900 kb
Host smart-6cd96257-9fcf-4c32-b587-64de61609056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508534031 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.1508534031
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.1333593250
Short name T568
Test name
Test status
Simulation time 37621751 ps
CPU time 0.91 seconds
Started Feb 25 01:29:21 PM PST 24
Finished Feb 25 01:29:22 PM PST 24
Peak memory 215040 kb
Host smart-202500e4-69b2-4349-90d2-d690e50bfd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333593250 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1333593250
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.2510024033
Short name T142
Test name
Test status
Simulation time 29799469 ps
CPU time 0.97 seconds
Started Feb 25 01:29:24 PM PST 24
Finished Feb 25 01:29:25 PM PST 24
Peak memory 214672 kb
Host smart-35f72996-acdd-4437-a339-cc5e00e2943b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510024033 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2510024033
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3879522614
Short name T277
Test name
Test status
Simulation time 273521485 ps
CPU time 1.99 seconds
Started Feb 25 01:29:25 PM PST 24
Finished Feb 25 01:29:27 PM PST 24
Peak memory 215980 kb
Host smart-31f2b459-55e6-44af-9eb8-5e2e4fc72819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879522614 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3879522614
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.4066449492
Short name T199
Test name
Test status
Simulation time 87045281237 ps
CPU time 783.57 seconds
Started Feb 25 01:29:24 PM PST 24
Finished Feb 25 01:42:28 PM PST 24
Peak memory 219044 kb
Host smart-84f99c23-f50e-429c-8469-a747d7b590d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066449492 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.4066449492
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.1779120911
Short name T502
Test name
Test status
Simulation time 66763067 ps
CPU time 1.27 seconds
Started Feb 25 01:31:08 PM PST 24
Finished Feb 25 01:31:09 PM PST 24
Peak memory 217248 kb
Host smart-02fd0bcc-6a40-4570-b4fb-8f65e82df753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779120911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1779120911
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.1534444546
Short name T30
Test name
Test status
Simulation time 48068803 ps
CPU time 1.33 seconds
Started Feb 25 01:31:05 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 217488 kb
Host smart-4e64bf09-3ce3-49da-bee5-fb27c641fe52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534444546 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1534444546
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.635487441
Short name T323
Test name
Test status
Simulation time 46316281 ps
CPU time 1.19 seconds
Started Feb 25 01:31:04 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 215808 kb
Host smart-c00d0341-ae4b-4820-9fe3-1ed499d48764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635487441 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.635487441
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.3226878155
Short name T529
Test name
Test status
Simulation time 32399797 ps
CPU time 1.1 seconds
Started Feb 25 01:31:05 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 215928 kb
Host smart-60e6baa4-d818-4bb9-b535-08a5268a3d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226878155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.3226878155
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.3122310029
Short name T261
Test name
Test status
Simulation time 79965238 ps
CPU time 1.19 seconds
Started Feb 25 01:31:05 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 218576 kb
Host smart-ecec124c-8ec5-4d4e-a0fd-8a6bc24fc65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122310029 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3122310029
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.3170679413
Short name T511
Test name
Test status
Simulation time 38083573 ps
CPU time 1.36 seconds
Started Feb 25 01:31:05 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 217008 kb
Host smart-40ae816d-88b1-46a7-bd16-8a2075f14137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170679413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.3170679413
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.1704466037
Short name T576
Test name
Test status
Simulation time 76434934 ps
CPU time 2.62 seconds
Started Feb 25 01:31:07 PM PST 24
Finished Feb 25 01:31:10 PM PST 24
Peak memory 217524 kb
Host smart-18d0c2af-21a0-4da3-955e-94703567032a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704466037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1704466037
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.4034613778
Short name T487
Test name
Test status
Simulation time 83570084 ps
CPU time 1.4 seconds
Started Feb 25 01:31:07 PM PST 24
Finished Feb 25 01:31:09 PM PST 24
Peak memory 217292 kb
Host smart-4843ce01-b45c-4acc-9c67-dcc4ed9c946e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034613778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.4034613778
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1581817476
Short name T650
Test name
Test status
Simulation time 47044330 ps
CPU time 1.1 seconds
Started Feb 25 01:31:07 PM PST 24
Finished Feb 25 01:31:08 PM PST 24
Peak memory 218236 kb
Host smart-f75b3d49-352b-4546-8cad-c0e6a36ddbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581817476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1581817476
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.491779989
Short name T243
Test name
Test status
Simulation time 40320640 ps
CPU time 1.47 seconds
Started Feb 25 01:31:05 PM PST 24
Finished Feb 25 01:31:07 PM PST 24
Peak memory 217400 kb
Host smart-8ab6b421-7aaf-4063-b5e1-46b180651610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491779989 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.491779989
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2379708771
Short name T287
Test name
Test status
Simulation time 74279751 ps
CPU time 1.14 seconds
Started Feb 25 01:29:24 PM PST 24
Finished Feb 25 01:29:26 PM PST 24
Peak memory 215052 kb
Host smart-a11f0f9c-8a49-4455-b791-b6c8bb1f3443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379708771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2379708771
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2201464806
Short name T672
Test name
Test status
Simulation time 14510460 ps
CPU time 0.87 seconds
Started Feb 25 01:29:24 PM PST 24
Finished Feb 25 01:29:25 PM PST 24
Peak memory 206224 kb
Host smart-14c446ce-a613-472a-88ee-865e6c5383ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201464806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2201464806
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1831377154
Short name T806
Test name
Test status
Simulation time 120953433 ps
CPU time 1.02 seconds
Started Feb 25 01:29:30 PM PST 24
Finished Feb 25 01:29:31 PM PST 24
Peak memory 215804 kb
Host smart-84a9f81e-a59b-4ec9-adcb-637eaac9cfb1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831377154 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1831377154
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.315612373
Short name T574
Test name
Test status
Simulation time 32810393 ps
CPU time 0.91 seconds
Started Feb 25 01:29:23 PM PST 24
Finished Feb 25 01:29:25 PM PST 24
Peak memory 217456 kb
Host smart-5bb0ea22-2fb4-47ae-ad73-3650b39aed43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315612373 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.315612373
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.548578717
Short name T657
Test name
Test status
Simulation time 74304172 ps
CPU time 2.59 seconds
Started Feb 25 01:29:24 PM PST 24
Finished Feb 25 01:29:27 PM PST 24
Peak memory 217368 kb
Host smart-5c1e8f56-e3f7-4415-b4f4-819782aeb7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548578717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.548578717
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.2271125662
Short name T765
Test name
Test status
Simulation time 22043415 ps
CPU time 1.21 seconds
Started Feb 25 01:29:24 PM PST 24
Finished Feb 25 01:29:26 PM PST 24
Peak memory 222568 kb
Host smart-4989be75-c430-4b84-845e-cd3cb2137fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271125662 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.2271125662
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3562060383
Short name T146
Test name
Test status
Simulation time 33178940 ps
CPU time 0.87 seconds
Started Feb 25 01:29:24 PM PST 24
Finished Feb 25 01:29:25 PM PST 24
Peak memory 214712 kb
Host smart-c3f039a1-dcf6-4f11-a756-cb37ff18b1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562060383 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3562060383
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.222920740
Short name T496
Test name
Test status
Simulation time 27116716574 ps
CPU time 306.05 seconds
Started Feb 25 01:29:24 PM PST 24
Finished Feb 25 01:34:31 PM PST 24
Peak memory 216568 kb
Host smart-ddc2d874-e6f1-45d9-8cc2-ef0d706af156
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222920740 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.222920740
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.3951155106
Short name T728
Test name
Test status
Simulation time 98835112 ps
CPU time 1.19 seconds
Started Feb 25 01:31:07 PM PST 24
Finished Feb 25 01:31:08 PM PST 24
Peak memory 216192 kb
Host smart-66b6cc50-f263-48f5-9041-fec1fc325ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951155106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.3951155106
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.3392828978
Short name T678
Test name
Test status
Simulation time 67660985 ps
CPU time 1.27 seconds
Started Feb 25 01:31:00 PM PST 24
Finished Feb 25 01:31:02 PM PST 24
Peak memory 215836 kb
Host smart-3ae1b1ea-db15-4778-8e1a-b687dc880ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392828978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.3392828978
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.1644984426
Short name T354
Test name
Test status
Simulation time 46137500 ps
CPU time 1.57 seconds
Started Feb 25 01:31:04 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 218796 kb
Host smart-a10dedc5-a7b9-4204-93f8-6d0917e15cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644984426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.1644984426
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3360018675
Short name T721
Test name
Test status
Simulation time 92060767 ps
CPU time 2.49 seconds
Started Feb 25 01:31:05 PM PST 24
Finished Feb 25 01:31:08 PM PST 24
Peak memory 219072 kb
Host smart-d3059da4-46b4-46b3-966b-9a11742beb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360018675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3360018675
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.3153785264
Short name T392
Test name
Test status
Simulation time 31297454 ps
CPU time 1.29 seconds
Started Feb 25 01:31:05 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 216080 kb
Host smart-7ed901c7-3cdf-4e5d-9cfc-aefca8d1b4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153785264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3153785264
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.2688268267
Short name T822
Test name
Test status
Simulation time 54863288 ps
CPU time 1.39 seconds
Started Feb 25 01:31:05 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 217544 kb
Host smart-30faf724-fea8-4ded-aa79-8a519d1656d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688268267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2688268267
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.2129331137
Short name T718
Test name
Test status
Simulation time 71522478 ps
CPU time 1.19 seconds
Started Feb 25 01:31:05 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 215848 kb
Host smart-aa292609-cce5-4d13-9265-8c83554ac30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129331137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.2129331137
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.3096936665
Short name T681
Test name
Test status
Simulation time 34677638 ps
CPU time 1.24 seconds
Started Feb 25 01:31:05 PM PST 24
Finished Feb 25 01:31:06 PM PST 24
Peak memory 216040 kb
Host smart-ec667471-48e8-475e-84b1-d0170df1c1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096936665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.3096936665
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.1141178770
Short name T829
Test name
Test status
Simulation time 46890238 ps
CPU time 1.53 seconds
Started Feb 25 01:31:14 PM PST 24
Finished Feb 25 01:31:16 PM PST 24
Peak memory 217168 kb
Host smart-1d2209ed-b746-4a61-a173-c45d2d7595de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141178770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.1141178770
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.2912236718
Short name T190
Test name
Test status
Simulation time 247065545 ps
CPU time 3.67 seconds
Started Feb 25 01:31:09 PM PST 24
Finished Feb 25 01:31:12 PM PST 24
Peak memory 218872 kb
Host smart-066da598-059c-4948-b4d5-808cf6c02d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912236718 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2912236718
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.4176891768
Short name T811
Test name
Test status
Simulation time 44912113 ps
CPU time 1.2 seconds
Started Feb 25 01:28:50 PM PST 24
Finished Feb 25 01:28:51 PM PST 24
Peak memory 215096 kb
Host smart-73c47e85-6308-4210-a19c-26b3946b6327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176891768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.4176891768
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.3169499522
Short name T414
Test name
Test status
Simulation time 17275909 ps
CPU time 0.93 seconds
Started Feb 25 01:28:39 PM PST 24
Finished Feb 25 01:28:40 PM PST 24
Peak memory 205420 kb
Host smart-ae02d64c-8632-4fcd-a6e2-946c844e5ce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169499522 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.3169499522
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.1178782345
Short name T669
Test name
Test status
Simulation time 26195433 ps
CPU time 1.06 seconds
Started Feb 25 01:28:40 PM PST 24
Finished Feb 25 01:28:41 PM PST 24
Peak memory 215752 kb
Host smart-19a3cba0-9b9e-4104-a6a6-26a54ba26699
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178782345 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.1178782345
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.2065203221
Short name T761
Test name
Test status
Simulation time 18226797 ps
CPU time 1.02 seconds
Started Feb 25 01:28:44 PM PST 24
Finished Feb 25 01:28:45 PM PST 24
Peak memory 217268 kb
Host smart-897675ac-ab6e-4e00-8700-88e44ec5d545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065203221 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.2065203221
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.4058890002
Short name T445
Test name
Test status
Simulation time 25319834 ps
CPU time 1.19 seconds
Started Feb 25 01:28:38 PM PST 24
Finished Feb 25 01:28:40 PM PST 24
Peak memory 216044 kb
Host smart-fd3aa6ae-75ef-465b-b631-8b099d909aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058890002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.4058890002
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.2382495547
Short name T332
Test name
Test status
Simulation time 22352283 ps
CPU time 1.12 seconds
Started Feb 25 01:28:35 PM PST 24
Finished Feb 25 01:28:36 PM PST 24
Peak memory 214892 kb
Host smart-12e5970b-65dc-4ca0-871a-e515e8967dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382495547 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.2382495547
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2168980607
Short name T54
Test name
Test status
Simulation time 312237797 ps
CPU time 3.31 seconds
Started Feb 25 01:28:38 PM PST 24
Finished Feb 25 01:28:41 PM PST 24
Peak memory 234136 kb
Host smart-67dadb8a-bb32-4125-a851-9acfe7d48c93
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168980607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2168980607
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.20000886
Short name T665
Test name
Test status
Simulation time 27435864 ps
CPU time 0.95 seconds
Started Feb 25 01:28:37 PM PST 24
Finished Feb 25 01:28:38 PM PST 24
Peak memory 214664 kb
Host smart-ac5d75b1-aca1-419d-b387-38a6a4ee0a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20000886 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.20000886
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.2413478578
Short name T270
Test name
Test status
Simulation time 87106815 ps
CPU time 2.16 seconds
Started Feb 25 01:28:37 PM PST 24
Finished Feb 25 01:28:40 PM PST 24
Peak memory 214572 kb
Host smart-b4b9f8dc-9c22-40f7-9840-2125f664f04e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413478578 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.2413478578
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3429066106
Short name T632
Test name
Test status
Simulation time 92681459432 ps
CPU time 1285.14 seconds
Started Feb 25 01:28:38 PM PST 24
Finished Feb 25 01:50:03 PM PST 24
Peak memory 222668 kb
Host smart-4e9a6fa3-d17c-4956-8d58-d43abc64ae5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429066106 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3429066106
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.335437449
Short name T13
Test name
Test status
Simulation time 38026727 ps
CPU time 1.14 seconds
Started Feb 25 01:29:23 PM PST 24
Finished Feb 25 01:29:24 PM PST 24
Peak memory 215052 kb
Host smart-ec79d68c-f975-4e9c-8aa7-d89984935824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335437449 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.335437449
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.4206069311
Short name T727
Test name
Test status
Simulation time 38597449 ps
CPU time 0.85 seconds
Started Feb 25 01:29:37 PM PST 24
Finished Feb 25 01:29:38 PM PST 24
Peak memory 206116 kb
Host smart-da1f788f-c01d-4df1-9a45-2c0193fd261e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206069311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.4206069311
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.4254997698
Short name T659
Test name
Test status
Simulation time 39595760 ps
CPU time 0.83 seconds
Started Feb 25 01:29:37 PM PST 24
Finished Feb 25 01:29:38 PM PST 24
Peak memory 214696 kb
Host smart-e7892773-4f4d-4eb3-9a79-b428c0b9d92c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254997698 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.4254997698
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3889339503
Short name T781
Test name
Test status
Simulation time 113184811 ps
CPU time 1.12 seconds
Started Feb 25 01:29:22 PM PST 24
Finished Feb 25 01:29:23 PM PST 24
Peak memory 215772 kb
Host smart-2597ea89-ede5-4387-85fd-2f513635ba46
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889339503 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3889339503
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.1031649982
Short name T552
Test name
Test status
Simulation time 23029549 ps
CPU time 0.98 seconds
Started Feb 25 01:29:28 PM PST 24
Finished Feb 25 01:29:29 PM PST 24
Peak memory 216164 kb
Host smart-b814f128-f609-4e84-8575-32fb4dc9bb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031649982 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1031649982
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2973733919
Short name T630
Test name
Test status
Simulation time 41317609 ps
CPU time 1.41 seconds
Started Feb 25 01:29:25 PM PST 24
Finished Feb 25 01:29:26 PM PST 24
Peak memory 216068 kb
Host smart-61162cac-f365-47a0-952c-96c6bb0506cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973733919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2973733919
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.4014373640
Short name T543
Test name
Test status
Simulation time 38731196 ps
CPU time 0.87 seconds
Started Feb 25 01:29:23 PM PST 24
Finished Feb 25 01:29:24 PM PST 24
Peak memory 214784 kb
Host smart-09667d04-a359-4b6a-b6a7-da5e57ef18fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014373640 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.4014373640
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.468287039
Short name T776
Test name
Test status
Simulation time 19054281 ps
CPU time 1.01 seconds
Started Feb 25 01:29:25 PM PST 24
Finished Feb 25 01:29:26 PM PST 24
Peak memory 214728 kb
Host smart-e04d5bcc-2d70-41d9-9ff8-de301e787395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468287039 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.468287039
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.598675710
Short name T685
Test name
Test status
Simulation time 391000501 ps
CPU time 4.42 seconds
Started Feb 25 01:29:37 PM PST 24
Finished Feb 25 01:29:42 PM PST 24
Peak memory 218740 kb
Host smart-2e772872-3862-49c6-b8e4-a0cf99ba08eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598675710 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.598675710
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2010233458
Short name T593
Test name
Test status
Simulation time 149287197947 ps
CPU time 911.2 seconds
Started Feb 25 01:29:30 PM PST 24
Finished Feb 25 01:44:42 PM PST 24
Peak memory 221168 kb
Host smart-cb3e1720-ca51-477e-8063-54734f2d905b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010233458 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2010233458
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.2579121798
Short name T623
Test name
Test status
Simulation time 48329874 ps
CPU time 1.75 seconds
Started Feb 25 01:31:07 PM PST 24
Finished Feb 25 01:31:08 PM PST 24
Peak memory 217396 kb
Host smart-1b6a58ff-3c10-426f-8292-fd32aa2e2908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579121798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.2579121798
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.4208580530
Short name T346
Test name
Test status
Simulation time 40652644 ps
CPU time 1.42 seconds
Started Feb 25 01:31:07 PM PST 24
Finished Feb 25 01:31:09 PM PST 24
Peak memory 215856 kb
Host smart-934d5f91-36aa-4a87-ae1b-3005bf28923f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208580530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.4208580530
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3516847954
Short name T558
Test name
Test status
Simulation time 56032598 ps
CPU time 1.69 seconds
Started Feb 25 01:31:10 PM PST 24
Finished Feb 25 01:31:11 PM PST 24
Peak memory 217536 kb
Host smart-e39a0784-737f-4c6d-8d05-dc4b211d31c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516847954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3516847954
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.534923988
Short name T263
Test name
Test status
Simulation time 58405380 ps
CPU time 2.35 seconds
Started Feb 25 01:31:14 PM PST 24
Finished Feb 25 01:31:16 PM PST 24
Peak memory 218792 kb
Host smart-efd6154e-bf4c-4abc-a8bf-a5d648172368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534923988 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.534923988
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2253619055
Short name T401
Test name
Test status
Simulation time 68687296 ps
CPU time 1.54 seconds
Started Feb 25 01:31:08 PM PST 24
Finished Feb 25 01:31:10 PM PST 24
Peak memory 217468 kb
Host smart-bd3f1112-7a45-4e94-9d55-4bdb6042a87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253619055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2253619055
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.2995017274
Short name T735
Test name
Test status
Simulation time 29932416 ps
CPU time 1.3 seconds
Started Feb 25 01:31:07 PM PST 24
Finished Feb 25 01:31:09 PM PST 24
Peak memory 215964 kb
Host smart-9f45a3ec-d8af-4a25-91bc-62fc7c010c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995017274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.2995017274
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.4074117868
Short name T321
Test name
Test status
Simulation time 88707673 ps
CPU time 1.38 seconds
Started Feb 25 01:31:08 PM PST 24
Finished Feb 25 01:31:09 PM PST 24
Peak memory 215948 kb
Host smart-9c2b9e4a-3fe6-490f-a6fe-8c2eb959e19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074117868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.4074117868
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3103894390
Short name T484
Test name
Test status
Simulation time 61495007 ps
CPU time 2.06 seconds
Started Feb 25 01:31:21 PM PST 24
Finished Feb 25 01:31:23 PM PST 24
Peak memory 216192 kb
Host smart-42dbe33a-a26b-4e8a-8582-73ab0b40c60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103894390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3103894390
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3263219627
Short name T266
Test name
Test status
Simulation time 48509438 ps
CPU time 1.28 seconds
Started Feb 25 01:31:21 PM PST 24
Finished Feb 25 01:31:23 PM PST 24
Peak memory 217356 kb
Host smart-42210fb9-52b8-466a-8f00-0c826a425121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263219627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3263219627
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.307574055
Short name T567
Test name
Test status
Simulation time 43434297 ps
CPU time 1.33 seconds
Started Feb 25 01:31:21 PM PST 24
Finished Feb 25 01:31:23 PM PST 24
Peak memory 217296 kb
Host smart-e3438f8c-ac34-492d-a4cb-7ad7d15ec09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307574055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.307574055
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert_test.2817708861
Short name T693
Test name
Test status
Simulation time 44357529 ps
CPU time 0.84 seconds
Started Feb 25 01:29:25 PM PST 24
Finished Feb 25 01:29:26 PM PST 24
Peak memory 206124 kb
Host smart-c5cbdafe-2324-40f2-9a83-afd5d0de6cb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817708861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2817708861
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.3218917495
Short name T161
Test name
Test status
Simulation time 71929085 ps
CPU time 1.26 seconds
Started Feb 25 01:29:23 PM PST 24
Finished Feb 25 01:29:24 PM PST 24
Peak memory 215640 kb
Host smart-63caf58b-3dce-43dc-9312-cd6f740410cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218917495 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.3218917495
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.928963681
Short name T77
Test name
Test status
Simulation time 30469257 ps
CPU time 1.05 seconds
Started Feb 25 01:29:24 PM PST 24
Finished Feb 25 01:29:25 PM PST 24
Peak memory 216040 kb
Host smart-27ec941d-2c66-4d31-a290-a448490cfd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928963681 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.928963681
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.2005002127
Short name T488
Test name
Test status
Simulation time 55613985 ps
CPU time 1.55 seconds
Started Feb 25 01:29:23 PM PST 24
Finished Feb 25 01:29:25 PM PST 24
Peak memory 217064 kb
Host smart-65411570-8948-4d80-ade4-18e45ec15eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005002127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.2005002127
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2057716794
Short name T588
Test name
Test status
Simulation time 40978653 ps
CPU time 1.01 seconds
Started Feb 25 01:29:22 PM PST 24
Finished Feb 25 01:29:23 PM PST 24
Peak memory 232004 kb
Host smart-76e54544-5d8e-459d-aa2b-2857ffe87f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057716794 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2057716794
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.4232545522
Short name T180
Test name
Test status
Simulation time 54300156 ps
CPU time 0.91 seconds
Started Feb 25 01:29:25 PM PST 24
Finished Feb 25 01:29:26 PM PST 24
Peak memory 206504 kb
Host smart-1c527a40-7019-4adc-9cb3-a662fbecafea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232545522 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.4232545522
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.718410147
Short name T474
Test name
Test status
Simulation time 193338044 ps
CPU time 1.57 seconds
Started Feb 25 01:29:24 PM PST 24
Finished Feb 25 01:29:26 PM PST 24
Peak memory 214736 kb
Host smart-3f440bb8-7db9-49ce-b401-e66b1a467958
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718410147 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.718410147
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.1847408332
Short name T202
Test name
Test status
Simulation time 211876162932 ps
CPU time 1347.19 seconds
Started Feb 25 01:29:25 PM PST 24
Finished Feb 25 01:51:53 PM PST 24
Peak memory 222136 kb
Host smart-4066eee2-97b0-4e32-b973-79c7e61556ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847408332 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.1847408332
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3074695944
Short name T550
Test name
Test status
Simulation time 75964018 ps
CPU time 1.17 seconds
Started Feb 25 01:31:09 PM PST 24
Finished Feb 25 01:31:10 PM PST 24
Peak memory 215840 kb
Host smart-4d24131d-2530-452a-aa73-044bded65cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074695944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3074695944
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3837708293
Short name T660
Test name
Test status
Simulation time 79251563 ps
CPU time 1.35 seconds
Started Feb 25 01:31:21 PM PST 24
Finished Feb 25 01:31:23 PM PST 24
Peak memory 217612 kb
Host smart-5dbd0fe6-0343-41c0-928b-2fe0881a80f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837708293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3837708293
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.24830126
Short name T676
Test name
Test status
Simulation time 47523051 ps
CPU time 1.22 seconds
Started Feb 25 01:31:12 PM PST 24
Finished Feb 25 01:31:13 PM PST 24
Peak memory 217200 kb
Host smart-8c55c6ef-d68d-484f-bbcf-711b2c4ec013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24830126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.24830126
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3278323574
Short name T671
Test name
Test status
Simulation time 73724937 ps
CPU time 1.03 seconds
Started Feb 25 01:31:21 PM PST 24
Finished Feb 25 01:31:22 PM PST 24
Peak memory 215892 kb
Host smart-14e38259-36cc-4bb1-b273-99360691e036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278323574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3278323574
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1465668069
Short name T749
Test name
Test status
Simulation time 76175775 ps
CPU time 2.84 seconds
Started Feb 25 01:31:11 PM PST 24
Finished Feb 25 01:31:14 PM PST 24
Peak memory 217868 kb
Host smart-27898328-70a1-45b1-9eb3-849d57797676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465668069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1465668069
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.4089595015
Short name T713
Test name
Test status
Simulation time 67325843 ps
CPU time 1.17 seconds
Started Feb 25 01:31:27 PM PST 24
Finished Feb 25 01:31:28 PM PST 24
Peak memory 216008 kb
Host smart-dcd1297b-33fb-4768-9a6e-940d4a1c0f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089595015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.4089595015
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.107288826
Short name T444
Test name
Test status
Simulation time 35183228 ps
CPU time 1.42 seconds
Started Feb 25 01:31:22 PM PST 24
Finished Feb 25 01:31:24 PM PST 24
Peak memory 217864 kb
Host smart-2cd66441-21fa-44ad-a166-953b4c1b3211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107288826 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.107288826
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.278751293
Short name T374
Test name
Test status
Simulation time 76660042 ps
CPU time 1.54 seconds
Started Feb 25 01:31:30 PM PST 24
Finished Feb 25 01:31:31 PM PST 24
Peak memory 217088 kb
Host smart-fb0b4812-c063-498a-b18b-32bcda5c9a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278751293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.278751293
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1760043028
Short name T355
Test name
Test status
Simulation time 243301469 ps
CPU time 2.16 seconds
Started Feb 25 01:31:31 PM PST 24
Finished Feb 25 01:31:33 PM PST 24
Peak memory 217496 kb
Host smart-a0304a60-f4e7-40a4-97b4-ccf1b22c9623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760043028 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1760043028
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3828620228
Short name T242
Test name
Test status
Simulation time 46920660 ps
CPU time 1.2 seconds
Started Feb 25 01:31:30 PM PST 24
Finished Feb 25 01:31:31 PM PST 24
Peak memory 217352 kb
Host smart-93da6916-9ee8-46b3-909e-ed6e6ba5c3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828620228 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3828620228
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.2603696084
Short name T809
Test name
Test status
Simulation time 99001343 ps
CPU time 1.31 seconds
Started Feb 25 01:29:23 PM PST 24
Finished Feb 25 01:29:25 PM PST 24
Peak memory 215104 kb
Host smart-6dc58b09-16e3-4dd1-bee0-fc89a3a12ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603696084 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.2603696084
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2810421173
Short name T406
Test name
Test status
Simulation time 62902529 ps
CPU time 0.94 seconds
Started Feb 25 01:29:27 PM PST 24
Finished Feb 25 01:29:28 PM PST 24
Peak memory 205924 kb
Host smart-e03aa1ee-8529-4784-b201-3c354fb2eec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810421173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2810421173
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.915842001
Short name T578
Test name
Test status
Simulation time 16457280 ps
CPU time 0.8 seconds
Started Feb 25 01:29:24 PM PST 24
Finished Feb 25 01:29:25 PM PST 24
Peak memory 215096 kb
Host smart-fc12aecf-ca16-438e-b036-3be668539dbe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915842001 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.915842001
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_err.2448543537
Short name T51
Test name
Test status
Simulation time 21483305 ps
CPU time 0.93 seconds
Started Feb 25 01:29:27 PM PST 24
Finished Feb 25 01:29:28 PM PST 24
Peak memory 217320 kb
Host smart-c7313474-c785-449e-a8ff-be7984a77514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448543537 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.2448543537
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.2967642255
Short name T211
Test name
Test status
Simulation time 127169810 ps
CPU time 1.65 seconds
Started Feb 25 01:29:27 PM PST 24
Finished Feb 25 01:29:29 PM PST 24
Peak memory 216168 kb
Host smart-9fb40505-834d-4907-aa44-e633fe68abc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967642255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.2967642255
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.1626926124
Short name T363
Test name
Test status
Simulation time 36332510 ps
CPU time 0.84 seconds
Started Feb 25 01:29:26 PM PST 24
Finished Feb 25 01:29:27 PM PST 24
Peak memory 214860 kb
Host smart-96fbe072-0cb1-4e91-8447-80b7e28ce3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626926124 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.1626926124
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2166668747
Short name T208
Test name
Test status
Simulation time 15980688 ps
CPU time 0.95 seconds
Started Feb 25 01:29:24 PM PST 24
Finished Feb 25 01:29:25 PM PST 24
Peak memory 206520 kb
Host smart-660d207e-57f7-4bba-a93d-40a7f72faf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166668747 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2166668747
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.2036059646
Short name T353
Test name
Test status
Simulation time 598398879 ps
CPU time 3.72 seconds
Started Feb 25 01:29:30 PM PST 24
Finished Feb 25 01:29:34 PM PST 24
Peak memory 216112 kb
Host smart-2b632993-1420-48a7-8c57-4d4be2f5e272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036059646 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.2036059646
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3632303380
Short name T512
Test name
Test status
Simulation time 232064525976 ps
CPU time 2239.47 seconds
Started Feb 25 01:29:30 PM PST 24
Finished Feb 25 02:06:50 PM PST 24
Peak memory 229552 kb
Host smart-3012adad-5a1d-4244-8cb7-255110f267e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632303380 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3632303380
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.536331711
Short name T258
Test name
Test status
Simulation time 40035046 ps
CPU time 1.11 seconds
Started Feb 25 01:31:28 PM PST 24
Finished Feb 25 01:31:29 PM PST 24
Peak memory 216016 kb
Host smart-f82808a1-bb78-4f2b-9a01-be9e4bced395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536331711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.536331711
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1294429051
Short name T722
Test name
Test status
Simulation time 87912979 ps
CPU time 1.2 seconds
Started Feb 25 01:31:30 PM PST 24
Finished Feb 25 01:31:32 PM PST 24
Peak memory 217288 kb
Host smart-6bdfad66-0a2a-4e06-ad4c-c13bb4a0f37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294429051 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1294429051
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2498433302
Short name T440
Test name
Test status
Simulation time 74568087 ps
CPU time 1.41 seconds
Started Feb 25 01:31:30 PM PST 24
Finished Feb 25 01:31:32 PM PST 24
Peak memory 217740 kb
Host smart-310913ce-d3bf-401b-a0ea-45437756442c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498433302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2498433302
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.606873834
Short name T371
Test name
Test status
Simulation time 49022509 ps
CPU time 1.26 seconds
Started Feb 25 01:31:20 PM PST 24
Finished Feb 25 01:31:21 PM PST 24
Peak memory 217284 kb
Host smart-df6fd61b-2ff7-4392-8fbd-799d4889ad4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606873834 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.606873834
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3882653931
Short name T556
Test name
Test status
Simulation time 51095098 ps
CPU time 1.47 seconds
Started Feb 25 01:31:30 PM PST 24
Finished Feb 25 01:31:31 PM PST 24
Peak memory 216152 kb
Host smart-8ec79816-bf04-4c21-b840-c1b7768bd4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882653931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3882653931
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.448449911
Short name T434
Test name
Test status
Simulation time 43906857 ps
CPU time 1.41 seconds
Started Feb 25 01:31:17 PM PST 24
Finished Feb 25 01:31:19 PM PST 24
Peak memory 218632 kb
Host smart-24580d5a-ca7c-4d15-9ad3-a0d8056ab52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448449911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.448449911
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.384502362
Short name T674
Test name
Test status
Simulation time 63781700 ps
CPU time 1.5 seconds
Started Feb 25 01:31:20 PM PST 24
Finished Feb 25 01:31:22 PM PST 24
Peak memory 216168 kb
Host smart-6b75c624-b0ab-4901-8497-7e64bf277e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384502362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.384502362
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.2706178502
Short name T282
Test name
Test status
Simulation time 106790045 ps
CPU time 1.64 seconds
Started Feb 25 01:31:30 PM PST 24
Finished Feb 25 01:31:31 PM PST 24
Peak memory 216140 kb
Host smart-5ccbf8c6-3fec-481c-9e00-c331beb9fb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706178502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.2706178502
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1381042130
Short name T641
Test name
Test status
Simulation time 82505688 ps
CPU time 2.73 seconds
Started Feb 25 01:31:22 PM PST 24
Finished Feb 25 01:31:26 PM PST 24
Peak memory 218420 kb
Host smart-84652013-d286-4deb-a50f-f18d49582e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381042130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1381042130
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.1486548515
Short name T454
Test name
Test status
Simulation time 53498223 ps
CPU time 2.02 seconds
Started Feb 25 01:31:35 PM PST 24
Finished Feb 25 01:31:37 PM PST 24
Peak memory 218548 kb
Host smart-390f5663-0c13-44e9-b146-ffd7ef20d472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486548515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.1486548515
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert_test.826975515
Short name T760
Test name
Test status
Simulation time 16109375 ps
CPU time 0.89 seconds
Started Feb 25 01:29:21 PM PST 24
Finished Feb 25 01:29:22 PM PST 24
Peak memory 206316 kb
Host smart-2280834b-ed79-4aa9-bf75-923b1b3ebc80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826975515 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.826975515
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1250906708
Short name T110
Test name
Test status
Simulation time 38371519 ps
CPU time 0.87 seconds
Started Feb 25 01:29:21 PM PST 24
Finished Feb 25 01:29:22 PM PST 24
Peak memory 215184 kb
Host smart-6fff7870-ef6b-44bd-a63a-7f230cfa175e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250906708 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1250906708
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.900824925
Short name T379
Test name
Test status
Simulation time 24751232 ps
CPU time 1.18 seconds
Started Feb 25 01:29:23 PM PST 24
Finished Feb 25 01:29:24 PM PST 24
Peak memory 218924 kb
Host smart-04190eaf-3430-4d41-9a93-a00c0edfc8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900824925 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.900824925
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2097624917
Short name T696
Test name
Test status
Simulation time 39264170 ps
CPU time 1.37 seconds
Started Feb 25 01:29:22 PM PST 24
Finished Feb 25 01:29:24 PM PST 24
Peak memory 215948 kb
Host smart-f325eaed-b48b-4808-ae59-2a2b9013f680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097624917 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2097624917
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3601907787
Short name T736
Test name
Test status
Simulation time 28991552 ps
CPU time 0.89 seconds
Started Feb 25 01:29:26 PM PST 24
Finished Feb 25 01:29:27 PM PST 24
Peak memory 215256 kb
Host smart-61a4fd6d-83a6-4c2b-bac6-a1c9f45bf45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601907787 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3601907787
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1846607869
Short name T751
Test name
Test status
Simulation time 24672622 ps
CPU time 0.9 seconds
Started Feb 25 01:29:25 PM PST 24
Finished Feb 25 01:29:27 PM PST 24
Peak memory 214772 kb
Host smart-a15bdf49-be16-4dd1-8542-cd34b2713014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846607869 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1846607869
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.3175198165
Short name T614
Test name
Test status
Simulation time 241198465 ps
CPU time 2.79 seconds
Started Feb 25 01:29:25 PM PST 24
Finished Feb 25 01:29:28 PM PST 24
Peak memory 215792 kb
Host smart-5024cabc-4168-4bce-b8d9-8c44c7e4a625
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175198165 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.3175198165
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.1124699162
Short name T141
Test name
Test status
Simulation time 33436721883 ps
CPU time 555.11 seconds
Started Feb 25 01:29:25 PM PST 24
Finished Feb 25 01:38:40 PM PST 24
Peak memory 217136 kb
Host smart-4c071958-9c48-4958-83af-d6ac3052cf0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124699162 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.1124699162
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.1704147313
Short name T439
Test name
Test status
Simulation time 107667419 ps
CPU time 0.9 seconds
Started Feb 25 01:31:30 PM PST 24
Finished Feb 25 01:31:31 PM PST 24
Peak memory 215880 kb
Host smart-0868b8fe-f2fd-48d2-8fc5-924220e58c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704147313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.1704147313
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3439913125
Short name T309
Test name
Test status
Simulation time 131897292 ps
CPU time 1.51 seconds
Started Feb 25 01:31:25 PM PST 24
Finished Feb 25 01:31:27 PM PST 24
Peak memory 217540 kb
Host smart-fc8b3b4c-4237-49d3-864e-977406211593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439913125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3439913125
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.686064338
Short name T352
Test name
Test status
Simulation time 26809932 ps
CPU time 1.21 seconds
Started Feb 25 01:31:21 PM PST 24
Finished Feb 25 01:31:23 PM PST 24
Peak memory 216024 kb
Host smart-330bd600-e909-486e-a346-1af47b0f00bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686064338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.686064338
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.524039019
Short name T767
Test name
Test status
Simulation time 93640029 ps
CPU time 1.22 seconds
Started Feb 25 01:31:18 PM PST 24
Finished Feb 25 01:31:19 PM PST 24
Peak memory 215856 kb
Host smart-11a656ec-d5b7-4bed-8817-61f6442e311e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524039019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.524039019
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1213159762
Short name T345
Test name
Test status
Simulation time 23821623 ps
CPU time 1.11 seconds
Started Feb 25 01:31:18 PM PST 24
Finished Feb 25 01:31:19 PM PST 24
Peak memory 217296 kb
Host smart-f7b1759f-cab0-4840-8ee7-a3129a234f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213159762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1213159762
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.736370209
Short name T356
Test name
Test status
Simulation time 295663202 ps
CPU time 4.25 seconds
Started Feb 25 01:31:33 PM PST 24
Finished Feb 25 01:31:38 PM PST 24
Peak memory 218744 kb
Host smart-3f3b2a0e-305c-449e-b246-157353430f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736370209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.736370209
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1047270663
Short name T486
Test name
Test status
Simulation time 67154993 ps
CPU time 1.09 seconds
Started Feb 25 01:31:31 PM PST 24
Finished Feb 25 01:31:32 PM PST 24
Peak memory 217292 kb
Host smart-900ecec3-9952-4553-aa37-b1f195d5b1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047270663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1047270663
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.441463893
Short name T506
Test name
Test status
Simulation time 38276968 ps
CPU time 1.17 seconds
Started Feb 25 01:31:30 PM PST 24
Finished Feb 25 01:31:31 PM PST 24
Peak memory 216116 kb
Host smart-a09c02a6-a209-45f7-b35a-478b9f76ea9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441463893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.441463893
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2036960157
Short name T661
Test name
Test status
Simulation time 84556801 ps
CPU time 1.49 seconds
Started Feb 25 01:31:29 PM PST 24
Finished Feb 25 01:31:31 PM PST 24
Peak memory 217520 kb
Host smart-6e01d11f-e349-46d8-af33-82465c6a2afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036960157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2036960157
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3377669823
Short name T695
Test name
Test status
Simulation time 40623924 ps
CPU time 1.16 seconds
Started Feb 25 01:29:35 PM PST 24
Finished Feb 25 01:29:36 PM PST 24
Peak memory 215116 kb
Host smart-f02adb27-0dff-4c5b-9948-fbc886eda340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377669823 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3377669823
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.4113292226
Short name T489
Test name
Test status
Simulation time 55308331 ps
CPU time 0.92 seconds
Started Feb 25 01:29:36 PM PST 24
Finished Feb 25 01:29:37 PM PST 24
Peak memory 206244 kb
Host smart-9522d40a-b67e-4e36-9a1c-4226964e87fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113292226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.4113292226
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3945450804
Short name T120
Test name
Test status
Simulation time 37252151 ps
CPU time 0.9 seconds
Started Feb 25 01:29:35 PM PST 24
Finished Feb 25 01:29:36 PM PST 24
Peak memory 215068 kb
Host smart-4bb45533-9a30-437b-b1da-2a77d5b76d45
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945450804 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3945450804
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.4010189296
Short name T86
Test name
Test status
Simulation time 63268587 ps
CPU time 1.02 seconds
Started Feb 25 01:29:29 PM PST 24
Finished Feb 25 01:29:31 PM PST 24
Peak memory 217120 kb
Host smart-9e95cd03-742a-44bf-ba71-a1e3cd8536cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010189296 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.4010189296
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.525833598
Short name T178
Test name
Test status
Simulation time 24889183 ps
CPU time 1.2 seconds
Started Feb 25 01:29:37 PM PST 24
Finished Feb 25 01:29:39 PM PST 24
Peak memory 219340 kb
Host smart-3c068415-00ea-439f-8274-448c78227a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525833598 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.525833598
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.601662127
Short name T775
Test name
Test status
Simulation time 27715352 ps
CPU time 1.12 seconds
Started Feb 25 01:29:22 PM PST 24
Finished Feb 25 01:29:24 PM PST 24
Peak memory 215920 kb
Host smart-5639a9e2-6b2b-4835-ae2e-376a35931c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601662127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.601662127
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.4129957784
Short name T620
Test name
Test status
Simulation time 37214744 ps
CPU time 0.87 seconds
Started Feb 25 01:29:33 PM PST 24
Finished Feb 25 01:29:34 PM PST 24
Peak memory 214780 kb
Host smart-fad44cfe-63e7-44f1-8779-a23038233047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129957784 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.4129957784
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.522275299
Short name T483
Test name
Test status
Simulation time 19937945 ps
CPU time 1 seconds
Started Feb 25 01:29:29 PM PST 24
Finished Feb 25 01:29:30 PM PST 24
Peak memory 214688 kb
Host smart-a2180991-ae97-4544-91c5-0520d3ae0969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522275299 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.522275299
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2572753694
Short name T448
Test name
Test status
Simulation time 154030326 ps
CPU time 1.42 seconds
Started Feb 25 01:29:37 PM PST 24
Finished Feb 25 01:29:39 PM PST 24
Peak memory 214632 kb
Host smart-06d5153b-5352-4e08-a304-1658232517e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572753694 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2572753694
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1402474871
Short name T200
Test name
Test status
Simulation time 81043828960 ps
CPU time 886.81 seconds
Started Feb 25 01:29:34 PM PST 24
Finished Feb 25 01:44:21 PM PST 24
Peak memory 220368 kb
Host smart-1b3129a2-616f-4e83-8d65-bc59aa4ddb4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402474871 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1402474871
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1544659888
Short name T655
Test name
Test status
Simulation time 98921575 ps
CPU time 2.88 seconds
Started Feb 25 01:31:30 PM PST 24
Finished Feb 25 01:31:33 PM PST 24
Peak memory 214692 kb
Host smart-1251d9b6-86e7-40f1-90ba-929875fa091b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544659888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1544659888
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3580825254
Short name T774
Test name
Test status
Simulation time 84208730 ps
CPU time 1.36 seconds
Started Feb 25 01:31:31 PM PST 24
Finished Feb 25 01:31:32 PM PST 24
Peak memory 217524 kb
Host smart-157847c6-dcd0-484d-b7b2-1011e8227b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580825254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3580825254
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3804194243
Short name T185
Test name
Test status
Simulation time 958300747 ps
CPU time 6.08 seconds
Started Feb 25 01:31:21 PM PST 24
Finished Feb 25 01:31:27 PM PST 24
Peak memory 218676 kb
Host smart-42463258-70ce-4087-81f4-7c8aeda70ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804194243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3804194243
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1344653857
Short name T790
Test name
Test status
Simulation time 44915568 ps
CPU time 1.54 seconds
Started Feb 25 01:31:30 PM PST 24
Finished Feb 25 01:31:32 PM PST 24
Peak memory 217172 kb
Host smart-44699136-1a9e-4965-b194-9ccb13e9d004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344653857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1344653857
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.7966831
Short name T716
Test name
Test status
Simulation time 260145559 ps
CPU time 3.5 seconds
Started Feb 25 01:31:21 PM PST 24
Finished Feb 25 01:31:25 PM PST 24
Peak memory 216144 kb
Host smart-ce831608-3e84-430c-b2f6-5b9eff2ad588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7966831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.7966831
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.1324271773
Short name T800
Test name
Test status
Simulation time 60423606 ps
CPU time 1.66 seconds
Started Feb 25 01:31:36 PM PST 24
Finished Feb 25 01:31:38 PM PST 24
Peak memory 217228 kb
Host smart-e333b2d6-bd91-4abc-9295-dc525580608e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324271773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.1324271773
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2555822711
Short name T437
Test name
Test status
Simulation time 182429488 ps
CPU time 3.18 seconds
Started Feb 25 01:31:31 PM PST 24
Finished Feb 25 01:31:34 PM PST 24
Peak memory 217268 kb
Host smart-d0102f54-e8bc-4f4a-86b9-a88ef7f5ec90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555822711 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2555822711
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.3170612271
Short name T571
Test name
Test status
Simulation time 41527939 ps
CPU time 1.77 seconds
Started Feb 25 01:31:35 PM PST 24
Finished Feb 25 01:31:37 PM PST 24
Peak memory 216124 kb
Host smart-84a92640-6f1d-4d6d-a53f-0385a066445f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170612271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3170612271
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3910285199
Short name T278
Test name
Test status
Simulation time 47503103 ps
CPU time 1.39 seconds
Started Feb 25 01:31:30 PM PST 24
Finished Feb 25 01:31:32 PM PST 24
Peak memory 216200 kb
Host smart-6a8e4fd3-b087-4d88-aea6-ce770e4fce6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910285199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3910285199
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.3853068582
Short name T827
Test name
Test status
Simulation time 185524636 ps
CPU time 0.98 seconds
Started Feb 25 01:31:37 PM PST 24
Finished Feb 25 01:31:39 PM PST 24
Peak memory 215960 kb
Host smart-97873f5e-2fc2-4e88-8850-331d7754dc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853068582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.3853068582
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.2850103263
Short name T148
Test name
Test status
Simulation time 59457485 ps
CPU time 1.2 seconds
Started Feb 25 01:29:35 PM PST 24
Finished Feb 25 01:29:36 PM PST 24
Peak memory 215060 kb
Host smart-ed55b603-4be8-4ae1-a033-5286c2affe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850103263 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2850103263
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.2361936505
Short name T306
Test name
Test status
Simulation time 32729304 ps
CPU time 0.84 seconds
Started Feb 25 01:29:33 PM PST 24
Finished Feb 25 01:29:34 PM PST 24
Peak memory 206104 kb
Host smart-86ae87b7-6955-417e-8f76-f29998e6c889
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361936505 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2361936505
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.2330972675
Short name T357
Test name
Test status
Simulation time 12038877 ps
CPU time 0.9 seconds
Started Feb 25 01:29:29 PM PST 24
Finished Feb 25 01:29:30 PM PST 24
Peak memory 215132 kb
Host smart-be108730-6846-4c65-a906-1bc5ec456d4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330972675 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2330972675
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.1556369938
Short name T47
Test name
Test status
Simulation time 29832516 ps
CPU time 1.38 seconds
Started Feb 25 01:29:37 PM PST 24
Finished Feb 25 01:29:38 PM PST 24
Peak memory 223508 kb
Host smart-c48f6544-e285-4b9e-b6ea-daf0ae300f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556369938 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.1556369938
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.212910405
Short name T427
Test name
Test status
Simulation time 43500787 ps
CPU time 1.75 seconds
Started Feb 25 01:29:34 PM PST 24
Finished Feb 25 01:29:36 PM PST 24
Peak memory 217104 kb
Host smart-48f8b64f-472c-41a1-9680-1e885191e936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212910405 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.212910405
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.2989003221
Short name T132
Test name
Test status
Simulation time 26684193 ps
CPU time 1.02 seconds
Started Feb 25 01:29:35 PM PST 24
Finished Feb 25 01:29:36 PM PST 24
Peak memory 215180 kb
Host smart-f40b0e3f-0074-4522-a672-262d74404888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989003221 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.2989003221
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.4162374865
Short name T663
Test name
Test status
Simulation time 24708131 ps
CPU time 0.94 seconds
Started Feb 25 01:29:37 PM PST 24
Finished Feb 25 01:29:38 PM PST 24
Peak memory 213784 kb
Host smart-9055fd10-ce6d-4900-8522-7f0f3448b94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162374865 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.4162374865
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2111553012
Short name T563
Test name
Test status
Simulation time 104042631 ps
CPU time 1.19 seconds
Started Feb 25 01:29:37 PM PST 24
Finished Feb 25 01:29:38 PM PST 24
Peak memory 206576 kb
Host smart-b2f655a3-f9d6-4b1f-88ed-91cc27c26675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111553012 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2111553012
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.399115246
Short name T20
Test name
Test status
Simulation time 71232758554 ps
CPU time 459.43 seconds
Started Feb 25 01:29:36 PM PST 24
Finished Feb 25 01:37:15 PM PST 24
Peak memory 217592 kb
Host smart-8573c91f-1de4-4235-aed0-fc1fb40d550f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399115246 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.399115246
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3455209192
Short name T725
Test name
Test status
Simulation time 145088197 ps
CPU time 0.96 seconds
Started Feb 25 01:31:33 PM PST 24
Finished Feb 25 01:31:34 PM PST 24
Peak memory 215812 kb
Host smart-660781d1-4e3b-4d5c-ad77-0916d2b44eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455209192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3455209192
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.2703282604
Short name T791
Test name
Test status
Simulation time 89921647 ps
CPU time 1.45 seconds
Started Feb 25 01:31:20 PM PST 24
Finished Feb 25 01:31:21 PM PST 24
Peak memory 216416 kb
Host smart-e40ba409-6199-4db9-b845-b69a6283fb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703282604 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.2703282604
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.3559308999
Short name T551
Test name
Test status
Simulation time 67259453 ps
CPU time 1.07 seconds
Started Feb 25 01:31:36 PM PST 24
Finished Feb 25 01:31:38 PM PST 24
Peak memory 214656 kb
Host smart-3ad64df6-4154-4c92-80b6-e43c4f830db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559308999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.3559308999
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.33658712
Short name T708
Test name
Test status
Simulation time 32933469 ps
CPU time 1.32 seconds
Started Feb 25 01:31:18 PM PST 24
Finished Feb 25 01:31:20 PM PST 24
Peak memory 217168 kb
Host smart-ea6c23c9-2e4e-4785-959b-a10e1ef333ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33658712 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.33658712
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.486900064
Short name T645
Test name
Test status
Simulation time 48049431 ps
CPU time 1.19 seconds
Started Feb 25 01:31:31 PM PST 24
Finished Feb 25 01:31:32 PM PST 24
Peak memory 218332 kb
Host smart-d68d494a-c2c0-43fc-89c5-7314746d9fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486900064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.486900064
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1958458574
Short name T651
Test name
Test status
Simulation time 114880281 ps
CPU time 1.32 seconds
Started Feb 25 01:31:20 PM PST 24
Finished Feb 25 01:31:21 PM PST 24
Peak memory 216076 kb
Host smart-86cf8e89-a33a-434a-971f-555f214188f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958458574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1958458574
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.4090881776
Short name T680
Test name
Test status
Simulation time 55588986 ps
CPU time 1.46 seconds
Started Feb 25 01:31:19 PM PST 24
Finished Feb 25 01:31:20 PM PST 24
Peak memory 217364 kb
Host smart-98183889-236d-4da7-8ae0-fb31dc297d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090881776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.4090881776
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.40025198
Short name T340
Test name
Test status
Simulation time 119669775 ps
CPU time 1.06 seconds
Started Feb 25 01:31:20 PM PST 24
Finished Feb 25 01:31:21 PM PST 24
Peak memory 216052 kb
Host smart-3389521a-aed5-4964-90c8-6c12f66210f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40025198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.40025198
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1589349134
Short name T18
Test name
Test status
Simulation time 42980977 ps
CPU time 1.36 seconds
Started Feb 25 01:31:31 PM PST 24
Finished Feb 25 01:31:32 PM PST 24
Peak memory 215924 kb
Host smart-098b8a92-fc3a-44f3-aac6-16a02e09164d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589349134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1589349134
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1945464284
Short name T691
Test name
Test status
Simulation time 47056208 ps
CPU time 1.9 seconds
Started Feb 25 01:31:28 PM PST 24
Finished Feb 25 01:31:30 PM PST 24
Peak memory 217420 kb
Host smart-fea368c1-4012-4f91-8838-00911c6b01d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945464284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1945464284
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.4041910413
Short name T794
Test name
Test status
Simulation time 30811277 ps
CPU time 1.37 seconds
Started Feb 25 01:29:34 PM PST 24
Finished Feb 25 01:29:36 PM PST 24
Peak memory 215068 kb
Host smart-a3260b48-3f30-4700-877e-c3c313bd1a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041910413 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.4041910413
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.656684950
Short name T470
Test name
Test status
Simulation time 40135039 ps
CPU time 1.03 seconds
Started Feb 25 01:29:36 PM PST 24
Finished Feb 25 01:29:37 PM PST 24
Peak memory 206264 kb
Host smart-a582658a-8ed7-4bbd-860c-5aa09ef868a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656684950 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.656684950
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_err.4032851446
Short name T608
Test name
Test status
Simulation time 19234382 ps
CPU time 1.09 seconds
Started Feb 25 01:29:36 PM PST 24
Finished Feb 25 01:29:37 PM PST 24
Peak memory 222440 kb
Host smart-182d0f1e-8ad5-4c77-a0ae-1ef07e8bcbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032851446 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.4032851446
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2109888862
Short name T359
Test name
Test status
Simulation time 46408181 ps
CPU time 1.67 seconds
Started Feb 25 01:29:37 PM PST 24
Finished Feb 25 01:29:39 PM PST 24
Peak memory 217040 kb
Host smart-b5f1ccb3-ec31-4da3-b605-4a11395d3253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109888862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2109888862
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.274464098
Short name T136
Test name
Test status
Simulation time 66600838 ps
CPU time 0.81 seconds
Started Feb 25 01:29:33 PM PST 24
Finished Feb 25 01:29:34 PM PST 24
Peak memory 214964 kb
Host smart-5d2d5a18-624e-4fef-9ad5-f9374a167a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274464098 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.274464098
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.3258239305
Short name T518
Test name
Test status
Simulation time 17330892 ps
CPU time 1 seconds
Started Feb 25 01:29:34 PM PST 24
Finished Feb 25 01:29:35 PM PST 24
Peak memory 214608 kb
Host smart-46b2b4cc-9a3a-46f0-bf55-eb15c195a226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258239305 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.3258239305
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3775172629
Short name T316
Test name
Test status
Simulation time 265309351 ps
CPU time 5.27 seconds
Started Feb 25 01:29:35 PM PST 24
Finished Feb 25 01:29:40 PM PST 24
Peak memory 215776 kb
Host smart-70ff060c-b800-4282-ab22-80276fea40a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775172629 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3775172629
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1046584658
Short name T194
Test name
Test status
Simulation time 79703386806 ps
CPU time 1055.37 seconds
Started Feb 25 01:29:36 PM PST 24
Finished Feb 25 01:47:11 PM PST 24
Peak memory 221840 kb
Host smart-3811880b-a02d-4404-ae8d-025441ae6e27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046584658 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1046584658
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.2565787428
Short name T274
Test name
Test status
Simulation time 345716223 ps
CPU time 1.25 seconds
Started Feb 25 01:31:21 PM PST 24
Finished Feb 25 01:31:24 PM PST 24
Peak memory 216076 kb
Host smart-028e4d6e-e3ef-4828-be38-a152c3461d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565787428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2565787428
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.2472110493
Short name T583
Test name
Test status
Simulation time 115046470 ps
CPU time 1.65 seconds
Started Feb 25 01:31:20 PM PST 24
Finished Feb 25 01:31:22 PM PST 24
Peak memory 217492 kb
Host smart-473e9802-38e9-4ca4-91d8-dba2f05a7755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472110493 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2472110493
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3861217622
Short name T247
Test name
Test status
Simulation time 73771790 ps
CPU time 1.73 seconds
Started Feb 25 01:31:31 PM PST 24
Finished Feb 25 01:31:33 PM PST 24
Peak memory 216096 kb
Host smart-a58a07b0-9789-4fbb-94d9-813da1fc3481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861217622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3861217622
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.615245191
Short name T301
Test name
Test status
Simulation time 50598809 ps
CPU time 1.22 seconds
Started Feb 25 01:31:33 PM PST 24
Finished Feb 25 01:31:35 PM PST 24
Peak memory 216124 kb
Host smart-fc339262-73a3-4054-9f6e-ced29b5f21c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615245191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.615245191
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.1105318595
Short name T458
Test name
Test status
Simulation time 123543789 ps
CPU time 1.08 seconds
Started Feb 25 01:31:21 PM PST 24
Finished Feb 25 01:31:22 PM PST 24
Peak memory 215868 kb
Host smart-8db4f413-5987-4a66-be4e-53fcc06d061d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105318595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.1105318595
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.835254815
Short name T527
Test name
Test status
Simulation time 34602992 ps
CPU time 1.53 seconds
Started Feb 25 01:31:19 PM PST 24
Finished Feb 25 01:31:20 PM PST 24
Peak memory 217200 kb
Host smart-aa7d85f4-5af0-47db-9891-145fac9eaac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835254815 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.835254815
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.3545555548
Short name T312
Test name
Test status
Simulation time 46287504 ps
CPU time 1.13 seconds
Started Feb 25 01:31:27 PM PST 24
Finished Feb 25 01:31:28 PM PST 24
Peak memory 216172 kb
Host smart-9e59c8cf-f171-4038-b165-a02c3636c479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545555548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.3545555548
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.3025936447
Short name T328
Test name
Test status
Simulation time 133919148 ps
CPU time 1.47 seconds
Started Feb 25 01:31:34 PM PST 24
Finished Feb 25 01:31:35 PM PST 24
Peak memory 217544 kb
Host smart-51936eae-ca4b-471e-926c-cbfde3d6b763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025936447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.3025936447
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.899935768
Short name T726
Test name
Test status
Simulation time 38892432 ps
CPU time 1.47 seconds
Started Feb 25 01:31:30 PM PST 24
Finished Feb 25 01:31:32 PM PST 24
Peak memory 216892 kb
Host smart-a9a1b804-504e-4f30-869e-0366ad512455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899935768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.899935768
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.728239213
Short name T123
Test name
Test status
Simulation time 41935848 ps
CPU time 1.18 seconds
Started Feb 25 01:29:36 PM PST 24
Finished Feb 25 01:29:37 PM PST 24
Peak memory 215056 kb
Host smart-114765bb-8a38-4d29-8541-8e4e43589e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728239213 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.728239213
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2460936846
Short name T154
Test name
Test status
Simulation time 36835683 ps
CPU time 0.83 seconds
Started Feb 25 01:29:39 PM PST 24
Finished Feb 25 01:29:40 PM PST 24
Peak memory 204700 kb
Host smart-0aa60bd1-fe68-40f7-8aa7-d84f73a14f41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460936846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2460936846
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.175070370
Short name T34
Test name
Test status
Simulation time 12304322 ps
CPU time 0.96 seconds
Started Feb 25 01:29:40 PM PST 24
Finished Feb 25 01:29:41 PM PST 24
Peak memory 215052 kb
Host smart-b8dc2c05-3e68-49da-aad4-5581d73a26bf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175070370 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.175070370
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.1199121470
Short name T580
Test name
Test status
Simulation time 26385275 ps
CPU time 1.07 seconds
Started Feb 25 01:29:53 PM PST 24
Finished Feb 25 01:29:55 PM PST 24
Peak memory 216864 kb
Host smart-9ebf39f6-7efe-47c5-80c0-fdff409c477d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199121470 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_d
isable_auto_req_mode.1199121470
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.1796589814
Short name T467
Test name
Test status
Simulation time 24787692 ps
CPU time 1.1 seconds
Started Feb 25 01:29:40 PM PST 24
Finished Feb 25 01:29:41 PM PST 24
Peak memory 217308 kb
Host smart-21a82514-4f9c-45fe-8564-bb09db39edb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796589814 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1796589814
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.912536027
Short name T789
Test name
Test status
Simulation time 399877443 ps
CPU time 1.43 seconds
Started Feb 25 01:29:35 PM PST 24
Finished Feb 25 01:29:36 PM PST 24
Peak memory 218352 kb
Host smart-6978421a-83ac-4e07-aa5f-055892b13629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912536027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.912536027
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.2568860669
Short name T723
Test name
Test status
Simulation time 28986149 ps
CPU time 1.08 seconds
Started Feb 25 01:29:33 PM PST 24
Finished Feb 25 01:29:35 PM PST 24
Peak memory 222480 kb
Host smart-f3e4b3eb-950e-4955-b119-39f4ca50fc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568860669 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.2568860669
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1706967360
Short name T649
Test name
Test status
Simulation time 17819543 ps
CPU time 0.94 seconds
Started Feb 25 01:29:35 PM PST 24
Finished Feb 25 01:29:36 PM PST 24
Peak memory 214672 kb
Host smart-060ae082-11a1-43c3-8935-189852322ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706967360 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1706967360
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.4117869082
Short name T731
Test name
Test status
Simulation time 909818836 ps
CPU time 5.04 seconds
Started Feb 25 01:29:36 PM PST 24
Finished Feb 25 01:29:41 PM PST 24
Peak memory 214784 kb
Host smart-4edee001-1f25-48c4-b0f5-7ff0b2c7dcf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117869082 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.4117869082
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.644917136
Short name T201
Test name
Test status
Simulation time 88320135968 ps
CPU time 944.88 seconds
Started Feb 25 01:29:37 PM PST 24
Finished Feb 25 01:45:22 PM PST 24
Peak memory 219652 kb
Host smart-1bed3aa4-d254-4fc2-99ca-f3c878c18e0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644917136 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.644917136
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1408529921
Short name T592
Test name
Test status
Simulation time 82577886 ps
CPU time 1.35 seconds
Started Feb 25 01:31:32 PM PST 24
Finished Feb 25 01:31:33 PM PST 24
Peak memory 218856 kb
Host smart-bf00a0e0-fd84-4aeb-b52a-ca22f8d2b2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408529921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1408529921
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2201250506
Short name T327
Test name
Test status
Simulation time 122175264 ps
CPU time 1.82 seconds
Started Feb 25 01:31:36 PM PST 24
Finished Feb 25 01:31:38 PM PST 24
Peak memory 218144 kb
Host smart-a4b88a22-b3b6-4500-aa3f-d68d09d96719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201250506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2201250506
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1465656771
Short name T724
Test name
Test status
Simulation time 57147900 ps
CPU time 1.16 seconds
Started Feb 25 01:31:34 PM PST 24
Finished Feb 25 01:31:36 PM PST 24
Peak memory 216012 kb
Host smart-64c9fbe1-58c8-45e8-8d10-96440e5f1f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465656771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1465656771
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.315606278
Short name T259
Test name
Test status
Simulation time 78892510 ps
CPU time 1.12 seconds
Started Feb 25 01:31:48 PM PST 24
Finished Feb 25 01:31:52 PM PST 24
Peak memory 215996 kb
Host smart-2912e54e-b783-4734-a692-371d8f067141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315606278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.315606278
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.182623103
Short name T814
Test name
Test status
Simulation time 40946865 ps
CPU time 1.39 seconds
Started Feb 25 01:31:30 PM PST 24
Finished Feb 25 01:31:31 PM PST 24
Peak memory 217176 kb
Host smart-4f8f6340-061b-4cb0-a727-8c0404abfad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182623103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.182623103
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.1075408428
Short name T692
Test name
Test status
Simulation time 82714532 ps
CPU time 1.32 seconds
Started Feb 25 01:31:34 PM PST 24
Finished Feb 25 01:31:35 PM PST 24
Peak memory 216420 kb
Host smart-269d09f1-a6c9-421f-8d7d-55e63f1a4705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075408428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.1075408428
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1757906623
Short name T244
Test name
Test status
Simulation time 52937681 ps
CPU time 0.96 seconds
Started Feb 25 01:31:30 PM PST 24
Finished Feb 25 01:31:31 PM PST 24
Peak memory 215968 kb
Host smart-64a5d1fd-97a8-445c-ab0f-3b845b38b593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757906623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1757906623
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2875124800
Short name T636
Test name
Test status
Simulation time 75693973 ps
CPU time 1.44 seconds
Started Feb 25 01:31:37 PM PST 24
Finished Feb 25 01:31:38 PM PST 24
Peak memory 217236 kb
Host smart-23bd61fc-85ba-4bcc-834c-64b063d87e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875124800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2875124800
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.3739274984
Short name T805
Test name
Test status
Simulation time 39847075 ps
CPU time 1.51 seconds
Started Feb 25 01:31:31 PM PST 24
Finished Feb 25 01:31:32 PM PST 24
Peak memory 218752 kb
Host smart-461b2a6d-4eb3-4635-adbe-8c2c5f489259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739274984 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.3739274984
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2135842651
Short name T683
Test name
Test status
Simulation time 38038061 ps
CPU time 1.44 seconds
Started Feb 25 01:31:36 PM PST 24
Finished Feb 25 01:31:38 PM PST 24
Peak memory 217112 kb
Host smart-0a1c8942-f244-45d3-83d3-7a9fd8c47a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135842651 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2135842651
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.910531147
Short name T746
Test name
Test status
Simulation time 300674916 ps
CPU time 1.23 seconds
Started Feb 25 01:29:38 PM PST 24
Finished Feb 25 01:29:40 PM PST 24
Peak memory 215108 kb
Host smart-5f970729-af2f-4af7-b66b-8b24bbae6a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910531147 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.910531147
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1242312597
Short name T153
Test name
Test status
Simulation time 31222269 ps
CPU time 0.95 seconds
Started Feb 25 01:29:38 PM PST 24
Finished Feb 25 01:29:39 PM PST 24
Peak memory 206420 kb
Host smart-dce00316-51f3-4983-bd80-6cd67c1d0f8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242312597 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1242312597
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.3818526552
Short name T686
Test name
Test status
Simulation time 22567664 ps
CPU time 0.91 seconds
Started Feb 25 01:29:48 PM PST 24
Finished Feb 25 01:29:49 PM PST 24
Peak memory 214792 kb
Host smart-4a39b959-f0de-47c8-a276-8bc2df8c182a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818526552 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3818526552
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2273765947
Short name T71
Test name
Test status
Simulation time 49132037 ps
CPU time 0.99 seconds
Started Feb 25 01:29:39 PM PST 24
Finished Feb 25 01:29:40 PM PST 24
Peak memory 216036 kb
Host smart-7fd4a55a-082f-43dd-8698-f16711b6866f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273765947 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2273765947
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.687537569
Short name T621
Test name
Test status
Simulation time 34108995 ps
CPU time 0.84 seconds
Started Feb 25 01:29:38 PM PST 24
Finished Feb 25 01:29:39 PM PST 24
Peak memory 217008 kb
Host smart-1162db3b-c581-4722-a756-9753c97cf498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687537569 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.687537569
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.1471837127
Short name T378
Test name
Test status
Simulation time 57779707 ps
CPU time 1.36 seconds
Started Feb 25 01:29:39 PM PST 24
Finished Feb 25 01:29:41 PM PST 24
Peak memory 216000 kb
Host smart-18824682-08ad-4728-9f40-29fc50a6c1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471837127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1471837127
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.259185573
Short name T652
Test name
Test status
Simulation time 36136979 ps
CPU time 0.95 seconds
Started Feb 25 01:29:41 PM PST 24
Finished Feb 25 01:29:42 PM PST 24
Peak memory 222408 kb
Host smart-cf4df040-08ae-4b52-b4b3-46d64f0a8d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259185573 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.259185573
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2036891980
Short name T304
Test name
Test status
Simulation time 168634313 ps
CPU time 0.86 seconds
Started Feb 25 01:29:38 PM PST 24
Finished Feb 25 01:29:39 PM PST 24
Peak memory 214524 kb
Host smart-cdb16d25-dd04-432a-9e92-2369c0ae63c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036891980 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2036891980
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3232387168
Short name T42
Test name
Test status
Simulation time 513253837 ps
CPU time 5.15 seconds
Started Feb 25 01:29:39 PM PST 24
Finished Feb 25 01:29:45 PM PST 24
Peak memory 214824 kb
Host smart-8df01508-96b0-4295-bfde-c3f7cc21c29d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232387168 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3232387168
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3624767891
Short name T562
Test name
Test status
Simulation time 28611698151 ps
CPU time 333.03 seconds
Started Feb 25 01:29:41 PM PST 24
Finished Feb 25 01:35:14 PM PST 24
Peak memory 217120 kb
Host smart-b4c11fb0-023b-4c23-9b70-901c45933acf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624767891 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3624767891
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1587691499
Short name T743
Test name
Test status
Simulation time 130813506 ps
CPU time 1.76 seconds
Started Feb 25 01:31:31 PM PST 24
Finished Feb 25 01:31:33 PM PST 24
Peak memory 217044 kb
Host smart-5664b988-dae8-46f6-b941-e8b2f0181c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587691499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1587691499
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.4221915436
Short name T828
Test name
Test status
Simulation time 148119043 ps
CPU time 1.15 seconds
Started Feb 25 01:31:34 PM PST 24
Finished Feb 25 01:31:35 PM PST 24
Peak memory 216164 kb
Host smart-13d41085-6cc2-4f34-8c8a-5bb800502006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221915436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.4221915436
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.606643560
Short name T400
Test name
Test status
Simulation time 29502503 ps
CPU time 1.4 seconds
Started Feb 25 01:31:35 PM PST 24
Finished Feb 25 01:31:36 PM PST 24
Peak memory 216068 kb
Host smart-6e19908c-7e48-46ea-849f-a8c6e7d9859f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606643560 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.606643560
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3192426106
Short name T634
Test name
Test status
Simulation time 82062396 ps
CPU time 1.29 seconds
Started Feb 25 01:31:33 PM PST 24
Finished Feb 25 01:31:35 PM PST 24
Peak memory 217324 kb
Host smart-c4a4ad4e-a160-487b-8294-7adc243de3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192426106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3192426106
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.3194337346
Short name T816
Test name
Test status
Simulation time 125547256 ps
CPU time 1.66 seconds
Started Feb 25 01:31:33 PM PST 24
Finished Feb 25 01:31:35 PM PST 24
Peak memory 217064 kb
Host smart-7c762005-58ad-4e6c-b131-61cfa36818fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194337346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.3194337346
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1992079417
Short name T670
Test name
Test status
Simulation time 83154238 ps
CPU time 1.49 seconds
Started Feb 25 01:31:33 PM PST 24
Finished Feb 25 01:31:35 PM PST 24
Peak memory 217344 kb
Host smart-0f47ee8e-677d-49ee-8766-cf49e134ec68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992079417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1992079417
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.1069835603
Short name T560
Test name
Test status
Simulation time 52602621 ps
CPU time 1.43 seconds
Started Feb 25 01:31:33 PM PST 24
Finished Feb 25 01:31:35 PM PST 24
Peak memory 217452 kb
Host smart-ad176e1c-8e9f-4d0c-b314-92f21d4812a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069835603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.1069835603
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2226062684
Short name T597
Test name
Test status
Simulation time 33257631 ps
CPU time 1.26 seconds
Started Feb 25 01:31:35 PM PST 24
Finished Feb 25 01:31:36 PM PST 24
Peak memory 217304 kb
Host smart-fb4bf320-8e91-4f61-98fb-a668e1fe668d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226062684 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2226062684
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.3593157417
Short name T793
Test name
Test status
Simulation time 65998148 ps
CPU time 1.34 seconds
Started Feb 25 01:31:37 PM PST 24
Finished Feb 25 01:31:39 PM PST 24
Peak memory 217948 kb
Host smart-f09928cb-c074-44b8-9c36-9521cd4d66e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593157417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.3593157417
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2482483738
Short name T667
Test name
Test status
Simulation time 167494941 ps
CPU time 2.19 seconds
Started Feb 25 01:31:33 PM PST 24
Finished Feb 25 01:31:36 PM PST 24
Peak memory 218316 kb
Host smart-caf12aad-eafa-48fd-a65d-57304010dd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482483738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2482483738
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert_test.481395888
Short name T689
Test name
Test status
Simulation time 70249556 ps
CPU time 0.94 seconds
Started Feb 25 01:29:38 PM PST 24
Finished Feb 25 01:29:39 PM PST 24
Peak memory 205972 kb
Host smart-91a15329-1afa-4cc0-b30b-4ffcc097ca45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481395888 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.481395888
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.1198387076
Short name T171
Test name
Test status
Simulation time 30251806 ps
CPU time 0.83 seconds
Started Feb 25 01:29:38 PM PST 24
Finished Feb 25 01:29:39 PM PST 24
Peak memory 215076 kb
Host smart-40f80631-a1e5-4b95-becb-ed8f8bbab9c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198387076 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.1198387076
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1331505596
Short name T750
Test name
Test status
Simulation time 54506142 ps
CPU time 1.05 seconds
Started Feb 25 01:29:37 PM PST 24
Finished Feb 25 01:29:39 PM PST 24
Peak memory 215680 kb
Host smart-80c047b9-f5dc-4a2c-a4a2-829e43ec9db3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331505596 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1331505596
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2053869961
Short name T824
Test name
Test status
Simulation time 19948602 ps
CPU time 1.11 seconds
Started Feb 25 01:29:48 PM PST 24
Finished Feb 25 01:29:49 PM PST 24
Peak memory 217392 kb
Host smart-4a44d651-e6a3-4ec5-a6cc-bcec5b3eb703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053869961 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2053869961
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.4060411946
Short name T383
Test name
Test status
Simulation time 54233972 ps
CPU time 1.88 seconds
Started Feb 25 01:29:40 PM PST 24
Finished Feb 25 01:29:42 PM PST 24
Peak memory 217196 kb
Host smart-8b878eac-ad75-4b1d-842e-1d750107204d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060411946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.4060411946
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.864688550
Short name T766
Test name
Test status
Simulation time 36458461 ps
CPU time 0.87 seconds
Started Feb 25 01:29:49 PM PST 24
Finished Feb 25 01:29:51 PM PST 24
Peak memory 214968 kb
Host smart-31908fa4-701c-42c3-8cef-44979b0b176a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864688550 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.864688550
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1944945080
Short name T214
Test name
Test status
Simulation time 52339466 ps
CPU time 0.93 seconds
Started Feb 25 01:29:45 PM PST 24
Finished Feb 25 01:29:46 PM PST 24
Peak memory 206496 kb
Host smart-2821001b-94ec-4ea1-93d5-204200763a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944945080 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1944945080
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.874945229
Short name T215
Test name
Test status
Simulation time 597287328 ps
CPU time 6.56 seconds
Started Feb 25 01:29:38 PM PST 24
Finished Feb 25 01:29:45 PM PST 24
Peak memory 214736 kb
Host smart-0667ba39-19ba-42dc-ba14-0bbc308f2ed3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874945229 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.874945229
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.4256941404
Short name T710
Test name
Test status
Simulation time 69912795552 ps
CPU time 1664.47 seconds
Started Feb 25 01:29:40 PM PST 24
Finished Feb 25 01:57:25 PM PST 24
Peak memory 225764 kb
Host smart-602acc2e-01cf-4690-80d8-2404171a7922
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256941404 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.4256941404
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.3446711619
Short name T280
Test name
Test status
Simulation time 42137239 ps
CPU time 1.58 seconds
Started Feb 25 01:31:35 PM PST 24
Finished Feb 25 01:31:37 PM PST 24
Peak memory 217236 kb
Host smart-7df11ac1-1ea9-4b43-8e60-5579edc3124f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446711619 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.3446711619
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2446888220
Short name T7
Test name
Test status
Simulation time 40339356 ps
CPU time 1.47 seconds
Started Feb 25 01:31:32 PM PST 24
Finished Feb 25 01:31:34 PM PST 24
Peak memory 216356 kb
Host smart-63743601-dae3-41ef-b74f-be4859819fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446888220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2446888220
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.918129146
Short name T535
Test name
Test status
Simulation time 34942370 ps
CPU time 1.43 seconds
Started Feb 25 01:31:33 PM PST 24
Finished Feb 25 01:31:34 PM PST 24
Peak memory 216392 kb
Host smart-e46dea19-f9f7-4b52-a340-609f71a88a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918129146 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.918129146
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.771213479
Short name T590
Test name
Test status
Simulation time 57402566 ps
CPU time 1.24 seconds
Started Feb 25 01:31:29 PM PST 24
Finished Feb 25 01:31:31 PM PST 24
Peak memory 216200 kb
Host smart-0143b2c5-a930-4569-8449-5ae401d4fea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771213479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.771213479
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.595288022
Short name T709
Test name
Test status
Simulation time 101126765 ps
CPU time 1.31 seconds
Started Feb 25 01:31:31 PM PST 24
Finished Feb 25 01:31:33 PM PST 24
Peak memory 218560 kb
Host smart-5451f1fc-4e93-46be-8352-c8502eb6f1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595288022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.595288022
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.4158460707
Short name T275
Test name
Test status
Simulation time 209857673 ps
CPU time 3.24 seconds
Started Feb 25 01:31:35 PM PST 24
Finished Feb 25 01:31:38 PM PST 24
Peak memory 217696 kb
Host smart-05500883-6432-4812-8a43-2344b772acd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158460707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.4158460707
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.563330290
Short name T423
Test name
Test status
Simulation time 53375760 ps
CPU time 1.15 seconds
Started Feb 25 01:31:35 PM PST 24
Finished Feb 25 01:31:36 PM PST 24
Peak memory 217128 kb
Host smart-5bb1fcbd-1544-4989-b5fe-9e407b21c5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563330290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.563330290
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.2664705135
Short name T654
Test name
Test status
Simulation time 42143789 ps
CPU time 1.41 seconds
Started Feb 25 01:31:33 PM PST 24
Finished Feb 25 01:31:35 PM PST 24
Peak memory 217104 kb
Host smart-484a3665-2ad8-47bc-8b3c-f34b89fadf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664705135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.2664705135
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.246976323
Short name T8
Test name
Test status
Simulation time 135126676 ps
CPU time 2.97 seconds
Started Feb 25 01:31:34 PM PST 24
Finished Feb 25 01:31:37 PM PST 24
Peak memory 218560 kb
Host smart-024a9774-9588-45cd-b6ed-91a3ee8a1896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246976323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.246976323
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1650772259
Short name T559
Test name
Test status
Simulation time 41720550 ps
CPU time 1.64 seconds
Started Feb 25 01:31:29 PM PST 24
Finished Feb 25 01:31:31 PM PST 24
Peak memory 217176 kb
Host smart-074abcd8-9a92-456e-9deb-c7b78775a49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650772259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1650772259
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.166724013
Short name T293
Test name
Test status
Simulation time 164630497 ps
CPU time 1.25 seconds
Started Feb 25 01:28:44 PM PST 24
Finished Feb 25 01:28:45 PM PST 24
Peak memory 214224 kb
Host smart-c06f83d9-2641-48a2-b402-487b9c93e2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166724013 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.166724013
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2039645511
Short name T815
Test name
Test status
Simulation time 27809758 ps
CPU time 1.21 seconds
Started Feb 25 01:28:46 PM PST 24
Finished Feb 25 01:28:48 PM PST 24
Peak memory 206288 kb
Host smart-afe4bb06-102d-48ae-a8d4-154646911d19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039645511 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2039645511
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.594423765
Short name T569
Test name
Test status
Simulation time 78265669 ps
CPU time 1.11 seconds
Started Feb 25 01:28:44 PM PST 24
Finished Feb 25 01:28:45 PM PST 24
Peak memory 214708 kb
Host smart-60fea7c6-ce99-4e0f-88f6-21eca089f3a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594423765 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.594423765
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1529010122
Short name T88
Test name
Test status
Simulation time 137013978 ps
CPU time 1.04 seconds
Started Feb 25 01:28:50 PM PST 24
Finished Feb 25 01:28:51 PM PST 24
Peak memory 217328 kb
Host smart-3653ca28-f0a7-488b-9571-330abd443448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529010122 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1529010122
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1408510004
Short name T618
Test name
Test status
Simulation time 97099852 ps
CPU time 1.13 seconds
Started Feb 25 01:28:44 PM PST 24
Finished Feb 25 01:28:45 PM PST 24
Peak memory 216136 kb
Host smart-2c1d4218-4fde-425e-9d23-62f780cea4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408510004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1408510004
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.294882741
Short name T801
Test name
Test status
Simulation time 19914156 ps
CPU time 1.09 seconds
Started Feb 25 01:28:43 PM PST 24
Finished Feb 25 01:28:44 PM PST 24
Peak memory 215152 kb
Host smart-71305964-6b0f-4c82-b748-3e773cf1fe6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294882741 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.294882741
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_sec_cm.161227562
Short name T53
Test name
Test status
Simulation time 733481837 ps
CPU time 3.6 seconds
Started Feb 25 01:28:41 PM PST 24
Finished Feb 25 01:28:45 PM PST 24
Peak memory 235188 kb
Host smart-51fcc9a5-6ea4-4e03-8f7a-3f463f25a616
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161227562 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.161227562
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.223706948
Short name T452
Test name
Test status
Simulation time 81336707 ps
CPU time 0.9 seconds
Started Feb 25 01:28:42 PM PST 24
Finished Feb 25 01:28:44 PM PST 24
Peak memory 214700 kb
Host smart-1874edc7-896c-4cda-bf5e-e296d3f338d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223706948 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.223706948
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.178134330
Short name T646
Test name
Test status
Simulation time 1258238830 ps
CPU time 5.03 seconds
Started Feb 25 01:28:41 PM PST 24
Finished Feb 25 01:28:46 PM PST 24
Peak memory 215908 kb
Host smart-83704ba6-6bdd-4b33-8ec9-542d9a0059cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178134330 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.178134330
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3622015102
Short name T591
Test name
Test status
Simulation time 159045934437 ps
CPU time 1804.71 seconds
Started Feb 25 01:28:43 PM PST 24
Finished Feb 25 01:58:48 PM PST 24
Peak memory 224176 kb
Host smart-b6aaa0bc-32ca-41e1-a46f-bbc6ce64c6be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622015102 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3622015102
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.2841620860
Short name T296
Test name
Test status
Simulation time 25281076 ps
CPU time 1.3 seconds
Started Feb 25 01:29:53 PM PST 24
Finished Feb 25 01:29:55 PM PST 24
Peak memory 215108 kb
Host smart-61a89e59-3637-4ad6-9082-07c0e05ab00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841620860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2841620860
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.161578006
Short name T602
Test name
Test status
Simulation time 81396109 ps
CPU time 0.91 seconds
Started Feb 25 01:29:56 PM PST 24
Finished Feb 25 01:29:57 PM PST 24
Peak memory 205904 kb
Host smart-19a01fa9-a390-49a1-89ac-484abba8d4c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161578006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.161578006
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.4068081988
Short name T176
Test name
Test status
Simulation time 18011457 ps
CPU time 0.89 seconds
Started Feb 25 01:29:58 PM PST 24
Finished Feb 25 01:29:59 PM PST 24
Peak memory 215104 kb
Host smart-a9ea4d78-2931-4e64-a8b9-4ca009249f52
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068081988 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.4068081988
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.3050566675
Short name T165
Test name
Test status
Simulation time 46346925 ps
CPU time 1.03 seconds
Started Feb 25 01:29:53 PM PST 24
Finished Feb 25 01:29:55 PM PST 24
Peak memory 215968 kb
Host smart-a5fa77bb-8c18-41ac-a051-b955eb7fd28a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050566675 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.3050566675
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.693002291
Short name T627
Test name
Test status
Simulation time 29380180 ps
CPU time 0.94 seconds
Started Feb 25 01:29:56 PM PST 24
Finished Feb 25 01:29:57 PM PST 24
Peak memory 216820 kb
Host smart-7a792b8a-1f64-4ae5-9384-241fbbb0b832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693002291 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.693002291
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2145025630
Short name T463
Test name
Test status
Simulation time 78263721 ps
CPU time 2.28 seconds
Started Feb 25 01:29:49 PM PST 24
Finished Feb 25 01:29:51 PM PST 24
Peak memory 218800 kb
Host smart-ac70126e-d2fa-4362-87fe-70437add244a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145025630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2145025630
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.3126746800
Short name T393
Test name
Test status
Simulation time 40548286 ps
CPU time 0.99 seconds
Started Feb 25 01:29:46 PM PST 24
Finished Feb 25 01:29:47 PM PST 24
Peak memory 214860 kb
Host smart-a7bc5812-9e07-43bb-82fc-5066d3dc10d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126746800 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.3126746800
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.1220962963
Short name T394
Test name
Test status
Simulation time 27616637 ps
CPU time 0.95 seconds
Started Feb 25 01:29:45 PM PST 24
Finished Feb 25 01:29:46 PM PST 24
Peak memory 214732 kb
Host smart-9da055d3-d4d3-4c1f-b44c-e12108959ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220962963 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.1220962963
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.3238198316
Short name T631
Test name
Test status
Simulation time 282331359 ps
CPU time 3.1 seconds
Started Feb 25 01:29:38 PM PST 24
Finished Feb 25 01:29:41 PM PST 24
Peak memory 214704 kb
Host smart-ef336cd7-6dd8-411e-af81-e210bf1c0f8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238198316 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.3238198316
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.113297823
Short name T204
Test name
Test status
Simulation time 180730842175 ps
CPU time 1586.33 seconds
Started Feb 25 01:29:45 PM PST 24
Finished Feb 25 01:56:12 PM PST 24
Peak memory 222076 kb
Host smart-a6cc6a1e-1301-46db-baf9-6317f898e55d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113297823 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.113297823
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1910367739
Short name T122
Test name
Test status
Simulation time 98833851 ps
CPU time 1.2 seconds
Started Feb 25 01:29:51 PM PST 24
Finished Feb 25 01:29:52 PM PST 24
Peak memory 215092 kb
Host smart-a67f0841-4b28-46b1-89d1-254cbe4aa6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910367739 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1910367739
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.1339370056
Short name T315
Test name
Test status
Simulation time 37824892 ps
CPU time 0.98 seconds
Started Feb 25 01:29:53 PM PST 24
Finished Feb 25 01:29:55 PM PST 24
Peak memory 206272 kb
Host smart-ec748474-943e-45a3-97e8-4d835b7393d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339370056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.1339370056
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3351136606
Short name T640
Test name
Test status
Simulation time 13628196 ps
CPU time 0.86 seconds
Started Feb 25 01:29:56 PM PST 24
Finished Feb 25 01:29:57 PM PST 24
Peak memory 214848 kb
Host smart-5ba26a09-748d-469b-ada1-1e2d1ad8e0f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351136606 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3351136606
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3139684688
Short name T741
Test name
Test status
Simulation time 91363438 ps
CPU time 1.18 seconds
Started Feb 25 01:30:01 PM PST 24
Finished Feb 25 01:30:02 PM PST 24
Peak memory 215684 kb
Host smart-1dee9efa-c280-4e3f-a063-085e8eacaad7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139684688 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3139684688
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2696085203
Short name T84
Test name
Test status
Simulation time 21232797 ps
CPU time 1.18 seconds
Started Feb 25 01:29:57 PM PST 24
Finished Feb 25 01:29:58 PM PST 24
Peak memory 229148 kb
Host smart-79bae773-ad4e-491a-bdeb-19a25629d24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696085203 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2696085203
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_intr.1236015054
Short name T134
Test name
Test status
Simulation time 44359779 ps
CPU time 0.88 seconds
Started Feb 25 01:29:57 PM PST 24
Finished Feb 25 01:29:58 PM PST 24
Peak memory 214972 kb
Host smart-5715dab5-0bbd-424a-8633-203b82201ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236015054 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.1236015054
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2409994664
Short name T812
Test name
Test status
Simulation time 31361398 ps
CPU time 0.96 seconds
Started Feb 25 01:29:55 PM PST 24
Finished Feb 25 01:29:56 PM PST 24
Peak memory 214796 kb
Host smart-3e00a9ef-17d7-4b39-841f-a2ebf58edd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409994664 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2409994664
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1244808594
Short name T700
Test name
Test status
Simulation time 64093669 ps
CPU time 1.27 seconds
Started Feb 25 01:29:57 PM PST 24
Finished Feb 25 01:29:58 PM PST 24
Peak memory 214676 kb
Host smart-b2c5c2ac-d442-45e3-aef4-9a7a3b9b2b77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244808594 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1244808594
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3643024261
Short name T205
Test name
Test status
Simulation time 122347996243 ps
CPU time 557.72 seconds
Started Feb 25 01:29:54 PM PST 24
Finished Feb 25 01:39:11 PM PST 24
Peak memory 218392 kb
Host smart-fe6adad9-a235-4ebb-a774-0886aa841226
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643024261 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3643024261
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3632284119
Short name T150
Test name
Test status
Simulation time 120641671 ps
CPU time 1.03 seconds
Started Feb 25 01:29:54 PM PST 24
Finished Feb 25 01:29:55 PM PST 24
Peak memory 215052 kb
Host smart-d510c509-f831-4bfb-94ca-2382c17b3edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632284119 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3632284119
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.85315742
Short name T385
Test name
Test status
Simulation time 15523600 ps
CPU time 0.9 seconds
Started Feb 25 01:29:56 PM PST 24
Finished Feb 25 01:29:57 PM PST 24
Peak memory 205944 kb
Host smart-129c0fec-9453-4220-b481-2ffeecfc15c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85315742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.85315742
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.475622740
Short name T170
Test name
Test status
Simulation time 51884823 ps
CPU time 0.84 seconds
Started Feb 25 01:29:51 PM PST 24
Finished Feb 25 01:29:52 PM PST 24
Peak memory 215104 kb
Host smart-b0baab69-29e4-405d-91f9-c3b175226a5d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475622740 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.475622740
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.363129447
Short name T159
Test name
Test status
Simulation time 124519672 ps
CPU time 1.04 seconds
Started Feb 25 01:29:56 PM PST 24
Finished Feb 25 01:29:58 PM PST 24
Peak memory 218372 kb
Host smart-a39bf2af-1eb3-443f-88de-3655003157aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363129447 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_di
sable_auto_req_mode.363129447
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.885467762
Short name T390
Test name
Test status
Simulation time 27078496 ps
CPU time 1.25 seconds
Started Feb 25 01:29:55 PM PST 24
Finished Feb 25 01:29:57 PM PST 24
Peak memory 219516 kb
Host smart-50a158a8-0327-431a-9d98-6c2c74369c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885467762 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.885467762
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3323975605
Short name T615
Test name
Test status
Simulation time 34385604 ps
CPU time 1.28 seconds
Started Feb 25 01:29:55 PM PST 24
Finished Feb 25 01:29:57 PM PST 24
Peak memory 215832 kb
Host smart-38c3c299-14fb-40d3-b807-ac72848c3e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323975605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3323975605
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1411768980
Short name T36
Test name
Test status
Simulation time 30772081 ps
CPU time 0.85 seconds
Started Feb 25 01:29:55 PM PST 24
Finished Feb 25 01:29:57 PM PST 24
Peak memory 215064 kb
Host smart-8c60d34d-95e6-4641-8d96-764b0db48381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411768980 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1411768980
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.3108218577
Short name T372
Test name
Test status
Simulation time 28635514 ps
CPU time 0.84 seconds
Started Feb 25 01:29:53 PM PST 24
Finished Feb 25 01:29:55 PM PST 24
Peak memory 214532 kb
Host smart-4ea7733f-c0af-46ff-a93f-fa1d57e0135d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108218577 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.3108218577
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2001582251
Short name T540
Test name
Test status
Simulation time 153234460 ps
CPU time 2.25 seconds
Started Feb 25 01:29:54 PM PST 24
Finished Feb 25 01:29:56 PM PST 24
Peak memory 215712 kb
Host smart-23f0cbe1-8024-4665-91ee-a7c45c8ed8c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001582251 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2001582251
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.1234511383
Short name T534
Test name
Test status
Simulation time 183868908486 ps
CPU time 950.06 seconds
Started Feb 25 01:29:55 PM PST 24
Finished Feb 25 01:45:45 PM PST 24
Peak memory 222076 kb
Host smart-3a0efa1e-6413-43b6-903f-0e060941f127
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234511383 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.1234511383
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3375262036
Short name T786
Test name
Test status
Simulation time 46415805 ps
CPU time 1.26 seconds
Started Feb 25 01:29:58 PM PST 24
Finished Feb 25 01:29:59 PM PST 24
Peak memory 215004 kb
Host smart-d611cbef-53a6-421a-a044-9ed90e65f947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375262036 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3375262036
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.4071377170
Short name T480
Test name
Test status
Simulation time 57940002 ps
CPU time 1.54 seconds
Started Feb 25 01:30:04 PM PST 24
Finished Feb 25 01:30:06 PM PST 24
Peak memory 206452 kb
Host smart-5539011e-09ab-4f0a-964d-e444278df45a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071377170 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.4071377170
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.3748491045
Short name T523
Test name
Test status
Simulation time 14059617 ps
CPU time 0.99 seconds
Started Feb 25 01:30:04 PM PST 24
Finished Feb 25 01:30:05 PM PST 24
Peak memory 215148 kb
Host smart-09f22e47-a007-453b-aa52-a7043580df44
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748491045 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.3748491045
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.3296951399
Short name T813
Test name
Test status
Simulation time 94215226 ps
CPU time 1.04 seconds
Started Feb 25 01:30:04 PM PST 24
Finished Feb 25 01:30:06 PM PST 24
Peak memory 217256 kb
Host smart-ee3ac102-b3b4-427d-837a-3d2aef230428
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296951399 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.3296951399
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.1344478050
Short name T155
Test name
Test status
Simulation time 40902537 ps
CPU time 1.22 seconds
Started Feb 25 01:30:01 PM PST 24
Finished Feb 25 01:30:03 PM PST 24
Peak memory 218700 kb
Host smart-b84b5faf-4051-4bdc-9f79-471bc48d1ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344478050 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1344478050
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3153435565
Short name T492
Test name
Test status
Simulation time 79995533 ps
CPU time 1.27 seconds
Started Feb 25 01:29:53 PM PST 24
Finished Feb 25 01:29:54 PM PST 24
Peak memory 215960 kb
Host smart-366efb2b-e02f-4a01-bb1f-d9bdd038b286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153435565 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3153435565
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.1766868984
Short name T754
Test name
Test status
Simulation time 26451006 ps
CPU time 0.86 seconds
Started Feb 25 01:29:57 PM PST 24
Finished Feb 25 01:29:58 PM PST 24
Peak memory 215176 kb
Host smart-1ce2dd62-9362-4fc1-94a9-3944b11a1b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766868984 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.1766868984
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1068559191
Short name T28
Test name
Test status
Simulation time 16498869 ps
CPU time 0.98 seconds
Started Feb 25 01:29:54 PM PST 24
Finished Feb 25 01:29:55 PM PST 24
Peak memory 214672 kb
Host smart-7985a7ff-5cf8-4c6a-998e-06e520336542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068559191 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1068559191
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.156703806
Short name T730
Test name
Test status
Simulation time 134413539 ps
CPU time 1.87 seconds
Started Feb 25 01:30:03 PM PST 24
Finished Feb 25 01:30:06 PM PST 24
Peak memory 214628 kb
Host smart-a850bce9-0b57-4792-a500-bcd754d2251e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156703806 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.156703806
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.1354912982
Short name T193
Test name
Test status
Simulation time 276013669079 ps
CPU time 526.34 seconds
Started Feb 25 01:29:55 PM PST 24
Finished Feb 25 01:38:41 PM PST 24
Peak memory 218660 kb
Host smart-c94d3209-14b5-434b-a11e-f9f1219a6bea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354912982 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.1354912982
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.3852402655
Short name T573
Test name
Test status
Simulation time 122811539 ps
CPU time 1.38 seconds
Started Feb 25 01:30:04 PM PST 24
Finished Feb 25 01:30:05 PM PST 24
Peak memory 215064 kb
Host smart-5bacacdf-0208-4491-8fea-923a7fa0e5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852402655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.3852402655
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.866643491
Short name T381
Test name
Test status
Simulation time 26690324 ps
CPU time 0.89 seconds
Started Feb 25 01:29:58 PM PST 24
Finished Feb 25 01:29:59 PM PST 24
Peak memory 206300 kb
Host smart-db329ff7-90c9-40ce-a54a-633e44a22db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866643491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.866643491
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2545485505
Short name T428
Test name
Test status
Simulation time 88683355 ps
CPU time 0.87 seconds
Started Feb 25 01:30:01 PM PST 24
Finished Feb 25 01:30:02 PM PST 24
Peak memory 214928 kb
Host smart-8c0bc63e-ec09-4481-9ebf-54c84bc5e3ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545485505 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2545485505
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.3930017417
Short name T520
Test name
Test status
Simulation time 146480528 ps
CPU time 0.96 seconds
Started Feb 25 01:30:05 PM PST 24
Finished Feb 25 01:30:06 PM PST 24
Peak memory 216408 kb
Host smart-5947608d-7563-457d-8574-07f86f5f1c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930017417 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3930017417
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.1467854567
Short name T759
Test name
Test status
Simulation time 95649761 ps
CPU time 1.26 seconds
Started Feb 25 01:30:03 PM PST 24
Finished Feb 25 01:30:05 PM PST 24
Peak memory 215972 kb
Host smart-9cdeaa3a-fe33-4d61-bd75-bd044aed1824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467854567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.1467854567
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.38158878
Short name T137
Test name
Test status
Simulation time 31569580 ps
CPU time 0.89 seconds
Started Feb 25 01:30:02 PM PST 24
Finished Feb 25 01:30:03 PM PST 24
Peak memory 215088 kb
Host smart-a214d3c0-fe0a-42f7-96ed-b386e4a42be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38158878 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.38158878
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3674688010
Short name T456
Test name
Test status
Simulation time 17706042 ps
CPU time 0.93 seconds
Started Feb 25 01:29:58 PM PST 24
Finished Feb 25 01:29:59 PM PST 24
Peak memory 214612 kb
Host smart-9f7477fe-e056-4496-a56d-d3ec55742c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674688010 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3674688010
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.1881721355
Short name T145
Test name
Test status
Simulation time 266177470 ps
CPU time 5.44 seconds
Started Feb 25 01:30:04 PM PST 24
Finished Feb 25 01:30:10 PM PST 24
Peak memory 215992 kb
Host smart-bb3c0711-1274-400a-8c5e-64acacfc3ef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881721355 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.1881721355
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.9755597
Short name T633
Test name
Test status
Simulation time 50965947096 ps
CPU time 569.01 seconds
Started Feb 25 01:30:03 PM PST 24
Finished Feb 25 01:39:33 PM PST 24
Peak memory 216788 kb
Host smart-d7b497b6-3d81-4139-81a4-1e6e19b74d70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9755597 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.9755597
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.704545684
Short name T73
Test name
Test status
Simulation time 83522754 ps
CPU time 1.23 seconds
Started Feb 25 01:30:06 PM PST 24
Finished Feb 25 01:30:07 PM PST 24
Peak memory 215116 kb
Host smart-5c6e73bc-0ecb-43f6-b0e4-1c98320bc51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704545684 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.704545684
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.352564791
Short name T758
Test name
Test status
Simulation time 17009066 ps
CPU time 0.94 seconds
Started Feb 25 01:29:59 PM PST 24
Finished Feb 25 01:30:00 PM PST 24
Peak memory 205936 kb
Host smart-4463ab4e-5a59-49c0-98bc-4d72587c64b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352564791 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.352564791
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_err.2155208502
Short name T61
Test name
Test status
Simulation time 24661999 ps
CPU time 1.08 seconds
Started Feb 25 01:30:04 PM PST 24
Finished Feb 25 01:30:06 PM PST 24
Peak memory 230784 kb
Host smart-1db705be-f57e-497d-bfd2-2e3229d64ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155208502 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2155208502
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.900794078
Short name T192
Test name
Test status
Simulation time 77622066 ps
CPU time 1.79 seconds
Started Feb 25 01:30:03 PM PST 24
Finished Feb 25 01:30:06 PM PST 24
Peak memory 218788 kb
Host smart-ad4844d7-e879-4ac1-95d8-080488d58fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900794078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.900794078
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.2516596593
Short name T44
Test name
Test status
Simulation time 21944257 ps
CPU time 1.22 seconds
Started Feb 25 01:30:01 PM PST 24
Finished Feb 25 01:30:02 PM PST 24
Peak memory 222560 kb
Host smart-0ea5009e-8c06-4a88-89b9-0fbc616d7bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516596593 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.2516596593
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2655766408
Short name T460
Test name
Test status
Simulation time 31677166 ps
CPU time 0.91 seconds
Started Feb 25 01:29:58 PM PST 24
Finished Feb 25 01:30:00 PM PST 24
Peak memory 214728 kb
Host smart-872342bf-5d29-4f4e-8f33-aa3d073e81a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655766408 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2655766408
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.548401013
Short name T216
Test name
Test status
Simulation time 54220886 ps
CPU time 1.12 seconds
Started Feb 25 01:29:55 PM PST 24
Finished Feb 25 01:29:57 PM PST 24
Peak memory 205448 kb
Host smart-917ba1f3-beb5-40d7-8409-75039103f373
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548401013 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.548401013
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3754500676
Short name T196
Test name
Test status
Simulation time 39878129258 ps
CPU time 905.93 seconds
Started Feb 25 01:29:57 PM PST 24
Finished Feb 25 01:45:03 PM PST 24
Peak memory 223044 kb
Host smart-72e51cad-30d1-4c0f-a786-da47d071c105
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754500676 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3754500676
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.301544156
Short name T151
Test name
Test status
Simulation time 60570104 ps
CPU time 1.2 seconds
Started Feb 25 01:30:06 PM PST 24
Finished Feb 25 01:30:07 PM PST 24
Peak memory 215052 kb
Host smart-87b981eb-a4e2-4ea2-81a5-b185fe4b9c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301544156 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.301544156
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3901621727
Short name T329
Test name
Test status
Simulation time 56540040 ps
CPU time 0.92 seconds
Started Feb 25 01:30:00 PM PST 24
Finished Feb 25 01:30:01 PM PST 24
Peak memory 206268 kb
Host smart-d6293df7-c7d1-4678-a5fa-4684ec5fa399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901621727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3901621727
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3624889073
Short name T399
Test name
Test status
Simulation time 21916851 ps
CPU time 0.88 seconds
Started Feb 25 01:30:01 PM PST 24
Finished Feb 25 01:30:02 PM PST 24
Peak memory 214812 kb
Host smart-534bcdf5-9df8-4b65-8444-953cf0a3c81b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624889073 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3624889073
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_err.2903500018
Short name T218
Test name
Test status
Simulation time 18357258 ps
CPU time 1.03 seconds
Started Feb 25 01:30:03 PM PST 24
Finished Feb 25 01:30:04 PM PST 24
Peak memory 217108 kb
Host smart-01a17740-1e61-460c-8132-9f7046358c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903500018 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.2903500018
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.37369469
Short name T67
Test name
Test status
Simulation time 54728445 ps
CPU time 1.82 seconds
Started Feb 25 01:30:06 PM PST 24
Finished Feb 25 01:30:08 PM PST 24
Peak memory 217172 kb
Host smart-33a086c7-68a1-4511-a357-533c80f2a609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37369469 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.37369469
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.1636453515
Short name T26
Test name
Test status
Simulation time 25458209 ps
CPU time 0.97 seconds
Started Feb 25 01:30:05 PM PST 24
Finished Feb 25 01:30:07 PM PST 24
Peak memory 215248 kb
Host smart-0834121d-220d-47c9-9717-86b7274ae040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636453515 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.1636453515
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1371104793
Short name T336
Test name
Test status
Simulation time 41392983 ps
CPU time 0.97 seconds
Started Feb 25 01:30:01 PM PST 24
Finished Feb 25 01:30:02 PM PST 24
Peak memory 214728 kb
Host smart-b39e3b89-7cee-4adc-ac3b-8b681afc694a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371104793 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1371104793
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3997786379
Short name T734
Test name
Test status
Simulation time 229587443 ps
CPU time 1.88 seconds
Started Feb 25 01:30:01 PM PST 24
Finished Feb 25 01:30:03 PM PST 24
Peak memory 215920 kb
Host smart-24415407-d725-4000-a951-4516120b2bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997786379 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3997786379
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1639417160
Short name T783
Test name
Test status
Simulation time 735830066147 ps
CPU time 1296.66 seconds
Started Feb 25 01:30:03 PM PST 24
Finished Feb 25 01:51:40 PM PST 24
Peak memory 221304 kb
Host smart-5a70d9f1-9f60-4568-946b-a7a4c2de7f11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639417160 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1639417160
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert_test.3420165307
Short name T364
Test name
Test status
Simulation time 11673716 ps
CPU time 0.82 seconds
Started Feb 25 01:30:03 PM PST 24
Finished Feb 25 01:30:05 PM PST 24
Peak memory 205284 kb
Host smart-ba680438-f762-42a6-81fc-3783b150f966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420165307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.3420165307
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1197129853
Short name T744
Test name
Test status
Simulation time 16859940 ps
CPU time 0.82 seconds
Started Feb 25 01:30:06 PM PST 24
Finished Feb 25 01:30:07 PM PST 24
Peak memory 215060 kb
Host smart-54cee8d6-d5cf-42fb-965c-41775d844e71
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197129853 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1197129853
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1206884328
Short name T91
Test name
Test status
Simulation time 131039094 ps
CPU time 1.22 seconds
Started Feb 25 01:30:03 PM PST 24
Finished Feb 25 01:30:05 PM PST 24
Peak memory 215808 kb
Host smart-5967de18-e0a6-4b70-8bce-cb7c4ab313df
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206884328 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1206884328
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.685149258
Short name T49
Test name
Test status
Simulation time 19987292 ps
CPU time 1.08 seconds
Started Feb 25 01:30:03 PM PST 24
Finished Feb 25 01:30:04 PM PST 24
Peak memory 222528 kb
Host smart-b7f85542-bbf0-479f-82d0-c100bd7af491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685149258 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.685149258
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2179122957
Short name T579
Test name
Test status
Simulation time 527698218 ps
CPU time 3.97 seconds
Started Feb 25 01:30:03 PM PST 24
Finished Feb 25 01:30:07 PM PST 24
Peak memory 217124 kb
Host smart-dda58460-a296-418e-84e9-1408e3998f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179122957 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2179122957
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_smoke.1000259966
Short name T181
Test name
Test status
Simulation time 56078464 ps
CPU time 0.94 seconds
Started Feb 25 01:29:59 PM PST 24
Finished Feb 25 01:30:00 PM PST 24
Peak memory 214720 kb
Host smart-714cb1e7-8269-47ac-bfa7-e9a341a4bff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000259966 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1000259966
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2102034966
Short name T376
Test name
Test status
Simulation time 1614589610 ps
CPU time 2.79 seconds
Started Feb 25 01:30:04 PM PST 24
Finished Feb 25 01:30:07 PM PST 24
Peak memory 214704 kb
Host smart-3a3b302c-a902-4da9-9b9f-b625d117c13d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102034966 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2102034966
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.4012658840
Short name T237
Test name
Test status
Simulation time 76327942708 ps
CPU time 898.27 seconds
Started Feb 25 01:30:02 PM PST 24
Finished Feb 25 01:45:01 PM PST 24
Peak memory 220988 kb
Host smart-a04b8187-a8ef-4cb7-a139-400828454a33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012658840 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.4012658840
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1619818339
Short name T457
Test name
Test status
Simulation time 38643942 ps
CPU time 1.14 seconds
Started Feb 25 01:30:15 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 215120 kb
Host smart-073980df-c6e4-45b2-b826-478395672086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619818339 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1619818339
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.850641631
Short name T342
Test name
Test status
Simulation time 26833947 ps
CPU time 0.9 seconds
Started Feb 25 01:30:15 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 206064 kb
Host smart-f40f5ab2-4ae0-49c8-b0c9-7ffac07ece73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850641631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.850641631
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.1481381544
Short name T477
Test name
Test status
Simulation time 86053031 ps
CPU time 0.87 seconds
Started Feb 25 01:30:12 PM PST 24
Finished Feb 25 01:30:13 PM PST 24
Peak memory 214840 kb
Host smart-b326f19a-614c-4091-9440-183b846a4c8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481381544 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.1481381544
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3586523079
Short name T478
Test name
Test status
Simulation time 37135633 ps
CPU time 0.97 seconds
Started Feb 25 01:30:12 PM PST 24
Finished Feb 25 01:30:13 PM PST 24
Peak memory 216944 kb
Host smart-e108af38-453e-4bab-aa2b-0b7b3907f965
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586523079 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3586523079
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.3931965928
Short name T118
Test name
Test status
Simulation time 47466826 ps
CPU time 1.02 seconds
Started Feb 25 01:30:15 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 230520 kb
Host smart-41af8a85-7757-44c0-8384-eac54676bda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931965928 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3931965928
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1799866553
Short name T260
Test name
Test status
Simulation time 54588753 ps
CPU time 1.6 seconds
Started Feb 25 01:30:06 PM PST 24
Finished Feb 25 01:30:08 PM PST 24
Peak memory 217496 kb
Host smart-a827bb8b-03d0-463b-bab2-61703f5d3bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799866553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1799866553
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1288594842
Short name T453
Test name
Test status
Simulation time 25698033 ps
CPU time 1.07 seconds
Started Feb 25 01:30:19 PM PST 24
Finished Feb 25 01:30:21 PM PST 24
Peak memory 214800 kb
Host smart-96c14193-d7da-47d4-b946-334af9c719b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288594842 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1288594842
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3394156837
Short name T570
Test name
Test status
Simulation time 25798724 ps
CPU time 0.96 seconds
Started Feb 25 01:30:03 PM PST 24
Finished Feb 25 01:30:04 PM PST 24
Peak memory 214724 kb
Host smart-e8d7e935-81d6-4623-934e-a1fc4a20ebf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394156837 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3394156837
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3649364641
Short name T773
Test name
Test status
Simulation time 384646859 ps
CPU time 7.7 seconds
Started Feb 25 01:30:02 PM PST 24
Finished Feb 25 01:30:10 PM PST 24
Peak memory 216168 kb
Host smart-52ae4a72-b76f-4e54-a977-39f686e112f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649364641 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3649364641
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.1947797216
Short name T432
Test name
Test status
Simulation time 63639167904 ps
CPU time 840.11 seconds
Started Feb 25 01:30:19 PM PST 24
Finished Feb 25 01:44:20 PM PST 24
Peak memory 220032 kb
Host smart-9bc94ff3-7ea0-40c3-844a-1d6641d6af56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947797216 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.1947797216
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2999387522
Short name T764
Test name
Test status
Simulation time 30402426 ps
CPU time 1.11 seconds
Started Feb 25 01:30:09 PM PST 24
Finished Feb 25 01:30:10 PM PST 24
Peak memory 215072 kb
Host smart-1e3cccd3-7e23-454a-8831-08d0084f2d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999387522 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2999387522
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.2766518128
Short name T369
Test name
Test status
Simulation time 23620600 ps
CPU time 0.84 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 205928 kb
Host smart-f636a235-f4b5-4fb8-9311-8c15ff40ad42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766518128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.2766518128
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2219036794
Short name T23
Test name
Test status
Simulation time 14680866 ps
CPU time 0.96 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 215012 kb
Host smart-76fa4dbf-6752-4770-a27b-c53cbf5e1636
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219036794 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2219036794
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_err.3501279610
Short name T94
Test name
Test status
Simulation time 116708417 ps
CPU time 1.13 seconds
Started Feb 25 01:30:16 PM PST 24
Finished Feb 25 01:30:18 PM PST 24
Peak memory 216232 kb
Host smart-e7c606b4-2ad2-4ea4-96f4-4fe88521888d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501279610 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.3501279610
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.2096360262
Short name T212
Test name
Test status
Simulation time 31071240 ps
CPU time 1.38 seconds
Started Feb 25 01:30:13 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 218572 kb
Host smart-e3f2e8fb-0683-4c4a-a560-a569386f0e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096360262 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2096360262
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1720674251
Short name T397
Test name
Test status
Simulation time 26332562 ps
CPU time 0.94 seconds
Started Feb 25 01:30:13 PM PST 24
Finished Feb 25 01:30:14 PM PST 24
Peak memory 214868 kb
Host smart-5bbb8373-4404-4313-a2c8-01efbe56a24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720674251 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1720674251
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.1105152153
Short name T611
Test name
Test status
Simulation time 17697526 ps
CPU time 0.97 seconds
Started Feb 25 01:30:10 PM PST 24
Finished Feb 25 01:30:11 PM PST 24
Peak memory 214688 kb
Host smart-d29c41bb-9d7c-4671-bcc6-f662bcc21b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105152153 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1105152153
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3379189496
Short name T541
Test name
Test status
Simulation time 286652724 ps
CPU time 2.6 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:17 PM PST 24
Peak memory 215636 kb
Host smart-2a016ddf-091c-43c1-bb9f-40722af48322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379189496 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3379189496
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.2955074070
Short name T742
Test name
Test status
Simulation time 242679177510 ps
CPU time 1388.08 seconds
Started Feb 25 01:30:17 PM PST 24
Finished Feb 25 01:53:26 PM PST 24
Peak memory 222560 kb
Host smart-f4e4767f-81a9-4fc0-8787-2af8b6d99aa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955074070 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.2955074070
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.2197473515
Short name T103
Test name
Test status
Simulation time 119224269 ps
CPU time 1.17 seconds
Started Feb 25 01:28:51 PM PST 24
Finished Feb 25 01:28:52 PM PST 24
Peak memory 215040 kb
Host smart-fb7db14f-997f-4c02-a718-7e1135c3a209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197473515 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.2197473515
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.711177715
Short name T706
Test name
Test status
Simulation time 41448212 ps
CPU time 1.04 seconds
Started Feb 25 01:28:57 PM PST 24
Finished Feb 25 01:28:59 PM PST 24
Peak memory 205920 kb
Host smart-f9d5eed0-df91-4ac4-bc1a-d390c3ee4217
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711177715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.711177715
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.217521686
Short name T675
Test name
Test status
Simulation time 37022839 ps
CPU time 0.88 seconds
Started Feb 25 01:28:51 PM PST 24
Finished Feb 25 01:28:52 PM PST 24
Peak memory 214068 kb
Host smart-b15bb833-fc34-464f-9a18-236f6e4a6d74
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217521686 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.217521686
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2796435738
Short name T75
Test name
Test status
Simulation time 45298902 ps
CPU time 1.31 seconds
Started Feb 25 01:28:55 PM PST 24
Finished Feb 25 01:28:57 PM PST 24
Peak memory 215856 kb
Host smart-4f26d27f-340e-42e6-a427-abe260969235
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796435738 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2796435738
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.205279583
Short name T739
Test name
Test status
Simulation time 39345096 ps
CPU time 1.04 seconds
Started Feb 25 01:28:46 PM PST 24
Finished Feb 25 01:28:48 PM PST 24
Peak memory 217500 kb
Host smart-9d3dfcf1-9807-46f8-88e3-32ab980a9bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205279583 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.205279583
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.324849908
Short name T817
Test name
Test status
Simulation time 88102724 ps
CPU time 1.18 seconds
Started Feb 25 01:28:51 PM PST 24
Finished Feb 25 01:28:52 PM PST 24
Peak memory 215988 kb
Host smart-4266eef6-2781-44a8-b11f-046ec69b4af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324849908 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.324849908
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.2222844546
Short name T43
Test name
Test status
Simulation time 23855514 ps
CPU time 1.17 seconds
Started Feb 25 01:28:50 PM PST 24
Finished Feb 25 01:28:51 PM PST 24
Peak memory 223468 kb
Host smart-d5ba7085-3b92-4ed6-9b82-be570955e540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222844546 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.2222844546
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_sec_cm.3737440751
Short name T14
Test name
Test status
Simulation time 694184640 ps
CPU time 3.23 seconds
Started Feb 25 01:28:59 PM PST 24
Finished Feb 25 01:29:03 PM PST 24
Peak memory 234832 kb
Host smart-fc3c1520-3e30-4e5c-8fea-c160dc3dad52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737440751 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.3737440751
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2579538596
Short name T407
Test name
Test status
Simulation time 16554778 ps
CPU time 1.04 seconds
Started Feb 25 01:28:51 PM PST 24
Finished Feb 25 01:28:52 PM PST 24
Peak memory 213616 kb
Host smart-5c9031a8-72ec-488d-beb9-7f2a97c5657d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579538596 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2579538596
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1117034241
Short name T587
Test name
Test status
Simulation time 1010682769 ps
CPU time 3.38 seconds
Started Feb 25 01:28:44 PM PST 24
Finished Feb 25 01:28:47 PM PST 24
Peak memory 214864 kb
Host smart-2093cebd-27ee-4217-a0e9-1281bb999a3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117034241 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1117034241
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.3780230744
Short name T56
Test name
Test status
Simulation time 34176659612 ps
CPU time 926.58 seconds
Started Feb 25 01:28:41 PM PST 24
Finished Feb 25 01:44:09 PM PST 24
Peak memory 218772 kb
Host smart-e27a7a87-c003-4bb9-ac37-43b990a5edd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780230744 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.3780230744
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.4001931584
Short name T246
Test name
Test status
Simulation time 23128514 ps
CPU time 1.22 seconds
Started Feb 25 01:30:16 PM PST 24
Finished Feb 25 01:30:18 PM PST 24
Peak memory 215180 kb
Host smart-daf563b5-e87d-4d73-9a28-48579655d99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001931584 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.4001931584
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3443220359
Short name T498
Test name
Test status
Simulation time 34816525 ps
CPU time 0.82 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 205036 kb
Host smart-75dcd8f1-156b-4791-81b8-3621b8c23c6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443220359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3443220359
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.165767150
Short name T419
Test name
Test status
Simulation time 13631672 ps
CPU time 0.96 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 214960 kb
Host smart-6f740c0a-a3d2-412e-94fc-6405c4cd9a74
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165767150 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.165767150
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.497862750
Short name T821
Test name
Test status
Simulation time 334218188 ps
CPU time 1.21 seconds
Started Feb 25 01:30:13 PM PST 24
Finished Feb 25 01:30:14 PM PST 24
Peak memory 215740 kb
Host smart-f14f2ee5-9cfe-4e1d-b54f-29374ec800c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497862750 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.497862750
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.606114462
Short name T68
Test name
Test status
Simulation time 27268666 ps
CPU time 1.12 seconds
Started Feb 25 01:30:13 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 216200 kb
Host smart-444966ea-4a51-4fc7-adb7-c37517767515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606114462 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.606114462
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3961308042
Short name T625
Test name
Test status
Simulation time 52262733 ps
CPU time 1.71 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 217292 kb
Host smart-291a374a-0254-4c6c-93c0-160c57465962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961308042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3961308042
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.8773819
Short name T586
Test name
Test status
Simulation time 24351422 ps
CPU time 1.18 seconds
Started Feb 25 01:30:15 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 214912 kb
Host smart-1321957e-9a26-451b-b8ec-46cced5b6110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8773819 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.8773819
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3290360993
Short name T318
Test name
Test status
Simulation time 62579590 ps
CPU time 0.86 seconds
Started Feb 25 01:30:19 PM PST 24
Finished Feb 25 01:30:21 PM PST 24
Peak memory 214476 kb
Host smart-ffcae9c8-b7bb-432a-a07c-325c233ece2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290360993 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3290360993
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3641621724
Short name T514
Test name
Test status
Simulation time 208917116 ps
CPU time 1.64 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 214792 kb
Host smart-c73da31d-5203-46bb-b31c-998e11a871b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641621724 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3641621724
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.2045147522
Short name T787
Test name
Test status
Simulation time 106871739933 ps
CPU time 1294.98 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:51:49 PM PST 24
Peak memory 224504 kb
Host smart-d9df0e7e-f1da-4b3b-b55f-61394e8a9832
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045147522 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.2045147522
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1712908976
Short name T188
Test name
Test status
Simulation time 107993196 ps
CPU time 1.21 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 215104 kb
Host smart-c678c6d9-99ff-4978-bf9d-2fb195cfab20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712908976 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1712908976
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.882376945
Short name T553
Test name
Test status
Simulation time 34646695 ps
CPU time 0.83 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 205088 kb
Host smart-0cf43183-da4d-424a-a4d7-1a0d7eeac99e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882376945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.882376945
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3373627447
Short name T612
Test name
Test status
Simulation time 10630204 ps
CPU time 0.88 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 215200 kb
Host smart-5e533ebb-aafe-4b2d-bdce-b6f80f9ce0c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373627447 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3373627447
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.4284364562
Short name T63
Test name
Test status
Simulation time 52952897 ps
CPU time 1 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 215788 kb
Host smart-044079f5-5739-4498-8c4f-9b91837c996b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284364562 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.4284364562
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.3924643773
Short name T96
Test name
Test status
Simulation time 23991781 ps
CPU time 0.99 seconds
Started Feb 25 01:30:15 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 217252 kb
Host smart-441e6d79-e11c-44c1-96f1-aa9387785b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924643773 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3924643773
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1051940713
Short name T389
Test name
Test status
Simulation time 112914258 ps
CPU time 2.36 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 216196 kb
Host smart-aed8fbab-78af-41f4-a93f-293be4aa225a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051940713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1051940713
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.780436035
Short name T330
Test name
Test status
Simulation time 22065043 ps
CPU time 1.09 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 215044 kb
Host smart-2989c506-cf15-4eeb-8ce2-28002577cc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780436035 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.780436035
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1747343073
Short name T619
Test name
Test status
Simulation time 91585543 ps
CPU time 0.87 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 214724 kb
Host smart-34f85730-086e-443f-bde5-292ebb85e587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747343073 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1747343073
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1032441965
Short name T302
Test name
Test status
Simulation time 180220160 ps
CPU time 3.16 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:18 PM PST 24
Peak memory 216020 kb
Host smart-03115ac3-b488-4590-8f5a-04fa3d004241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032441965 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1032441965
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_alert.3224575973
Short name T720
Test name
Test status
Simulation time 101670269 ps
CPU time 1.35 seconds
Started Feb 25 01:30:17 PM PST 24
Finished Feb 25 01:30:19 PM PST 24
Peak memory 215068 kb
Host smart-60b06b41-7c1f-4641-b59d-9af4113bac77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224575973 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3224575973
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2321390670
Short name T443
Test name
Test status
Simulation time 21050585 ps
CPU time 0.81 seconds
Started Feb 25 01:30:13 PM PST 24
Finished Feb 25 01:30:14 PM PST 24
Peak memory 206100 kb
Host smart-becf1790-ed4f-43d6-8301-619047fdfdaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321390670 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2321390670
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3945574267
Short name T186
Test name
Test status
Simulation time 14014594 ps
CPU time 0.88 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 215040 kb
Host smart-992d0817-8fc5-45d3-8921-367a2c12d215
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945574267 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3945574267
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2791940070
Short name T421
Test name
Test status
Simulation time 46132545 ps
CPU time 1.06 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 217064 kb
Host smart-bb77043d-fbb8-496b-9c96-03f53d36172c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791940070 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2791940070
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.1426447592
Short name T64
Test name
Test status
Simulation time 22318792 ps
CPU time 1.09 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 218660 kb
Host smart-fb5c1a8e-4ae5-4141-9791-0ae5d3d77524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426447592 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.1426447592
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1814255862
Short name T5
Test name
Test status
Simulation time 80432844 ps
CPU time 1.23 seconds
Started Feb 25 01:30:12 PM PST 24
Finished Feb 25 01:30:14 PM PST 24
Peak memory 216292 kb
Host smart-43510c39-0179-46d6-9666-897b74218377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814255862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1814255862
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1374399428
Short name T338
Test name
Test status
Simulation time 27131507 ps
CPU time 0.98 seconds
Started Feb 25 01:30:15 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 215116 kb
Host smart-6d7eb2e7-a640-459a-acaf-3e06f1eb53ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374399428 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1374399428
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2918246434
Short name T386
Test name
Test status
Simulation time 126822779 ps
CPU time 0.88 seconds
Started Feb 25 01:30:12 PM PST 24
Finished Feb 25 01:30:14 PM PST 24
Peak memory 214732 kb
Host smart-3d29389e-3e94-46e2-afcd-4b64b89429d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918246434 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2918246434
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2729215097
Short name T755
Test name
Test status
Simulation time 186061252 ps
CPU time 3.67 seconds
Started Feb 25 01:30:19 PM PST 24
Finished Feb 25 01:30:24 PM PST 24
Peak memory 214676 kb
Host smart-9349de29-1ba6-44ff-bd12-309bd7e09951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729215097 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2729215097
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.4265045957
Short name T21
Test name
Test status
Simulation time 195764538550 ps
CPU time 1602.36 seconds
Started Feb 25 01:30:13 PM PST 24
Finished Feb 25 01:56:55 PM PST 24
Peak memory 226164 kb
Host smart-cf73a23d-2c15-452d-86ca-a0568734240a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265045957 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.4265045957
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.458473559
Short name T12
Test name
Test status
Simulation time 78518449 ps
CPU time 1.1 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 215112 kb
Host smart-597732c8-5b4e-4803-9a9b-b1f4cb6b92b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458473559 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.458473559
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3989643915
Short name T360
Test name
Test status
Simulation time 45525323 ps
CPU time 0.83 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 205088 kb
Host smart-6d293827-66ae-4239-9636-7602f7cd325d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989643915 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3989643915
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.563228668
Short name T115
Test name
Test status
Simulation time 18365535 ps
CPU time 0.86 seconds
Started Feb 25 01:30:15 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 215112 kb
Host smart-a560fd7c-3a16-4be2-a1bf-8ac5e07d6650
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563228668 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.563228668
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.3575338696
Short name T503
Test name
Test status
Simulation time 62147453 ps
CPU time 1.17 seconds
Started Feb 25 01:30:13 PM PST 24
Finished Feb 25 01:30:14 PM PST 24
Peak memory 215884 kb
Host smart-8781a6d3-46e5-495b-813f-ef79a593247e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575338696 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.3575338696
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.2581054465
Short name T172
Test name
Test status
Simulation time 31753836 ps
CPU time 0.99 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 218872 kb
Host smart-12254cf7-a504-48e5-9a70-5ace7d33eb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581054465 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2581054465
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.155033689
Short name T459
Test name
Test status
Simulation time 44136618 ps
CPU time 1.21 seconds
Started Feb 25 01:30:18 PM PST 24
Finished Feb 25 01:30:20 PM PST 24
Peak memory 216004 kb
Host smart-c8ceb4a2-c45f-43f7-aa95-ca9d7d0d3ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155033689 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.155033689
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1406061743
Short name T326
Test name
Test status
Simulation time 38545334 ps
CPU time 0.84 seconds
Started Feb 25 01:30:13 PM PST 24
Finished Feb 25 01:30:14 PM PST 24
Peak memory 214840 kb
Host smart-5decb668-67e5-457c-b162-3e08bfe6378e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406061743 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1406061743
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1709319151
Short name T628
Test name
Test status
Simulation time 133466867 ps
CPU time 0.9 seconds
Started Feb 25 01:30:15 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 214732 kb
Host smart-c5a42e55-0526-4b01-8b8c-9e76572eefd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709319151 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1709319151
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2191764238
Short name T494
Test name
Test status
Simulation time 702112713 ps
CPU time 4.26 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:19 PM PST 24
Peak memory 215688 kb
Host smart-68700bde-cbde-464b-966c-9bca163ad5ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191764238 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2191764238
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2287468170
Short name T740
Test name
Test status
Simulation time 32550589565 ps
CPU time 334.51 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:35:48 PM PST 24
Peak memory 220296 kb
Host smart-5b4d1f59-1e14-4347-9223-fdffbcbe046a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287468170 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2287468170
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.234125100
Short name T149
Test name
Test status
Simulation time 221874184 ps
CPU time 1.36 seconds
Started Feb 25 01:30:15 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 215116 kb
Host smart-ded240b7-9e72-451a-aac8-85ffc6d4ce96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234125100 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.234125100
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2591096024
Short name T792
Test name
Test status
Simulation time 42109495 ps
CPU time 1.29 seconds
Started Feb 25 01:30:15 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 206308 kb
Host smart-b1f3823a-9e03-4250-b733-da6b8e418bc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591096024 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2591096024
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2259662604
Short name T311
Test name
Test status
Simulation time 33134433 ps
CPU time 0.88 seconds
Started Feb 25 01:30:18 PM PST 24
Finished Feb 25 01:30:20 PM PST 24
Peak memory 214760 kb
Host smart-55061a5c-8c34-45a0-8c81-f3b17c8538d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259662604 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2259662604
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_err.163939797
Short name T412
Test name
Test status
Simulation time 33213980 ps
CPU time 1.03 seconds
Started Feb 25 01:30:17 PM PST 24
Finished Feb 25 01:30:19 PM PST 24
Peak memory 216188 kb
Host smart-fa4daa4b-7511-43f6-9dce-5d6db9fec231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163939797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.163939797
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2039712958
Short name T538
Test name
Test status
Simulation time 620720015 ps
CPU time 5.46 seconds
Started Feb 25 01:30:17 PM PST 24
Finished Feb 25 01:30:24 PM PST 24
Peak memory 216212 kb
Host smart-eb877b0b-283b-4041-aa88-c69a121074e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039712958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2039712958
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1199114173
Short name T10
Test name
Test status
Simulation time 37036849 ps
CPU time 0.98 seconds
Started Feb 25 01:30:15 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 223268 kb
Host smart-d67d1c3e-9108-443e-bfc7-da58e46acebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199114173 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1199114173
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.4141287712
Short name T549
Test name
Test status
Simulation time 21101113 ps
CPU time 0.93 seconds
Started Feb 25 01:30:17 PM PST 24
Finished Feb 25 01:30:19 PM PST 24
Peak memory 214676 kb
Host smart-3cc1f45d-0bd9-4e4d-9c4a-fddb71e07b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141287712 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.4141287712
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.674025913
Short name T797
Test name
Test status
Simulation time 570305904 ps
CPU time 4.34 seconds
Started Feb 25 01:30:18 PM PST 24
Finished Feb 25 01:30:24 PM PST 24
Peak memory 214684 kb
Host smart-e1e4d1c1-ccff-462a-b27f-d448b866474e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674025913 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.674025913
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1385632233
Short name T203
Test name
Test status
Simulation time 78321910074 ps
CPU time 442.93 seconds
Started Feb 25 01:30:18 PM PST 24
Finished Feb 25 01:37:42 PM PST 24
Peak memory 223032 kb
Host smart-60e0b11f-4e4b-4dc1-ae26-e050a549f0f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385632233 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1385632233
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1310560814
Short name T604
Test name
Test status
Simulation time 82347633 ps
CPU time 1.1 seconds
Started Feb 25 01:30:15 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 215108 kb
Host smart-81420900-2cb0-4e26-bc07-8f7e2719d1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310560814 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1310560814
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3214695981
Short name T733
Test name
Test status
Simulation time 74106999 ps
CPU time 0.9 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 205928 kb
Host smart-e07cd06f-d626-4255-ba78-6f5f1c22dfd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214695981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3214695981
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1434679586
Short name T187
Test name
Test status
Simulation time 29599089 ps
CPU time 0.83 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 215112 kb
Host smart-98c49eb9-49af-4960-95d4-0cf38cfdbd3e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434679586 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1434679586
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.946494549
Short name T411
Test name
Test status
Simulation time 28593007 ps
CPU time 1.11 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 217068 kb
Host smart-9ffb3adb-b61c-4093-9e63-2d294789d720
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946494549 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_di
sable_auto_req_mode.946494549
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.846241478
Short name T79
Test name
Test status
Simulation time 21779249 ps
CPU time 1.14 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 216084 kb
Host smart-a4acff34-0c1c-448b-b104-29128c98fb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846241478 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.846241478
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3218166142
Short name T504
Test name
Test status
Simulation time 246820107 ps
CPU time 3.73 seconds
Started Feb 25 01:30:16 PM PST 24
Finished Feb 25 01:30:20 PM PST 24
Peak memory 216184 kb
Host smart-c9b1e899-069a-43c2-9f65-41fdf57d79d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218166142 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3218166142
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.725372089
Short name T424
Test name
Test status
Simulation time 25921529 ps
CPU time 1.06 seconds
Started Feb 25 01:30:15 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 222660 kb
Host smart-994e0091-b725-4c6a-95d0-36fdc0bc4b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725372089 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.725372089
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1940778626
Short name T609
Test name
Test status
Simulation time 17462744 ps
CPU time 0.96 seconds
Started Feb 25 01:30:15 PM PST 24
Finished Feb 25 01:30:17 PM PST 24
Peak memory 214728 kb
Host smart-138d7d0e-5699-4e76-837b-39946203c92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940778626 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1940778626
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2601574410
Short name T207
Test name
Test status
Simulation time 240511981 ps
CPU time 2.82 seconds
Started Feb 25 01:30:15 PM PST 24
Finished Feb 25 01:30:18 PM PST 24
Peak memory 214732 kb
Host smart-c76068db-50a5-484a-935e-51be36d1bdbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601574410 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2601574410
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.572452974
Short name T206
Test name
Test status
Simulation time 68755788715 ps
CPU time 966.6 seconds
Started Feb 25 01:30:11 PM PST 24
Finished Feb 25 01:46:18 PM PST 24
Peak memory 219536 kb
Host smart-0823b0c8-0df6-42a5-9115-cafd0b9534b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572452974 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.572452974
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.319699792
Short name T752
Test name
Test status
Simulation time 157716492 ps
CPU time 1.32 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:15 PM PST 24
Peak memory 215108 kb
Host smart-0575e7ee-5182-4ce4-a34a-7cf77fcf0add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319699792 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.319699792
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1382304757
Short name T818
Test name
Test status
Simulation time 33806376 ps
CPU time 0.95 seconds
Started Feb 25 01:30:22 PM PST 24
Finished Feb 25 01:30:23 PM PST 24
Peak memory 205972 kb
Host smart-049e5b1c-8551-4698-bab8-f680525ce08f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382304757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1382304757
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1229572620
Short name T175
Test name
Test status
Simulation time 35966374 ps
CPU time 0.82 seconds
Started Feb 25 01:30:16 PM PST 24
Finished Feb 25 01:30:18 PM PST 24
Peak memory 215232 kb
Host smart-3dacfbf6-5ad1-428b-9231-71e6d40e9a4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229572620 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1229572620
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_err.1719666125
Short name T629
Test name
Test status
Simulation time 23598997 ps
CPU time 0.97 seconds
Started Feb 25 01:30:17 PM PST 24
Finished Feb 25 01:30:19 PM PST 24
Peak memory 217608 kb
Host smart-b254ca32-e56a-4604-a4a2-d2cb8ef620aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719666125 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1719666125
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.2309894765
Short name T785
Test name
Test status
Simulation time 77327720 ps
CPU time 1.56 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:16 PM PST 24
Peak memory 217400 kb
Host smart-b4d9eb5d-57fa-4758-966e-98323840e60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309894765 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.2309894765
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.608498714
Short name T510
Test name
Test status
Simulation time 21127727 ps
CPU time 1.08 seconds
Started Feb 25 01:30:17 PM PST 24
Finished Feb 25 01:30:19 PM PST 24
Peak memory 215024 kb
Host smart-53d637b4-4e8f-4ae4-9d57-81bf3ea547a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608498714 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.608498714
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3001024953
Short name T339
Test name
Test status
Simulation time 46532422 ps
CPU time 0.99 seconds
Started Feb 25 01:30:15 PM PST 24
Finished Feb 25 01:30:17 PM PST 24
Peak memory 214712 kb
Host smart-9fc5f510-9d52-4b44-a60b-504377f23be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001024953 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3001024953
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.3365424049
Short name T269
Test name
Test status
Simulation time 728580309 ps
CPU time 4.16 seconds
Started Feb 25 01:30:14 PM PST 24
Finished Feb 25 01:30:18 PM PST 24
Peak memory 214780 kb
Host smart-d586e0a2-b2ff-4002-9fe2-65747c912c13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365424049 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.3365424049
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.3843674877
Short name T507
Test name
Test status
Simulation time 169330502039 ps
CPU time 1114.23 seconds
Started Feb 25 01:30:12 PM PST 24
Finished Feb 25 01:48:47 PM PST 24
Peak memory 221876 kb
Host smart-bf604aa2-da36-4838-8f13-7b4fefb1cd3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843674877 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.3843674877
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.795724326
Short name T555
Test name
Test status
Simulation time 25449528 ps
CPU time 1.13 seconds
Started Feb 25 01:30:25 PM PST 24
Finished Feb 25 01:30:27 PM PST 24
Peak memory 215104 kb
Host smart-690d06b2-f12b-4354-9846-a46657afc137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795724326 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.795724326
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2462671378
Short name T545
Test name
Test status
Simulation time 13686268 ps
CPU time 0.87 seconds
Started Feb 25 01:30:25 PM PST 24
Finished Feb 25 01:30:26 PM PST 24
Peak memory 205364 kb
Host smart-e03b8aab-c639-463c-a809-b615b94a4050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462671378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2462671378
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.682948595
Short name T745
Test name
Test status
Simulation time 33836859 ps
CPU time 0.84 seconds
Started Feb 25 01:30:40 PM PST 24
Finished Feb 25 01:30:41 PM PST 24
Peak memory 214768 kb
Host smart-f06c819d-fb28-4496-9f6d-ac016b9aa6d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682948595 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.682948595
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.951153179
Short name T564
Test name
Test status
Simulation time 36331660 ps
CPU time 1.17 seconds
Started Feb 25 01:30:27 PM PST 24
Finished Feb 25 01:30:29 PM PST 24
Peak memory 215820 kb
Host smart-c399a3d5-92e8-4b6c-a48b-ad61a805b590
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951153179 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.951153179
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1118218248
Short name T461
Test name
Test status
Simulation time 18348425 ps
CPU time 1 seconds
Started Feb 25 01:30:26 PM PST 24
Finished Feb 25 01:30:27 PM PST 24
Peak memory 217584 kb
Host smart-c44537a9-be54-40b0-a3a9-67ec64f1b358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118218248 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1118218248
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.117972976
Short name T420
Test name
Test status
Simulation time 137419233 ps
CPU time 3.28 seconds
Started Feb 25 01:30:23 PM PST 24
Finished Feb 25 01:30:27 PM PST 24
Peak memory 217448 kb
Host smart-f785235d-5f72-4177-bee9-cbea6348bd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117972976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.117972976
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1928438444
Short name T135
Test name
Test status
Simulation time 23063853 ps
CPU time 1.04 seconds
Started Feb 25 01:30:26 PM PST 24
Finished Feb 25 01:30:27 PM PST 24
Peak memory 215240 kb
Host smart-5513c1b3-80cb-43e7-a076-a5983648baeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928438444 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1928438444
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.149931096
Short name T517
Test name
Test status
Simulation time 21030238 ps
CPU time 0.92 seconds
Started Feb 25 01:30:26 PM PST 24
Finished Feb 25 01:30:28 PM PST 24
Peak memory 214668 kb
Host smart-9d721602-743f-4c08-90d6-cc522511f2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149931096 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.149931096
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1926610514
Short name T375
Test name
Test status
Simulation time 205487994 ps
CPU time 2.82 seconds
Started Feb 25 01:30:23 PM PST 24
Finished Feb 25 01:30:27 PM PST 24
Peak memory 215936 kb
Host smart-77c7e01e-13c0-47d4-82af-2f318c82bbb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926610514 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1926610514
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.200395604
Short name T581
Test name
Test status
Simulation time 150091749475 ps
CPU time 1079.18 seconds
Started Feb 25 01:30:24 PM PST 24
Finished Feb 25 01:48:24 PM PST 24
Peak memory 223128 kb
Host smart-ec829536-c3f7-40ad-a9f1-bf4cadb9d1ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200395604 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.200395604
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.2714232787
Short name T547
Test name
Test status
Simulation time 26198132 ps
CPU time 1.29 seconds
Started Feb 25 01:30:27 PM PST 24
Finished Feb 25 01:30:29 PM PST 24
Peak memory 215004 kb
Host smart-6775c3ec-d173-4a28-9923-baabefed47a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714232787 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2714232787
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1459380126
Short name T690
Test name
Test status
Simulation time 25757004 ps
CPU time 1.09 seconds
Started Feb 25 01:30:23 PM PST 24
Finished Feb 25 01:30:25 PM PST 24
Peak memory 206304 kb
Host smart-9d93d87a-4d86-4e3d-92de-dd0aefc9b025
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459380126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1459380126
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3705517969
Short name T796
Test name
Test status
Simulation time 21576837 ps
CPU time 0.9 seconds
Started Feb 25 01:30:26 PM PST 24
Finished Feb 25 01:30:28 PM PST 24
Peak memory 215252 kb
Host smart-757b0b53-1679-4c22-b945-7e33ac4af918
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705517969 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3705517969
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_err.3205774422
Short name T679
Test name
Test status
Simulation time 19317232 ps
CPU time 1.11 seconds
Started Feb 25 01:30:19 PM PST 24
Finished Feb 25 01:30:21 PM PST 24
Peak memory 217284 kb
Host smart-931fcdb4-21e9-47d5-9b5a-b27b262c3f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205774422 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3205774422
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.630009846
Short name T410
Test name
Test status
Simulation time 54920748 ps
CPU time 1.23 seconds
Started Feb 25 01:30:22 PM PST 24
Finished Feb 25 01:30:23 PM PST 24
Peak memory 217284 kb
Host smart-2fdc638e-e334-4834-8503-9a6af47dbe53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630009846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.630009846
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1707893244
Short name T476
Test name
Test status
Simulation time 22808054 ps
CPU time 1.14 seconds
Started Feb 25 01:30:29 PM PST 24
Finished Feb 25 01:30:30 PM PST 24
Peak memory 214804 kb
Host smart-09f1ce13-908c-4c87-853b-8469e64a1d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707893244 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1707893244
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.26853402
Short name T595
Test name
Test status
Simulation time 106135649 ps
CPU time 0.93 seconds
Started Feb 25 01:30:29 PM PST 24
Finished Feb 25 01:30:30 PM PST 24
Peak memory 214472 kb
Host smart-21ca2db9-551f-443c-8c8f-e52fd9611b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26853402 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.26853402
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2594535145
Short name T59
Test name
Test status
Simulation time 133190648 ps
CPU time 2.86 seconds
Started Feb 25 01:30:26 PM PST 24
Finished Feb 25 01:30:29 PM PST 24
Peak memory 214748 kb
Host smart-bae76a17-7b3d-483d-ab9f-970eebe05050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594535145 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2594535145
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2641315199
Short name T525
Test name
Test status
Simulation time 49212474472 ps
CPU time 322.48 seconds
Started Feb 25 01:30:24 PM PST 24
Finished Feb 25 01:35:47 PM PST 24
Peak memory 218232 kb
Host smart-fac14c94-7f7f-4784-a478-8339c123669b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641315199 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2641315199
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2311081259
Short name T770
Test name
Test status
Simulation time 47477137 ps
CPU time 1.18 seconds
Started Feb 25 01:30:26 PM PST 24
Finished Feb 25 01:30:28 PM PST 24
Peak memory 215124 kb
Host smart-5b88c93f-111e-4bcb-b2ab-51d7c7bff5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311081259 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2311081259
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.551821876
Short name T417
Test name
Test status
Simulation time 20952477 ps
CPU time 0.83 seconds
Started Feb 25 01:30:26 PM PST 24
Finished Feb 25 01:30:28 PM PST 24
Peak memory 205136 kb
Host smart-d4c8d246-951e-49bd-a076-b247ab41aa2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551821876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.551821876
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.526496868
Short name T32
Test name
Test status
Simulation time 44749461 ps
CPU time 0.89 seconds
Started Feb 25 01:30:27 PM PST 24
Finished Feb 25 01:30:29 PM PST 24
Peak memory 214780 kb
Host smart-a3bf5510-8f3c-488a-9ad4-3209243453d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526496868 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.526496868
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.1998818736
Short name T85
Test name
Test status
Simulation time 32264732 ps
CPU time 0.96 seconds
Started Feb 25 01:30:26 PM PST 24
Finished Feb 25 01:30:27 PM PST 24
Peak memory 215792 kb
Host smart-69d2fcd0-0711-4202-a9e2-c71c235e8f04
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998818736 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.1998818736
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.3735222762
Short name T74
Test name
Test status
Simulation time 33960598 ps
CPU time 1 seconds
Started Feb 25 01:30:20 PM PST 24
Finished Feb 25 01:30:22 PM PST 24
Peak memory 218608 kb
Host smart-2677ff77-0b7d-492d-9c8a-ebcf5ad8d391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735222762 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3735222762
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_intr.3271178571
Short name T664
Test name
Test status
Simulation time 27599216 ps
CPU time 0.9 seconds
Started Feb 25 01:30:40 PM PST 24
Finished Feb 25 01:30:41 PM PST 24
Peak memory 214664 kb
Host smart-36715c15-a4fe-4b23-ae90-72afd09d7429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271178571 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3271178571
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3818515677
Short name T577
Test name
Test status
Simulation time 19340918 ps
CPU time 1 seconds
Started Feb 25 01:30:26 PM PST 24
Finished Feb 25 01:30:28 PM PST 24
Peak memory 214728 kb
Host smart-6ef294f5-335f-47f9-98ad-d0e6065c4feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818515677 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3818515677
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.3676296283
Short name T482
Test name
Test status
Simulation time 465222594 ps
CPU time 2.13 seconds
Started Feb 25 01:30:23 PM PST 24
Finished Feb 25 01:30:26 PM PST 24
Peak memory 216116 kb
Host smart-5877df6c-9613-4906-83d3-e8e0c89b17ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676296283 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.3676296283
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.234410264
Short name T438
Test name
Test status
Simulation time 185802043072 ps
CPU time 530.53 seconds
Started Feb 25 01:30:26 PM PST 24
Finished Feb 25 01:39:17 PM PST 24
Peak memory 218708 kb
Host smart-2a360af3-9281-4d22-8a62-86d75653cd73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234410264 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.234410264
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.3349287764
Short name T825
Test name
Test status
Simulation time 86490510 ps
CPU time 1.26 seconds
Started Feb 25 01:29:07 PM PST 24
Finished Feb 25 01:29:09 PM PST 24
Peak memory 215116 kb
Host smart-37d59c96-c835-4760-9a3a-0c9b914c7ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349287764 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.3349287764
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.1805639215
Short name T530
Test name
Test status
Simulation time 14858580 ps
CPU time 0.94 seconds
Started Feb 25 01:28:58 PM PST 24
Finished Feb 25 01:29:00 PM PST 24
Peak memory 206432 kb
Host smart-93aaad58-da27-4761-bd37-9fa826e774a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805639215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.1805639215
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.1417020362
Short name T102
Test name
Test status
Simulation time 36358285 ps
CPU time 0.84 seconds
Started Feb 25 01:28:58 PM PST 24
Finished Feb 25 01:28:59 PM PST 24
Peak memory 215192 kb
Host smart-53d99486-7c80-4ce0-865e-3083e9ece059
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417020362 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.1417020362
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.1524976476
Short name T162
Test name
Test status
Simulation time 28824482 ps
CPU time 1.16 seconds
Started Feb 25 01:28:58 PM PST 24
Finished Feb 25 01:29:00 PM PST 24
Peak memory 215684 kb
Host smart-3b06635c-941e-4aed-8315-79115720401d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524976476 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.1524976476
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.4020450895
Short name T656
Test name
Test status
Simulation time 21671402 ps
CPU time 1.21 seconds
Started Feb 25 01:28:55 PM PST 24
Finished Feb 25 01:28:57 PM PST 24
Peak memory 222460 kb
Host smart-a54dd0c1-dbdf-4967-b68a-85a213dad24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020450895 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.4020450895
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1792802535
Short name T572
Test name
Test status
Simulation time 37161647 ps
CPU time 1.57 seconds
Started Feb 25 01:29:02 PM PST 24
Finished Feb 25 01:29:03 PM PST 24
Peak memory 218396 kb
Host smart-5e047898-2fec-4a66-9668-82f6960f004f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792802535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1792802535
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.1100283541
Short name T133
Test name
Test status
Simulation time 27881448 ps
CPU time 0.9 seconds
Started Feb 25 01:28:58 PM PST 24
Finished Feb 25 01:28:59 PM PST 24
Peak memory 215032 kb
Host smart-6d98c5ef-9940-4758-aaeb-f4dfe17a6b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100283541 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.1100283541
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1492071831
Short name T128
Test name
Test status
Simulation time 19228682 ps
CPU time 1.02 seconds
Started Feb 25 01:29:03 PM PST 24
Finished Feb 25 01:29:04 PM PST 24
Peak memory 206584 kb
Host smart-20da9122-3f46-46bf-8410-91025eb09a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492071831 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1492071831
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.1201611090
Short name T698
Test name
Test status
Simulation time 22986568 ps
CPU time 1.02 seconds
Started Feb 25 01:29:06 PM PST 24
Finished Feb 25 01:29:07 PM PST 24
Peak memory 214720 kb
Host smart-b1327de0-68d6-47cb-b611-66b9b9956688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201611090 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.1201611090
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2768548296
Short name T584
Test name
Test status
Simulation time 313720719 ps
CPU time 2.26 seconds
Started Feb 25 01:28:58 PM PST 24
Finished Feb 25 01:29:01 PM PST 24
Peak memory 215916 kb
Host smart-91621525-7b24-4d5a-9db6-9ae6881c119a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768548296 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2768548296
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.3976132153
Short name T557
Test name
Test status
Simulation time 63037265265 ps
CPU time 440.21 seconds
Started Feb 25 01:29:06 PM PST 24
Finished Feb 25 01:36:26 PM PST 24
Peak memory 217016 kb
Host smart-72de5fc0-1235-4099-b4f6-63f92166e998
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976132153 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.3976132153
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.2973579413
Short name T93
Test name
Test status
Simulation time 28274388 ps
CPU time 1.22 seconds
Started Feb 25 01:30:29 PM PST 24
Finished Feb 25 01:30:31 PM PST 24
Peak memory 216096 kb
Host smart-c4a2dacd-a9b0-4b49-9690-d16fba60ea4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973579413 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2973579413
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2236133727
Short name T331
Test name
Test status
Simulation time 46265440 ps
CPU time 1.4 seconds
Started Feb 25 01:30:23 PM PST 24
Finished Feb 25 01:30:25 PM PST 24
Peak memory 217064 kb
Host smart-abe8ff08-4047-4258-a956-2ff3e8f4488c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236133727 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2236133727
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.2229957003
Short name T702
Test name
Test status
Simulation time 19588916 ps
CPU time 1.07 seconds
Started Feb 25 01:30:29 PM PST 24
Finished Feb 25 01:30:30 PM PST 24
Peak memory 217580 kb
Host smart-5d06f599-418d-4e48-81dd-21a8385914a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229957003 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2229957003
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1388514749
Short name T481
Test name
Test status
Simulation time 57688471 ps
CPU time 1.67 seconds
Started Feb 25 01:30:20 PM PST 24
Finished Feb 25 01:30:22 PM PST 24
Peak memory 217820 kb
Host smart-bb32b249-3245-4390-8466-6ef4200a14c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388514749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1388514749
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.3146076077
Short name T756
Test name
Test status
Simulation time 23423030 ps
CPU time 1 seconds
Started Feb 25 01:30:24 PM PST 24
Finished Feb 25 01:30:26 PM PST 24
Peak memory 217656 kb
Host smart-26dd772f-98cd-44f2-8705-d9deade76850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146076077 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.3146076077
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.129228775
Short name T262
Test name
Test status
Simulation time 32193668 ps
CPU time 1.1 seconds
Started Feb 25 01:30:26 PM PST 24
Finished Feb 25 01:30:28 PM PST 24
Peak memory 217220 kb
Host smart-9a71fec4-4960-4a52-b70e-285cc809986e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129228775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.129228775
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_genbits.3768675233
Short name T521
Test name
Test status
Simulation time 56933647 ps
CPU time 1.2 seconds
Started Feb 25 01:30:35 PM PST 24
Finished Feb 25 01:30:37 PM PST 24
Peak memory 217064 kb
Host smart-4602b73a-3053-4b71-a0de-b1dd61844b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768675233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3768675233
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.180068850
Short name T87
Test name
Test status
Simulation time 27233514 ps
CPU time 1.1 seconds
Started Feb 25 01:30:27 PM PST 24
Finished Feb 25 01:30:29 PM PST 24
Peak memory 217332 kb
Host smart-fbb0eaa3-c112-48b2-ba06-86d001ff9e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180068850 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.180068850
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1421413509
Short name T273
Test name
Test status
Simulation time 137921173 ps
CPU time 2.64 seconds
Started Feb 25 01:30:20 PM PST 24
Finished Feb 25 01:30:23 PM PST 24
Peak memory 218908 kb
Host smart-a3a8dd5d-eafb-4280-b00e-67765db44772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421413509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1421413509
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.3138948010
Short name T90
Test name
Test status
Simulation time 37020772 ps
CPU time 1.16 seconds
Started Feb 25 01:30:24 PM PST 24
Finished Feb 25 01:30:25 PM PST 24
Peak memory 229008 kb
Host smart-d75854b8-0ec4-45da-b0c0-3beb9a035ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138948010 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3138948010
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.888758346
Short name T729
Test name
Test status
Simulation time 58306824 ps
CPU time 1.22 seconds
Started Feb 25 01:30:24 PM PST 24
Finished Feb 25 01:30:26 PM PST 24
Peak memory 215996 kb
Host smart-ff907803-da75-4b12-a279-aefd20c93d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888758346 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.888758346
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.3014824485
Short name T27
Test name
Test status
Simulation time 32994047 ps
CPU time 0.9 seconds
Started Feb 25 01:30:26 PM PST 24
Finished Feb 25 01:30:27 PM PST 24
Peak memory 218732 kb
Host smart-7fe03b4f-13b4-428d-9885-365ac189f528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014824485 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3014824485
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.1336795708
Short name T554
Test name
Test status
Simulation time 50245158 ps
CPU time 1.36 seconds
Started Feb 25 01:30:22 PM PST 24
Finished Feb 25 01:30:23 PM PST 24
Peak memory 217244 kb
Host smart-a3d7131a-d162-4173-a3f2-c284608eaf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336795708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.1336795708
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.3611178691
Short name T490
Test name
Test status
Simulation time 65387238 ps
CPU time 1.14 seconds
Started Feb 25 01:30:21 PM PST 24
Finished Feb 25 01:30:23 PM PST 24
Peak memory 219580 kb
Host smart-feb32a3a-2fb1-4c42-9d90-54e3f52ed616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611178691 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3611178691
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.2322565369
Short name T442
Test name
Test status
Simulation time 30926030 ps
CPU time 1.3 seconds
Started Feb 25 01:30:21 PM PST 24
Finished Feb 25 01:30:22 PM PST 24
Peak memory 218052 kb
Host smart-2eafe604-1990-46f4-a66b-48ad28829ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322565369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.2322565369
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.2692391553
Short name T65
Test name
Test status
Simulation time 67027290 ps
CPU time 0.78 seconds
Started Feb 25 01:30:20 PM PST 24
Finished Feb 25 01:30:21 PM PST 24
Peak memory 216908 kb
Host smart-cfe1ffab-52f4-4a8e-9140-b6e949e39880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692391553 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.2692391553
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.249394145
Short name T143
Test name
Test status
Simulation time 70687326 ps
CPU time 1.29 seconds
Started Feb 25 01:30:26 PM PST 24
Finished Feb 25 01:30:27 PM PST 24
Peak memory 217472 kb
Host smart-4e40f34c-3558-4908-810b-5152f0a1db22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249394145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.249394145
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.2402047581
Short name T45
Test name
Test status
Simulation time 17815990 ps
CPU time 1.19 seconds
Started Feb 25 01:30:26 PM PST 24
Finished Feb 25 01:30:27 PM PST 24
Peak memory 222520 kb
Host smart-ec8bff07-9c85-420b-9867-9d14ad6e580d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402047581 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.2402047581
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.86684964
Short name T493
Test name
Test status
Simulation time 153177877 ps
CPU time 2.21 seconds
Started Feb 25 01:30:28 PM PST 24
Finished Feb 25 01:30:31 PM PST 24
Peak memory 219024 kb
Host smart-9cba4e4e-b2f3-4b1e-8ba9-cf0348a78320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86684964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.86684964
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.39036849
Short name T124
Test name
Test status
Simulation time 25011464 ps
CPU time 1.23 seconds
Started Feb 25 01:28:58 PM PST 24
Finished Feb 25 01:29:00 PM PST 24
Peak memory 215128 kb
Host smart-6ac8022f-a260-45b6-9478-f9d696bc837c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39036849 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.39036849
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.675924909
Short name T308
Test name
Test status
Simulation time 14200657 ps
CPU time 0.95 seconds
Started Feb 25 01:28:56 PM PST 24
Finished Feb 25 01:28:58 PM PST 24
Peak memory 205964 kb
Host smart-90df6790-e050-488d-9c1c-a29d0e779480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675924909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.675924909
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3104697970
Short name T116
Test name
Test status
Simulation time 10177848 ps
CPU time 0.88 seconds
Started Feb 25 01:29:00 PM PST 24
Finished Feb 25 01:29:02 PM PST 24
Peak memory 215116 kb
Host smart-539e249a-58fa-46f9-b9eb-680af757c013
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104697970 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3104697970
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2971191761
Short name T92
Test name
Test status
Simulation time 41540567 ps
CPU time 1.4 seconds
Started Feb 25 01:29:05 PM PST 24
Finished Feb 25 01:29:07 PM PST 24
Peak memory 215888 kb
Host smart-51b11150-f052-462f-8cbf-242a944ecbd0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971191761 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2971191761
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.3886935993
Short name T585
Test name
Test status
Simulation time 35140491 ps
CPU time 1.21 seconds
Started Feb 25 01:28:59 PM PST 24
Finished Feb 25 01:29:01 PM PST 24
Peak memory 229072 kb
Host smart-cff926ff-c4bb-4b6f-b914-1c28251ab4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886935993 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3886935993
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1857347910
Short name T501
Test name
Test status
Simulation time 133827712 ps
CPU time 1.44 seconds
Started Feb 25 01:29:06 PM PST 24
Finished Feb 25 01:29:07 PM PST 24
Peak memory 217328 kb
Host smart-6c41a7d1-394f-4803-a9b4-e8fa7e2765fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857347910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1857347910
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2575235967
Short name T358
Test name
Test status
Simulation time 22423001 ps
CPU time 1.09 seconds
Started Feb 25 01:28:59 PM PST 24
Finished Feb 25 01:29:01 PM PST 24
Peak memory 215012 kb
Host smart-1cac7dc6-69f9-4a7a-97c8-41931c8831ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575235967 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2575235967
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.2130926151
Short name T285
Test name
Test status
Simulation time 33466399 ps
CPU time 0.9 seconds
Started Feb 25 01:28:56 PM PST 24
Finished Feb 25 01:28:57 PM PST 24
Peak memory 206516 kb
Host smart-0dea7294-4def-4296-b319-e951e3105ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130926151 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.2130926151
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3624703633
Short name T465
Test name
Test status
Simulation time 20572981 ps
CPU time 0.98 seconds
Started Feb 25 01:29:00 PM PST 24
Finished Feb 25 01:29:02 PM PST 24
Peak memory 214732 kb
Host smart-6cc0bbf6-4c21-40b2-8d12-3d2fc3b6ad7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624703633 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3624703633
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1459385496
Short name T368
Test name
Test status
Simulation time 307349658 ps
CPU time 2.31 seconds
Started Feb 25 01:29:02 PM PST 24
Finished Feb 25 01:29:04 PM PST 24
Peak memory 214764 kb
Host smart-52299b42-0f1d-4584-9686-1aa1de8f5f37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459385496 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1459385496
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.276675184
Short name T737
Test name
Test status
Simulation time 43880185831 ps
CPU time 255.27 seconds
Started Feb 25 01:28:59 PM PST 24
Finished Feb 25 01:33:15 PM PST 24
Peak memory 218652 kb
Host smart-6dbbdc40-cacd-4514-9de3-44055e4eaeb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276675184 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.276675184
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.947079125
Short name T69
Test name
Test status
Simulation time 23979880 ps
CPU time 1.22 seconds
Started Feb 25 01:30:29 PM PST 24
Finished Feb 25 01:30:30 PM PST 24
Peak memory 216020 kb
Host smart-89d69653-05e8-44b4-aaae-45ff6f513fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947079125 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.947079125
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.4105210250
Short name T362
Test name
Test status
Simulation time 128917664 ps
CPU time 1.44 seconds
Started Feb 25 01:30:29 PM PST 24
Finished Feb 25 01:30:30 PM PST 24
Peak memory 215948 kb
Host smart-d3309356-48ec-40c8-bdc5-e1c983dde5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105210250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.4105210250
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.3949116931
Short name T603
Test name
Test status
Simulation time 67757081 ps
CPU time 1.13 seconds
Started Feb 25 01:30:33 PM PST 24
Finished Feb 25 01:30:34 PM PST 24
Peak memory 216296 kb
Host smart-a6eedc4b-9507-4ccf-b086-9e10c3387848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949116931 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3949116931
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.280418695
Short name T416
Test name
Test status
Simulation time 91632813 ps
CPU time 1.53 seconds
Started Feb 25 01:30:33 PM PST 24
Finished Feb 25 01:30:34 PM PST 24
Peak memory 217640 kb
Host smart-93abf542-ee21-433a-9ea9-4c4263529813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280418695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.280418695
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.3647509136
Short name T167
Test name
Test status
Simulation time 22455712 ps
CPU time 1.1 seconds
Started Feb 25 01:30:30 PM PST 24
Finished Feb 25 01:30:32 PM PST 24
Peak memory 218664 kb
Host smart-727f68e1-3e92-47d9-ace5-3d277f1494da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647509136 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3647509136
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.338687094
Short name T707
Test name
Test status
Simulation time 41162910 ps
CPU time 1.64 seconds
Started Feb 25 01:30:25 PM PST 24
Finished Feb 25 01:30:28 PM PST 24
Peak memory 218484 kb
Host smart-e849ffe7-2c85-4f20-9d95-43f492a4d6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338687094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.338687094
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.1463222007
Short name T533
Test name
Test status
Simulation time 19347210 ps
CPU time 1.18 seconds
Started Feb 25 01:30:26 PM PST 24
Finished Feb 25 01:30:28 PM PST 24
Peak memory 230716 kb
Host smart-523587dd-0fe4-4abb-9a21-7a96872b5085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463222007 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1463222007
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1310440434
Short name T497
Test name
Test status
Simulation time 104947573 ps
CPU time 1.71 seconds
Started Feb 25 01:30:32 PM PST 24
Finished Feb 25 01:30:34 PM PST 24
Peak memory 216112 kb
Host smart-a23f4006-8547-4978-92df-88afba173e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310440434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1310440434
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.3390479237
Short name T320
Test name
Test status
Simulation time 24105505 ps
CPU time 1.2 seconds
Started Feb 25 01:30:41 PM PST 24
Finished Feb 25 01:30:42 PM PST 24
Peak memory 216364 kb
Host smart-c2d79215-ce57-4d87-84ea-5689dd4c03a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390479237 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3390479237
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2382269361
Short name T38
Test name
Test status
Simulation time 31790602 ps
CPU time 1.39 seconds
Started Feb 25 01:30:33 PM PST 24
Finished Feb 25 01:30:34 PM PST 24
Peak memory 216004 kb
Host smart-2ae7a9ce-0511-427d-9256-e68b9fcc3b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382269361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2382269361
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.3180817931
Short name T703
Test name
Test status
Simulation time 18282496 ps
CPU time 1.05 seconds
Started Feb 25 01:30:27 PM PST 24
Finished Feb 25 01:30:29 PM PST 24
Peak memory 217356 kb
Host smart-71c35da4-7fcb-4df7-9d5d-93c98c424d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180817931 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3180817931
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/66.edn_err.1731815797
Short name T819
Test name
Test status
Simulation time 22743211 ps
CPU time 1.05 seconds
Started Feb 25 01:30:41 PM PST 24
Finished Feb 25 01:30:42 PM PST 24
Peak memory 217388 kb
Host smart-dfb21c6b-74c2-4004-bc8a-e2f9d3543699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731815797 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1731815797
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1594573962
Short name T546
Test name
Test status
Simulation time 86553468 ps
CPU time 3.13 seconds
Started Feb 25 01:30:40 PM PST 24
Finished Feb 25 01:30:44 PM PST 24
Peak memory 217232 kb
Host smart-14056a2b-41a9-4131-b1a7-548083ce605e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594573962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1594573962
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.1497137499
Short name T616
Test name
Test status
Simulation time 29487656 ps
CPU time 1.23 seconds
Started Feb 25 01:30:27 PM PST 24
Finished Feb 25 01:30:29 PM PST 24
Peak memory 218628 kb
Host smart-badec4a2-125e-48ef-bcc2-43eeaa58dd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497137499 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.1497137499
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1980242224
Short name T782
Test name
Test status
Simulation time 89942891 ps
CPU time 1.36 seconds
Started Feb 25 01:30:21 PM PST 24
Finished Feb 25 01:30:23 PM PST 24
Peak memory 217368 kb
Host smart-1248a7d6-a704-4be7-b185-c93dfbf43edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980242224 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1980242224
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.287370960
Short name T820
Test name
Test status
Simulation time 59299210 ps
CPU time 0.83 seconds
Started Feb 25 01:30:37 PM PST 24
Finished Feb 25 01:30:38 PM PST 24
Peak memory 216916 kb
Host smart-635974fa-0379-4f65-a5d3-d3aecbdb4d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287370960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.287370960
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.1692786058
Short name T485
Test name
Test status
Simulation time 53908529 ps
CPU time 0.96 seconds
Started Feb 25 01:30:27 PM PST 24
Finished Feb 25 01:30:29 PM PST 24
Peak memory 216012 kb
Host smart-4c01170c-4101-4b87-a1c0-b502b1598d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692786058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.1692786058
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.1554703858
Short name T1
Test name
Test status
Simulation time 37031365 ps
CPU time 0.92 seconds
Started Feb 25 01:30:38 PM PST 24
Finished Feb 25 01:30:39 PM PST 24
Peak memory 216144 kb
Host smart-8105f83f-7e9e-4c8f-91ae-d76a00da16b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554703858 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.1554703858
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1576581811
Short name T450
Test name
Test status
Simulation time 28669457 ps
CPU time 1.31 seconds
Started Feb 25 01:30:40 PM PST 24
Finished Feb 25 01:30:41 PM PST 24
Peak memory 218720 kb
Host smart-4b4d2f22-64bb-4535-8f56-22c4830b8abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576581811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1576581811
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.629877932
Short name T705
Test name
Test status
Simulation time 25461952 ps
CPU time 1.19 seconds
Started Feb 25 01:29:05 PM PST 24
Finished Feb 25 01:29:06 PM PST 24
Peak memory 215064 kb
Host smart-0c4d36d2-37e5-41a4-9dd2-67d520f2a48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629877932 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.629877932
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.471223150
Short name T152
Test name
Test status
Simulation time 42891165 ps
CPU time 0.87 seconds
Started Feb 25 01:28:58 PM PST 24
Finished Feb 25 01:28:59 PM PST 24
Peak memory 206120 kb
Host smart-84b8b7db-728a-4615-9504-4183db423df6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471223150 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.471223150
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.4193753876
Short name T403
Test name
Test status
Simulation time 25315875 ps
CPU time 0.87 seconds
Started Feb 25 01:28:57 PM PST 24
Finished Feb 25 01:28:58 PM PST 24
Peak memory 214788 kb
Host smart-64d4a113-0741-49a8-928a-0351384c46f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193753876 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.4193753876
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3681053890
Short name T779
Test name
Test status
Simulation time 90773195 ps
CPU time 1.04 seconds
Started Feb 25 01:28:59 PM PST 24
Finished Feb 25 01:29:01 PM PST 24
Peak memory 215964 kb
Host smart-3039fffc-9855-4666-9daf-3dbad8fa3763
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681053890 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3681053890
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3362784866
Short name T48
Test name
Test status
Simulation time 46504935 ps
CPU time 1.08 seconds
Started Feb 25 01:28:58 PM PST 24
Finished Feb 25 01:29:00 PM PST 24
Peak memory 230564 kb
Host smart-b54de890-6f90-43be-a139-7d689bebdd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362784866 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3362784866
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.122463504
Short name T464
Test name
Test status
Simulation time 84755539 ps
CPU time 1.15 seconds
Started Feb 25 01:29:03 PM PST 24
Finished Feb 25 01:29:04 PM PST 24
Peak memory 216076 kb
Host smart-2c2e3abd-6189-4e32-b8d5-64f82b651ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122463504 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.122463504
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.3442457901
Short name T712
Test name
Test status
Simulation time 31852007 ps
CPU time 0.98 seconds
Started Feb 25 01:28:59 PM PST 24
Finished Feb 25 01:29:01 PM PST 24
Peak memory 222596 kb
Host smart-24684153-7652-4bad-bb4f-0d5a082f039d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442457901 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3442457901
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.57377900
Short name T290
Test name
Test status
Simulation time 18244079 ps
CPU time 1.06 seconds
Started Feb 25 01:29:02 PM PST 24
Finished Feb 25 01:29:03 PM PST 24
Peak memory 206568 kb
Host smart-05285ed5-d7af-47b2-b1d5-1a8415603bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57377900 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.57377900
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.4165746182
Short name T408
Test name
Test status
Simulation time 24871750 ps
CPU time 0.94 seconds
Started Feb 25 01:28:57 PM PST 24
Finished Feb 25 01:28:59 PM PST 24
Peak memory 214776 kb
Host smart-3733883b-5268-449f-bd0e-c93e9b3e665f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165746182 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.4165746182
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2145131866
Short name T334
Test name
Test status
Simulation time 66154656 ps
CPU time 1.88 seconds
Started Feb 25 01:29:09 PM PST 24
Finished Feb 25 01:29:11 PM PST 24
Peak memory 215844 kb
Host smart-696b4450-38e7-4d55-b844-4d435a3256c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145131866 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2145131866
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.242267519
Short name T197
Test name
Test status
Simulation time 196151288677 ps
CPU time 1009.25 seconds
Started Feb 25 01:29:00 PM PST 24
Finished Feb 25 01:45:51 PM PST 24
Peak memory 221220 kb
Host smart-6e6e3e97-fe13-4928-a8b2-9edb82d509d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242267519 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.242267519
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.2431912974
Short name T384
Test name
Test status
Simulation time 28909394 ps
CPU time 0.86 seconds
Started Feb 25 01:30:35 PM PST 24
Finished Feb 25 01:30:36 PM PST 24
Peak memory 216988 kb
Host smart-e02dce53-d438-47af-a707-24bf41a3fc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431912974 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.2431912974
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.720000814
Short name T248
Test name
Test status
Simulation time 51530048 ps
CPU time 1.48 seconds
Started Feb 25 01:30:37 PM PST 24
Finished Feb 25 01:30:39 PM PST 24
Peak memory 217600 kb
Host smart-6f92ef97-00e9-445e-b886-925a16afcf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720000814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.720000814
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.664033184
Short name T81
Test name
Test status
Simulation time 48501174 ps
CPU time 1.03 seconds
Started Feb 25 01:30:38 PM PST 24
Finished Feb 25 01:30:39 PM PST 24
Peak memory 218612 kb
Host smart-3856c653-bf5a-4fa4-b91f-29c9b913f9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664033184 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.664033184
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1992653732
Short name T446
Test name
Test status
Simulation time 37756286 ps
CPU time 1.42 seconds
Started Feb 25 01:30:38 PM PST 24
Finished Feb 25 01:30:40 PM PST 24
Peak memory 215976 kb
Host smart-9bda1c66-2909-4949-933c-30428be31ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992653732 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1992653732
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.3293314927
Short name T606
Test name
Test status
Simulation time 56710485 ps
CPU time 1.01 seconds
Started Feb 25 01:30:32 PM PST 24
Finished Feb 25 01:30:34 PM PST 24
Peak memory 219464 kb
Host smart-533a41de-fc44-4117-8799-fa56fc924da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293314927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3293314927
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3526274899
Short name T429
Test name
Test status
Simulation time 43591857 ps
CPU time 1.75 seconds
Started Feb 25 01:30:36 PM PST 24
Finished Feb 25 01:30:38 PM PST 24
Peak memory 217332 kb
Host smart-6253085f-3579-4d10-8b44-b5538f7232fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526274899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3526274899
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.4023534539
Short name T808
Test name
Test status
Simulation time 31255012 ps
CPU time 1.04 seconds
Started Feb 25 01:30:37 PM PST 24
Finished Feb 25 01:30:39 PM PST 24
Peak memory 229132 kb
Host smart-3429fb4b-8732-4186-9229-98351879b605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023534539 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.4023534539
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.4196131556
Short name T39
Test name
Test status
Simulation time 36062460 ps
CPU time 1.4 seconds
Started Feb 25 01:30:38 PM PST 24
Finished Feb 25 01:30:39 PM PST 24
Peak memory 217356 kb
Host smart-85e28162-daf3-4921-a227-175bfe270604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196131556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.4196131556
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.1207500198
Short name T179
Test name
Test status
Simulation time 54016159 ps
CPU time 1.07 seconds
Started Feb 25 01:30:38 PM PST 24
Finished Feb 25 01:30:39 PM PST 24
Peak memory 219568 kb
Host smart-217aebd8-533e-43cf-81f4-0c5728873f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207500198 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1207500198
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.715188755
Short name T687
Test name
Test status
Simulation time 72550063 ps
CPU time 1.19 seconds
Started Feb 25 01:30:36 PM PST 24
Finished Feb 25 01:30:37 PM PST 24
Peak memory 218392 kb
Host smart-714d6a49-5948-4868-9dee-116066c19c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715188755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.715188755
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.522924665
Short name T111
Test name
Test status
Simulation time 19565109 ps
CPU time 1.17 seconds
Started Feb 25 01:30:44 PM PST 24
Finished Feb 25 01:30:45 PM PST 24
Peak memory 222440 kb
Host smart-a1c02781-7297-479d-9d11-3dcf3608ba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522924665 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.522924665
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2174846828
Short name T694
Test name
Test status
Simulation time 81600883 ps
CPU time 1.23 seconds
Started Feb 25 01:30:44 PM PST 24
Finished Feb 25 01:30:46 PM PST 24
Peak memory 217372 kb
Host smart-8cfa6434-ec81-4987-b37d-ed1403c1fe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174846828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2174846828
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.836455056
Short name T475
Test name
Test status
Simulation time 45920819 ps
CPU time 0.81 seconds
Started Feb 25 01:30:43 PM PST 24
Finished Feb 25 01:30:44 PM PST 24
Peak memory 216940 kb
Host smart-2580fd27-fc4c-40ac-b6ef-e81e975b7625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836455056 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.836455056
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1479318690
Short name T715
Test name
Test status
Simulation time 50782724 ps
CPU time 1.03 seconds
Started Feb 25 01:30:38 PM PST 24
Finished Feb 25 01:30:39 PM PST 24
Peak memory 215940 kb
Host smart-a05cc082-2735-4c3b-b9be-da84320f51fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479318690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1479318690
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.1578754704
Short name T164
Test name
Test status
Simulation time 91142972 ps
CPU time 1.14 seconds
Started Feb 25 01:30:41 PM PST 24
Finished Feb 25 01:30:42 PM PST 24
Peak memory 218736 kb
Host smart-efc0e52a-6c0c-44f8-a92f-bbeb44356c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578754704 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1578754704
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.4047875
Short name T370
Test name
Test status
Simulation time 67801656 ps
CPU time 1.18 seconds
Started Feb 25 01:30:47 PM PST 24
Finished Feb 25 01:30:48 PM PST 24
Peak memory 217476 kb
Host smart-9363c625-27df-445f-bc88-de7f04e5f61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.4047875
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.206454261
Short name T173
Test name
Test status
Simulation time 67602650 ps
CPU time 1.17 seconds
Started Feb 25 01:30:44 PM PST 24
Finished Feb 25 01:30:45 PM PST 24
Peak memory 231680 kb
Host smart-510e7a5c-6c1a-4523-b741-ceb14341f1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206454261 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.206454261
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.195935315
Short name T823
Test name
Test status
Simulation time 38230583 ps
CPU time 1.39 seconds
Started Feb 25 01:30:46 PM PST 24
Finished Feb 25 01:30:48 PM PST 24
Peak memory 218308 kb
Host smart-a37e130c-4c60-4986-b142-97ccc8be836b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195935315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.195935315
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.3114957868
Short name T125
Test name
Test status
Simulation time 71091610 ps
CPU time 0.8 seconds
Started Feb 25 01:30:40 PM PST 24
Finished Feb 25 01:30:41 PM PST 24
Peak memory 216924 kb
Host smart-ebd8fd82-e927-4231-a76a-f047a8208d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114957868 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3114957868
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2095196419
Short name T499
Test name
Test status
Simulation time 93890910 ps
CPU time 1.19 seconds
Started Feb 25 01:30:41 PM PST 24
Finished Feb 25 01:30:42 PM PST 24
Peak memory 215864 kb
Host smart-f39667a9-f062-4fe9-9d5c-e8ccac6b2f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095196419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2095196419
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2039642297
Short name T624
Test name
Test status
Simulation time 90705613 ps
CPU time 1.24 seconds
Started Feb 25 01:29:10 PM PST 24
Finished Feb 25 01:29:12 PM PST 24
Peak memory 215116 kb
Host smart-d58ea916-1892-4f7d-be2f-12fb5f4b2a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039642297 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2039642297
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2526464756
Short name T803
Test name
Test status
Simulation time 44243413 ps
CPU time 0.85 seconds
Started Feb 25 01:29:12 PM PST 24
Finished Feb 25 01:29:13 PM PST 24
Peak memory 206052 kb
Host smart-fd9c3c07-197f-4395-9c21-3d436fcb9534
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526464756 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2526464756
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.4087042540
Short name T174
Test name
Test status
Simulation time 17827639 ps
CPU time 0.85 seconds
Started Feb 25 01:29:13 PM PST 24
Finished Feb 25 01:29:14 PM PST 24
Peak memory 215112 kb
Host smart-2d8221e5-7c8e-40c9-967a-1036ebd581fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087042540 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.4087042540
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_err.1247224282
Short name T647
Test name
Test status
Simulation time 56009946 ps
CPU time 1 seconds
Started Feb 25 01:29:12 PM PST 24
Finished Feb 25 01:29:13 PM PST 24
Peak memory 218868 kb
Host smart-4dd4449f-2f90-4c77-93ea-eb1089815a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247224282 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1247224282
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.2235965149
Short name T601
Test name
Test status
Simulation time 103664741 ps
CPU time 1.57 seconds
Started Feb 25 01:29:11 PM PST 24
Finished Feb 25 01:29:13 PM PST 24
Peak memory 217440 kb
Host smart-132fce7a-8ae7-41ac-9cdb-30b0f6182ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235965149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2235965149
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1309101794
Short name T382
Test name
Test status
Simulation time 40850444 ps
CPU time 0.9 seconds
Started Feb 25 01:29:11 PM PST 24
Finished Feb 25 01:29:13 PM PST 24
Peak memory 214652 kb
Host smart-3a6c9f1e-2de9-449d-8b4b-fbdba79689da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309101794 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1309101794
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.2813774478
Short name T299
Test name
Test status
Simulation time 25362303 ps
CPU time 0.91 seconds
Started Feb 25 01:29:04 PM PST 24
Finished Feb 25 01:29:05 PM PST 24
Peak memory 206508 kb
Host smart-b1916e5e-2e72-4468-9b26-5608e3b6b327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813774478 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2813774478
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2650700983
Short name T303
Test name
Test status
Simulation time 17718997 ps
CPU time 0.99 seconds
Started Feb 25 01:29:06 PM PST 24
Finished Feb 25 01:29:08 PM PST 24
Peak memory 214716 kb
Host smart-25712e17-590e-4531-a22f-2f9d9fbfec78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650700983 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2650700983
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.3042666918
Short name T325
Test name
Test status
Simulation time 365897667 ps
CPU time 3.96 seconds
Started Feb 25 01:29:12 PM PST 24
Finished Feb 25 01:29:16 PM PST 24
Peak memory 216072 kb
Host smart-88593f2d-896d-4d15-912b-45f66b5ca8bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042666918 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.3042666918
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3761276048
Short name T430
Test name
Test status
Simulation time 62782447572 ps
CPU time 691.57 seconds
Started Feb 25 01:29:14 PM PST 24
Finished Feb 25 01:40:46 PM PST 24
Peak memory 223024 kb
Host smart-0068d683-9760-4bff-a2f9-9664c7b4a94f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761276048 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3761276048
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.191603889
Short name T112
Test name
Test status
Simulation time 18730097 ps
CPU time 0.97 seconds
Started Feb 25 01:30:46 PM PST 24
Finished Feb 25 01:30:47 PM PST 24
Peak memory 217100 kb
Host smart-bca074de-8157-460a-8170-ebdb38c47ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191603889 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.191603889
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.4202528896
Short name T310
Test name
Test status
Simulation time 37472802 ps
CPU time 1.32 seconds
Started Feb 25 01:30:44 PM PST 24
Finished Feb 25 01:30:46 PM PST 24
Peak memory 215740 kb
Host smart-5a6c02ed-28b7-4f7a-9566-03ba00674189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202528896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.4202528896
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.3247273217
Short name T95
Test name
Test status
Simulation time 30541120 ps
CPU time 0.85 seconds
Started Feb 25 01:30:44 PM PST 24
Finished Feb 25 01:30:45 PM PST 24
Peak memory 217060 kb
Host smart-4c3f35cf-5494-4a0d-9e97-bf03763ef9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247273217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3247273217
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1141713145
Short name T418
Test name
Test status
Simulation time 31869845 ps
CPU time 1.37 seconds
Started Feb 25 01:30:40 PM PST 24
Finished Feb 25 01:30:42 PM PST 24
Peak memory 217416 kb
Host smart-0306f01a-d1a4-4532-85b7-3a812569c716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141713145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1141713145
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.1298727193
Short name T11
Test name
Test status
Simulation time 31028816 ps
CPU time 1.35 seconds
Started Feb 25 01:30:48 PM PST 24
Finished Feb 25 01:30:49 PM PST 24
Peak memory 223760 kb
Host smart-481d8309-68af-4918-800b-ac213a1cf384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298727193 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1298727193
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3353992399
Short name T191
Test name
Test status
Simulation time 89900553 ps
CPU time 1.23 seconds
Started Feb 25 01:30:48 PM PST 24
Finished Feb 25 01:30:50 PM PST 24
Peak memory 217356 kb
Host smart-a27019a6-1e68-41c5-abbf-7328e6bbbe4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353992399 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3353992399
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.3040863146
Short name T62
Test name
Test status
Simulation time 81221158 ps
CPU time 0.83 seconds
Started Feb 25 01:30:40 PM PST 24
Finished Feb 25 01:30:41 PM PST 24
Peak memory 217392 kb
Host smart-56d860e9-5a9e-4287-8e6c-b53ca4d66a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040863146 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3040863146
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2061641985
Short name T413
Test name
Test status
Simulation time 101461523 ps
CPU time 1.26 seconds
Started Feb 25 01:30:48 PM PST 24
Finished Feb 25 01:30:49 PM PST 24
Peak memory 215900 kb
Host smart-d6760c85-fbb9-40ca-9d8d-437e49388760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061641985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2061641985
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.2626849617
Short name T117
Test name
Test status
Simulation time 18934510 ps
CPU time 1.12 seconds
Started Feb 25 01:30:40 PM PST 24
Finished Feb 25 01:30:42 PM PST 24
Peak memory 217484 kb
Host smart-ea2cf08f-5fbb-41fc-abec-1c4aba6f1dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626849617 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2626849617
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.2092738049
Short name T140
Test name
Test status
Simulation time 143551036 ps
CPU time 1.21 seconds
Started Feb 25 01:30:47 PM PST 24
Finished Feb 25 01:30:48 PM PST 24
Peak memory 217296 kb
Host smart-97e82217-0b48-4439-a752-3679da3df166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092738049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.2092738049
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.2856536023
Short name T697
Test name
Test status
Simulation time 32747432 ps
CPU time 1.24 seconds
Started Feb 25 01:30:41 PM PST 24
Finished Feb 25 01:30:42 PM PST 24
Peak memory 230724 kb
Host smart-b00667c0-57cf-4abb-88f4-cc5820b6eec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856536023 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2856536023
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/86.edn_err.3521263302
Short name T99
Test name
Test status
Simulation time 19567158 ps
CPU time 1.2 seconds
Started Feb 25 01:30:44 PM PST 24
Finished Feb 25 01:30:45 PM PST 24
Peak memory 230660 kb
Host smart-e2b15db2-5e60-45b6-8daf-acdbad3866eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521263302 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.3521263302
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.4234912537
Short name T719
Test name
Test status
Simulation time 66130254 ps
CPU time 1.62 seconds
Started Feb 25 01:30:47 PM PST 24
Finished Feb 25 01:30:48 PM PST 24
Peak memory 217464 kb
Host smart-adf42501-24f2-4ccf-8997-67ac6e8e25c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234912537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.4234912537
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1393307768
Short name T589
Test name
Test status
Simulation time 103093460 ps
CPU time 1.1 seconds
Started Feb 25 01:30:44 PM PST 24
Finished Feb 25 01:30:45 PM PST 24
Peak memory 229240 kb
Host smart-6712ca08-9019-40bd-a3a7-273052389ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393307768 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1393307768
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.634929584
Short name T748
Test name
Test status
Simulation time 208607040 ps
CPU time 1.03 seconds
Started Feb 25 01:30:47 PM PST 24
Finished Feb 25 01:30:48 PM PST 24
Peak memory 216116 kb
Host smart-ea0761da-1346-41cf-a696-56a4230db479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634929584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.634929584
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.760405688
Short name T536
Test name
Test status
Simulation time 32662210 ps
CPU time 0.85 seconds
Started Feb 25 01:30:47 PM PST 24
Finished Feb 25 01:30:48 PM PST 24
Peak memory 217004 kb
Host smart-d842de74-3172-4c7d-9365-c7261d8aab2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760405688 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.760405688
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.4202046219
Short name T50
Test name
Test status
Simulation time 31523136 ps
CPU time 1.29 seconds
Started Feb 25 01:30:39 PM PST 24
Finished Feb 25 01:30:41 PM PST 24
Peak memory 218468 kb
Host smart-9e932887-38b1-40a6-8253-fbd4c2e2d873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202046219 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.4202046219
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.3677376280
Short name T78
Test name
Test status
Simulation time 27067226 ps
CPU time 1.21 seconds
Started Feb 25 01:30:46 PM PST 24
Finished Feb 25 01:30:47 PM PST 24
Peak memory 215824 kb
Host smart-f8977eb4-665f-478f-b33e-5848f8adfad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677376280 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3677376280
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2669787336
Short name T516
Test name
Test status
Simulation time 88765426 ps
CPU time 1.37 seconds
Started Feb 25 01:30:46 PM PST 24
Finished Feb 25 01:30:48 PM PST 24
Peak memory 216280 kb
Host smart-7a40f373-e127-4f99-98f6-a758e420acc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669787336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2669787336
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.326525267
Short name T298
Test name
Test status
Simulation time 78644566 ps
CPU time 1.14 seconds
Started Feb 25 01:29:15 PM PST 24
Finished Feb 25 01:29:16 PM PST 24
Peak memory 215076 kb
Host smart-776a7df4-a6fb-44f3-805b-b7d304b60fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326525267 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.326525267
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2165135779
Short name T335
Test name
Test status
Simulation time 56986078 ps
CPU time 0.89 seconds
Started Feb 25 01:29:12 PM PST 24
Finished Feb 25 01:29:13 PM PST 24
Peak memory 205892 kb
Host smart-40cede51-f98e-4754-b49b-2a7d76a68e57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165135779 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2165135779
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3117661555
Short name T182
Test name
Test status
Simulation time 18283987 ps
CPU time 0.85 seconds
Started Feb 25 01:29:13 PM PST 24
Finished Feb 25 01:29:14 PM PST 24
Peak memory 214832 kb
Host smart-294abcf0-d225-4756-aa7f-e4c4e20eb942
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117661555 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3117661555
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.1323375530
Short name T565
Test name
Test status
Simulation time 58890227 ps
CPU time 0.99 seconds
Started Feb 25 01:29:08 PM PST 24
Finished Feb 25 01:29:09 PM PST 24
Peak memory 216948 kb
Host smart-1b9b92cf-99ab-4411-bf19-4ac5f0064a91
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323375530 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.1323375530
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.1657456335
Short name T160
Test name
Test status
Simulation time 97751069 ps
CPU time 1.16 seconds
Started Feb 25 01:29:16 PM PST 24
Finished Feb 25 01:29:18 PM PST 24
Peak memory 229128 kb
Host smart-6bb83f12-f93c-48f1-ab01-45c2a7c168cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657456335 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.1657456335
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.2032941810
Short name T594
Test name
Test status
Simulation time 68895046 ps
CPU time 1.06 seconds
Started Feb 25 01:29:07 PM PST 24
Finished Feb 25 01:29:08 PM PST 24
Peak memory 217532 kb
Host smart-974abbbb-1be6-4edb-98d7-99334350e6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032941810 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2032941810
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.3251665183
Short name T139
Test name
Test status
Simulation time 20181313 ps
CPU time 1.06 seconds
Started Feb 25 01:29:16 PM PST 24
Finished Feb 25 01:29:18 PM PST 24
Peak memory 215244 kb
Host smart-6b611bd1-c18e-41aa-bca9-d41c546802f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251665183 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.3251665183
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_smoke.1707764165
Short name T349
Test name
Test status
Simulation time 40350296 ps
CPU time 0.9 seconds
Started Feb 25 01:29:10 PM PST 24
Finished Feb 25 01:29:11 PM PST 24
Peak memory 214708 kb
Host smart-4cb571f6-a34e-45c7-a179-5f7219d66cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707764165 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1707764165
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2839004637
Short name T466
Test name
Test status
Simulation time 674463348 ps
CPU time 3.2 seconds
Started Feb 25 01:29:09 PM PST 24
Finished Feb 25 01:29:12 PM PST 24
Peak memory 215832 kb
Host smart-dcd87acc-61c2-4985-ac85-99552e8249ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839004637 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2839004637
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.800533103
Short name T799
Test name
Test status
Simulation time 13198554463 ps
CPU time 301.12 seconds
Started Feb 25 01:29:14 PM PST 24
Finished Feb 25 01:34:16 PM PST 24
Peak memory 216728 kb
Host smart-ec0f321b-1db3-4b18-803e-b1c445306091
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800533103 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.800533103
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.2907546350
Short name T166
Test name
Test status
Simulation time 43120767 ps
CPU time 1 seconds
Started Feb 25 01:30:40 PM PST 24
Finished Feb 25 01:30:41 PM PST 24
Peak memory 214964 kb
Host smart-3a9cc423-c1cd-4e84-87ca-d43070fc4f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907546350 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.2907546350
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1072202505
Short name T505
Test name
Test status
Simulation time 52634305 ps
CPU time 1.24 seconds
Started Feb 25 01:30:47 PM PST 24
Finished Feb 25 01:30:49 PM PST 24
Peak memory 216196 kb
Host smart-2acbaf9b-dbd3-4052-b683-322fa80b41c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072202505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1072202505
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_genbits.1105767286
Short name T644
Test name
Test status
Simulation time 42772220 ps
CPU time 1.53 seconds
Started Feb 25 01:30:47 PM PST 24
Finished Feb 25 01:30:49 PM PST 24
Peak memory 217148 kb
Host smart-668a13ec-7448-4c82-8cd1-e1a0e7400659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105767286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1105767286
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.726165693
Short name T126
Test name
Test status
Simulation time 69720674 ps
CPU time 0.83 seconds
Started Feb 25 01:30:40 PM PST 24
Finished Feb 25 01:30:41 PM PST 24
Peak memory 217168 kb
Host smart-0ef4bc20-bfb9-4195-8f11-b795d3a92360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726165693 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.726165693
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1523987148
Short name T209
Test name
Test status
Simulation time 248816881 ps
CPU time 3.67 seconds
Started Feb 25 01:30:39 PM PST 24
Finished Feb 25 01:30:43 PM PST 24
Peak memory 216244 kb
Host smart-2238441d-5787-4e9e-be02-3d173bd091de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523987148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1523987148
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.1745659236
Short name T711
Test name
Test status
Simulation time 32962171 ps
CPU time 0.87 seconds
Started Feb 25 01:30:39 PM PST 24
Finished Feb 25 01:30:40 PM PST 24
Peak memory 214808 kb
Host smart-3c5dc68d-8e9f-4ea6-b431-404202718045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745659236 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1745659236
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.1446081047
Short name T435
Test name
Test status
Simulation time 66750568 ps
CPU time 1.06 seconds
Started Feb 25 01:30:41 PM PST 24
Finished Feb 25 01:30:42 PM PST 24
Peak memory 215996 kb
Host smart-c8319a07-42a7-4a21-9d77-45472e3ea3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446081047 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.1446081047
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.1648643946
Short name T101
Test name
Test status
Simulation time 39691337 ps
CPU time 0.92 seconds
Started Feb 25 01:30:46 PM PST 24
Finished Feb 25 01:30:47 PM PST 24
Peak memory 217396 kb
Host smart-b986ca1f-eb53-49a8-99c5-5bf57e1ae94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648643946 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1648643946
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2951901413
Short name T522
Test name
Test status
Simulation time 51637193 ps
CPU time 1.75 seconds
Started Feb 25 01:30:50 PM PST 24
Finished Feb 25 01:30:52 PM PST 24
Peak memory 218800 kb
Host smart-b830ff49-8033-4f90-bbf6-bd40c8101c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951901413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2951901413
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.1425945211
Short name T66
Test name
Test status
Simulation time 35767912 ps
CPU time 0.94 seconds
Started Feb 25 01:30:40 PM PST 24
Finished Feb 25 01:30:41 PM PST 24
Peak memory 218692 kb
Host smart-f0c15ea0-7858-4379-a283-5514cf07e66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425945211 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1425945211
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1106419074
Short name T366
Test name
Test status
Simulation time 33224770 ps
CPU time 1.3 seconds
Started Feb 25 01:30:45 PM PST 24
Finished Feb 25 01:30:47 PM PST 24
Peak memory 218192 kb
Host smart-ade4d4b1-3ebe-46ce-ad58-c705c8ec720f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106419074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1106419074
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.4144469301
Short name T46
Test name
Test status
Simulation time 27414540 ps
CPU time 1.03 seconds
Started Feb 25 01:30:39 PM PST 24
Finished Feb 25 01:30:40 PM PST 24
Peak memory 222572 kb
Host smart-7b165d8c-7271-44a3-81bd-a81f8767a778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144469301 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.4144469301
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2300250009
Short name T52
Test name
Test status
Simulation time 37987665 ps
CPU time 1.07 seconds
Started Feb 25 01:30:45 PM PST 24
Finished Feb 25 01:30:46 PM PST 24
Peak memory 217144 kb
Host smart-2233507a-38d2-41b5-bf5e-e1ecaba00c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300250009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2300250009
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.842353399
Short name T433
Test name
Test status
Simulation time 22760034 ps
CPU time 0.96 seconds
Started Feb 25 01:30:50 PM PST 24
Finished Feb 25 01:30:51 PM PST 24
Peak memory 217484 kb
Host smart-c749649b-9f3f-4c47-a0ef-5024ed20c8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842353399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.842353399
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/98.edn_err.3149368010
Short name T415
Test name
Test status
Simulation time 23645196 ps
CPU time 1.12 seconds
Started Feb 25 01:30:53 PM PST 24
Finished Feb 25 01:30:54 PM PST 24
Peak memory 217568 kb
Host smart-3827fec8-c8bd-49b5-910a-6d89f042a91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149368010 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3149368010
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2218600118
Short name T795
Test name
Test status
Simulation time 124336757 ps
CPU time 2.96 seconds
Started Feb 25 01:30:54 PM PST 24
Finished Feb 25 01:30:57 PM PST 24
Peak memory 219128 kb
Host smart-e4b686c9-9007-40a5-a636-b3efff685fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218600118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2218600118
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.3368998453
Short name T83
Test name
Test status
Simulation time 25104776 ps
CPU time 1.16 seconds
Started Feb 25 01:30:54 PM PST 24
Finished Feb 25 01:30:55 PM PST 24
Peak memory 216228 kb
Host smart-d4fd5ede-6a4d-404d-99a5-b5a0fcdb1361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368998453 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3368998453
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1706567457
Short name T333
Test name
Test status
Simulation time 58094172 ps
CPU time 1.01 seconds
Started Feb 25 01:30:55 PM PST 24
Finished Feb 25 01:30:56 PM PST 24
Peak memory 215768 kb
Host smart-30532491-3ece-456c-b8ca-b267c4f1907f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706567457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1706567457
Directory /workspace/99.edn_genbits/latest
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