Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.63 98.27 93.44 96.79 80.35 96.87 96.58 93.15


Total test records in report: 968
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T791 /workspace/coverage/default/184.edn_genbits.1352768390 Feb 29 01:41:58 PM PST 24 Feb 29 01:41:59 PM PST 24 37741080 ps
T792 /workspace/coverage/default/1.edn_stress_all.2833442501 Feb 29 01:39:53 PM PST 24 Feb 29 01:39:56 PM PST 24 81858455 ps
T263 /workspace/coverage/default/1.edn_alert.2764921849 Feb 29 01:39:56 PM PST 24 Feb 29 01:39:57 PM PST 24 38652519 ps
T82 /workspace/coverage/default/13.edn_err.1552688817 Feb 29 01:40:30 PM PST 24 Feb 29 01:40:32 PM PST 24 23783900 ps
T793 /workspace/coverage/default/45.edn_smoke.72016656 Feb 29 01:41:21 PM PST 24 Feb 29 01:41:22 PM PST 24 16200375 ps
T794 /workspace/coverage/default/41.edn_intr.939160929 Feb 29 01:41:19 PM PST 24 Feb 29 01:41:21 PM PST 24 22583180 ps
T795 /workspace/coverage/default/169.edn_genbits.3225249690 Feb 29 01:42:05 PM PST 24 Feb 29 01:42:07 PM PST 24 81596251 ps
T796 /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3837153501 Feb 29 01:40:52 PM PST 24 Feb 29 02:03:13 PM PST 24 112724109737 ps
T797 /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2081935693 Feb 29 01:41:33 PM PST 24 Feb 29 01:53:32 PM PST 24 31655429948 ps
T268 /workspace/coverage/default/4.edn_regwen.724876177 Feb 29 01:40:09 PM PST 24 Feb 29 01:40:11 PM PST 24 41527015 ps
T798 /workspace/coverage/default/116.edn_genbits.2976957936 Feb 29 01:41:53 PM PST 24 Feb 29 01:41:54 PM PST 24 84244099 ps
T799 /workspace/coverage/default/4.edn_disable_auto_req_mode.2595901293 Feb 29 01:40:09 PM PST 24 Feb 29 01:40:11 PM PST 24 85225953 ps
T800 /workspace/coverage/default/14.edn_alert.85863758 Feb 29 01:40:33 PM PST 24 Feb 29 01:40:34 PM PST 24 26936876 ps
T801 /workspace/coverage/default/24.edn_disable_auto_req_mode.1375031392 Feb 29 01:40:56 PM PST 24 Feb 29 01:40:58 PM PST 24 41789282 ps
T802 /workspace/coverage/default/287.edn_genbits.2223944568 Feb 29 01:42:31 PM PST 24 Feb 29 01:42:33 PM PST 24 53248287 ps
T803 /workspace/coverage/default/30.edn_alert_test.1759956084 Feb 29 01:40:51 PM PST 24 Feb 29 01:40:52 PM PST 24 109907089 ps
T45 /workspace/coverage/default/0.edn_sec_cm.1074399764 Feb 29 01:39:55 PM PST 24 Feb 29 01:40:00 PM PST 24 919493376 ps
T804 /workspace/coverage/default/137.edn_genbits.2076844891 Feb 29 01:42:02 PM PST 24 Feb 29 01:42:05 PM PST 24 142712076 ps
T805 /workspace/coverage/default/9.edn_alert_test.4250068266 Feb 29 01:40:17 PM PST 24 Feb 29 01:40:18 PM PST 24 14251428 ps
T806 /workspace/coverage/default/41.edn_disable.981521831 Feb 29 01:41:19 PM PST 24 Feb 29 01:41:20 PM PST 24 31066594 ps
T807 /workspace/coverage/default/10.edn_alert.3278336997 Feb 29 01:40:13 PM PST 24 Feb 29 01:40:15 PM PST 24 23775044 ps
T808 /workspace/coverage/default/32.edn_smoke.2144399620 Feb 29 01:40:51 PM PST 24 Feb 29 01:40:52 PM PST 24 40584009 ps
T809 /workspace/coverage/default/38.edn_smoke.3454151272 Feb 29 01:41:06 PM PST 24 Feb 29 01:41:09 PM PST 24 178444164 ps
T810 /workspace/coverage/default/130.edn_genbits.1779752055 Feb 29 01:41:50 PM PST 24 Feb 29 01:41:51 PM PST 24 29022083 ps
T811 /workspace/coverage/default/34.edn_stress_all.2478442516 Feb 29 01:41:06 PM PST 24 Feb 29 01:41:11 PM PST 24 445586446 ps
T812 /workspace/coverage/default/12.edn_alert.1928025169 Feb 29 01:40:27 PM PST 24 Feb 29 01:40:28 PM PST 24 46300063 ps
T813 /workspace/coverage/default/13.edn_genbits.1252556092 Feb 29 01:40:27 PM PST 24 Feb 29 01:40:30 PM PST 24 181684239 ps
T814 /workspace/coverage/default/79.edn_err.302364416 Feb 29 01:41:49 PM PST 24 Feb 29 01:41:50 PM PST 24 25133107 ps
T815 /workspace/coverage/default/70.edn_err.1471145963 Feb 29 01:41:43 PM PST 24 Feb 29 01:41:44 PM PST 24 18750478 ps
T816 /workspace/coverage/default/73.edn_err.4223212436 Feb 29 01:41:41 PM PST 24 Feb 29 01:41:42 PM PST 24 27944028 ps
T817 /workspace/coverage/default/45.edn_genbits.217031526 Feb 29 01:41:23 PM PST 24 Feb 29 01:41:25 PM PST 24 45103864 ps
T83 /workspace/coverage/default/29.edn_err.1106247455 Feb 29 01:40:59 PM PST 24 Feb 29 01:41:01 PM PST 24 36277312 ps
T818 /workspace/coverage/default/48.edn_disable_auto_req_mode.1601062866 Feb 29 01:41:36 PM PST 24 Feb 29 01:41:37 PM PST 24 32958699 ps
T819 /workspace/coverage/default/85.edn_genbits.2491602163 Feb 29 01:41:48 PM PST 24 Feb 29 01:41:50 PM PST 24 48423831 ps
T820 /workspace/coverage/default/37.edn_disable.3729387426 Feb 29 01:41:04 PM PST 24 Feb 29 01:41:05 PM PST 24 49700091 ps
T91 /workspace/coverage/default/40.edn_err.4068215157 Feb 29 01:41:19 PM PST 24 Feb 29 01:41:21 PM PST 24 22879863 ps
T821 /workspace/coverage/default/61.edn_err.370814441 Feb 29 01:41:34 PM PST 24 Feb 29 01:41:37 PM PST 24 31136959 ps
T822 /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1503698722 Feb 29 01:40:05 PM PST 24 Feb 29 01:49:06 PM PST 24 46464539945 ps
T823 /workspace/coverage/default/211.edn_genbits.2254034480 Feb 29 01:42:17 PM PST 24 Feb 29 01:42:18 PM PST 24 52486748 ps
T824 /workspace/coverage/default/15.edn_disable_auto_req_mode.3121204059 Feb 29 01:40:30 PM PST 24 Feb 29 01:40:31 PM PST 24 56614650 ps
T825 /workspace/coverage/default/15.edn_alert.3598429014 Feb 29 01:40:28 PM PST 24 Feb 29 01:40:30 PM PST 24 83373588 ps
T826 /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1981815724 Feb 29 01:40:10 PM PST 24 Feb 29 02:04:42 PM PST 24 223412086214 ps
T827 /workspace/coverage/default/21.edn_err.3793832619 Feb 29 01:40:42 PM PST 24 Feb 29 01:40:43 PM PST 24 20046983 ps
T828 /workspace/coverage/default/39.edn_stress_all_with_rand_reset.318521439 Feb 29 01:41:20 PM PST 24 Feb 29 02:21:52 PM PST 24 94860757826 ps
T829 /workspace/coverage/default/19.edn_genbits.1390845610 Feb 29 01:40:42 PM PST 24 Feb 29 01:40:43 PM PST 24 80254068 ps
T830 /workspace/coverage/default/268.edn_genbits.2481238587 Feb 29 01:42:27 PM PST 24 Feb 29 01:42:29 PM PST 24 48203310 ps
T831 /workspace/coverage/default/144.edn_genbits.2513974158 Feb 29 01:41:58 PM PST 24 Feb 29 01:42:00 PM PST 24 49902194 ps
T832 /workspace/coverage/default/48.edn_smoke.764928313 Feb 29 01:41:34 PM PST 24 Feb 29 01:41:37 PM PST 24 26943381 ps
T833 /workspace/coverage/default/10.edn_alert_test.567442608 Feb 29 01:40:16 PM PST 24 Feb 29 01:40:17 PM PST 24 135387118 ps
T834 /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3483687109 Feb 29 01:40:16 PM PST 24 Feb 29 01:54:05 PM PST 24 355093604328 ps
T835 /workspace/coverage/default/4.edn_alert.390662693 Feb 29 01:40:08 PM PST 24 Feb 29 01:40:09 PM PST 24 72821272 ps
T836 /workspace/coverage/default/14.edn_err.1059552789 Feb 29 01:40:30 PM PST 24 Feb 29 01:40:31 PM PST 24 75728369 ps
T837 /workspace/coverage/default/44.edn_intr.553430739 Feb 29 01:41:18 PM PST 24 Feb 29 01:41:19 PM PST 24 31249128 ps
T838 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1067737776 Feb 29 12:41:47 PM PST 24 Feb 29 12:41:49 PM PST 24 62175267 ps
T839 /workspace/coverage/cover_reg_top/12.edn_tl_errors.1412245331 Feb 29 12:41:35 PM PST 24 Feb 29 12:41:38 PM PST 24 97484953 ps
T840 /workspace/coverage/cover_reg_top/48.edn_intr_test.3148676181 Feb 29 12:41:42 PM PST 24 Feb 29 12:41:43 PM PST 24 22178810 ps
T245 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.379628915 Feb 29 12:41:46 PM PST 24 Feb 29 12:41:49 PM PST 24 207504129 ps
T246 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2924639941 Feb 29 12:41:25 PM PST 24 Feb 29 12:41:28 PM PST 24 56592729 ps
T841 /workspace/coverage/cover_reg_top/43.edn_intr_test.292990470 Feb 29 12:41:59 PM PST 24 Feb 29 12:42:00 PM PST 24 12581429 ps
T842 /workspace/coverage/cover_reg_top/34.edn_intr_test.3969403609 Feb 29 12:41:48 PM PST 24 Feb 29 12:41:49 PM PST 24 32585269 ps
T247 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.487152222 Feb 29 12:41:34 PM PST 24 Feb 29 12:41:40 PM PST 24 254708249 ps
T843 /workspace/coverage/cover_reg_top/29.edn_intr_test.1372921316 Feb 29 12:41:46 PM PST 24 Feb 29 12:41:48 PM PST 24 27288701 ps
T844 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1931641695 Feb 29 12:41:47 PM PST 24 Feb 29 12:41:49 PM PST 24 106983771 ps
T210 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.303970608 Feb 29 12:41:14 PM PST 24 Feb 29 12:41:16 PM PST 24 36506299 ps
T845 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3086716386 Feb 29 12:41:36 PM PST 24 Feb 29 12:41:38 PM PST 24 26458751 ps
T846 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.185054171 Feb 29 12:41:25 PM PST 24 Feb 29 12:41:27 PM PST 24 23080264 ps
T847 /workspace/coverage/cover_reg_top/41.edn_intr_test.3029645622 Feb 29 12:41:42 PM PST 24 Feb 29 12:41:44 PM PST 24 25596934 ps
T848 /workspace/coverage/cover_reg_top/37.edn_intr_test.1501893761 Feb 29 12:41:40 PM PST 24 Feb 29 12:41:42 PM PST 24 160318846 ps
T849 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2089160358 Feb 29 12:41:35 PM PST 24 Feb 29 12:41:38 PM PST 24 111759311 ps
T254 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.885420846 Feb 29 12:41:34 PM PST 24 Feb 29 12:41:39 PM PST 24 197450313 ps
T850 /workspace/coverage/cover_reg_top/21.edn_intr_test.1639373729 Feb 29 12:41:40 PM PST 24 Feb 29 12:41:47 PM PST 24 44674937 ps
T228 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1219713738 Feb 29 12:41:45 PM PST 24 Feb 29 12:41:46 PM PST 24 39854028 ps
T851 /workspace/coverage/cover_reg_top/33.edn_intr_test.978013671 Feb 29 12:41:41 PM PST 24 Feb 29 12:41:43 PM PST 24 16805976 ps
T852 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2805878571 Feb 29 12:41:32 PM PST 24 Feb 29 12:41:35 PM PST 24 72658071 ps
T853 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.785382827 Feb 29 12:41:38 PM PST 24 Feb 29 12:41:39 PM PST 24 103300151 ps
T244 /workspace/coverage/cover_reg_top/13.edn_csr_rw.2014706173 Feb 29 12:41:40 PM PST 24 Feb 29 12:41:43 PM PST 24 35873238 ps
T854 /workspace/coverage/cover_reg_top/39.edn_intr_test.2725877118 Feb 29 12:41:55 PM PST 24 Feb 29 12:41:56 PM PST 24 48043973 ps
T211 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1402797275 Feb 29 12:41:42 PM PST 24 Feb 29 12:41:44 PM PST 24 43424715 ps
T258 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1569652911 Feb 29 12:41:29 PM PST 24 Feb 29 12:41:31 PM PST 24 262559722 ps
T212 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1327356016 Feb 29 12:41:26 PM PST 24 Feb 29 12:41:32 PM PST 24 344505459 ps
T855 /workspace/coverage/cover_reg_top/46.edn_intr_test.940139821 Feb 29 12:41:57 PM PST 24 Feb 29 12:41:58 PM PST 24 157682775 ps
T229 /workspace/coverage/cover_reg_top/14.edn_csr_rw.2365158846 Feb 29 12:41:32 PM PST 24 Feb 29 12:41:33 PM PST 24 13641481 ps
T856 /workspace/coverage/cover_reg_top/49.edn_intr_test.2514873941 Feb 29 12:41:49 PM PST 24 Feb 29 12:41:55 PM PST 24 37369943 ps
T230 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.909042068 Feb 29 12:41:37 PM PST 24 Feb 29 12:41:39 PM PST 24 37913185 ps
T213 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.512580713 Feb 29 12:41:33 PM PST 24 Feb 29 12:41:35 PM PST 24 12623655 ps
T214 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3486730478 Feb 29 12:41:29 PM PST 24 Feb 29 12:41:30 PM PST 24 17857421 ps
T857 /workspace/coverage/cover_reg_top/24.edn_intr_test.1959450417 Feb 29 12:41:51 PM PST 24 Feb 29 12:42:02 PM PST 24 34744854 ps
T215 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2722370810 Feb 29 12:41:43 PM PST 24 Feb 29 12:41:45 PM PST 24 128892846 ps
T858 /workspace/coverage/cover_reg_top/3.edn_tl_errors.3418362153 Feb 29 12:41:42 PM PST 24 Feb 29 12:41:45 PM PST 24 177361428 ps
T216 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2846637438 Feb 29 12:41:39 PM PST 24 Feb 29 12:41:42 PM PST 24 16426889 ps
T231 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1213336904 Feb 29 12:41:25 PM PST 24 Feb 29 12:41:27 PM PST 24 39868880 ps
T255 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2842033160 Feb 29 12:41:40 PM PST 24 Feb 29 12:41:44 PM PST 24 198562314 ps
T859 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2185964902 Feb 29 12:41:50 PM PST 24 Feb 29 12:41:52 PM PST 24 201785524 ps
T860 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2081947626 Feb 29 12:41:25 PM PST 24 Feb 29 12:41:27 PM PST 24 78338764 ps
T861 /workspace/coverage/cover_reg_top/0.edn_tl_errors.2050363694 Feb 29 12:41:31 PM PST 24 Feb 29 12:41:34 PM PST 24 77048559 ps
T217 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.257464956 Feb 29 12:41:45 PM PST 24 Feb 29 12:41:47 PM PST 24 40490429 ps
T862 /workspace/coverage/cover_reg_top/22.edn_intr_test.2397334461 Feb 29 12:41:45 PM PST 24 Feb 29 12:41:47 PM PST 24 46624968 ps
T863 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1076315696 Feb 29 12:41:38 PM PST 24 Feb 29 12:41:40 PM PST 24 66659865 ps
T864 /workspace/coverage/cover_reg_top/17.edn_intr_test.3732963357 Feb 29 12:41:43 PM PST 24 Feb 29 12:41:45 PM PST 24 23704418 ps
T232 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3831074330 Feb 29 12:41:47 PM PST 24 Feb 29 12:41:49 PM PST 24 31662127 ps
T865 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2154882894 Feb 29 12:42:08 PM PST 24 Feb 29 12:42:09 PM PST 24 36589154 ps
T866 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1669917619 Feb 29 12:41:40 PM PST 24 Feb 29 12:41:42 PM PST 24 18966995 ps
T867 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1470337660 Feb 29 12:41:54 PM PST 24 Feb 29 12:41:56 PM PST 24 139548797 ps
T868 /workspace/coverage/cover_reg_top/1.edn_intr_test.2989788468 Feb 29 12:41:28 PM PST 24 Feb 29 12:41:29 PM PST 24 15538184 ps
T869 /workspace/coverage/cover_reg_top/47.edn_intr_test.1338169249 Feb 29 12:41:52 PM PST 24 Feb 29 12:41:53 PM PST 24 37410820 ps
T870 /workspace/coverage/cover_reg_top/20.edn_intr_test.2226995265 Feb 29 12:41:46 PM PST 24 Feb 29 12:41:47 PM PST 24 11894035 ps
T871 /workspace/coverage/cover_reg_top/13.edn_intr_test.128922325 Feb 29 12:41:36 PM PST 24 Feb 29 12:41:37 PM PST 24 11020460 ps
T233 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1340452375 Feb 29 12:41:43 PM PST 24 Feb 29 12:41:46 PM PST 24 90442882 ps
T872 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2663777134 Feb 29 12:41:43 PM PST 24 Feb 29 12:41:46 PM PST 24 21416981 ps
T218 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1723701398 Feb 29 12:41:24 PM PST 24 Feb 29 12:41:25 PM PST 24 15328957 ps
T873 /workspace/coverage/cover_reg_top/3.edn_intr_test.817530470 Feb 29 12:41:30 PM PST 24 Feb 29 12:41:32 PM PST 24 24352256 ps
T874 /workspace/coverage/cover_reg_top/15.edn_intr_test.1455161242 Feb 29 12:41:42 PM PST 24 Feb 29 12:41:44 PM PST 24 11528871 ps
T875 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.858849466 Feb 29 12:41:29 PM PST 24 Feb 29 12:41:31 PM PST 24 80925209 ps
T876 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4038900931 Feb 29 12:41:42 PM PST 24 Feb 29 12:41:45 PM PST 24 400598952 ps
T877 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1140831046 Feb 29 12:41:38 PM PST 24 Feb 29 12:41:40 PM PST 24 47713907 ps
T878 /workspace/coverage/cover_reg_top/25.edn_intr_test.3882713429 Feb 29 12:41:40 PM PST 24 Feb 29 12:41:42 PM PST 24 56764657 ps
T879 /workspace/coverage/cover_reg_top/9.edn_tl_errors.3806816440 Feb 29 12:41:24 PM PST 24 Feb 29 12:41:26 PM PST 24 75302260 ps
T880 /workspace/coverage/cover_reg_top/19.edn_tl_errors.190164098 Feb 29 12:41:59 PM PST 24 Feb 29 12:42:02 PM PST 24 527992728 ps
T219 /workspace/coverage/cover_reg_top/9.edn_csr_rw.3653770783 Feb 29 12:41:27 PM PST 24 Feb 29 12:41:29 PM PST 24 13437036 ps
T234 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3207945763 Feb 29 12:41:29 PM PST 24 Feb 29 12:41:30 PM PST 24 35648427 ps
T881 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1111071508 Feb 29 12:41:22 PM PST 24 Feb 29 12:41:26 PM PST 24 514192597 ps
T882 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1158572951 Feb 29 12:41:29 PM PST 24 Feb 29 12:41:30 PM PST 24 193200043 ps
T883 /workspace/coverage/cover_reg_top/23.edn_intr_test.4215731122 Feb 29 12:41:58 PM PST 24 Feb 29 12:41:59 PM PST 24 61621601 ps
T884 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2116289205 Feb 29 12:41:27 PM PST 24 Feb 29 12:41:28 PM PST 24 42651601 ps
T220 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1423490423 Feb 29 12:41:51 PM PST 24 Feb 29 12:41:52 PM PST 24 14066110 ps
T885 /workspace/coverage/cover_reg_top/8.edn_csr_rw.2993736103 Feb 29 12:41:24 PM PST 24 Feb 29 12:41:26 PM PST 24 27708725 ps
T886 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2576939650 Feb 29 12:41:44 PM PST 24 Feb 29 12:41:48 PM PST 24 68548166 ps
T887 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.968256351 Feb 29 12:41:25 PM PST 24 Feb 29 12:41:27 PM PST 24 62801797 ps
T888 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3547062738 Feb 29 12:41:34 PM PST 24 Feb 29 12:41:36 PM PST 24 38070027 ps
T889 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1596455344 Feb 29 12:41:38 PM PST 24 Feb 29 12:41:40 PM PST 24 51356284 ps
T890 /workspace/coverage/cover_reg_top/11.edn_intr_test.244667260 Feb 29 12:41:32 PM PST 24 Feb 29 12:41:33 PM PST 24 46650918 ps
T891 /workspace/coverage/cover_reg_top/7.edn_intr_test.3114761312 Feb 29 12:41:45 PM PST 24 Feb 29 12:41:47 PM PST 24 18744727 ps
T892 /workspace/coverage/cover_reg_top/4.edn_tl_errors.1515881146 Feb 29 12:41:22 PM PST 24 Feb 29 12:41:26 PM PST 24 148670335 ps
T893 /workspace/coverage/cover_reg_top/13.edn_tl_errors.1284897877 Feb 29 12:41:42 PM PST 24 Feb 29 12:41:45 PM PST 24 22779632 ps
T894 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2334509675 Feb 29 12:41:36 PM PST 24 Feb 29 12:41:40 PM PST 24 50974636 ps
T221 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.454714203 Feb 29 12:41:35 PM PST 24 Feb 29 12:41:37 PM PST 24 141609852 ps
T895 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1981221935 Feb 29 12:41:43 PM PST 24 Feb 29 12:41:46 PM PST 24 65261440 ps
T896 /workspace/coverage/cover_reg_top/36.edn_intr_test.3555483447 Feb 29 12:41:55 PM PST 24 Feb 29 12:41:57 PM PST 24 10793732 ps
T256 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.4195344726 Feb 29 12:41:39 PM PST 24 Feb 29 12:41:41 PM PST 24 387744355 ps
T897 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3844629538 Feb 29 12:41:37 PM PST 24 Feb 29 12:41:39 PM PST 24 22952853 ps
T222 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2576434126 Feb 29 12:41:38 PM PST 24 Feb 29 12:41:39 PM PST 24 13519295 ps
T898 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2210563971 Feb 29 12:41:40 PM PST 24 Feb 29 12:41:44 PM PST 24 61163499 ps
T899 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.4035018553 Feb 29 12:41:21 PM PST 24 Feb 29 12:41:23 PM PST 24 27590746 ps
T900 /workspace/coverage/cover_reg_top/0.edn_intr_test.2647749406 Feb 29 12:41:39 PM PST 24 Feb 29 12:41:41 PM PST 24 15635763 ps
T901 /workspace/coverage/cover_reg_top/19.edn_intr_test.2739767291 Feb 29 12:41:48 PM PST 24 Feb 29 12:41:49 PM PST 24 19890677 ps
T902 /workspace/coverage/cover_reg_top/18.edn_csr_rw.1232100914 Feb 29 12:41:49 PM PST 24 Feb 29 12:41:50 PM PST 24 16946011 ps
T903 /workspace/coverage/cover_reg_top/0.edn_csr_rw.2714026102 Feb 29 12:41:35 PM PST 24 Feb 29 12:41:37 PM PST 24 13892168 ps
T904 /workspace/coverage/cover_reg_top/4.edn_intr_test.956185415 Feb 29 12:41:25 PM PST 24 Feb 29 12:41:27 PM PST 24 16348156 ps
T905 /workspace/coverage/cover_reg_top/40.edn_intr_test.2660854711 Feb 29 12:42:02 PM PST 24 Feb 29 12:42:03 PM PST 24 125048727 ps
T906 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1824742168 Feb 29 12:41:30 PM PST 24 Feb 29 12:41:31 PM PST 24 23782220 ps
T907 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.859788407 Feb 29 12:41:33 PM PST 24 Feb 29 12:41:35 PM PST 24 80514875 ps
T908 /workspace/coverage/cover_reg_top/1.edn_tl_errors.3960490555 Feb 29 12:41:30 PM PST 24 Feb 29 12:41:32 PM PST 24 27339043 ps
T909 /workspace/coverage/cover_reg_top/16.edn_tl_errors.321976766 Feb 29 12:41:41 PM PST 24 Feb 29 12:41:45 PM PST 24 88257621 ps
T910 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3854763804 Feb 29 12:41:31 PM PST 24 Feb 29 12:41:32 PM PST 24 54869073 ps
T911 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3017182626 Feb 29 12:41:43 PM PST 24 Feb 29 12:41:45 PM PST 24 18156686 ps
T912 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3068675247 Feb 29 12:41:45 PM PST 24 Feb 29 12:41:55 PM PST 24 125191404 ps
T913 /workspace/coverage/cover_reg_top/18.edn_intr_test.231876047 Feb 29 12:41:47 PM PST 24 Feb 29 12:41:49 PM PST 24 15266245 ps
T914 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1536238502 Feb 29 12:41:31 PM PST 24 Feb 29 12:41:32 PM PST 24 14812043 ps
T915 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1910032974 Feb 29 12:41:38 PM PST 24 Feb 29 12:41:42 PM PST 24 140073435 ps
T223 /workspace/coverage/cover_reg_top/2.edn_csr_rw.510371694 Feb 29 12:41:38 PM PST 24 Feb 29 12:41:40 PM PST 24 21259342 ps
T916 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3151342662 Feb 29 12:41:47 PM PST 24 Feb 29 12:41:49 PM PST 24 76576487 ps
T917 /workspace/coverage/cover_reg_top/14.edn_intr_test.3922542836 Feb 29 12:41:44 PM PST 24 Feb 29 12:41:46 PM PST 24 24393289 ps
T918 /workspace/coverage/cover_reg_top/35.edn_intr_test.3470373048 Feb 29 12:41:43 PM PST 24 Feb 29 12:41:45 PM PST 24 48044200 ps
T919 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.4136827729 Feb 29 12:41:41 PM PST 24 Feb 29 12:41:43 PM PST 24 75842060 ps
T920 /workspace/coverage/cover_reg_top/28.edn_intr_test.1828262429 Feb 29 12:41:43 PM PST 24 Feb 29 12:41:45 PM PST 24 17975350 ps
T921 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3622268598 Feb 29 12:41:22 PM PST 24 Feb 29 12:41:24 PM PST 24 34208960 ps
T226 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1247467775 Feb 29 12:41:21 PM PST 24 Feb 29 12:41:25 PM PST 24 213057321 ps
T257 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1594424631 Feb 29 12:41:42 PM PST 24 Feb 29 12:41:45 PM PST 24 151373170 ps
T922 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1204995589 Feb 29 12:41:32 PM PST 24 Feb 29 12:41:34 PM PST 24 46878119 ps
T923 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.4142600091 Feb 29 12:41:30 PM PST 24 Feb 29 12:41:31 PM PST 24 38406891 ps
T924 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1181914011 Feb 29 12:41:41 PM PST 24 Feb 29 12:41:44 PM PST 24 281185862 ps
T925 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3505924606 Feb 29 12:41:37 PM PST 24 Feb 29 12:41:38 PM PST 24 39992611 ps
T926 /workspace/coverage/cover_reg_top/9.edn_intr_test.2881800424 Feb 29 12:41:43 PM PST 24 Feb 29 12:41:46 PM PST 24 23530622 ps
T927 /workspace/coverage/cover_reg_top/26.edn_intr_test.3294752180 Feb 29 12:41:54 PM PST 24 Feb 29 12:41:55 PM PST 24 27306886 ps
T928 /workspace/coverage/cover_reg_top/32.edn_intr_test.556006512 Feb 29 12:41:39 PM PST 24 Feb 29 12:41:42 PM PST 24 14419781 ps
T929 /workspace/coverage/cover_reg_top/27.edn_intr_test.2368693436 Feb 29 12:41:41 PM PST 24 Feb 29 12:41:43 PM PST 24 12580605 ps
T930 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.4139007578 Feb 29 12:41:38 PM PST 24 Feb 29 12:41:41 PM PST 24 79911183 ps
T931 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.583177946 Feb 29 12:41:37 PM PST 24 Feb 29 12:41:39 PM PST 24 37094991 ps
T932 /workspace/coverage/cover_reg_top/42.edn_intr_test.3814837236 Feb 29 12:41:43 PM PST 24 Feb 29 12:41:45 PM PST 24 38064829 ps
T933 /workspace/coverage/cover_reg_top/31.edn_intr_test.3686966578 Feb 29 12:41:29 PM PST 24 Feb 29 12:41:30 PM PST 24 11686902 ps
T934 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1051890614 Feb 29 12:41:45 PM PST 24 Feb 29 12:41:48 PM PST 24 85795172 ps
T935 /workspace/coverage/cover_reg_top/5.edn_intr_test.2299939672 Feb 29 12:41:29 PM PST 24 Feb 29 12:41:30 PM PST 24 100043964 ps
T936 /workspace/coverage/cover_reg_top/7.edn_csr_rw.468020337 Feb 29 12:41:31 PM PST 24 Feb 29 12:41:32 PM PST 24 55223647 ps
T937 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1729723652 Feb 29 12:41:42 PM PST 24 Feb 29 12:41:44 PM PST 24 28924407 ps
T938 /workspace/coverage/cover_reg_top/12.edn_intr_test.1441559384 Feb 29 12:42:00 PM PST 24 Feb 29 12:42:06 PM PST 24 35143364 ps
T224 /workspace/coverage/cover_reg_top/11.edn_csr_rw.1266604937 Feb 29 12:41:47 PM PST 24 Feb 29 12:41:48 PM PST 24 11757111 ps
T939 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1486394411 Feb 29 12:41:40 PM PST 24 Feb 29 12:41:43 PM PST 24 63696736 ps
T940 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.337547313 Feb 29 12:41:21 PM PST 24 Feb 29 12:41:23 PM PST 24 170140458 ps
T941 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3996315395 Feb 29 12:41:47 PM PST 24 Feb 29 12:41:50 PM PST 24 380265140 ps
T942 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3722400641 Feb 29 12:41:45 PM PST 24 Feb 29 12:41:48 PM PST 24 24628037 ps
T943 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3547336271 Feb 29 12:41:30 PM PST 24 Feb 29 12:41:32 PM PST 24 18385806 ps
T944 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1134884543 Feb 29 12:41:27 PM PST 24 Feb 29 12:41:29 PM PST 24 51004689 ps
T945 /workspace/coverage/cover_reg_top/38.edn_intr_test.1619647930 Feb 29 12:41:43 PM PST 24 Feb 29 12:41:46 PM PST 24 17316035 ps
T946 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3897266066 Feb 29 12:41:58 PM PST 24 Feb 29 12:41:59 PM PST 24 37838527 ps
T947 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.343844908 Feb 29 12:41:35 PM PST 24 Feb 29 12:41:37 PM PST 24 27304943 ps
T948 /workspace/coverage/cover_reg_top/16.edn_csr_rw.108241324 Feb 29 12:41:33 PM PST 24 Feb 29 12:41:35 PM PST 24 31197879 ps
T949 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1392569927 Feb 29 12:41:34 PM PST 24 Feb 29 12:41:36 PM PST 24 285371155 ps
T950 /workspace/coverage/cover_reg_top/44.edn_intr_test.2435825958 Feb 29 12:41:47 PM PST 24 Feb 29 12:41:49 PM PST 24 23964443 ps
T227 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3986793160 Feb 29 12:41:43 PM PST 24 Feb 29 12:41:46 PM PST 24 227419340 ps
T951 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1758827189 Feb 29 12:41:44 PM PST 24 Feb 29 12:41:48 PM PST 24 92905997 ps
T952 /workspace/coverage/cover_reg_top/2.edn_intr_test.3201470678 Feb 29 12:41:29 PM PST 24 Feb 29 12:41:30 PM PST 24 15576963 ps
T953 /workspace/coverage/cover_reg_top/14.edn_tl_errors.363911749 Feb 29 12:41:54 PM PST 24 Feb 29 12:41:56 PM PST 24 39912723 ps
T954 /workspace/coverage/cover_reg_top/2.edn_tl_errors.798581942 Feb 29 12:41:41 PM PST 24 Feb 29 12:41:44 PM PST 24 189729393 ps
T955 /workspace/coverage/cover_reg_top/8.edn_intr_test.2607869604 Feb 29 12:41:34 PM PST 24 Feb 29 12:41:36 PM PST 24 41614225 ps
T956 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3973176727 Feb 29 12:41:39 PM PST 24 Feb 29 12:41:41 PM PST 24 23805561 ps
T957 /workspace/coverage/cover_reg_top/45.edn_intr_test.3559192849 Feb 29 12:41:45 PM PST 24 Feb 29 12:41:46 PM PST 24 88718313 ps
T958 /workspace/coverage/cover_reg_top/16.edn_intr_test.596270847 Feb 29 12:41:40 PM PST 24 Feb 29 12:41:42 PM PST 24 44868497 ps
T959 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1682929375 Feb 29 12:41:47 PM PST 24 Feb 29 12:41:49 PM PST 24 43375360 ps
T960 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1941886753 Feb 29 12:41:47 PM PST 24 Feb 29 12:41:51 PM PST 24 212759607 ps
T961 /workspace/coverage/cover_reg_top/10.edn_intr_test.826830156 Feb 29 12:41:39 PM PST 24 Feb 29 12:41:41 PM PST 24 39547860 ps
T962 /workspace/coverage/cover_reg_top/8.edn_tl_errors.3635772283 Feb 29 12:41:38 PM PST 24 Feb 29 12:41:41 PM PST 24 199958991 ps
T963 /workspace/coverage/cover_reg_top/30.edn_intr_test.2571865787 Feb 29 12:41:59 PM PST 24 Feb 29 12:42:00 PM PST 24 91102323 ps
T225 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2491298577 Feb 29 12:41:25 PM PST 24 Feb 29 12:41:26 PM PST 24 17271876 ps
T964 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1781116729 Feb 29 12:41:37 PM PST 24 Feb 29 12:41:39 PM PST 24 43198077 ps
T965 /workspace/coverage/cover_reg_top/6.edn_intr_test.1168982489 Feb 29 12:41:43 PM PST 24 Feb 29 12:41:45 PM PST 24 11535668 ps
T966 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3839370974 Feb 29 12:41:47 PM PST 24 Feb 29 12:41:49 PM PST 24 42390108 ps
T967 /workspace/coverage/cover_reg_top/5.edn_csr_rw.1886985823 Feb 29 12:41:36 PM PST 24 Feb 29 12:41:38 PM PST 24 29178294 ps
T968 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.519727518 Feb 29 12:41:42 PM PST 24 Feb 29 12:41:49 PM PST 24 17606548 ps

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.614228722
Short name T1
Test name
Test status
Simulation time 88465338202 ps
CPU time 434.35 seconds
Started Feb 29 01:39:55 PM PST 24
Finished Feb 29 01:47:10 PM PST 24
Peak memory 217860 kb
Host smart-4b63bace-e706-4160-ad09-f0df0cb64230
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614228722 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.614228722
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.edn_alert.2668518050
Short name T14
Test name
Test status
Simulation time 88535707 ps
CPU time 1.18 seconds
Started Feb 29 01:40:59 PM PST 24
Finished Feb 29 01:41:00 PM PST 24
Peak memory 215064 kb
Host smart-616f57e1-3b60-4194-a631-456af6438ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668518050 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2668518050
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/28.edn_genbits.1303718440
Short name T24
Test name
Test status
Simulation time 94803801 ps
CPU time 1.26 seconds
Started Feb 29 01:40:52 PM PST 24
Finished Feb 29 01:40:53 PM PST 24
Peak memory 215932 kb
Host smart-ed243f96-2e46-41cf-9ff3-955e172e7989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303718440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1303718440
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_sec_cm.3076670375
Short name T17
Test name
Test status
Simulation time 2104379675 ps
CPU time 7.01 seconds
Started Feb 29 01:39:50 PM PST 24
Finished Feb 29 01:39:57 PM PST 24
Peak memory 234944 kb
Host smart-9fc17073-abb2-4217-8ee6-d7dff56c0118
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076670375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.3076670375
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/8.edn_err.595233808
Short name T7
Test name
Test status
Simulation time 28245587 ps
CPU time 1.3 seconds
Started Feb 29 01:40:17 PM PST 24
Finished Feb 29 01:40:19 PM PST 24
Peak memory 216328 kb
Host smart-1c83ce60-85f2-41a4-93f2-f48fe8e863c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595233808 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.595233808
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.3828337671
Short name T58
Test name
Test status
Simulation time 170855107 ps
CPU time 1.03 seconds
Started Feb 29 01:40:19 PM PST 24
Finished Feb 29 01:40:20 PM PST 24
Peak memory 215904 kb
Host smart-11cbfab6-a4ad-4733-b4cc-28ac1976b734
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828337671 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.3828337671
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_stress_all.1027225296
Short name T133
Test name
Test status
Simulation time 599354706 ps
CPU time 3.72 seconds
Started Feb 29 01:40:39 PM PST 24
Finished Feb 29 01:40:43 PM PST 24
Peak memory 215812 kb
Host smart-4c91e404-c49b-4998-b456-833c714d92d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027225296 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1027225296
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.4076814798
Short name T8
Test name
Test status
Simulation time 250053368 ps
CPU time 1.25 seconds
Started Feb 29 01:41:22 PM PST 24
Finished Feb 29 01:41:24 PM PST 24
Peak memory 215988 kb
Host smart-12d8b271-0202-480d-afe6-e61cb088e2fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076814798 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.4076814798
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_alert.3163256896
Short name T114
Test name
Test status
Simulation time 45701177 ps
CPU time 1.17 seconds
Started Feb 29 01:40:08 PM PST 24
Finished Feb 29 01:40:11 PM PST 24
Peak memory 215052 kb
Host smart-80cbed96-59b4-4914-a57d-fde73d2df7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163256896 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3163256896
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/20.edn_intr.2036835456
Short name T121
Test name
Test status
Simulation time 24476932 ps
CPU time 0.91 seconds
Started Feb 29 01:40:48 PM PST 24
Finished Feb 29 01:40:49 PM PST 24
Peak memory 215200 kb
Host smart-86f8ecb7-e40b-4313-897b-ad58104787c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036835456 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.2036835456
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/294.edn_genbits.2574508824
Short name T173
Test name
Test status
Simulation time 605471843 ps
CPU time 5.27 seconds
Started Feb 29 01:42:34 PM PST 24
Finished Feb 29 01:42:39 PM PST 24
Peak memory 216208 kb
Host smart-d3adecea-7211-4138-9329-8427a655c7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574508824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.2574508824
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_regwen.3206033469
Short name T195
Test name
Test status
Simulation time 29975467 ps
CPU time 0.95 seconds
Started Feb 29 01:39:51 PM PST 24
Finished Feb 29 01:39:53 PM PST 24
Peak memory 206588 kb
Host smart-bbe55278-15d7-41e5-a5e5-961ba2d0afc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206033469 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3206033469
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.4253002452
Short name T185
Test name
Test status
Simulation time 38700747210 ps
CPU time 798.39 seconds
Started Feb 29 01:41:17 PM PST 24
Finished Feb 29 01:54:35 PM PST 24
Peak memory 217056 kb
Host smart-81a89268-88a3-4132-897b-ac04d5617c8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253002452 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.4253002452
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_err.3121849494
Short name T27
Test name
Test status
Simulation time 34783867 ps
CPU time 0.91 seconds
Started Feb 29 01:41:21 PM PST 24
Finished Feb 29 01:41:22 PM PST 24
Peak memory 217392 kb
Host smart-eacf756d-f458-4ea9-a953-17130680be11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121849494 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3121849494
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.379628915
Short name T245
Test name
Test status
Simulation time 207504129 ps
CPU time 2.47 seconds
Started Feb 29 12:41:46 PM PST 24
Finished Feb 29 12:41:49 PM PST 24
Peak memory 205780 kb
Host smart-9704fdf0-e60c-40a4-b57b-7a7ffd693018
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379628915 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.379628915
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1327356016
Short name T212
Test name
Test status
Simulation time 344505459 ps
CPU time 6.11 seconds
Started Feb 29 12:41:26 PM PST 24
Finished Feb 29 12:41:32 PM PST 24
Peak memory 205768 kb
Host smart-567646ec-806c-45c5-b185-0672f1c07f02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327356016 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1327356016
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/default/42.edn_alert.648170060
Short name T99
Test name
Test status
Simulation time 62307098 ps
CPU time 1.17 seconds
Started Feb 29 01:41:18 PM PST 24
Finished Feb 29 01:41:20 PM PST 24
Peak memory 215072 kb
Host smart-57c153c5-a5d7-42b0-ad4b-ebe7eb249e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648170060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.648170060
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert.3349486431
Short name T15
Test name
Test status
Simulation time 81640443 ps
CPU time 1.16 seconds
Started Feb 29 01:40:45 PM PST 24
Finished Feb 29 01:40:46 PM PST 24
Peak memory 215056 kb
Host smart-001ca82b-aab9-485c-9bef-f9faa7e4e861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349486431 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3349486431
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/49.edn_disable.4259777976
Short name T103
Test name
Test status
Simulation time 37078059 ps
CPU time 0.84 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:49 PM PST 24
Peak memory 215136 kb
Host smart-d4b11bdc-bd2b-4b2a-8c71-b040a6a0c48d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259777976 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.4259777976
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/18.edn_intr.3221237611
Short name T125
Test name
Test status
Simulation time 65808547 ps
CPU time 0.85 seconds
Started Feb 29 01:40:32 PM PST 24
Finished Feb 29 01:40:33 PM PST 24
Peak memory 215016 kb
Host smart-f904c4d4-5042-42b9-9545-6728f058a1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221237611 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3221237611
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/30.edn_disable.3702738454
Short name T87
Test name
Test status
Simulation time 13311786 ps
CPU time 0.92 seconds
Started Feb 29 01:40:53 PM PST 24
Finished Feb 29 01:40:54 PM PST 24
Peak memory 215020 kb
Host smart-f20ceac8-9273-4150-ba27-9710deb6cf37
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702738454 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3702738454
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/92.edn_err.2118610725
Short name T38
Test name
Test status
Simulation time 35877602 ps
CPU time 0.98 seconds
Started Feb 29 01:41:49 PM PST 24
Finished Feb 29 01:41:50 PM PST 24
Peak memory 222292 kb
Host smart-455fd951-0fbd-4652-a523-f61790471c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118610725 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2118610725
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/277.edn_genbits.545589708
Short name T178
Test name
Test status
Simulation time 51293756 ps
CPU time 1.46 seconds
Started Feb 29 01:42:31 PM PST 24
Finished Feb 29 01:42:33 PM PST 24
Peak memory 217056 kb
Host smart-43cbfe53-c34d-4be3-9d84-e8543c4c9bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545589708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.545589708
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.241909548
Short name T289
Test name
Test status
Simulation time 34537873 ps
CPU time 1.37 seconds
Started Feb 29 01:42:16 PM PST 24
Finished Feb 29 01:42:18 PM PST 24
Peak memory 217264 kb
Host smart-3f2fb190-010c-4db9-b7c1-6ca40297e674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241909548 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.241909548
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3617750652
Short name T783
Test name
Test status
Simulation time 269853583 ps
CPU time 1.18 seconds
Started Feb 29 01:40:41 PM PST 24
Finished Feb 29 01:40:42 PM PST 24
Peak memory 216108 kb
Host smart-8dc01151-2358-4484-b406-7b6ef8763cd5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617750652 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3617750652
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_alert.1866259752
Short name T164
Test name
Test status
Simulation time 111588318 ps
CPU time 1.28 seconds
Started Feb 29 01:41:09 PM PST 24
Finished Feb 29 01:41:12 PM PST 24
Peak memory 215080 kb
Host smart-7db7bd6a-673d-4d6e-93c3-2019055f5ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866259752 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1866259752
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.1300284506
Short name T85
Test name
Test status
Simulation time 97889562 ps
CPU time 1.11 seconds
Started Feb 29 01:39:48 PM PST 24
Finished Feb 29 01:39:50 PM PST 24
Peak memory 215872 kb
Host smart-f12da100-3f4b-414a-a217-9b4c5705b265
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300284506 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.1300284506
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_disable.1353074127
Short name T111
Test name
Test status
Simulation time 14155622 ps
CPU time 0.94 seconds
Started Feb 29 01:40:52 PM PST 24
Finished Feb 29 01:40:53 PM PST 24
Peak memory 215260 kb
Host smart-8af8108f-a144-414e-848b-0dbfe8f11294
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353074127 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1353074127
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/18.edn_alert_test.2559106265
Short name T301
Test name
Test status
Simulation time 24314302 ps
CPU time 1.1 seconds
Started Feb 29 01:40:41 PM PST 24
Finished Feb 29 01:40:43 PM PST 24
Peak memory 205880 kb
Host smart-29eb95a0-609f-41a6-9364-87711c325ffa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559106265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2559106265
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.682799909
Short name T72
Test name
Test status
Simulation time 90505344 ps
CPU time 1.07 seconds
Started Feb 29 01:40:34 PM PST 24
Finished Feb 29 01:40:35 PM PST 24
Peak memory 217208 kb
Host smart-0d3bc27e-07ea-48ec-ad6b-04953e757b45
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682799909 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.682799909
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.1829388767
Short name T66
Test name
Test status
Simulation time 56206623 ps
CPU time 1.24 seconds
Started Feb 29 01:40:42 PM PST 24
Finished Feb 29 01:40:43 PM PST 24
Peak memory 215884 kb
Host smart-29b8c7f6-c308-4f84-b3d8-a7ae1c69efbf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829388767 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.1829388767
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_disable.3537544504
Short name T106
Test name
Test status
Simulation time 21687797 ps
CPU time 0.86 seconds
Started Feb 29 01:39:55 PM PST 24
Finished Feb 29 01:39:56 PM PST 24
Peak memory 215128 kb
Host smart-19dfaf3a-a465-4054-babe-4cb25322ada9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537544504 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3537544504
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.466839971
Short name T148
Test name
Test status
Simulation time 31615614 ps
CPU time 1.27 seconds
Started Feb 29 01:39:52 PM PST 24
Finished Feb 29 01:39:53 PM PST 24
Peak memory 215960 kb
Host smart-d1317b32-b117-4c54-a25d-ec9c2f00dd4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466839971 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.466839971
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_disable.2779638317
Short name T144
Test name
Test status
Simulation time 53924451 ps
CPU time 0.83 seconds
Started Feb 29 01:40:52 PM PST 24
Finished Feb 29 01:40:53 PM PST 24
Peak memory 215068 kb
Host smart-e50a9cfb-db20-4b66-a55a-92167e2f8e8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779638317 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.2779638317
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable.3729387426
Short name T820
Test name
Test status
Simulation time 49700091 ps
CPU time 0.86 seconds
Started Feb 29 01:41:04 PM PST 24
Finished Feb 29 01:41:05 PM PST 24
Peak memory 215128 kb
Host smart-c1985459-d0ce-4b3d-b87c-fc91fd15b4ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729387426 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.3729387426
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/16.edn_genbits.811007121
Short name T2
Test name
Test status
Simulation time 41476018 ps
CPU time 1.46 seconds
Started Feb 29 01:40:30 PM PST 24
Finished Feb 29 01:40:31 PM PST 24
Peak memory 217040 kb
Host smart-201d6ded-aa35-4404-a1fe-f97ad98f08cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811007121 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.811007121
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.158080621
Short name T264
Test name
Test status
Simulation time 103937782 ps
CPU time 0.96 seconds
Started Feb 29 01:39:55 PM PST 24
Finished Feb 29 01:39:57 PM PST 24
Peak memory 206524 kb
Host smart-6bbe5d02-7e01-4cf6-a682-4b7267a15799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158080621 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.158080621
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/170.edn_genbits.2320280699
Short name T281
Test name
Test status
Simulation time 39952560 ps
CPU time 1.13 seconds
Started Feb 29 01:42:02 PM PST 24
Finished Feb 29 01:42:03 PM PST 24
Peak memory 218696 kb
Host smart-02f2acbe-bba4-44bc-ac19-c5f8ed5982b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320280699 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.2320280699
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_genbits.3645520012
Short name T23
Test name
Test status
Simulation time 161152975 ps
CPU time 2.09 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:50 PM PST 24
Peak memory 217424 kb
Host smart-a6d2e70e-da94-4235-9cba-5069a96023be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645520012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3645520012
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_regwen.2853971555
Short name T118
Test name
Test status
Simulation time 14109363 ps
CPU time 0.97 seconds
Started Feb 29 01:40:15 PM PST 24
Finished Feb 29 01:40:16 PM PST 24
Peak memory 206492 kb
Host smart-9db79833-46ee-4e3c-8694-0a260fa45694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853971555 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2853971555
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_regwen.724876177
Short name T268
Test name
Test status
Simulation time 41527015 ps
CPU time 0.87 seconds
Started Feb 29 01:40:09 PM PST 24
Finished Feb 29 01:40:11 PM PST 24
Peak memory 206464 kb
Host smart-3d1699b3-44b9-48d7-bf07-56f4686dc218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724876177 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.724876177
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_intr.3599222243
Short name T122
Test name
Test status
Simulation time 29390388 ps
CPU time 0.84 seconds
Started Feb 29 01:40:15 PM PST 24
Finished Feb 29 01:40:16 PM PST 24
Peak memory 215012 kb
Host smart-58f54c84-68af-4bb7-a465-2dd1e8116094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599222243 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3599222243
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/22.edn_genbits.3104503544
Short name T288
Test name
Test status
Simulation time 97060604 ps
CPU time 1.23 seconds
Started Feb 29 01:40:45 PM PST 24
Finished Feb 29 01:40:46 PM PST 24
Peak memory 216352 kb
Host smart-16308aa6-5027-4aa2-a67b-fc1c0807ec93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104503544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.3104503544
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.454714203
Short name T221
Test name
Test status
Simulation time 141609852 ps
CPU time 1.5 seconds
Started Feb 29 12:41:35 PM PST 24
Finished Feb 29 12:41:37 PM PST 24
Peak memory 205708 kb
Host smart-f2a6cc94-77ac-4e28-8925-d832900886de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454714203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.454714203
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.909042068
Short name T230
Test name
Test status
Simulation time 37913185 ps
CPU time 1.45 seconds
Started Feb 29 12:41:37 PM PST 24
Finished Feb 29 12:41:39 PM PST 24
Peak memory 206020 kb
Host smart-0e301da1-7f8f-47ce-80ac-b0831ccd43e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909042068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_ou
tstanding.909042068
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.487152222
Short name T247
Test name
Test status
Simulation time 254708249 ps
CPU time 1.68 seconds
Started Feb 29 12:41:34 PM PST 24
Finished Feb 29 12:41:40 PM PST 24
Peak memory 205684 kb
Host smart-4cd69156-eb15-43a6-a741-d5cb24b0f124
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487152222 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.487152222
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/default/100.edn_genbits.2385316143
Short name T642
Test name
Test status
Simulation time 71991675 ps
CPU time 1.2 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:50 PM PST 24
Peak memory 215996 kb
Host smart-585f95de-4d35-42fb-9ef6-7b45c4157eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385316143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2385316143
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.885581858
Short name T293
Test name
Test status
Simulation time 87912159 ps
CPU time 1.29 seconds
Started Feb 29 01:41:53 PM PST 24
Finished Feb 29 01:41:54 PM PST 24
Peak memory 217136 kb
Host smart-1b02aef1-219a-47d5-b41d-7013d73a181d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885581858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.885581858
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.21246681
Short name T282
Test name
Test status
Simulation time 120882512 ps
CPU time 1.24 seconds
Started Feb 29 01:41:53 PM PST 24
Finished Feb 29 01:41:54 PM PST 24
Peak memory 217200 kb
Host smart-ee8dc880-5178-4e08-aa96-d9c7690345ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21246681 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.21246681
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/140.edn_genbits.60402318
Short name T207
Test name
Test status
Simulation time 43735636 ps
CPU time 1.61 seconds
Started Feb 29 01:41:57 PM PST 24
Finished Feb 29 01:41:59 PM PST 24
Peak memory 217352 kb
Host smart-fb1ecd60-be84-4748-b1ef-aa9c2016d809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60402318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.60402318
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.1770460505
Short name T305
Test name
Test status
Simulation time 45364714 ps
CPU time 1.49 seconds
Started Feb 29 01:42:01 PM PST 24
Finished Feb 29 01:42:02 PM PST 24
Peak memory 217144 kb
Host smart-93fcdf9e-3c0c-4cc5-b8d8-4495329c0d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770460505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.1770460505
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.3622928863
Short name T285
Test name
Test status
Simulation time 76714787 ps
CPU time 1.3 seconds
Started Feb 29 01:42:00 PM PST 24
Finished Feb 29 01:42:01 PM PST 24
Peak memory 217604 kb
Host smart-b6878159-f229-4283-94d9-43f86a955dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622928863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3622928863
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.2965341261
Short name T291
Test name
Test status
Simulation time 77309607 ps
CPU time 1.76 seconds
Started Feb 29 01:42:02 PM PST 24
Finished Feb 29 01:42:04 PM PST 24
Peak memory 217340 kb
Host smart-09fc0994-dec0-49fc-bd8c-bb304f0c0fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965341261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.2965341261
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.3225249690
Short name T795
Test name
Test status
Simulation time 81596251 ps
CPU time 1.29 seconds
Started Feb 29 01:42:05 PM PST 24
Finished Feb 29 01:42:07 PM PST 24
Peak memory 217192 kb
Host smart-5f07bdc1-e1fb-4bf0-90e1-60013f2b1c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225249690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.3225249690
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.2195966355
Short name T290
Test name
Test status
Simulation time 76697644 ps
CPU time 1.15 seconds
Started Feb 29 01:42:28 PM PST 24
Finished Feb 29 01:42:30 PM PST 24
Peak memory 217260 kb
Host smart-752e66a9-7f96-4d51-b9a0-eef45a79bcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195966355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.2195966355
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_alert.2192777639
Short name T250
Test name
Test status
Simulation time 26354681 ps
CPU time 1.16 seconds
Started Feb 29 01:41:06 PM PST 24
Finished Feb 29 01:41:08 PM PST 24
Peak memory 215136 kb
Host smart-71c8686e-1f38-4ebd-b94d-85e8f07804a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192777639 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2192777639
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/11.edn_intr.198108834
Short name T153
Test name
Test status
Simulation time 23603862 ps
CPU time 0.98 seconds
Started Feb 29 01:40:17 PM PST 24
Finished Feb 29 01:40:18 PM PST 24
Peak memory 215144 kb
Host smart-c14050d5-f95e-4ced-bc56-c618702e3f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198108834 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.198108834
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/0.edn_disable.488361201
Short name T183
Test name
Test status
Simulation time 30504343 ps
CPU time 0.81 seconds
Started Feb 29 01:39:56 PM PST 24
Finished Feb 29 01:39:57 PM PST 24
Peak memory 214728 kb
Host smart-4bcd57c5-5d59-40b8-a70a-001a89bdfc85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488361201 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.488361201
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable.3219267174
Short name T502
Test name
Test status
Simulation time 31825999 ps
CPU time 0.82 seconds
Started Feb 29 01:39:54 PM PST 24
Finished Feb 29 01:39:55 PM PST 24
Peak memory 214836 kb
Host smart-4d323017-ba60-4ada-bfaf-fd3e80ae589a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219267174 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3219267174
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/19.edn_alert.991711167
Short name T172
Test name
Test status
Simulation time 28640849 ps
CPU time 1.24 seconds
Started Feb 29 01:40:41 PM PST 24
Finished Feb 29 01:40:42 PM PST 24
Peak memory 214900 kb
Host smart-e190ea02-31c7-489f-bdf7-41f7e787e8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991711167 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.991711167
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/115.edn_genbits.2094353237
Short name T409
Test name
Test status
Simulation time 36225138 ps
CPU time 1.39 seconds
Started Feb 29 01:41:52 PM PST 24
Finished Feb 29 01:41:54 PM PST 24
Peak memory 216420 kb
Host smart-b8ce7ffc-01db-4130-a0a0-eccd0f46e50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094353237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2094353237
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_genbits.783670456
Short name T383
Test name
Test status
Simulation time 137347600 ps
CPU time 1.51 seconds
Started Feb 29 01:40:17 PM PST 24
Finished Feb 29 01:40:19 PM PST 24
Peak memory 218372 kb
Host smart-0f1b3c63-65eb-4b64-9071-e49fe4f2a402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783670456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.783670456
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.4035018553
Short name T899
Test name
Test status
Simulation time 27590746 ps
CPU time 1.19 seconds
Started Feb 29 12:41:21 PM PST 24
Finished Feb 29 12:41:23 PM PST 24
Peak memory 205704 kb
Host smart-951e43ef-03aa-4c21-aab9-e2353feee811
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035018553 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.4035018553
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.512580713
Short name T213
Test name
Test status
Simulation time 12623655 ps
CPU time 0.85 seconds
Started Feb 29 12:41:33 PM PST 24
Finished Feb 29 12:41:35 PM PST 24
Peak memory 205704 kb
Host smart-20da18c4-32e1-4242-95ad-f0cd87a0c3a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512580713 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.512580713
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.968256351
Short name T887
Test name
Test status
Simulation time 62801797 ps
CPU time 1.11 seconds
Started Feb 29 12:41:25 PM PST 24
Finished Feb 29 12:41:27 PM PST 24
Peak memory 213924 kb
Host smart-3a7fb911-2855-4997-8099-d3d52b05e95e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968256351 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.968256351
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.2714026102
Short name T903
Test name
Test status
Simulation time 13892168 ps
CPU time 0.84 seconds
Started Feb 29 12:41:35 PM PST 24
Finished Feb 29 12:41:37 PM PST 24
Peak memory 205688 kb
Host smart-d115d8ab-be27-4f82-b77b-5c76c578c100
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714026102 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.2714026102
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2647749406
Short name T900
Test name
Test status
Simulation time 15635763 ps
CPU time 0.9 seconds
Started Feb 29 12:41:39 PM PST 24
Finished Feb 29 12:41:41 PM PST 24
Peak memory 205648 kb
Host smart-a8caf89c-ed9f-45d5-9808-4c99b4ae20c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647749406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2647749406
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.337547313
Short name T940
Test name
Test status
Simulation time 170140458 ps
CPU time 1.12 seconds
Started Feb 29 12:41:21 PM PST 24
Finished Feb 29 12:41:23 PM PST 24
Peak memory 205740 kb
Host smart-3e79a3cb-cca2-48aa-bcd0-3cd7276a5a8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337547313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.337547313
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.2050363694
Short name T861
Test name
Test status
Simulation time 77048559 ps
CPU time 2.69 seconds
Started Feb 29 12:41:31 PM PST 24
Finished Feb 29 12:41:34 PM PST 24
Peak memory 213856 kb
Host smart-c2856a92-8e35-421b-8217-991fbd0348d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050363694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.2050363694
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1569652911
Short name T258
Test name
Test status
Simulation time 262559722 ps
CPU time 2.22 seconds
Started Feb 29 12:41:29 PM PST 24
Finished Feb 29 12:41:31 PM PST 24
Peak memory 205692 kb
Host smart-73b95dc7-92ea-4508-8479-e51d21e31b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569652911 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1569652911
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.303970608
Short name T210
Test name
Test status
Simulation time 36506299 ps
CPU time 2.06 seconds
Started Feb 29 12:41:14 PM PST 24
Finished Feb 29 12:41:16 PM PST 24
Peak memory 205680 kb
Host smart-e52e77db-53a4-4970-ab39-cec1601431b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303970608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.303970608
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1140831046
Short name T877
Test name
Test status
Simulation time 47713907 ps
CPU time 0.88 seconds
Started Feb 29 12:41:38 PM PST 24
Finished Feb 29 12:41:40 PM PST 24
Peak memory 205696 kb
Host smart-cf5df942-d174-4bf7-8616-b6bb2f4970aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140831046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1140831046
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.185054171
Short name T846
Test name
Test status
Simulation time 23080264 ps
CPU time 1 seconds
Started Feb 29 12:41:25 PM PST 24
Finished Feb 29 12:41:27 PM PST 24
Peak memory 205744 kb
Host smart-493bc0f3-d751-493e-b24b-278f829473b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185054171 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.185054171
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3973176727
Short name T956
Test name
Test status
Simulation time 23805561 ps
CPU time 0.85 seconds
Started Feb 29 12:41:39 PM PST 24
Finished Feb 29 12:41:41 PM PST 24
Peak memory 205656 kb
Host smart-16ff6055-d447-45c5-b5c5-944fb905bae0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973176727 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3973176727
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2989788468
Short name T868
Test name
Test status
Simulation time 15538184 ps
CPU time 0.89 seconds
Started Feb 29 12:41:28 PM PST 24
Finished Feb 29 12:41:29 PM PST 24
Peak memory 205624 kb
Host smart-e436faf9-dbcb-4ab9-8d94-7efc910343a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989788468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2989788468
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1134884543
Short name T944
Test name
Test status
Simulation time 51004689 ps
CPU time 1.19 seconds
Started Feb 29 12:41:27 PM PST 24
Finished Feb 29 12:41:29 PM PST 24
Peak memory 205740 kb
Host smart-00dc6f0e-b7c9-4e9c-b17e-1e7d7304821d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134884543 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1134884543
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.3960490555
Short name T908
Test name
Test status
Simulation time 27339043 ps
CPU time 1.83 seconds
Started Feb 29 12:41:30 PM PST 24
Finished Feb 29 12:41:32 PM PST 24
Peak memory 214044 kb
Host smart-ebe53796-fe20-4920-acba-8f5349a7b1af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960490555 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.3960490555
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.1981221935
Short name T895
Test name
Test status
Simulation time 65261440 ps
CPU time 1.81 seconds
Started Feb 29 12:41:43 PM PST 24
Finished Feb 29 12:41:46 PM PST 24
Peak memory 222172 kb
Host smart-a34ad07b-f41e-4c84-a671-d174ba2a683f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981221935 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.1981221935
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1158572951
Short name T882
Test name
Test status
Simulation time 193200043 ps
CPU time 0.83 seconds
Started Feb 29 12:41:29 PM PST 24
Finished Feb 29 12:41:30 PM PST 24
Peak memory 205600 kb
Host smart-c07f784c-96f0-4100-bc8f-e0a16e22ca88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158572951 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1158572951
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.826830156
Short name T961
Test name
Test status
Simulation time 39547860 ps
CPU time 0.86 seconds
Started Feb 29 12:41:39 PM PST 24
Finished Feb 29 12:41:41 PM PST 24
Peak memory 205648 kb
Host smart-1ecbdbab-9a62-4e7c-8944-34da05bc1ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826830156 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.826830156
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2210563971
Short name T898
Test name
Test status
Simulation time 61163499 ps
CPU time 2.38 seconds
Started Feb 29 12:41:40 PM PST 24
Finished Feb 29 12:41:44 PM PST 24
Peak memory 213940 kb
Host smart-3be8b294-93aa-4241-a9df-d5b18d69aef1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210563971 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2210563971
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.343844908
Short name T947
Test name
Test status
Simulation time 27304943 ps
CPU time 1.28 seconds
Started Feb 29 12:41:35 PM PST 24
Finished Feb 29 12:41:37 PM PST 24
Peak memory 213964 kb
Host smart-fcdc66a0-550c-45d9-b708-30d2ecaeadcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343844908 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.343844908
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.1266604937
Short name T224
Test name
Test status
Simulation time 11757111 ps
CPU time 0.85 seconds
Started Feb 29 12:41:47 PM PST 24
Finished Feb 29 12:41:48 PM PST 24
Peak memory 205716 kb
Host smart-ce23e229-d7b8-4a10-8e98-1b2f23a45bb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266604937 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.1266604937
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.244667260
Short name T890
Test name
Test status
Simulation time 46650918 ps
CPU time 0.85 seconds
Started Feb 29 12:41:32 PM PST 24
Finished Feb 29 12:41:33 PM PST 24
Peak memory 205720 kb
Host smart-550a6267-3325-43df-880a-07ab783e9b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244667260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.244667260
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.2334509675
Short name T894
Test name
Test status
Simulation time 50974636 ps
CPU time 1.23 seconds
Started Feb 29 12:41:36 PM PST 24
Finished Feb 29 12:41:40 PM PST 24
Peak memory 205768 kb
Host smart-84077c4c-254b-42b5-a820-ea9d1784fc9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334509675 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_o
utstanding.2334509675
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1941886753
Short name T960
Test name
Test status
Simulation time 212759607 ps
CPU time 3.8 seconds
Started Feb 29 12:41:47 PM PST 24
Finished Feb 29 12:41:51 PM PST 24
Peak memory 214112 kb
Host smart-30e3b1c4-da0b-4f9d-9335-1c4bf678055d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941886753 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1941886753
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.4139007578
Short name T930
Test name
Test status
Simulation time 79911183 ps
CPU time 1.53 seconds
Started Feb 29 12:41:38 PM PST 24
Finished Feb 29 12:41:41 PM PST 24
Peak memory 205764 kb
Host smart-6e7b62c3-dd66-4188-b96c-2951ad7c4a08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139007578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.4139007578
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3844629538
Short name T897
Test name
Test status
Simulation time 22952853 ps
CPU time 1.46 seconds
Started Feb 29 12:41:37 PM PST 24
Finished Feb 29 12:41:39 PM PST 24
Peak memory 213940 kb
Host smart-7b8c3080-93a2-40e7-a07f-ddafbf5bad76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844629538 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3844629538
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1536238502
Short name T914
Test name
Test status
Simulation time 14812043 ps
CPU time 0.89 seconds
Started Feb 29 12:41:31 PM PST 24
Finished Feb 29 12:41:32 PM PST 24
Peak memory 206020 kb
Host smart-119f8df6-1966-45a7-b52d-a2e052269278
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536238502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1536238502
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1441559384
Short name T938
Test name
Test status
Simulation time 35143364 ps
CPU time 0.83 seconds
Started Feb 29 12:42:00 PM PST 24
Finished Feb 29 12:42:06 PM PST 24
Peak memory 205648 kb
Host smart-79e612b7-7433-44fb-81dc-2e5d04d6a812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441559384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1441559384
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.3505924606
Short name T925
Test name
Test status
Simulation time 39992611 ps
CPU time 0.99 seconds
Started Feb 29 12:41:37 PM PST 24
Finished Feb 29 12:41:38 PM PST 24
Peak memory 205716 kb
Host smart-1606f2ad-ae11-4eac-a965-ce4816ac4601
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505924606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.3505924606
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.1412245331
Short name T839
Test name
Test status
Simulation time 97484953 ps
CPU time 2.94 seconds
Started Feb 29 12:41:35 PM PST 24
Finished Feb 29 12:41:38 PM PST 24
Peak memory 214020 kb
Host smart-550f4470-c7c5-46ff-86cf-3f1cd77f77a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412245331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.1412245331
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2185964902
Short name T859
Test name
Test status
Simulation time 201785524 ps
CPU time 2.67 seconds
Started Feb 29 12:41:50 PM PST 24
Finished Feb 29 12:41:52 PM PST 24
Peak memory 205612 kb
Host smart-5f26877e-d526-4fdd-9ecc-fd4d31fe9504
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185964902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2185964902
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.1392569927
Short name T949
Test name
Test status
Simulation time 285371155 ps
CPU time 1.42 seconds
Started Feb 29 12:41:34 PM PST 24
Finished Feb 29 12:41:36 PM PST 24
Peak memory 213884 kb
Host smart-533ddf65-a974-47e9-bbaa-a99ed868a021
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392569927 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.1392569927
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2014706173
Short name T244
Test name
Test status
Simulation time 35873238 ps
CPU time 0.83 seconds
Started Feb 29 12:41:40 PM PST 24
Finished Feb 29 12:41:43 PM PST 24
Peak memory 205544 kb
Host smart-cf776784-05bd-41d4-a47a-7fb1914341da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014706173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2014706173
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.128922325
Short name T871
Test name
Test status
Simulation time 11020460 ps
CPU time 0.82 seconds
Started Feb 29 12:41:36 PM PST 24
Finished Feb 29 12:41:37 PM PST 24
Peak memory 205540 kb
Host smart-67b6ada6-6d04-4bed-9e3b-cb0bcc55ea97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128922325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.128922325
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3831074330
Short name T232
Test name
Test status
Simulation time 31662127 ps
CPU time 1.15 seconds
Started Feb 29 12:41:47 PM PST 24
Finished Feb 29 12:41:49 PM PST 24
Peak memory 206092 kb
Host smart-bf4f1705-2e5e-49ef-b483-0edb02346964
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831074330 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3831074330
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.1284897877
Short name T893
Test name
Test status
Simulation time 22779632 ps
CPU time 1.54 seconds
Started Feb 29 12:41:42 PM PST 24
Finished Feb 29 12:41:45 PM PST 24
Peak memory 213940 kb
Host smart-b7934526-c293-4f83-8efd-1eb7b2102746
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284897877 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.1284897877
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.885420846
Short name T254
Test name
Test status
Simulation time 197450313 ps
CPU time 4.03 seconds
Started Feb 29 12:41:34 PM PST 24
Finished Feb 29 12:41:39 PM PST 24
Peak memory 205808 kb
Host smart-62d89f4e-dd96-4ca7-a98a-a73dcb3f824a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885420846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.885420846
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1669917619
Short name T866
Test name
Test status
Simulation time 18966995 ps
CPU time 1.32 seconds
Started Feb 29 12:41:40 PM PST 24
Finished Feb 29 12:41:42 PM PST 24
Peak memory 213908 kb
Host smart-328b5105-0bb4-4e3b-b5a0-1071cb215880
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669917619 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1669917619
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.2365158846
Short name T229
Test name
Test status
Simulation time 13641481 ps
CPU time 0.89 seconds
Started Feb 29 12:41:32 PM PST 24
Finished Feb 29 12:41:33 PM PST 24
Peak memory 205708 kb
Host smart-dc83d6b6-f3d0-4e16-ad9d-2010e66f02a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365158846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.2365158846
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3922542836
Short name T917
Test name
Test status
Simulation time 24393289 ps
CPU time 0.86 seconds
Started Feb 29 12:41:44 PM PST 24
Finished Feb 29 12:41:46 PM PST 24
Peak memory 205584 kb
Host smart-1810f2b6-0275-4ed8-9e28-768dd28fa202
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922542836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3922542836
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.3017182626
Short name T911
Test name
Test status
Simulation time 18156686 ps
CPU time 1.11 seconds
Started Feb 29 12:41:43 PM PST 24
Finished Feb 29 12:41:45 PM PST 24
Peak memory 205632 kb
Host smart-1a6ac06e-478c-4410-b23d-f33498130052
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017182626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.3017182626
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.363911749
Short name T953
Test name
Test status
Simulation time 39912723 ps
CPU time 1.81 seconds
Started Feb 29 12:41:54 PM PST 24
Finished Feb 29 12:41:56 PM PST 24
Peak memory 214080 kb
Host smart-7efc3c43-ad03-4134-85f1-70d0aeaabd1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363911749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.363911749
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3996315395
Short name T941
Test name
Test status
Simulation time 380265140 ps
CPU time 2.39 seconds
Started Feb 29 12:41:47 PM PST 24
Finished Feb 29 12:41:50 PM PST 24
Peak memory 205720 kb
Host smart-aa20ad35-cb7a-4f79-9f49-d1d674cb3cb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996315395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3996315395
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1067737776
Short name T838
Test name
Test status
Simulation time 62175267 ps
CPU time 1.32 seconds
Started Feb 29 12:41:47 PM PST 24
Finished Feb 29 12:41:49 PM PST 24
Peak memory 215872 kb
Host smart-54c3863a-8854-44e2-a839-5066f7c4280d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067737776 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1067737776
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2576434126
Short name T222
Test name
Test status
Simulation time 13519295 ps
CPU time 0.87 seconds
Started Feb 29 12:41:38 PM PST 24
Finished Feb 29 12:41:39 PM PST 24
Peak memory 205592 kb
Host smart-89b073d5-39da-4938-b6da-24be7b3d98cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576434126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2576434126
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1455161242
Short name T874
Test name
Test status
Simulation time 11528871 ps
CPU time 0.82 seconds
Started Feb 29 12:41:42 PM PST 24
Finished Feb 29 12:41:44 PM PST 24
Peak memory 205640 kb
Host smart-829bee9e-b78f-45e5-99e5-327de1d3ed2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455161242 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1455161242
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.1219713738
Short name T228
Test name
Test status
Simulation time 39854028 ps
CPU time 0.94 seconds
Started Feb 29 12:41:45 PM PST 24
Finished Feb 29 12:41:46 PM PST 24
Peak memory 205724 kb
Host smart-59e2c452-a536-4a42-9ef6-7e4eaa8f3d6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219713738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.1219713738
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2805878571
Short name T852
Test name
Test status
Simulation time 72658071 ps
CPU time 2.74 seconds
Started Feb 29 12:41:32 PM PST 24
Finished Feb 29 12:41:35 PM PST 24
Peak memory 214092 kb
Host smart-687d718a-11f5-4c01-8ad7-c9143ebb799c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805878571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2805878571
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1758827189
Short name T951
Test name
Test status
Simulation time 92905997 ps
CPU time 2.55 seconds
Started Feb 29 12:41:44 PM PST 24
Finished Feb 29 12:41:48 PM PST 24
Peak memory 205724 kb
Host smart-c0cc32f1-d032-49f8-b8ee-06e44c39837e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758827189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1758827189
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.3086716386
Short name T845
Test name
Test status
Simulation time 26458751 ps
CPU time 1.53 seconds
Started Feb 29 12:41:36 PM PST 24
Finished Feb 29 12:41:38 PM PST 24
Peak memory 214036 kb
Host smart-59221662-db65-4e73-b229-c2ea90203d0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086716386 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.3086716386
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.108241324
Short name T948
Test name
Test status
Simulation time 31197879 ps
CPU time 0.86 seconds
Started Feb 29 12:41:33 PM PST 24
Finished Feb 29 12:41:35 PM PST 24
Peak memory 205584 kb
Host smart-3d555185-0e37-48e9-b406-69ac6f51bfbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108241324 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.108241324
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.596270847
Short name T958
Test name
Test status
Simulation time 44868497 ps
CPU time 0.85 seconds
Started Feb 29 12:41:40 PM PST 24
Finished Feb 29 12:41:42 PM PST 24
Peak memory 205596 kb
Host smart-5f95c3d9-79eb-455b-a196-0e6f666a4874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596270847 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.596270847
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3547336271
Short name T943
Test name
Test status
Simulation time 18385806 ps
CPU time 1.19 seconds
Started Feb 29 12:41:30 PM PST 24
Finished Feb 29 12:41:32 PM PST 24
Peak memory 205768 kb
Host smart-7c6aa726-b72e-400a-98db-a6bed4059c95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547336271 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3547336271
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.321976766
Short name T909
Test name
Test status
Simulation time 88257621 ps
CPU time 2.73 seconds
Started Feb 29 12:41:41 PM PST 24
Finished Feb 29 12:41:45 PM PST 24
Peak memory 213892 kb
Host smart-db235ac6-d638-49ab-a0c6-e2e841c93b11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321976766 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.321976766
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4038900931
Short name T876
Test name
Test status
Simulation time 400598952 ps
CPU time 1.51 seconds
Started Feb 29 12:41:42 PM PST 24
Finished Feb 29 12:41:45 PM PST 24
Peak memory 205748 kb
Host smart-e3e1f9dd-6b1d-4659-a437-a3cdde5b6e1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038900931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.4038900931
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.2154882894
Short name T865
Test name
Test status
Simulation time 36589154 ps
CPU time 1.19 seconds
Started Feb 29 12:42:08 PM PST 24
Finished Feb 29 12:42:09 PM PST 24
Peak memory 214024 kb
Host smart-e1355187-6f1f-42ad-a072-d6d873646fc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154882894 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.2154882894
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1423490423
Short name T220
Test name
Test status
Simulation time 14066110 ps
CPU time 0.92 seconds
Started Feb 29 12:41:51 PM PST 24
Finished Feb 29 12:41:52 PM PST 24
Peak memory 205608 kb
Host smart-625065b7-b440-4594-b987-3ba664f4d112
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423490423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1423490423
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.3732963357
Short name T864
Test name
Test status
Simulation time 23704418 ps
CPU time 0.86 seconds
Started Feb 29 12:41:43 PM PST 24
Finished Feb 29 12:41:45 PM PST 24
Peak memory 205600 kb
Host smart-d9ed8d7f-1848-4172-b034-38c027104839
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732963357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.3732963357
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1340452375
Short name T233
Test name
Test status
Simulation time 90442882 ps
CPU time 1.36 seconds
Started Feb 29 12:41:43 PM PST 24
Finished Feb 29 12:41:46 PM PST 24
Peak memory 205804 kb
Host smart-25d2dea5-d55d-4209-bc20-a598da03e2f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340452375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1340452375
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3068675247
Short name T912
Test name
Test status
Simulation time 125191404 ps
CPU time 4.6 seconds
Started Feb 29 12:41:45 PM PST 24
Finished Feb 29 12:41:55 PM PST 24
Peak memory 213976 kb
Host smart-dffa9777-cfc8-47a9-8c3f-ab6c09c49a5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068675247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3068675247
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2576939650
Short name T886
Test name
Test status
Simulation time 68548166 ps
CPU time 2.11 seconds
Started Feb 29 12:41:44 PM PST 24
Finished Feb 29 12:41:48 PM PST 24
Peak memory 205748 kb
Host smart-48546b25-f03f-48a2-bb70-abbf254a9fe2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576939650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2576939650
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3839370974
Short name T966
Test name
Test status
Simulation time 42390108 ps
CPU time 1.41 seconds
Started Feb 29 12:41:47 PM PST 24
Finished Feb 29 12:41:49 PM PST 24
Peak memory 213928 kb
Host smart-344ac182-d914-4678-ae46-63f59d11cab6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839370974 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3839370974
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.1232100914
Short name T902
Test name
Test status
Simulation time 16946011 ps
CPU time 0.93 seconds
Started Feb 29 12:41:49 PM PST 24
Finished Feb 29 12:41:50 PM PST 24
Peak memory 205696 kb
Host smart-4748234a-10a3-4481-98bb-d5247315b118
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232100914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.1232100914
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.231876047
Short name T913
Test name
Test status
Simulation time 15266245 ps
CPU time 0.86 seconds
Started Feb 29 12:41:47 PM PST 24
Finished Feb 29 12:41:49 PM PST 24
Peak memory 205712 kb
Host smart-c6d17cd5-78d9-4d30-bac4-ab05e06b9215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231876047 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.231876047
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.257464956
Short name T217
Test name
Test status
Simulation time 40490429 ps
CPU time 1.11 seconds
Started Feb 29 12:41:45 PM PST 24
Finished Feb 29 12:41:47 PM PST 24
Peak memory 205776 kb
Host smart-0d7abc52-b779-4194-88ed-350d43db590d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257464956 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_ou
tstanding.257464956
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3547062738
Short name T888
Test name
Test status
Simulation time 38070027 ps
CPU time 1.62 seconds
Started Feb 29 12:41:34 PM PST 24
Finished Feb 29 12:41:36 PM PST 24
Peak memory 217056 kb
Host smart-9a1ffde1-771b-4610-8639-36efca0e2109
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547062738 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3547062738
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.1594424631
Short name T257
Test name
Test status
Simulation time 151373170 ps
CPU time 2.22 seconds
Started Feb 29 12:41:42 PM PST 24
Finished Feb 29 12:41:45 PM PST 24
Peak memory 205676 kb
Host smart-7b1a5212-f176-4012-8688-b90dcd8fe39e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594424631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.1594424631
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.1470337660
Short name T867
Test name
Test status
Simulation time 139548797 ps
CPU time 2.21 seconds
Started Feb 29 12:41:54 PM PST 24
Finished Feb 29 12:41:56 PM PST 24
Peak memory 214052 kb
Host smart-bd914203-3c1a-45db-9e35-d4db722a55aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470337660 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.1470337660
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3897266066
Short name T946
Test name
Test status
Simulation time 37838527 ps
CPU time 0.82 seconds
Started Feb 29 12:41:58 PM PST 24
Finished Feb 29 12:41:59 PM PST 24
Peak memory 205676 kb
Host smart-c73138d0-e8fc-42c5-9673-ca89745d5bca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897266066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3897266066
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2739767291
Short name T901
Test name
Test status
Simulation time 19890677 ps
CPU time 0.85 seconds
Started Feb 29 12:41:48 PM PST 24
Finished Feb 29 12:41:49 PM PST 24
Peak memory 205612 kb
Host smart-6d0d4cab-1e34-4f62-9cae-01af9db4998b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739767291 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2739767291
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1682929375
Short name T959
Test name
Test status
Simulation time 43375360 ps
CPU time 0.94 seconds
Started Feb 29 12:41:47 PM PST 24
Finished Feb 29 12:41:49 PM PST 24
Peak memory 205784 kb
Host smart-8e649269-2277-4326-83cc-10469674a83b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682929375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1682929375
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.190164098
Short name T880
Test name
Test status
Simulation time 527992728 ps
CPU time 2.81 seconds
Started Feb 29 12:41:59 PM PST 24
Finished Feb 29 12:42:02 PM PST 24
Peak memory 214076 kb
Host smart-dcae32f9-8627-432b-b6f4-075a205e5053
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190164098 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.190164098
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.3151342662
Short name T916
Test name
Test status
Simulation time 76576487 ps
CPU time 1.4 seconds
Started Feb 29 12:41:47 PM PST 24
Finished Feb 29 12:41:49 PM PST 24
Peak memory 205740 kb
Host smart-74ed0ec2-c9f8-424e-90ce-c33f23560b5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151342662 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.3151342662
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.519727518
Short name T968
Test name
Test status
Simulation time 17606548 ps
CPU time 1.07 seconds
Started Feb 29 12:41:42 PM PST 24
Finished Feb 29 12:41:49 PM PST 24
Peak memory 205720 kb
Host smart-4b31b728-5b1c-4622-8877-c3d01462746d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519727518 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.519727518
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1111071508
Short name T881
Test name
Test status
Simulation time 514192597 ps
CPU time 3.78 seconds
Started Feb 29 12:41:22 PM PST 24
Finished Feb 29 12:41:26 PM PST 24
Peak memory 205744 kb
Host smart-9181c3bb-68a4-44d6-8b1f-8d0cd49a95b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111071508 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1111071508
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.3486730478
Short name T214
Test name
Test status
Simulation time 17857421 ps
CPU time 0.99 seconds
Started Feb 29 12:41:29 PM PST 24
Finished Feb 29 12:41:30 PM PST 24
Peak memory 205720 kb
Host smart-6b46e413-6301-4556-a761-2ca6e0ce146b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486730478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.3486730478
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3622268598
Short name T921
Test name
Test status
Simulation time 34208960 ps
CPU time 1.09 seconds
Started Feb 29 12:41:22 PM PST 24
Finished Feb 29 12:41:24 PM PST 24
Peak memory 213884 kb
Host smart-6650faed-841e-4c55-91c1-f006cead0100
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622268598 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3622268598
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.510371694
Short name T223
Test name
Test status
Simulation time 21259342 ps
CPU time 0.84 seconds
Started Feb 29 12:41:38 PM PST 24
Finished Feb 29 12:41:40 PM PST 24
Peak memory 205612 kb
Host smart-468ec100-986b-4844-9b7c-6b2b8f4d2d0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510371694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.510371694
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3201470678
Short name T952
Test name
Test status
Simulation time 15576963 ps
CPU time 0.86 seconds
Started Feb 29 12:41:29 PM PST 24
Finished Feb 29 12:41:30 PM PST 24
Peak memory 205640 kb
Host smart-7664a708-1f46-45bc-964c-1f470e2415e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201470678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3201470678
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1781116729
Short name T964
Test name
Test status
Simulation time 43198077 ps
CPU time 1.07 seconds
Started Feb 29 12:41:37 PM PST 24
Finished Feb 29 12:41:39 PM PST 24
Peak memory 205684 kb
Host smart-cd72c4a7-d976-4164-8438-d7061dde93af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781116729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1781116729
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.798581942
Short name T954
Test name
Test status
Simulation time 189729393 ps
CPU time 2.26 seconds
Started Feb 29 12:41:41 PM PST 24
Finished Feb 29 12:41:44 PM PST 24
Peak memory 213652 kb
Host smart-4630e39e-1f82-4a7f-83c0-8f31d1dc2fed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798581942 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.798581942
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.1910032974
Short name T915
Test name
Test status
Simulation time 140073435 ps
CPU time 2.91 seconds
Started Feb 29 12:41:38 PM PST 24
Finished Feb 29 12:41:42 PM PST 24
Peak memory 205776 kb
Host smart-2d8eaed2-a57a-496f-a818-c6b0b5d5953b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910032974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.1910032974
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.2226995265
Short name T870
Test name
Test status
Simulation time 11894035 ps
CPU time 0.8 seconds
Started Feb 29 12:41:46 PM PST 24
Finished Feb 29 12:41:47 PM PST 24
Peak memory 205600 kb
Host smart-db55bcc7-969e-4852-865c-08e3608664fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226995265 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.2226995265
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1639373729
Short name T850
Test name
Test status
Simulation time 44674937 ps
CPU time 0.81 seconds
Started Feb 29 12:41:40 PM PST 24
Finished Feb 29 12:41:47 PM PST 24
Peak memory 205636 kb
Host smart-05b9b9e7-e56b-4429-b922-39975a97b2a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639373729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1639373729
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.2397334461
Short name T862
Test name
Test status
Simulation time 46624968 ps
CPU time 0.84 seconds
Started Feb 29 12:41:45 PM PST 24
Finished Feb 29 12:41:47 PM PST 24
Peak memory 205528 kb
Host smart-cdbf46c8-8cef-4e89-86c6-b2ee49ef6dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397334461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.2397334461
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.4215731122
Short name T883
Test name
Test status
Simulation time 61621601 ps
CPU time 0.91 seconds
Started Feb 29 12:41:58 PM PST 24
Finished Feb 29 12:41:59 PM PST 24
Peak memory 205636 kb
Host smart-e6264bdd-4c0b-4126-b6ac-a9113cdc8d1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215731122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.4215731122
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1959450417
Short name T857
Test name
Test status
Simulation time 34744854 ps
CPU time 0.84 seconds
Started Feb 29 12:41:51 PM PST 24
Finished Feb 29 12:42:02 PM PST 24
Peak memory 204844 kb
Host smart-c4d42842-2b13-40a0-9392-d78890a4c8a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959450417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1959450417
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3882713429
Short name T878
Test name
Test status
Simulation time 56764657 ps
CPU time 0.88 seconds
Started Feb 29 12:41:40 PM PST 24
Finished Feb 29 12:41:42 PM PST 24
Peak memory 205528 kb
Host smart-4466c06a-226f-470e-bc17-62656afe491f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882713429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3882713429
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.3294752180
Short name T927
Test name
Test status
Simulation time 27306886 ps
CPU time 0.81 seconds
Started Feb 29 12:41:54 PM PST 24
Finished Feb 29 12:41:55 PM PST 24
Peak memory 205528 kb
Host smart-a99d60c0-49a1-4462-9dd0-b29f81e0df1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294752180 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.3294752180
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2368693436
Short name T929
Test name
Test status
Simulation time 12580605 ps
CPU time 0.93 seconds
Started Feb 29 12:41:41 PM PST 24
Finished Feb 29 12:41:43 PM PST 24
Peak memory 205672 kb
Host smart-73590741-ffaf-454c-93da-f9ff95318fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368693436 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2368693436
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1828262429
Short name T920
Test name
Test status
Simulation time 17975350 ps
CPU time 0.83 seconds
Started Feb 29 12:41:43 PM PST 24
Finished Feb 29 12:41:45 PM PST 24
Peak memory 205596 kb
Host smart-a630b1e5-b42a-41a8-ad75-08a309f634bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828262429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1828262429
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1372921316
Short name T843
Test name
Test status
Simulation time 27288701 ps
CPU time 0.94 seconds
Started Feb 29 12:41:46 PM PST 24
Finished Feb 29 12:41:48 PM PST 24
Peak memory 205740 kb
Host smart-19ae9c2f-77d6-4934-97ce-f514d6e746ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372921316 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1372921316
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2081947626
Short name T860
Test name
Test status
Simulation time 78338764 ps
CPU time 1.37 seconds
Started Feb 29 12:41:25 PM PST 24
Finished Feb 29 12:41:27 PM PST 24
Peak memory 205740 kb
Host smart-7eff6c58-d4d9-471b-baad-b72967dd37d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081947626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2081947626
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.3986793160
Short name T227
Test name
Test status
Simulation time 227419340 ps
CPU time 1.98 seconds
Started Feb 29 12:41:43 PM PST 24
Finished Feb 29 12:41:46 PM PST 24
Peak memory 205668 kb
Host smart-61d5c405-3a2e-42d8-85e7-765d7bf7668e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986793160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.3986793160
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.1723701398
Short name T218
Test name
Test status
Simulation time 15328957 ps
CPU time 0.9 seconds
Started Feb 29 12:41:24 PM PST 24
Finished Feb 29 12:41:25 PM PST 24
Peak memory 205736 kb
Host smart-90fe3ccd-7f7b-466c-9738-01398902f7ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723701398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.1723701398
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.785382827
Short name T853
Test name
Test status
Simulation time 103300151 ps
CPU time 1.29 seconds
Started Feb 29 12:41:38 PM PST 24
Finished Feb 29 12:41:39 PM PST 24
Peak memory 214060 kb
Host smart-f6d4f8f7-3fc4-43fd-b696-a0d01c7d0161
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785382827 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.785382827
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1402797275
Short name T211
Test name
Test status
Simulation time 43424715 ps
CPU time 0.84 seconds
Started Feb 29 12:41:42 PM PST 24
Finished Feb 29 12:41:44 PM PST 24
Peak memory 205692 kb
Host smart-e9cf33c9-bd57-4f2e-8b22-a6d45ff1ded8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402797275 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1402797275
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.817530470
Short name T873
Test name
Test status
Simulation time 24352256 ps
CPU time 0.83 seconds
Started Feb 29 12:41:30 PM PST 24
Finished Feb 29 12:41:32 PM PST 24
Peak memory 205608 kb
Host smart-c0414e3d-e3ab-4999-a0af-d5c6690645a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817530470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.817530470
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1213336904
Short name T231
Test name
Test status
Simulation time 39868880 ps
CPU time 0.91 seconds
Started Feb 29 12:41:25 PM PST 24
Finished Feb 29 12:41:27 PM PST 24
Peak memory 205680 kb
Host smart-1a863c88-6c77-4eb8-9f36-7bba8d3c66d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213336904 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1213336904
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.3418362153
Short name T858
Test name
Test status
Simulation time 177361428 ps
CPU time 2.04 seconds
Started Feb 29 12:41:42 PM PST 24
Finished Feb 29 12:41:45 PM PST 24
Peak memory 213960 kb
Host smart-07ff6d50-1385-434e-8f86-20c0e9f47695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418362153 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.3418362153
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1181914011
Short name T924
Test name
Test status
Simulation time 281185862 ps
CPU time 1.72 seconds
Started Feb 29 12:41:41 PM PST 24
Finished Feb 29 12:41:44 PM PST 24
Peak memory 205620 kb
Host smart-d62f46e6-4827-4601-8de7-9900556b46f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181914011 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1181914011
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2571865787
Short name T963
Test name
Test status
Simulation time 91102323 ps
CPU time 0.85 seconds
Started Feb 29 12:41:59 PM PST 24
Finished Feb 29 12:42:00 PM PST 24
Peak memory 205696 kb
Host smart-2bc1f503-a282-4596-8c6f-4aabf62ebe9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571865787 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2571865787
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3686966578
Short name T933
Test name
Test status
Simulation time 11686902 ps
CPU time 0.87 seconds
Started Feb 29 12:41:29 PM PST 24
Finished Feb 29 12:41:30 PM PST 24
Peak memory 205636 kb
Host smart-bf1496ab-fc67-492a-952e-be29556635f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686966578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3686966578
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.556006512
Short name T928
Test name
Test status
Simulation time 14419781 ps
CPU time 0.84 seconds
Started Feb 29 12:41:39 PM PST 24
Finished Feb 29 12:41:42 PM PST 24
Peak memory 205684 kb
Host smart-6f124ff8-d78c-496c-b670-3ce717f5dddb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556006512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.556006512
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.978013671
Short name T851
Test name
Test status
Simulation time 16805976 ps
CPU time 0.92 seconds
Started Feb 29 12:41:41 PM PST 24
Finished Feb 29 12:41:43 PM PST 24
Peak memory 205956 kb
Host smart-4158475b-d776-401e-b839-91151ec539e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978013671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.978013671
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3969403609
Short name T842
Test name
Test status
Simulation time 32585269 ps
CPU time 0.79 seconds
Started Feb 29 12:41:48 PM PST 24
Finished Feb 29 12:41:49 PM PST 24
Peak memory 205564 kb
Host smart-b7041a29-a249-4225-a92b-a9ae02c68c19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969403609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3969403609
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3470373048
Short name T918
Test name
Test status
Simulation time 48044200 ps
CPU time 0.85 seconds
Started Feb 29 12:41:43 PM PST 24
Finished Feb 29 12:41:45 PM PST 24
Peak memory 205596 kb
Host smart-caa58b9e-7bc3-4c3a-a551-784e42c008ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470373048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3470373048
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.3555483447
Short name T896
Test name
Test status
Simulation time 10793732 ps
CPU time 0.85 seconds
Started Feb 29 12:41:55 PM PST 24
Finished Feb 29 12:41:57 PM PST 24
Peak memory 205616 kb
Host smart-25b26c6c-42b3-43fa-a697-dbebf88634f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555483447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.3555483447
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.1501893761
Short name T848
Test name
Test status
Simulation time 160318846 ps
CPU time 0.86 seconds
Started Feb 29 12:41:40 PM PST 24
Finished Feb 29 12:41:42 PM PST 24
Peak memory 205556 kb
Host smart-d068b5b1-fb1a-4484-a6fa-668b79c32cfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501893761 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.1501893761
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1619647930
Short name T945
Test name
Test status
Simulation time 17316035 ps
CPU time 0.93 seconds
Started Feb 29 12:41:43 PM PST 24
Finished Feb 29 12:41:46 PM PST 24
Peak memory 205548 kb
Host smart-1a504f48-e16a-43c7-b4a2-35ed25eaf04d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619647930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1619647930
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2725877118
Short name T854
Test name
Test status
Simulation time 48043973 ps
CPU time 0.82 seconds
Started Feb 29 12:41:55 PM PST 24
Finished Feb 29 12:41:56 PM PST 24
Peak memory 205632 kb
Host smart-a557ba04-58de-41ea-88f3-9b8e03bac51f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725877118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2725877118
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.4142600091
Short name T923
Test name
Test status
Simulation time 38406891 ps
CPU time 1.11 seconds
Started Feb 29 12:41:30 PM PST 24
Finished Feb 29 12:41:31 PM PST 24
Peak memory 205692 kb
Host smart-e086c78a-4963-421e-b720-19632e457bb6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142600091 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.4142600091
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.1247467775
Short name T226
Test name
Test status
Simulation time 213057321 ps
CPU time 3.08 seconds
Started Feb 29 12:41:21 PM PST 24
Finished Feb 29 12:41:25 PM PST 24
Peak memory 205700 kb
Host smart-e5b717d0-0510-4070-9d73-8b74c0f1e1f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247467775 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.1247467775
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1204995589
Short name T922
Test name
Test status
Simulation time 46878119 ps
CPU time 0.86 seconds
Started Feb 29 12:41:32 PM PST 24
Finished Feb 29 12:41:34 PM PST 24
Peak memory 205600 kb
Host smart-0a688cb8-1e85-44ed-8bc5-625d4784e75c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204995589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1204995589
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.4136827729
Short name T919
Test name
Test status
Simulation time 75842060 ps
CPU time 1.14 seconds
Started Feb 29 12:41:41 PM PST 24
Finished Feb 29 12:41:43 PM PST 24
Peak memory 213988 kb
Host smart-915bbbb4-f696-4cce-ad85-6a0806daec13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136827729 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.4136827729
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2491298577
Short name T225
Test name
Test status
Simulation time 17271876 ps
CPU time 0.79 seconds
Started Feb 29 12:41:25 PM PST 24
Finished Feb 29 12:41:26 PM PST 24
Peak memory 205668 kb
Host smart-bc71549d-4c1e-4de1-812a-3b2a19b1eef9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491298577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2491298577
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.956185415
Short name T904
Test name
Test status
Simulation time 16348156 ps
CPU time 0.92 seconds
Started Feb 29 12:41:25 PM PST 24
Finished Feb 29 12:41:27 PM PST 24
Peak memory 204420 kb
Host smart-467083b6-fe4e-47fb-8540-bb036f9c3651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956185415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.956185415
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.583177946
Short name T931
Test name
Test status
Simulation time 37094991 ps
CPU time 1.46 seconds
Started Feb 29 12:41:37 PM PST 24
Finished Feb 29 12:41:39 PM PST 24
Peak memory 205716 kb
Host smart-42549d02-4196-472e-94cc-107f7b1d97f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583177946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.583177946
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.1515881146
Short name T892
Test name
Test status
Simulation time 148670335 ps
CPU time 2.76 seconds
Started Feb 29 12:41:22 PM PST 24
Finished Feb 29 12:41:26 PM PST 24
Peak memory 214056 kb
Host smart-b36d46be-cb94-4030-b065-bc7c53cf6548
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515881146 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.1515881146
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.858849466
Short name T875
Test name
Test status
Simulation time 80925209 ps
CPU time 1.58 seconds
Started Feb 29 12:41:29 PM PST 24
Finished Feb 29 12:41:31 PM PST 24
Peak memory 205760 kb
Host smart-6e59a1c9-6575-4fdc-9360-c3ee92f6b7f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858849466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.858849466
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.2660854711
Short name T905
Test name
Test status
Simulation time 125048727 ps
CPU time 0.83 seconds
Started Feb 29 12:42:02 PM PST 24
Finished Feb 29 12:42:03 PM PST 24
Peak memory 205532 kb
Host smart-5e0855f8-de4a-40ca-a2ba-54fda3f1ffbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660854711 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.2660854711
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.3029645622
Short name T847
Test name
Test status
Simulation time 25596934 ps
CPU time 0.85 seconds
Started Feb 29 12:41:42 PM PST 24
Finished Feb 29 12:41:44 PM PST 24
Peak memory 205676 kb
Host smart-7809e0c4-7f25-433d-8917-9dbf32cffb68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029645622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.3029645622
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.3814837236
Short name T932
Test name
Test status
Simulation time 38064829 ps
CPU time 0.85 seconds
Started Feb 29 12:41:43 PM PST 24
Finished Feb 29 12:41:45 PM PST 24
Peak memory 205688 kb
Host smart-1819db01-bad7-4230-9f91-95c9fd3da7c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814837236 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.3814837236
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.292990470
Short name T841
Test name
Test status
Simulation time 12581429 ps
CPU time 0.85 seconds
Started Feb 29 12:41:59 PM PST 24
Finished Feb 29 12:42:00 PM PST 24
Peak memory 205616 kb
Host smart-d5ec1b1a-7058-4b72-88ed-dad7a76fa95b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292990470 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.292990470
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2435825958
Short name T950
Test name
Test status
Simulation time 23964443 ps
CPU time 0.84 seconds
Started Feb 29 12:41:47 PM PST 24
Finished Feb 29 12:41:49 PM PST 24
Peak memory 205640 kb
Host smart-0cd7e723-0c52-48f3-bda0-684035744fb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435825958 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2435825958
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.3559192849
Short name T957
Test name
Test status
Simulation time 88718313 ps
CPU time 0.77 seconds
Started Feb 29 12:41:45 PM PST 24
Finished Feb 29 12:41:46 PM PST 24
Peak memory 205516 kb
Host smart-bd1c9621-0dc6-489e-a9e9-90f501236cec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559192849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.3559192849
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.940139821
Short name T855
Test name
Test status
Simulation time 157682775 ps
CPU time 0.9 seconds
Started Feb 29 12:41:57 PM PST 24
Finished Feb 29 12:41:58 PM PST 24
Peak memory 205684 kb
Host smart-b3110894-161c-4931-b884-3c6bc82c7f60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940139821 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.940139821
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1338169249
Short name T869
Test name
Test status
Simulation time 37410820 ps
CPU time 0.85 seconds
Started Feb 29 12:41:52 PM PST 24
Finished Feb 29 12:41:53 PM PST 24
Peak memory 205600 kb
Host smart-f377279e-2e25-4719-b84b-da927d8a11b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338169249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1338169249
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3148676181
Short name T840
Test name
Test status
Simulation time 22178810 ps
CPU time 0.84 seconds
Started Feb 29 12:41:42 PM PST 24
Finished Feb 29 12:41:43 PM PST 24
Peak memory 205588 kb
Host smart-7285b567-9c2d-41aa-8157-4c8c28d9487c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148676181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3148676181
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.2514873941
Short name T856
Test name
Test status
Simulation time 37369943 ps
CPU time 0.8 seconds
Started Feb 29 12:41:49 PM PST 24
Finished Feb 29 12:41:55 PM PST 24
Peak memory 205544 kb
Host smart-edbf0804-db18-4fd4-9637-52bfb6e336b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514873941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.2514873941
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1076315696
Short name T863
Test name
Test status
Simulation time 66659865 ps
CPU time 1.29 seconds
Started Feb 29 12:41:38 PM PST 24
Finished Feb 29 12:41:40 PM PST 24
Peak memory 213972 kb
Host smart-0525e6fc-2ee5-4086-a804-92e999142206
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076315696 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1076315696
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.1886985823
Short name T967
Test name
Test status
Simulation time 29178294 ps
CPU time 0.84 seconds
Started Feb 29 12:41:36 PM PST 24
Finished Feb 29 12:41:38 PM PST 24
Peak memory 205624 kb
Host smart-192dfb94-5945-4f5c-97cb-a48b390ca830
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886985823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.1886985823
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2299939672
Short name T935
Test name
Test status
Simulation time 100043964 ps
CPU time 0.9 seconds
Started Feb 29 12:41:29 PM PST 24
Finished Feb 29 12:41:30 PM PST 24
Peak memory 205628 kb
Host smart-238bc4c9-afb6-4b74-8c9a-c6acb45fed24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299939672 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2299939672
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3207945763
Short name T234
Test name
Test status
Simulation time 35648427 ps
CPU time 0.94 seconds
Started Feb 29 12:41:29 PM PST 24
Finished Feb 29 12:41:30 PM PST 24
Peak memory 205668 kb
Host smart-de6defc9-5ce1-412b-98c2-f8bec4d0eb6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207945763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3207945763
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2089160358
Short name T849
Test name
Test status
Simulation time 111759311 ps
CPU time 2.04 seconds
Started Feb 29 12:41:35 PM PST 24
Finished Feb 29 12:41:38 PM PST 24
Peak memory 213984 kb
Host smart-6dcacd78-2a22-42e8-9948-a98ef0316367
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089160358 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2089160358
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2924639941
Short name T246
Test name
Test status
Simulation time 56592729 ps
CPU time 1.79 seconds
Started Feb 29 12:41:25 PM PST 24
Finished Feb 29 12:41:28 PM PST 24
Peak memory 204508 kb
Host smart-e580bfb4-6749-44fa-9d13-ab247f2c1906
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924639941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2924639941
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.2663777134
Short name T872
Test name
Test status
Simulation time 21416981 ps
CPU time 1.49 seconds
Started Feb 29 12:41:43 PM PST 24
Finished Feb 29 12:41:46 PM PST 24
Peak memory 213976 kb
Host smart-9907ff40-f0b0-4e11-9ea2-a90f23b32046
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663777134 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.2663777134
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2116289205
Short name T884
Test name
Test status
Simulation time 42651601 ps
CPU time 0.84 seconds
Started Feb 29 12:41:27 PM PST 24
Finished Feb 29 12:41:28 PM PST 24
Peak memory 205580 kb
Host smart-64a213c6-1515-4990-9deb-38848960ab6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116289205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2116289205
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.1168982489
Short name T965
Test name
Test status
Simulation time 11535668 ps
CPU time 0.82 seconds
Started Feb 29 12:41:43 PM PST 24
Finished Feb 29 12:41:45 PM PST 24
Peak memory 205612 kb
Host smart-7bbcd1cf-37a2-43b5-9aa2-7e12264a11d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168982489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.1168982489
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3854763804
Short name T910
Test name
Test status
Simulation time 54869073 ps
CPU time 1.07 seconds
Started Feb 29 12:41:31 PM PST 24
Finished Feb 29 12:41:32 PM PST 24
Peak memory 205760 kb
Host smart-a6f820a3-b52a-446c-812b-b7150decf3be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854763804 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3854763804
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1931641695
Short name T844
Test name
Test status
Simulation time 106983771 ps
CPU time 1.99 seconds
Started Feb 29 12:41:47 PM PST 24
Finished Feb 29 12:41:49 PM PST 24
Peak memory 214084 kb
Host smart-139ece67-b8d0-4230-8739-2bedc189d698
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931641695 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1931641695
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.4195344726
Short name T256
Test name
Test status
Simulation time 387744355 ps
CPU time 1.61 seconds
Started Feb 29 12:41:39 PM PST 24
Finished Feb 29 12:41:41 PM PST 24
Peak memory 205720 kb
Host smart-5084213a-b482-40e9-b635-b5b25476d27e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195344726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.4195344726
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.1729723652
Short name T937
Test name
Test status
Simulation time 28924407 ps
CPU time 1.69 seconds
Started Feb 29 12:41:42 PM PST 24
Finished Feb 29 12:41:44 PM PST 24
Peak memory 213932 kb
Host smart-a4e553cf-b816-40c7-afb6-ac03a6836164
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729723652 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.1729723652
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.468020337
Short name T936
Test name
Test status
Simulation time 55223647 ps
CPU time 0.91 seconds
Started Feb 29 12:41:31 PM PST 24
Finished Feb 29 12:41:32 PM PST 24
Peak memory 205688 kb
Host smart-23d4104f-3cd3-4563-96d6-da94807ea7d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468020337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.468020337
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3114761312
Short name T891
Test name
Test status
Simulation time 18744727 ps
CPU time 0.89 seconds
Started Feb 29 12:41:45 PM PST 24
Finished Feb 29 12:41:47 PM PST 24
Peak memory 205628 kb
Host smart-8b36d58c-e871-4532-b7d0-746dfe2a656c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114761312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3114761312
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2722370810
Short name T215
Test name
Test status
Simulation time 128892846 ps
CPU time 1.32 seconds
Started Feb 29 12:41:43 PM PST 24
Finished Feb 29 12:41:45 PM PST 24
Peak memory 205716 kb
Host smart-89389d3b-dfc0-4983-9048-50a387f28438
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722370810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2722370810
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3722400641
Short name T942
Test name
Test status
Simulation time 24628037 ps
CPU time 1.65 seconds
Started Feb 29 12:41:45 PM PST 24
Finished Feb 29 12:41:48 PM PST 24
Peak memory 214116 kb
Host smart-ddc34637-70b4-4f44-9b74-1ee65620dbca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722400641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3722400641
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.2842033160
Short name T255
Test name
Test status
Simulation time 198562314 ps
CPU time 2.79 seconds
Started Feb 29 12:41:40 PM PST 24
Finished Feb 29 12:41:44 PM PST 24
Peak memory 205676 kb
Host smart-3f0bf0d5-03d5-488b-894d-e9459deec5bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842033160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.2842033160
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1824742168
Short name T906
Test name
Test status
Simulation time 23782220 ps
CPU time 1.25 seconds
Started Feb 29 12:41:30 PM PST 24
Finished Feb 29 12:41:31 PM PST 24
Peak memory 205792 kb
Host smart-e75dfafb-8a10-458d-a737-4b9ea6085e0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824742168 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1824742168
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.2993736103
Short name T885
Test name
Test status
Simulation time 27708725 ps
CPU time 0.83 seconds
Started Feb 29 12:41:24 PM PST 24
Finished Feb 29 12:41:26 PM PST 24
Peak memory 205692 kb
Host smart-8d6ca6ba-a53b-4e77-b20e-6b77793d2a3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993736103 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.2993736103
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2607869604
Short name T955
Test name
Test status
Simulation time 41614225 ps
CPU time 0.87 seconds
Started Feb 29 12:41:34 PM PST 24
Finished Feb 29 12:41:36 PM PST 24
Peak memory 205728 kb
Host smart-979d7363-3a27-41e0-b08b-4498cd699c04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607869604 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2607869604
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.859788407
Short name T907
Test name
Test status
Simulation time 80514875 ps
CPU time 1.06 seconds
Started Feb 29 12:41:33 PM PST 24
Finished Feb 29 12:41:35 PM PST 24
Peak memory 205784 kb
Host smart-f7501246-0528-457b-acbc-dca9ca68b481
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859788407 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_out
standing.859788407
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.3635772283
Short name T962
Test name
Test status
Simulation time 199958991 ps
CPU time 1.91 seconds
Started Feb 29 12:41:38 PM PST 24
Finished Feb 29 12:41:41 PM PST 24
Peak memory 213976 kb
Host smart-744b31b3-8817-4868-8bb3-092b21be2e66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635772283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.3635772283
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1596455344
Short name T889
Test name
Test status
Simulation time 51356284 ps
CPU time 1.77 seconds
Started Feb 29 12:41:38 PM PST 24
Finished Feb 29 12:41:40 PM PST 24
Peak memory 205684 kb
Host smart-d154a201-70b5-4961-850a-26e9213f0f25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596455344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1596455344
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1486394411
Short name T939
Test name
Test status
Simulation time 63696736 ps
CPU time 1.55 seconds
Started Feb 29 12:41:40 PM PST 24
Finished Feb 29 12:41:43 PM PST 24
Peak memory 214020 kb
Host smart-8a018a88-98a6-4ee3-b73e-d5add9c348e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486394411 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1486394411
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.3653770783
Short name T219
Test name
Test status
Simulation time 13437036 ps
CPU time 0.93 seconds
Started Feb 29 12:41:27 PM PST 24
Finished Feb 29 12:41:29 PM PST 24
Peak memory 204984 kb
Host smart-a6ef6f25-cd1b-4c35-8650-d04f56c4426c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653770783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.3653770783
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.2881800424
Short name T926
Test name
Test status
Simulation time 23530622 ps
CPU time 0.87 seconds
Started Feb 29 12:41:43 PM PST 24
Finished Feb 29 12:41:46 PM PST 24
Peak memory 205628 kb
Host smart-8203b140-758d-43de-a8e4-cd4b510a6c1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881800424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.2881800424
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2846637438
Short name T216
Test name
Test status
Simulation time 16426889 ps
CPU time 1.02 seconds
Started Feb 29 12:41:39 PM PST 24
Finished Feb 29 12:41:42 PM PST 24
Peak memory 205748 kb
Host smart-fada52ce-fe8b-456b-869b-740d52689b64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846637438 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2846637438
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3806816440
Short name T879
Test name
Test status
Simulation time 75302260 ps
CPU time 1.52 seconds
Started Feb 29 12:41:24 PM PST 24
Finished Feb 29 12:41:26 PM PST 24
Peak memory 214032 kb
Host smart-1df678ed-af7b-44d5-86c5-62a5de0bf3cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806816440 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3806816440
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.1051890614
Short name T934
Test name
Test status
Simulation time 85795172 ps
CPU time 2.35 seconds
Started Feb 29 12:41:45 PM PST 24
Finished Feb 29 12:41:48 PM PST 24
Peak memory 205700 kb
Host smart-a2f244e6-6e9b-4452-8c85-978aca042a14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051890614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.1051890614
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.2249697634
Short name T552
Test name
Test status
Simulation time 42837564 ps
CPU time 1.22 seconds
Started Feb 29 01:39:50 PM PST 24
Finished Feb 29 01:39:51 PM PST 24
Peak memory 215060 kb
Host smart-c03fa093-11ea-4691-a845-e17cb6157d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249697634 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2249697634
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.729277760
Short name T451
Test name
Test status
Simulation time 19588359 ps
CPU time 1.01 seconds
Started Feb 29 01:39:57 PM PST 24
Finished Feb 29 01:39:58 PM PST 24
Peak memory 205880 kb
Host smart-3c4093e2-0d93-4320-942d-84c9fbc066d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729277760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.729277760
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_err.4229113675
Short name T529
Test name
Test status
Simulation time 34024473 ps
CPU time 1.04 seconds
Started Feb 29 01:39:49 PM PST 24
Finished Feb 29 01:39:50 PM PST 24
Peak memory 229216 kb
Host smart-f72dbe34-26c8-45b7-b9b3-ac60bc949caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229113675 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.4229113675
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.2425210088
Short name T26
Test name
Test status
Simulation time 55233794 ps
CPU time 1.25 seconds
Started Feb 29 01:39:53 PM PST 24
Finished Feb 29 01:39:54 PM PST 24
Peak memory 216044 kb
Host smart-4188b817-2fd2-41b1-818b-6872f20ea5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425210088 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.2425210088
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.763299693
Short name T127
Test name
Test status
Simulation time 21791203 ps
CPU time 1.09 seconds
Started Feb 29 01:39:50 PM PST 24
Finished Feb 29 01:39:51 PM PST 24
Peak memory 215280 kb
Host smart-bcd1ba47-78fd-439d-8a3b-f5fcd102ad54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763299693 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.763299693
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.1947845864
Short name T208
Test name
Test status
Simulation time 24221276 ps
CPU time 0.94 seconds
Started Feb 29 01:39:48 PM PST 24
Finished Feb 29 01:39:49 PM PST 24
Peak memory 206656 kb
Host smart-71550339-9592-4943-a2f0-24e7c259137d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947845864 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1947845864
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1074399764
Short name T45
Test name
Test status
Simulation time 919493376 ps
CPU time 4.21 seconds
Started Feb 29 01:39:55 PM PST 24
Finished Feb 29 01:40:00 PM PST 24
Peak memory 234116 kb
Host smart-a4d0284c-ad8b-43c0-aa5a-da439739618d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074399764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1074399764
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2986886259
Short name T308
Test name
Test status
Simulation time 73595725 ps
CPU time 0.94 seconds
Started Feb 29 01:39:51 PM PST 24
Finished Feb 29 01:39:52 PM PST 24
Peak memory 214696 kb
Host smart-175137e4-3b09-4ba1-978b-0832d74f0f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986886259 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2986886259
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3870827826
Short name T442
Test name
Test status
Simulation time 147199754 ps
CPU time 2 seconds
Started Feb 29 01:40:00 PM PST 24
Finished Feb 29 01:40:02 PM PST 24
Peak memory 215856 kb
Host smart-250da3a0-a416-48db-a9fe-457fd7c756d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870827826 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3870827826
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.920299852
Short name T665
Test name
Test status
Simulation time 50559414533 ps
CPU time 493 seconds
Started Feb 29 01:39:55 PM PST 24
Finished Feb 29 01:48:08 PM PST 24
Peak memory 217588 kb
Host smart-644e7d1c-0b7d-4e35-9d24-f5c25c691cec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920299852 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.920299852
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.2764921849
Short name T263
Test name
Test status
Simulation time 38652519 ps
CPU time 1.13 seconds
Started Feb 29 01:39:56 PM PST 24
Finished Feb 29 01:39:57 PM PST 24
Peak memory 214996 kb
Host smart-0299ff78-e990-4dc9-ae51-97574014a2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764921849 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.2764921849
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.187546171
Short name T362
Test name
Test status
Simulation time 40810303 ps
CPU time 0.97 seconds
Started Feb 29 01:39:54 PM PST 24
Finished Feb 29 01:39:55 PM PST 24
Peak memory 206272 kb
Host smart-4397eb27-cdc5-4e9b-9ec0-2dc7f0bf3c6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187546171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.187546171
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.501378460
Short name T349
Test name
Test status
Simulation time 46078560 ps
CPU time 1.09 seconds
Started Feb 29 01:39:53 PM PST 24
Finished Feb 29 01:39:55 PM PST 24
Peak memory 215784 kb
Host smart-c496d6cf-7e14-4945-9e9e-3898536951ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501378460 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_dis
able_auto_req_mode.501378460
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.388943249
Short name T41
Test name
Test status
Simulation time 18379631 ps
CPU time 1.13 seconds
Started Feb 29 01:39:51 PM PST 24
Finished Feb 29 01:39:52 PM PST 24
Peak memory 222396 kb
Host smart-a6ce9e46-0da2-494e-a255-686689ea40e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388943249 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.388943249
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.1515066508
Short name T463
Test name
Test status
Simulation time 89936166 ps
CPU time 1.43 seconds
Started Feb 29 01:39:55 PM PST 24
Finished Feb 29 01:39:57 PM PST 24
Peak memory 217368 kb
Host smart-12f4dc66-b0cc-481e-8892-7f14e95de6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515066508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.1515066508
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.2347273345
Short name T471
Test name
Test status
Simulation time 25001372 ps
CPU time 0.96 seconds
Started Feb 29 01:39:55 PM PST 24
Finished Feb 29 01:39:56 PM PST 24
Peak memory 214884 kb
Host smart-86b9438f-6844-455b-90d8-b4b1875b12b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347273345 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.2347273345
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2299488068
Short name T19
Test name
Test status
Simulation time 554917762 ps
CPU time 4.72 seconds
Started Feb 29 01:39:53 PM PST 24
Finished Feb 29 01:39:58 PM PST 24
Peak memory 232672 kb
Host smart-d063fe3f-f9f7-4300-a480-e0bfdce6a90f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299488068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2299488068
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.3917204562
Short name T373
Test name
Test status
Simulation time 17508657 ps
CPU time 0.98 seconds
Started Feb 29 01:39:52 PM PST 24
Finished Feb 29 01:39:53 PM PST 24
Peak memory 214896 kb
Host smart-590281dd-8590-4496-8781-69a60f08c2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917204562 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.3917204562
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.2833442501
Short name T792
Test name
Test status
Simulation time 81858455 ps
CPU time 2.18 seconds
Started Feb 29 01:39:53 PM PST 24
Finished Feb 29 01:39:56 PM PST 24
Peak memory 216084 kb
Host smart-fbbfaa5e-261a-4cf0-a948-8ae87dd3e1df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833442501 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.2833442501
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.1278290117
Short name T467
Test name
Test status
Simulation time 332561776709 ps
CPU time 2501.87 seconds
Started Feb 29 01:39:51 PM PST 24
Finished Feb 29 02:21:34 PM PST 24
Peak memory 227024 kb
Host smart-8daf0c1a-e6d0-4087-9b43-0f52726c4f69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278290117 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.1278290117
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.3278336997
Short name T807
Test name
Test status
Simulation time 23775044 ps
CPU time 1.19 seconds
Started Feb 29 01:40:13 PM PST 24
Finished Feb 29 01:40:15 PM PST 24
Peak memory 215068 kb
Host smart-ed6b1c3d-880a-440c-98a2-24721191e90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278336997 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.3278336997
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.567442608
Short name T833
Test name
Test status
Simulation time 135387118 ps
CPU time 1.06 seconds
Started Feb 29 01:40:16 PM PST 24
Finished Feb 29 01:40:17 PM PST 24
Peak memory 206252 kb
Host smart-b47666f9-da75-4885-ba3a-89475a2d4d5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567442608 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.567442608
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.3040538445
Short name T745
Test name
Test status
Simulation time 32644500 ps
CPU time 0.85 seconds
Started Feb 29 01:40:14 PM PST 24
Finished Feb 29 01:40:15 PM PST 24
Peak memory 214852 kb
Host smart-91b19f99-c7d8-4fa5-ac52-75727202183b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040538445 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.3040538445
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1643839016
Short name T9
Test name
Test status
Simulation time 103911041 ps
CPU time 1.13 seconds
Started Feb 29 01:40:15 PM PST 24
Finished Feb 29 01:40:16 PM PST 24
Peak memory 217000 kb
Host smart-d7ed2bbc-b94e-4801-b417-5a591d309d9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643839016 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1643839016
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.1332311451
Short name T69
Test name
Test status
Simulation time 41614853 ps
CPU time 1.06 seconds
Started Feb 29 01:40:15 PM PST 24
Finished Feb 29 01:40:16 PM PST 24
Peak memory 215936 kb
Host smart-cf7f31ab-a448-4a29-a4b7-c0bb26a66939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332311451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.1332311451
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1943132700
Short name T622
Test name
Test status
Simulation time 89811693 ps
CPU time 2.17 seconds
Started Feb 29 01:40:18 PM PST 24
Finished Feb 29 01:40:21 PM PST 24
Peak memory 216276 kb
Host smart-0106919a-336d-43f0-b932-c6a46c5c267e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943132700 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1943132700
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.2509403293
Short name T575
Test name
Test status
Simulation time 22251638 ps
CPU time 1.09 seconds
Started Feb 29 01:40:16 PM PST 24
Finished Feb 29 01:40:17 PM PST 24
Peak memory 214960 kb
Host smart-98dd79c1-fe77-426b-911b-b53a9ceb8064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509403293 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2509403293
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.456172766
Short name T414
Test name
Test status
Simulation time 23385171 ps
CPU time 1.08 seconds
Started Feb 29 01:40:19 PM PST 24
Finished Feb 29 01:40:20 PM PST 24
Peak memory 214636 kb
Host smart-72426526-baca-41e7-a1ee-6f1a5843deb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456172766 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.456172766
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3003643461
Short name T747
Test name
Test status
Simulation time 137682896 ps
CPU time 1.78 seconds
Started Feb 29 01:40:26 PM PST 24
Finished Feb 29 01:40:28 PM PST 24
Peak memory 215948 kb
Host smart-d976c5f2-3866-4b02-bd29-4cef079faa9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003643461 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3003643461
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3617221784
Short name T194
Test name
Test status
Simulation time 181099379414 ps
CPU time 765.91 seconds
Started Feb 29 01:40:15 PM PST 24
Finished Feb 29 01:53:01 PM PST 24
Peak memory 218868 kb
Host smart-24b70e66-1142-4df2-8cc1-d2aa135aabc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617221784 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3617221784
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.edn_genbits.2661008880
Short name T706
Test name
Test status
Simulation time 94606981 ps
CPU time 1.46 seconds
Started Feb 29 01:41:49 PM PST 24
Finished Feb 29 01:41:50 PM PST 24
Peak memory 217908 kb
Host smart-73cc931f-f328-4b96-8d39-2e8044eeb247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661008880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2661008880
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.1512906035
Short name T604
Test name
Test status
Simulation time 121662284 ps
CPU time 1.5 seconds
Started Feb 29 01:41:55 PM PST 24
Finished Feb 29 01:41:56 PM PST 24
Peak memory 218148 kb
Host smart-17ba64a1-d75d-452f-a599-607ad8d41fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512906035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.1512906035
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.2655442567
Short name T760
Test name
Test status
Simulation time 124779353 ps
CPU time 1.58 seconds
Started Feb 29 01:41:49 PM PST 24
Finished Feb 29 01:41:51 PM PST 24
Peak memory 217464 kb
Host smart-718bfca6-b25f-48e8-a25f-e929255607c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655442567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.2655442567
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1543445861
Short name T636
Test name
Test status
Simulation time 36655703 ps
CPU time 1.52 seconds
Started Feb 29 01:41:44 PM PST 24
Finished Feb 29 01:41:46 PM PST 24
Peak memory 217392 kb
Host smart-6542c745-f9c5-42c3-918c-30c571e6fbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543445861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1543445861
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.742842008
Short name T428
Test name
Test status
Simulation time 28163725 ps
CPU time 1.59 seconds
Started Feb 29 01:41:55 PM PST 24
Finished Feb 29 01:41:57 PM PST 24
Peak memory 217492 kb
Host smart-acef798c-2809-4731-bc96-53721e3f4c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742842008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.742842008
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.1064978141
Short name T51
Test name
Test status
Simulation time 91253351 ps
CPU time 1.12 seconds
Started Feb 29 01:41:53 PM PST 24
Finished Feb 29 01:41:54 PM PST 24
Peak memory 215832 kb
Host smart-39379eea-965d-4dba-85be-50421625e9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064978141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1064978141
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.1240877624
Short name T284
Test name
Test status
Simulation time 118899089 ps
CPU time 2.52 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:51 PM PST 24
Peak memory 218240 kb
Host smart-3380b918-a1bf-4a0f-a1f3-88324f61beda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240877624 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.1240877624
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.1857052761
Short name T673
Test name
Test status
Simulation time 159953306 ps
CPU time 1.26 seconds
Started Feb 29 01:40:17 PM PST 24
Finished Feb 29 01:40:18 PM PST 24
Peak memory 215044 kb
Host smart-2402a1ae-d59b-4e18-a725-20121b769a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857052761 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1857052761
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.2569882616
Short name T332
Test name
Test status
Simulation time 18969311 ps
CPU time 0.93 seconds
Started Feb 29 01:40:22 PM PST 24
Finished Feb 29 01:40:23 PM PST 24
Peak memory 205388 kb
Host smart-569df93e-4b2b-4b06-b560-b60d417950fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569882616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.2569882616
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.3421341647
Short name T756
Test name
Test status
Simulation time 22631334 ps
CPU time 0.88 seconds
Started Feb 29 01:40:19 PM PST 24
Finished Feb 29 01:40:21 PM PST 24
Peak memory 215164 kb
Host smart-8b7347f0-8995-4b0e-99ee-15870526fab1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421341647 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.3421341647
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2560696362
Short name T134
Test name
Test status
Simulation time 71073679 ps
CPU time 1.09 seconds
Started Feb 29 01:40:15 PM PST 24
Finished Feb 29 01:40:17 PM PST 24
Peak memory 217076 kb
Host smart-6e665d9e-141c-48d5-8688-6fe665731860
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560696362 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2560696362
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.3722758683
Short name T406
Test name
Test status
Simulation time 49026218 ps
CPU time 1.09 seconds
Started Feb 29 01:40:17 PM PST 24
Finished Feb 29 01:40:18 PM PST 24
Peak memory 230680 kb
Host smart-6652d814-c823-4404-9971-4f57ea342e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722758683 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.3722758683
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.2359702196
Short name T700
Test name
Test status
Simulation time 40689576 ps
CPU time 1.47 seconds
Started Feb 29 01:40:17 PM PST 24
Finished Feb 29 01:40:18 PM PST 24
Peak memory 215916 kb
Host smart-5c390c57-2cdc-4a47-beb3-7289cae9ac25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359702196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.2359702196
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_smoke.1702476880
Short name T565
Test name
Test status
Simulation time 16856545 ps
CPU time 1.02 seconds
Started Feb 29 01:40:17 PM PST 24
Finished Feb 29 01:40:18 PM PST 24
Peak memory 214676 kb
Host smart-6ff492d8-0906-4e9a-bbbf-33fbf4405f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702476880 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.1702476880
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.2035876645
Short name T785
Test name
Test status
Simulation time 220741391 ps
CPU time 4.91 seconds
Started Feb 29 01:40:16 PM PST 24
Finished Feb 29 01:40:21 PM PST 24
Peak memory 214724 kb
Host smart-3abae10b-c8fd-4f8f-ad1c-a293990e4351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035876645 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.2035876645
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.4094663729
Short name T550
Test name
Test status
Simulation time 124985495773 ps
CPU time 763.52 seconds
Started Feb 29 01:40:19 PM PST 24
Finished Feb 29 01:53:02 PM PST 24
Peak memory 223092 kb
Host smart-f0595de5-1495-4091-95d4-603bcf91e889
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094663729 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.4094663729
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.3130854536
Short name T517
Test name
Test status
Simulation time 63933017 ps
CPU time 1.27 seconds
Started Feb 29 01:41:49 PM PST 24
Finished Feb 29 01:41:51 PM PST 24
Peak memory 218224 kb
Host smart-45ce4108-50f9-49cf-a6be-3c6fa683adf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130854536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.3130854536
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.971445697
Short name T621
Test name
Test status
Simulation time 27080229 ps
CPU time 1.22 seconds
Started Feb 29 01:41:44 PM PST 24
Finished Feb 29 01:41:45 PM PST 24
Peak memory 216032 kb
Host smart-467695ce-8e5f-4d1e-ab1f-effb2be271f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971445697 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.971445697
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.481658556
Short name T448
Test name
Test status
Simulation time 68213389 ps
CPU time 1.29 seconds
Started Feb 29 01:41:49 PM PST 24
Finished Feb 29 01:41:51 PM PST 24
Peak memory 217220 kb
Host smart-e8114cda-1c78-4cc8-a671-6ed37ed01884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481658556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.481658556
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.4276913914
Short name T477
Test name
Test status
Simulation time 75828583 ps
CPU time 1.04 seconds
Started Feb 29 01:41:55 PM PST 24
Finished Feb 29 01:41:56 PM PST 24
Peak memory 215988 kb
Host smart-7d952fd5-78ab-47e3-81d4-8c80ad63b690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276913914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.4276913914
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.3347399862
Short name T389
Test name
Test status
Simulation time 65872516 ps
CPU time 1.51 seconds
Started Feb 29 01:41:46 PM PST 24
Finished Feb 29 01:41:48 PM PST 24
Peak memory 217440 kb
Host smart-ba43d4fc-0fd8-47ae-a8d8-1648c0ebc51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347399862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3347399862
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.2976957936
Short name T798
Test name
Test status
Simulation time 84244099 ps
CPU time 1.41 seconds
Started Feb 29 01:41:53 PM PST 24
Finished Feb 29 01:41:54 PM PST 24
Peak memory 218324 kb
Host smart-ca7a2e06-7733-47e3-b480-7ad396e5a1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976957936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.2976957936
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.2149165935
Short name T366
Test name
Test status
Simulation time 270171189 ps
CPU time 1.34 seconds
Started Feb 29 01:41:49 PM PST 24
Finished Feb 29 01:41:50 PM PST 24
Peak memory 218816 kb
Host smart-bfd1a1d4-3601-4620-b79f-67522928ee17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149165935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.2149165935
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.1099387975
Short name T415
Test name
Test status
Simulation time 73017619 ps
CPU time 1.31 seconds
Started Feb 29 01:41:46 PM PST 24
Finished Feb 29 01:41:47 PM PST 24
Peak memory 217252 kb
Host smart-a45082c6-54d4-4700-9250-07d2c3be60f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099387975 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.1099387975
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.1317196714
Short name T702
Test name
Test status
Simulation time 454164401 ps
CPU time 4.91 seconds
Started Feb 29 01:41:47 PM PST 24
Finished Feb 29 01:41:53 PM PST 24
Peak memory 217872 kb
Host smart-62391fb7-965b-4945-912f-80984c9eed0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317196714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.1317196714
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1928025169
Short name T812
Test name
Test status
Simulation time 46300063 ps
CPU time 1.15 seconds
Started Feb 29 01:40:27 PM PST 24
Finished Feb 29 01:40:28 PM PST 24
Peak memory 215032 kb
Host smart-3cb2652d-231e-4b8c-b07f-15204d1de6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928025169 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1928025169
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2851070576
Short name T299
Test name
Test status
Simulation time 17293554 ps
CPU time 0.94 seconds
Started Feb 29 01:40:17 PM PST 24
Finished Feb 29 01:40:18 PM PST 24
Peak memory 206200 kb
Host smart-4309f6aa-fb97-4d21-8c1e-c70244703e70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851070576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2851070576
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.2732576145
Short name T93
Test name
Test status
Simulation time 35395912 ps
CPU time 0.8 seconds
Started Feb 29 01:40:16 PM PST 24
Finished Feb 29 01:40:17 PM PST 24
Peak memory 215196 kb
Host smart-9afe6aa0-f6aa-4fb9-a919-08a39d046627
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732576145 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2732576145
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.3707486084
Short name T5
Test name
Test status
Simulation time 52114596 ps
CPU time 1.05 seconds
Started Feb 29 01:40:24 PM PST 24
Finished Feb 29 01:40:25 PM PST 24
Peak memory 229064 kb
Host smart-acf16c68-bfc6-4c5b-9e44-476a6f9487a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707486084 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3707486084
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_intr.41116072
Short name T524
Test name
Test status
Simulation time 53180960 ps
CPU time 0.97 seconds
Started Feb 29 01:40:24 PM PST 24
Finished Feb 29 01:40:25 PM PST 24
Peak memory 222368 kb
Host smart-107bdc46-aafb-4c9d-a6bd-c5f6598fabea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41116072 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.41116072
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.259083234
Short name T53
Test name
Test status
Simulation time 36200052 ps
CPU time 1.02 seconds
Started Feb 29 01:40:18 PM PST 24
Finished Feb 29 01:40:19 PM PST 24
Peak memory 214772 kb
Host smart-f2990c04-f514-4de0-86ed-11a367bcba99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259083234 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.259083234
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.480088297
Short name T307
Test name
Test status
Simulation time 26008483 ps
CPU time 1.24 seconds
Started Feb 29 01:40:19 PM PST 24
Finished Feb 29 01:40:20 PM PST 24
Peak memory 214744 kb
Host smart-a69255ac-9308-44a6-a23a-9d8cf43745b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480088297 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.480088297
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.2700060388
Short name T48
Test name
Test status
Simulation time 272720004636 ps
CPU time 3233.34 seconds
Started Feb 29 01:40:22 PM PST 24
Finished Feb 29 02:34:16 PM PST 24
Peak memory 229260 kb
Host smart-b81ec39f-4574-49ce-84ec-7f63a7e19744
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700060388 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.2700060388
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.2090954396
Short name T387
Test name
Test status
Simulation time 43428327 ps
CPU time 1.29 seconds
Started Feb 29 01:41:53 PM PST 24
Finished Feb 29 01:41:54 PM PST 24
Peak memory 217244 kb
Host smart-dd85d1da-529d-4c51-a6fa-512d5a6119e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090954396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2090954396
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.3255546879
Short name T181
Test name
Test status
Simulation time 84260456 ps
CPU time 2.02 seconds
Started Feb 29 01:41:45 PM PST 24
Finished Feb 29 01:41:47 PM PST 24
Peak memory 217912 kb
Host smart-0dba1174-472b-4e00-b053-6049f9539ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255546879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.3255546879
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.3250287267
Short name T345
Test name
Test status
Simulation time 43599125 ps
CPU time 1.7 seconds
Started Feb 29 01:41:49 PM PST 24
Finished Feb 29 01:41:51 PM PST 24
Peak memory 217268 kb
Host smart-57d64d29-0ab7-4a38-82b2-fab085d9295f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250287267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.3250287267
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.3195641858
Short name T619
Test name
Test status
Simulation time 91036339 ps
CPU time 1.43 seconds
Started Feb 29 01:41:46 PM PST 24
Finished Feb 29 01:41:48 PM PST 24
Peak memory 218768 kb
Host smart-c77b53d8-449c-4b4e-9a7a-10ca3468b973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195641858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3195641858
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.1525685322
Short name T671
Test name
Test status
Simulation time 50934697 ps
CPU time 1.63 seconds
Started Feb 29 01:41:45 PM PST 24
Finished Feb 29 01:41:47 PM PST 24
Peak memory 217152 kb
Host smart-8ed683ea-6a67-452e-9409-54522231d7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525685322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.1525685322
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.230144185
Short name T434
Test name
Test status
Simulation time 51123053 ps
CPU time 1.65 seconds
Started Feb 29 01:41:47 PM PST 24
Finished Feb 29 01:41:49 PM PST 24
Peak memory 217156 kb
Host smart-c4b10d91-7817-45ce-9e01-41d0019fa0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230144185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.230144185
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.225348165
Short name T287
Test name
Test status
Simulation time 37380819 ps
CPU time 1.51 seconds
Started Feb 29 01:41:47 PM PST 24
Finished Feb 29 01:41:48 PM PST 24
Peak memory 216160 kb
Host smart-a5214228-5609-4c31-ab8b-c001b2628709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225348165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.225348165
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.3524764348
Short name T380
Test name
Test status
Simulation time 28889062 ps
CPU time 1.1 seconds
Started Feb 29 01:41:49 PM PST 24
Finished Feb 29 01:41:50 PM PST 24
Peak memory 216000 kb
Host smart-8efc69df-f013-4497-988b-b4c2b15997bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524764348 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3524764348
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.3592408355
Short name T680
Test name
Test status
Simulation time 114890317 ps
CPU time 1.52 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:50 PM PST 24
Peak memory 217428 kb
Host smart-ac8850b1-d2ab-43c9-9b20-ee443bcc5456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592408355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3592408355
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.3065743573
Short name T483
Test name
Test status
Simulation time 168631639 ps
CPU time 3.39 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:52 PM PST 24
Peak memory 218004 kb
Host smart-f63f7727-4b2a-46a6-abf6-e766e5e94446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065743573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.3065743573
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.957079372
Short name T116
Test name
Test status
Simulation time 89619558 ps
CPU time 1.22 seconds
Started Feb 29 01:40:24 PM PST 24
Finished Feb 29 01:40:25 PM PST 24
Peak memory 215056 kb
Host smart-ff930ddc-da4c-4598-9bb9-9b66c38f8d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957079372 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.957079372
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3567152303
Short name T753
Test name
Test status
Simulation time 22477218 ps
CPU time 0.99 seconds
Started Feb 29 01:40:31 PM PST 24
Finished Feb 29 01:40:32 PM PST 24
Peak memory 206024 kb
Host smart-50587790-457e-4d19-9256-691cb6131e1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567152303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3567152303
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3834067313
Short name T580
Test name
Test status
Simulation time 11520511 ps
CPU time 0.91 seconds
Started Feb 29 01:40:27 PM PST 24
Finished Feb 29 01:40:28 PM PST 24
Peak memory 214952 kb
Host smart-668b97a2-404f-4c74-a50e-bfc3df9feb57
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834067313 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3834067313
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.78888490
Short name T633
Test name
Test status
Simulation time 51165354 ps
CPU time 1.28 seconds
Started Feb 29 01:40:30 PM PST 24
Finished Feb 29 01:40:31 PM PST 24
Peak memory 215748 kb
Host smart-1ae98372-426e-4a80-907a-2af66fe2c383
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78888490 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_dis
able_auto_req_mode.78888490
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1552688817
Short name T82
Test name
Test status
Simulation time 23783900 ps
CPU time 1.14 seconds
Started Feb 29 01:40:30 PM PST 24
Finished Feb 29 01:40:32 PM PST 24
Peak memory 216028 kb
Host smart-363937ea-d4cf-46a0-adc3-93168103f38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552688817 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1552688817
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.1252556092
Short name T813
Test name
Test status
Simulation time 181684239 ps
CPU time 2.82 seconds
Started Feb 29 01:40:27 PM PST 24
Finished Feb 29 01:40:30 PM PST 24
Peak memory 217324 kb
Host smart-1a5957bd-8d1d-439e-bd7f-8524ff41251f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252556092 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.1252556092
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3567981234
Short name T691
Test name
Test status
Simulation time 82516117 ps
CPU time 0.79 seconds
Started Feb 29 01:40:25 PM PST 24
Finished Feb 29 01:40:26 PM PST 24
Peak memory 214756 kb
Host smart-2250fe83-3b74-4e80-b0bd-1972f5fc40cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567981234 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3567981234
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.3704972819
Short name T618
Test name
Test status
Simulation time 40565456 ps
CPU time 0.94 seconds
Started Feb 29 01:40:13 PM PST 24
Finished Feb 29 01:40:14 PM PST 24
Peak memory 214800 kb
Host smart-e7d781a8-902e-4445-8e84-a4137b4b6378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704972819 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3704972819
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.3208532829
Short name T511
Test name
Test status
Simulation time 238966393 ps
CPU time 5.23 seconds
Started Feb 29 01:40:22 PM PST 24
Finished Feb 29 01:40:27 PM PST 24
Peak memory 218936 kb
Host smart-a80bf6cf-2b1e-4462-82c0-7c00b389d5fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208532829 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.3208532829
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1646523935
Short name T21
Test name
Test status
Simulation time 109253176630 ps
CPU time 1338.91 seconds
Started Feb 29 01:40:16 PM PST 24
Finished Feb 29 02:02:35 PM PST 24
Peak memory 221652 kb
Host smart-38a82db9-40de-4113-ad19-b3050ec637a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646523935 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1646523935
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.1779752055
Short name T810
Test name
Test status
Simulation time 29022083 ps
CPU time 1.32 seconds
Started Feb 29 01:41:50 PM PST 24
Finished Feb 29 01:41:51 PM PST 24
Peak memory 216036 kb
Host smart-6ba036b1-9e3b-4b43-8080-374573bfa153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779752055 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1779752055
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.3613158340
Short name T767
Test name
Test status
Simulation time 49218575 ps
CPU time 1.2 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:50 PM PST 24
Peak memory 216180 kb
Host smart-f8a9712b-21c2-45d6-b47c-917926305cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613158340 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.3613158340
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.713294637
Short name T600
Test name
Test status
Simulation time 59876881 ps
CPU time 1.4 seconds
Started Feb 29 01:41:47 PM PST 24
Finished Feb 29 01:41:48 PM PST 24
Peak memory 217332 kb
Host smart-d829d203-1d19-476e-a387-e7cf9ffa5b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713294637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.713294637
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.3105974136
Short name T784
Test name
Test status
Simulation time 87266172 ps
CPU time 1.22 seconds
Started Feb 29 01:41:46 PM PST 24
Finished Feb 29 01:41:48 PM PST 24
Peak memory 216152 kb
Host smart-a90740e0-00cb-4348-aff3-d9028dd64d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105974136 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3105974136
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2609189388
Short name T367
Test name
Test status
Simulation time 76541667 ps
CPU time 1.55 seconds
Started Feb 29 01:41:58 PM PST 24
Finished Feb 29 01:41:59 PM PST 24
Peak memory 217540 kb
Host smart-7316fa91-2404-43c6-b940-881ea0dfa1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609189388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2609189388
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.1868389032
Short name T488
Test name
Test status
Simulation time 43463830 ps
CPU time 1.73 seconds
Started Feb 29 01:41:58 PM PST 24
Finished Feb 29 01:42:00 PM PST 24
Peak memory 217276 kb
Host smart-556c473e-4f60-45c1-a219-26c1dd0e95fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868389032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1868389032
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.47804830
Short name T363
Test name
Test status
Simulation time 83471102 ps
CPU time 1.43 seconds
Started Feb 29 01:41:59 PM PST 24
Finished Feb 29 01:42:00 PM PST 24
Peak memory 217432 kb
Host smart-4cb3f3d9-c3b3-4c9b-81d0-4fabc935baca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47804830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.47804830
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.2076844891
Short name T804
Test name
Test status
Simulation time 142712076 ps
CPU time 2.99 seconds
Started Feb 29 01:42:02 PM PST 24
Finished Feb 29 01:42:05 PM PST 24
Peak memory 216192 kb
Host smart-9c5727f2-f071-4951-823e-c8d1e050d0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076844891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.2076844891
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.2633951164
Short name T563
Test name
Test status
Simulation time 54791171 ps
CPU time 1.66 seconds
Started Feb 29 01:42:02 PM PST 24
Finished Feb 29 01:42:04 PM PST 24
Peak memory 217356 kb
Host smart-8b8bd2a5-cee6-44d8-ab30-b879a1fe289f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633951164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2633951164
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.84755664
Short name T251
Test name
Test status
Simulation time 43339137 ps
CPU time 1.12 seconds
Started Feb 29 01:42:12 PM PST 24
Finished Feb 29 01:42:14 PM PST 24
Peak memory 217220 kb
Host smart-b9c7c267-5722-45ce-8f5b-7908d382b320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84755664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.84755664
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.85863758
Short name T800
Test name
Test status
Simulation time 26936876 ps
CPU time 1.18 seconds
Started Feb 29 01:40:33 PM PST 24
Finished Feb 29 01:40:34 PM PST 24
Peak memory 215064 kb
Host smart-08078e0e-9788-47e1-baf5-397dbfe3f0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85863758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.85863758
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.4153273128
Short name T312
Test name
Test status
Simulation time 28967367 ps
CPU time 0.92 seconds
Started Feb 29 01:40:37 PM PST 24
Finished Feb 29 01:40:38 PM PST 24
Peak memory 205916 kb
Host smart-529cb9b1-59d9-4ac6-85dd-9be1d2c12bbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153273128 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.4153273128
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1766347556
Short name T750
Test name
Test status
Simulation time 13808816 ps
CPU time 0.9 seconds
Started Feb 29 01:40:27 PM PST 24
Finished Feb 29 01:40:28 PM PST 24
Peak memory 215036 kb
Host smart-15ed6509-6916-4b9a-9074-754d3f01ddf1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766347556 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1766347556
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.1059552789
Short name T836
Test name
Test status
Simulation time 75728369 ps
CPU time 0.82 seconds
Started Feb 29 01:40:30 PM PST 24
Finished Feb 29 01:40:31 PM PST 24
Peak memory 216932 kb
Host smart-bb708003-d101-4db0-b359-618c56082dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059552789 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1059552789
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2550668833
Short name T490
Test name
Test status
Simulation time 35691980 ps
CPU time 1.43 seconds
Started Feb 29 01:40:29 PM PST 24
Finished Feb 29 01:40:30 PM PST 24
Peak memory 218404 kb
Host smart-7c029a65-f337-4f79-bbbc-bcdbdb16ef7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550668833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2550668833
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.1023105830
Short name T721
Test name
Test status
Simulation time 22330742 ps
CPU time 1.23 seconds
Started Feb 29 01:40:26 PM PST 24
Finished Feb 29 01:40:28 PM PST 24
Peak memory 231892 kb
Host smart-d2340e8b-ee1b-49d5-abb5-2ef4c5647774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023105830 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.1023105830
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2417375421
Short name T704
Test name
Test status
Simulation time 119215891 ps
CPU time 0.91 seconds
Started Feb 29 01:40:26 PM PST 24
Finished Feb 29 01:40:27 PM PST 24
Peak memory 214764 kb
Host smart-a4ba73db-74f1-46d4-a924-2a34b9753582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417375421 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2417375421
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1028907989
Short name T273
Test name
Test status
Simulation time 31175387 ps
CPU time 1.23 seconds
Started Feb 29 01:40:30 PM PST 24
Finished Feb 29 01:40:31 PM PST 24
Peak memory 214816 kb
Host smart-3a73c971-7690-40ad-af8a-bf107e4c6c15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028907989 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1028907989
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.1173862555
Short name T435
Test name
Test status
Simulation time 15017833095 ps
CPU time 409.01 seconds
Started Feb 29 01:40:31 PM PST 24
Finished Feb 29 01:47:20 PM PST 24
Peak memory 217088 kb
Host smart-67990c81-6904-4fce-a774-f332aa984f91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173862555 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.1173862555
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.edn_genbits.320470444
Short name T462
Test name
Test status
Simulation time 334778547 ps
CPU time 1.54 seconds
Started Feb 29 01:41:58 PM PST 24
Finished Feb 29 01:42:00 PM PST 24
Peak memory 217536 kb
Host smart-12f741c3-abaa-4350-bd66-b48c0bfd341f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320470444 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.320470444
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.3997383771
Short name T399
Test name
Test status
Simulation time 29161842 ps
CPU time 1.3 seconds
Started Feb 29 01:42:01 PM PST 24
Finished Feb 29 01:42:02 PM PST 24
Peak memory 216144 kb
Host smart-590a5b01-a27e-4832-a097-72a2e1e2b707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997383771 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3997383771
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.34831928
Short name T440
Test name
Test status
Simulation time 29826364 ps
CPU time 1.28 seconds
Started Feb 29 01:42:01 PM PST 24
Finished Feb 29 01:42:03 PM PST 24
Peak memory 216144 kb
Host smart-3b4737ec-ea49-40c3-8956-5c49e7559b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34831928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.34831928
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.2513974158
Short name T831
Test name
Test status
Simulation time 49902194 ps
CPU time 1.28 seconds
Started Feb 29 01:41:58 PM PST 24
Finished Feb 29 01:42:00 PM PST 24
Peak memory 217152 kb
Host smart-0471804d-061a-45a5-aae2-7eb13372c5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513974158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2513974158
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.2876171256
Short name T482
Test name
Test status
Simulation time 74821469 ps
CPU time 1.28 seconds
Started Feb 29 01:42:01 PM PST 24
Finished Feb 29 01:42:03 PM PST 24
Peak memory 217312 kb
Host smart-4c3125bd-3400-494b-98cb-a6e0a7b99c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876171256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.2876171256
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.1905958006
Short name T336
Test name
Test status
Simulation time 43982214 ps
CPU time 1.07 seconds
Started Feb 29 01:42:00 PM PST 24
Finished Feb 29 01:42:01 PM PST 24
Peak memory 218424 kb
Host smart-7fbbe745-746c-4310-bf60-7570a4da1e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905958006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1905958006
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.123881566
Short name T501
Test name
Test status
Simulation time 35607153 ps
CPU time 1.46 seconds
Started Feb 29 01:42:01 PM PST 24
Finished Feb 29 01:42:02 PM PST 24
Peak memory 217144 kb
Host smart-2d4ff175-37b9-497f-93b4-92bd8d4ef40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123881566 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.123881566
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.3167805643
Short name T762
Test name
Test status
Simulation time 84210961 ps
CPU time 1.28 seconds
Started Feb 29 01:42:02 PM PST 24
Finished Feb 29 01:42:03 PM PST 24
Peak memory 217784 kb
Host smart-673f8c07-7a6b-4c66-8c0c-e7c840bcf3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167805643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3167805643
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3598429014
Short name T825
Test name
Test status
Simulation time 83373588 ps
CPU time 1.11 seconds
Started Feb 29 01:40:28 PM PST 24
Finished Feb 29 01:40:30 PM PST 24
Peak memory 215052 kb
Host smart-56271607-d11c-41f6-b93e-9299328fd4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598429014 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3598429014
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3274059564
Short name T510
Test name
Test status
Simulation time 62859443 ps
CPU time 0.87 seconds
Started Feb 29 01:40:31 PM PST 24
Finished Feb 29 01:40:32 PM PST 24
Peak memory 205876 kb
Host smart-23d06106-488f-4855-a745-01638d365351
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274059564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3274059564
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.3079762514
Short name T492
Test name
Test status
Simulation time 82205252 ps
CPU time 0.85 seconds
Started Feb 29 01:40:29 PM PST 24
Finished Feb 29 01:40:30 PM PST 24
Peak memory 214876 kb
Host smart-e56d46bd-8c32-4413-a78f-23d7c53f079e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079762514 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3079762514
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3121204059
Short name T824
Test name
Test status
Simulation time 56614650 ps
CPU time 1.06 seconds
Started Feb 29 01:40:30 PM PST 24
Finished Feb 29 01:40:31 PM PST 24
Peak memory 217228 kb
Host smart-4ff2daf2-d537-409c-ac1b-c75d4fa9df93
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121204059 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3121204059
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.3934879779
Short name T76
Test name
Test status
Simulation time 24028659 ps
CPU time 1.12 seconds
Started Feb 29 01:40:33 PM PST 24
Finished Feb 29 01:40:34 PM PST 24
Peak memory 222508 kb
Host smart-8c273ec8-3ca5-45c3-822f-ee8b4a26c835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934879779 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.3934879779
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.863280241
Short name T422
Test name
Test status
Simulation time 33266466 ps
CPU time 1.61 seconds
Started Feb 29 01:40:28 PM PST 24
Finished Feb 29 01:40:30 PM PST 24
Peak memory 218448 kb
Host smart-cc620a16-f89f-4056-90ba-817c35ff7794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863280241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.863280241
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.827741333
Short name T39
Test name
Test status
Simulation time 35816309 ps
CPU time 0.99 seconds
Started Feb 29 01:40:32 PM PST 24
Finished Feb 29 01:40:33 PM PST 24
Peak memory 222672 kb
Host smart-9039b8b5-422e-45fb-9e0e-0989377c4683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827741333 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.827741333
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.1817073603
Short name T378
Test name
Test status
Simulation time 19438597 ps
CPU time 1.07 seconds
Started Feb 29 01:40:30 PM PST 24
Finished Feb 29 01:40:31 PM PST 24
Peak memory 206460 kb
Host smart-7ed39f32-725b-47f6-ab98-25e4792b71c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817073603 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.1817073603
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.3088357813
Short name T423
Test name
Test status
Simulation time 943214109 ps
CPU time 4.2 seconds
Started Feb 29 01:40:31 PM PST 24
Finished Feb 29 01:40:36 PM PST 24
Peak memory 218656 kb
Host smart-030e5a1a-d305-4d72-8ddf-b1ecdfd812e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088357813 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.3088357813
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.3304978128
Short name T188
Test name
Test status
Simulation time 73283791755 ps
CPU time 848.02 seconds
Started Feb 29 01:40:28 PM PST 24
Finished Feb 29 01:54:36 PM PST 24
Peak memory 223136 kb
Host smart-5a9880b8-5042-447e-9583-5e4ea1d3f6fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304978128 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.3304978128
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.3431301046
Short name T567
Test name
Test status
Simulation time 89357364 ps
CPU time 1.46 seconds
Started Feb 29 01:42:01 PM PST 24
Finished Feb 29 01:42:02 PM PST 24
Peak memory 217500 kb
Host smart-8b3236d5-4ad4-4c13-8547-fdb0c53ee575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431301046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3431301046
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.3456513558
Short name T294
Test name
Test status
Simulation time 299787019 ps
CPU time 3.45 seconds
Started Feb 29 01:41:59 PM PST 24
Finished Feb 29 01:42:02 PM PST 24
Peak memory 216316 kb
Host smart-86dca116-d8e6-46d9-87a7-a62a206a741a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456513558 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3456513558
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.4093296501
Short name T300
Test name
Test status
Simulation time 86284853 ps
CPU time 1.13 seconds
Started Feb 29 01:41:59 PM PST 24
Finished Feb 29 01:42:00 PM PST 24
Peak memory 215992 kb
Host smart-43b88ae5-c06c-49ab-be21-07b9afebe3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093296501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.4093296501
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.2019950628
Short name T322
Test name
Test status
Simulation time 156806392 ps
CPU time 1.07 seconds
Started Feb 29 01:42:00 PM PST 24
Finished Feb 29 01:42:01 PM PST 24
Peak memory 216116 kb
Host smart-8d95a85c-46cc-4e81-abea-a930c90d1d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019950628 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2019950628
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.3851602470
Short name T715
Test name
Test status
Simulation time 161904483 ps
CPU time 1.33 seconds
Started Feb 29 01:42:02 PM PST 24
Finished Feb 29 01:42:04 PM PST 24
Peak memory 217616 kb
Host smart-fab2bb5f-4835-4a7b-ada5-3a5f44404d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851602470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3851602470
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.1352714736
Short name T678
Test name
Test status
Simulation time 114470032 ps
CPU time 2.99 seconds
Started Feb 29 01:42:01 PM PST 24
Finished Feb 29 01:42:04 PM PST 24
Peak memory 217892 kb
Host smart-dd6031e4-92b2-436f-ab18-398693838d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352714736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1352714736
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.3070971167
Short name T689
Test name
Test status
Simulation time 63851960 ps
CPU time 1.34 seconds
Started Feb 29 01:42:03 PM PST 24
Finished Feb 29 01:42:04 PM PST 24
Peak memory 217160 kb
Host smart-41ce8467-ae02-4f03-852d-c5c43ccd6b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070971167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3070971167
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.657570510
Short name T334
Test name
Test status
Simulation time 50370096 ps
CPU time 1.1 seconds
Started Feb 29 01:42:07 PM PST 24
Finished Feb 29 01:42:08 PM PST 24
Peak memory 215896 kb
Host smart-7ef116ae-4a1a-40e2-99fb-0b31d7246ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657570510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.657570510
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.1126636146
Short name T235
Test name
Test status
Simulation time 60672067 ps
CPU time 1.31 seconds
Started Feb 29 01:40:27 PM PST 24
Finished Feb 29 01:40:29 PM PST 24
Peak memory 215016 kb
Host smart-ec391df6-c7a2-4997-99fa-c7a74828e052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126636146 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1126636146
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.2627038986
Short name T472
Test name
Test status
Simulation time 41228556 ps
CPU time 0.94 seconds
Started Feb 29 01:40:32 PM PST 24
Finished Feb 29 01:40:33 PM PST 24
Peak memory 206240 kb
Host smart-7cd2c378-123f-4130-bbf1-ba1f7f6ab92a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627038986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2627038986
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.2187242675
Short name T150
Test name
Test status
Simulation time 11712168 ps
CPU time 0.87 seconds
Started Feb 29 01:40:34 PM PST 24
Finished Feb 29 01:40:35 PM PST 24
Peak memory 215144 kb
Host smart-220514fc-9157-4107-b2f6-226c4b0d4b23
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187242675 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2187242675
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.3291852810
Short name T449
Test name
Test status
Simulation time 41142398 ps
CPU time 1.07 seconds
Started Feb 29 01:40:30 PM PST 24
Finished Feb 29 01:40:31 PM PST 24
Peak memory 216964 kb
Host smart-a508d772-36a7-4cfa-b79d-630aaccff060
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291852810 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.3291852810
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.3664105785
Short name T146
Test name
Test status
Simulation time 32596442 ps
CPU time 0.91 seconds
Started Feb 29 01:40:32 PM PST 24
Finished Feb 29 01:40:33 PM PST 24
Peak memory 217332 kb
Host smart-606111fd-c778-4a78-a02d-955cd119a7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664105785 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3664105785
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_intr.3094989230
Short name T154
Test name
Test status
Simulation time 46711997 ps
CPU time 0.84 seconds
Started Feb 29 01:40:29 PM PST 24
Finished Feb 29 01:40:30 PM PST 24
Peak memory 214996 kb
Host smart-1c3baf4a-da2c-4ffb-a5f1-bedc71668c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094989230 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3094989230
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.381542194
Short name T752
Test name
Test status
Simulation time 17039309 ps
CPU time 1.08 seconds
Started Feb 29 01:40:28 PM PST 24
Finished Feb 29 01:40:29 PM PST 24
Peak memory 214784 kb
Host smart-244d906e-2ab8-4e6a-9569-540c9d9a95db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381542194 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.381542194
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1428625242
Short name T197
Test name
Test status
Simulation time 330138345 ps
CPU time 4.16 seconds
Started Feb 29 01:40:30 PM PST 24
Finished Feb 29 01:40:34 PM PST 24
Peak memory 214732 kb
Host smart-f767fc10-4714-44b0-96db-850f600f5aeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428625242 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1428625242
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3745170940
Short name T436
Test name
Test status
Simulation time 56648163560 ps
CPU time 1326.68 seconds
Started Feb 29 01:40:31 PM PST 24
Finished Feb 29 02:02:38 PM PST 24
Peak memory 220896 kb
Host smart-6b63fb79-18d9-40d4-bc2a-7d2444791de2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745170940 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3745170940
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.1197794523
Short name T486
Test name
Test status
Simulation time 63502061 ps
CPU time 1.24 seconds
Started Feb 29 01:42:07 PM PST 24
Finished Feb 29 01:42:08 PM PST 24
Peak memory 217692 kb
Host smart-e7d84299-a3fd-4f27-a95e-dc841875f1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197794523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.1197794523
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.3064632800
Short name T441
Test name
Test status
Simulation time 579590389 ps
CPU time 6.11 seconds
Started Feb 29 01:42:02 PM PST 24
Finished Feb 29 01:42:08 PM PST 24
Peak memory 219120 kb
Host smart-8d6c470f-e002-47ee-8932-3001d1e26fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064632800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.3064632800
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.719884410
Short name T639
Test name
Test status
Simulation time 51163192 ps
CPU time 1.56 seconds
Started Feb 29 01:42:00 PM PST 24
Finished Feb 29 01:42:02 PM PST 24
Peak memory 217316 kb
Host smart-5ac10d2f-ac6a-4262-be64-bf50420db720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719884410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.719884410
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.2357762067
Short name T505
Test name
Test status
Simulation time 57964531 ps
CPU time 1.47 seconds
Started Feb 29 01:42:04 PM PST 24
Finished Feb 29 01:42:05 PM PST 24
Peak memory 218272 kb
Host smart-2e721c2a-fed6-49e7-93c5-7b2585117284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357762067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2357762067
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.2961399559
Short name T292
Test name
Test status
Simulation time 144575763 ps
CPU time 2.25 seconds
Started Feb 29 01:42:03 PM PST 24
Finished Feb 29 01:42:06 PM PST 24
Peak memory 216280 kb
Host smart-632e380a-3455-436c-b22b-61c9b8bfb8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961399559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.2961399559
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.2126783808
Short name T652
Test name
Test status
Simulation time 96071095 ps
CPU time 1.43 seconds
Started Feb 29 01:42:02 PM PST 24
Finished Feb 29 01:42:03 PM PST 24
Peak memory 217236 kb
Host smart-d7b40db4-3e98-43f6-8627-2625cfae7dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126783808 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2126783808
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.259795688
Short name T270
Test name
Test status
Simulation time 49788077 ps
CPU time 1.22 seconds
Started Feb 29 01:42:03 PM PST 24
Finished Feb 29 01:42:04 PM PST 24
Peak memory 217240 kb
Host smart-e9d7c738-684e-4354-adba-5f18001823ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259795688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.259795688
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.2765147154
Short name T724
Test name
Test status
Simulation time 33194833 ps
CPU time 1.24 seconds
Started Feb 29 01:42:01 PM PST 24
Finished Feb 29 01:42:02 PM PST 24
Peak memory 217296 kb
Host smart-9155d754-43f0-447d-8004-fa8cc275dfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765147154 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2765147154
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.1201764749
Short name T564
Test name
Test status
Simulation time 72153560 ps
CPU time 1.18 seconds
Started Feb 29 01:42:02 PM PST 24
Finished Feb 29 01:42:03 PM PST 24
Peak memory 216132 kb
Host smart-a9a5ed97-8419-475d-b146-1865b3222b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201764749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1201764749
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3343625483
Short name T265
Test name
Test status
Simulation time 46846245 ps
CPU time 1.23 seconds
Started Feb 29 01:40:30 PM PST 24
Finished Feb 29 01:40:31 PM PST 24
Peak memory 215084 kb
Host smart-44de9324-27c6-49f4-ab6c-64f93d4c1db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343625483 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3343625483
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.1922730653
Short name T328
Test name
Test status
Simulation time 50198862 ps
CPU time 0.88 seconds
Started Feb 29 01:40:27 PM PST 24
Finished Feb 29 01:40:28 PM PST 24
Peak memory 206216 kb
Host smart-c84783be-5939-469e-943e-fd88b60bcba9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922730653 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.1922730653
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3625345416
Short name T386
Test name
Test status
Simulation time 14046032 ps
CPU time 0.89 seconds
Started Feb 29 01:40:30 PM PST 24
Finished Feb 29 01:40:32 PM PST 24
Peak memory 215176 kb
Host smart-95865a99-8d0c-4d0c-96c0-1473676bf9a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625345416 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3625345416
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.2231426179
Short name T96
Test name
Test status
Simulation time 19585783 ps
CPU time 1.16 seconds
Started Feb 29 01:40:34 PM PST 24
Finished Feb 29 01:40:35 PM PST 24
Peak memory 222396 kb
Host smart-86640c0c-0372-4373-af9e-6cd06f078727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231426179 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.2231426179
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2804821587
Short name T640
Test name
Test status
Simulation time 110971081 ps
CPU time 1.74 seconds
Started Feb 29 01:40:33 PM PST 24
Finished Feb 29 01:40:35 PM PST 24
Peak memory 218856 kb
Host smart-62c7e51f-b940-4d31-8a99-6b51c8cf03d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804821587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2804821587
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1698257795
Short name T4
Test name
Test status
Simulation time 22565134 ps
CPU time 1.11 seconds
Started Feb 29 01:40:29 PM PST 24
Finished Feb 29 01:40:30 PM PST 24
Peak memory 222564 kb
Host smart-dd527094-4197-4ce9-b7a1-233b78072a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698257795 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1698257795
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2842278533
Short name T649
Test name
Test status
Simulation time 26074890 ps
CPU time 0.93 seconds
Started Feb 29 01:40:29 PM PST 24
Finished Feb 29 01:40:30 PM PST 24
Peak memory 214720 kb
Host smart-b802d7d6-4ee3-4a4a-b07b-0fa979e5cbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842278533 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2842278533
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.1903239154
Short name T751
Test name
Test status
Simulation time 84229964 ps
CPU time 1.37 seconds
Started Feb 29 01:40:31 PM PST 24
Finished Feb 29 01:40:32 PM PST 24
Peak memory 215680 kb
Host smart-5465912a-e1a9-4b2c-8d55-ded7b10dab62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903239154 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.1903239154
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.2600524709
Short name T375
Test name
Test status
Simulation time 232795466060 ps
CPU time 740.35 seconds
Started Feb 29 01:40:30 PM PST 24
Finished Feb 29 01:52:50 PM PST 24
Peak memory 218972 kb
Host smart-9f531fa3-44cc-4b6c-b093-99c039cf4245
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600524709 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.2600524709
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.edn_genbits.1259024634
Short name T352
Test name
Test status
Simulation time 39839195 ps
CPU time 1.26 seconds
Started Feb 29 01:42:02 PM PST 24
Finished Feb 29 01:42:04 PM PST 24
Peak memory 217212 kb
Host smart-c3002067-fa2b-4404-a196-9574b66532b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259024634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1259024634
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.3327591672
Short name T669
Test name
Test status
Simulation time 31280376 ps
CPU time 1.33 seconds
Started Feb 29 01:42:03 PM PST 24
Finished Feb 29 01:42:05 PM PST 24
Peak memory 216136 kb
Host smart-7f3b5668-0267-4a5c-9c05-26dfd3685269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327591672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3327591672
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.1297149067
Short name T469
Test name
Test status
Simulation time 34829649 ps
CPU time 1.2 seconds
Started Feb 29 01:42:03 PM PST 24
Finished Feb 29 01:42:04 PM PST 24
Peak memory 217316 kb
Host smart-b97f512e-3ed2-47aa-9de0-db61bfe4c993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297149067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.1297149067
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.12402630
Short name T474
Test name
Test status
Simulation time 112847345 ps
CPU time 1.95 seconds
Started Feb 29 01:42:03 PM PST 24
Finished Feb 29 01:42:05 PM PST 24
Peak memory 217812 kb
Host smart-5681d215-0e34-4a1e-8292-c8b45cd4b988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12402630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.12402630
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.2588443268
Short name T667
Test name
Test status
Simulation time 41114963 ps
CPU time 1.39 seconds
Started Feb 29 01:42:10 PM PST 24
Finished Feb 29 01:42:12 PM PST 24
Peak memory 217244 kb
Host smart-bddf002f-af96-4310-8d3f-502975908e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588443268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2588443268
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.1484996107
Short name T699
Test name
Test status
Simulation time 37026046 ps
CPU time 1.59 seconds
Started Feb 29 01:42:01 PM PST 24
Finished Feb 29 01:42:03 PM PST 24
Peak memory 216172 kb
Host smart-d9c60cd8-03f8-4a6d-bbed-592876a32dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484996107 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1484996107
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.2816369233
Short name T495
Test name
Test status
Simulation time 70320329 ps
CPU time 2.91 seconds
Started Feb 29 01:42:07 PM PST 24
Finished Feb 29 01:42:10 PM PST 24
Peak memory 218896 kb
Host smart-7a278d41-ee6c-4607-8776-1b11ee47fc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816369233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2816369233
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.1294350096
Short name T723
Test name
Test status
Simulation time 63882998 ps
CPU time 1.11 seconds
Started Feb 29 01:42:09 PM PST 24
Finished Feb 29 01:42:11 PM PST 24
Peak memory 215896 kb
Host smart-478dfce8-9fdf-4cb1-9adc-a1763be7d7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294350096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1294350096
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.1371976567
Short name T275
Test name
Test status
Simulation time 59309520 ps
CPU time 1.53 seconds
Started Feb 29 01:42:05 PM PST 24
Finished Feb 29 01:42:07 PM PST 24
Peak memory 217204 kb
Host smart-dbcd4857-5db0-4b96-9dac-f194cf58e169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371976567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.1371976567
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.2332555745
Short name T100
Test name
Test status
Simulation time 74544671 ps
CPU time 1.24 seconds
Started Feb 29 01:40:30 PM PST 24
Finished Feb 29 01:40:31 PM PST 24
Peak memory 215068 kb
Host smart-f771da58-7955-4610-a7cc-bc0cea9fba0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332555745 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2332555745
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_disable.1246491156
Short name T104
Test name
Test status
Simulation time 14603021 ps
CPU time 0.92 seconds
Started Feb 29 01:40:42 PM PST 24
Finished Feb 29 01:40:43 PM PST 24
Peak memory 215332 kb
Host smart-8f899f75-8419-43cd-bd2c-466e3fd8a30d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246491156 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1246491156
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_err.3049600604
Short name T60
Test name
Test status
Simulation time 94228838 ps
CPU time 0.97 seconds
Started Feb 29 01:40:40 PM PST 24
Finished Feb 29 01:40:41 PM PST 24
Peak memory 218540 kb
Host smart-ab34b772-cd56-426a-a550-17524d699117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049600604 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.3049600604
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.528606476
Short name T323
Test name
Test status
Simulation time 51874127 ps
CPU time 1.43 seconds
Started Feb 29 01:40:30 PM PST 24
Finished Feb 29 01:40:31 PM PST 24
Peak memory 217556 kb
Host smart-9acd9587-9e74-4cc5-821a-f9c06c19c8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528606476 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.528606476
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_smoke.1034865522
Short name T571
Test name
Test status
Simulation time 40318251 ps
CPU time 0.88 seconds
Started Feb 29 01:40:28 PM PST 24
Finished Feb 29 01:40:29 PM PST 24
Peak memory 214708 kb
Host smart-d978c669-462e-49cf-a928-ffce97f12b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034865522 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.1034865522
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.249896577
Short name T327
Test name
Test status
Simulation time 97690769 ps
CPU time 2.36 seconds
Started Feb 29 01:40:30 PM PST 24
Finished Feb 29 01:40:32 PM PST 24
Peak memory 216024 kb
Host smart-63f64fc1-4dfb-4007-9623-2f9898ed7a99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249896577 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.249896577
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.2653585079
Short name T500
Test name
Test status
Simulation time 15469712766 ps
CPU time 270.84 seconds
Started Feb 29 01:40:33 PM PST 24
Finished Feb 29 01:45:04 PM PST 24
Peak memory 222160 kb
Host smart-98d74246-9f2f-48b4-9ab3-46a99b8051b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653585079 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.2653585079
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.1318293969
Short name T355
Test name
Test status
Simulation time 139082677 ps
CPU time 1.43 seconds
Started Feb 29 01:42:06 PM PST 24
Finished Feb 29 01:42:08 PM PST 24
Peak memory 215928 kb
Host smart-a400a499-78d0-4d5c-bccc-a1f55d7c4274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318293969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1318293969
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.3176350502
Short name T206
Test name
Test status
Simulation time 44182600 ps
CPU time 2.03 seconds
Started Feb 29 01:42:05 PM PST 24
Finished Feb 29 01:42:07 PM PST 24
Peak memory 217164 kb
Host smart-5dbbcf54-5cd1-42db-999b-d0caff9a672a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176350502 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3176350502
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.125708991
Short name T433
Test name
Test status
Simulation time 170451820 ps
CPU time 1.15 seconds
Started Feb 29 01:42:04 PM PST 24
Finished Feb 29 01:42:05 PM PST 24
Peak memory 216000 kb
Host smart-5428b43d-6303-4d2e-b46a-6bbe2f7f9769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125708991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.125708991
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.2659634760
Short name T447
Test name
Test status
Simulation time 160499502 ps
CPU time 1.15 seconds
Started Feb 29 01:42:05 PM PST 24
Finished Feb 29 01:42:07 PM PST 24
Peak memory 216084 kb
Host smart-0f34c4d5-547e-4b16-a016-5e011b90f959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659634760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2659634760
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.1352768390
Short name T791
Test name
Test status
Simulation time 37741080 ps
CPU time 1.39 seconds
Started Feb 29 01:41:58 PM PST 24
Finished Feb 29 01:41:59 PM PST 24
Peak memory 217196 kb
Host smart-31e46c20-454b-490e-aff3-c2a461b7d894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352768390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.1352768390
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.4139123555
Short name T512
Test name
Test status
Simulation time 107163008 ps
CPU time 1.2 seconds
Started Feb 29 01:42:02 PM PST 24
Finished Feb 29 01:42:04 PM PST 24
Peak memory 216964 kb
Host smart-fb055ee6-d2a6-4d10-939e-b01da7d3eff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139123555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.4139123555
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.2252511267
Short name T330
Test name
Test status
Simulation time 51516706 ps
CPU time 1.22 seconds
Started Feb 29 01:41:58 PM PST 24
Finished Feb 29 01:41:59 PM PST 24
Peak memory 217444 kb
Host smart-bc39f39d-ebd5-4bb5-b35d-20b47e653ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252511267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2252511267
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.1930685236
Short name T184
Test name
Test status
Simulation time 49834393 ps
CPU time 1.6 seconds
Started Feb 29 01:41:58 PM PST 24
Finished Feb 29 01:42:00 PM PST 24
Peak memory 217164 kb
Host smart-8103f681-d4b7-4ffe-92f6-94f1eb06b673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930685236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1930685236
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.3438008592
Short name T598
Test name
Test status
Simulation time 50935508 ps
CPU time 1.32 seconds
Started Feb 29 01:42:03 PM PST 24
Finished Feb 29 01:42:04 PM PST 24
Peak memory 217192 kb
Host smart-8abb1965-0001-4342-aab1-8319ac39d8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438008592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3438008592
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.816206514
Short name T786
Test name
Test status
Simulation time 37032256 ps
CPU time 1.56 seconds
Started Feb 29 01:42:00 PM PST 24
Finished Feb 29 01:42:01 PM PST 24
Peak memory 217136 kb
Host smart-5e09d53a-67f2-41be-b5fa-4e14763a9e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816206514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.816206514
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert_test.65614649
Short name T34
Test name
Test status
Simulation time 75383932 ps
CPU time 0.86 seconds
Started Feb 29 01:40:44 PM PST 24
Finished Feb 29 01:40:45 PM PST 24
Peak memory 206252 kb
Host smart-e5829daa-ae95-4841-b0f4-f8b24c2c8568
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65614649 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.65614649
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable.3164636278
Short name T142
Test name
Test status
Simulation time 41206157 ps
CPU time 0.87 seconds
Started Feb 29 01:40:42 PM PST 24
Finished Feb 29 01:40:43 PM PST 24
Peak memory 215400 kb
Host smart-478b2ba0-3e84-410d-9acc-54bf7d018f31
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164636278 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3164636278
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/19.edn_err.3463368557
Short name T6
Test name
Test status
Simulation time 48097114 ps
CPU time 1 seconds
Started Feb 29 01:40:41 PM PST 24
Finished Feb 29 01:40:42 PM PST 24
Peak memory 218624 kb
Host smart-efca89e5-64fd-4d5b-805f-203a8f9d0ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463368557 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3463368557
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.1390845610
Short name T829
Test name
Test status
Simulation time 80254068 ps
CPU time 0.98 seconds
Started Feb 29 01:40:42 PM PST 24
Finished Feb 29 01:40:43 PM PST 24
Peak memory 215900 kb
Host smart-3d4a06ea-d05e-4dd5-81fb-866e330b61df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390845610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.1390845610
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3956022891
Short name T628
Test name
Test status
Simulation time 38116519 ps
CPU time 0.9 seconds
Started Feb 29 01:40:43 PM PST 24
Finished Feb 29 01:40:44 PM PST 24
Peak memory 215172 kb
Host smart-d5cbb98b-9d60-48b4-b229-d1f22321d701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956022891 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3956022891
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.1103885677
Short name T660
Test name
Test status
Simulation time 42660671 ps
CPU time 0.91 seconds
Started Feb 29 01:40:41 PM PST 24
Finished Feb 29 01:40:42 PM PST 24
Peak memory 214780 kb
Host smart-0612f50a-5a45-4765-9396-bd9e5f5442db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103885677 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.1103885677
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2573985888
Short name T496
Test name
Test status
Simulation time 60599152743 ps
CPU time 344.41 seconds
Started Feb 29 01:40:41 PM PST 24
Finished Feb 29 01:46:25 PM PST 24
Peak memory 217988 kb
Host smart-298c8e20-da87-4b0c-afe6-23b6303c1947
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573985888 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2573985888
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.2634970748
Short name T259
Test name
Test status
Simulation time 52016224 ps
CPU time 1.27 seconds
Started Feb 29 01:41:59 PM PST 24
Finished Feb 29 01:42:01 PM PST 24
Peak memory 217576 kb
Host smart-4a3a509d-9edc-4756-9d7e-60185b95ad4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634970748 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2634970748
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.1513162537
Short name T692
Test name
Test status
Simulation time 28408980 ps
CPU time 1.39 seconds
Started Feb 29 01:42:02 PM PST 24
Finished Feb 29 01:42:03 PM PST 24
Peak memory 216280 kb
Host smart-78fc592e-cc97-477e-8778-d0b27345e9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513162537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1513162537
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.3782628630
Short name T430
Test name
Test status
Simulation time 57014716 ps
CPU time 1.25 seconds
Started Feb 29 01:41:58 PM PST 24
Finished Feb 29 01:41:59 PM PST 24
Peak memory 218588 kb
Host smart-9360570c-303f-4ae9-ba99-755a8b5b8798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782628630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3782628630
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.92033569
Short name T427
Test name
Test status
Simulation time 211027119 ps
CPU time 1.11 seconds
Started Feb 29 01:42:10 PM PST 24
Finished Feb 29 01:42:11 PM PST 24
Peak memory 216084 kb
Host smart-29b476ea-c569-48cc-82c9-3cc2b347a76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92033569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.92033569
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.1115021204
Short name T596
Test name
Test status
Simulation time 45107723 ps
CPU time 1.2 seconds
Started Feb 29 01:42:15 PM PST 24
Finished Feb 29 01:42:16 PM PST 24
Peak memory 217360 kb
Host smart-13b5d482-8f2b-468a-bb55-741fdd9be3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115021204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.1115021204
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.2496803032
Short name T360
Test name
Test status
Simulation time 23778899 ps
CPU time 1.18 seconds
Started Feb 29 01:42:12 PM PST 24
Finished Feb 29 01:42:13 PM PST 24
Peak memory 216048 kb
Host smart-067943fe-4f6d-4a77-bf78-e397f394b7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496803032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2496803032
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.4257972754
Short name T523
Test name
Test status
Simulation time 44755842 ps
CPU time 1.06 seconds
Started Feb 29 01:42:18 PM PST 24
Finished Feb 29 01:42:19 PM PST 24
Peak memory 216016 kb
Host smart-677c23e8-2324-4a54-87d4-2887a1ba8fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257972754 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.4257972754
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.2377635769
Short name T722
Test name
Test status
Simulation time 33134104 ps
CPU time 1.35 seconds
Started Feb 29 01:42:15 PM PST 24
Finished Feb 29 01:42:16 PM PST 24
Peak memory 218204 kb
Host smart-d5887b50-d952-4757-b8e3-9074f8c3cba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377635769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2377635769
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.3565311945
Short name T329
Test name
Test status
Simulation time 303503060 ps
CPU time 1.21 seconds
Started Feb 29 01:42:13 PM PST 24
Finished Feb 29 01:42:15 PM PST 24
Peak memory 216220 kb
Host smart-97f5f54a-eb10-4087-b302-775e1e4636f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565311945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.3565311945
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.4198423626
Short name T527
Test name
Test status
Simulation time 86574467 ps
CPU time 1.82 seconds
Started Feb 29 01:42:17 PM PST 24
Finished Feb 29 01:42:19 PM PST 24
Peak memory 217340 kb
Host smart-8ce12e58-2138-4d2b-a907-ed63445a784b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198423626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.4198423626
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1690716486
Short name T163
Test name
Test status
Simulation time 85790703 ps
CPU time 1.13 seconds
Started Feb 29 01:39:55 PM PST 24
Finished Feb 29 01:39:56 PM PST 24
Peak memory 215076 kb
Host smart-a9905887-5592-4cb4-bab2-2adc80f888dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690716486 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1690716486
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.950198276
Short name T591
Test name
Test status
Simulation time 30505623 ps
CPU time 1.1 seconds
Started Feb 29 01:39:52 PM PST 24
Finished Feb 29 01:39:54 PM PST 24
Peak memory 206340 kb
Host smart-4af1dfa8-3e65-4bf4-9c5f-e79a6af63d9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950198276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.950198276
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_err.532963490
Short name T321
Test name
Test status
Simulation time 19074675 ps
CPU time 1.02 seconds
Started Feb 29 01:39:53 PM PST 24
Finished Feb 29 01:39:54 PM PST 24
Peak memory 217184 kb
Host smart-e0cdd117-288e-42f9-a8e5-457b53b1f238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532963490 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.532963490
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.501734401
Short name T712
Test name
Test status
Simulation time 66641472 ps
CPU time 1.12 seconds
Started Feb 29 01:39:50 PM PST 24
Finished Feb 29 01:39:52 PM PST 24
Peak memory 217344 kb
Host smart-21190f7e-5f37-449a-be53-f3869ae79637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501734401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.501734401
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3656185609
Short name T201
Test name
Test status
Simulation time 27901133 ps
CPU time 1.04 seconds
Started Feb 29 01:39:52 PM PST 24
Finished Feb 29 01:39:53 PM PST 24
Peak memory 222516 kb
Host smart-a12031a0-5116-4eb9-8b85-d4229c25d37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656185609 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3656185609
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_sec_cm.657522335
Short name T18
Test name
Test status
Simulation time 168719215 ps
CPU time 3.28 seconds
Started Feb 29 01:39:54 PM PST 24
Finished Feb 29 01:39:57 PM PST 24
Peak memory 235024 kb
Host smart-fc02b176-7c47-4686-bb0c-db80014f7457
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657522335 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.657522335
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.3461826103
Short name T236
Test name
Test status
Simulation time 62973246 ps
CPU time 0.96 seconds
Started Feb 29 01:39:49 PM PST 24
Finished Feb 29 01:39:51 PM PST 24
Peak memory 214696 kb
Host smart-04e27444-818a-46c7-9b0b-4f2de80fefff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461826103 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.3461826103
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1070540879
Short name T331
Test name
Test status
Simulation time 188572802 ps
CPU time 2.58 seconds
Started Feb 29 01:39:55 PM PST 24
Finished Feb 29 01:39:58 PM PST 24
Peak memory 214688 kb
Host smart-f7354639-e4a5-4f82-9d7c-c9771cc1dbbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070540879 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1070540879
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.1978452999
Short name T632
Test name
Test status
Simulation time 72162097151 ps
CPU time 1412.99 seconds
Started Feb 29 01:39:51 PM PST 24
Finished Feb 29 02:03:24 PM PST 24
Peak memory 223676 kb
Host smart-542be95e-c17c-4555-882c-edeb7b003219
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978452999 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.1978452999
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2005192104
Short name T780
Test name
Test status
Simulation time 53043968 ps
CPU time 1.14 seconds
Started Feb 29 01:40:40 PM PST 24
Finished Feb 29 01:40:41 PM PST 24
Peak memory 215064 kb
Host smart-4cc76b75-32fd-4179-ae3e-39a547bbc4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005192104 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2005192104
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3007094521
Short name T613
Test name
Test status
Simulation time 36432917 ps
CPU time 0.81 seconds
Started Feb 29 01:40:40 PM PST 24
Finished Feb 29 01:40:41 PM PST 24
Peak memory 205084 kb
Host smart-c75d18e4-674d-49bb-9721-bba0d2416d8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007094521 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3007094521
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_err.3406885458
Short name T141
Test name
Test status
Simulation time 59630931 ps
CPU time 1.1 seconds
Started Feb 29 01:40:39 PM PST 24
Finished Feb 29 01:40:41 PM PST 24
Peak memory 229176 kb
Host smart-88a30ab6-44bd-473d-8369-57d02d44fdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406885458 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3406885458
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3648282089
Short name T326
Test name
Test status
Simulation time 74172089 ps
CPU time 1.14 seconds
Started Feb 29 01:40:43 PM PST 24
Finished Feb 29 01:40:44 PM PST 24
Peak memory 219056 kb
Host smart-08744128-2d27-47b3-b833-0090b4b49aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648282089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3648282089
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_smoke.2217024640
Short name T666
Test name
Test status
Simulation time 17091096 ps
CPU time 0.96 seconds
Started Feb 29 01:40:44 PM PST 24
Finished Feb 29 01:40:45 PM PST 24
Peak memory 214748 kb
Host smart-a0f58658-4dd0-4136-a1d2-7b699e0db2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217024640 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2217024640
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.46209990
Short name T339
Test name
Test status
Simulation time 557420649 ps
CPU time 5.85 seconds
Started Feb 29 01:40:40 PM PST 24
Finished Feb 29 01:40:46 PM PST 24
Peak memory 214716 kb
Host smart-14264bd3-fa73-48eb-ab05-e2825962d154
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46209990 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.46209990
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.807086048
Short name T161
Test name
Test status
Simulation time 75090348659 ps
CPU time 500.09 seconds
Started Feb 29 01:40:39 PM PST 24
Finished Feb 29 01:48:59 PM PST 24
Peak memory 217956 kb
Host smart-644a100a-b55f-4c36-8167-08a5b7c9e9ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807086048 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.807086048
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.561944147
Short name T276
Test name
Test status
Simulation time 31494204 ps
CPU time 1.27 seconds
Started Feb 29 01:42:11 PM PST 24
Finished Feb 29 01:42:12 PM PST 24
Peak memory 216172 kb
Host smart-216b20e2-2c92-4f75-81bc-78cbe49f79db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561944147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.561944147
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.1353463285
Short name T498
Test name
Test status
Simulation time 43488348 ps
CPU time 1.19 seconds
Started Feb 29 01:42:18 PM PST 24
Finished Feb 29 01:42:19 PM PST 24
Peak memory 216088 kb
Host smart-6354d58e-0705-4f3f-96b5-5cd9c9792fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353463285 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.1353463285
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.78369573
Short name T531
Test name
Test status
Simulation time 41580972 ps
CPU time 1.36 seconds
Started Feb 29 01:42:11 PM PST 24
Finished Feb 29 01:42:13 PM PST 24
Peak memory 216964 kb
Host smart-168e72b2-af84-444a-af05-378dcebbefef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78369573 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.78369573
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.4142078165
Short name T314
Test name
Test status
Simulation time 82183868 ps
CPU time 1.35 seconds
Started Feb 29 01:42:12 PM PST 24
Finished Feb 29 01:42:13 PM PST 24
Peak memory 217296 kb
Host smart-c1fa334d-9a29-45be-98bf-040476a3d797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142078165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.4142078165
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2899569551
Short name T725
Test name
Test status
Simulation time 62662371 ps
CPU time 1.46 seconds
Started Feb 29 01:42:18 PM PST 24
Finished Feb 29 01:42:19 PM PST 24
Peak memory 217092 kb
Host smart-b5bd184a-2d70-4cf7-9f19-3a7364a0d119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899569551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2899569551
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1496952163
Short name T238
Test name
Test status
Simulation time 54816461 ps
CPU time 1.93 seconds
Started Feb 29 01:42:10 PM PST 24
Finished Feb 29 01:42:12 PM PST 24
Peak memory 217000 kb
Host smart-d0e3363a-12ca-4a9a-a949-ae23a7ade005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496952163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1496952163
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1105412361
Short name T532
Test name
Test status
Simulation time 88192625 ps
CPU time 1.27 seconds
Started Feb 29 01:42:13 PM PST 24
Finished Feb 29 01:42:14 PM PST 24
Peak memory 216036 kb
Host smart-18eefe36-2bf6-436f-ac25-51f0622c5c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105412361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1105412361
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.2714767856
Short name T597
Test name
Test status
Simulation time 29325110 ps
CPU time 1.21 seconds
Started Feb 29 01:42:18 PM PST 24
Finished Feb 29 01:42:20 PM PST 24
Peak memory 217324 kb
Host smart-747e00e3-c1b2-41f1-97b0-8f8f81f8068a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714767856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.2714767856
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1060631629
Short name T653
Test name
Test status
Simulation time 51035735 ps
CPU time 1.2 seconds
Started Feb 29 01:42:09 PM PST 24
Finished Feb 29 01:42:10 PM PST 24
Peak memory 217504 kb
Host smart-7a9a65d9-c018-42d2-9aed-f21ae6e586c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060631629 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1060631629
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.335691111
Short name T557
Test name
Test status
Simulation time 156907907 ps
CPU time 1.84 seconds
Started Feb 29 01:42:13 PM PST 24
Finished Feb 29 01:42:15 PM PST 24
Peak memory 217496 kb
Host smart-278629da-3ccc-402e-8fb5-fbbae282bf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335691111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.335691111
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.1259045804
Short name T611
Test name
Test status
Simulation time 76840242 ps
CPU time 1.17 seconds
Started Feb 29 01:40:40 PM PST 24
Finished Feb 29 01:40:41 PM PST 24
Peak memory 215080 kb
Host smart-b4adbbe4-cd7b-4a5e-bac1-a7d86467da36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259045804 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1259045804
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.1222531763
Short name T476
Test name
Test status
Simulation time 16567215 ps
CPU time 0.92 seconds
Started Feb 29 01:40:41 PM PST 24
Finished Feb 29 01:40:42 PM PST 24
Peak memory 206108 kb
Host smart-6068c28d-b38e-4ac1-9bc0-e4eb3c7dc156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222531763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.1222531763
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.4281303981
Short name T151
Test name
Test status
Simulation time 14646383 ps
CPU time 0.93 seconds
Started Feb 29 01:40:43 PM PST 24
Finished Feb 29 01:40:44 PM PST 24
Peak memory 215332 kb
Host smart-bbb335d3-c8a4-4575-bb4f-f9ab667059da
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281303981 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.4281303981
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_err.3793832619
Short name T827
Test name
Test status
Simulation time 20046983 ps
CPU time 1 seconds
Started Feb 29 01:40:42 PM PST 24
Finished Feb 29 01:40:43 PM PST 24
Peak memory 217148 kb
Host smart-6b433a5b-fe6c-4ee1-9476-777246ba569e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793832619 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3793832619
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.1561154641
Short name T460
Test name
Test status
Simulation time 66512614 ps
CPU time 1.13 seconds
Started Feb 29 01:40:38 PM PST 24
Finished Feb 29 01:40:39 PM PST 24
Peak memory 215932 kb
Host smart-b968bb53-0ff4-4ad7-9113-4042326851e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561154641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1561154641
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.991480954
Short name T624
Test name
Test status
Simulation time 29090059 ps
CPU time 1.09 seconds
Started Feb 29 01:40:43 PM PST 24
Finished Feb 29 01:40:44 PM PST 24
Peak memory 222516 kb
Host smart-69c89384-7934-4809-ad98-65d7bf868f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991480954 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.991480954
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.2995575683
Short name T518
Test name
Test status
Simulation time 26365134 ps
CPU time 0.93 seconds
Started Feb 29 01:40:43 PM PST 24
Finished Feb 29 01:40:44 PM PST 24
Peak memory 214672 kb
Host smart-b347d543-4d6e-4223-ab65-e2fd7edec54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995575683 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.2995575683
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.4076030944
Short name T54
Test name
Test status
Simulation time 433412921 ps
CPU time 4.8 seconds
Started Feb 29 01:40:41 PM PST 24
Finished Feb 29 01:40:46 PM PST 24
Peak memory 215872 kb
Host smart-3086ba44-77bc-4d9c-9bd3-9f5883068ea5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076030944 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.4076030944
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.456729591
Short name T480
Test name
Test status
Simulation time 117918480668 ps
CPU time 495.37 seconds
Started Feb 29 01:40:43 PM PST 24
Finished Feb 29 01:48:58 PM PST 24
Peak memory 223180 kb
Host smart-6e40a002-e97a-4a16-b73e-d8e3c1540439
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456729591 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.456729591
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.4056014218
Short name T688
Test name
Test status
Simulation time 38149258 ps
CPU time 1.67 seconds
Started Feb 29 01:42:15 PM PST 24
Finished Feb 29 01:42:17 PM PST 24
Peak memory 215920 kb
Host smart-2d314ce8-f461-495c-9a2b-f29c279987d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056014218 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.4056014218
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.2254034480
Short name T823
Test name
Test status
Simulation time 52486748 ps
CPU time 1.32 seconds
Started Feb 29 01:42:17 PM PST 24
Finished Feb 29 01:42:18 PM PST 24
Peak memory 215932 kb
Host smart-78bd0a56-85e4-481e-aae6-b6469afbbf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254034480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.2254034480
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.515586421
Short name T439
Test name
Test status
Simulation time 48164551 ps
CPU time 1.11 seconds
Started Feb 29 01:42:18 PM PST 24
Finished Feb 29 01:42:19 PM PST 24
Peak memory 215916 kb
Host smart-6bbe0b73-4de7-4d6b-ac87-034793ed1445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515586421 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.515586421
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3821897423
Short name T11
Test name
Test status
Simulation time 387802615 ps
CPU time 1.36 seconds
Started Feb 29 01:42:17 PM PST 24
Finished Feb 29 01:42:18 PM PST 24
Peak memory 217744 kb
Host smart-41e85fc2-c175-4bb3-a0bc-60608f488aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821897423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3821897423
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.142190382
Short name T650
Test name
Test status
Simulation time 98073508 ps
CPU time 1.42 seconds
Started Feb 29 01:42:15 PM PST 24
Finished Feb 29 01:42:16 PM PST 24
Peak memory 217628 kb
Host smart-1e0b9aa8-38a4-49d6-abb2-01f34d4a4bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142190382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.142190382
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.544813620
Short name T117
Test name
Test status
Simulation time 46087949 ps
CPU time 1.21 seconds
Started Feb 29 01:42:11 PM PST 24
Finished Feb 29 01:42:13 PM PST 24
Peak memory 217308 kb
Host smart-fbf071d4-d319-4d47-a4e3-a5c440d5d406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544813620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.544813620
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.679722962
Short name T413
Test name
Test status
Simulation time 31669863 ps
CPU time 1.4 seconds
Started Feb 29 01:42:16 PM PST 24
Finished Feb 29 01:42:18 PM PST 24
Peak memory 217132 kb
Host smart-26c23c8f-f7c6-4d76-bedc-1aaba932c777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679722962 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.679722962
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.3893378267
Short name T239
Test name
Test status
Simulation time 43217648 ps
CPU time 1.61 seconds
Started Feb 29 01:42:13 PM PST 24
Finished Feb 29 01:42:14 PM PST 24
Peak memory 217300 kb
Host smart-8869492b-79da-470e-a425-f19ad4cbce6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893378267 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.3893378267
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.284231709
Short name T410
Test name
Test status
Simulation time 79253316 ps
CPU time 1.18 seconds
Started Feb 29 01:42:13 PM PST 24
Finished Feb 29 01:42:15 PM PST 24
Peak memory 218320 kb
Host smart-4fa4b029-c4b3-42f4-9c73-cd7ecc93e9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284231709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.284231709
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1103849886
Short name T269
Test name
Test status
Simulation time 51917238 ps
CPU time 1.29 seconds
Started Feb 29 01:40:43 PM PST 24
Finished Feb 29 01:40:44 PM PST 24
Peak memory 214996 kb
Host smart-ab85e0f1-864a-42c7-9444-244caf6bdfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103849886 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1103849886
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.3840518599
Short name T371
Test name
Test status
Simulation time 35759540 ps
CPU time 0.93 seconds
Started Feb 29 01:40:45 PM PST 24
Finished Feb 29 01:40:46 PM PST 24
Peak memory 206244 kb
Host smart-dcca9675-134b-46f9-8dfe-03cb08e7a32e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840518599 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.3840518599
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.1448734994
Short name T175
Test name
Test status
Simulation time 37560936 ps
CPU time 0.82 seconds
Started Feb 29 01:40:45 PM PST 24
Finished Feb 29 01:40:46 PM PST 24
Peak memory 214852 kb
Host smart-7089c397-cd7f-456f-9e36-5cff042037c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448734994 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.1448734994
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2110530579
Short name T733
Test name
Test status
Simulation time 67188634 ps
CPU time 1.19 seconds
Started Feb 29 01:40:44 PM PST 24
Finished Feb 29 01:40:46 PM PST 24
Peak memory 215792 kb
Host smart-2cf27421-d833-410b-af5a-b0d9d8cb004d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110530579 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2110530579
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.4127334336
Short name T70
Test name
Test status
Simulation time 20362033 ps
CPU time 1.19 seconds
Started Feb 29 01:40:42 PM PST 24
Finished Feb 29 01:40:43 PM PST 24
Peak memory 228996 kb
Host smart-3d50cdd3-6efa-45ed-8338-7916eb4854e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127334336 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.4127334336
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_intr.826896706
Short name T670
Test name
Test status
Simulation time 54784003 ps
CPU time 0.81 seconds
Started Feb 29 01:40:43 PM PST 24
Finished Feb 29 01:40:44 PM PST 24
Peak memory 214780 kb
Host smart-37d8fde4-d21f-409c-b050-5a7a1803e00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826896706 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.826896706
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.717646541
Short name T599
Test name
Test status
Simulation time 25406859 ps
CPU time 0.94 seconds
Started Feb 29 01:40:45 PM PST 24
Finished Feb 29 01:40:46 PM PST 24
Peak memory 214736 kb
Host smart-2b75bac4-d20a-4c57-9adb-68c7ddb1557a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717646541 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.717646541
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3199899315
Short name T766
Test name
Test status
Simulation time 912807678 ps
CPU time 1.52 seconds
Started Feb 29 01:40:42 PM PST 24
Finished Feb 29 01:40:44 PM PST 24
Peak memory 215672 kb
Host smart-916d1bb9-aff7-407c-82e9-1cd6e6404e93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199899315 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3199899315
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3806509524
Short name T354
Test name
Test status
Simulation time 219483614650 ps
CPU time 1462.56 seconds
Started Feb 29 01:40:42 PM PST 24
Finished Feb 29 02:05:04 PM PST 24
Peak memory 225516 kb
Host smart-2ffa538d-5271-4245-ab4e-a149ca0cc400
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806509524 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3806509524
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1050678868
Short name T672
Test name
Test status
Simulation time 122698872 ps
CPU time 1.69 seconds
Started Feb 29 01:42:18 PM PST 24
Finished Feb 29 01:42:20 PM PST 24
Peak memory 217480 kb
Host smart-5b7474e5-76b8-44d0-93da-0ad10827657d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050678868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1050678868
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3853772999
Short name T464
Test name
Test status
Simulation time 91405859 ps
CPU time 1.38 seconds
Started Feb 29 01:42:15 PM PST 24
Finished Feb 29 01:42:16 PM PST 24
Peak memory 217492 kb
Host smart-5b0ec3f2-67a2-4e19-bb5d-1322a9fae5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853772999 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3853772999
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.1502469183
Short name T736
Test name
Test status
Simulation time 40531183 ps
CPU time 1.6 seconds
Started Feb 29 01:42:14 PM PST 24
Finished Feb 29 01:42:15 PM PST 24
Peak memory 216216 kb
Host smart-f07f9328-7d41-4961-97cb-19d0f74b0958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502469183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.1502469183
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.82010773
Short name T757
Test name
Test status
Simulation time 112812696 ps
CPU time 1.21 seconds
Started Feb 29 01:42:15 PM PST 24
Finished Feb 29 01:42:16 PM PST 24
Peak memory 216388 kb
Host smart-79bcf6e8-2320-4b80-b620-240ed4ebb0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82010773 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.82010773
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2091260401
Short name T286
Test name
Test status
Simulation time 158604715 ps
CPU time 3.24 seconds
Started Feb 29 01:42:19 PM PST 24
Finished Feb 29 01:42:22 PM PST 24
Peak memory 218112 kb
Host smart-74c88cc1-3203-4764-b455-b2d20ddc6bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091260401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2091260401
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.3618964295
Short name T397
Test name
Test status
Simulation time 103128463 ps
CPU time 1 seconds
Started Feb 29 01:42:19 PM PST 24
Finished Feb 29 01:42:20 PM PST 24
Peak memory 216024 kb
Host smart-d1aad6d6-64c5-452f-bc70-eee34a3a4fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618964295 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.3618964295
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.725244182
Short name T343
Test name
Test status
Simulation time 98443529 ps
CPU time 1.27 seconds
Started Feb 29 01:42:18 PM PST 24
Finished Feb 29 01:42:20 PM PST 24
Peak memory 215872 kb
Host smart-a7dbddfa-1757-4464-ad3f-1947e5a3fe15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725244182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.725244182
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.37745849
Short name T717
Test name
Test status
Simulation time 72686546 ps
CPU time 2.44 seconds
Started Feb 29 01:42:14 PM PST 24
Finished Feb 29 01:42:17 PM PST 24
Peak memory 216232 kb
Host smart-85fc38ed-aba4-411f-a8ef-0bed5b06517c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37745849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.37745849
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1332360147
Short name T603
Test name
Test status
Simulation time 47453011 ps
CPU time 1.52 seconds
Started Feb 29 01:42:16 PM PST 24
Finished Feb 29 01:42:18 PM PST 24
Peak memory 217108 kb
Host smart-196e46b3-0f91-4a38-a58d-f75332404c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332360147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1332360147
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.2363732945
Short name T454
Test name
Test status
Simulation time 38774739 ps
CPU time 1.46 seconds
Started Feb 29 01:42:13 PM PST 24
Finished Feb 29 01:42:15 PM PST 24
Peak memory 218504 kb
Host smart-5a7c2441-69b7-47d5-8013-42fd1f79aa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363732945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.2363732945
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.2624879645
Short name T16
Test name
Test status
Simulation time 23351696 ps
CPU time 1.21 seconds
Started Feb 29 01:40:40 PM PST 24
Finished Feb 29 01:40:42 PM PST 24
Peak memory 215056 kb
Host smart-4b6333b4-4235-415c-815e-83a78e588a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624879645 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.2624879645
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2935105755
Short name T390
Test name
Test status
Simulation time 20701291 ps
CPU time 0.86 seconds
Started Feb 29 01:40:45 PM PST 24
Finished Feb 29 01:40:46 PM PST 24
Peak memory 205868 kb
Host smart-0ba23e60-1a8c-43dc-9d75-5fdb1b502639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935105755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2935105755
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1000956261
Short name T182
Test name
Test status
Simulation time 13648158 ps
CPU time 0.9 seconds
Started Feb 29 01:40:44 PM PST 24
Finished Feb 29 01:40:45 PM PST 24
Peak memory 215504 kb
Host smart-abf16e3d-338f-41a0-82e5-eaec7beee01e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000956261 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1000956261
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.4077750307
Short name T623
Test name
Test status
Simulation time 25444731 ps
CPU time 1.01 seconds
Started Feb 29 01:40:44 PM PST 24
Finished Feb 29 01:40:45 PM PST 24
Peak memory 216228 kb
Host smart-7d9f456e-0eb8-4b5c-9fe1-c2eb8f1f38d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077750307 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.4077750307
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3690192333
Short name T46
Test name
Test status
Simulation time 260437035 ps
CPU time 3.79 seconds
Started Feb 29 01:40:44 PM PST 24
Finished Feb 29 01:40:48 PM PST 24
Peak memory 216328 kb
Host smart-cbfba2bf-f5b0-409a-9296-ccdfcd6ff22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690192333 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3690192333
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3328750890
Short name T630
Test name
Test status
Simulation time 20554441 ps
CPU time 1.02 seconds
Started Feb 29 01:40:44 PM PST 24
Finished Feb 29 01:40:45 PM PST 24
Peak memory 215184 kb
Host smart-e0a3f692-5dda-419e-b4bf-209bcbcefb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328750890 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3328750890
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.1475760758
Short name T595
Test name
Test status
Simulation time 49016087 ps
CPU time 0.88 seconds
Started Feb 29 01:40:43 PM PST 24
Finished Feb 29 01:40:44 PM PST 24
Peak memory 214728 kb
Host smart-9b98148d-a561-49c7-83cf-a0bd78bff17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475760758 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.1475760758
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.755664430
Short name T576
Test name
Test status
Simulation time 116943810 ps
CPU time 1.29 seconds
Started Feb 29 01:40:43 PM PST 24
Finished Feb 29 01:40:45 PM PST 24
Peak memory 217136 kb
Host smart-1832c064-6186-4944-9468-903b3f7bb5a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755664430 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.755664430
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.4220674464
Short name T155
Test name
Test status
Simulation time 137144828177 ps
CPU time 781.12 seconds
Started Feb 29 01:40:43 PM PST 24
Finished Feb 29 01:53:44 PM PST 24
Peak memory 220200 kb
Host smart-6abf3a57-4e12-4d98-aa0c-4f3252b66708
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220674464 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.4220674464
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.4109447760
Short name T456
Test name
Test status
Simulation time 259402784 ps
CPU time 1.08 seconds
Started Feb 29 01:42:13 PM PST 24
Finished Feb 29 01:42:14 PM PST 24
Peak memory 215752 kb
Host smart-99f77201-3a9a-4244-9bf0-ca05e7ba1ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109447760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.4109447760
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2957836688
Short name T748
Test name
Test status
Simulation time 82473935 ps
CPU time 1.31 seconds
Started Feb 29 01:42:13 PM PST 24
Finished Feb 29 01:42:15 PM PST 24
Peak memory 217464 kb
Host smart-cbd0fb3f-7806-48e7-b68a-f9295e29c403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957836688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2957836688
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2233522943
Short name T408
Test name
Test status
Simulation time 60817321 ps
CPU time 1.32 seconds
Started Feb 29 01:42:11 PM PST 24
Finished Feb 29 01:42:13 PM PST 24
Peak memory 215972 kb
Host smart-b2dd2e3e-b71d-4541-b494-6e8b87d8c6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233522943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2233522943
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3578206272
Short name T475
Test name
Test status
Simulation time 46720902 ps
CPU time 1.46 seconds
Started Feb 29 01:42:13 PM PST 24
Finished Feb 29 01:42:14 PM PST 24
Peak memory 216984 kb
Host smart-88e1f46b-ddab-413e-a9ee-8078928cde0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578206272 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3578206272
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.172966627
Short name T516
Test name
Test status
Simulation time 42055005 ps
CPU time 1.46 seconds
Started Feb 29 01:42:17 PM PST 24
Finished Feb 29 01:42:19 PM PST 24
Peak memory 218576 kb
Host smart-fe45063f-9f37-4308-93d8-90b88088f648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172966627 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.172966627
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1955815385
Short name T398
Test name
Test status
Simulation time 185817561 ps
CPU time 2.55 seconds
Started Feb 29 01:42:17 PM PST 24
Finished Feb 29 01:42:19 PM PST 24
Peak memory 218960 kb
Host smart-d5e053b8-0a66-496c-9cc6-dcd4cb2aaf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955815385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1955815385
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3357289162
Short name T617
Test name
Test status
Simulation time 65630717 ps
CPU time 1.4 seconds
Started Feb 29 01:42:17 PM PST 24
Finished Feb 29 01:42:19 PM PST 24
Peak memory 217432 kb
Host smart-051f22d2-4ae9-4524-91cc-403ac67712ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357289162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3357289162
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.2035713102
Short name T31
Test name
Test status
Simulation time 28277646 ps
CPU time 1.43 seconds
Started Feb 29 01:42:17 PM PST 24
Finished Feb 29 01:42:18 PM PST 24
Peak memory 217268 kb
Host smart-41ceb362-ba4e-4822-8743-153a6b467a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035713102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.2035713102
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3190270980
Short name T682
Test name
Test status
Simulation time 97605599 ps
CPU time 1.19 seconds
Started Feb 29 01:42:14 PM PST 24
Finished Feb 29 01:42:15 PM PST 24
Peak memory 216100 kb
Host smart-d7732fb4-8ee7-4849-a7ea-346cd74b4a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190270980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3190270980
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.2950892899
Short name T393
Test name
Test status
Simulation time 269300972 ps
CPU time 1.15 seconds
Started Feb 29 01:42:18 PM PST 24
Finished Feb 29 01:42:19 PM PST 24
Peak memory 216196 kb
Host smart-7aef27e7-02ef-49c5-aa17-93e2b50f1e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950892899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.2950892899
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert_test.2780965357
Short name T528
Test name
Test status
Simulation time 90543202 ps
CPU time 0.98 seconds
Started Feb 29 01:40:45 PM PST 24
Finished Feb 29 01:40:46 PM PST 24
Peak memory 206236 kb
Host smart-2c1f5a7e-d05c-42eb-945c-a49dd4c35693
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780965357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2780965357
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.270660547
Short name T734
Test name
Test status
Simulation time 18297430 ps
CPU time 0.82 seconds
Started Feb 29 01:40:44 PM PST 24
Finished Feb 29 01:40:45 PM PST 24
Peak memory 215100 kb
Host smart-30797e18-39e6-402c-bd74-f59f55ac3852
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270660547 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.270660547
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.1375031392
Short name T801
Test name
Test status
Simulation time 41789282 ps
CPU time 1.22 seconds
Started Feb 29 01:40:56 PM PST 24
Finished Feb 29 01:40:58 PM PST 24
Peak memory 217332 kb
Host smart-89907149-2946-47a0-961c-f611905880ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375031392 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.1375031392
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.4234309080
Short name T55
Test name
Test status
Simulation time 18960782 ps
CPU time 1 seconds
Started Feb 29 01:40:39 PM PST 24
Finished Feb 29 01:40:40 PM PST 24
Peak memory 217396 kb
Host smart-485bfb61-ab5f-41a9-a7e6-2c32470f77cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234309080 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.4234309080
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.4003024875
Short name T585
Test name
Test status
Simulation time 58114750 ps
CPU time 1.43 seconds
Started Feb 29 01:40:48 PM PST 24
Finished Feb 29 01:40:49 PM PST 24
Peak memory 217400 kb
Host smart-fe372025-d6b2-40b5-b909-ef9cc9f8949c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003024875 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.4003024875
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.288742517
Short name T578
Test name
Test status
Simulation time 29686209 ps
CPU time 1.13 seconds
Started Feb 29 01:40:44 PM PST 24
Finished Feb 29 01:40:46 PM PST 24
Peak memory 222508 kb
Host smart-f6314761-cc46-472b-99e5-3c460cab81c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288742517 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.288742517
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.1386911380
Short name T420
Test name
Test status
Simulation time 18087122 ps
CPU time 1.01 seconds
Started Feb 29 01:40:43 PM PST 24
Finished Feb 29 01:40:44 PM PST 24
Peak memory 214736 kb
Host smart-01ea1733-6faa-476f-af9c-02c8bc72e333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386911380 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.1386911380
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3156437883
Short name T28
Test name
Test status
Simulation time 473976623 ps
CPU time 4.95 seconds
Started Feb 29 01:40:46 PM PST 24
Finished Feb 29 01:40:51 PM PST 24
Peak memory 214740 kb
Host smart-71cba106-161c-4791-8677-c59e0846f814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156437883 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3156437883
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1079397723
Short name T730
Test name
Test status
Simulation time 15794964973 ps
CPU time 356.55 seconds
Started Feb 29 01:40:43 PM PST 24
Finished Feb 29 01:46:40 PM PST 24
Peak memory 217600 kb
Host smart-76213c38-d453-4f1d-83f7-bbd7f3d657f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079397723 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1079397723
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2686188063
Short name T401
Test name
Test status
Simulation time 49084375 ps
CPU time 1.41 seconds
Started Feb 29 01:42:13 PM PST 24
Finished Feb 29 01:42:14 PM PST 24
Peak memory 216080 kb
Host smart-8ee40b40-7165-4a19-ae26-4e6a8a2013f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686188063 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2686188063
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.522684635
Short name T295
Test name
Test status
Simulation time 53027769 ps
CPU time 1.7 seconds
Started Feb 29 01:42:17 PM PST 24
Finished Feb 29 01:42:18 PM PST 24
Peak memory 217428 kb
Host smart-70f00766-4a26-4142-8b68-0803b6c110b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522684635 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.522684635
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.1079278153
Short name T174
Test name
Test status
Simulation time 31306078 ps
CPU time 1.31 seconds
Started Feb 29 01:42:13 PM PST 24
Finished Feb 29 01:42:14 PM PST 24
Peak memory 217412 kb
Host smart-3739b359-1543-447c-a974-458217ef38f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079278153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.1079278153
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1420288001
Short name T607
Test name
Test status
Simulation time 80204688 ps
CPU time 1.04 seconds
Started Feb 29 01:42:19 PM PST 24
Finished Feb 29 01:42:21 PM PST 24
Peak memory 216112 kb
Host smart-76cfe032-2db7-483a-b017-036ae15df9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420288001 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1420288001
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.3954886673
Short name T494
Test name
Test status
Simulation time 52741446 ps
CPU time 1.51 seconds
Started Feb 29 01:42:15 PM PST 24
Finished Feb 29 01:42:17 PM PST 24
Peak memory 216348 kb
Host smart-41097761-fbbe-4077-bdb2-2eec93172f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954886673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.3954886673
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2464513648
Short name T252
Test name
Test status
Simulation time 56878216 ps
CPU time 1.83 seconds
Started Feb 29 01:42:20 PM PST 24
Finished Feb 29 01:42:22 PM PST 24
Peak memory 217220 kb
Host smart-27b0df91-dc05-4bb0-a822-167c3524ead9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464513648 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2464513648
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1856032179
Short name T629
Test name
Test status
Simulation time 99062086 ps
CPU time 1.71 seconds
Started Feb 29 01:42:12 PM PST 24
Finished Feb 29 01:42:13 PM PST 24
Peak memory 217376 kb
Host smart-7940d3b5-1b0c-44c9-96cb-16574ed12740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856032179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1856032179
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.974047393
Short name T297
Test name
Test status
Simulation time 93086865 ps
CPU time 1.33 seconds
Started Feb 29 01:42:14 PM PST 24
Finished Feb 29 01:42:16 PM PST 24
Peak memory 217312 kb
Host smart-fa91f82a-56b1-41aa-9607-6bd0f35562ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974047393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.974047393
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.3046386321
Short name T763
Test name
Test status
Simulation time 51762154 ps
CPU time 1.44 seconds
Started Feb 29 01:42:12 PM PST 24
Finished Feb 29 01:42:14 PM PST 24
Peak memory 217380 kb
Host smart-0d7dc1ad-ce31-4b31-bee1-448c51e0922c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046386321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.3046386321
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.959115924
Short name T647
Test name
Test status
Simulation time 51933857 ps
CPU time 1.66 seconds
Started Feb 29 01:42:18 PM PST 24
Finished Feb 29 01:42:20 PM PST 24
Peak memory 217200 kb
Host smart-e5356968-41aa-4ed4-95b5-35e6868abb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959115924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.959115924
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.3723213181
Short name T59
Test name
Test status
Simulation time 89839886 ps
CPU time 1.28 seconds
Started Feb 29 01:40:46 PM PST 24
Finished Feb 29 01:40:47 PM PST 24
Peak memory 215048 kb
Host smart-79517449-e507-4212-9f12-ba2535b440e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723213181 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.3723213181
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.1760660307
Short name T35
Test name
Test status
Simulation time 54882311 ps
CPU time 0.88 seconds
Started Feb 29 01:40:41 PM PST 24
Finished Feb 29 01:40:42 PM PST 24
Peak memory 206228 kb
Host smart-070f0682-ac78-47f5-aed1-ce943114246c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760660307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.1760660307
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.3713255031
Short name T509
Test name
Test status
Simulation time 11141326 ps
CPU time 0.9 seconds
Started Feb 29 01:40:56 PM PST 24
Finished Feb 29 01:40:57 PM PST 24
Peak memory 214852 kb
Host smart-a42753b9-74c1-41b1-9615-01ec5295fdde
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713255031 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3713255031
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1860056654
Short name T62
Test name
Test status
Simulation time 214117335 ps
CPU time 1.14 seconds
Started Feb 29 01:40:41 PM PST 24
Finished Feb 29 01:40:42 PM PST 24
Peak memory 215756 kb
Host smart-facea76c-a4dc-4b6a-9523-fd58daa41a7e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860056654 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1860056654
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.613467356
Short name T588
Test name
Test status
Simulation time 71774412 ps
CPU time 1.07 seconds
Started Feb 29 01:40:43 PM PST 24
Finished Feb 29 01:40:44 PM PST 24
Peak memory 218328 kb
Host smart-edfb6f5c-419b-4d95-8ad8-9542e286dc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613467356 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.613467356
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3209509613
Short name T455
Test name
Test status
Simulation time 56162643 ps
CPU time 1.28 seconds
Started Feb 29 01:40:42 PM PST 24
Finished Feb 29 01:40:44 PM PST 24
Peak memory 217212 kb
Host smart-af4e39e5-d019-48db-8240-cea64223b350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209509613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3209509613
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.30075559
Short name T126
Test name
Test status
Simulation time 24510923 ps
CPU time 0.97 seconds
Started Feb 29 01:40:41 PM PST 24
Finished Feb 29 01:40:42 PM PST 24
Peak memory 215144 kb
Host smart-e7edd3c6-7421-473a-905b-ad95cbfedf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30075559 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.30075559
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2700942520
Short name T356
Test name
Test status
Simulation time 52787129 ps
CPU time 0.95 seconds
Started Feb 29 01:40:45 PM PST 24
Finished Feb 29 01:40:46 PM PST 24
Peak memory 214716 kb
Host smart-53590be4-307d-4a7f-a1f4-48292510fc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700942520 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2700942520
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2829189004
Short name T657
Test name
Test status
Simulation time 365960399 ps
CPU time 6.86 seconds
Started Feb 29 01:40:41 PM PST 24
Finished Feb 29 01:40:48 PM PST 24
Peak memory 214760 kb
Host smart-573ff52e-bd8a-42cb-a3f0-8dff9410dbf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829189004 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2829189004
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.1381779439
Short name T189
Test name
Test status
Simulation time 36136721361 ps
CPU time 489.07 seconds
Started Feb 29 01:40:46 PM PST 24
Finished Feb 29 01:48:55 PM PST 24
Peak memory 217660 kb
Host smart-78bd0493-902c-45d1-8b70-0f4a7d05a188
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381779439 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.1381779439
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2130561330
Short name T525
Test name
Test status
Simulation time 54972702 ps
CPU time 1.1 seconds
Started Feb 29 01:42:19 PM PST 24
Finished Feb 29 01:42:21 PM PST 24
Peak memory 217548 kb
Host smart-197e7cb8-0b17-46a1-ace5-7762f77e70cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130561330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2130561330
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.4016785956
Short name T637
Test name
Test status
Simulation time 48913813 ps
CPU time 1.52 seconds
Started Feb 29 01:42:17 PM PST 24
Finished Feb 29 01:42:18 PM PST 24
Peak memory 217248 kb
Host smart-0b80cb60-882d-4167-8940-99aa2f5aa290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016785956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.4016785956
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.2703637038
Short name T357
Test name
Test status
Simulation time 68548319 ps
CPU time 1.45 seconds
Started Feb 29 01:42:13 PM PST 24
Finished Feb 29 01:42:14 PM PST 24
Peak memory 217492 kb
Host smart-76b43c75-3784-44d7-bced-40f5939a3f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703637038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.2703637038
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.3047869783
Short name T708
Test name
Test status
Simulation time 84884123 ps
CPU time 1.16 seconds
Started Feb 29 01:42:20 PM PST 24
Finished Feb 29 01:42:21 PM PST 24
Peak memory 216048 kb
Host smart-343945a6-0dc1-4fc6-bb53-a1941f811188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047869783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.3047869783
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.80053413
Short name T450
Test name
Test status
Simulation time 96084381 ps
CPU time 1.4 seconds
Started Feb 29 01:42:10 PM PST 24
Finished Feb 29 01:42:11 PM PST 24
Peak memory 217636 kb
Host smart-55d2837a-2687-449b-a31b-d793757af3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80053413 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.80053413
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2994915553
Short name T685
Test name
Test status
Simulation time 62418964 ps
CPU time 1.07 seconds
Started Feb 29 01:42:10 PM PST 24
Finished Feb 29 01:42:11 PM PST 24
Peak memory 215904 kb
Host smart-a3ecfe83-16cc-450f-8c2e-e193e13a3cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994915553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2994915553
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3127710394
Short name T347
Test name
Test status
Simulation time 43522662 ps
CPU time 1.23 seconds
Started Feb 29 01:42:12 PM PST 24
Finished Feb 29 01:42:13 PM PST 24
Peak memory 214716 kb
Host smart-1140c82c-c827-4980-aa8d-3e3d712de6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127710394 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3127710394
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1676277601
Short name T341
Test name
Test status
Simulation time 45998121 ps
CPU time 1.67 seconds
Started Feb 29 01:42:11 PM PST 24
Finished Feb 29 01:42:13 PM PST 24
Peak memory 217340 kb
Host smart-9cc8b588-7013-45de-a96d-4e1521cc1600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676277601 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1676277601
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2498446563
Short name T590
Test name
Test status
Simulation time 59666762 ps
CPU time 1.91 seconds
Started Feb 29 01:42:19 PM PST 24
Finished Feb 29 01:42:21 PM PST 24
Peak memory 218392 kb
Host smart-8991420a-bff2-440a-8a34-3f5fd0f09885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498446563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2498446563
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1826593860
Short name T709
Test name
Test status
Simulation time 33847812 ps
CPU time 1.39 seconds
Started Feb 29 01:42:10 PM PST 24
Finished Feb 29 01:42:12 PM PST 24
Peak memory 218280 kb
Host smart-0cc9c60a-a8bf-4895-b892-4f0400511d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826593860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1826593860
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.3734722935
Short name T602
Test name
Test status
Simulation time 30653627 ps
CPU time 1.27 seconds
Started Feb 29 01:40:54 PM PST 24
Finished Feb 29 01:40:55 PM PST 24
Peak memory 215064 kb
Host smart-27a589c1-da7b-42af-8139-28ba9e328bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734722935 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.3734722935
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2329948380
Short name T473
Test name
Test status
Simulation time 14311806 ps
CPU time 0.84 seconds
Started Feb 29 01:40:49 PM PST 24
Finished Feb 29 01:40:50 PM PST 24
Peak memory 206220 kb
Host smart-70ffb525-e42f-4279-9318-4d3316ef2231
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329948380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2329948380
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2231658850
Short name T437
Test name
Test status
Simulation time 29395371 ps
CPU time 0.79 seconds
Started Feb 29 01:40:45 PM PST 24
Finished Feb 29 01:40:46 PM PST 24
Peak memory 214844 kb
Host smart-f5ab88ad-2b24-4236-94d7-49d74f695f4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231658850 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2231658850
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.2192800112
Short name T396
Test name
Test status
Simulation time 18912025 ps
CPU time 1.08 seconds
Started Feb 29 01:40:49 PM PST 24
Finished Feb 29 01:40:50 PM PST 24
Peak memory 217368 kb
Host smart-e5c5c2c0-e0f1-4958-9577-79859791f0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192800112 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2192800112
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.423360843
Short name T549
Test name
Test status
Simulation time 413509854 ps
CPU time 4.49 seconds
Started Feb 29 01:40:56 PM PST 24
Finished Feb 29 01:41:01 PM PST 24
Peak memory 214744 kb
Host smart-a89ed84f-1c01-4d80-9418-5a39c787d8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423360843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.423360843
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3356818896
Short name T727
Test name
Test status
Simulation time 45953170 ps
CPU time 0.94 seconds
Started Feb 29 01:40:54 PM PST 24
Finished Feb 29 01:40:55 PM PST 24
Peak memory 222448 kb
Host smart-7a729b3c-7289-4ace-ac9b-dab1483b0803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356818896 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3356818896
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.4051190492
Short name T405
Test name
Test status
Simulation time 26283455 ps
CPU time 0.98 seconds
Started Feb 29 01:40:45 PM PST 24
Finished Feb 29 01:40:46 PM PST 24
Peak memory 214716 kb
Host smart-3800bde7-5477-4554-942a-ff21bd81038c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051190492 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.4051190492
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1800586241
Short name T765
Test name
Test status
Simulation time 189707043 ps
CPU time 1.69 seconds
Started Feb 29 01:40:51 PM PST 24
Finished Feb 29 01:40:53 PM PST 24
Peak memory 214764 kb
Host smart-1af6306f-1dd3-424f-b0d1-d0afe277a624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800586241 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1800586241
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3466060894
Short name T190
Test name
Test status
Simulation time 49354381445 ps
CPU time 341.92 seconds
Started Feb 29 01:40:50 PM PST 24
Finished Feb 29 01:46:32 PM PST 24
Peak memory 217768 kb
Host smart-dcaf7271-6519-4575-aa8e-b41aa993679f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466060894 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3466060894
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.600514006
Short name T608
Test name
Test status
Simulation time 57171358 ps
CPU time 1.63 seconds
Started Feb 29 01:42:13 PM PST 24
Finished Feb 29 01:42:14 PM PST 24
Peak memory 217216 kb
Host smart-08d22129-d72a-4ed0-8a9e-f06272afd34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600514006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.600514006
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.15429271
Short name T274
Test name
Test status
Simulation time 94708232 ps
CPU time 1.1 seconds
Started Feb 29 01:42:13 PM PST 24
Finished Feb 29 01:42:14 PM PST 24
Peak memory 215848 kb
Host smart-de3cd857-70be-454a-9b5c-905fe7e09939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15429271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.15429271
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1840910176
Short name T645
Test name
Test status
Simulation time 37288430 ps
CPU time 1.55 seconds
Started Feb 29 01:42:11 PM PST 24
Finished Feb 29 01:42:13 PM PST 24
Peak memory 217160 kb
Host smart-76fc98d4-6950-4d29-bcb9-5cc63ffd54ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840910176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1840910176
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2598148133
Short name T445
Test name
Test status
Simulation time 59170896 ps
CPU time 1.71 seconds
Started Feb 29 01:42:15 PM PST 24
Finished Feb 29 01:42:16 PM PST 24
Peak memory 217080 kb
Host smart-e02906cd-3acb-4531-9a35-f1f3aea5ffe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598148133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2598148133
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2036696768
Short name T279
Test name
Test status
Simulation time 51789425 ps
CPU time 1.45 seconds
Started Feb 29 01:42:14 PM PST 24
Finished Feb 29 01:42:15 PM PST 24
Peak memory 217348 kb
Host smart-ae8751fd-f6c4-4be9-aaff-fec4eb9e0c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036696768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2036696768
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2092324838
Short name T29
Test name
Test status
Simulation time 267521224 ps
CPU time 3.78 seconds
Started Feb 29 01:42:18 PM PST 24
Finished Feb 29 01:42:22 PM PST 24
Peak memory 217612 kb
Host smart-4e46cebd-045f-4885-b66e-0195b72e550d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092324838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2092324838
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.4277820167
Short name T573
Test name
Test status
Simulation time 93203840 ps
CPU time 1.26 seconds
Started Feb 29 01:42:27 PM PST 24
Finished Feb 29 01:42:29 PM PST 24
Peak memory 216524 kb
Host smart-170e20da-e229-4039-b3fd-c6420ea9cd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277820167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.4277820167
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2711574887
Short name T664
Test name
Test status
Simulation time 114933435 ps
CPU time 1.53 seconds
Started Feb 29 01:42:26 PM PST 24
Finished Feb 29 01:42:28 PM PST 24
Peak memory 218288 kb
Host smart-27f58c3c-b7ce-46e5-8037-dac1e6c7f19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711574887 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2711574887
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2481238587
Short name T830
Test name
Test status
Simulation time 48203310 ps
CPU time 1.18 seconds
Started Feb 29 01:42:27 PM PST 24
Finished Feb 29 01:42:29 PM PST 24
Peak memory 214540 kb
Host smart-35119732-cbfb-440d-9fb8-518d4b1e74cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481238587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2481238587
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3734109158
Short name T568
Test name
Test status
Simulation time 116706498 ps
CPU time 1.55 seconds
Started Feb 29 01:42:25 PM PST 24
Finished Feb 29 01:42:27 PM PST 24
Peak memory 218884 kb
Host smart-ea5d868d-3f05-485e-b6c5-09d10595cb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734109158 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3734109158
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2420984291
Short name T772
Test name
Test status
Simulation time 28200861 ps
CPU time 1.23 seconds
Started Feb 29 01:40:48 PM PST 24
Finished Feb 29 01:40:50 PM PST 24
Peak memory 215072 kb
Host smart-f2e30cda-4bac-4f36-b838-1f72adcbb4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420984291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2420984291
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.2008385996
Short name T424
Test name
Test status
Simulation time 14137159 ps
CPU time 0.88 seconds
Started Feb 29 01:40:55 PM PST 24
Finished Feb 29 01:40:56 PM PST 24
Peak memory 205872 kb
Host smart-c197f765-8036-45cb-915d-84db5c9beac5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008385996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2008385996
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.962159659
Short name T65
Test name
Test status
Simulation time 37543376 ps
CPU time 1.04 seconds
Started Feb 29 01:40:56 PM PST 24
Finished Feb 29 01:40:58 PM PST 24
Peak memory 215708 kb
Host smart-a4ed5111-2627-4675-b0b0-4a90d04cbfdc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962159659 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.962159659
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.2515166716
Short name T365
Test name
Test status
Simulation time 34827786 ps
CPU time 0.84 seconds
Started Feb 29 01:40:49 PM PST 24
Finished Feb 29 01:40:50 PM PST 24
Peak memory 217156 kb
Host smart-450a6cb1-473a-4f10-853e-0f77b1e30a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515166716 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2515166716
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.4151835929
Short name T544
Test name
Test status
Simulation time 34469574 ps
CPU time 1.35 seconds
Started Feb 29 01:40:43 PM PST 24
Finished Feb 29 01:40:44 PM PST 24
Peak memory 215796 kb
Host smart-56efacfc-2d35-4565-be29-d7a23aa2f02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151835929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.4151835929
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.105993318
Short name T429
Test name
Test status
Simulation time 22882350 ps
CPU time 1.09 seconds
Started Feb 29 01:40:47 PM PST 24
Finished Feb 29 01:40:48 PM PST 24
Peak memory 214800 kb
Host smart-4a1f194b-87c0-46de-942e-10c75a9f50af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105993318 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.105993318
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.918367059
Short name T610
Test name
Test status
Simulation time 25079158 ps
CPU time 0.92 seconds
Started Feb 29 01:40:45 PM PST 24
Finished Feb 29 01:40:46 PM PST 24
Peak memory 214732 kb
Host smart-98e984a9-f66c-4c73-8eb8-8e5027df41a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918367059 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.918367059
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.525428314
Short name T316
Test name
Test status
Simulation time 361048947 ps
CPU time 2.52 seconds
Started Feb 29 01:40:49 PM PST 24
Finished Feb 29 01:40:51 PM PST 24
Peak memory 206568 kb
Host smart-42af232c-bed6-4ba2-8f0f-44a2aa626678
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525428314 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.525428314
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2458190976
Short name T659
Test name
Test status
Simulation time 150300544054 ps
CPU time 890.28 seconds
Started Feb 29 01:40:50 PM PST 24
Finished Feb 29 01:55:41 PM PST 24
Peak memory 219288 kb
Host smart-21720b40-2228-4975-b435-d5825c10d501
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458190976 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2458190976
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.1320190794
Short name T744
Test name
Test status
Simulation time 98400602 ps
CPU time 1.47 seconds
Started Feb 29 01:42:31 PM PST 24
Finished Feb 29 01:42:33 PM PST 24
Peak memory 217372 kb
Host smart-a6eba1fe-c900-4fd3-a2a1-e277ed5b011d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320190794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.1320190794
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1312094818
Short name T773
Test name
Test status
Simulation time 35829965 ps
CPU time 1.4 seconds
Started Feb 29 01:42:27 PM PST 24
Finished Feb 29 01:42:29 PM PST 24
Peak memory 217248 kb
Host smart-6d0411fb-c226-4994-91db-5c552ee6b02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312094818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1312094818
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1241113535
Short name T740
Test name
Test status
Simulation time 69425566 ps
CPU time 0.99 seconds
Started Feb 29 01:42:31 PM PST 24
Finished Feb 29 01:42:32 PM PST 24
Peak memory 215884 kb
Host smart-70202dc5-ebb9-418b-a19c-490e9638745e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241113535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1241113535
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2480037161
Short name T458
Test name
Test status
Simulation time 302110289 ps
CPU time 1.72 seconds
Started Feb 29 01:42:25 PM PST 24
Finished Feb 29 01:42:27 PM PST 24
Peak memory 217476 kb
Host smart-38bc8002-e8ec-450f-8cf2-235b11f7f8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480037161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2480037161
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.784331321
Short name T170
Test name
Test status
Simulation time 77552048 ps
CPU time 1.7 seconds
Started Feb 29 01:42:26 PM PST 24
Finished Feb 29 01:42:28 PM PST 24
Peak memory 216056 kb
Host smart-e6f46eb8-8e0e-40af-a3f8-5fc5db273dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784331321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.784331321
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.688107998
Short name T769
Test name
Test status
Simulation time 46294404 ps
CPU time 1.05 seconds
Started Feb 29 01:42:29 PM PST 24
Finished Feb 29 01:42:31 PM PST 24
Peak memory 215956 kb
Host smart-81db4154-37b0-4797-8efb-73847c2fd507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688107998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.688107998
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.4163078044
Short name T583
Test name
Test status
Simulation time 130962870 ps
CPU time 1.27 seconds
Started Feb 29 01:42:27 PM PST 24
Finished Feb 29 01:42:29 PM PST 24
Peak memory 218016 kb
Host smart-0dcf1670-27be-4c3d-9776-6dec9b731cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163078044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.4163078044
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.77840166
Short name T417
Test name
Test status
Simulation time 124657014 ps
CPU time 1.18 seconds
Started Feb 29 01:42:30 PM PST 24
Finished Feb 29 01:42:32 PM PST 24
Peak memory 216084 kb
Host smart-3c1f9995-b199-47f2-9cdc-28960a1477b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77840166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.77840166
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.3144891330
Short name T569
Test name
Test status
Simulation time 82902622 ps
CPU time 2.91 seconds
Started Feb 29 01:42:30 PM PST 24
Finished Feb 29 01:42:34 PM PST 24
Peak memory 218948 kb
Host smart-2d2aba81-bd62-4a62-b007-d930d07db5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144891330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.3144891330
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3176592926
Short name T166
Test name
Test status
Simulation time 75971201 ps
CPU time 1.11 seconds
Started Feb 29 01:40:52 PM PST 24
Finished Feb 29 01:40:53 PM PST 24
Peak memory 215060 kb
Host smart-9122dd8c-4469-4b88-a859-dec5ba7ac5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176592926 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3176592926
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1825294579
Short name T742
Test name
Test status
Simulation time 35644814 ps
CPU time 1.04 seconds
Started Feb 29 01:40:53 PM PST 24
Finished Feb 29 01:40:55 PM PST 24
Peak memory 206244 kb
Host smart-45280de3-edb6-4dbb-ab2d-81da5e403cc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825294579 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1825294579
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.51454710
Short name T240
Test name
Test status
Simulation time 12878031 ps
CPU time 0.85 seconds
Started Feb 29 01:40:52 PM PST 24
Finished Feb 29 01:40:53 PM PST 24
Peak memory 214792 kb
Host smart-dc598121-e17e-4462-8abc-c46cf9223f1e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51454710 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.51454710
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2360112858
Short name T79
Test name
Test status
Simulation time 21735254 ps
CPU time 1.06 seconds
Started Feb 29 01:40:53 PM PST 24
Finished Feb 29 01:40:54 PM PST 24
Peak memory 215864 kb
Host smart-cd3c961f-b051-4749-9261-3036cfda5633
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360112858 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2360112858
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2834136705
Short name T614
Test name
Test status
Simulation time 31238135 ps
CPU time 0.83 seconds
Started Feb 29 01:40:52 PM PST 24
Finished Feb 29 01:40:53 PM PST 24
Peak memory 216944 kb
Host smart-1e940236-7a2a-4e41-9a8e-cf0fd8ffe089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834136705 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2834136705
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_intr.1529086031
Short name T412
Test name
Test status
Simulation time 23106443 ps
CPU time 1.07 seconds
Started Feb 29 01:41:03 PM PST 24
Finished Feb 29 01:41:04 PM PST 24
Peak memory 214860 kb
Host smart-a9d8e72e-ed5c-44ea-be4b-cbe218cd2c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529086031 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.1529086031
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.2487167533
Short name T432
Test name
Test status
Simulation time 46662509 ps
CPU time 0.95 seconds
Started Feb 29 01:40:56 PM PST 24
Finished Feb 29 01:40:57 PM PST 24
Peak memory 214740 kb
Host smart-c28e68da-61ad-4cf0-9505-7109a6d244d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487167533 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.2487167533
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.39915108
Short name T160
Test name
Test status
Simulation time 375041924 ps
CPU time 3.91 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:12 PM PST 24
Peak memory 218380 kb
Host smart-89e4776c-10d7-4905-8fd9-a1663057b704
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39915108 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.39915108
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.1044998892
Short name T193
Test name
Test status
Simulation time 717915769530 ps
CPU time 899.11 seconds
Started Feb 29 01:40:51 PM PST 24
Finished Feb 29 01:55:50 PM PST 24
Peak memory 223172 kb
Host smart-40be56e6-5dfc-4c6b-92a6-f9a03beb9932
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044998892 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.1044998892
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1502824021
Short name T768
Test name
Test status
Simulation time 158804933 ps
CPU time 1.31 seconds
Started Feb 29 01:42:29 PM PST 24
Finished Feb 29 01:42:32 PM PST 24
Peak memory 217412 kb
Host smart-3aea531c-4820-4c8d-acc7-94fb2250c7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502824021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1502824021
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3488060585
Short name T317
Test name
Test status
Simulation time 70481927 ps
CPU time 1.26 seconds
Started Feb 29 01:42:29 PM PST 24
Finished Feb 29 01:42:32 PM PST 24
Peak memory 217292 kb
Host smart-cb571e16-e65d-48c1-b131-b09fc17f756f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488060585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3488060585
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3732743204
Short name T697
Test name
Test status
Simulation time 62384219 ps
CPU time 1.2 seconds
Started Feb 29 01:42:29 PM PST 24
Finished Feb 29 01:42:31 PM PST 24
Peak memory 217664 kb
Host smart-76f6b6e7-5eb9-4824-b751-cffffc00a019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732743204 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3732743204
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.4234992715
Short name T459
Test name
Test status
Simulation time 104641437 ps
CPU time 1.22 seconds
Started Feb 29 01:42:30 PM PST 24
Finished Feb 29 01:42:32 PM PST 24
Peak memory 216088 kb
Host smart-b6f7e2f3-90ff-4329-a8ae-8a1b5dbb8473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234992715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.4234992715
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.342191620
Short name T157
Test name
Test status
Simulation time 39558282 ps
CPU time 1.36 seconds
Started Feb 29 01:42:26 PM PST 24
Finished Feb 29 01:42:28 PM PST 24
Peak memory 218816 kb
Host smart-80827735-8a1e-4738-a982-8e5d9171a8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342191620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.342191620
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.3723976981
Short name T781
Test name
Test status
Simulation time 48548428 ps
CPU time 1.45 seconds
Started Feb 29 01:42:32 PM PST 24
Finished Feb 29 01:42:33 PM PST 24
Peak memory 217448 kb
Host smart-4fb2127d-3e20-463a-8897-36c1c0ad61ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723976981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.3723976981
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.843197389
Short name T340
Test name
Test status
Simulation time 46092808 ps
CPU time 1.09 seconds
Started Feb 29 01:42:27 PM PST 24
Finished Feb 29 01:42:29 PM PST 24
Peak memory 216272 kb
Host smart-6b261b6c-cebb-4948-b24a-7d632e9e4b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843197389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.843197389
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2223944568
Short name T802
Test name
Test status
Simulation time 53248287 ps
CPU time 1.75 seconds
Started Feb 29 01:42:31 PM PST 24
Finished Feb 29 01:42:33 PM PST 24
Peak memory 217156 kb
Host smart-921b00ab-b91f-4408-9d3b-a2431c0528cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223944568 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2223944568
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2493322577
Short name T620
Test name
Test status
Simulation time 57535703 ps
CPU time 1.21 seconds
Started Feb 29 01:42:26 PM PST 24
Finished Feb 29 01:42:27 PM PST 24
Peak memory 217328 kb
Host smart-9f64fe32-fb36-441f-aedd-f469b5e56f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493322577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2493322577
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert_test.252518987
Short name T537
Test name
Test status
Simulation time 46644036 ps
CPU time 0.88 seconds
Started Feb 29 01:40:53 PM PST 24
Finished Feb 29 01:40:54 PM PST 24
Peak memory 206084 kb
Host smart-a5803e65-2269-4ac3-b014-7f7f8c8c660a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252518987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.252518987
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.870213005
Short name T169
Test name
Test status
Simulation time 48042436 ps
CPU time 0.79 seconds
Started Feb 29 01:40:50 PM PST 24
Finished Feb 29 01:40:51 PM PST 24
Peak memory 214804 kb
Host smart-8c24b112-715f-4610-8fed-6bb04af0ff63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870213005 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.870213005
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1723134443
Short name T64
Test name
Test status
Simulation time 123627730 ps
CPU time 1.17 seconds
Started Feb 29 01:40:50 PM PST 24
Finished Feb 29 01:40:51 PM PST 24
Peak memory 215672 kb
Host smart-53702e89-0883-4e1d-83a3-d8a120a630e3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723134443 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1723134443
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.1106247455
Short name T83
Test name
Test status
Simulation time 36277312 ps
CPU time 0.89 seconds
Started Feb 29 01:40:59 PM PST 24
Finished Feb 29 01:41:01 PM PST 24
Peak memory 216092 kb
Host smart-6b15c8dc-a447-487b-967e-bd560bc33ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106247455 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.1106247455
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2048169876
Short name T755
Test name
Test status
Simulation time 454025045 ps
CPU time 4.46 seconds
Started Feb 29 01:40:51 PM PST 24
Finished Feb 29 01:40:56 PM PST 24
Peak memory 216344 kb
Host smart-b3928513-e9bc-40d8-ae2b-3e24a7cbf04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048169876 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2048169876
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2902432763
Short name T701
Test name
Test status
Simulation time 27521797 ps
CPU time 0.98 seconds
Started Feb 29 01:40:51 PM PST 24
Finished Feb 29 01:40:52 PM PST 24
Peak memory 214872 kb
Host smart-7bcdf954-e649-4a14-9853-39631831a7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902432763 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2902432763
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1817307609
Short name T572
Test name
Test status
Simulation time 85787801 ps
CPU time 0.94 seconds
Started Feb 29 01:40:52 PM PST 24
Finished Feb 29 01:40:53 PM PST 24
Peak memory 214724 kb
Host smart-0e0fedd9-c785-4dd9-a3ce-71298b32f2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817307609 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1817307609
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3746149724
Short name T534
Test name
Test status
Simulation time 111427564 ps
CPU time 2.34 seconds
Started Feb 29 01:40:51 PM PST 24
Finished Feb 29 01:40:54 PM PST 24
Peak memory 216020 kb
Host smart-f721fb0a-4e4c-4f5b-b74f-a2aa6b05a956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746149724 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3746149724
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.3837153501
Short name T796
Test name
Test status
Simulation time 112724109737 ps
CPU time 1341.1 seconds
Started Feb 29 01:40:52 PM PST 24
Finished Feb 29 02:03:13 PM PST 24
Peak memory 222196 kb
Host smart-5daec8d0-5f6e-455b-926f-7f39194ca1e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837153501 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.3837153501
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.592296638
Short name T716
Test name
Test status
Simulation time 56676344 ps
CPU time 1.35 seconds
Started Feb 29 01:42:28 PM PST 24
Finished Feb 29 01:42:30 PM PST 24
Peak memory 217384 kb
Host smart-87619641-33e4-4c05-8025-6e4085919231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592296638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.592296638
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2864939677
Short name T280
Test name
Test status
Simulation time 128472536 ps
CPU time 1.15 seconds
Started Feb 29 01:42:31 PM PST 24
Finished Feb 29 01:42:32 PM PST 24
Peak memory 218644 kb
Host smart-3b22139f-316a-4f6d-befa-b87c090e5e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864939677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2864939677
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.43339226
Short name T179
Test name
Test status
Simulation time 37691451 ps
CPU time 1.81 seconds
Started Feb 29 01:42:27 PM PST 24
Finished Feb 29 01:42:30 PM PST 24
Peak memory 216036 kb
Host smart-500d1140-c515-453f-9733-98eea4e38888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43339226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.43339226
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1377567438
Short name T168
Test name
Test status
Simulation time 26378195 ps
CPU time 1.14 seconds
Started Feb 29 01:42:33 PM PST 24
Finished Feb 29 01:42:35 PM PST 24
Peak memory 216072 kb
Host smart-1c20f6f8-b79c-4a76-ad7b-dea9b7e41ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377567438 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1377567438
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.3883464762
Short name T775
Test name
Test status
Simulation time 162210341 ps
CPU time 2.7 seconds
Started Feb 29 01:42:30 PM PST 24
Finished Feb 29 01:42:33 PM PST 24
Peak memory 218680 kb
Host smart-68d8dbd8-7f96-4ccc-8805-7306ba895b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883464762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.3883464762
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.2962527880
Short name T402
Test name
Test status
Simulation time 76211807 ps
CPU time 1.51 seconds
Started Feb 29 01:42:28 PM PST 24
Finished Feb 29 01:42:30 PM PST 24
Peak memory 217292 kb
Host smart-9f6154e1-1b13-4838-9c20-67849470db09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962527880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.2962527880
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.3695081373
Short name T526
Test name
Test status
Simulation time 86916301 ps
CPU time 1.27 seconds
Started Feb 29 01:42:26 PM PST 24
Finished Feb 29 01:42:27 PM PST 24
Peak memory 217216 kb
Host smart-d0e0e8c3-3bc9-48e9-89d2-b90a54304940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695081373 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.3695081373
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.168653317
Short name T37
Test name
Test status
Simulation time 57542605 ps
CPU time 1.34 seconds
Started Feb 29 01:42:30 PM PST 24
Finished Feb 29 01:42:32 PM PST 24
Peak memory 217032 kb
Host smart-846f9225-3207-4ac1-8300-514c33c858bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168653317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.168653317
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.372173928
Short name T377
Test name
Test status
Simulation time 89941956 ps
CPU time 1.13 seconds
Started Feb 29 01:42:27 PM PST 24
Finished Feb 29 01:42:30 PM PST 24
Peak memory 216080 kb
Host smart-9815bd5e-0090-4f4f-91a4-d4e84f90bde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372173928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.372173928
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.799401079
Short name T407
Test name
Test status
Simulation time 30612966 ps
CPU time 1.35 seconds
Started Feb 29 01:39:52 PM PST 24
Finished Feb 29 01:39:54 PM PST 24
Peak memory 215032 kb
Host smart-e2f5b096-5d58-403f-a888-b712acac0557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799401079 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.799401079
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.82357482
Short name T497
Test name
Test status
Simulation time 22786790 ps
CPU time 0.85 seconds
Started Feb 29 01:39:51 PM PST 24
Finished Feb 29 01:39:52 PM PST 24
Peak memory 206216 kb
Host smart-cc0fa149-7a6d-4bd2-80b6-494ef4ddad50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82357482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.82357482
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.3840642723
Short name T728
Test name
Test status
Simulation time 60000578 ps
CPU time 0.84 seconds
Started Feb 29 01:39:52 PM PST 24
Finished Feb 29 01:39:53 PM PST 24
Peak memory 215128 kb
Host smart-90fc5f15-005e-4cc9-9ebd-1bd6b3e1479c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840642723 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.3840642723
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_err.2362915657
Short name T105
Test name
Test status
Simulation time 94546169 ps
CPU time 0.91 seconds
Started Feb 29 01:39:56 PM PST 24
Finished Feb 29 01:39:57 PM PST 24
Peak memory 217176 kb
Host smart-1b99257b-4960-4e23-9554-2bab4a63dcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362915657 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2362915657
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.3425144477
Short name T758
Test name
Test status
Simulation time 46777412 ps
CPU time 1.49 seconds
Started Feb 29 01:39:51 PM PST 24
Finished Feb 29 01:39:52 PM PST 24
Peak memory 217164 kb
Host smart-2cd480d0-ae80-40f8-b798-2c55de90bde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425144477 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.3425144477
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.1786724777
Short name T304
Test name
Test status
Simulation time 23345609 ps
CPU time 1.06 seconds
Started Feb 29 01:39:55 PM PST 24
Finished Feb 29 01:39:57 PM PST 24
Peak memory 214980 kb
Host smart-143ff478-614c-4a14-ab1c-c5707adbfbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786724777 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.1786724777
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1955554132
Short name T261
Test name
Test status
Simulation time 21850543 ps
CPU time 0.93 seconds
Started Feb 29 01:39:52 PM PST 24
Finished Feb 29 01:39:53 PM PST 24
Peak memory 206496 kb
Host smart-1325a857-1e09-4839-92e3-31f80767ac25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955554132 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1955554132
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_smoke.4014087029
Short name T353
Test name
Test status
Simulation time 39660552 ps
CPU time 0.9 seconds
Started Feb 29 01:39:54 PM PST 24
Finished Feb 29 01:39:56 PM PST 24
Peak memory 214748 kb
Host smart-fa8614c9-ed92-44d2-bd4d-8dd7d29acc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014087029 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.4014087029
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2058810756
Short name T248
Test name
Test status
Simulation time 126860012 ps
CPU time 2.93 seconds
Started Feb 29 01:39:56 PM PST 24
Finished Feb 29 01:39:59 PM PST 24
Peak memory 217140 kb
Host smart-e852032c-a84a-4a92-aae9-d2274b3d0612
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058810756 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2058810756
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_alert.292555132
Short name T165
Test name
Test status
Simulation time 69569746 ps
CPU time 1.18 seconds
Started Feb 29 01:40:59 PM PST 24
Finished Feb 29 01:41:01 PM PST 24
Peak memory 215132 kb
Host smart-11997ab3-14da-4f36-a341-4d313aab0383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292555132 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.292555132
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1759956084
Short name T803
Test name
Test status
Simulation time 109907089 ps
CPU time 0.97 seconds
Started Feb 29 01:40:51 PM PST 24
Finished Feb 29 01:40:52 PM PST 24
Peak memory 206236 kb
Host smart-c2902354-47bc-4e86-be88-c36ccf9b469e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759956084 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1759956084
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_err.3284283089
Short name T662
Test name
Test status
Simulation time 21904876 ps
CPU time 0.95 seconds
Started Feb 29 01:40:51 PM PST 24
Finished Feb 29 01:40:52 PM PST 24
Peak memory 217536 kb
Host smart-b04b13d0-fce6-4c89-a646-3eba179630f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284283089 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3284283089
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.2725051409
Short name T310
Test name
Test status
Simulation time 40713548 ps
CPU time 1.57 seconds
Started Feb 29 01:40:53 PM PST 24
Finished Feb 29 01:40:54 PM PST 24
Peak memory 217316 kb
Host smart-db9947bf-b7b5-428b-a0d6-36a825a4ded7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725051409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.2725051409
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2588814390
Short name T123
Test name
Test status
Simulation time 40078641 ps
CPU time 0.93 seconds
Started Feb 29 01:40:56 PM PST 24
Finished Feb 29 01:40:57 PM PST 24
Peak memory 215012 kb
Host smart-82b1d867-6680-4486-960f-4cfa750d254f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588814390 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2588814390
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.4089139516
Short name T581
Test name
Test status
Simulation time 54167296 ps
CPU time 0.95 seconds
Started Feb 29 01:40:51 PM PST 24
Finished Feb 29 01:40:52 PM PST 24
Peak memory 214720 kb
Host smart-8fbc3a7a-b8c2-4c39-a0c6-2947e2bee73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089139516 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.4089139516
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.567074896
Short name T654
Test name
Test status
Simulation time 378834687 ps
CPU time 4.12 seconds
Started Feb 29 01:40:56 PM PST 24
Finished Feb 29 01:41:00 PM PST 24
Peak memory 215940 kb
Host smart-a52143f5-6383-49fc-b1dc-2953c1d000c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567074896 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.567074896
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.123432756
Short name T22
Test name
Test status
Simulation time 442256438778 ps
CPU time 901.8 seconds
Started Feb 29 01:40:53 PM PST 24
Finished Feb 29 01:55:55 PM PST 24
Peak memory 223132 kb
Host smart-8c4212a5-5696-4b33-b0e2-77618ecbb248
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123432756 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.123432756
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1187662432
Short name T162
Test name
Test status
Simulation time 25122909 ps
CPU time 1.21 seconds
Started Feb 29 01:40:55 PM PST 24
Finished Feb 29 01:40:56 PM PST 24
Peak memory 215048 kb
Host smart-266ed078-22e0-4561-982c-8973641aa0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187662432 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1187662432
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.360560313
Short name T658
Test name
Test status
Simulation time 18162226 ps
CPU time 1.01 seconds
Started Feb 29 01:41:00 PM PST 24
Finished Feb 29 01:41:02 PM PST 24
Peak memory 205400 kb
Host smart-99947ee2-095a-4b10-98b6-4517eab98fe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360560313 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.360560313
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3413876232
Short name T135
Test name
Test status
Simulation time 16605697 ps
CPU time 0.83 seconds
Started Feb 29 01:40:50 PM PST 24
Finished Feb 29 01:40:51 PM PST 24
Peak memory 215256 kb
Host smart-18d882b9-6c7e-44d4-bc41-f3b1bb0e22d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413876232 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3413876232
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.3803460553
Short name T86
Test name
Test status
Simulation time 123997123 ps
CPU time 1.29 seconds
Started Feb 29 01:40:52 PM PST 24
Finished Feb 29 01:40:53 PM PST 24
Peak memory 215824 kb
Host smart-ad33c469-d627-4238-b409-1b87ff7dc801
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803460553 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_d
isable_auto_req_mode.3803460553
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.4289479727
Short name T548
Test name
Test status
Simulation time 32442925 ps
CPU time 1.3 seconds
Started Feb 29 01:40:54 PM PST 24
Finished Feb 29 01:40:55 PM PST 24
Peak memory 219772 kb
Host smart-b1c1917d-08d0-4032-a846-4555bcb37382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289479727 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.4289479727
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.129628696
Short name T616
Test name
Test status
Simulation time 37259537 ps
CPU time 1.39 seconds
Started Feb 29 01:40:53 PM PST 24
Finished Feb 29 01:40:55 PM PST 24
Peak memory 217292 kb
Host smart-85d3396e-7ba5-4520-99a8-3f9a58e641a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129628696 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.129628696
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2126730949
Short name T176
Test name
Test status
Simulation time 39946482 ps
CPU time 0.9 seconds
Started Feb 29 01:40:52 PM PST 24
Finished Feb 29 01:40:53 PM PST 24
Peak memory 214780 kb
Host smart-420dcec1-866a-4ef6-8f2c-17b3ab8154fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126730949 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2126730949
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.2574951789
Short name T344
Test name
Test status
Simulation time 15282591 ps
CPU time 0.94 seconds
Started Feb 29 01:40:59 PM PST 24
Finished Feb 29 01:41:00 PM PST 24
Peak memory 214800 kb
Host smart-84112b57-2853-42de-8372-923f43baf17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574951789 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.2574951789
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.95574229
Short name T683
Test name
Test status
Simulation time 1561583774 ps
CPU time 4.89 seconds
Started Feb 29 01:40:56 PM PST 24
Finished Feb 29 01:41:01 PM PST 24
Peak memory 218696 kb
Host smart-68887e97-6d3e-4d2b-a867-aecf539beb98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95574229 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.95574229
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.420717252
Short name T333
Test name
Test status
Simulation time 165894270541 ps
CPU time 2127.75 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 02:16:37 PM PST 24
Peak memory 228928 kb
Host smart-2be10569-ba9e-4836-9d41-f0115faf8c8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420717252 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.420717252
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.3051602291
Short name T243
Test name
Test status
Simulation time 45984405 ps
CPU time 1.23 seconds
Started Feb 29 01:40:56 PM PST 24
Finished Feb 29 01:40:57 PM PST 24
Peak memory 215068 kb
Host smart-1b5b9538-a1c8-4654-85ab-37fca1c95266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051602291 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3051602291
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.2254931190
Short name T553
Test name
Test status
Simulation time 33723780 ps
CPU time 0.85 seconds
Started Feb 29 01:40:56 PM PST 24
Finished Feb 29 01:40:57 PM PST 24
Peak memory 205868 kb
Host smart-22b59786-92e2-4a54-83f0-639510458767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254931190 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.2254931190
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.62995122
Short name T177
Test name
Test status
Simulation time 50476062 ps
CPU time 0.92 seconds
Started Feb 29 01:40:52 PM PST 24
Finished Feb 29 01:40:53 PM PST 24
Peak memory 214892 kb
Host smart-9fb0943f-675d-450f-8e65-2fc120eb0b3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62995122 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.62995122
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3854373182
Short name T789
Test name
Test status
Simulation time 28207282 ps
CPU time 1.06 seconds
Started Feb 29 01:40:54 PM PST 24
Finished Feb 29 01:40:55 PM PST 24
Peak memory 217004 kb
Host smart-df7e0a38-8e7c-485f-a512-d6e1bb22a833
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854373182 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3854373182
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.2874450730
Short name T97
Test name
Test status
Simulation time 20027410 ps
CPU time 1.12 seconds
Started Feb 29 01:40:55 PM PST 24
Finished Feb 29 01:40:56 PM PST 24
Peak memory 230612 kb
Host smart-6c8d5fba-8193-4f27-9d5f-9c9f311c1d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874450730 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2874450730
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.436321356
Short name T237
Test name
Test status
Simulation time 70076318 ps
CPU time 2.44 seconds
Started Feb 29 01:41:00 PM PST 24
Finished Feb 29 01:41:03 PM PST 24
Peak memory 218800 kb
Host smart-dc82c168-f7a4-4943-b573-a96810fee0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436321356 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.436321356
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1964078148
Short name T535
Test name
Test status
Simulation time 38877431 ps
CPU time 0.89 seconds
Started Feb 29 01:41:00 PM PST 24
Finished Feb 29 01:41:01 PM PST 24
Peak memory 214812 kb
Host smart-40e5c053-faa8-4db5-9d6d-c4b39faf8899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964078148 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1964078148
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2144399620
Short name T808
Test name
Test status
Simulation time 40584009 ps
CPU time 0.86 seconds
Started Feb 29 01:40:51 PM PST 24
Finished Feb 29 01:40:52 PM PST 24
Peak memory 214712 kb
Host smart-84457041-c2e8-4ed9-983e-be2310a2f973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144399620 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2144399620
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.2495835726
Short name T337
Test name
Test status
Simulation time 448091149 ps
CPU time 5.27 seconds
Started Feb 29 01:40:52 PM PST 24
Finished Feb 29 01:40:58 PM PST 24
Peak memory 214792 kb
Host smart-4dca5f10-c2de-4a65-bba7-aed50754e44a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495835726 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.2495835726
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.141911770
Short name T562
Test name
Test status
Simulation time 1483161725349 ps
CPU time 2374.19 seconds
Started Feb 29 01:40:55 PM PST 24
Finished Feb 29 02:20:29 PM PST 24
Peak memory 235912 kb
Host smart-87309d0c-95ca-4e86-9731-15b0dd007b55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141911770 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.141911770
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3146695498
Short name T513
Test name
Test status
Simulation time 37791223 ps
CPU time 1.15 seconds
Started Feb 29 01:40:53 PM PST 24
Finished Feb 29 01:40:54 PM PST 24
Peak memory 215108 kb
Host smart-211a065b-ba22-4dd5-a04c-5e6c9279bf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146695498 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3146695498
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2496454732
Short name T764
Test name
Test status
Simulation time 24106489 ps
CPU time 0.91 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:10 PM PST 24
Peak memory 206252 kb
Host smart-dc79d236-41f8-4321-ad62-7dd527f058e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496454732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2496454732
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2737736353
Short name T143
Test name
Test status
Simulation time 14397529 ps
CPU time 0.93 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:10 PM PST 24
Peak memory 215332 kb
Host smart-a604cea4-2865-4c53-be15-a51350e12a1c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737736353 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2737736353
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2219160660
Short name T145
Test name
Test status
Simulation time 46970799 ps
CPU time 1.32 seconds
Started Feb 29 01:41:06 PM PST 24
Finished Feb 29 01:41:09 PM PST 24
Peak memory 215864 kb
Host smart-3ebd0bc7-4fd5-43bf-af1c-bade4cbea057
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219160660 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2219160660
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.1212417205
Short name T787
Test name
Test status
Simulation time 32754948 ps
CPU time 1.11 seconds
Started Feb 29 01:40:55 PM PST 24
Finished Feb 29 01:40:56 PM PST 24
Peak memory 222512 kb
Host smart-4a118549-b720-429b-b3eb-83cf67aa8831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212417205 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1212417205
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2481342192
Short name T350
Test name
Test status
Simulation time 182395125 ps
CPU time 1.72 seconds
Started Feb 29 01:40:56 PM PST 24
Finished Feb 29 01:40:58 PM PST 24
Peak memory 217700 kb
Host smart-942aa869-b9d0-4c8e-bac9-8a0ca97e04ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481342192 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2481342192
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.2559815145
Short name T129
Test name
Test status
Simulation time 21975155 ps
CPU time 0.89 seconds
Started Feb 29 01:40:59 PM PST 24
Finished Feb 29 01:41:01 PM PST 24
Peak memory 215248 kb
Host smart-b895a514-b399-4a74-909c-b7229d8e2e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559815145 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.2559815145
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.4058370162
Short name T707
Test name
Test status
Simulation time 47492767 ps
CPU time 0.9 seconds
Started Feb 29 01:40:55 PM PST 24
Finished Feb 29 01:40:56 PM PST 24
Peak memory 214736 kb
Host smart-6280d009-74b1-43af-afea-189c96ad2f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058370162 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.4058370162
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.4084196143
Short name T676
Test name
Test status
Simulation time 210278388 ps
CPU time 4.41 seconds
Started Feb 29 01:40:51 PM PST 24
Finished Feb 29 01:40:56 PM PST 24
Peak memory 218684 kb
Host smart-68b9f12b-84b2-43e8-957f-74459ebf550d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084196143 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.4084196143
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.4191785360
Short name T705
Test name
Test status
Simulation time 99081571318 ps
CPU time 467.78 seconds
Started Feb 29 01:40:59 PM PST 24
Finished Feb 29 01:48:47 PM PST 24
Peak memory 217652 kb
Host smart-14a3fb70-f058-4836-91cc-1014f06ac56d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191785360 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.4191785360
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1998525537
Short name T533
Test name
Test status
Simulation time 30914317 ps
CPU time 1.33 seconds
Started Feb 29 01:41:06 PM PST 24
Finished Feb 29 01:41:09 PM PST 24
Peak memory 215076 kb
Host smart-730e25bb-b302-409d-9955-c41f1f1f3fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998525537 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1998525537
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.654752458
Short name T577
Test name
Test status
Simulation time 16741869 ps
CPU time 0.9 seconds
Started Feb 29 01:41:11 PM PST 24
Finished Feb 29 01:41:12 PM PST 24
Peak memory 206312 kb
Host smart-5f488776-cb19-47e8-b8b9-23089e23e0e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654752458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.654752458
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.2419116054
Short name T586
Test name
Test status
Simulation time 13170384 ps
CPU time 0.92 seconds
Started Feb 29 01:41:06 PM PST 24
Finished Feb 29 01:41:09 PM PST 24
Peak memory 215044 kb
Host smart-5c8b179a-836f-4397-a1b2-f1d47a20132f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419116054 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.2419116054
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.2222958732
Short name T348
Test name
Test status
Simulation time 18944102 ps
CPU time 1.01 seconds
Started Feb 29 01:41:02 PM PST 24
Finished Feb 29 01:41:04 PM PST 24
Peak memory 217288 kb
Host smart-c35c0a0c-42bc-43c9-8241-c5f7766c9109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222958732 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.2222958732
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.888017450
Short name T30
Test name
Test status
Simulation time 50771750 ps
CPU time 1.52 seconds
Started Feb 29 01:41:06 PM PST 24
Finished Feb 29 01:41:09 PM PST 24
Peak memory 217104 kb
Host smart-cd4c3f0c-064b-43af-8a85-5066ab4659b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888017450 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.888017450
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.2018999048
Short name T627
Test name
Test status
Simulation time 36764507 ps
CPU time 0.9 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:10 PM PST 24
Peak memory 214984 kb
Host smart-1e52c64c-8fdd-4dc9-8abe-3bd36ccb2eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018999048 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.2018999048
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1325903077
Short name T732
Test name
Test status
Simulation time 58268741 ps
CPU time 0.98 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:10 PM PST 24
Peak memory 214736 kb
Host smart-cd43bc96-0050-42ef-8287-52f9b4510b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325903077 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1325903077
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2478442516
Short name T811
Test name
Test status
Simulation time 445586446 ps
CPU time 4.08 seconds
Started Feb 29 01:41:06 PM PST 24
Finished Feb 29 01:41:11 PM PST 24
Peak memory 216148 kb
Host smart-f8b87be6-a29e-4023-b025-85052e66eece
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478442516 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2478442516
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.2420738965
Short name T419
Test name
Test status
Simulation time 24031015198 ps
CPU time 604.18 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:51:14 PM PST 24
Peak memory 216832 kb
Host smart-bf07212c-d4f3-4db7-9670-67b5c81d1d1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420738965 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.2420738965
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert_test.3392327203
Short name T167
Test name
Test status
Simulation time 90135273 ps
CPU time 1.05 seconds
Started Feb 29 01:41:13 PM PST 24
Finished Feb 29 01:41:14 PM PST 24
Peak memory 205948 kb
Host smart-d35cffb2-e2d2-490f-a362-28bd09dcfb22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392327203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3392327203
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.635863868
Short name T606
Test name
Test status
Simulation time 147308698 ps
CPU time 0.9 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:09 PM PST 24
Peak memory 215144 kb
Host smart-9caea733-8ac8-48ca-9046-affdba9a4c6c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635863868 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.635863868
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.241417327
Short name T73
Test name
Test status
Simulation time 42715985 ps
CPU time 1.3 seconds
Started Feb 29 01:41:06 PM PST 24
Finished Feb 29 01:41:09 PM PST 24
Peak memory 218304 kb
Host smart-c92dca49-1b68-480c-8803-94528da4d6c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241417327 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.241417327
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.900453110
Short name T203
Test name
Test status
Simulation time 37530849 ps
CPU time 0.94 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:10 PM PST 24
Peak memory 222144 kb
Host smart-5338d3f5-50c2-47e5-b555-8d78a2127466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900453110 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.900453110
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.3147229321
Short name T668
Test name
Test status
Simulation time 70288957 ps
CPU time 1.17 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:10 PM PST 24
Peak memory 215900 kb
Host smart-9508cbc9-4242-4346-89c6-aa8310e0ce28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147229321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.3147229321
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1170734389
Short name T539
Test name
Test status
Simulation time 26215244 ps
CPU time 0.92 seconds
Started Feb 29 01:41:09 PM PST 24
Finished Feb 29 01:41:11 PM PST 24
Peak memory 215176 kb
Host smart-14718565-137e-4634-95df-f39fa0c7719d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170734389 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1170734389
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1412808218
Short name T582
Test name
Test status
Simulation time 16225749 ps
CPU time 1.03 seconds
Started Feb 29 01:41:08 PM PST 24
Finished Feb 29 01:41:11 PM PST 24
Peak memory 214756 kb
Host smart-4df9b330-df1f-4649-a7cd-21cd510f364f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412808218 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1412808218
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.4110049744
Short name T655
Test name
Test status
Simulation time 429516164 ps
CPU time 5.89 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:15 PM PST 24
Peak memory 216036 kb
Host smart-2541f584-95d7-40e0-816c-87844cd9066f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110049744 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.4110049744
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1774453162
Short name T186
Test name
Test status
Simulation time 129739961729 ps
CPU time 1706.69 seconds
Started Feb 29 01:41:10 PM PST 24
Finished Feb 29 02:09:37 PM PST 24
Peak memory 226576 kb
Host smart-5534bc4a-8f4f-4c4e-807d-f6794dc1c731
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774453162 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1774453162
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1452005777
Short name T262
Test name
Test status
Simulation time 26251880 ps
CPU time 1.23 seconds
Started Feb 29 01:41:10 PM PST 24
Finished Feb 29 01:41:12 PM PST 24
Peak memory 215072 kb
Host smart-5bf4cff6-aa94-4b13-9e58-473d9983507c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452005777 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1452005777
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3188161323
Short name T560
Test name
Test status
Simulation time 15146442 ps
CPU time 0.9 seconds
Started Feb 29 01:41:11 PM PST 24
Finished Feb 29 01:41:12 PM PST 24
Peak memory 205976 kb
Host smart-5b7719ef-a8a8-44a1-8039-5fa65d948476
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188161323 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3188161323
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.2294180447
Short name T698
Test name
Test status
Simulation time 41638229 ps
CPU time 0.88 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:09 PM PST 24
Peak memory 214836 kb
Host smart-a55a7602-eb39-4fca-8851-0aec5bd29c6b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294180447 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.2294180447
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1252248775
Short name T631
Test name
Test status
Simulation time 55905555 ps
CPU time 1.14 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:10 PM PST 24
Peak memory 217204 kb
Host smart-6b5d60a3-3aa7-4885-a693-63437c358cf1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252248775 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1252248775
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.872260755
Short name T98
Test name
Test status
Simulation time 30093677 ps
CPU time 1.27 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:10 PM PST 24
Peak memory 218580 kb
Host smart-289a0563-7b57-4c63-8b9c-1e67fa2a6d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872260755 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.872260755
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.3719044326
Short name T519
Test name
Test status
Simulation time 38482855 ps
CPU time 1.4 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:11 PM PST 24
Peak memory 216140 kb
Host smart-d49c3c80-81b2-4d92-afd0-5aac4f33c7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719044326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.3719044326
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.4048499772
Short name T499
Test name
Test status
Simulation time 28121137 ps
CPU time 1.11 seconds
Started Feb 29 01:41:03 PM PST 24
Finished Feb 29 01:41:04 PM PST 24
Peak memory 231992 kb
Host smart-50db7d6c-4d5a-4af8-a39c-cd496b8d38f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048499772 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.4048499772
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.1048186641
Short name T404
Test name
Test status
Simulation time 38370977 ps
CPU time 0.89 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:10 PM PST 24
Peak memory 214704 kb
Host smart-4dec1735-cfce-4641-9fbf-c0d4d471bd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048186641 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1048186641
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.1731397753
Short name T491
Test name
Test status
Simulation time 426807415 ps
CPU time 2.2 seconds
Started Feb 29 01:41:05 PM PST 24
Finished Feb 29 01:41:09 PM PST 24
Peak memory 218644 kb
Host smart-7c37bc1a-aa21-4753-afe2-406ffb1ba9cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731397753 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.1731397753
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1377909398
Short name T418
Test name
Test status
Simulation time 162052004980 ps
CPU time 1004.86 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:57:54 PM PST 24
Peak memory 222736 kb
Host smart-bba95e3e-b5b1-4fd8-8824-17d9d02946f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377909398 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1377909398
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.3193898730
Short name T94
Test name
Test status
Simulation time 29113158 ps
CPU time 1.22 seconds
Started Feb 29 01:41:06 PM PST 24
Finished Feb 29 01:41:09 PM PST 24
Peak memory 215036 kb
Host smart-1f1b2e3e-4599-4a7d-a219-0bff9559944d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193898730 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.3193898730
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.4069497033
Short name T443
Test name
Test status
Simulation time 22202899 ps
CPU time 1 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:10 PM PST 24
Peak memory 206176 kb
Host smart-1ddbb3d4-c0bf-440b-9c4d-37fc4c576ce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069497033 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.4069497033
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.570937339
Short name T138
Test name
Test status
Simulation time 123754481 ps
CPU time 1.18 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:10 PM PST 24
Peak memory 215764 kb
Host smart-a902bf95-a18b-44b0-8ab3-39b92b712a1c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570937339 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_di
sable_auto_req_mode.570937339
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1216859781
Short name T438
Test name
Test status
Simulation time 51731195 ps
CPU time 0.94 seconds
Started Feb 29 01:41:09 PM PST 24
Finished Feb 29 01:41:11 PM PST 24
Peak memory 217060 kb
Host smart-eeb35dc1-3a39-42a0-a519-fe59dae6ff89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216859781 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1216859781
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.911925578
Short name T33
Test name
Test status
Simulation time 46739427 ps
CPU time 1.54 seconds
Started Feb 29 01:41:03 PM PST 24
Finished Feb 29 01:41:05 PM PST 24
Peak memory 217180 kb
Host smart-be9071c7-09f0-475e-be92-6a4f39c7fdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911925578 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.911925578
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.1677232600
Short name T368
Test name
Test status
Simulation time 27236748 ps
CPU time 1.15 seconds
Started Feb 29 01:41:05 PM PST 24
Finished Feb 29 01:41:07 PM PST 24
Peak memory 223452 kb
Host smart-43d97173-1ef2-430b-a79f-93b36a2bb780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677232600 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1677232600
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.1814203890
Short name T504
Test name
Test status
Simulation time 17508595 ps
CPU time 1 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:10 PM PST 24
Peak memory 214664 kb
Host smart-e7c9cf0b-8390-47fb-a415-cc7d9b4a1b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814203890 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.1814203890
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1840064822
Short name T609
Test name
Test status
Simulation time 65261259 ps
CPU time 0.97 seconds
Started Feb 29 01:41:08 PM PST 24
Finished Feb 29 01:41:11 PM PST 24
Peak memory 205320 kb
Host smart-51b5b62e-1509-4a06-810e-989b8bbe4b61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840064822 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1840064822
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.822159954
Short name T625
Test name
Test status
Simulation time 537565452034 ps
CPU time 1868 seconds
Started Feb 29 01:41:05 PM PST 24
Finished Feb 29 02:12:14 PM PST 24
Peak memory 224280 kb
Host smart-fdfbb8df-2866-4492-879e-272d2b310df1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822159954 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.822159954
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert_test.616811525
Short name T679
Test name
Test status
Simulation time 28530652 ps
CPU time 0.86 seconds
Started Feb 29 01:41:06 PM PST 24
Finished Feb 29 01:41:09 PM PST 24
Peak memory 205876 kb
Host smart-0d6e4fbb-3626-4948-ab1c-d09c58f56828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616811525 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.616811525
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.337568250
Short name T108
Test name
Test status
Simulation time 22387633 ps
CPU time 0.87 seconds
Started Feb 29 01:41:05 PM PST 24
Finished Feb 29 01:41:07 PM PST 24
Peak memory 215244 kb
Host smart-22d38598-9785-49e0-9104-5e46465063b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337568250 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.337568250
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.1445082107
Short name T346
Test name
Test status
Simulation time 53011037 ps
CPU time 1.2 seconds
Started Feb 29 01:41:09 PM PST 24
Finished Feb 29 01:41:12 PM PST 24
Peak memory 215880 kb
Host smart-2f7b6328-a8d0-4ebd-a161-3ddf22226cda
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445082107 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.1445082107
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.2289515846
Short name T56
Test name
Test status
Simulation time 19374445 ps
CPU time 1.14 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:11 PM PST 24
Peak memory 217720 kb
Host smart-f3a11c54-1cc5-4af4-af9b-7139d1f50a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289515846 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2289515846
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2104206030
Short name T538
Test name
Test status
Simulation time 107023016 ps
CPU time 1.2 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:10 PM PST 24
Peak memory 215840 kb
Host smart-5061bbcd-5b2e-4585-8a1c-8257d4058e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104206030 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2104206030
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.2757711698
Short name T741
Test name
Test status
Simulation time 31816242 ps
CPU time 0.92 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:10 PM PST 24
Peak memory 214796 kb
Host smart-32c1a1dc-e9ac-4613-924a-8ed5cf661a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757711698 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.2757711698
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.3454151272
Short name T809
Test name
Test status
Simulation time 178444164 ps
CPU time 0.91 seconds
Started Feb 29 01:41:06 PM PST 24
Finished Feb 29 01:41:09 PM PST 24
Peak memory 214700 kb
Host smart-b7973fd4-e03d-48a5-8e42-ecf28500eff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454151272 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.3454151272
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.1706250219
Short name T555
Test name
Test status
Simulation time 119976349 ps
CPU time 2.66 seconds
Started Feb 29 01:41:08 PM PST 24
Finished Feb 29 01:41:12 PM PST 24
Peak memory 216244 kb
Host smart-fd49ae14-b871-4271-982a-41c3fdb3154c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706250219 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1706250219
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3005072022
Short name T677
Test name
Test status
Simulation time 156935707506 ps
CPU time 1691.29 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 02:09:21 PM PST 24
Peak memory 223876 kb
Host smart-79893994-62da-46df-9666-a0651b85986e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005072022 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3005072022
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.8778408
Short name T95
Test name
Test status
Simulation time 73940396 ps
CPU time 1.12 seconds
Started Feb 29 01:41:17 PM PST 24
Finished Feb 29 01:41:18 PM PST 24
Peak memory 215052 kb
Host smart-788eaeed-2674-4e31-b528-0799cb91bc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8778408 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.8778408
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3909485769
Short name T570
Test name
Test status
Simulation time 51428407 ps
CPU time 0.99 seconds
Started Feb 29 01:41:18 PM PST 24
Finished Feb 29 01:41:19 PM PST 24
Peak memory 206244 kb
Host smart-25831e79-b102-4d81-a086-e532d6f8caa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909485769 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3909485769
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.789252841
Short name T113
Test name
Test status
Simulation time 11679109 ps
CPU time 0.92 seconds
Started Feb 29 01:41:19 PM PST 24
Finished Feb 29 01:41:20 PM PST 24
Peak memory 215280 kb
Host smart-23916916-5730-4467-9f6d-660e5f07bdb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789252841 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.789252841
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_err.2778241277
Short name T684
Test name
Test status
Simulation time 20692873 ps
CPU time 0.92 seconds
Started Feb 29 01:41:18 PM PST 24
Finished Feb 29 01:41:20 PM PST 24
Peak memory 217152 kb
Host smart-2cfe5cc7-63f8-44e2-9a3a-f0e7c6f43a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778241277 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2778241277
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3002971007
Short name T558
Test name
Test status
Simulation time 30493075 ps
CPU time 1.4 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:11 PM PST 24
Peak memory 217120 kb
Host smart-1c38f700-5216-4ed2-81d5-e0b600fbd92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002971007 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3002971007
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.1722921236
Short name T43
Test name
Test status
Simulation time 48085928 ps
CPU time 0.96 seconds
Started Feb 29 01:41:22 PM PST 24
Finished Feb 29 01:41:24 PM PST 24
Peak memory 222436 kb
Host smart-1d4f37ab-d52a-4995-bd05-fd5027699cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722921236 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.1722921236
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.3391864518
Short name T641
Test name
Test status
Simulation time 17904329 ps
CPU time 0.97 seconds
Started Feb 29 01:41:06 PM PST 24
Finished Feb 29 01:41:08 PM PST 24
Peak memory 214732 kb
Host smart-17bbd0a2-4719-4e9f-9497-d1129d5d4879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391864518 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.3391864518
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2066880657
Short name T696
Test name
Test status
Simulation time 889649929 ps
CPU time 3.35 seconds
Started Feb 29 01:41:07 PM PST 24
Finished Feb 29 01:41:13 PM PST 24
Peak memory 214892 kb
Host smart-0b58d959-6aea-45ae-819f-14821228f90f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066880657 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2066880657
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.318521439
Short name T828
Test name
Test status
Simulation time 94860757826 ps
CPU time 2431.25 seconds
Started Feb 29 01:41:20 PM PST 24
Finished Feb 29 02:21:52 PM PST 24
Peak memory 230372 kb
Host smart-28b448e9-76fd-4d5f-8fb7-ce071ecc2af0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318521439 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.318521439
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.390662693
Short name T835
Test name
Test status
Simulation time 72821272 ps
CPU time 1.19 seconds
Started Feb 29 01:40:08 PM PST 24
Finished Feb 29 01:40:09 PM PST 24
Peak memory 215040 kb
Host smart-9304504d-d5c2-4a23-8065-07e5d39bb0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390662693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.390662693
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.3259848640
Short name T648
Test name
Test status
Simulation time 22117842 ps
CPU time 0.98 seconds
Started Feb 29 01:40:04 PM PST 24
Finished Feb 29 01:40:05 PM PST 24
Peak memory 206156 kb
Host smart-d5a942b9-c722-4b1b-841a-8cd1f8210cb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259848640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.3259848640
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3795758905
Short name T112
Test name
Test status
Simulation time 13992129 ps
CPU time 0.95 seconds
Started Feb 29 01:40:06 PM PST 24
Finished Feb 29 01:40:07 PM PST 24
Peak memory 215344 kb
Host smart-cc61a846-58b0-4b1b-8038-823dbea3b185
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795758905 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3795758905
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2595901293
Short name T799
Test name
Test status
Simulation time 85225953 ps
CPU time 1.1 seconds
Started Feb 29 01:40:09 PM PST 24
Finished Feb 29 01:40:11 PM PST 24
Peak memory 216032 kb
Host smart-aecf32ad-16ca-427c-9d85-77a98b3b31ca
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595901293 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2595901293
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.2843671104
Short name T579
Test name
Test status
Simulation time 23437913 ps
CPU time 0.92 seconds
Started Feb 29 01:40:08 PM PST 24
Finished Feb 29 01:40:11 PM PST 24
Peak memory 217324 kb
Host smart-ba0f36b2-4e28-43ed-9506-4146885ada66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843671104 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.2843671104
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.1727556290
Short name T202
Test name
Test status
Simulation time 152938652 ps
CPU time 2.63 seconds
Started Feb 29 01:40:08 PM PST 24
Finished Feb 29 01:40:11 PM PST 24
Peak memory 216416 kb
Host smart-824d73e9-c6a3-4a59-a722-e20d59a90f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727556290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.1727556290
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.753994199
Short name T131
Test name
Test status
Simulation time 34001535 ps
CPU time 0.82 seconds
Started Feb 29 01:40:10 PM PST 24
Finished Feb 29 01:40:12 PM PST 24
Peak memory 215008 kb
Host smart-9fff9704-13bc-4681-b0dd-286445dde543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753994199 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.753994199
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_sec_cm.907522884
Short name T44
Test name
Test status
Simulation time 208766120 ps
CPU time 3.79 seconds
Started Feb 29 01:40:07 PM PST 24
Finished Feb 29 01:40:11 PM PST 24
Peak memory 233616 kb
Host smart-49a22595-f5db-4105-87f0-2f47a88b4ba0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907522884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.907522884
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.2328334243
Short name T587
Test name
Test status
Simulation time 19046353 ps
CPU time 1.03 seconds
Started Feb 29 01:39:57 PM PST 24
Finished Feb 29 01:39:58 PM PST 24
Peak memory 214728 kb
Host smart-e119d37b-e14d-486e-9f4a-e53dc4793a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328334243 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2328334243
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1641352192
Short name T770
Test name
Test status
Simulation time 283347708 ps
CPU time 5.76 seconds
Started Feb 29 01:40:07 PM PST 24
Finished Feb 29 01:40:13 PM PST 24
Peak memory 214788 kb
Host smart-4a04e108-b574-4024-b304-9db8947400a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641352192 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1641352192
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1981815724
Short name T826
Test name
Test status
Simulation time 223412086214 ps
CPU time 1470.3 seconds
Started Feb 29 01:40:10 PM PST 24
Finished Feb 29 02:04:42 PM PST 24
Peak memory 222752 kb
Host smart-58cf57a2-309e-427c-9e02-826a0531285f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981815724 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1981815724
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.260958860
Short name T171
Test name
Test status
Simulation time 94514721 ps
CPU time 1.31 seconds
Started Feb 29 01:41:15 PM PST 24
Finished Feb 29 01:41:16 PM PST 24
Peak memory 215076 kb
Host smart-c7c75572-2c6e-4799-b44a-c5c7ce7b884a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260958860 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.260958860
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2774409394
Short name T566
Test name
Test status
Simulation time 37166894 ps
CPU time 0.93 seconds
Started Feb 29 01:41:19 PM PST 24
Finished Feb 29 01:41:21 PM PST 24
Peak memory 206260 kb
Host smart-d1478f3e-b7a5-427d-ba90-35d81d046ef4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774409394 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2774409394
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.673238311
Short name T88
Test name
Test status
Simulation time 13537809 ps
CPU time 0.89 seconds
Started Feb 29 01:41:26 PM PST 24
Finished Feb 29 01:41:28 PM PST 24
Peak memory 215012 kb
Host smart-f86e2661-41a8-41ef-a2b1-b29577bd1708
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673238311 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.673238311
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3929511180
Short name T80
Test name
Test status
Simulation time 42638198 ps
CPU time 1.11 seconds
Started Feb 29 01:41:21 PM PST 24
Finished Feb 29 01:41:23 PM PST 24
Peak memory 215968 kb
Host smart-3502882d-63e3-41c7-afe5-10efa18a8ee0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929511180 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3929511180
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.4068215157
Short name T91
Test name
Test status
Simulation time 22879863 ps
CPU time 1.07 seconds
Started Feb 29 01:41:19 PM PST 24
Finished Feb 29 01:41:21 PM PST 24
Peak memory 222420 kb
Host smart-a7db8d3d-86be-4782-9cb2-45f8d0744e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068215157 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.4068215157
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.3314084530
Short name T551
Test name
Test status
Simulation time 267591548 ps
CPU time 1.02 seconds
Started Feb 29 01:41:15 PM PST 24
Finished Feb 29 01:41:16 PM PST 24
Peak memory 216020 kb
Host smart-19370d0d-cb92-4e56-8741-289f005ac791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314084530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.3314084530
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.3850502274
Short name T395
Test name
Test status
Simulation time 25495885 ps
CPU time 0.96 seconds
Started Feb 29 01:41:17 PM PST 24
Finished Feb 29 01:41:18 PM PST 24
Peak memory 214800 kb
Host smart-22541b73-9ae8-47d1-8c5c-8feca5653f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850502274 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3850502274
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2367375909
Short name T421
Test name
Test status
Simulation time 16500148 ps
CPU time 0.98 seconds
Started Feb 29 01:41:29 PM PST 24
Finished Feb 29 01:41:30 PM PST 24
Peak memory 214728 kb
Host smart-8addb2e6-de80-43f2-ad36-7478834d8d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367375909 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2367375909
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.357350649
Short name T199
Test name
Test status
Simulation time 119805740 ps
CPU time 2.65 seconds
Started Feb 29 01:41:18 PM PST 24
Finished Feb 29 01:41:21 PM PST 24
Peak memory 214716 kb
Host smart-0ab908fc-c0e0-4e49-a67e-b83c2033de15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357350649 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.357350649
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.1696981066
Short name T643
Test name
Test status
Simulation time 85011580200 ps
CPU time 2138.07 seconds
Started Feb 29 01:41:17 PM PST 24
Finished Feb 29 02:16:56 PM PST 24
Peak memory 228504 kb
Host smart-ecef4457-281c-47d0-805c-724dbc7fb08f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696981066 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.1696981066
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.1508366914
Short name T267
Test name
Test status
Simulation time 30848412 ps
CPU time 1.25 seconds
Started Feb 29 01:41:24 PM PST 24
Finished Feb 29 01:41:26 PM PST 24
Peak memory 215088 kb
Host smart-9c97a9a4-5a19-4164-bb36-891328de5a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508366914 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.1508366914
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.244690852
Short name T241
Test name
Test status
Simulation time 25290563 ps
CPU time 0.86 seconds
Started Feb 29 01:41:23 PM PST 24
Finished Feb 29 01:41:24 PM PST 24
Peak memory 206260 kb
Host smart-72d4dd94-4b46-4ab1-aa11-f987addd53d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244690852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.244690852
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.981521831
Short name T806
Test name
Test status
Simulation time 31066594 ps
CPU time 0.81 seconds
Started Feb 29 01:41:19 PM PST 24
Finished Feb 29 01:41:20 PM PST 24
Peak memory 214844 kb
Host smart-cee48f3a-6727-45ed-95dd-37ad5b92bdaa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981521831 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.981521831
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.383934096
Short name T594
Test name
Test status
Simulation time 91001248 ps
CPU time 1.07 seconds
Started Feb 29 01:41:18 PM PST 24
Finished Feb 29 01:41:20 PM PST 24
Peak memory 215792 kb
Host smart-71da1d3d-cabd-411f-9729-fa84f1f0c6fa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383934096 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.383934096
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2882384353
Short name T90
Test name
Test status
Simulation time 56492507 ps
CPU time 0.83 seconds
Started Feb 29 01:41:20 PM PST 24
Finished Feb 29 01:41:21 PM PST 24
Peak memory 217012 kb
Host smart-550ff505-70f5-4178-a6a2-4e6c8bc74bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882384353 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2882384353
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.2692515990
Short name T278
Test name
Test status
Simulation time 299444718 ps
CPU time 1.82 seconds
Started Feb 29 01:41:18 PM PST 24
Finished Feb 29 01:41:20 PM PST 24
Peak memory 217524 kb
Host smart-2fd484eb-b12b-4846-b9af-acd890593e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692515990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.2692515990
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.939160929
Short name T794
Test name
Test status
Simulation time 22583180 ps
CPU time 1.12 seconds
Started Feb 29 01:41:19 PM PST 24
Finished Feb 29 01:41:21 PM PST 24
Peak memory 214988 kb
Host smart-f3bd70ac-3423-448d-9d12-5c339c66a42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939160929 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.939160929
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.4238029977
Short name T703
Test name
Test status
Simulation time 23316786 ps
CPU time 0.9 seconds
Started Feb 29 01:41:29 PM PST 24
Finished Feb 29 01:41:30 PM PST 24
Peak memory 214728 kb
Host smart-f5b33181-2c89-4075-b0b4-05ec2de550ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238029977 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.4238029977
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.2615721374
Short name T271
Test name
Test status
Simulation time 49222975 ps
CPU time 1.15 seconds
Started Feb 29 01:41:21 PM PST 24
Finished Feb 29 01:41:22 PM PST 24
Peak memory 215976 kb
Host smart-e7e7e9b2-36b1-4075-934f-1664b5303166
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615721374 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2615721374
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3030304105
Short name T536
Test name
Test status
Simulation time 47548602800 ps
CPU time 546.07 seconds
Started Feb 29 01:41:21 PM PST 24
Finished Feb 29 01:50:27 PM PST 24
Peak memory 216620 kb
Host smart-0b275360-0551-42b6-bc3d-e546a8d66bd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030304105 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3030304105
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert_test.3831100173
Short name T385
Test name
Test status
Simulation time 22133421 ps
CPU time 0.99 seconds
Started Feb 29 01:41:29 PM PST 24
Finished Feb 29 01:41:30 PM PST 24
Peak memory 206248 kb
Host smart-235a6c6a-736d-441e-a0dc-87eae70dd869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831100173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.3831100173
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1487805987
Short name T149
Test name
Test status
Simulation time 20036158 ps
CPU time 0.91 seconds
Started Feb 29 01:41:16 PM PST 24
Finished Feb 29 01:41:17 PM PST 24
Peak memory 215120 kb
Host smart-d213f189-260e-466e-990e-f0a31159cc9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487805987 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1487805987
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.1399006803
Short name T71
Test name
Test status
Simulation time 84810803 ps
CPU time 1.09 seconds
Started Feb 29 01:41:19 PM PST 24
Finished Feb 29 01:41:20 PM PST 24
Peak memory 217092 kb
Host smart-6b4c03c3-9277-4526-987e-4b8a08ff7680
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399006803 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.1399006803
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.722306343
Short name T205
Test name
Test status
Simulation time 18297052 ps
CPU time 1.15 seconds
Started Feb 29 01:41:19 PM PST 24
Finished Feb 29 01:41:21 PM PST 24
Peak memory 222556 kb
Host smart-f3d03593-8bd7-4ece-9d19-0899871e40fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722306343 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.722306343
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.4220255232
Short name T384
Test name
Test status
Simulation time 77689041 ps
CPU time 1.14 seconds
Started Feb 29 01:41:21 PM PST 24
Finished Feb 29 01:41:22 PM PST 24
Peak memory 215864 kb
Host smart-1ffa7dfd-ba0d-4db6-9d61-56a9cf714620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220255232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.4220255232
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2530316383
Short name T128
Test name
Test status
Simulation time 30809051 ps
CPU time 0.85 seconds
Started Feb 29 01:41:21 PM PST 24
Finished Feb 29 01:41:22 PM PST 24
Peak memory 214700 kb
Host smart-155d20de-b807-4367-8efa-5d681f48f6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530316383 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2530316383
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.4172546584
Short name T311
Test name
Test status
Simulation time 46490754 ps
CPU time 0.89 seconds
Started Feb 29 01:41:19 PM PST 24
Finished Feb 29 01:41:20 PM PST 24
Peak memory 214600 kb
Host smart-6bf4a0e1-db66-412a-b4f0-f67752de6bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172546584 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.4172546584
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.821921443
Short name T156
Test name
Test status
Simulation time 344287672 ps
CPU time 2.27 seconds
Started Feb 29 01:41:18 PM PST 24
Finished Feb 29 01:41:21 PM PST 24
Peak memory 214672 kb
Host smart-a6108733-a1bf-44f6-9715-0e66dd13bc19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821921443 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.821921443
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.2895616467
Short name T191
Test name
Test status
Simulation time 42591541649 ps
CPU time 929.62 seconds
Started Feb 29 01:41:21 PM PST 24
Finished Feb 29 01:56:51 PM PST 24
Peak memory 218080 kb
Host smart-1e860fef-d66f-48b1-9b8c-198ed051ee3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895616467 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.2895616467
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2610280897
Short name T749
Test name
Test status
Simulation time 26485418 ps
CPU time 1.25 seconds
Started Feb 29 01:41:21 PM PST 24
Finished Feb 29 01:41:22 PM PST 24
Peak memory 214984 kb
Host smart-ea8039d9-c94c-43ec-8a8d-cbfb60aed6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610280897 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2610280897
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.4147954235
Short name T465
Test name
Test status
Simulation time 19030766 ps
CPU time 0.77 seconds
Started Feb 29 01:41:20 PM PST 24
Finished Feb 29 01:41:22 PM PST 24
Peak memory 205048 kb
Host smart-b36930c5-1024-4a23-8e50-ad67635f6d97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147954235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.4147954235
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2284367073
Short name T136
Test name
Test status
Simulation time 41139960 ps
CPU time 0.88 seconds
Started Feb 29 01:41:19 PM PST 24
Finished Feb 29 01:41:20 PM PST 24
Peak memory 215200 kb
Host smart-753f3af7-154f-43cb-a509-51350b81200b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284367073 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2284367073
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.2430601982
Short name T84
Test name
Test status
Simulation time 57337071 ps
CPU time 1.22 seconds
Started Feb 29 01:41:17 PM PST 24
Finished Feb 29 01:41:18 PM PST 24
Peak memory 215700 kb
Host smart-6afc7ded-030f-427c-8310-a321d2ef3704
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430601982 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.2430601982
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.3104571321
Short name T503
Test name
Test status
Simulation time 18454027 ps
CPU time 1.04 seconds
Started Feb 29 01:41:20 PM PST 24
Finished Feb 29 01:41:22 PM PST 24
Peak memory 217392 kb
Host smart-0fe41a41-9f1d-4701-a70e-b0a8f2267a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104571321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3104571321
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1196114351
Short name T713
Test name
Test status
Simulation time 33401307 ps
CPU time 1.28 seconds
Started Feb 29 01:41:24 PM PST 24
Finished Feb 29 01:41:26 PM PST 24
Peak memory 217320 kb
Host smart-94aa3557-74a4-4708-82c3-ab4ee1a84b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196114351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1196114351
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.1666423079
Short name T508
Test name
Test status
Simulation time 41328130 ps
CPU time 0.9 seconds
Started Feb 29 01:41:29 PM PST 24
Finished Feb 29 01:41:30 PM PST 24
Peak memory 214988 kb
Host smart-8f9f2c4c-a710-4304-a412-16a02abf740e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666423079 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.1666423079
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.901192664
Short name T788
Test name
Test status
Simulation time 41494529 ps
CPU time 0.97 seconds
Started Feb 29 01:41:21 PM PST 24
Finished Feb 29 01:41:23 PM PST 24
Peak memory 214800 kb
Host smart-c41d8fee-0c33-4e0b-80f6-dedecb50aba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901192664 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.901192664
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.1019799737
Short name T493
Test name
Test status
Simulation time 85318663 ps
CPU time 2.18 seconds
Started Feb 29 01:41:18 PM PST 24
Finished Feb 29 01:41:20 PM PST 24
Peak memory 216012 kb
Host smart-37227b00-f420-4a87-886c-2d6062c4d8bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019799737 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.1019799737
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2398070381
Short name T192
Test name
Test status
Simulation time 13594690762 ps
CPU time 291.43 seconds
Started Feb 29 01:41:19 PM PST 24
Finished Feb 29 01:46:11 PM PST 24
Peak memory 217844 kb
Host smart-cbc4f86b-72b0-45c5-973d-d505570dbc25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398070381 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2398070381
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.4170205086
Short name T774
Test name
Test status
Simulation time 85597523 ps
CPU time 1.19 seconds
Started Feb 29 01:41:20 PM PST 24
Finished Feb 29 01:41:22 PM PST 24
Peak memory 215100 kb
Host smart-ac846052-69f7-4169-8264-fed2d23654e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170205086 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.4170205086
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2646537483
Short name T369
Test name
Test status
Simulation time 21129076 ps
CPU time 0.86 seconds
Started Feb 29 01:41:17 PM PST 24
Finished Feb 29 01:41:18 PM PST 24
Peak memory 205864 kb
Host smart-d92bc1d0-1c15-4ad5-a195-d937f9593feb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646537483 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2646537483
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.122348978
Short name T771
Test name
Test status
Simulation time 10946480 ps
CPU time 0.91 seconds
Started Feb 29 01:41:18 PM PST 24
Finished Feb 29 01:41:19 PM PST 24
Peak memory 214800 kb
Host smart-ceba7b75-251f-4436-9905-05b888be9c69
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122348978 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.122348978
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.3025328328
Short name T50
Test name
Test status
Simulation time 61001705 ps
CPU time 1.2 seconds
Started Feb 29 01:41:23 PM PST 24
Finished Feb 29 01:41:25 PM PST 24
Peak memory 215704 kb
Host smart-c9a89e0d-e6a0-4109-b0b8-fcb4bee482ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025328328 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.3025328328
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2979253322
Short name T782
Test name
Test status
Simulation time 51452939 ps
CPU time 1.08 seconds
Started Feb 29 01:41:28 PM PST 24
Finished Feb 29 01:41:30 PM PST 24
Peak memory 230704 kb
Host smart-133739cd-9921-4f3b-bbea-e3ed42638587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979253322 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2979253322
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.2585037906
Short name T737
Test name
Test status
Simulation time 82722095 ps
CPU time 1.15 seconds
Started Feb 29 01:41:21 PM PST 24
Finished Feb 29 01:41:22 PM PST 24
Peak memory 218424 kb
Host smart-d571903b-0e5b-40a6-b576-9f4777e734fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585037906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.2585037906
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.553430739
Short name T837
Test name
Test status
Simulation time 31249128 ps
CPU time 0.98 seconds
Started Feb 29 01:41:18 PM PST 24
Finished Feb 29 01:41:19 PM PST 24
Peak memory 214952 kb
Host smart-0bb3cb94-dcca-46f8-83c9-288798bba294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553430739 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.553430739
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1209509037
Short name T735
Test name
Test status
Simulation time 17819767 ps
CPU time 0.97 seconds
Started Feb 29 01:41:24 PM PST 24
Finished Feb 29 01:41:26 PM PST 24
Peak memory 214708 kb
Host smart-d8d40e91-a439-4a8f-b0f2-eddacdd808fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209509037 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1209509037
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.953473865
Short name T452
Test name
Test status
Simulation time 86215469 ps
CPU time 2.23 seconds
Started Feb 29 01:41:24 PM PST 24
Finished Feb 29 01:41:27 PM PST 24
Peak memory 214812 kb
Host smart-18a656fb-2a0c-4cb1-a962-b77d83bf16c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953473865 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.953473865
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1479961179
Short name T507
Test name
Test status
Simulation time 193485227566 ps
CPU time 2312.16 seconds
Started Feb 29 01:41:19 PM PST 24
Finished Feb 29 02:19:52 PM PST 24
Peak memory 226940 kb
Host smart-30d2f176-bf3e-4808-b4f3-59b6143db3cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479961179 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1479961179
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.1495186755
Short name T522
Test name
Test status
Simulation time 30365247 ps
CPU time 1.33 seconds
Started Feb 29 01:41:20 PM PST 24
Finished Feb 29 01:41:22 PM PST 24
Peak memory 215000 kb
Host smart-dc922131-323c-46f5-9776-9702f4b6b56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495186755 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.1495186755
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2075882221
Short name T690
Test name
Test status
Simulation time 52843238 ps
CPU time 0.92 seconds
Started Feb 29 01:41:19 PM PST 24
Finished Feb 29 01:41:21 PM PST 24
Peak memory 205436 kb
Host smart-47b2bd91-e56c-4b85-a89f-a7937040c561
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075882221 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2075882221
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2110156268
Short name T204
Test name
Test status
Simulation time 17019101 ps
CPU time 0.83 seconds
Started Feb 29 01:41:17 PM PST 24
Finished Feb 29 01:41:18 PM PST 24
Peak memory 214940 kb
Host smart-54c90754-c114-4e77-870d-bbf8ecb6a77c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110156268 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2110156268
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3268562533
Short name T139
Test name
Test status
Simulation time 149384677 ps
CPU time 1.06 seconds
Started Feb 29 01:41:17 PM PST 24
Finished Feb 29 01:41:18 PM PST 24
Peak memory 216140 kb
Host smart-b3683d8f-efe8-4ed5-81c6-677551028a0a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268562533 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3268562533
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_genbits.217031526
Short name T817
Test name
Test status
Simulation time 45103864 ps
CPU time 1.65 seconds
Started Feb 29 01:41:23 PM PST 24
Finished Feb 29 01:41:25 PM PST 24
Peak memory 218272 kb
Host smart-20e5b345-6c1c-4e37-9dd6-05f0114a211b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217031526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.217031526
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3321377123
Short name T359
Test name
Test status
Simulation time 36889087 ps
CPU time 0.94 seconds
Started Feb 29 01:41:20 PM PST 24
Finished Feb 29 01:41:21 PM PST 24
Peak memory 215012 kb
Host smart-5c49700d-2b21-4bb3-947c-85f1b9f6de71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321377123 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3321377123
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.72016656
Short name T793
Test name
Test status
Simulation time 16200375 ps
CPU time 0.97 seconds
Started Feb 29 01:41:21 PM PST 24
Finished Feb 29 01:41:22 PM PST 24
Peak memory 214748 kb
Host smart-807d171b-7828-4252-ae7b-9a6b11d98df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72016656 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.72016656
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2693663393
Short name T198
Test name
Test status
Simulation time 920900402 ps
CPU time 5.31 seconds
Started Feb 29 01:41:22 PM PST 24
Finished Feb 29 01:41:27 PM PST 24
Peak memory 215904 kb
Host smart-9447f3e8-be0d-4329-9361-43dd7c992e3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693663393 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2693663393
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3386805240
Short name T187
Test name
Test status
Simulation time 26729070203 ps
CPU time 622.49 seconds
Started Feb 29 01:41:21 PM PST 24
Finished Feb 29 01:51:44 PM PST 24
Peak memory 217276 kb
Host smart-2aa60112-ebd9-44b2-920c-44268273fcfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386805240 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3386805240
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1346220301
Short name T478
Test name
Test status
Simulation time 42299040 ps
CPU time 1.18 seconds
Started Feb 29 01:41:20 PM PST 24
Finished Feb 29 01:41:22 PM PST 24
Peak memory 215052 kb
Host smart-fabc374e-2566-4c48-aa8d-0a6ef9ab0712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346220301 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1346220301
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.3177914080
Short name T530
Test name
Test status
Simulation time 37940292 ps
CPU time 0.95 seconds
Started Feb 29 01:41:33 PM PST 24
Finished Feb 29 01:41:36 PM PST 24
Peak memory 206112 kb
Host smart-dff574cd-020a-4dd5-a926-d3f3856b4cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177914080 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.3177914080
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1718863870
Short name T545
Test name
Test status
Simulation time 115075772 ps
CPU time 0.86 seconds
Started Feb 29 01:41:20 PM PST 24
Finished Feb 29 01:41:21 PM PST 24
Peak memory 214920 kb
Host smart-22fe182c-be72-4c6b-8352-127c382b98bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718863870 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1718863870
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_err.1606190946
Short name T74
Test name
Test status
Simulation time 31814497 ps
CPU time 1.09 seconds
Started Feb 29 01:41:20 PM PST 24
Finished Feb 29 01:41:22 PM PST 24
Peak memory 217200 kb
Host smart-c6e02254-050e-4f45-b234-ec5c4c4f7883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606190946 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.1606190946
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.894494043
Short name T10
Test name
Test status
Simulation time 130931175 ps
CPU time 1.18 seconds
Started Feb 29 01:41:21 PM PST 24
Finished Feb 29 01:41:22 PM PST 24
Peak memory 216416 kb
Host smart-bb6d3c7f-5bc4-44aa-944f-56a5f1cb6e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894494043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.894494043
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3150708543
Short name T634
Test name
Test status
Simulation time 22884938 ps
CPU time 1 seconds
Started Feb 29 01:41:20 PM PST 24
Finished Feb 29 01:41:21 PM PST 24
Peak memory 215168 kb
Host smart-f50c66fe-bfc8-44e6-a7b3-5a795ebba851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150708543 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3150708543
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.63741432
Short name T520
Test name
Test status
Simulation time 35978609 ps
CPU time 0.94 seconds
Started Feb 29 01:41:28 PM PST 24
Finished Feb 29 01:41:29 PM PST 24
Peak memory 214720 kb
Host smart-a83829d6-e891-4382-b6aa-9df22c733b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63741432 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.63741432
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.4274345310
Short name T159
Test name
Test status
Simulation time 313866289 ps
CPU time 3.52 seconds
Started Feb 29 01:41:21 PM PST 24
Finished Feb 29 01:41:25 PM PST 24
Peak memory 215844 kb
Host smart-8660d546-b9e0-440f-a677-4fdfda23010f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274345310 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.4274345310
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_alert.4136233973
Short name T453
Test name
Test status
Simulation time 81221888 ps
CPU time 1.14 seconds
Started Feb 29 01:41:32 PM PST 24
Finished Feb 29 01:41:33 PM PST 24
Peak memory 215052 kb
Host smart-0edd6d2e-c6e5-4711-8f8a-9c81b21bb8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136233973 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.4136233973
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.3166365954
Short name T388
Test name
Test status
Simulation time 18850341 ps
CPU time 0.98 seconds
Started Feb 29 01:41:34 PM PST 24
Finished Feb 29 01:41:36 PM PST 24
Peak memory 206180 kb
Host smart-6653849f-1c5b-4077-aaa8-fee467dacf37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166365954 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.3166365954
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.771361257
Short name T318
Test name
Test status
Simulation time 38452951 ps
CPU time 0.86 seconds
Started Feb 29 01:41:32 PM PST 24
Finished Feb 29 01:41:32 PM PST 24
Peak memory 214744 kb
Host smart-94cfd148-27ae-4128-bf5c-8bab61464edf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771361257 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.771361257
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.2609063638
Short name T718
Test name
Test status
Simulation time 28731648 ps
CPU time 1.08 seconds
Started Feb 29 01:41:35 PM PST 24
Finished Feb 29 01:41:37 PM PST 24
Peak memory 217112 kb
Host smart-daae8bed-1255-4350-8a42-923edbc58d50
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609063638 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.2609063638
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.696730403
Short name T92
Test name
Test status
Simulation time 31971041 ps
CPU time 0.92 seconds
Started Feb 29 01:41:39 PM PST 24
Finished Feb 29 01:41:41 PM PST 24
Peak memory 217168 kb
Host smart-599faf48-e6fb-4818-909c-1dd897d7abab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696730403 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.696730403
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.1758066862
Short name T376
Test name
Test status
Simulation time 44865633 ps
CPU time 1.12 seconds
Started Feb 29 01:41:34 PM PST 24
Finished Feb 29 01:41:37 PM PST 24
Peak memory 215940 kb
Host smart-72cb0fbc-d117-455b-8060-583559510eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758066862 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.1758066862
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.352887169
Short name T342
Test name
Test status
Simulation time 26457534 ps
CPU time 0.92 seconds
Started Feb 29 01:41:32 PM PST 24
Finished Feb 29 01:41:33 PM PST 24
Peak memory 214972 kb
Host smart-ded0317c-7506-4abd-9838-ac43ffeadd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352887169 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.352887169
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3831448910
Short name T729
Test name
Test status
Simulation time 67133256 ps
CPU time 0.95 seconds
Started Feb 29 01:41:33 PM PST 24
Finished Feb 29 01:41:35 PM PST 24
Peak memory 214676 kb
Host smart-febb2552-cb50-400e-9085-64283f7998db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831448910 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3831448910
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3508874395
Short name T738
Test name
Test status
Simulation time 358554438 ps
CPU time 3.83 seconds
Started Feb 29 01:41:33 PM PST 24
Finished Feb 29 01:41:37 PM PST 24
Peak memory 215992 kb
Host smart-250a120f-d3f2-47cc-ae99-98da3aa9908b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508874395 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3508874395
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3870352729
Short name T446
Test name
Test status
Simulation time 154244425009 ps
CPU time 1402.36 seconds
Started Feb 29 01:41:32 PM PST 24
Finished Feb 29 02:04:54 PM PST 24
Peak memory 224176 kb
Host smart-ab7ef2b1-f52d-4430-b8f0-1deccb141486
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870352729 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3870352729
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.455348182
Short name T249
Test name
Test status
Simulation time 30422119 ps
CPU time 1.27 seconds
Started Feb 29 01:41:36 PM PST 24
Finished Feb 29 01:41:37 PM PST 24
Peak memory 215056 kb
Host smart-17ee7665-333f-48ac-9bec-f558a936e982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455348182 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.455348182
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.2427074163
Short name T313
Test name
Test status
Simulation time 19087239 ps
CPU time 1.01 seconds
Started Feb 29 01:41:33 PM PST 24
Finished Feb 29 01:41:35 PM PST 24
Peak memory 206220 kb
Host smart-877d30f1-c538-4c99-be60-336240fb142d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427074163 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.2427074163
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3003219914
Short name T687
Test name
Test status
Simulation time 19317729 ps
CPU time 0.82 seconds
Started Feb 29 01:41:36 PM PST 24
Finished Feb 29 01:41:38 PM PST 24
Peak memory 214820 kb
Host smart-b80bc759-e234-488f-9a2c-473a90002a81
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003219914 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3003219914
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1601062866
Short name T818
Test name
Test status
Simulation time 32958699 ps
CPU time 1.19 seconds
Started Feb 29 01:41:36 PM PST 24
Finished Feb 29 01:41:37 PM PST 24
Peak memory 216008 kb
Host smart-cf4841cf-ff6a-4ab0-8731-1ca410316d70
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601062866 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1601062866
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2585840363
Short name T81
Test name
Test status
Simulation time 59953717 ps
CPU time 1.03 seconds
Started Feb 29 01:41:34 PM PST 24
Finished Feb 29 01:41:37 PM PST 24
Peak memory 216104 kb
Host smart-a5ef1bea-9241-46db-9779-b0345581d36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585840363 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2585840363
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.1897235202
Short name T12
Test name
Test status
Simulation time 50526075 ps
CPU time 1.61 seconds
Started Feb 29 01:41:32 PM PST 24
Finished Feb 29 01:41:33 PM PST 24
Peak memory 218420 kb
Host smart-9088ce9c-6d5f-45bc-a9dd-aac18b56afe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897235202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.1897235202
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.354290922
Short name T3
Test name
Test status
Simulation time 28852667 ps
CPU time 0.91 seconds
Started Feb 29 01:41:34 PM PST 24
Finished Feb 29 01:41:37 PM PST 24
Peak memory 215000 kb
Host smart-c3e1ff9b-25ad-4111-8524-c0ef9f89adee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354290922 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.354290922
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.764928313
Short name T832
Test name
Test status
Simulation time 26943381 ps
CPU time 0.89 seconds
Started Feb 29 01:41:34 PM PST 24
Finished Feb 29 01:41:37 PM PST 24
Peak memory 214744 kb
Host smart-0aae9023-8881-4a67-a1a5-f6d96eae2f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764928313 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.764928313
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2567486185
Short name T615
Test name
Test status
Simulation time 241469925 ps
CPU time 5.47 seconds
Started Feb 29 01:41:32 PM PST 24
Finished Feb 29 01:41:39 PM PST 24
Peak memory 217328 kb
Host smart-ef2a39a6-6545-4460-a01f-e0319a5a287c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567486185 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2567486185
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.4190647329
Short name T431
Test name
Test status
Simulation time 399475646168 ps
CPU time 2660.39 seconds
Started Feb 29 01:41:34 PM PST 24
Finished Feb 29 02:25:56 PM PST 24
Peak memory 230848 kb
Host smart-20a3ff9a-d77c-42ba-a5a5-c4c5fad8dc7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190647329 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.4190647329
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.281040863
Short name T115
Test name
Test status
Simulation time 86454276 ps
CPU time 1.15 seconds
Started Feb 29 01:41:31 PM PST 24
Finished Feb 29 01:41:33 PM PST 24
Peak memory 215052 kb
Host smart-8a32f567-198a-4937-b05f-ef9388dd4655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281040863 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.281040863
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1415571321
Short name T651
Test name
Test status
Simulation time 65269143 ps
CPU time 0.9 seconds
Started Feb 29 01:41:33 PM PST 24
Finished Feb 29 01:41:35 PM PST 24
Peak memory 206252 kb
Host smart-f1a0432a-6fac-473e-bd1f-4f6a37756b9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415571321 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1415571321
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_err.3198206033
Short name T57
Test name
Test status
Simulation time 85352654 ps
CPU time 1.06 seconds
Started Feb 29 01:41:36 PM PST 24
Finished Feb 29 01:41:38 PM PST 24
Peak memory 229096 kb
Host smart-c3379e81-2702-48e6-b6ff-a25873b4b2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198206033 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3198206033
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.2523068442
Short name T242
Test name
Test status
Simulation time 52144916 ps
CPU time 1.95 seconds
Started Feb 29 01:41:34 PM PST 24
Finished Feb 29 01:41:38 PM PST 24
Peak memory 216160 kb
Host smart-df15c712-d7ab-49de-82d0-f6982a0575bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523068442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.2523068442
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.3098365209
Short name T656
Test name
Test status
Simulation time 22107309 ps
CPU time 1.07 seconds
Started Feb 29 01:41:34 PM PST 24
Finished Feb 29 01:41:36 PM PST 24
Peak memory 215204 kb
Host smart-3274f224-96b1-40aa-8cfd-7eb4d03599e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098365209 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.3098365209
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.3731282502
Short name T315
Test name
Test status
Simulation time 74835138 ps
CPU time 0.85 seconds
Started Feb 29 01:41:33 PM PST 24
Finished Feb 29 01:41:36 PM PST 24
Peak memory 214688 kb
Host smart-1613960e-1827-4c8f-80f8-739c7f1e39ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731282502 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.3731282502
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.61061791
Short name T542
Test name
Test status
Simulation time 548170932 ps
CPU time 3.3 seconds
Started Feb 29 01:41:30 PM PST 24
Finished Feb 29 01:41:34 PM PST 24
Peak memory 215876 kb
Host smart-3ca3b09a-0693-4fcf-8bb8-b24ba5911652
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61061791 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.61061791
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2081935693
Short name T797
Test name
Test status
Simulation time 31655429948 ps
CPU time 718.55 seconds
Started Feb 29 01:41:33 PM PST 24
Finished Feb 29 01:53:32 PM PST 24
Peak memory 217676 kb
Host smart-9e3c1d34-fb52-4ffa-9654-fb1aa979e7e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081935693 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2081935693
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1816854910
Short name T209
Test name
Test status
Simulation time 30748392 ps
CPU time 1.28 seconds
Started Feb 29 01:40:05 PM PST 24
Finished Feb 29 01:40:07 PM PST 24
Peak memory 215076 kb
Host smart-1544e6e5-66b1-48a4-9bda-c6bfe944464a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816854910 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1816854910
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.817672297
Short name T559
Test name
Test status
Simulation time 26123846 ps
CPU time 0.89 seconds
Started Feb 29 01:40:08 PM PST 24
Finished Feb 29 01:40:11 PM PST 24
Peak memory 205888 kb
Host smart-8305efe6-0652-440c-a217-0ce46a4e3531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817672297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.817672297
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2450887431
Short name T107
Test name
Test status
Simulation time 12749508 ps
CPU time 0.9 seconds
Started Feb 29 01:40:05 PM PST 24
Finished Feb 29 01:40:06 PM PST 24
Peak memory 215316 kb
Host smart-d6f2058f-cd47-4e0c-a72f-419daa806069
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450887431 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2450887431
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_err.1988524284
Short name T466
Test name
Test status
Simulation time 78501732 ps
CPU time 0.82 seconds
Started Feb 29 01:40:08 PM PST 24
Finished Feb 29 01:40:11 PM PST 24
Peak memory 217128 kb
Host smart-cf031ce7-d962-4724-a1b0-42f3cd1379da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988524284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.1988524284
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.180390210
Short name T158
Test name
Test status
Simulation time 28840253 ps
CPU time 1.18 seconds
Started Feb 29 01:40:04 PM PST 24
Finished Feb 29 01:40:06 PM PST 24
Peak memory 215976 kb
Host smart-d4547ef5-4b5f-4800-8ef3-4c6c3bf93a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180390210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.180390210
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.299182097
Short name T124
Test name
Test status
Simulation time 23214756 ps
CPU time 0.97 seconds
Started Feb 29 01:40:05 PM PST 24
Finished Feb 29 01:40:06 PM PST 24
Peak memory 215128 kb
Host smart-c7234861-5c30-43ca-80ca-7f12a66d9a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299182097 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.299182097
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.4272998626
Short name T119
Test name
Test status
Simulation time 15364576 ps
CPU time 0.91 seconds
Started Feb 29 01:40:10 PM PST 24
Finished Feb 29 01:40:12 PM PST 24
Peak memory 206540 kb
Host smart-592ccba0-1da7-42de-8e99-904aa39546b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272998626 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.4272998626
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.3958568537
Short name T391
Test name
Test status
Simulation time 30269876 ps
CPU time 0.94 seconds
Started Feb 29 01:40:06 PM PST 24
Finished Feb 29 01:40:08 PM PST 24
Peak memory 214728 kb
Host smart-b7a7ca4e-2bc8-4727-9f75-241e1be3c7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958568537 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.3958568537
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.3528850331
Short name T309
Test name
Test status
Simulation time 310131481 ps
CPU time 6.3 seconds
Started Feb 29 01:40:04 PM PST 24
Finished Feb 29 01:40:11 PM PST 24
Peak memory 215860 kb
Host smart-fc3bd532-74eb-43eb-8188-1b9a299efb45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528850331 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.3528850331
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1503698722
Short name T822
Test name
Test status
Simulation time 46464539945 ps
CPU time 541.14 seconds
Started Feb 29 01:40:05 PM PST 24
Finished Feb 29 01:49:06 PM PST 24
Peak memory 219048 kb
Host smart-b4fd16ad-9121-4b4d-b41c-323fd13fc8d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503698722 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1503698722
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.2043905451
Short name T726
Test name
Test status
Simulation time 65770536 ps
CPU time 1.04 seconds
Started Feb 29 01:41:33 PM PST 24
Finished Feb 29 01:41:35 PM PST 24
Peak memory 219532 kb
Host smart-be521058-decd-4d3b-955f-71c7a2866c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043905451 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.2043905451
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.295344016
Short name T400
Test name
Test status
Simulation time 41752446 ps
CPU time 1.07 seconds
Started Feb 29 01:41:34 PM PST 24
Finished Feb 29 01:41:36 PM PST 24
Peak memory 216164 kb
Host smart-12074054-1375-40f4-8320-5f454638fd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295344016 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.295344016
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.2292881783
Short name T67
Test name
Test status
Simulation time 54297638 ps
CPU time 1.02 seconds
Started Feb 29 01:41:37 PM PST 24
Finished Feb 29 01:41:39 PM PST 24
Peak memory 216036 kb
Host smart-f776863b-9a33-45e0-b3a3-e57841bb7de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292881783 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.2292881783
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1673566270
Short name T485
Test name
Test status
Simulation time 90394125 ps
CPU time 1.46 seconds
Started Feb 29 01:41:32 PM PST 24
Finished Feb 29 01:41:34 PM PST 24
Peak memory 217504 kb
Host smart-cd242845-b72d-4095-849a-4fd327622689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673566270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1673566270
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.2539751030
Short name T457
Test name
Test status
Simulation time 32074370 ps
CPU time 0.86 seconds
Started Feb 29 01:41:34 PM PST 24
Finished Feb 29 01:41:37 PM PST 24
Peak memory 217036 kb
Host smart-bb7d3523-b335-4f20-8b37-b6f2129030c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539751030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2539751030
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.4053145384
Short name T36
Test name
Test status
Simulation time 73528604 ps
CPU time 1.33 seconds
Started Feb 29 01:41:32 PM PST 24
Finished Feb 29 01:41:35 PM PST 24
Peak memory 217528 kb
Host smart-65b1bdbf-082d-4cb6-b7e7-102c8b3e261b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053145384 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.4053145384
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.2058321123
Short name T101
Test name
Test status
Simulation time 21505562 ps
CPU time 1.04 seconds
Started Feb 29 01:41:34 PM PST 24
Finished Feb 29 01:41:36 PM PST 24
Peak memory 217084 kb
Host smart-de469c59-fb41-4085-9827-3fdc0d4fb449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058321123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.2058321123
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3025423331
Short name T272
Test name
Test status
Simulation time 61807793 ps
CPU time 0.97 seconds
Started Feb 29 01:41:37 PM PST 24
Finished Feb 29 01:41:38 PM PST 24
Peak memory 215908 kb
Host smart-ed656827-e479-4a09-a416-a79a9d0e6ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025423331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3025423331
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.857795978
Short name T338
Test name
Test status
Simulation time 43993556 ps
CPU time 0.82 seconds
Started Feb 29 01:41:33 PM PST 24
Finished Feb 29 01:41:35 PM PST 24
Peak memory 217296 kb
Host smart-e6c3c99c-83c1-442f-9522-bfe93808d4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857795978 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.857795978
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.1786498247
Short name T425
Test name
Test status
Simulation time 55177765 ps
CPU time 1.45 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:50 PM PST 24
Peak memory 216160 kb
Host smart-1b95398e-bf83-4d1c-9cf5-401b2ef2aa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786498247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.1786498247
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.869206052
Short name T487
Test name
Test status
Simulation time 19124533 ps
CPU time 1.1 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:49 PM PST 24
Peak memory 217612 kb
Host smart-fb2c0efa-a7c5-41f6-8db9-16bbafa630c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869206052 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.869206052
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.2207615881
Short name T361
Test name
Test status
Simulation time 69368107 ps
CPU time 1.07 seconds
Started Feb 29 01:41:36 PM PST 24
Finished Feb 29 01:41:37 PM PST 24
Peak memory 214716 kb
Host smart-e973f630-43d2-4094-b054-cb3d2cdd468b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207615881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.2207615881
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.1973227871
Short name T42
Test name
Test status
Simulation time 18753070 ps
CPU time 1.1 seconds
Started Feb 29 01:41:35 PM PST 24
Finished Feb 29 01:41:37 PM PST 24
Peak memory 222396 kb
Host smart-36cb607e-f41a-44ba-85b1-ccb0a2316f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973227871 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1973227871
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.3165721618
Short name T403
Test name
Test status
Simulation time 82979669 ps
CPU time 1.13 seconds
Started Feb 29 01:41:35 PM PST 24
Finished Feb 29 01:41:38 PM PST 24
Peak memory 216056 kb
Host smart-c15b8d42-7f89-4466-badd-5df8485cc9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165721618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.3165721618
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.2383761957
Short name T468
Test name
Test status
Simulation time 32891443 ps
CPU time 1.12 seconds
Started Feb 29 01:41:33 PM PST 24
Finished Feb 29 01:41:35 PM PST 24
Peak memory 217204 kb
Host smart-de4eef6a-1823-45bd-8d7e-efab205da1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383761957 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2383761957
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.939615709
Short name T589
Test name
Test status
Simulation time 163785277 ps
CPU time 3.33 seconds
Started Feb 29 01:41:36 PM PST 24
Finished Feb 29 01:41:40 PM PST 24
Peak memory 217428 kb
Host smart-689dd4ad-fe34-4335-b094-93000fe8095f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939615709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.939615709
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.4212746511
Short name T694
Test name
Test status
Simulation time 20902976 ps
CPU time 0.93 seconds
Started Feb 29 01:41:35 PM PST 24
Finished Feb 29 01:41:38 PM PST 24
Peak memory 217124 kb
Host smart-eaa77894-9845-4486-9f20-268080249205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212746511 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.4212746511
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.2745108673
Short name T711
Test name
Test status
Simulation time 33896246 ps
CPU time 1.34 seconds
Started Feb 29 01:41:33 PM PST 24
Finished Feb 29 01:41:37 PM PST 24
Peak memory 217212 kb
Host smart-e1139092-5ff0-43d6-93f5-b36c1cbfbecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745108673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.2745108673
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.1716193197
Short name T638
Test name
Test status
Simulation time 19482285 ps
CPU time 1.02 seconds
Started Feb 29 01:41:38 PM PST 24
Finished Feb 29 01:41:40 PM PST 24
Peak memory 217004 kb
Host smart-997d519f-4836-4184-8d0b-f5913b841e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716193197 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.1716193197
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.4175735717
Short name T296
Test name
Test status
Simulation time 40518882 ps
CPU time 1.42 seconds
Started Feb 29 01:41:34 PM PST 24
Finished Feb 29 01:41:36 PM PST 24
Peak memory 218000 kb
Host smart-3021fa67-f96b-428f-8fa3-760062b1f47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175735717 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.4175735717
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert_test.35346916
Short name T584
Test name
Test status
Simulation time 33924173 ps
CPU time 0.91 seconds
Started Feb 29 01:40:08 PM PST 24
Finished Feb 29 01:40:11 PM PST 24
Peak memory 206212 kb
Host smart-1485aeec-6bef-4b34-b5b5-c1903a3b11be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35346916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.35346916
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3141906194
Short name T137
Test name
Test status
Simulation time 37245317 ps
CPU time 0.83 seconds
Started Feb 29 01:40:09 PM PST 24
Finished Feb 29 01:40:11 PM PST 24
Peak memory 215160 kb
Host smart-406816fe-8f09-4725-bade-c234e0e4233e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141906194 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3141906194
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2570238467
Short name T695
Test name
Test status
Simulation time 27368244 ps
CPU time 1.06 seconds
Started Feb 29 01:40:07 PM PST 24
Finished Feb 29 01:40:08 PM PST 24
Peak memory 217180 kb
Host smart-48f2deed-b3aa-4d0e-b665-5b34c7723e9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570238467 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2570238467
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.1638257644
Short name T52
Test name
Test status
Simulation time 19437516 ps
CPU time 0.99 seconds
Started Feb 29 01:40:05 PM PST 24
Finished Feb 29 01:40:07 PM PST 24
Peak memory 217320 kb
Host smart-73e0c60a-5ff1-4a4b-85b1-a89dde75b69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638257644 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1638257644
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3704699921
Short name T130
Test name
Test status
Simulation time 50264009 ps
CPU time 2.11 seconds
Started Feb 29 01:40:06 PM PST 24
Finished Feb 29 01:40:09 PM PST 24
Peak memory 216372 kb
Host smart-b3287a58-3a31-47d2-a66f-f69fc24c701a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704699921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3704699921
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.2576133800
Short name T720
Test name
Test status
Simulation time 42395694 ps
CPU time 0.91 seconds
Started Feb 29 01:40:07 PM PST 24
Finished Feb 29 01:40:08 PM PST 24
Peak memory 214800 kb
Host smart-4c3f5d86-61a0-4a1c-b525-4eeb00f8ff21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576133800 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.2576133800
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.47760281
Short name T266
Test name
Test status
Simulation time 31774078 ps
CPU time 0.84 seconds
Started Feb 29 01:40:08 PM PST 24
Finished Feb 29 01:40:09 PM PST 24
Peak memory 206692 kb
Host smart-7254e90f-5f74-4b5d-b311-bc4cb4a47698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47760281 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.47760281
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.109041858
Short name T302
Test name
Test status
Simulation time 15730910 ps
CPU time 0.98 seconds
Started Feb 29 01:40:06 PM PST 24
Finished Feb 29 01:40:08 PM PST 24
Peak memory 206496 kb
Host smart-1867d42b-82ad-4844-abcb-163b2e1a5bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109041858 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.109041858
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.97322553
Short name T196
Test name
Test status
Simulation time 726973554 ps
CPU time 3.99 seconds
Started Feb 29 01:40:07 PM PST 24
Finished Feb 29 01:40:11 PM PST 24
Peak memory 215932 kb
Host smart-53928d97-0624-4a6a-9ac8-3dd8cb02409d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97322553 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.97322553
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3052436367
Short name T200
Test name
Test status
Simulation time 1184375577172 ps
CPU time 4215.09 seconds
Started Feb 29 01:40:07 PM PST 24
Finished Feb 29 02:50:23 PM PST 24
Peak memory 234088 kb
Host smart-9eb9ab14-4810-4781-82de-77b62cfb9ef4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052436367 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3052436367
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.3436620783
Short name T489
Test name
Test status
Simulation time 23660309 ps
CPU time 0.93 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:49 PM PST 24
Peak memory 217156 kb
Host smart-a5130c48-a21f-480b-8120-e1375b983460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436620783 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3436620783
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.2967640432
Short name T546
Test name
Test status
Simulation time 61211891 ps
CPU time 1.12 seconds
Started Feb 29 01:41:34 PM PST 24
Finished Feb 29 01:41:36 PM PST 24
Peak memory 217604 kb
Host smart-f7b2190d-3637-4e2a-acc5-d21475e2edfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967640432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2967640432
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.370814441
Short name T821
Test name
Test status
Simulation time 31136959 ps
CPU time 1.04 seconds
Started Feb 29 01:41:34 PM PST 24
Finished Feb 29 01:41:37 PM PST 24
Peak memory 229332 kb
Host smart-129aa20e-7e1e-4a23-80ae-b8c8262c1b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370814441 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.370814441
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1162837855
Short name T540
Test name
Test status
Simulation time 116126687 ps
CPU time 1.32 seconds
Started Feb 29 01:41:35 PM PST 24
Finished Feb 29 01:41:37 PM PST 24
Peak memory 218332 kb
Host smart-7e2cf392-3d9c-4b1a-a781-f69514eda0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162837855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1162837855
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.658028904
Short name T132
Test name
Test status
Simulation time 34929124 ps
CPU time 0.91 seconds
Started Feb 29 01:41:37 PM PST 24
Finished Feb 29 01:41:39 PM PST 24
Peak memory 217264 kb
Host smart-7fca5264-02cd-4a46-af2c-0e4f53b9c2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658028904 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.658028904
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1803095555
Short name T790
Test name
Test status
Simulation time 57308227 ps
CPU time 1.51 seconds
Started Feb 29 01:41:34 PM PST 24
Finished Feb 29 01:41:37 PM PST 24
Peak memory 217404 kb
Host smart-92efc610-9139-41cf-a28e-37089d3816a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803095555 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1803095555
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.1348818612
Short name T379
Test name
Test status
Simulation time 27455253 ps
CPU time 0.93 seconds
Started Feb 29 01:41:38 PM PST 24
Finished Feb 29 01:41:40 PM PST 24
Peak memory 221908 kb
Host smart-57dda43f-ab3d-427b-9575-521a6202376e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348818612 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1348818612
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.571632654
Short name T686
Test name
Test status
Simulation time 39494133 ps
CPU time 1.41 seconds
Started Feb 29 01:41:43 PM PST 24
Finished Feb 29 01:41:44 PM PST 24
Peak memory 217888 kb
Host smart-8c3c11df-1c61-4341-a862-36955aad3f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571632654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.571632654
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.4002103464
Short name T411
Test name
Test status
Simulation time 63761652 ps
CPU time 1.04 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:49 PM PST 24
Peak memory 216100 kb
Host smart-0b2ef7bc-59ba-4aea-a9d5-c6f34445e914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002103464 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.4002103464
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/65.edn_err.301978084
Short name T77
Test name
Test status
Simulation time 23286608 ps
CPU time 1.24 seconds
Started Feb 29 01:41:36 PM PST 24
Finished Feb 29 01:41:39 PM PST 24
Peak memory 215964 kb
Host smart-7b0c42c2-1e09-44ff-bc85-aebb0e7d7c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301978084 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.301978084
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1643024740
Short name T25
Test name
Test status
Simulation time 134393746 ps
CPU time 1.05 seconds
Started Feb 29 01:41:36 PM PST 24
Finished Feb 29 01:41:39 PM PST 24
Peak memory 215816 kb
Host smart-63391f6b-53a5-4b7b-acdf-2e0ab785db43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643024740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1643024740
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.4245158608
Short name T777
Test name
Test status
Simulation time 35460390 ps
CPU time 1.13 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:49 PM PST 24
Peak memory 218548 kb
Host smart-14181cec-cb21-4f51-b052-281f45bdf52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245158608 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.4245158608
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1206351640
Short name T298
Test name
Test status
Simulation time 74458193 ps
CPU time 2.62 seconds
Started Feb 29 01:41:26 PM PST 24
Finished Feb 29 01:41:29 PM PST 24
Peak memory 219044 kb
Host smart-438584bd-66e0-4afe-8f85-47a583a1bb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206351640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1206351640
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.971910298
Short name T484
Test name
Test status
Simulation time 29452636 ps
CPU time 1.4 seconds
Started Feb 29 01:41:36 PM PST 24
Finished Feb 29 01:41:38 PM PST 24
Peak memory 230116 kb
Host smart-9669c099-cecf-4382-b404-dea9372be463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971910298 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.971910298
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.4007982153
Short name T325
Test name
Test status
Simulation time 239213675 ps
CPU time 1.32 seconds
Started Feb 29 01:41:36 PM PST 24
Finished Feb 29 01:41:39 PM PST 24
Peak memory 215984 kb
Host smart-490889be-49f4-49b0-a77c-756f2293a63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007982153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.4007982153
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1925361083
Short name T68
Test name
Test status
Simulation time 33966115 ps
CPU time 0.98 seconds
Started Feb 29 01:41:41 PM PST 24
Finished Feb 29 01:41:42 PM PST 24
Peak memory 218508 kb
Host smart-d5fb9a88-4d8d-4a0f-a1c6-00e8893f5165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925361083 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1925361083
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2657930797
Short name T277
Test name
Test status
Simulation time 46587475 ps
CPU time 1.5 seconds
Started Feb 29 01:41:38 PM PST 24
Finished Feb 29 01:41:41 PM PST 24
Peak memory 217216 kb
Host smart-448a5cd8-d085-43a1-b4bd-a2ea413ef825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657930797 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2657930797
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.2578448418
Short name T661
Test name
Test status
Simulation time 82623486 ps
CPU time 0.84 seconds
Started Feb 29 01:41:40 PM PST 24
Finished Feb 29 01:41:41 PM PST 24
Peak memory 217128 kb
Host smart-761b5dc7-ebbe-422a-9ab6-667bae88a1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578448418 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2578448418
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1432214174
Short name T754
Test name
Test status
Simulation time 324934794 ps
CPU time 4.53 seconds
Started Feb 29 01:41:37 PM PST 24
Finished Feb 29 01:41:43 PM PST 24
Peak memory 217388 kb
Host smart-f08744f1-c017-45f3-917d-9139b2c3c139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432214174 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1432214174
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1019277128
Short name T541
Test name
Test status
Simulation time 56570783 ps
CPU time 1.18 seconds
Started Feb 29 01:40:09 PM PST 24
Finished Feb 29 01:40:12 PM PST 24
Peak memory 215112 kb
Host smart-f3f4cef6-a5c4-441a-b19e-d75767657372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019277128 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1019277128
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.951366557
Short name T481
Test name
Test status
Simulation time 20552790 ps
CPU time 0.86 seconds
Started Feb 29 01:40:08 PM PST 24
Finished Feb 29 01:40:10 PM PST 24
Peak memory 205140 kb
Host smart-a2c566ef-08db-4e8b-bbfb-ec89a0f61f3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951366557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.951366557
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.2244085971
Short name T89
Test name
Test status
Simulation time 104340373 ps
CPU time 0.9 seconds
Started Feb 29 01:40:07 PM PST 24
Finished Feb 29 01:40:08 PM PST 24
Peak memory 214852 kb
Host smart-81143b7d-4295-4096-a1f2-a9c18a180df4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244085971 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.2244085971
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.3650418370
Short name T147
Test name
Test status
Simulation time 338144771 ps
CPU time 1.15 seconds
Started Feb 29 01:40:05 PM PST 24
Finished Feb 29 01:40:06 PM PST 24
Peak memory 215708 kb
Host smart-07a7c34a-ff08-44e7-8ebd-a8da3500c7ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650418370 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.3650418370
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.3395276313
Short name T743
Test name
Test status
Simulation time 36190208 ps
CPU time 1.03 seconds
Started Feb 29 01:40:06 PM PST 24
Finished Feb 29 01:40:08 PM PST 24
Peak memory 218612 kb
Host smart-614cf832-f548-4b6d-a1c8-d562eb9a0e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395276313 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3395276313
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.1377124570
Short name T605
Test name
Test status
Simulation time 457605152 ps
CPU time 4.72 seconds
Started Feb 29 01:40:06 PM PST 24
Finished Feb 29 01:40:11 PM PST 24
Peak memory 219032 kb
Host smart-7af5c61a-c8da-4139-81d3-ff0372da7b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377124570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.1377124570
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2061748836
Short name T635
Test name
Test status
Simulation time 21081097 ps
CPU time 1.14 seconds
Started Feb 29 01:40:12 PM PST 24
Finished Feb 29 01:40:13 PM PST 24
Peak memory 231948 kb
Host smart-53e85b05-0d8a-4752-8186-c04c09b07ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061748836 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2061748836
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3640877117
Short name T120
Test name
Test status
Simulation time 18157914 ps
CPU time 1.04 seconds
Started Feb 29 01:40:09 PM PST 24
Finished Feb 29 01:40:12 PM PST 24
Peak memory 206604 kb
Host smart-cda0618e-f549-488c-baf7-92ef5a349a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640877117 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3640877117
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.4157159883
Short name T351
Test name
Test status
Simulation time 165997561 ps
CPU time 1.04 seconds
Started Feb 29 01:40:08 PM PST 24
Finished Feb 29 01:40:09 PM PST 24
Peak memory 214688 kb
Host smart-ce931bb5-81af-4730-a19f-2804592d749d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157159883 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.4157159883
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1103196198
Short name T358
Test name
Test status
Simulation time 310140067 ps
CPU time 5.97 seconds
Started Feb 29 01:40:08 PM PST 24
Finished Feb 29 01:40:14 PM PST 24
Peak memory 215756 kb
Host smart-5ce475b9-ab62-4b07-a4a4-e73e83b66384
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103196198 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1103196198
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1496221448
Short name T626
Test name
Test status
Simulation time 130238833635 ps
CPU time 757.02 seconds
Started Feb 29 01:40:12 PM PST 24
Finished Feb 29 01:52:49 PM PST 24
Peak memory 220980 kb
Host smart-4ba2bb2d-3095-4eaa-870e-e7c5dfecf32f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496221448 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1496221448
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.1471145963
Short name T815
Test name
Test status
Simulation time 18750478 ps
CPU time 1.08 seconds
Started Feb 29 01:41:43 PM PST 24
Finished Feb 29 01:41:44 PM PST 24
Peak memory 217600 kb
Host smart-da8bbb1a-7bda-4f57-bc0e-ec045ff3e7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471145963 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1471145963
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1728226760
Short name T335
Test name
Test status
Simulation time 32214784 ps
CPU time 1.29 seconds
Started Feb 29 01:41:43 PM PST 24
Finished Feb 29 01:41:44 PM PST 24
Peak memory 216040 kb
Host smart-2a381aa7-e94d-4cb0-8424-14ba46a8990e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728226760 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1728226760
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.2343967564
Short name T776
Test name
Test status
Simulation time 34821366 ps
CPU time 1.14 seconds
Started Feb 29 01:41:41 PM PST 24
Finished Feb 29 01:41:42 PM PST 24
Peak memory 229184 kb
Host smart-f05f65d5-1502-4818-b909-524097df4ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343967564 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.2343967564
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2377792404
Short name T20
Test name
Test status
Simulation time 30918458 ps
CPU time 1.26 seconds
Started Feb 29 01:41:38 PM PST 24
Finished Feb 29 01:41:40 PM PST 24
Peak memory 217136 kb
Host smart-827d53c5-08b9-4fc6-98c7-5c9a6e39173e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377792404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2377792404
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.3991368719
Short name T731
Test name
Test status
Simulation time 35278784 ps
CPU time 0.93 seconds
Started Feb 29 01:41:42 PM PST 24
Finished Feb 29 01:41:43 PM PST 24
Peak memory 214540 kb
Host smart-866d574a-bcb2-444f-88d2-620e83010036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991368719 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3991368719
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2138057202
Short name T710
Test name
Test status
Simulation time 50834715 ps
CPU time 1.06 seconds
Started Feb 29 01:41:40 PM PST 24
Finished Feb 29 01:41:41 PM PST 24
Peak memory 216076 kb
Host smart-962b3670-8478-4415-9be2-f024ff3f10b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138057202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2138057202
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.4223212436
Short name T816
Test name
Test status
Simulation time 27944028 ps
CPU time 0.93 seconds
Started Feb 29 01:41:41 PM PST 24
Finished Feb 29 01:41:42 PM PST 24
Peak memory 222304 kb
Host smart-745b9244-29c3-40f8-ba66-5949e537edfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223212436 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.4223212436
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2906813535
Short name T374
Test name
Test status
Simulation time 66345774 ps
CPU time 1.36 seconds
Started Feb 29 01:41:40 PM PST 24
Finished Feb 29 01:41:42 PM PST 24
Peak memory 217676 kb
Host smart-4f3de881-c66a-4bd1-9501-40edadf7d61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906813535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2906813535
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.2586284595
Short name T719
Test name
Test status
Simulation time 21208505 ps
CPU time 0.89 seconds
Started Feb 29 01:41:41 PM PST 24
Finished Feb 29 01:41:42 PM PST 24
Peak memory 217080 kb
Host smart-f3064a20-86cc-4318-9207-37badbb8800c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586284595 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2586284595
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.39224182
Short name T320
Test name
Test status
Simulation time 67114434 ps
CPU time 1.05 seconds
Started Feb 29 01:41:37 PM PST 24
Finished Feb 29 01:41:39 PM PST 24
Peak memory 215888 kb
Host smart-2a49d559-7793-4580-9be7-60898f688db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39224182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.39224182
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.3450848333
Short name T416
Test name
Test status
Simulation time 29600803 ps
CPU time 0.89 seconds
Started Feb 29 01:41:45 PM PST 24
Finished Feb 29 01:41:46 PM PST 24
Peak memory 217368 kb
Host smart-601991b2-43e2-402a-8bed-1ee54da25edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450848333 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3450848333
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.2519902643
Short name T381
Test name
Test status
Simulation time 150235875 ps
CPU time 1.08 seconds
Started Feb 29 01:41:44 PM PST 24
Finished Feb 29 01:41:45 PM PST 24
Peak memory 216064 kb
Host smart-b4b64292-224d-4d80-bdde-6699be269bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519902643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.2519902643
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3995274985
Short name T102
Test name
Test status
Simulation time 19444788 ps
CPU time 1.04 seconds
Started Feb 29 01:41:46 PM PST 24
Finished Feb 29 01:41:47 PM PST 24
Peak memory 217368 kb
Host smart-a4af9efd-ffb1-4b1d-ba4b-6482b0c4fefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995274985 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3995274985
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.219986129
Short name T461
Test name
Test status
Simulation time 38983279 ps
CPU time 1.67 seconds
Started Feb 29 01:41:45 PM PST 24
Finished Feb 29 01:41:47 PM PST 24
Peak memory 216072 kb
Host smart-4b39fcf3-2e14-4dd0-9c88-d81382fe1ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219986129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.219986129
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.1038230726
Short name T506
Test name
Test status
Simulation time 18833183 ps
CPU time 1.02 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:49 PM PST 24
Peak memory 217180 kb
Host smart-995f069e-e0c9-4f8d-a7b4-def6d8474774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038230726 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1038230726
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.288817974
Short name T681
Test name
Test status
Simulation time 35496694 ps
CPU time 1.57 seconds
Started Feb 29 01:41:44 PM PST 24
Finished Feb 29 01:41:46 PM PST 24
Peak memory 217148 kb
Host smart-7b12a201-0f5b-4034-8f7e-3d98b99b793a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288817974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.288817974
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.1220273027
Short name T140
Test name
Test status
Simulation time 74205304 ps
CPU time 1.12 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:49 PM PST 24
Peak memory 218764 kb
Host smart-7248f141-aa9f-40ed-9fa5-79cac65caa8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220273027 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.1220273027
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.791782381
Short name T283
Test name
Test status
Simulation time 36335329 ps
CPU time 1.4 seconds
Started Feb 29 01:41:46 PM PST 24
Finished Feb 29 01:41:47 PM PST 24
Peak memory 217352 kb
Host smart-3fdc7ef7-1cc4-4898-bf00-77eb98433274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791782381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.791782381
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.302364416
Short name T814
Test name
Test status
Simulation time 25133107 ps
CPU time 0.97 seconds
Started Feb 29 01:41:49 PM PST 24
Finished Feb 29 01:41:50 PM PST 24
Peak memory 217444 kb
Host smart-602e3227-69ec-457a-bf0c-bb02e911ceb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302364416 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.302364416
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3362655223
Short name T319
Test name
Test status
Simulation time 38177027 ps
CPU time 1.42 seconds
Started Feb 29 01:41:47 PM PST 24
Finished Feb 29 01:41:49 PM PST 24
Peak memory 217060 kb
Host smart-500843a8-becc-4cf9-bf70-d528b6df23ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362655223 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3362655223
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.287911806
Short name T47
Test name
Test status
Simulation time 91337850 ps
CPU time 1.19 seconds
Started Feb 29 01:40:18 PM PST 24
Finished Feb 29 01:40:19 PM PST 24
Peak memory 215048 kb
Host smart-f05e3579-3185-43a6-a665-f4f236421e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287911806 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.287911806
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.2508387784
Short name T49
Test name
Test status
Simulation time 24877176 ps
CPU time 1.04 seconds
Started Feb 29 01:40:18 PM PST 24
Finished Feb 29 01:40:19 PM PST 24
Peak memory 206272 kb
Host smart-9b460f82-c74f-416d-8556-a005a080d10e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508387784 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.2508387784
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3579650560
Short name T574
Test name
Test status
Simulation time 16579242 ps
CPU time 0.8 seconds
Started Feb 29 01:40:15 PM PST 24
Finished Feb 29 01:40:16 PM PST 24
Peak memory 214836 kb
Host smart-d619b01d-6ab8-4cc0-8bcf-d58a47626bd5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579650560 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3579650560
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_genbits.3554865692
Short name T32
Test name
Test status
Simulation time 74896660 ps
CPU time 1.37 seconds
Started Feb 29 01:40:15 PM PST 24
Finished Feb 29 01:40:17 PM PST 24
Peak memory 217248 kb
Host smart-079d239e-6749-4e50-ad0a-78e4820b3e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554865692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3554865692
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_regwen.4096002211
Short name T543
Test name
Test status
Simulation time 53993764 ps
CPU time 0.96 seconds
Started Feb 29 01:40:18 PM PST 24
Finished Feb 29 01:40:19 PM PST 24
Peak memory 206584 kb
Host smart-f922656b-6dbc-49ca-a39e-12e067d33f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096002211 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.4096002211
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.2767515872
Short name T306
Test name
Test status
Simulation time 14730044 ps
CPU time 0.9 seconds
Started Feb 29 01:40:08 PM PST 24
Finished Feb 29 01:40:09 PM PST 24
Peak memory 214736 kb
Host smart-44e3511c-7546-4c47-9512-e3ab2f8e5e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767515872 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.2767515872
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.4190794003
Short name T644
Test name
Test status
Simulation time 523447351 ps
CPU time 3.05 seconds
Started Feb 29 01:40:16 PM PST 24
Finished Feb 29 01:40:19 PM PST 24
Peak memory 216028 kb
Host smart-25ad3c99-15f1-4975-98e6-cc87ad104b9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190794003 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.4190794003
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.2861172519
Short name T761
Test name
Test status
Simulation time 41717832547 ps
CPU time 454.99 seconds
Started Feb 29 01:40:16 PM PST 24
Finished Feb 29 01:47:51 PM PST 24
Peak memory 217052 kb
Host smart-57655d3a-23d4-482e-85f9-e38bc564e9d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861172519 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.2861172519
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.1023929742
Short name T61
Test name
Test status
Simulation time 32434680 ps
CPU time 0.93 seconds
Started Feb 29 01:41:47 PM PST 24
Finished Feb 29 01:41:48 PM PST 24
Peak memory 218624 kb
Host smart-a95f9f38-3e54-4941-a585-8a36db35fc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023929742 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.1023929742
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3911128776
Short name T593
Test name
Test status
Simulation time 88870896 ps
CPU time 1.2 seconds
Started Feb 29 01:41:49 PM PST 24
Finished Feb 29 01:41:51 PM PST 24
Peak memory 216272 kb
Host smart-fe81f2d6-0bec-404b-8023-2dcfe3707057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911128776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3911128776
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.2992948943
Short name T547
Test name
Test status
Simulation time 64414412 ps
CPU time 1.16 seconds
Started Feb 29 01:41:46 PM PST 24
Finished Feb 29 01:41:47 PM PST 24
Peak memory 231680 kb
Host smart-67feb65a-80fb-496d-8bf7-62e4a6a390bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992948943 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.2992948943
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.3977857011
Short name T612
Test name
Test status
Simulation time 50742615 ps
CPU time 1.15 seconds
Started Feb 29 01:41:47 PM PST 24
Finished Feb 29 01:41:48 PM PST 24
Peak memory 217120 kb
Host smart-865b1fcd-20e9-4ac0-a2ad-cf87c5273f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977857011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.3977857011
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.1695560363
Short name T601
Test name
Test status
Simulation time 63437176 ps
CPU time 0.92 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:49 PM PST 24
Peak memory 222140 kb
Host smart-dd0fb309-ed88-4079-9fce-93f973c335af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695560363 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1695560363
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.4271032067
Short name T554
Test name
Test status
Simulation time 221967911 ps
CPU time 1.32 seconds
Started Feb 29 01:41:53 PM PST 24
Finished Feb 29 01:41:54 PM PST 24
Peak memory 216180 kb
Host smart-a7698501-c9ef-4855-956f-a2ef63ddc80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271032067 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.4271032067
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.878861935
Short name T778
Test name
Test status
Simulation time 74132567 ps
CPU time 1.04 seconds
Started Feb 29 01:41:50 PM PST 24
Finished Feb 29 01:41:51 PM PST 24
Peak memory 218396 kb
Host smart-e5294dd2-22f8-4332-a684-423f499b8529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878861935 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.878861935
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.711419387
Short name T364
Test name
Test status
Simulation time 62154861 ps
CPU time 1.06 seconds
Started Feb 29 01:41:55 PM PST 24
Finished Feb 29 01:41:56 PM PST 24
Peak memory 216016 kb
Host smart-2f721b9b-e447-41ac-8f75-10a902d4ed41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711419387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.711419387
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.3239019403
Short name T521
Test name
Test status
Simulation time 46166621 ps
CPU time 1 seconds
Started Feb 29 01:41:44 PM PST 24
Finished Feb 29 01:41:45 PM PST 24
Peak memory 229116 kb
Host smart-2d4ae8be-083d-437a-b27b-bcffc340c5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239019403 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.3239019403
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.79855244
Short name T556
Test name
Test status
Simulation time 36996806 ps
CPU time 1.28 seconds
Started Feb 29 01:41:49 PM PST 24
Finished Feb 29 01:41:50 PM PST 24
Peak memory 215952 kb
Host smart-668e8331-22bf-4fe2-ae05-6acc99f8a4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79855244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.79855244
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.4057891745
Short name T110
Test name
Test status
Simulation time 19229261 ps
CPU time 1.18 seconds
Started Feb 29 01:41:44 PM PST 24
Finished Feb 29 01:41:45 PM PST 24
Peak memory 222348 kb
Host smart-a8a883e9-2d7f-4474-8d01-b84e5f98cd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057891745 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.4057891745
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.2491602163
Short name T819
Test name
Test status
Simulation time 48423831 ps
CPU time 1.71 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:50 PM PST 24
Peak memory 217060 kb
Host smart-f7dd96b3-309a-4091-8c2e-508f7714625f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491602163 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.2491602163
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.658488870
Short name T152
Test name
Test status
Simulation time 28888378 ps
CPU time 1.25 seconds
Started Feb 29 01:41:44 PM PST 24
Finished Feb 29 01:41:45 PM PST 24
Peak memory 218760 kb
Host smart-3e4ed165-e553-42f4-b3c3-b5ca12efc493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658488870 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.658488870
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.1421053899
Short name T479
Test name
Test status
Simulation time 81036736 ps
CPU time 2.66 seconds
Started Feb 29 01:41:49 PM PST 24
Finished Feb 29 01:41:52 PM PST 24
Peak memory 218948 kb
Host smart-f56d6104-25dc-4f08-8857-4e1d35cc0f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421053899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.1421053899
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1492386056
Short name T78
Test name
Test status
Simulation time 24962733 ps
CPU time 1.01 seconds
Started Feb 29 01:41:49 PM PST 24
Finished Feb 29 01:41:51 PM PST 24
Peak memory 229100 kb
Host smart-4e5bef55-d2b3-411f-99c1-6d4c0226fbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492386056 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1492386056
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.681940910
Short name T426
Test name
Test status
Simulation time 153349503 ps
CPU time 1.01 seconds
Started Feb 29 01:41:53 PM PST 24
Finished Feb 29 01:41:54 PM PST 24
Peak memory 215936 kb
Host smart-82bfc8e9-7eff-46c5-97e4-ce1f7a66e55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681940910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.681940910
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.3681932024
Short name T63
Test name
Test status
Simulation time 27056670 ps
CPU time 1.23 seconds
Started Feb 29 01:41:50 PM PST 24
Finished Feb 29 01:41:51 PM PST 24
Peak memory 219536 kb
Host smart-4b30f3e9-04d8-42cc-88bc-7d763de5c8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681932024 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3681932024
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.786095741
Short name T253
Test name
Test status
Simulation time 206100524 ps
CPU time 1.1 seconds
Started Feb 29 01:41:50 PM PST 24
Finished Feb 29 01:41:51 PM PST 24
Peak memory 215972 kb
Host smart-be257319-0cb5-4f9e-8db9-fc0c41367557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786095741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.786095741
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.3981531337
Short name T663
Test name
Test status
Simulation time 23829227 ps
CPU time 0.93 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:49 PM PST 24
Peak memory 217192 kb
Host smart-9ecfe012-e91e-43ce-beec-f55f7e44f40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981531337 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.3981531337
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.1640363518
Short name T746
Test name
Test status
Simulation time 59549671 ps
CPU time 1.73 seconds
Started Feb 29 01:41:55 PM PST 24
Finished Feb 29 01:41:57 PM PST 24
Peak memory 216016 kb
Host smart-256fe544-ebb5-4a7f-b290-8dac3bec9ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640363518 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.1640363518
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.128242616
Short name T444
Test name
Test status
Simulation time 86020279 ps
CPU time 1.37 seconds
Started Feb 29 01:40:19 PM PST 24
Finished Feb 29 01:40:20 PM PST 24
Peak memory 215108 kb
Host smart-a66a0a9a-2af4-4872-9be2-246d452b434a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128242616 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.128242616
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.4250068266
Short name T805
Test name
Test status
Simulation time 14251428 ps
CPU time 0.93 seconds
Started Feb 29 01:40:17 PM PST 24
Finished Feb 29 01:40:18 PM PST 24
Peak memory 205400 kb
Host smart-a2b20ada-8ce4-4725-b3d2-02b796d08df3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250068266 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.4250068266
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.3545732450
Short name T180
Test name
Test status
Simulation time 31901047 ps
CPU time 0.86 seconds
Started Feb 29 01:40:16 PM PST 24
Finished Feb 29 01:40:17 PM PST 24
Peak memory 215272 kb
Host smart-b0542a4e-8f1b-43a8-8cec-aecb019dc729
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545732450 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.3545732450
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.4128208672
Short name T759
Test name
Test status
Simulation time 69706830 ps
CPU time 1.19 seconds
Started Feb 29 01:40:26 PM PST 24
Finished Feb 29 01:40:28 PM PST 24
Peak memory 215836 kb
Host smart-56b4e53e-2ca8-4c26-a511-0f0c5efe25bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128208672 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.4128208672
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.639101906
Short name T75
Test name
Test status
Simulation time 96856691 ps
CPU time 1.06 seconds
Started Feb 29 01:40:24 PM PST 24
Finished Feb 29 01:40:25 PM PST 24
Peak memory 222564 kb
Host smart-9368cf98-13f2-4c5c-99b5-e396a9fee59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639101906 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.639101906
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.3947663828
Short name T561
Test name
Test status
Simulation time 34382494 ps
CPU time 1.33 seconds
Started Feb 29 01:40:16 PM PST 24
Finished Feb 29 01:40:18 PM PST 24
Peak memory 217216 kb
Host smart-b20bdc76-6057-443e-a100-a6fd801d4936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947663828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3947663828
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2082649537
Short name T675
Test name
Test status
Simulation time 31653610 ps
CPU time 0.93 seconds
Started Feb 29 01:40:18 PM PST 24
Finished Feb 29 01:40:19 PM PST 24
Peak memory 214804 kb
Host smart-ac317631-9e76-4f80-9e0b-f0cbd63a953d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082649537 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2082649537
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_smoke.944292560
Short name T303
Test name
Test status
Simulation time 18775678 ps
CPU time 0.97 seconds
Started Feb 29 01:40:27 PM PST 24
Finished Feb 29 01:40:28 PM PST 24
Peak memory 214708 kb
Host smart-5c79536d-2045-485e-a15f-d20588b0f9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944292560 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.944292560
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1304250074
Short name T739
Test name
Test status
Simulation time 108995311 ps
CPU time 1.32 seconds
Started Feb 29 01:40:16 PM PST 24
Finished Feb 29 01:40:18 PM PST 24
Peak memory 215872 kb
Host smart-50389467-9b71-4567-b31a-17e5b5821a25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304250074 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1304250074
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3483687109
Short name T834
Test name
Test status
Simulation time 355093604328 ps
CPU time 828.45 seconds
Started Feb 29 01:40:16 PM PST 24
Finished Feb 29 01:54:05 PM PST 24
Peak memory 220204 kb
Host smart-ee791916-2d6c-4558-b116-ad19fc8042a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483687109 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3483687109
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.1761380195
Short name T13
Test name
Test status
Simulation time 27229241 ps
CPU time 0.98 seconds
Started Feb 29 01:41:47 PM PST 24
Finished Feb 29 01:41:48 PM PST 24
Peak memory 222360 kb
Host smart-a558d375-22b8-420f-a65b-81c92c998b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761380195 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.1761380195
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.1013740533
Short name T392
Test name
Test status
Simulation time 190963172 ps
CPU time 2.64 seconds
Started Feb 29 01:41:50 PM PST 24
Finished Feb 29 01:41:53 PM PST 24
Peak memory 217460 kb
Host smart-35541db7-5db7-4322-9474-c06de2dc33e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013740533 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.1013740533
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.748444992
Short name T646
Test name
Test status
Simulation time 31041598 ps
CPU time 0.85 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:48 PM PST 24
Peak memory 217100 kb
Host smart-a84d6eb5-3c3f-4eb2-91fa-6517f761e12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748444992 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.748444992
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.2329957499
Short name T372
Test name
Test status
Simulation time 34299932 ps
CPU time 1.29 seconds
Started Feb 29 01:41:46 PM PST 24
Finished Feb 29 01:41:48 PM PST 24
Peak memory 216920 kb
Host smart-455b9cf1-7685-4b1c-96dd-4338f12565e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329957499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.2329957499
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_genbits.1289827320
Short name T514
Test name
Test status
Simulation time 70090973 ps
CPU time 1.28 seconds
Started Feb 29 01:41:46 PM PST 24
Finished Feb 29 01:41:48 PM PST 24
Peak memory 217088 kb
Host smart-7e4891ee-9b24-4a0e-8f2d-272789cd616b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289827320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1289827320
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.2796566122
Short name T515
Test name
Test status
Simulation time 23772463 ps
CPU time 0.93 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:49 PM PST 24
Peak memory 217368 kb
Host smart-6309e692-a0ff-47e0-b9dd-a0e6566ffe50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796566122 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2796566122
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2575919242
Short name T592
Test name
Test status
Simulation time 52269221 ps
CPU time 1.35 seconds
Started Feb 29 01:41:46 PM PST 24
Finished Feb 29 01:41:47 PM PST 24
Peak memory 218948 kb
Host smart-9743a91f-a6e1-4cc5-96bc-4b83f172452a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575919242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2575919242
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.1118911346
Short name T470
Test name
Test status
Simulation time 24193754 ps
CPU time 1 seconds
Started Feb 29 01:41:49 PM PST 24
Finished Feb 29 01:41:50 PM PST 24
Peak memory 222444 kb
Host smart-e1bceb7e-c7d7-42e5-8ed4-81274895ced4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118911346 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.1118911346
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.509669641
Short name T779
Test name
Test status
Simulation time 26459100 ps
CPU time 1.22 seconds
Started Feb 29 01:41:53 PM PST 24
Finished Feb 29 01:41:54 PM PST 24
Peak memory 217312 kb
Host smart-9de8f263-eaaf-4eb1-93d4-647a467a5063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509669641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.509669641
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.4160362034
Short name T109
Test name
Test status
Simulation time 26312711 ps
CPU time 0.93 seconds
Started Feb 29 01:41:48 PM PST 24
Finished Feb 29 01:41:49 PM PST 24
Peak memory 217284 kb
Host smart-99b13683-2e33-4f17-b12d-2be836c357f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160362034 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.4160362034
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.4174453574
Short name T324
Test name
Test status
Simulation time 75653272 ps
CPU time 1.04 seconds
Started Feb 29 01:41:40 PM PST 24
Finished Feb 29 01:41:41 PM PST 24
Peak memory 217160 kb
Host smart-64432aa2-0c5a-43c6-b979-6f59d0c41c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174453574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.4174453574
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.1721006369
Short name T693
Test name
Test status
Simulation time 32121137 ps
CPU time 0.85 seconds
Started Feb 29 01:41:44 PM PST 24
Finished Feb 29 01:41:45 PM PST 24
Peak memory 216980 kb
Host smart-f0a9d2e9-3df0-4f21-84f5-91ec1f9996d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721006369 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1721006369
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3076396281
Short name T370
Test name
Test status
Simulation time 53073084 ps
CPU time 1.23 seconds
Started Feb 29 01:41:49 PM PST 24
Finished Feb 29 01:41:51 PM PST 24
Peak memory 218308 kb
Host smart-8dceff33-679f-40b3-b781-4be61975f53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076396281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3076396281
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.991212101
Short name T714
Test name
Test status
Simulation time 24915604 ps
CPU time 1.17 seconds
Started Feb 29 01:41:49 PM PST 24
Finished Feb 29 01:41:51 PM PST 24
Peak memory 217444 kb
Host smart-0399e79b-8dfc-40cf-888f-d475d7d9a798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991212101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.991212101
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3597880713
Short name T260
Test name
Test status
Simulation time 71652238 ps
CPU time 1.16 seconds
Started Feb 29 01:41:55 PM PST 24
Finished Feb 29 01:41:56 PM PST 24
Peak memory 216280 kb
Host smart-7735fa95-ac1d-4307-b561-6d461fe0a292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597880713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3597880713
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.3295375270
Short name T40
Test name
Test status
Simulation time 22163489 ps
CPU time 1.02 seconds
Started Feb 29 01:41:49 PM PST 24
Finished Feb 29 01:41:50 PM PST 24
Peak memory 222412 kb
Host smart-4935918b-2f75-4912-b20a-4a94ccda5204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295375270 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.3295375270
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.941739675
Short name T382
Test name
Test status
Simulation time 62752300 ps
CPU time 1 seconds
Started Feb 29 01:41:49 PM PST 24
Finished Feb 29 01:41:51 PM PST 24
Peak memory 216056 kb
Host smart-ea957d73-3762-4e7b-915a-ebc46967c530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941739675 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.941739675
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.652005839
Short name T674
Test name
Test status
Simulation time 20805752 ps
CPU time 1.08 seconds
Started Feb 29 01:41:47 PM PST 24
Finished Feb 29 01:41:48 PM PST 24
Peak memory 218756 kb
Host smart-c026aa37-0941-47f2-9ae9-bed69ec41fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652005839 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.652005839
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.2868794377
Short name T394
Test name
Test status
Simulation time 70063325 ps
CPU time 1.02 seconds
Started Feb 29 01:41:47 PM PST 24
Finished Feb 29 01:41:48 PM PST 24
Peak memory 215992 kb
Host smart-1dd4165b-346e-4139-87d8-2156e75662ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868794377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.2868794377
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%