Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.94 98.27 93.63 96.79 82.08 96.87 96.58 93.35


Total test records in report: 966
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T789 /workspace/coverage/default/35.edn_intr.1366104182 Mar 03 02:45:46 PM PST 24 Mar 03 02:45:47 PM PST 24 20238910 ps
T790 /workspace/coverage/default/166.edn_genbits.58400065 Mar 03 02:46:40 PM PST 24 Mar 03 02:46:42 PM PST 24 65137209 ps
T791 /workspace/coverage/default/116.edn_genbits.1164982217 Mar 03 02:46:38 PM PST 24 Mar 03 02:46:40 PM PST 24 54364368 ps
T792 /workspace/coverage/default/5.edn_intr.585292353 Mar 03 02:44:42 PM PST 24 Mar 03 02:44:43 PM PST 24 31505827 ps
T793 /workspace/coverage/default/19.edn_alert_test.3477020921 Mar 03 02:45:14 PM PST 24 Mar 03 02:45:16 PM PST 24 58751552 ps
T794 /workspace/coverage/default/136.edn_genbits.2863507410 Mar 03 02:46:41 PM PST 24 Mar 03 02:49:08 PM PST 24 10971004565 ps
T795 /workspace/coverage/default/46.edn_disable.3599764806 Mar 03 02:46:04 PM PST 24 Mar 03 02:46:05 PM PST 24 13410336 ps
T796 /workspace/coverage/default/72.edn_err.211733484 Mar 03 02:46:21 PM PST 24 Mar 03 02:46:23 PM PST 24 32170663 ps
T797 /workspace/coverage/default/42.edn_alert_test.351964417 Mar 03 02:46:02 PM PST 24 Mar 03 02:46:03 PM PST 24 19782632 ps
T798 /workspace/coverage/default/222.edn_genbits.3793745559 Mar 03 02:46:55 PM PST 24 Mar 03 02:46:56 PM PST 24 34214684 ps
T799 /workspace/coverage/default/268.edn_genbits.3199852310 Mar 03 02:47:01 PM PST 24 Mar 03 02:47:02 PM PST 24 92745707 ps
T800 /workspace/coverage/default/14.edn_disable.3419919916 Mar 03 02:45:04 PM PST 24 Mar 03 02:45:05 PM PST 24 14111634 ps
T801 /workspace/coverage/default/38.edn_disable.3173615240 Mar 03 02:45:46 PM PST 24 Mar 03 02:45:48 PM PST 24 13835321 ps
T802 /workspace/coverage/default/8.edn_alert_test.3022677576 Mar 03 02:44:56 PM PST 24 Mar 03 02:44:57 PM PST 24 53784013 ps
T803 /workspace/coverage/default/14.edn_intr.2039827607 Mar 03 02:45:03 PM PST 24 Mar 03 02:45:04 PM PST 24 22751028 ps
T804 /workspace/coverage/default/0.edn_alert_test.439820668 Mar 03 02:44:31 PM PST 24 Mar 03 02:44:32 PM PST 24 20016416 ps
T805 /workspace/coverage/default/42.edn_intr.1668177174 Mar 03 02:45:58 PM PST 24 Mar 03 02:46:00 PM PST 24 21497545 ps
T806 /workspace/coverage/default/78.edn_genbits.2978534895 Mar 03 02:46:24 PM PST 24 Mar 03 02:46:26 PM PST 24 52951643 ps
T162 /workspace/coverage/default/28.edn_disable.3509422219 Mar 03 02:45:37 PM PST 24 Mar 03 02:45:39 PM PST 24 13548481 ps
T807 /workspace/coverage/default/37.edn_genbits.390007454 Mar 03 02:45:47 PM PST 24 Mar 03 02:45:49 PM PST 24 72683495 ps
T56 /workspace/coverage/default/0.edn_sec_cm.2992848856 Mar 03 02:44:30 PM PST 24 Mar 03 02:44:35 PM PST 24 372030427 ps
T808 /workspace/coverage/default/290.edn_genbits.778081664 Mar 03 02:47:10 PM PST 24 Mar 03 02:47:11 PM PST 24 67289393 ps
T809 /workspace/coverage/default/264.edn_genbits.2985488739 Mar 03 02:47:01 PM PST 24 Mar 03 02:47:02 PM PST 24 63946536 ps
T810 /workspace/coverage/default/260.edn_genbits.1529233035 Mar 03 02:47:03 PM PST 24 Mar 03 02:47:04 PM PST 24 81603751 ps
T811 /workspace/coverage/default/40.edn_stress_all.272941492 Mar 03 02:45:56 PM PST 24 Mar 03 02:45:59 PM PST 24 160830400 ps
T812 /workspace/coverage/default/258.edn_genbits.1857652501 Mar 03 02:47:09 PM PST 24 Mar 03 02:47:11 PM PST 24 42776914 ps
T813 /workspace/coverage/default/27.edn_stress_all_with_rand_reset.759566582 Mar 03 02:45:34 PM PST 24 Mar 03 03:13:43 PM PST 24 74028758437 ps
T814 /workspace/coverage/default/41.edn_stress_all_with_rand_reset.236124002 Mar 03 02:46:00 PM PST 24 Mar 03 02:49:56 PM PST 24 9315510724 ps
T815 /workspace/coverage/default/209.edn_genbits.474175062 Mar 03 02:46:55 PM PST 24 Mar 03 02:46:57 PM PST 24 29712372 ps
T816 /workspace/coverage/default/31.edn_disable.3675273898 Mar 03 02:45:38 PM PST 24 Mar 03 02:45:39 PM PST 24 10821681 ps
T817 /workspace/coverage/default/159.edn_genbits.2522041038 Mar 03 02:46:42 PM PST 24 Mar 03 02:46:44 PM PST 24 28647307 ps
T818 /workspace/coverage/default/113.edn_genbits.430267726 Mar 03 02:46:31 PM PST 24 Mar 03 02:46:33 PM PST 24 46773961 ps
T819 /workspace/coverage/default/17.edn_stress_all.2994249428 Mar 03 02:45:10 PM PST 24 Mar 03 02:45:15 PM PST 24 253621401 ps
T255 /workspace/coverage/default/38.edn_alert.1925671070 Mar 03 02:45:50 PM PST 24 Mar 03 02:45:51 PM PST 24 95627767 ps
T57 /workspace/coverage/default/3.edn_sec_cm.1585795238 Mar 03 02:44:41 PM PST 24 Mar 03 02:44:45 PM PST 24 400818139 ps
T820 /workspace/coverage/default/110.edn_genbits.2254441556 Mar 03 02:46:29 PM PST 24 Mar 03 02:46:30 PM PST 24 210270774 ps
T185 /workspace/coverage/default/9.edn_disable.1861462049 Mar 03 02:44:53 PM PST 24 Mar 03 02:44:54 PM PST 24 20138099 ps
T821 /workspace/coverage/default/6.edn_intr.1951789015 Mar 03 02:44:46 PM PST 24 Mar 03 02:44:47 PM PST 24 47438686 ps
T822 /workspace/coverage/default/224.edn_genbits.2591330667 Mar 03 02:46:53 PM PST 24 Mar 03 02:48:08 PM PST 24 2227372696 ps
T823 /workspace/coverage/default/10.edn_smoke.1239627665 Mar 03 02:44:54 PM PST 24 Mar 03 02:44:55 PM PST 24 42755552 ps
T824 /workspace/coverage/default/29.edn_stress_all.1357817326 Mar 03 02:45:33 PM PST 24 Mar 03 02:45:37 PM PST 24 222159822 ps
T825 /workspace/coverage/default/43.edn_stress_all_with_rand_reset.589886044 Mar 03 02:45:59 PM PST 24 Mar 03 02:56:51 PM PST 24 47242713153 ps
T826 /workspace/coverage/default/26.edn_err.2222939232 Mar 03 02:45:29 PM PST 24 Mar 03 02:45:31 PM PST 24 20582540 ps
T827 /workspace/coverage/default/31.edn_intr.2021865085 Mar 03 02:45:40 PM PST 24 Mar 03 02:45:42 PM PST 24 27996032 ps
T828 /workspace/coverage/default/71.edn_genbits.1147824855 Mar 03 02:46:21 PM PST 24 Mar 03 02:46:22 PM PST 24 68090982 ps
T829 /workspace/coverage/default/26.edn_smoke.977104124 Mar 03 02:45:30 PM PST 24 Mar 03 02:45:32 PM PST 24 65676401 ps
T830 /workspace/coverage/default/5.edn_err.3319890525 Mar 03 02:44:42 PM PST 24 Mar 03 02:44:43 PM PST 24 19956848 ps
T831 /workspace/coverage/default/14.edn_stress_all.1374529982 Mar 03 02:45:04 PM PST 24 Mar 03 02:45:10 PM PST 24 1541154342 ps
T270 /workspace/coverage/default/201.edn_genbits.2600657926 Mar 03 02:46:52 PM PST 24 Mar 03 02:46:53 PM PST 24 86984822 ps
T832 /workspace/coverage/default/21.edn_stress_all.633655552 Mar 03 02:45:19 PM PST 24 Mar 03 02:45:20 PM PST 24 43895912 ps
T186 /workspace/coverage/default/3.edn_alert.2971014806 Mar 03 02:44:35 PM PST 24 Mar 03 02:44:36 PM PST 24 47570200 ps
T197 /workspace/coverage/cover_reg_top/3.edn_csr_rw.2077904067 Mar 03 12:40:16 PM PST 24 Mar 03 12:40:18 PM PST 24 16137752 ps
T215 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.569454892 Mar 03 12:40:34 PM PST 24 Mar 03 12:40:36 PM PST 24 23553718 ps
T216 /workspace/coverage/cover_reg_top/12.edn_csr_rw.1396999099 Mar 03 12:40:40 PM PST 24 Mar 03 12:40:41 PM PST 24 12053605 ps
T833 /workspace/coverage/cover_reg_top/40.edn_intr_test.1097600063 Mar 03 12:40:47 PM PST 24 Mar 03 12:40:48 PM PST 24 38058610 ps
T217 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1598249061 Mar 03 12:40:49 PM PST 24 Mar 03 12:40:51 PM PST 24 21179196 ps
T218 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.933508611 Mar 03 12:40:23 PM PST 24 Mar 03 12:40:24 PM PST 24 20615942 ps
T198 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1131070044 Mar 03 12:40:33 PM PST 24 Mar 03 12:40:34 PM PST 24 19647996 ps
T219 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1517066309 Mar 03 12:40:18 PM PST 24 Mar 03 12:40:19 PM PST 24 14432519 ps
T231 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2999357781 Mar 03 12:40:33 PM PST 24 Mar 03 12:40:35 PM PST 24 140118823 ps
T199 /workspace/coverage/cover_reg_top/16.edn_csr_rw.2833947607 Mar 03 12:40:21 PM PST 24 Mar 03 12:40:22 PM PST 24 12653521 ps
T232 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1420275691 Mar 03 12:40:24 PM PST 24 Mar 03 12:40:26 PM PST 24 103776969 ps
T200 /workspace/coverage/cover_reg_top/17.edn_csr_rw.4288375583 Mar 03 12:40:40 PM PST 24 Mar 03 12:40:41 PM PST 24 12805714 ps
T834 /workspace/coverage/cover_reg_top/11.edn_tl_errors.835602477 Mar 03 12:40:29 PM PST 24 Mar 03 12:40:33 PM PST 24 1588878843 ps
T835 /workspace/coverage/cover_reg_top/31.edn_intr_test.1518534520 Mar 03 12:40:45 PM PST 24 Mar 03 12:40:47 PM PST 24 11344441 ps
T836 /workspace/coverage/cover_reg_top/4.edn_intr_test.2739485781 Mar 03 12:40:20 PM PST 24 Mar 03 12:40:21 PM PST 24 16561987 ps
T201 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2396452105 Mar 03 12:40:55 PM PST 24 Mar 03 12:41:02 PM PST 24 40962285 ps
T837 /workspace/coverage/cover_reg_top/27.edn_intr_test.3838140975 Mar 03 12:40:40 PM PST 24 Mar 03 12:40:41 PM PST 24 14017260 ps
T202 /workspace/coverage/cover_reg_top/6.edn_csr_rw.4150377378 Mar 03 12:40:31 PM PST 24 Mar 03 12:40:32 PM PST 24 21589507 ps
T838 /workspace/coverage/cover_reg_top/18.edn_intr_test.1287241682 Mar 03 12:40:37 PM PST 24 Mar 03 12:40:38 PM PST 24 22573387 ps
T839 /workspace/coverage/cover_reg_top/38.edn_intr_test.1493209371 Mar 03 12:40:57 PM PST 24 Mar 03 12:40:58 PM PST 24 14873352 ps
T840 /workspace/coverage/cover_reg_top/41.edn_intr_test.1769498476 Mar 03 12:40:42 PM PST 24 Mar 03 12:40:43 PM PST 24 13959937 ps
T203 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.434763645 Mar 03 12:40:24 PM PST 24 Mar 03 12:40:26 PM PST 24 27624477 ps
T841 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1489392575 Mar 03 12:40:38 PM PST 24 Mar 03 12:40:40 PM PST 24 57376019 ps
T233 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.846017458 Mar 03 12:41:05 PM PST 24 Mar 03 12:41:07 PM PST 24 301692779 ps
T245 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2168652652 Mar 03 12:40:43 PM PST 24 Mar 03 12:40:45 PM PST 24 475134768 ps
T842 /workspace/coverage/cover_reg_top/30.edn_intr_test.2606616755 Mar 03 12:40:39 PM PST 24 Mar 03 12:40:40 PM PST 24 47351046 ps
T220 /workspace/coverage/cover_reg_top/18.edn_csr_rw.2817695528 Mar 03 12:40:48 PM PST 24 Mar 03 12:40:49 PM PST 24 89088831 ps
T843 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3006371903 Mar 03 12:40:22 PM PST 24 Mar 03 12:40:24 PM PST 24 17066273 ps
T844 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3701012680 Mar 03 12:40:41 PM PST 24 Mar 03 12:40:42 PM PST 24 447150490 ps
T845 /workspace/coverage/cover_reg_top/47.edn_intr_test.3397112082 Mar 03 12:40:51 PM PST 24 Mar 03 12:40:51 PM PST 24 21523166 ps
T846 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.228922596 Mar 03 12:40:21 PM PST 24 Mar 03 12:40:23 PM PST 24 36527668 ps
T204 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.4222242057 Mar 03 12:40:22 PM PST 24 Mar 03 12:40:24 PM PST 24 568605420 ps
T205 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3095619427 Mar 03 12:40:34 PM PST 24 Mar 03 12:40:37 PM PST 24 60506255 ps
T206 /workspace/coverage/cover_reg_top/13.edn_csr_rw.2661597318 Mar 03 12:40:24 PM PST 24 Mar 03 12:40:30 PM PST 24 54236216 ps
T847 /workspace/coverage/cover_reg_top/1.edn_intr_test.2874106162 Mar 03 12:40:42 PM PST 24 Mar 03 12:40:43 PM PST 24 125488577 ps
T244 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3654461734 Mar 03 12:40:42 PM PST 24 Mar 03 12:40:45 PM PST 24 161801324 ps
T848 /workspace/coverage/cover_reg_top/17.edn_intr_test.1254202472 Mar 03 12:40:53 PM PST 24 Mar 03 12:40:54 PM PST 24 14313963 ps
T849 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3547236218 Mar 03 12:40:44 PM PST 24 Mar 03 12:40:45 PM PST 24 31233710 ps
T850 /workspace/coverage/cover_reg_top/28.edn_intr_test.396208071 Mar 03 12:40:31 PM PST 24 Mar 03 12:40:32 PM PST 24 24599041 ps
T851 /workspace/coverage/cover_reg_top/11.edn_intr_test.2351185343 Mar 03 12:40:49 PM PST 24 Mar 03 12:40:50 PM PST 24 20835688 ps
T852 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2825117887 Mar 03 12:40:24 PM PST 24 Mar 03 12:40:27 PM PST 24 281173467 ps
T853 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3736352493 Mar 03 12:40:28 PM PST 24 Mar 03 12:40:32 PM PST 24 45507452 ps
T854 /workspace/coverage/cover_reg_top/20.edn_intr_test.3564257841 Mar 03 12:40:42 PM PST 24 Mar 03 12:40:44 PM PST 24 128468501 ps
T242 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2765648449 Mar 03 12:40:34 PM PST 24 Mar 03 12:40:36 PM PST 24 280202420 ps
T855 /workspace/coverage/cover_reg_top/1.edn_tl_errors.1810585858 Mar 03 12:40:20 PM PST 24 Mar 03 12:40:23 PM PST 24 257495653 ps
T207 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2674643566 Mar 03 12:40:31 PM PST 24 Mar 03 12:40:32 PM PST 24 67928446 ps
T856 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2596624596 Mar 03 12:40:58 PM PST 24 Mar 03 12:40:59 PM PST 24 59496015 ps
T857 /workspace/coverage/cover_reg_top/25.edn_intr_test.1566509344 Mar 03 12:40:45 PM PST 24 Mar 03 12:40:47 PM PST 24 11362925 ps
T858 /workspace/coverage/cover_reg_top/46.edn_intr_test.3885867486 Mar 03 12:40:55 PM PST 24 Mar 03 12:40:56 PM PST 24 55033088 ps
T859 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.683761867 Mar 03 12:40:27 PM PST 24 Mar 03 12:40:29 PM PST 24 93896855 ps
T860 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3525740614 Mar 03 12:40:38 PM PST 24 Mar 03 12:40:40 PM PST 24 174386616 ps
T861 /workspace/coverage/cover_reg_top/7.edn_intr_test.3946762955 Mar 03 12:40:53 PM PST 24 Mar 03 12:40:54 PM PST 24 27830385 ps
T208 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2298227050 Mar 03 12:40:27 PM PST 24 Mar 03 12:40:28 PM PST 24 17427216 ps
T862 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3900747166 Mar 03 12:40:40 PM PST 24 Mar 03 12:40:41 PM PST 24 68671191 ps
T863 /workspace/coverage/cover_reg_top/45.edn_intr_test.4001703384 Mar 03 12:40:50 PM PST 24 Mar 03 12:40:51 PM PST 24 47420737 ps
T864 /workspace/coverage/cover_reg_top/14.edn_intr_test.3877840417 Mar 03 12:40:46 PM PST 24 Mar 03 12:40:47 PM PST 24 84186649 ps
T865 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.821218736 Mar 03 12:40:37 PM PST 24 Mar 03 12:40:39 PM PST 24 25147441 ps
T866 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3154374955 Mar 03 12:40:27 PM PST 24 Mar 03 12:40:28 PM PST 24 46890535 ps
T867 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.572130302 Mar 03 12:40:38 PM PST 24 Mar 03 12:40:39 PM PST 24 18336247 ps
T868 /workspace/coverage/cover_reg_top/12.edn_intr_test.320728539 Mar 03 12:40:37 PM PST 24 Mar 03 12:40:39 PM PST 24 14208004 ps
T869 /workspace/coverage/cover_reg_top/33.edn_intr_test.144887385 Mar 03 12:40:24 PM PST 24 Mar 03 12:40:25 PM PST 24 12834108 ps
T870 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.70256628 Mar 03 12:40:56 PM PST 24 Mar 03 12:40:57 PM PST 24 103003001 ps
T871 /workspace/coverage/cover_reg_top/16.edn_intr_test.456548673 Mar 03 12:40:55 PM PST 24 Mar 03 12:40:56 PM PST 24 14080626 ps
T872 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.4083805631 Mar 03 12:40:26 PM PST 24 Mar 03 12:40:31 PM PST 24 176932174 ps
T873 /workspace/coverage/cover_reg_top/23.edn_intr_test.3796901880 Mar 03 12:40:31 PM PST 24 Mar 03 12:40:32 PM PST 24 12703205 ps
T874 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2052363484 Mar 03 12:40:28 PM PST 24 Mar 03 12:40:29 PM PST 24 73297036 ps
T875 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.740008068 Mar 03 12:40:34 PM PST 24 Mar 03 12:40:36 PM PST 24 151336416 ps
T876 /workspace/coverage/cover_reg_top/22.edn_intr_test.392587993 Mar 03 12:40:54 PM PST 24 Mar 03 12:40:55 PM PST 24 28565566 ps
T877 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3919808374 Mar 03 12:40:25 PM PST 24 Mar 03 12:40:27 PM PST 24 116511851 ps
T878 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1391405842 Mar 03 12:40:28 PM PST 24 Mar 03 12:40:31 PM PST 24 89051453 ps
T879 /workspace/coverage/cover_reg_top/13.edn_tl_errors.813866921 Mar 03 12:40:59 PM PST 24 Mar 03 12:41:01 PM PST 24 100440938 ps
T880 /workspace/coverage/cover_reg_top/10.edn_csr_rw.1505330322 Mar 03 12:41:04 PM PST 24 Mar 03 12:41:05 PM PST 24 13903120 ps
T881 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.740191026 Mar 03 12:40:26 PM PST 24 Mar 03 12:40:28 PM PST 24 36339434 ps
T882 /workspace/coverage/cover_reg_top/9.edn_csr_rw.4139501616 Mar 03 12:40:25 PM PST 24 Mar 03 12:40:26 PM PST 24 23928682 ps
T883 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.221063748 Mar 03 12:40:36 PM PST 24 Mar 03 12:40:38 PM PST 24 75197647 ps
T884 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1099499906 Mar 03 12:40:41 PM PST 24 Mar 03 12:40:43 PM PST 24 60795388 ps
T885 /workspace/coverage/cover_reg_top/24.edn_intr_test.3094366754 Mar 03 12:40:49 PM PST 24 Mar 03 12:40:50 PM PST 24 17506955 ps
T886 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3074058675 Mar 03 12:40:45 PM PST 24 Mar 03 12:40:46 PM PST 24 52200975 ps
T887 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3744998463 Mar 03 12:40:19 PM PST 24 Mar 03 12:40:22 PM PST 24 194645525 ps
T209 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.566232589 Mar 03 12:40:43 PM PST 24 Mar 03 12:40:45 PM PST 24 40559694 ps
T888 /workspace/coverage/cover_reg_top/10.edn_intr_test.1867568125 Mar 03 12:40:25 PM PST 24 Mar 03 12:40:26 PM PST 24 22160593 ps
T210 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2207591332 Mar 03 12:40:33 PM PST 24 Mar 03 12:40:34 PM PST 24 19667489 ps
T211 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3738015317 Mar 03 12:40:24 PM PST 24 Mar 03 12:40:25 PM PST 24 25188611 ps
T889 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.907423154 Mar 03 12:40:37 PM PST 24 Mar 03 12:40:39 PM PST 24 179919129 ps
T890 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2566169697 Mar 03 12:40:26 PM PST 24 Mar 03 12:40:27 PM PST 24 49337140 ps
T891 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2310913924 Mar 03 12:40:56 PM PST 24 Mar 03 12:40:57 PM PST 24 17339200 ps
T892 /workspace/coverage/cover_reg_top/7.edn_tl_errors.1611780902 Mar 03 12:40:44 PM PST 24 Mar 03 12:40:47 PM PST 24 105374742 ps
T893 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1113445097 Mar 03 12:40:15 PM PST 24 Mar 03 12:40:18 PM PST 24 79823385 ps
T894 /workspace/coverage/cover_reg_top/43.edn_intr_test.1687791457 Mar 03 12:40:40 PM PST 24 Mar 03 12:40:41 PM PST 24 12341036 ps
T895 /workspace/coverage/cover_reg_top/5.edn_tl_errors.2698179696 Mar 03 12:40:44 PM PST 24 Mar 03 12:40:49 PM PST 24 135981300 ps
T896 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.516316916 Mar 03 12:40:32 PM PST 24 Mar 03 12:40:34 PM PST 24 178268145 ps
T897 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3994286036 Mar 03 12:40:34 PM PST 24 Mar 03 12:40:36 PM PST 24 441665708 ps
T898 /workspace/coverage/cover_reg_top/26.edn_intr_test.155766307 Mar 03 12:40:25 PM PST 24 Mar 03 12:40:26 PM PST 24 11622127 ps
T899 /workspace/coverage/cover_reg_top/6.edn_tl_errors.1312454855 Mar 03 12:40:27 PM PST 24 Mar 03 12:40:29 PM PST 24 214481212 ps
T900 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3498557467 Mar 03 12:40:23 PM PST 24 Mar 03 12:40:29 PM PST 24 1013623954 ps
T901 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1494058248 Mar 03 12:40:24 PM PST 24 Mar 03 12:40:25 PM PST 24 36278616 ps
T212 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.911575602 Mar 03 12:40:14 PM PST 24 Mar 03 12:40:17 PM PST 24 35615851 ps
T902 /workspace/coverage/cover_reg_top/49.edn_intr_test.1434054325 Mar 03 12:40:57 PM PST 24 Mar 03 12:40:58 PM PST 24 65033124 ps
T903 /workspace/coverage/cover_reg_top/9.edn_tl_errors.1639665983 Mar 03 12:40:32 PM PST 24 Mar 03 12:40:34 PM PST 24 30129276 ps
T904 /workspace/coverage/cover_reg_top/37.edn_intr_test.234125536 Mar 03 12:40:47 PM PST 24 Mar 03 12:40:48 PM PST 24 40042985 ps
T905 /workspace/coverage/cover_reg_top/0.edn_csr_rw.1703547484 Mar 03 12:40:13 PM PST 24 Mar 03 12:40:14 PM PST 24 21895431 ps
T906 /workspace/coverage/cover_reg_top/36.edn_intr_test.274337539 Mar 03 12:41:17 PM PST 24 Mar 03 12:41:18 PM PST 24 41220097 ps
T907 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3016319446 Mar 03 12:40:52 PM PST 24 Mar 03 12:40:53 PM PST 24 51981482 ps
T908 /workspace/coverage/cover_reg_top/8.edn_tl_errors.2015604048 Mar 03 12:40:26 PM PST 24 Mar 03 12:40:29 PM PST 24 881136015 ps
T909 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1986536115 Mar 03 12:40:54 PM PST 24 Mar 03 12:40:55 PM PST 24 129356658 ps
T910 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.506219122 Mar 03 12:40:54 PM PST 24 Mar 03 12:40:55 PM PST 24 69716470 ps
T911 /workspace/coverage/cover_reg_top/29.edn_intr_test.584324912 Mar 03 12:40:49 PM PST 24 Mar 03 12:40:50 PM PST 24 15371492 ps
T912 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2635201861 Mar 03 12:40:10 PM PST 24 Mar 03 12:40:14 PM PST 24 180173250 ps
T913 /workspace/coverage/cover_reg_top/8.edn_csr_rw.374997534 Mar 03 12:40:28 PM PST 24 Mar 03 12:40:29 PM PST 24 17745606 ps
T914 /workspace/coverage/cover_reg_top/44.edn_intr_test.3462521973 Mar 03 12:40:49 PM PST 24 Mar 03 12:40:50 PM PST 24 16619452 ps
T915 /workspace/coverage/cover_reg_top/34.edn_intr_test.2540071686 Mar 03 12:40:33 PM PST 24 Mar 03 12:40:34 PM PST 24 22780274 ps
T916 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.4009222184 Mar 03 12:40:21 PM PST 24 Mar 03 12:40:23 PM PST 24 30125331 ps
T917 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1795315867 Mar 03 12:40:26 PM PST 24 Mar 03 12:40:28 PM PST 24 84897152 ps
T918 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3481422975 Mar 03 12:40:22 PM PST 24 Mar 03 12:40:23 PM PST 24 111480557 ps
T919 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.761078981 Mar 03 12:40:25 PM PST 24 Mar 03 12:40:26 PM PST 24 53573969 ps
T920 /workspace/coverage/cover_reg_top/17.edn_tl_errors.2775247823 Mar 03 12:40:55 PM PST 24 Mar 03 12:41:00 PM PST 24 120431617 ps
T921 /workspace/coverage/cover_reg_top/14.edn_tl_errors.2675923522 Mar 03 12:40:25 PM PST 24 Mar 03 12:40:27 PM PST 24 31991572 ps
T213 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2731782056 Mar 03 12:40:30 PM PST 24 Mar 03 12:40:34 PM PST 24 184308199 ps
T922 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1466736165 Mar 03 12:40:26 PM PST 24 Mar 03 12:40:32 PM PST 24 29101794 ps
T923 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4084037258 Mar 03 12:40:38 PM PST 24 Mar 03 12:40:44 PM PST 24 161746321 ps
T924 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.211621140 Mar 03 12:40:24 PM PST 24 Mar 03 12:40:27 PM PST 24 145152931 ps
T925 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2439830600 Mar 03 12:40:20 PM PST 24 Mar 03 12:40:25 PM PST 24 209857469 ps
T926 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3378682354 Mar 03 12:40:38 PM PST 24 Mar 03 12:40:39 PM PST 24 313564672 ps
T927 /workspace/coverage/cover_reg_top/42.edn_intr_test.1192711839 Mar 03 12:41:01 PM PST 24 Mar 03 12:41:02 PM PST 24 19703473 ps
T928 /workspace/coverage/cover_reg_top/2.edn_intr_test.4003503643 Mar 03 12:40:20 PM PST 24 Mar 03 12:40:26 PM PST 24 71734288 ps
T929 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.584195273 Mar 03 12:40:28 PM PST 24 Mar 03 12:40:30 PM PST 24 98314923 ps
T930 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2112807491 Mar 03 12:40:27 PM PST 24 Mar 03 12:40:28 PM PST 24 105854506 ps
T931 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.108425912 Mar 03 12:40:50 PM PST 24 Mar 03 12:40:52 PM PST 24 82012603 ps
T932 /workspace/coverage/cover_reg_top/5.edn_intr_test.138273975 Mar 03 12:40:44 PM PST 24 Mar 03 12:40:45 PM PST 24 23602099 ps
T933 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1004855984 Mar 03 12:40:22 PM PST 24 Mar 03 12:40:24 PM PST 24 49926868 ps
T934 /workspace/coverage/cover_reg_top/0.edn_intr_test.3602566234 Mar 03 12:40:20 PM PST 24 Mar 03 12:40:21 PM PST 24 13233618 ps
T935 /workspace/coverage/cover_reg_top/15.edn_tl_errors.3307925886 Mar 03 12:40:29 PM PST 24 Mar 03 12:40:36 PM PST 24 21668400 ps
T936 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2147039105 Mar 03 12:40:47 PM PST 24 Mar 03 12:40:49 PM PST 24 14692100 ps
T937 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3153481700 Mar 03 12:41:05 PM PST 24 Mar 03 12:41:06 PM PST 24 111451710 ps
T938 /workspace/coverage/cover_reg_top/4.edn_csr_rw.1383471817 Mar 03 12:40:28 PM PST 24 Mar 03 12:40:30 PM PST 24 38714825 ps
T939 /workspace/coverage/cover_reg_top/39.edn_intr_test.2372729549 Mar 03 12:40:52 PM PST 24 Mar 03 12:40:53 PM PST 24 44519096 ps
T940 /workspace/coverage/cover_reg_top/6.edn_intr_test.752723813 Mar 03 12:41:04 PM PST 24 Mar 03 12:41:05 PM PST 24 32463212 ps
T941 /workspace/coverage/cover_reg_top/21.edn_intr_test.328038289 Mar 03 12:40:28 PM PST 24 Mar 03 12:40:30 PM PST 24 14810802 ps
T942 /workspace/coverage/cover_reg_top/19.edn_intr_test.2042746978 Mar 03 12:40:59 PM PST 24 Mar 03 12:41:00 PM PST 24 10506067 ps
T943 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1547604566 Mar 03 12:40:44 PM PST 24 Mar 03 12:40:46 PM PST 24 66838583 ps
T944 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1997225466 Mar 03 12:41:07 PM PST 24 Mar 03 12:41:08 PM PST 24 37499541 ps
T945 /workspace/coverage/cover_reg_top/9.edn_intr_test.3937197460 Mar 03 12:40:30 PM PST 24 Mar 03 12:40:31 PM PST 24 29799505 ps
T243 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.387117439 Mar 03 12:40:34 PM PST 24 Mar 03 12:40:36 PM PST 24 226998775 ps
T946 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1226085557 Mar 03 12:40:51 PM PST 24 Mar 03 12:40:53 PM PST 24 146955972 ps
T947 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3185432687 Mar 03 12:40:56 PM PST 24 Mar 03 12:40:57 PM PST 24 80428789 ps
T948 /workspace/coverage/cover_reg_top/14.edn_csr_rw.1324760169 Mar 03 12:40:26 PM PST 24 Mar 03 12:40:28 PM PST 24 13581171 ps
T949 /workspace/coverage/cover_reg_top/2.edn_tl_errors.234815973 Mar 03 12:40:23 PM PST 24 Mar 03 12:40:25 PM PST 24 163134280 ps
T950 /workspace/coverage/cover_reg_top/48.edn_intr_test.319846631 Mar 03 12:40:43 PM PST 24 Mar 03 12:40:44 PM PST 24 15813381 ps
T951 /workspace/coverage/cover_reg_top/13.edn_intr_test.2480305659 Mar 03 12:40:36 PM PST 24 Mar 03 12:40:37 PM PST 24 47362369 ps
T952 /workspace/coverage/cover_reg_top/35.edn_intr_test.2862459706 Mar 03 12:40:36 PM PST 24 Mar 03 12:40:37 PM PST 24 13771571 ps
T953 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2787828919 Mar 03 12:40:26 PM PST 24 Mar 03 12:40:28 PM PST 24 73188627 ps
T214 /workspace/coverage/cover_reg_top/5.edn_csr_rw.2053146795 Mar 03 12:40:27 PM PST 24 Mar 03 12:40:28 PM PST 24 14158073 ps
T954 /workspace/coverage/cover_reg_top/8.edn_intr_test.2110173845 Mar 03 12:40:27 PM PST 24 Mar 03 12:40:28 PM PST 24 30540935 ps
T955 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2901920410 Mar 03 12:40:37 PM PST 24 Mar 03 12:40:40 PM PST 24 139153818 ps
T956 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3170846520 Mar 03 12:40:42 PM PST 24 Mar 03 12:40:43 PM PST 24 208892197 ps
T957 /workspace/coverage/cover_reg_top/15.edn_intr_test.1133196251 Mar 03 12:40:29 PM PST 24 Mar 03 12:40:30 PM PST 24 19026287 ps
T958 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3948183702 Mar 03 12:40:25 PM PST 24 Mar 03 12:40:27 PM PST 24 26792011 ps
T959 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1898333066 Mar 03 12:40:38 PM PST 24 Mar 03 12:40:40 PM PST 24 102278049 ps
T960 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3472251734 Mar 03 12:40:37 PM PST 24 Mar 03 12:40:39 PM PST 24 51049328 ps
T961 /workspace/coverage/cover_reg_top/3.edn_intr_test.1437469834 Mar 03 12:40:22 PM PST 24 Mar 03 12:40:24 PM PST 24 14745526 ps
T962 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4086359331 Mar 03 12:40:05 PM PST 24 Mar 03 12:40:06 PM PST 24 172805690 ps
T963 /workspace/coverage/cover_reg_top/32.edn_intr_test.3001208311 Mar 03 12:40:49 PM PST 24 Mar 03 12:40:50 PM PST 24 17458895 ps
T964 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.4162788593 Mar 03 12:40:43 PM PST 24 Mar 03 12:40:46 PM PST 24 286657177 ps
T965 /workspace/coverage/cover_reg_top/12.edn_tl_errors.405532435 Mar 03 12:40:29 PM PST 24 Mar 03 12:40:31 PM PST 24 83974069 ps
T966 /workspace/coverage/cover_reg_top/19.edn_tl_errors.3319509644 Mar 03 12:40:27 PM PST 24 Mar 03 12:40:31 PM PST 24 265203128 ps

Test location /workspace/coverage/default/32.edn_stress_all.765813854
Short name T35
Test name
Test status
Simulation time 1713031421 ps
CPU time 5.25 seconds
Started Mar 03 02:45:39 PM PST 24
Finished Mar 03 02:45:45 PM PST 24
Peak memory 215196 kb
Host smart-b7f00df0-321e-4fdb-b17b-5e2a847284b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765813854 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.765813854
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.3862437767
Short name T9
Test name
Test status
Simulation time 44972354 ps
CPU time 1.04 seconds
Started Mar 03 02:45:58 PM PST 24
Finished Mar 03 02:45:59 PM PST 24
Peak memory 215192 kb
Host smart-8a7fb628-507c-49a0-86d6-997981fe84e1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862437767 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.3862437767
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/79.edn_genbits.4241314878
Short name T12
Test name
Test status
Simulation time 68757056 ps
CPU time 1.48 seconds
Started Mar 03 02:46:25 PM PST 24
Finished Mar 03 02:46:26 PM PST 24
Peak memory 218356 kb
Host smart-be93bc4f-6887-4dc7-a754-6b6c5a6e4346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241314878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.4241314878
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_alert.4193586828
Short name T16
Test name
Test status
Simulation time 24971133 ps
CPU time 1.19 seconds
Started Mar 03 02:44:34 PM PST 24
Finished Mar 03 02:44:35 PM PST 24
Peak memory 214500 kb
Host smart-f931fe95-4040-4cff-8299-f2c95ed4368a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193586828 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.4193586828
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/60.edn_err.3217590354
Short name T25
Test name
Test status
Simulation time 26296614 ps
CPU time 1.01 seconds
Started Mar 03 02:46:18 PM PST 24
Finished Mar 03 02:46:19 PM PST 24
Peak memory 221796 kb
Host smart-2549f369-4b6a-4b35-9b3d-9d93f19a9938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217590354 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.3217590354
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1884874454
Short name T23
Test name
Test status
Simulation time 354251240707 ps
CPU time 1318.4 seconds
Started Mar 03 02:46:00 PM PST 24
Finished Mar 03 03:07:59 PM PST 24
Peak memory 222436 kb
Host smart-18ff9ffe-1659-453b-a6a9-ea45288656d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884874454 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1884874454
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2172254654
Short name T19
Test name
Test status
Simulation time 1261788978 ps
CPU time 6.56 seconds
Started Mar 03 02:44:42 PM PST 24
Finished Mar 03 02:44:49 PM PST 24
Peak memory 235828 kb
Host smart-7ea5f1dd-9b98-457c-ad4f-b57c701c8880
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172254654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2172254654
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/24.edn_err.393110483
Short name T5
Test name
Test status
Simulation time 31915553 ps
CPU time 1.16 seconds
Started Mar 03 02:45:29 PM PST 24
Finished Mar 03 02:45:31 PM PST 24
Peak memory 230136 kb
Host smart-acec228c-7d97-4a29-8746-49e29162dd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393110483 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.393110483
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/20.edn_alert.2573591150
Short name T17
Test name
Test status
Simulation time 50861431 ps
CPU time 1.27 seconds
Started Mar 03 02:45:14 PM PST 24
Finished Mar 03 02:45:15 PM PST 24
Peak memory 214488 kb
Host smart-26207969-70f4-4d23-9e38-ffe27e37dd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573591150 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2573591150
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/1.edn_regwen.684657300
Short name T130
Test name
Test status
Simulation time 27070067 ps
CPU time 0.93 seconds
Started Mar 03 02:44:29 PM PST 24
Finished Mar 03 02:44:31 PM PST 24
Peak memory 205924 kb
Host smart-2a29947f-06af-4a89-afab-0eeebfbcf05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684657300 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.684657300
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/18.edn_intr.1671744084
Short name T137
Test name
Test status
Simulation time 24054245 ps
CPU time 1.04 seconds
Started Mar 03 02:45:09 PM PST 24
Finished Mar 03 02:45:10 PM PST 24
Peak memory 214464 kb
Host smart-1825b873-78fa-4656-9b02-8e675f019781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671744084 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.1671744084
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.2999357781
Short name T231
Test name
Test status
Simulation time 140118823 ps
CPU time 1.48 seconds
Started Mar 03 12:40:33 PM PST 24
Finished Mar 03 12:40:35 PM PST 24
Peak memory 206192 kb
Host smart-41fdd365-0278-4827-9c44-03b975331d98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999357781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.2999357781
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.4150377378
Short name T202
Test name
Test status
Simulation time 21589507 ps
CPU time 0.9 seconds
Started Mar 03 12:40:31 PM PST 24
Finished Mar 03 12:40:32 PM PST 24
Peak memory 206192 kb
Host smart-096adac9-1437-45be-94d9-8d878f843263
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150377378 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.4150377378
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/default/25.edn_alert.4145313092
Short name T106
Test name
Test status
Simulation time 81853148 ps
CPU time 1.08 seconds
Started Mar 03 02:45:27 PM PST 24
Finished Mar 03 02:45:28 PM PST 24
Peak memory 214556 kb
Host smart-4560d9c7-9c1e-4ce9-992f-6f963d9e9037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145313092 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.4145313092
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/18.edn_disable.2823897799
Short name T45
Test name
Test status
Simulation time 10849213 ps
CPU time 0.86 seconds
Started Mar 03 02:45:11 PM PST 24
Finished Mar 03 02:45:12 PM PST 24
Peak memory 214544 kb
Host smart-1287e0e3-ebb0-49b5-9452-96530d14e801
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823897799 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2823897799
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.2364819135
Short name T68
Test name
Test status
Simulation time 24281497 ps
CPU time 0.92 seconds
Started Mar 03 02:44:57 PM PST 24
Finished Mar 03 02:44:58 PM PST 24
Peak memory 216476 kb
Host smart-7e8f3754-7f9c-49dd-be7f-4b0cb99545d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364819135 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2364819135
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.2865205200
Short name T92
Test name
Test status
Simulation time 53345794 ps
CPU time 1.1 seconds
Started Mar 03 02:44:34 PM PST 24
Finished Mar 03 02:44:35 PM PST 24
Peak memory 215200 kb
Host smart-b128ea5c-72f4-49ec-9f58-b29f98652bf9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865205200 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.2865205200
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_disable.364875436
Short name T127
Test name
Test status
Simulation time 13710163 ps
CPU time 0.91 seconds
Started Mar 03 02:44:41 PM PST 24
Finished Mar 03 02:44:43 PM PST 24
Peak memory 214744 kb
Host smart-020abc96-b29d-4edc-a1f8-d3717f6922a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364875436 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.364875436
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.3986549799
Short name T161
Test name
Test status
Simulation time 43622453 ps
CPU time 1.2 seconds
Started Mar 03 02:45:00 PM PST 24
Finished Mar 03 02:45:02 PM PST 24
Peak memory 215312 kb
Host smart-9c63c339-81fd-44e1-8679-6e9b2e25ce65
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986549799 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.3986549799
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_disable.2051349871
Short name T158
Test name
Test status
Simulation time 38617331 ps
CPU time 0.88 seconds
Started Mar 03 02:45:11 PM PST 24
Finished Mar 03 02:45:12 PM PST 24
Peak memory 214608 kb
Host smart-86ae1e21-15ed-498f-8649-e2aaba790c44
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051349871 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2051349871
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/20.edn_intr.1695473930
Short name T142
Test name
Test status
Simulation time 26667069 ps
CPU time 0.91 seconds
Started Mar 03 02:45:17 PM PST 24
Finished Mar 03 02:45:18 PM PST 24
Peak memory 214548 kb
Host smart-3ab5b202-369f-447d-9b29-39a52249c9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695473930 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.1695473930
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/16.edn_genbits.3264913332
Short name T10
Test name
Test status
Simulation time 41341817 ps
CPU time 1.23 seconds
Started Mar 03 02:45:10 PM PST 24
Finished Mar 03 02:45:12 PM PST 24
Peak memory 217860 kb
Host smart-1fbda389-7352-4c15-b1e6-a30aac93c271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264913332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.3264913332
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_disable.3597497414
Short name T40
Test name
Test status
Simulation time 24808603 ps
CPU time 0.91 seconds
Started Mar 03 02:44:49 PM PST 24
Finished Mar 03 02:44:50 PM PST 24
Peak memory 214616 kb
Host smart-bf817a5b-c378-4bc3-a61c-054a8135bef5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597497414 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.3597497414
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/145.edn_genbits.3587029623
Short name T241
Test name
Test status
Simulation time 80122854 ps
CPU time 1.21 seconds
Started Mar 03 02:46:38 PM PST 24
Finished Mar 03 02:46:39 PM PST 24
Peak memory 215756 kb
Host smart-5f62543f-555a-4ae9-8e7f-d26d6d72a170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587029623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.3587029623
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_alert.24882654
Short name T110
Test name
Test status
Simulation time 39869146 ps
CPU time 1.15 seconds
Started Mar 03 02:44:57 PM PST 24
Finished Mar 03 02:44:59 PM PST 24
Peak memory 214572 kb
Host smart-c07977e3-a508-42e4-9bef-7e64d8bf916e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24882654 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.24882654
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/247.edn_genbits.3855823177
Short name T325
Test name
Test status
Simulation time 27675764 ps
CPU time 1.35 seconds
Started Mar 03 02:47:02 PM PST 24
Finished Mar 03 02:47:03 PM PST 24
Peak memory 216696 kb
Host smart-cf456f0e-fc1d-4c32-908f-d65c3ef71556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855823177 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.3855823177
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_disable.54246847
Short name T100
Test name
Test status
Simulation time 13234220 ps
CPU time 0.91 seconds
Started Mar 03 02:46:09 PM PST 24
Finished Mar 03 02:46:10 PM PST 24
Peak memory 214464 kb
Host smart-34766f6d-d26f-4cba-97e8-1d160b1c1728
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54246847 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.54246847
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/106.edn_genbits.3310264151
Short name T37
Test name
Test status
Simulation time 490597996 ps
CPU time 5.25 seconds
Started Mar 03 02:46:32 PM PST 24
Finished Mar 03 02:46:37 PM PST 24
Peak memory 218324 kb
Host smart-b1f40989-ca01-4b46-acde-c54fe949d695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310264151 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3310264151
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3536091465
Short name T549
Test name
Test status
Simulation time 69174957 ps
CPU time 1.23 seconds
Started Mar 03 02:45:02 PM PST 24
Finished Mar 03 02:45:04 PM PST 24
Peak memory 214568 kb
Host smart-6dd4faef-4f83-437b-838f-763136f4a4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536091465 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3536091465
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/40.edn_genbits.1392130776
Short name T499
Test name
Test status
Simulation time 29156790 ps
CPU time 1.27 seconds
Started Mar 03 02:45:54 PM PST 24
Finished Mar 03 02:45:56 PM PST 24
Peak memory 215284 kb
Host smart-2682a7e2-bd02-4d97-9288-e0866aca9999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392130776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1392130776
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_disable.3851719354
Short name T167
Test name
Test status
Simulation time 61451269 ps
CPU time 0.85 seconds
Started Mar 03 02:46:07 PM PST 24
Finished Mar 03 02:46:08 PM PST 24
Peak memory 214612 kb
Host smart-498bff66-8b8d-4319-aa5f-0cc3305a56fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851719354 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.3851719354
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/27.edn_alert.1480364621
Short name T526
Test name
Test status
Simulation time 64102428 ps
CPU time 1.2 seconds
Started Mar 03 02:45:26 PM PST 24
Finished Mar 03 02:45:27 PM PST 24
Peak memory 214564 kb
Host smart-97a48f79-32b9-48cc-9f32-7c2928f48fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480364621 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1480364621
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/11.edn_disable.2567689684
Short name T121
Test name
Test status
Simulation time 32566939 ps
CPU time 0.81 seconds
Started Mar 03 02:44:57 PM PST 24
Finished Mar 03 02:44:58 PM PST 24
Peak memory 214616 kb
Host smart-0aca86cd-e6e8-4342-992c-9aef2ad3a457
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567689684 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2567689684
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.2180917475
Short name T94
Test name
Test status
Simulation time 40227764 ps
CPU time 1.38 seconds
Started Mar 03 02:45:09 PM PST 24
Finished Mar 03 02:45:10 PM PST 24
Peak memory 215320 kb
Host smart-e64a2f4e-4e8f-438f-b6a2-8ede02a52bc3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180917475 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.2180917475
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_disable.2002257192
Short name T126
Test name
Test status
Simulation time 36105219 ps
CPU time 0.82 seconds
Started Mar 03 02:45:14 PM PST 24
Finished Mar 03 02:45:14 PM PST 24
Peak memory 214624 kb
Host smart-d8b6e7b5-72b3-4e3e-a217-f87c7cd53e70
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002257192 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2002257192
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable.2903630238
Short name T170
Test name
Test status
Simulation time 20486058 ps
CPU time 0.91 seconds
Started Mar 03 02:45:27 PM PST 24
Finished Mar 03 02:45:28 PM PST 24
Peak memory 214684 kb
Host smart-07c7fdef-a5e4-4e4f-bca1-e9153c8b80eb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903630238 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.2903630238
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.620560476
Short name T81
Test name
Test status
Simulation time 43810025 ps
CPU time 1.17 seconds
Started Mar 03 02:45:40 PM PST 24
Finished Mar 03 02:45:42 PM PST 24
Peak memory 215344 kb
Host smart-22ed94b2-cdd5-4d7e-8f09-bf62a79e4768
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620560476 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di
sable_auto_req_mode.620560476
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.1966355631
Short name T85
Test name
Test status
Simulation time 216901889 ps
CPU time 1.06 seconds
Started Mar 03 02:45:40 PM PST 24
Finished Mar 03 02:45:41 PM PST 24
Peak memory 215208 kb
Host smart-d40fbda7-e529-4e7e-bd23-c8eaa55138dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966355631 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.1966355631
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_disable.3962790756
Short name T125
Test name
Test status
Simulation time 11377537 ps
CPU time 0.87 seconds
Started Mar 03 02:46:09 PM PST 24
Finished Mar 03 02:46:10 PM PST 24
Peak memory 214636 kb
Host smart-5be8e9d6-9200-422c-bb3c-4f83c94d4ec3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962790756 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.3962790756
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/16.edn_alert_test.2639873552
Short name T335
Test name
Test status
Simulation time 45546883 ps
CPU time 0.87 seconds
Started Mar 03 02:45:07 PM PST 24
Finished Mar 03 02:45:09 PM PST 24
Peak memory 205884 kb
Host smart-dd8ded7d-2671-4da1-b57a-813b23f85ef9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639873552 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.2639873552
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/154.edn_genbits.1967002945
Short name T264
Test name
Test status
Simulation time 68659790 ps
CPU time 1.04 seconds
Started Mar 03 02:46:41 PM PST 24
Finished Mar 03 02:46:42 PM PST 24
Peak memory 215268 kb
Host smart-451b88f8-f847-4209-90c4-d9a69b733221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967002945 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.1967002945
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_regwen.312171858
Short name T254
Test name
Test status
Simulation time 35742197 ps
CPU time 0.89 seconds
Started Mar 03 02:44:48 PM PST 24
Finished Mar 03 02:44:49 PM PST 24
Peak memory 205892 kb
Host smart-f9438801-7b53-4398-8447-0ec5d53bdedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312171858 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.312171858
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/207.edn_genbits.642142291
Short name T38
Test name
Test status
Simulation time 42154718 ps
CPU time 1.51 seconds
Started Mar 03 02:46:51 PM PST 24
Finished Mar 03 02:46:53 PM PST 24
Peak memory 218068 kb
Host smart-976a90d4-e507-4b21-8e72-eddc01838f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642142291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.642142291
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_alert.1919315955
Short name T221
Test name
Test status
Simulation time 27198881 ps
CPU time 1.15 seconds
Started Mar 03 02:46:02 PM PST 24
Finished Mar 03 02:46:04 PM PST 24
Peak memory 214512 kb
Host smart-32c2e073-935d-4f07-805b-b0173cd2f75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919315955 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1919315955
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/132.edn_genbits.634992521
Short name T28
Test name
Test status
Simulation time 91946126 ps
CPU time 1.37 seconds
Started Mar 03 02:46:37 PM PST 24
Finished Mar 03 02:46:38 PM PST 24
Peak memory 216776 kb
Host smart-00ca8d6b-2457-4cdf-9ef5-cd59bd386c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634992521 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.634992521
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3384319998
Short name T141
Test name
Test status
Simulation time 35645543 ps
CPU time 0.88 seconds
Started Mar 03 02:44:32 PM PST 24
Finished Mar 03 02:44:33 PM PST 24
Peak memory 214236 kb
Host smart-281b560b-16a8-4ad9-befe-d5256ff83dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384319998 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3384319998
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/9.edn_err.889423604
Short name T166
Test name
Test status
Simulation time 20676530 ps
CPU time 1.06 seconds
Started Mar 03 02:44:53 PM PST 24
Finished Mar 03 02:44:54 PM PST 24
Peak memory 218316 kb
Host smart-21335a9d-c622-49fa-bc90-523060566f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889423604 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.889423604
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/121.edn_genbits.168091849
Short name T578
Test name
Test status
Simulation time 99098035 ps
CPU time 1.37 seconds
Started Mar 03 02:46:34 PM PST 24
Finished Mar 03 02:46:36 PM PST 24
Peak memory 216552 kb
Host smart-454d3470-50c9-43f2-bfd6-3f497ce27e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168091849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.168091849
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert.2371930464
Short name T257
Test name
Test status
Simulation time 51899427 ps
CPU time 1.21 seconds
Started Mar 03 02:44:30 PM PST 24
Finished Mar 03 02:44:31 PM PST 24
Peak memory 214560 kb
Host smart-834bdcfe-3a49-4f3b-af7b-d4bd12f35f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371930464 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2371930464
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.3919418002
Short name T523
Test name
Test status
Simulation time 204676327124 ps
CPU time 1441.31 seconds
Started Mar 03 02:44:57 PM PST 24
Finished Mar 03 03:08:59 PM PST 24
Peak memory 223804 kb
Host smart-ea107e9b-69a0-4469-8173-77323ee05dc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919418002 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.3919418002
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/104.edn_genbits.3932187039
Short name T284
Test name
Test status
Simulation time 34407896 ps
CPU time 1.36 seconds
Started Mar 03 02:46:29 PM PST 24
Finished Mar 03 02:46:31 PM PST 24
Peak memory 215324 kb
Host smart-a4dcec04-f8ca-42ee-bd09-cb948e41037d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932187039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3932187039
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.1052302203
Short name T519
Test name
Test status
Simulation time 69158905 ps
CPU time 1.38 seconds
Started Mar 03 02:46:35 PM PST 24
Finished Mar 03 02:46:37 PM PST 24
Peak memory 216508 kb
Host smart-50add4c0-3697-418c-b017-dcc888e91e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052302203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1052302203
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.1081591909
Short name T291
Test name
Test status
Simulation time 10013273646 ps
CPU time 132.06 seconds
Started Mar 03 02:46:38 PM PST 24
Finished Mar 03 02:48:51 PM PST 24
Peak memory 216668 kb
Host smart-b37232ff-7f8c-4d82-91bb-f7665ef2ae9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081591909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.1081591909
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.3947807306
Short name T668
Test name
Test status
Simulation time 66705726 ps
CPU time 1.44 seconds
Started Mar 03 02:46:39 PM PST 24
Finished Mar 03 02:46:40 PM PST 24
Peak memory 216696 kb
Host smart-b9d33185-b48a-4662-8e5c-597c86f6493a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947807306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3947807306
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1285858361
Short name T706
Test name
Test status
Simulation time 219602168 ps
CPU time 1.38 seconds
Started Mar 03 02:45:09 PM PST 24
Finished Mar 03 02:45:11 PM PST 24
Peak memory 214556 kb
Host smart-ca1edc46-0b82-4710-80b3-e9499028d288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285858361 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1285858361
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/198.edn_genbits.174880125
Short name T290
Test name
Test status
Simulation time 50540641 ps
CPU time 2.08 seconds
Started Mar 03 02:46:55 PM PST 24
Finished Mar 03 02:46:57 PM PST 24
Peak memory 216600 kb
Host smart-63559a60-0c85-4d0d-844d-a0231ef4537e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174880125 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.174880125
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.461976797
Short name T236
Test name
Test status
Simulation time 49758427 ps
CPU time 1.17 seconds
Started Mar 03 02:44:35 PM PST 24
Finished Mar 03 02:44:36 PM PST 24
Peak memory 214576 kb
Host smart-8eb6230e-bf6a-4913-b033-fba08ecf0185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461976797 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.461976797
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/201.edn_genbits.2600657926
Short name T270
Test name
Test status
Simulation time 86984822 ps
CPU time 1.24 seconds
Started Mar 03 02:46:52 PM PST 24
Finished Mar 03 02:46:53 PM PST 24
Peak memory 216988 kb
Host smart-b5e86edf-9720-4653-8567-4ac25eadc9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600657926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2600657926
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3640788744
Short name T63
Test name
Test status
Simulation time 115026641 ps
CPU time 2.53 seconds
Started Mar 03 02:46:54 PM PST 24
Finished Mar 03 02:46:56 PM PST 24
Peak memory 218412 kb
Host smart-ad9e6632-eb81-4d02-ad85-76539a62ab98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640788744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3640788744
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.426360670
Short name T286
Test name
Test status
Simulation time 55181268 ps
CPU time 2 seconds
Started Mar 03 02:46:54 PM PST 24
Finished Mar 03 02:46:56 PM PST 24
Peak memory 216612 kb
Host smart-2040793f-2982-4b82-952d-3fb520e8a0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426360670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.426360670
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_alert.1400489010
Short name T75
Test name
Test status
Simulation time 86736850 ps
CPU time 1.16 seconds
Started Mar 03 02:45:44 PM PST 24
Finished Mar 03 02:45:45 PM PST 24
Peak memory 214580 kb
Host smart-e0282dd4-7c02-449f-a485-c00e552851a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400489010 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.1400489010
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2382143519
Short name T153
Test name
Test status
Simulation time 147882158078 ps
CPU time 297.86 seconds
Started Mar 03 02:44:33 PM PST 24
Finished Mar 03 02:49:31 PM PST 24
Peak memory 218092 kb
Host smart-7c1ff82c-926f-4694-a011-f85273ae3cbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382143519 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2382143519
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.edn_intr.3310542955
Short name T139
Test name
Test status
Simulation time 23047655 ps
CPU time 0.94 seconds
Started Mar 03 02:45:29 PM PST 24
Finished Mar 03 02:45:32 PM PST 24
Peak memory 214496 kb
Host smart-2f578643-c2c2-4492-9630-dc1ddcffa413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310542955 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3310542955
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/147.edn_genbits.2324290106
Short name T13
Test name
Test status
Simulation time 98189380 ps
CPU time 1.56 seconds
Started Mar 03 02:46:39 PM PST 24
Finished Mar 03 02:46:41 PM PST 24
Peak memory 218164 kb
Host smart-a798006b-50c6-4922-b4be-a82df7410b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324290106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2324290106
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_disable.4202332741
Short name T99
Test name
Test status
Simulation time 30450902 ps
CPU time 0.82 seconds
Started Mar 03 02:44:58 PM PST 24
Finished Mar 03 02:44:59 PM PST 24
Peak memory 214356 kb
Host smart-8d7027d2-6816-4b27-97e9-4bdfb1a3e5ae
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202332741 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.4202332741
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.4222242057
Short name T204
Test name
Test status
Simulation time 568605420 ps
CPU time 1.63 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:40:24 PM PST 24
Peak memory 206220 kb
Host smart-a8216ae3-1fcd-4846-9d62-0618de739eb7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222242057 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.4222242057
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.3498557467
Short name T900
Test name
Test status
Simulation time 1013623954 ps
CPU time 6.22 seconds
Started Mar 03 12:40:23 PM PST 24
Finished Mar 03 12:40:29 PM PST 24
Peak memory 206216 kb
Host smart-013ca7c0-a782-4ed6-be5d-13726fd5c3f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498557467 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.3498557467
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2112807491
Short name T930
Test name
Test status
Simulation time 105854506 ps
CPU time 0.88 seconds
Started Mar 03 12:40:27 PM PST 24
Finished Mar 03 12:40:28 PM PST 24
Peak memory 206104 kb
Host smart-30013139-b4a0-4232-a681-912f2c52081d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112807491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2112807491
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.4009222184
Short name T916
Test name
Test status
Simulation time 30125331 ps
CPU time 1.32 seconds
Started Mar 03 12:40:21 PM PST 24
Finished Mar 03 12:40:23 PM PST 24
Peak memory 214556 kb
Host smart-3b4c8d34-ca1e-4c22-93b5-3c3c5a321a40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009222184 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.4009222184
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1703547484
Short name T905
Test name
Test status
Simulation time 21895431 ps
CPU time 0.82 seconds
Started Mar 03 12:40:13 PM PST 24
Finished Mar 03 12:40:14 PM PST 24
Peak memory 206108 kb
Host smart-2ab6e768-5a08-4235-b9f1-e41b1486c07e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703547484 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1703547484
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.3602566234
Short name T934
Test name
Test status
Simulation time 13233618 ps
CPU time 0.86 seconds
Started Mar 03 12:40:20 PM PST 24
Finished Mar 03 12:40:21 PM PST 24
Peak memory 206120 kb
Host smart-6b65814f-8571-46fc-a576-75563085fdec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602566234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.3602566234
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.569454892
Short name T215
Test name
Test status
Simulation time 23553718 ps
CPU time 1.09 seconds
Started Mar 03 12:40:34 PM PST 24
Finished Mar 03 12:40:36 PM PST 24
Peak memory 206216 kb
Host smart-572d6cb3-e400-4f21-bad2-c499454550ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569454892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_out
standing.569454892
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1391405842
Short name T878
Test name
Test status
Simulation time 89051453 ps
CPU time 3.18 seconds
Started Mar 03 12:40:28 PM PST 24
Finished Mar 03 12:40:31 PM PST 24
Peak memory 214496 kb
Host smart-7b470619-11bd-4bde-b8f0-07384c5ee15b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391405842 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1391405842
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4086359331
Short name T962
Test name
Test status
Simulation time 172805690 ps
CPU time 1.35 seconds
Started Mar 03 12:40:05 PM PST 24
Finished Mar 03 12:40:06 PM PST 24
Peak memory 206172 kb
Host smart-06201697-2dad-4ae6-b590-e8100c636e6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086359331 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.4086359331
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.911575602
Short name T212
Test name
Test status
Simulation time 35615851 ps
CPU time 1.44 seconds
Started Mar 03 12:40:14 PM PST 24
Finished Mar 03 12:40:17 PM PST 24
Peak memory 206120 kb
Host smart-b705dd61-c536-44b2-aec2-ff433a636f0f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911575602 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.911575602
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.2731782056
Short name T213
Test name
Test status
Simulation time 184308199 ps
CPU time 3.18 seconds
Started Mar 03 12:40:30 PM PST 24
Finished Mar 03 12:40:34 PM PST 24
Peak memory 206188 kb
Host smart-6ac4f088-ea1d-498a-bbcf-27c788a3ef83
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731782056 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.2731782056
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1131070044
Short name T198
Test name
Test status
Simulation time 19647996 ps
CPU time 0.95 seconds
Started Mar 03 12:40:33 PM PST 24
Finished Mar 03 12:40:34 PM PST 24
Peak memory 206216 kb
Host smart-776a747b-b843-4f33-8b29-e97dc4af01c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131070044 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1131070044
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2052363484
Short name T874
Test name
Test status
Simulation time 73297036 ps
CPU time 1.33 seconds
Started Mar 03 12:40:28 PM PST 24
Finished Mar 03 12:40:29 PM PST 24
Peak memory 214456 kb
Host smart-5df3f729-85a3-4fbc-8a6f-02da27c8b816
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052363484 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2052363484
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3738015317
Short name T211
Test name
Test status
Simulation time 25188611 ps
CPU time 0.88 seconds
Started Mar 03 12:40:24 PM PST 24
Finished Mar 03 12:40:25 PM PST 24
Peak memory 206108 kb
Host smart-b697e22e-4403-4802-a48e-b6dea69b4b1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738015317 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3738015317
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2874106162
Short name T847
Test name
Test status
Simulation time 125488577 ps
CPU time 0.96 seconds
Started Mar 03 12:40:42 PM PST 24
Finished Mar 03 12:40:43 PM PST 24
Peak memory 206108 kb
Host smart-7c50adf4-5a39-4e6d-9a09-062aed8f4474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874106162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2874106162
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.3900747166
Short name T862
Test name
Test status
Simulation time 68671191 ps
CPU time 1.03 seconds
Started Mar 03 12:40:40 PM PST 24
Finished Mar 03 12:40:41 PM PST 24
Peak memory 206204 kb
Host smart-65910069-fa1e-4e4b-80ab-4a01498ac685
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900747166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.3900747166
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.1810585858
Short name T855
Test name
Test status
Simulation time 257495653 ps
CPU time 3.15 seconds
Started Mar 03 12:40:20 PM PST 24
Finished Mar 03 12:40:23 PM PST 24
Peak memory 214364 kb
Host smart-fa3569e7-2173-412e-9b20-1fd6c3bdc30e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810585858 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.1810585858
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.3744998463
Short name T887
Test name
Test status
Simulation time 194645525 ps
CPU time 2.61 seconds
Started Mar 03 12:40:19 PM PST 24
Finished Mar 03 12:40:22 PM PST 24
Peak memory 206040 kb
Host smart-5067c7b3-ee07-4e97-a9b6-6058864e0161
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744998463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.3744998463
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.584195273
Short name T929
Test name
Test status
Simulation time 98314923 ps
CPU time 1.17 seconds
Started Mar 03 12:40:28 PM PST 24
Finished Mar 03 12:40:30 PM PST 24
Peak memory 214552 kb
Host smart-a3dbd651-4817-4811-927d-522793d7a0ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584195273 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.584195273
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.1505330322
Short name T880
Test name
Test status
Simulation time 13903120 ps
CPU time 0.94 seconds
Started Mar 03 12:41:04 PM PST 24
Finished Mar 03 12:41:05 PM PST 24
Peak memory 206200 kb
Host smart-1ac03da8-860c-48bb-9547-c3a05a425728
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505330322 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.1505330322
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.1867568125
Short name T888
Test name
Test status
Simulation time 22160593 ps
CPU time 0.85 seconds
Started Mar 03 12:40:25 PM PST 24
Finished Mar 03 12:40:26 PM PST 24
Peak memory 206108 kb
Host smart-1e45845a-3607-4474-a5e4-db423be32ef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867568125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.1867568125
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2310913924
Short name T891
Test name
Test status
Simulation time 17339200 ps
CPU time 1.02 seconds
Started Mar 03 12:40:56 PM PST 24
Finished Mar 03 12:40:57 PM PST 24
Peak memory 206228 kb
Host smart-fe07a201-3656-4adc-83c6-d99f2b2f85b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310913924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2310913924
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3185432687
Short name T947
Test name
Test status
Simulation time 80428789 ps
CPU time 1.52 seconds
Started Mar 03 12:40:56 PM PST 24
Finished Mar 03 12:40:57 PM PST 24
Peak memory 214384 kb
Host smart-7868d054-57ed-4939-b787-c0607814814f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185432687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3185432687
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.2168652652
Short name T245
Test name
Test status
Simulation time 475134768 ps
CPU time 2.22 seconds
Started Mar 03 12:40:43 PM PST 24
Finished Mar 03 12:40:45 PM PST 24
Peak memory 206188 kb
Host smart-00a38d71-5e4a-46f3-be9c-57871efdf0ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168652652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.2168652652
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.740191026
Short name T881
Test name
Test status
Simulation time 36339434 ps
CPU time 1.54 seconds
Started Mar 03 12:40:26 PM PST 24
Finished Mar 03 12:40:28 PM PST 24
Peak memory 214428 kb
Host smart-84737177-553b-4b61-9384-98088078dbb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740191026 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.740191026
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3074058675
Short name T886
Test name
Test status
Simulation time 52200975 ps
CPU time 0.95 seconds
Started Mar 03 12:40:45 PM PST 24
Finished Mar 03 12:40:46 PM PST 24
Peak memory 206092 kb
Host smart-94907369-12b6-4742-a16f-0e767158965f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074058675 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3074058675
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2351185343
Short name T851
Test name
Test status
Simulation time 20835688 ps
CPU time 0.9 seconds
Started Mar 03 12:40:49 PM PST 24
Finished Mar 03 12:40:50 PM PST 24
Peak memory 206112 kb
Host smart-abb24d5b-6a9b-41c3-9e80-aa6c461ee125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351185343 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2351185343
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.434763645
Short name T203
Test name
Test status
Simulation time 27624477 ps
CPU time 1.21 seconds
Started Mar 03 12:40:24 PM PST 24
Finished Mar 03 12:40:26 PM PST 24
Peak memory 206176 kb
Host smart-a1f0cd49-9548-4737-af3c-558547f46e8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434763645 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou
tstanding.434763645
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.835602477
Short name T834
Test name
Test status
Simulation time 1588878843 ps
CPU time 4.32 seconds
Started Mar 03 12:40:29 PM PST 24
Finished Mar 03 12:40:33 PM PST 24
Peak memory 214388 kb
Host smart-8f64beed-3b2d-4f1c-8390-6683627f06b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835602477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.835602477
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1795315867
Short name T917
Test name
Test status
Simulation time 84897152 ps
CPU time 1.5 seconds
Started Mar 03 12:40:26 PM PST 24
Finished Mar 03 12:40:28 PM PST 24
Peak memory 205396 kb
Host smart-16f289f4-9799-486c-a185-eb66162b0a08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795315867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1795315867
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1099499906
Short name T884
Test name
Test status
Simulation time 60795388 ps
CPU time 1.3 seconds
Started Mar 03 12:40:41 PM PST 24
Finished Mar 03 12:40:43 PM PST 24
Peak memory 216748 kb
Host smart-30e60828-b5d8-451d-85a3-d99da07ca52a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099499906 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1099499906
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.1396999099
Short name T216
Test name
Test status
Simulation time 12053605 ps
CPU time 0.89 seconds
Started Mar 03 12:40:40 PM PST 24
Finished Mar 03 12:40:41 PM PST 24
Peak memory 206108 kb
Host smart-ce527e38-dbe6-470e-a036-fc64467e8145
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396999099 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.1396999099
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.320728539
Short name T868
Test name
Test status
Simulation time 14208004 ps
CPU time 0.87 seconds
Started Mar 03 12:40:37 PM PST 24
Finished Mar 03 12:40:39 PM PST 24
Peak memory 206172 kb
Host smart-675547be-58e0-4922-a6e1-ee9d56849cee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320728539 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.320728539
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.821218736
Short name T865
Test name
Test status
Simulation time 25147441 ps
CPU time 1.19 seconds
Started Mar 03 12:40:37 PM PST 24
Finished Mar 03 12:40:39 PM PST 24
Peak memory 206172 kb
Host smart-f4d96207-0510-442d-b883-5c08647bb153
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821218736 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.821218736
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.405532435
Short name T965
Test name
Test status
Simulation time 83974069 ps
CPU time 1.58 seconds
Started Mar 03 12:40:29 PM PST 24
Finished Mar 03 12:40:31 PM PST 24
Peak memory 214432 kb
Host smart-9d782b97-ca99-401f-9cd8-c484a80c657d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405532435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.405532435
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.2765648449
Short name T242
Test name
Test status
Simulation time 280202420 ps
CPU time 2.21 seconds
Started Mar 03 12:40:34 PM PST 24
Finished Mar 03 12:40:36 PM PST 24
Peak memory 206208 kb
Host smart-207bb8d7-24be-47e7-b923-8daa6b8f7426
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765648449 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.2765648449
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2147039105
Short name T936
Test name
Test status
Simulation time 14692100 ps
CPU time 1 seconds
Started Mar 03 12:40:47 PM PST 24
Finished Mar 03 12:40:49 PM PST 24
Peak memory 206264 kb
Host smart-a08daf81-bcff-41e1-9215-3bba750ee82b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147039105 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2147039105
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.2661597318
Short name T206
Test name
Test status
Simulation time 54236216 ps
CPU time 0.9 seconds
Started Mar 03 12:40:24 PM PST 24
Finished Mar 03 12:40:30 PM PST 24
Peak memory 206088 kb
Host smart-b43ec205-76ef-4a51-891e-370b7b532bd2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661597318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.2661597318
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.2480305659
Short name T951
Test name
Test status
Simulation time 47362369 ps
CPU time 0.85 seconds
Started Mar 03 12:40:36 PM PST 24
Finished Mar 03 12:40:37 PM PST 24
Peak memory 206088 kb
Host smart-54b49d09-bd6b-44af-abc3-5ea66bd004ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480305659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.2480305659
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3919808374
Short name T877
Test name
Test status
Simulation time 116511851 ps
CPU time 1.58 seconds
Started Mar 03 12:40:25 PM PST 24
Finished Mar 03 12:40:27 PM PST 24
Peak memory 206124 kb
Host smart-4ef671bd-1a4f-474c-b9dd-8766002da18c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919808374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3919808374
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.813866921
Short name T879
Test name
Test status
Simulation time 100440938 ps
CPU time 1.91 seconds
Started Mar 03 12:40:59 PM PST 24
Finished Mar 03 12:41:01 PM PST 24
Peak memory 214364 kb
Host smart-b4f0c9e8-642e-497c-b150-8640abb48186
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813866921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.813866921
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2566169697
Short name T890
Test name
Test status
Simulation time 49337140 ps
CPU time 1.63 seconds
Started Mar 03 12:40:26 PM PST 24
Finished Mar 03 12:40:27 PM PST 24
Peak memory 206180 kb
Host smart-94eff4f8-e765-4fd0-a245-8ca18b925686
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566169697 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2566169697
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1547604566
Short name T943
Test name
Test status
Simulation time 66838583 ps
CPU time 1.72 seconds
Started Mar 03 12:40:44 PM PST 24
Finished Mar 03 12:40:46 PM PST 24
Peak memory 214512 kb
Host smart-83318663-42de-4f83-97b6-9bc91f245b50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547604566 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1547604566
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.1324760169
Short name T948
Test name
Test status
Simulation time 13581171 ps
CPU time 0.91 seconds
Started Mar 03 12:40:26 PM PST 24
Finished Mar 03 12:40:28 PM PST 24
Peak memory 206112 kb
Host smart-7ce45520-0999-42c1-9b76-d2ce089e1563
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324760169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.1324760169
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3877840417
Short name T864
Test name
Test status
Simulation time 84186649 ps
CPU time 0.85 seconds
Started Mar 03 12:40:46 PM PST 24
Finished Mar 03 12:40:47 PM PST 24
Peak memory 206196 kb
Host smart-978e0433-2f5a-47d7-bb65-0ef6d67121c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877840417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3877840417
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.506219122
Short name T910
Test name
Test status
Simulation time 69716470 ps
CPU time 1.05 seconds
Started Mar 03 12:40:54 PM PST 24
Finished Mar 03 12:40:55 PM PST 24
Peak memory 206208 kb
Host smart-5fab9391-f2ce-447a-8c36-b65902922a78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506219122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.506219122
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.2675923522
Short name T921
Test name
Test status
Simulation time 31991572 ps
CPU time 1.93 seconds
Started Mar 03 12:40:25 PM PST 24
Finished Mar 03 12:40:27 PM PST 24
Peak memory 214408 kb
Host smart-f8895c6c-a492-4d85-8084-9a77c14c66e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675923522 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.2675923522
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.108425912
Short name T931
Test name
Test status
Simulation time 82012603 ps
CPU time 1.23 seconds
Started Mar 03 12:40:50 PM PST 24
Finished Mar 03 12:40:52 PM PST 24
Peak memory 214576 kb
Host smart-bb9dc524-1474-4d2c-adae-893938297d02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108425912 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.108425912
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1494058248
Short name T901
Test name
Test status
Simulation time 36278616 ps
CPU time 0.78 seconds
Started Mar 03 12:40:24 PM PST 24
Finished Mar 03 12:40:25 PM PST 24
Peak memory 205884 kb
Host smart-c13fbdd4-0cfe-476b-84f8-6ed96e2ff4fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494058248 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1494058248
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1133196251
Short name T957
Test name
Test status
Simulation time 19026287 ps
CPU time 0.78 seconds
Started Mar 03 12:40:29 PM PST 24
Finished Mar 03 12:40:30 PM PST 24
Peak memory 205940 kb
Host smart-7606041c-abec-4365-ac74-3ab3d62a8170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133196251 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1133196251
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.3547236218
Short name T849
Test name
Test status
Simulation time 31233710 ps
CPU time 1.07 seconds
Started Mar 03 12:40:44 PM PST 24
Finished Mar 03 12:40:45 PM PST 24
Peak memory 206176 kb
Host smart-4faaa2a7-1a00-407b-9ffb-fe2f64455b2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547236218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.3547236218
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.3307925886
Short name T935
Test name
Test status
Simulation time 21668400 ps
CPU time 1.51 seconds
Started Mar 03 12:40:29 PM PST 24
Finished Mar 03 12:40:36 PM PST 24
Peak memory 214436 kb
Host smart-ee81c058-0fbf-4d96-b90e-55c9087a76fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307925886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.3307925886
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.846017458
Short name T233
Test name
Test status
Simulation time 301692779 ps
CPU time 2.23 seconds
Started Mar 03 12:41:05 PM PST 24
Finished Mar 03 12:41:07 PM PST 24
Peak memory 206100 kb
Host smart-0884b58c-8de1-4879-b5b2-c512ef420ede
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846017458 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.846017458
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2787828919
Short name T953
Test name
Test status
Simulation time 73188627 ps
CPU time 1.44 seconds
Started Mar 03 12:40:26 PM PST 24
Finished Mar 03 12:40:28 PM PST 24
Peak memory 214372 kb
Host smart-6a4abd38-ba0e-488b-b086-454b1c1347d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787828919 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2787828919
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.2833947607
Short name T199
Test name
Test status
Simulation time 12653521 ps
CPU time 0.88 seconds
Started Mar 03 12:40:21 PM PST 24
Finished Mar 03 12:40:22 PM PST 24
Peak memory 206112 kb
Host smart-8d6ee600-5679-474c-8700-6b9cf89dfde4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833947607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.2833947607
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.456548673
Short name T871
Test name
Test status
Simulation time 14080626 ps
CPU time 0.84 seconds
Started Mar 03 12:40:55 PM PST 24
Finished Mar 03 12:40:56 PM PST 24
Peak memory 206128 kb
Host smart-44cfa764-a8d2-43ec-a9de-0f5564ea3ab9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456548673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.456548673
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.3481422975
Short name T918
Test name
Test status
Simulation time 111480557 ps
CPU time 1.33 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:40:23 PM PST 24
Peak memory 206104 kb
Host smart-8036054e-7f5b-4498-8936-528cf1e39bce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481422975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.3481422975
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3736352493
Short name T853
Test name
Test status
Simulation time 45507452 ps
CPU time 2.86 seconds
Started Mar 03 12:40:28 PM PST 24
Finished Mar 03 12:40:32 PM PST 24
Peak memory 214560 kb
Host smart-26fc5938-fc6a-4b4c-9e8f-c8ac0772fc00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736352493 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3736352493
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.683761867
Short name T859
Test name
Test status
Simulation time 93896855 ps
CPU time 1.58 seconds
Started Mar 03 12:40:27 PM PST 24
Finished Mar 03 12:40:29 PM PST 24
Peak memory 206116 kb
Host smart-c325c816-034f-4d6e-ab57-f0f072a7b587
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683761867 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.683761867
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.572130302
Short name T867
Test name
Test status
Simulation time 18336247 ps
CPU time 1.2 seconds
Started Mar 03 12:40:38 PM PST 24
Finished Mar 03 12:40:39 PM PST 24
Peak memory 215936 kb
Host smart-c8cca5f1-e44f-4bfe-b2d8-2119d693b4a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572130302 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.572130302
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.4288375583
Short name T200
Test name
Test status
Simulation time 12805714 ps
CPU time 0.83 seconds
Started Mar 03 12:40:40 PM PST 24
Finished Mar 03 12:40:41 PM PST 24
Peak memory 206196 kb
Host smart-6cd12cf3-4e15-437c-905a-d4a700f7dbd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288375583 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.4288375583
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.1254202472
Short name T848
Test name
Test status
Simulation time 14313963 ps
CPU time 0.87 seconds
Started Mar 03 12:40:53 PM PST 24
Finished Mar 03 12:40:54 PM PST 24
Peak memory 206192 kb
Host smart-5ea6d771-04ab-47cc-a2ec-e1b84376dc66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254202472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.1254202472
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1226085557
Short name T946
Test name
Test status
Simulation time 146955972 ps
CPU time 1.36 seconds
Started Mar 03 12:40:51 PM PST 24
Finished Mar 03 12:40:53 PM PST 24
Peak memory 206140 kb
Host smart-01c4a9cb-e8ac-4bcf-82b7-7d8c3cc4589a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226085557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1226085557
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.2775247823
Short name T920
Test name
Test status
Simulation time 120431617 ps
CPU time 4.53 seconds
Started Mar 03 12:40:55 PM PST 24
Finished Mar 03 12:41:00 PM PST 24
Peak memory 214484 kb
Host smart-b97efbd0-f325-4aa3-9cc7-e0978853bae5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775247823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.2775247823
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.1898333066
Short name T959
Test name
Test status
Simulation time 102278049 ps
CPU time 2.56 seconds
Started Mar 03 12:40:38 PM PST 24
Finished Mar 03 12:40:40 PM PST 24
Peak memory 206180 kb
Host smart-e855334d-fef9-4ce6-b140-8bbb0af86363
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898333066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.1898333066
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2596624596
Short name T856
Test name
Test status
Simulation time 59496015 ps
CPU time 1.18 seconds
Started Mar 03 12:40:58 PM PST 24
Finished Mar 03 12:40:59 PM PST 24
Peak memory 214372 kb
Host smart-f3726b21-4d54-4bc5-a480-b734bbeb94ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596624596 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2596624596
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2817695528
Short name T220
Test name
Test status
Simulation time 89088831 ps
CPU time 0.83 seconds
Started Mar 03 12:40:48 PM PST 24
Finished Mar 03 12:40:49 PM PST 24
Peak memory 206060 kb
Host smart-284711e1-18ea-4411-976d-419ebcc1140e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817695528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2817695528
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.1287241682
Short name T838
Test name
Test status
Simulation time 22573387 ps
CPU time 0.84 seconds
Started Mar 03 12:40:37 PM PST 24
Finished Mar 03 12:40:38 PM PST 24
Peak memory 206176 kb
Host smart-f05a90dc-1640-4963-9412-c16c5f32b94c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287241682 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.1287241682
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3378682354
Short name T926
Test name
Test status
Simulation time 313564672 ps
CPU time 1.05 seconds
Started Mar 03 12:40:38 PM PST 24
Finished Mar 03 12:40:39 PM PST 24
Peak memory 206124 kb
Host smart-f35b4197-7684-4fe8-9f27-a38f1f33f472
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378682354 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3378682354
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3994286036
Short name T897
Test name
Test status
Simulation time 441665708 ps
CPU time 1.71 seconds
Started Mar 03 12:40:34 PM PST 24
Finished Mar 03 12:40:36 PM PST 24
Peak memory 214388 kb
Host smart-f3a4a666-0312-4880-87f2-9680f8c84612
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994286036 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3994286036
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3654461734
Short name T244
Test name
Test status
Simulation time 161801324 ps
CPU time 2.27 seconds
Started Mar 03 12:40:42 PM PST 24
Finished Mar 03 12:40:45 PM PST 24
Peak memory 206288 kb
Host smart-4fb5179e-2847-4fe0-a7e6-febb760307dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654461734 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3654461734
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3153481700
Short name T937
Test name
Test status
Simulation time 111451710 ps
CPU time 1.43 seconds
Started Mar 03 12:41:05 PM PST 24
Finished Mar 03 12:41:06 PM PST 24
Peak memory 214348 kb
Host smart-8cd1e39f-f38e-44d7-8de8-531252694af3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153481700 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3153481700
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3016319446
Short name T907
Test name
Test status
Simulation time 51981482 ps
CPU time 0.84 seconds
Started Mar 03 12:40:52 PM PST 24
Finished Mar 03 12:40:53 PM PST 24
Peak memory 206112 kb
Host smart-aa875c0d-9f4d-4883-90b6-1617adb385ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016319446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3016319446
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2042746978
Short name T942
Test name
Test status
Simulation time 10506067 ps
CPU time 0.81 seconds
Started Mar 03 12:40:59 PM PST 24
Finished Mar 03 12:41:00 PM PST 24
Peak memory 206124 kb
Host smart-c9ce9930-11ff-4b1d-b59d-6d39e9183d52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042746978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2042746978
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.1986536115
Short name T909
Test name
Test status
Simulation time 129356658 ps
CPU time 0.96 seconds
Started Mar 03 12:40:54 PM PST 24
Finished Mar 03 12:40:55 PM PST 24
Peak memory 206208 kb
Host smart-9071779c-c8e5-4988-a221-52c49cda3671
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986536115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.1986536115
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3319509644
Short name T966
Test name
Test status
Simulation time 265203128 ps
CPU time 4.08 seconds
Started Mar 03 12:40:27 PM PST 24
Finished Mar 03 12:40:31 PM PST 24
Peak memory 214384 kb
Host smart-021caa56-78a6-4f41-8ff0-98c3da4cf23b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319509644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3319509644
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.907423154
Short name T889
Test name
Test status
Simulation time 179919129 ps
CPU time 1.57 seconds
Started Mar 03 12:40:37 PM PST 24
Finished Mar 03 12:40:39 PM PST 24
Peak memory 206136 kb
Host smart-9af4dca9-5ea6-4a19-823a-a941549d03c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907423154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.907423154
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.566232589
Short name T209
Test name
Test status
Simulation time 40559694 ps
CPU time 1.54 seconds
Started Mar 03 12:40:43 PM PST 24
Finished Mar 03 12:40:45 PM PST 24
Peak memory 206252 kb
Host smart-a00377ee-8223-4420-9c5a-375368955149
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566232589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.566232589
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2439830600
Short name T925
Test name
Test status
Simulation time 209857469 ps
CPU time 5.16 seconds
Started Mar 03 12:40:20 PM PST 24
Finished Mar 03 12:40:25 PM PST 24
Peak memory 206100 kb
Host smart-0c1a01e9-3b1f-4049-bd3b-84a162079641
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439830600 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2439830600
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.1004855984
Short name T933
Test name
Test status
Simulation time 49926868 ps
CPU time 0.89 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:40:24 PM PST 24
Peak memory 206440 kb
Host smart-d5b6c42e-6e27-4d04-8c1f-df01b1761695
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004855984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.1004855984
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.3701012680
Short name T844
Test name
Test status
Simulation time 447150490 ps
CPU time 1.58 seconds
Started Mar 03 12:40:41 PM PST 24
Finished Mar 03 12:40:42 PM PST 24
Peak memory 214364 kb
Host smart-0868f0b0-517a-436b-8d88-6d62872788ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701012680 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.3701012680
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1517066309
Short name T219
Test name
Test status
Simulation time 14432519 ps
CPU time 0.89 seconds
Started Mar 03 12:40:18 PM PST 24
Finished Mar 03 12:40:19 PM PST 24
Peak memory 206092 kb
Host smart-68b8b80f-1fae-40c8-8f46-7f6176653af5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517066309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1517066309
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.4003503643
Short name T928
Test name
Test status
Simulation time 71734288 ps
CPU time 0.8 seconds
Started Mar 03 12:40:20 PM PST 24
Finished Mar 03 12:40:26 PM PST 24
Peak memory 205964 kb
Host smart-f542b073-defb-4f40-91f0-f9e57d518753
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003503643 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.4003503643
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.3154374955
Short name T866
Test name
Test status
Simulation time 46890535 ps
CPU time 1.28 seconds
Started Mar 03 12:40:27 PM PST 24
Finished Mar 03 12:40:28 PM PST 24
Peak memory 206216 kb
Host smart-4ec9a5bb-0a2d-4145-8910-24dcc51b60c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154374955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.3154374955
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.234815973
Short name T949
Test name
Test status
Simulation time 163134280 ps
CPU time 1.63 seconds
Started Mar 03 12:40:23 PM PST 24
Finished Mar 03 12:40:25 PM PST 24
Peak memory 214436 kb
Host smart-3d2dc2ed-8289-43f0-917d-1c26184e61f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234815973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.234815973
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2825117887
Short name T852
Test name
Test status
Simulation time 281173467 ps
CPU time 2.13 seconds
Started Mar 03 12:40:24 PM PST 24
Finished Mar 03 12:40:27 PM PST 24
Peak memory 206256 kb
Host smart-087efb32-49f9-4a55-85a0-54c036bd0b8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825117887 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2825117887
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.3564257841
Short name T854
Test name
Test status
Simulation time 128468501 ps
CPU time 0.77 seconds
Started Mar 03 12:40:42 PM PST 24
Finished Mar 03 12:40:44 PM PST 24
Peak memory 206056 kb
Host smart-b6a52ad2-9ff8-43f5-9922-65f4e6fc4bd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564257841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.3564257841
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.328038289
Short name T941
Test name
Test status
Simulation time 14810802 ps
CPU time 0.87 seconds
Started Mar 03 12:40:28 PM PST 24
Finished Mar 03 12:40:30 PM PST 24
Peak memory 206112 kb
Host smart-d5a1f32c-4a73-4a02-bb0f-d15107dfa283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328038289 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.328038289
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.392587993
Short name T876
Test name
Test status
Simulation time 28565566 ps
CPU time 0.77 seconds
Started Mar 03 12:40:54 PM PST 24
Finished Mar 03 12:40:55 PM PST 24
Peak memory 205952 kb
Host smart-e4e7446f-4a59-448d-943c-d8023c0b2454
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392587993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.392587993
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3796901880
Short name T873
Test name
Test status
Simulation time 12703205 ps
CPU time 0.87 seconds
Started Mar 03 12:40:31 PM PST 24
Finished Mar 03 12:40:32 PM PST 24
Peak memory 206068 kb
Host smart-394a38b8-3cfb-4ec0-90d5-f279cea450f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796901880 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3796901880
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.3094366754
Short name T885
Test name
Test status
Simulation time 17506955 ps
CPU time 0.79 seconds
Started Mar 03 12:40:49 PM PST 24
Finished Mar 03 12:40:50 PM PST 24
Peak memory 205960 kb
Host smart-702c6e93-9f57-4ae1-9018-840e7f5a2a76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094366754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.3094366754
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.1566509344
Short name T857
Test name
Test status
Simulation time 11362925 ps
CPU time 0.87 seconds
Started Mar 03 12:40:45 PM PST 24
Finished Mar 03 12:40:47 PM PST 24
Peak memory 206116 kb
Host smart-03887383-e185-450d-9fe9-240a69c57b7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566509344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.1566509344
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.155766307
Short name T898
Test name
Test status
Simulation time 11622127 ps
CPU time 0.84 seconds
Started Mar 03 12:40:25 PM PST 24
Finished Mar 03 12:40:26 PM PST 24
Peak memory 206100 kb
Host smart-53e4bf97-5d83-4820-8754-b9d8bdc5e973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155766307 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.155766307
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3838140975
Short name T837
Test name
Test status
Simulation time 14017260 ps
CPU time 0.86 seconds
Started Mar 03 12:40:40 PM PST 24
Finished Mar 03 12:40:41 PM PST 24
Peak memory 206152 kb
Host smart-a21c5c5c-2617-458d-9944-d153f903d7c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838140975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3838140975
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.396208071
Short name T850
Test name
Test status
Simulation time 24599041 ps
CPU time 0.86 seconds
Started Mar 03 12:40:31 PM PST 24
Finished Mar 03 12:40:32 PM PST 24
Peak memory 206104 kb
Host smart-42439503-bad5-4ac8-b25e-62fbfd3ea3a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396208071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.396208071
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.584324912
Short name T911
Test name
Test status
Simulation time 15371492 ps
CPU time 0.85 seconds
Started Mar 03 12:40:49 PM PST 24
Finished Mar 03 12:40:50 PM PST 24
Peak memory 206208 kb
Host smart-0b8010f2-a4e9-4a15-9551-1721ed95034e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584324912 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.584324912
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.2207591332
Short name T210
Test name
Test status
Simulation time 19667489 ps
CPU time 1.18 seconds
Started Mar 03 12:40:33 PM PST 24
Finished Mar 03 12:40:34 PM PST 24
Peak memory 206168 kb
Host smart-90815804-e1e9-4e95-af06-9d128c1a1d95
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207591332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.2207591332
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.4083805631
Short name T872
Test name
Test status
Simulation time 176932174 ps
CPU time 4.94 seconds
Started Mar 03 12:40:26 PM PST 24
Finished Mar 03 12:40:31 PM PST 24
Peak memory 206116 kb
Host smart-460302be-dd88-45d2-b07e-3c7e50335b86
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083805631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.4083805631
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.2298227050
Short name T208
Test name
Test status
Simulation time 17427216 ps
CPU time 1.06 seconds
Started Mar 03 12:40:27 PM PST 24
Finished Mar 03 12:40:28 PM PST 24
Peak memory 206120 kb
Host smart-b8427370-d5f2-43a9-877d-ae87e2fccd94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298227050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.2298227050
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1113445097
Short name T893
Test name
Test status
Simulation time 79823385 ps
CPU time 1.05 seconds
Started Mar 03 12:40:15 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 214488 kb
Host smart-26a926e4-2fe6-4058-acdc-245910cade66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113445097 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1113445097
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.2077904067
Short name T197
Test name
Test status
Simulation time 16137752 ps
CPU time 0.92 seconds
Started Mar 03 12:40:16 PM PST 24
Finished Mar 03 12:40:18 PM PST 24
Peak memory 206208 kb
Host smart-748715de-4f3d-4118-98fb-81c45a316437
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077904067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.2077904067
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1437469834
Short name T961
Test name
Test status
Simulation time 14745526 ps
CPU time 0.85 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:40:24 PM PST 24
Peak memory 206100 kb
Host smart-d2ff4018-4ef1-401a-8d01-6a7188da4b1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437469834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1437469834
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.228922596
Short name T846
Test name
Test status
Simulation time 36527668 ps
CPU time 1.33 seconds
Started Mar 03 12:40:21 PM PST 24
Finished Mar 03 12:40:23 PM PST 24
Peak memory 206116 kb
Host smart-5e1a5afe-e904-4f45-afcc-3cc795b15f72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228922596 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.228922596
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2901920410
Short name T955
Test name
Test status
Simulation time 139153818 ps
CPU time 2.49 seconds
Started Mar 03 12:40:37 PM PST 24
Finished Mar 03 12:40:40 PM PST 24
Peak memory 214488 kb
Host smart-cb674060-876e-48cd-9cad-9d0152209369
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901920410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2901920410
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.4162788593
Short name T964
Test name
Test status
Simulation time 286657177 ps
CPU time 2.12 seconds
Started Mar 03 12:40:43 PM PST 24
Finished Mar 03 12:40:46 PM PST 24
Peak memory 206180 kb
Host smart-1ee4dd2a-98fa-454c-96d7-b9a4799b21ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162788593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.4162788593
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2606616755
Short name T842
Test name
Test status
Simulation time 47351046 ps
CPU time 0.81 seconds
Started Mar 03 12:40:39 PM PST 24
Finished Mar 03 12:40:40 PM PST 24
Peak memory 206128 kb
Host smart-94f9e5d7-0211-4516-97cf-d2be00424073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606616755 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2606616755
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.1518534520
Short name T835
Test name
Test status
Simulation time 11344441 ps
CPU time 0.85 seconds
Started Mar 03 12:40:45 PM PST 24
Finished Mar 03 12:40:47 PM PST 24
Peak memory 206116 kb
Host smart-1ff706fb-6570-4cd7-932b-5cab6e5f5ff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518534520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.1518534520
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3001208311
Short name T963
Test name
Test status
Simulation time 17458895 ps
CPU time 0.9 seconds
Started Mar 03 12:40:49 PM PST 24
Finished Mar 03 12:40:50 PM PST 24
Peak memory 206068 kb
Host smart-187efd88-637f-45d1-90ff-05f9cb85da02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001208311 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3001208311
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.144887385
Short name T869
Test name
Test status
Simulation time 12834108 ps
CPU time 0.87 seconds
Started Mar 03 12:40:24 PM PST 24
Finished Mar 03 12:40:25 PM PST 24
Peak memory 206136 kb
Host smart-f4688448-7a0d-4eb7-8eb4-04ab4a2c0291
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144887385 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.144887385
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2540071686
Short name T915
Test name
Test status
Simulation time 22780274 ps
CPU time 0.99 seconds
Started Mar 03 12:40:33 PM PST 24
Finished Mar 03 12:40:34 PM PST 24
Peak memory 206124 kb
Host smart-936b734a-e059-490a-98b5-1be0079173e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540071686 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2540071686
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.2862459706
Short name T952
Test name
Test status
Simulation time 13771571 ps
CPU time 0.82 seconds
Started Mar 03 12:40:36 PM PST 24
Finished Mar 03 12:40:37 PM PST 24
Peak memory 206064 kb
Host smart-9227056e-14f4-4e5b-a7cf-ca9aaecbb469
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862459706 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.2862459706
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.274337539
Short name T906
Test name
Test status
Simulation time 41220097 ps
CPU time 0.82 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 12:41:18 PM PST 24
Peak memory 206440 kb
Host smart-a99976eb-81f4-4657-a459-a1caafd8cfd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274337539 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.274337539
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.234125536
Short name T904
Test name
Test status
Simulation time 40042985 ps
CPU time 0.8 seconds
Started Mar 03 12:40:47 PM PST 24
Finished Mar 03 12:40:48 PM PST 24
Peak memory 205972 kb
Host smart-e2a4070a-5219-4784-ad34-a431bfa777d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234125536 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.234125536
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1493209371
Short name T839
Test name
Test status
Simulation time 14873352 ps
CPU time 0.87 seconds
Started Mar 03 12:40:57 PM PST 24
Finished Mar 03 12:40:58 PM PST 24
Peak memory 206216 kb
Host smart-d0bc48b3-173f-4b1e-8861-7b95215afcdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493209371 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1493209371
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.2372729549
Short name T939
Test name
Test status
Simulation time 44519096 ps
CPU time 0.8 seconds
Started Mar 03 12:40:52 PM PST 24
Finished Mar 03 12:40:53 PM PST 24
Peak memory 206108 kb
Host smart-16bc9eaf-e7bc-48b8-8fb3-f912738379db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372729549 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.2372729549
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2396452105
Short name T201
Test name
Test status
Simulation time 40962285 ps
CPU time 1.61 seconds
Started Mar 03 12:40:55 PM PST 24
Finished Mar 03 12:41:02 PM PST 24
Peak memory 206188 kb
Host smart-c788c6d9-7ad1-4bd8-bbef-0816ea856a6a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396452105 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2396452105
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.3095619427
Short name T205
Test name
Test status
Simulation time 60506255 ps
CPU time 3.29 seconds
Started Mar 03 12:40:34 PM PST 24
Finished Mar 03 12:40:37 PM PST 24
Peak memory 206172 kb
Host smart-53ad075e-fdb0-422e-b3b5-c2a565d234f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095619427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.3095619427
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2674643566
Short name T207
Test name
Test status
Simulation time 67928446 ps
CPU time 0.87 seconds
Started Mar 03 12:40:31 PM PST 24
Finished Mar 03 12:40:32 PM PST 24
Peak memory 206176 kb
Host smart-7cf1e1d3-f739-4672-a303-c56459acd142
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674643566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2674643566
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.516316916
Short name T896
Test name
Test status
Simulation time 178268145 ps
CPU time 1.58 seconds
Started Mar 03 12:40:32 PM PST 24
Finished Mar 03 12:40:34 PM PST 24
Peak memory 214380 kb
Host smart-f7ce06b4-b6dc-45ba-bfef-a90882440c78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516316916 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.516316916
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.1383471817
Short name T938
Test name
Test status
Simulation time 38714825 ps
CPU time 0.87 seconds
Started Mar 03 12:40:28 PM PST 24
Finished Mar 03 12:40:30 PM PST 24
Peak memory 206104 kb
Host smart-1baa2273-3584-4c56-99a4-08cb82d719f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383471817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.1383471817
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2739485781
Short name T836
Test name
Test status
Simulation time 16561987 ps
CPU time 0.93 seconds
Started Mar 03 12:40:20 PM PST 24
Finished Mar 03 12:40:21 PM PST 24
Peak memory 206128 kb
Host smart-a6b54cf5-d885-48d3-be2b-aa7df271a803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739485781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2739485781
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.3006371903
Short name T843
Test name
Test status
Simulation time 17066273 ps
CPU time 0.91 seconds
Started Mar 03 12:40:22 PM PST 24
Finished Mar 03 12:40:24 PM PST 24
Peak memory 206184 kb
Host smart-acb056b6-53ac-4bf5-81e0-9b508d9e9ede
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006371903 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.3006371903
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2635201861
Short name T912
Test name
Test status
Simulation time 180173250 ps
CPU time 3.02 seconds
Started Mar 03 12:40:10 PM PST 24
Finished Mar 03 12:40:14 PM PST 24
Peak memory 214492 kb
Host smart-535e6997-7793-4f55-b252-133546eb630e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635201861 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2635201861
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1420275691
Short name T232
Test name
Test status
Simulation time 103776969 ps
CPU time 1.61 seconds
Started Mar 03 12:40:24 PM PST 24
Finished Mar 03 12:40:26 PM PST 24
Peak memory 206284 kb
Host smart-5c831c9e-30cc-4ee8-ae89-676c707a5749
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420275691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1420275691
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.1097600063
Short name T833
Test name
Test status
Simulation time 38058610 ps
CPU time 0.79 seconds
Started Mar 03 12:40:47 PM PST 24
Finished Mar 03 12:40:48 PM PST 24
Peak memory 205968 kb
Host smart-7bb5b099-d621-4393-8ffc-2e82384165f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097600063 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.1097600063
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.1769498476
Short name T840
Test name
Test status
Simulation time 13959937 ps
CPU time 0.86 seconds
Started Mar 03 12:40:42 PM PST 24
Finished Mar 03 12:40:43 PM PST 24
Peak memory 206116 kb
Host smart-c53e3157-3bc5-4100-8cb5-b49a1130fafc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769498476 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.1769498476
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1192711839
Short name T927
Test name
Test status
Simulation time 19703473 ps
CPU time 0.81 seconds
Started Mar 03 12:41:01 PM PST 24
Finished Mar 03 12:41:02 PM PST 24
Peak memory 206112 kb
Host smart-50b066f0-dc55-45e5-ab43-618d9c62011d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192711839 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1192711839
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1687791457
Short name T894
Test name
Test status
Simulation time 12341036 ps
CPU time 0.84 seconds
Started Mar 03 12:40:40 PM PST 24
Finished Mar 03 12:40:41 PM PST 24
Peak memory 206064 kb
Host smart-97246314-6e2a-40b5-8652-e63a6135b4ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687791457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1687791457
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3462521973
Short name T914
Test name
Test status
Simulation time 16619452 ps
CPU time 0.98 seconds
Started Mar 03 12:40:49 PM PST 24
Finished Mar 03 12:40:50 PM PST 24
Peak memory 206120 kb
Host smart-9edfa609-e7b8-4347-91fa-af724572e5e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462521973 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3462521973
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.4001703384
Short name T863
Test name
Test status
Simulation time 47420737 ps
CPU time 0.85 seconds
Started Mar 03 12:40:50 PM PST 24
Finished Mar 03 12:40:51 PM PST 24
Peak memory 206108 kb
Host smart-33f8c7e8-fa80-4af5-8fd1-be2c83294d0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001703384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.4001703384
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.3885867486
Short name T858
Test name
Test status
Simulation time 55033088 ps
CPU time 0.81 seconds
Started Mar 03 12:40:55 PM PST 24
Finished Mar 03 12:40:56 PM PST 24
Peak memory 205984 kb
Host smart-4b6dc411-d7ac-440b-91cf-38afbc0a18af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885867486 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.3885867486
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3397112082
Short name T845
Test name
Test status
Simulation time 21523166 ps
CPU time 0.77 seconds
Started Mar 03 12:40:51 PM PST 24
Finished Mar 03 12:40:51 PM PST 24
Peak memory 205960 kb
Host smart-e4bd1b81-21b5-45ae-a8ac-bfc8b12b87d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397112082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3397112082
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.319846631
Short name T950
Test name
Test status
Simulation time 15813381 ps
CPU time 0.84 seconds
Started Mar 03 12:40:43 PM PST 24
Finished Mar 03 12:40:44 PM PST 24
Peak memory 206120 kb
Host smart-5381e196-dfe9-41ba-b366-d02ca9d8f2af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319846631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.319846631
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1434054325
Short name T902
Test name
Test status
Simulation time 65033124 ps
CPU time 0.82 seconds
Started Mar 03 12:40:57 PM PST 24
Finished Mar 03 12:40:58 PM PST 24
Peak memory 206104 kb
Host smart-4afc5fba-7898-425a-bbf2-06cff8d9265e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434054325 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1434054325
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.1489392575
Short name T841
Test name
Test status
Simulation time 57376019 ps
CPU time 1.35 seconds
Started Mar 03 12:40:38 PM PST 24
Finished Mar 03 12:40:40 PM PST 24
Peak memory 214416 kb
Host smart-21dc1478-841e-4cca-8e76-159dc1ce91ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489392575 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.1489392575
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.2053146795
Short name T214
Test name
Test status
Simulation time 14158073 ps
CPU time 0.87 seconds
Started Mar 03 12:40:27 PM PST 24
Finished Mar 03 12:40:28 PM PST 24
Peak memory 206024 kb
Host smart-e907e6d4-510c-4a8b-a560-cf6cf8cd7ddc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053146795 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.2053146795
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.138273975
Short name T932
Test name
Test status
Simulation time 23602099 ps
CPU time 0.81 seconds
Started Mar 03 12:40:44 PM PST 24
Finished Mar 03 12:40:45 PM PST 24
Peak memory 206112 kb
Host smart-c90ee8d4-e506-4803-ab9b-87016da323cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138273975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.138273975
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.3170846520
Short name T956
Test name
Test status
Simulation time 208892197 ps
CPU time 1.05 seconds
Started Mar 03 12:40:42 PM PST 24
Finished Mar 03 12:40:43 PM PST 24
Peak memory 206280 kb
Host smart-581590a6-7d23-468a-9953-40ef65558e7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170846520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.3170846520
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.2698179696
Short name T895
Test name
Test status
Simulation time 135981300 ps
CPU time 4.41 seconds
Started Mar 03 12:40:44 PM PST 24
Finished Mar 03 12:40:49 PM PST 24
Peak memory 217756 kb
Host smart-0db6cc75-e254-4031-a21c-50231fdac709
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698179696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.2698179696
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3525740614
Short name T860
Test name
Test status
Simulation time 174386616 ps
CPU time 1.56 seconds
Started Mar 03 12:40:38 PM PST 24
Finished Mar 03 12:40:40 PM PST 24
Peak memory 206096 kb
Host smart-383c1b05-4b18-4d34-b2f6-e38ac8e15d43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525740614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3525740614
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3472251734
Short name T960
Test name
Test status
Simulation time 51049328 ps
CPU time 1.34 seconds
Started Mar 03 12:40:37 PM PST 24
Finished Mar 03 12:40:39 PM PST 24
Peak memory 214712 kb
Host smart-57db6308-a61b-4cb5-ada7-9f0c4f7e8350
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472251734 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3472251734
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.752723813
Short name T940
Test name
Test status
Simulation time 32463212 ps
CPU time 0.82 seconds
Started Mar 03 12:41:04 PM PST 24
Finished Mar 03 12:41:05 PM PST 24
Peak memory 206124 kb
Host smart-90fde368-d82b-4cff-bb2b-229419bfad1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752723813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.752723813
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1997225466
Short name T944
Test name
Test status
Simulation time 37499541 ps
CPU time 1.02 seconds
Started Mar 03 12:41:07 PM PST 24
Finished Mar 03 12:41:08 PM PST 24
Peak memory 206156 kb
Host smart-7645c808-e4fc-454c-a73c-3b252cd196ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997225466 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1997225466
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.1312454855
Short name T899
Test name
Test status
Simulation time 214481212 ps
CPU time 1.99 seconds
Started Mar 03 12:40:27 PM PST 24
Finished Mar 03 12:40:29 PM PST 24
Peak memory 214476 kb
Host smart-45183dc2-5558-4a2d-9bcc-3f03551f43f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312454855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.1312454855
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.387117439
Short name T243
Test name
Test status
Simulation time 226998775 ps
CPU time 1.92 seconds
Started Mar 03 12:40:34 PM PST 24
Finished Mar 03 12:40:36 PM PST 24
Peak memory 206188 kb
Host smart-9ac6c103-8623-4f53-998d-ad695e2ab029
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387117439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.387117439
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3948183702
Short name T958
Test name
Test status
Simulation time 26792011 ps
CPU time 1.2 seconds
Started Mar 03 12:40:25 PM PST 24
Finished Mar 03 12:40:27 PM PST 24
Peak memory 215956 kb
Host smart-6786d88f-5185-4637-b44f-31b1f127cf75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948183702 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3948183702
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1466736165
Short name T922
Test name
Test status
Simulation time 29101794 ps
CPU time 0.93 seconds
Started Mar 03 12:40:26 PM PST 24
Finished Mar 03 12:40:32 PM PST 24
Peak memory 205096 kb
Host smart-06e0a2ee-cf04-436d-841b-f688c4c4dc44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466736165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1466736165
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3946762955
Short name T861
Test name
Test status
Simulation time 27830385 ps
CPU time 0.88 seconds
Started Mar 03 12:40:53 PM PST 24
Finished Mar 03 12:40:54 PM PST 24
Peak memory 206124 kb
Host smart-f9eb8e02-6300-4881-b839-42926e5ed48e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946762955 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3946762955
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.761078981
Short name T919
Test name
Test status
Simulation time 53573969 ps
CPU time 1.03 seconds
Started Mar 03 12:40:25 PM PST 24
Finished Mar 03 12:40:26 PM PST 24
Peak memory 206220 kb
Host smart-5275cbd7-6242-4128-85c5-5f81c54b5700
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761078981 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.761078981
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.1611780902
Short name T892
Test name
Test status
Simulation time 105374742 ps
CPU time 3.47 seconds
Started Mar 03 12:40:44 PM PST 24
Finished Mar 03 12:40:47 PM PST 24
Peak memory 214392 kb
Host smart-4dc713fe-c83e-479d-83f2-716d4b83ffd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611780902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.1611780902
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.211621140
Short name T924
Test name
Test status
Simulation time 145152931 ps
CPU time 3.05 seconds
Started Mar 03 12:40:24 PM PST 24
Finished Mar 03 12:40:27 PM PST 24
Peak memory 206124 kb
Host smart-618ee82d-6249-4fc9-ba2e-4cca84fe46c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211621140 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.211621140
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.221063748
Short name T883
Test name
Test status
Simulation time 75197647 ps
CPU time 1.46 seconds
Started Mar 03 12:40:36 PM PST 24
Finished Mar 03 12:40:38 PM PST 24
Peak memory 214428 kb
Host smart-5e3710f0-44e9-4a83-bdeb-c4a8ee94511e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221063748 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.221063748
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.374997534
Short name T913
Test name
Test status
Simulation time 17745606 ps
CPU time 0.96 seconds
Started Mar 03 12:40:28 PM PST 24
Finished Mar 03 12:40:29 PM PST 24
Peak memory 206100 kb
Host smart-5b198d2e-b9f1-4641-a6c4-cfb7e6b1945d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374997534 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.374997534
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2110173845
Short name T954
Test name
Test status
Simulation time 30540935 ps
CPU time 0.84 seconds
Started Mar 03 12:40:27 PM PST 24
Finished Mar 03 12:40:28 PM PST 24
Peak memory 205952 kb
Host smart-2ff7daec-5fde-4bec-bb2c-e1ecdcadc716
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110173845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2110173845
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1598249061
Short name T217
Test name
Test status
Simulation time 21179196 ps
CPU time 1.09 seconds
Started Mar 03 12:40:49 PM PST 24
Finished Mar 03 12:40:51 PM PST 24
Peak memory 206128 kb
Host smart-ed0810e6-2afa-4942-af9c-a98bc24446c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598249061 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1598249061
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.2015604048
Short name T908
Test name
Test status
Simulation time 881136015 ps
CPU time 2.95 seconds
Started Mar 03 12:40:26 PM PST 24
Finished Mar 03 12:40:29 PM PST 24
Peak memory 214424 kb
Host smart-3974d4ce-0f55-4019-b0aa-bd4c4733843b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015604048 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.2015604048
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.4084037258
Short name T923
Test name
Test status
Simulation time 161746321 ps
CPU time 1.51 seconds
Started Mar 03 12:40:38 PM PST 24
Finished Mar 03 12:40:44 PM PST 24
Peak memory 206216 kb
Host smart-cfc0225a-d838-43ef-95c2-f5ced7ed3e7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084037258 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.4084037258
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.70256628
Short name T870
Test name
Test status
Simulation time 103003001 ps
CPU time 1.27 seconds
Started Mar 03 12:40:56 PM PST 24
Finished Mar 03 12:40:57 PM PST 24
Peak memory 214536 kb
Host smart-e191e7fb-dd17-4e3f-b22e-397ffd3de1d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70256628 -assert nopostproc +UVM_TESTNAME=e
dn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.70256628
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.4139501616
Short name T882
Test name
Test status
Simulation time 23928682 ps
CPU time 0.85 seconds
Started Mar 03 12:40:25 PM PST 24
Finished Mar 03 12:40:26 PM PST 24
Peak memory 206080 kb
Host smart-74a4f535-cebb-4191-89be-405bae8c3a0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139501616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.4139501616
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.3937197460
Short name T945
Test name
Test status
Simulation time 29799505 ps
CPU time 0.78 seconds
Started Mar 03 12:40:30 PM PST 24
Finished Mar 03 12:40:31 PM PST 24
Peak memory 206292 kb
Host smart-3fc7ce72-d55f-4d3d-9284-39e233af3988
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937197460 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.3937197460
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.933508611
Short name T218
Test name
Test status
Simulation time 20615942 ps
CPU time 1.02 seconds
Started Mar 03 12:40:23 PM PST 24
Finished Mar 03 12:40:24 PM PST 24
Peak memory 206180 kb
Host smart-e1c77dae-ac8a-45c4-84b6-17461039b2ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933508611 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_out
standing.933508611
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.1639665983
Short name T903
Test name
Test status
Simulation time 30129276 ps
CPU time 2.01 seconds
Started Mar 03 12:40:32 PM PST 24
Finished Mar 03 12:40:34 PM PST 24
Peak memory 214400 kb
Host smart-42441af5-21dc-4542-93e5-c0c19ee8b0b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639665983 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.1639665983
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.740008068
Short name T875
Test name
Test status
Simulation time 151336416 ps
CPU time 1.43 seconds
Started Mar 03 12:40:34 PM PST 24
Finished Mar 03 12:40:36 PM PST 24
Peak memory 206152 kb
Host smart-0c9d20f6-65ba-4288-be1f-415e79407b9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740008068 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.740008068
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.439820668
Short name T804
Test name
Test status
Simulation time 20016416 ps
CPU time 1.05 seconds
Started Mar 03 02:44:31 PM PST 24
Finished Mar 03 02:44:32 PM PST 24
Peak memory 205464 kb
Host smart-29293aab-9031-441f-b575-d3d3e400bf24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439820668 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.439820668
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.4074562843
Short name T442
Test name
Test status
Simulation time 37419753 ps
CPU time 0.85 seconds
Started Mar 03 02:44:32 PM PST 24
Finished Mar 03 02:44:33 PM PST 24
Peak memory 214352 kb
Host smart-34628e2e-9115-4b82-b206-c1b6ce633d1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074562843 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.4074562843
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.546142769
Short name T457
Test name
Test status
Simulation time 81637074 ps
CPU time 1.17 seconds
Started Mar 03 02:44:30 PM PST 24
Finished Mar 03 02:44:31 PM PST 24
Peak memory 215244 kb
Host smart-167121d5-148c-4ee3-9cbd-f4c52ad846fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546142769 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.546142769
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.3627564685
Short name T96
Test name
Test status
Simulation time 44381241 ps
CPU time 1.23 seconds
Started Mar 03 02:44:30 PM PST 24
Finished Mar 03 02:44:31 PM PST 24
Peak memory 222896 kb
Host smart-7ce0f803-eca8-4320-bed9-2e3669191a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627564685 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.3627564685
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1204459312
Short name T281
Test name
Test status
Simulation time 38946756 ps
CPU time 1.13 seconds
Started Mar 03 02:44:26 PM PST 24
Finished Mar 03 02:44:28 PM PST 24
Peak memory 214060 kb
Host smart-d6f0bd93-d74f-4b3c-aa7c-582a3eeae742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204459312 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1204459312
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.2650420400
Short name T525
Test name
Test status
Simulation time 25583212 ps
CPU time 0.97 seconds
Started Mar 03 02:44:32 PM PST 24
Finished Mar 03 02:44:33 PM PST 24
Peak memory 214180 kb
Host smart-cdb3f4f0-1b51-47f4-b6b9-c4ca22dbe0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650420400 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.2650420400
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.1792473173
Short name T131
Test name
Test status
Simulation time 31095512 ps
CPU time 0.88 seconds
Started Mar 03 02:44:33 PM PST 24
Finished Mar 03 02:44:34 PM PST 24
Peak memory 205912 kb
Host smart-68235a57-2d3c-43a3-8eb5-d9e83e1de0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792473173 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1792473173
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2992848856
Short name T56
Test name
Test status
Simulation time 372030427 ps
CPU time 3.77 seconds
Started Mar 03 02:44:30 PM PST 24
Finished Mar 03 02:44:35 PM PST 24
Peak memory 233392 kb
Host smart-0e44eeeb-96e8-4df3-8723-d02d479f030a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992848856 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2992848856
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.1978735919
Short name T720
Test name
Test status
Simulation time 16579613 ps
CPU time 0.98 seconds
Started Mar 03 02:44:33 PM PST 24
Finished Mar 03 02:44:34 PM PST 24
Peak memory 214120 kb
Host smart-f710805e-7761-47b1-9344-ebe24f7c43ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978735919 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.1978735919
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1619992501
Short name T786
Test name
Test status
Simulation time 190625242 ps
CPU time 4.02 seconds
Started Mar 03 02:44:24 PM PST 24
Finished Mar 03 02:44:28 PM PST 24
Peak memory 214100 kb
Host smart-bd2fd16c-0079-4274-855e-52c8c6cce18d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619992501 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1619992501
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.2227036003
Short name T785
Test name
Test status
Simulation time 88442080804 ps
CPU time 1017.63 seconds
Started Mar 03 02:44:34 PM PST 24
Finished Mar 03 03:01:32 PM PST 24
Peak memory 220336 kb
Host smart-e0e222ce-57d6-43d8-8b95-7f637298b2a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227036003 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.2227036003
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.1463525370
Short name T518
Test name
Test status
Simulation time 49116134 ps
CPU time 0.82 seconds
Started Mar 03 02:44:30 PM PST 24
Finished Mar 03 02:44:31 PM PST 24
Peak memory 204896 kb
Host smart-99f7163b-0ca2-4d7d-be0b-f5f300116753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463525370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1463525370
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.2191243369
Short name T184
Test name
Test status
Simulation time 37944768 ps
CPU time 0.89 seconds
Started Mar 03 02:44:32 PM PST 24
Finished Mar 03 02:44:33 PM PST 24
Peak memory 214352 kb
Host smart-bd525f97-86b8-4f05-bed2-c3baa3599988
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191243369 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.2191243369
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.2413118213
Short name T585
Test name
Test status
Simulation time 77638010 ps
CPU time 1.09 seconds
Started Mar 03 02:44:31 PM PST 24
Finished Mar 03 02:44:32 PM PST 24
Peak memory 216532 kb
Host smart-6321d279-bfd8-43d8-b852-4ddeea7fce01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413118213 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.2413118213
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.1732180671
Short name T89
Test name
Test status
Simulation time 32544875 ps
CPU time 1.16 seconds
Started Mar 03 02:44:31 PM PST 24
Finished Mar 03 02:44:33 PM PST 24
Peak memory 230128 kb
Host smart-98e80dff-f327-4f4e-adc2-af7e2a47c37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732180671 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1732180671
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.201926432
Short name T307
Test name
Test status
Simulation time 91127414 ps
CPU time 1.06 seconds
Started Mar 03 02:44:34 PM PST 24
Finished Mar 03 02:44:35 PM PST 24
Peak memory 215256 kb
Host smart-38c20f82-c7a6-48d6-b32f-990ad431498d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201926432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.201926432
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2237454183
Short name T18
Test name
Test status
Simulation time 1274245825 ps
CPU time 9.71 seconds
Started Mar 03 02:44:30 PM PST 24
Finished Mar 03 02:44:40 PM PST 24
Peak memory 234588 kb
Host smart-7c46ed57-c05d-4822-819b-79ef1be4b146
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237454183 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2237454183
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.950161192
Short name T506
Test name
Test status
Simulation time 17407274 ps
CPU time 0.99 seconds
Started Mar 03 02:44:32 PM PST 24
Finished Mar 03 02:44:33 PM PST 24
Peak memory 214116 kb
Host smart-d59f049c-5850-42d2-bdd5-36a3496a0873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950161192 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.950161192
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.3972941884
Short name T367
Test name
Test status
Simulation time 409639465 ps
CPU time 5.72 seconds
Started Mar 03 02:44:33 PM PST 24
Finished Mar 03 02:44:39 PM PST 24
Peak memory 215372 kb
Host smart-080e5bf9-4829-47c8-afe6-97732a5226aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972941884 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.3972941884
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_alert_test.1144945362
Short name T670
Test name
Test status
Simulation time 37313296 ps
CPU time 0.84 seconds
Started Mar 03 02:45:00 PM PST 24
Finished Mar 03 02:45:01 PM PST 24
Peak memory 204612 kb
Host smart-7125e35c-84c4-4015-a74e-97ee62f1af98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144945362 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.1144945362
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_err.3612426544
Short name T675
Test name
Test status
Simulation time 34778893 ps
CPU time 0.86 seconds
Started Mar 03 02:45:02 PM PST 24
Finished Mar 03 02:45:03 PM PST 24
Peak memory 216496 kb
Host smart-a1823fbd-7037-4c16-ae91-6d9240d57b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612426544 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.3612426544
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_genbits.1863520052
Short name T521
Test name
Test status
Simulation time 34098534 ps
CPU time 1.31 seconds
Started Mar 03 02:44:54 PM PST 24
Finished Mar 03 02:44:56 PM PST 24
Peak memory 217328 kb
Host smart-d194932a-67d4-407f-8242-c4af99b5c352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863520052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.1863520052
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.2873447716
Short name T469
Test name
Test status
Simulation time 27609411 ps
CPU time 0.85 seconds
Started Mar 03 02:44:56 PM PST 24
Finished Mar 03 02:44:56 PM PST 24
Peak memory 214508 kb
Host smart-6dc4044e-273e-4407-b917-6a70f70f20f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873447716 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2873447716
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.1239627665
Short name T823
Test name
Test status
Simulation time 42755552 ps
CPU time 0.88 seconds
Started Mar 03 02:44:54 PM PST 24
Finished Mar 03 02:44:55 PM PST 24
Peak memory 214120 kb
Host smart-90ebff33-24ec-4868-9455-89abfcef6e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239627665 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.1239627665
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3266789550
Short name T543
Test name
Test status
Simulation time 134304006 ps
CPU time 1.89 seconds
Started Mar 03 02:44:53 PM PST 24
Finished Mar 03 02:44:55 PM PST 24
Peak memory 215296 kb
Host smart-de56bfe6-a113-4db2-9529-7d763c7f0673
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266789550 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3266789550
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/100.edn_genbits.2228006733
Short name T762
Test name
Test status
Simulation time 35762996 ps
CPU time 1.44 seconds
Started Mar 03 02:46:29 PM PST 24
Finished Mar 03 02:46:31 PM PST 24
Peak memory 218464 kb
Host smart-11ebaaae-d342-4d9d-bd72-7000c84d1f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228006733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2228006733
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.3839055509
Short name T44
Test name
Test status
Simulation time 72054704 ps
CPU time 1.16 seconds
Started Mar 03 02:46:28 PM PST 24
Finished Mar 03 02:46:29 PM PST 24
Peak memory 215300 kb
Host smart-4f48f0e3-1de0-4218-a1a8-d3e4725d0961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839055509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3839055509
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.4030930201
Short name T742
Test name
Test status
Simulation time 68170849 ps
CPU time 2.68 seconds
Started Mar 03 02:46:32 PM PST 24
Finished Mar 03 02:46:35 PM PST 24
Peak memory 218384 kb
Host smart-646c014a-7636-48f5-a2cc-d01ea776a6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030930201 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.4030930201
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.1196024646
Short name T297
Test name
Test status
Simulation time 82871363 ps
CPU time 1.14 seconds
Started Mar 03 02:46:28 PM PST 24
Finished Mar 03 02:46:29 PM PST 24
Peak memory 217888 kb
Host smart-d7e4305a-de23-459d-9e75-66edddd4b7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196024646 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1196024646
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1003749402
Short name T26
Test name
Test status
Simulation time 70072573 ps
CPU time 2.44 seconds
Started Mar 03 02:46:30 PM PST 24
Finished Mar 03 02:46:32 PM PST 24
Peak memory 217672 kb
Host smart-620d81f9-a16d-4094-8898-6adf5fe9e36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003749402 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1003749402
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.2504631575
Short name T602
Test name
Test status
Simulation time 46586555 ps
CPU time 1.19 seconds
Started Mar 03 02:46:28 PM PST 24
Finished Mar 03 02:46:29 PM PST 24
Peak memory 216504 kb
Host smart-cf55ec34-6106-41f5-a9fd-6c372516bfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504631575 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.2504631575
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.560219740
Short name T277
Test name
Test status
Simulation time 114022464 ps
CPU time 2.46 seconds
Started Mar 03 02:46:29 PM PST 24
Finished Mar 03 02:46:31 PM PST 24
Peak memory 216804 kb
Host smart-3f2aa5be-239b-402c-85b7-b9d6f80e75aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560219740 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.560219740
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.2971059936
Short name T661
Test name
Test status
Simulation time 140861857 ps
CPU time 3.07 seconds
Started Mar 03 02:46:30 PM PST 24
Finished Mar 03 02:46:34 PM PST 24
Peak memory 216840 kb
Host smart-111fbf7b-b668-4a53-a96f-38fd64ad1415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971059936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.2971059936
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.1575644749
Short name T234
Test name
Test status
Simulation time 25075522 ps
CPU time 1.27 seconds
Started Mar 03 02:44:56 PM PST 24
Finished Mar 03 02:44:58 PM PST 24
Peak memory 214572 kb
Host smart-24efeb74-41aa-4e06-b41e-56534cdb858d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575644749 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.1575644749
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_alert_test.207936154
Short name T643
Test name
Test status
Simulation time 42765428 ps
CPU time 1.07 seconds
Started Mar 03 02:45:01 PM PST 24
Finished Mar 03 02:45:02 PM PST 24
Peak memory 205000 kb
Host smart-e832053b-b865-4318-ba60-6917d2b4333f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207936154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.207936154
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.3922652532
Short name T761
Test name
Test status
Simulation time 38831829 ps
CPU time 1.3 seconds
Started Mar 03 02:44:59 PM PST 24
Finished Mar 03 02:45:00 PM PST 24
Peak memory 215228 kb
Host smart-6dcab508-5640-4714-a0be-e78446a3b1d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922652532 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.3922652532
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_genbits.3184808966
Short name T703
Test name
Test status
Simulation time 206277386 ps
CPU time 1.79 seconds
Started Mar 03 02:45:06 PM PST 24
Finished Mar 03 02:45:08 PM PST 24
Peak memory 216968 kb
Host smart-eba6836d-4bf4-4084-92eb-b0f5f50b26d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184808966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.3184808966
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.3701631276
Short name T55
Test name
Test status
Simulation time 41171459 ps
CPU time 0.98 seconds
Started Mar 03 02:44:58 PM PST 24
Finished Mar 03 02:44:59 PM PST 24
Peak memory 221888 kb
Host smart-81113da2-89ef-47bc-8e05-869a1bc0c0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701631276 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.3701631276
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.2911927888
Short name T420
Test name
Test status
Simulation time 38579813 ps
CPU time 0.91 seconds
Started Mar 03 02:44:59 PM PST 24
Finished Mar 03 02:44:59 PM PST 24
Peak memory 214112 kb
Host smart-bf2befef-8331-4754-be59-0740db9cbcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911927888 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2911927888
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.619866328
Short name T704
Test name
Test status
Simulation time 2192442770 ps
CPU time 3.84 seconds
Started Mar 03 02:44:59 PM PST 24
Finished Mar 03 02:45:03 PM PST 24
Peak memory 214256 kb
Host smart-f5da90ab-8f13-4a3a-8ac7-bf4dbb7e2838
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619866328 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.619866328
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.590995395
Short name T145
Test name
Test status
Simulation time 301041076053 ps
CPU time 1900.34 seconds
Started Mar 03 02:45:00 PM PST 24
Finished Mar 03 03:16:41 PM PST 24
Peak memory 224128 kb
Host smart-ba20916e-5a60-4a25-9a64-269194e09f5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590995395 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.590995395
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.2254441556
Short name T820
Test name
Test status
Simulation time 210270774 ps
CPU time 0.99 seconds
Started Mar 03 02:46:29 PM PST 24
Finished Mar 03 02:46:30 PM PST 24
Peak memory 215412 kb
Host smart-b1a4c134-6c1d-410c-b77a-ef096d10dbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254441556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2254441556
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.613079060
Short name T751
Test name
Test status
Simulation time 123773971 ps
CPU time 1.23 seconds
Started Mar 03 02:46:31 PM PST 24
Finished Mar 03 02:46:33 PM PST 24
Peak memory 216896 kb
Host smart-0e61a833-05e0-4faa-83ea-7b50c8874221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613079060 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.613079060
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.1797711928
Short name T676
Test name
Test status
Simulation time 192463750 ps
CPU time 2.52 seconds
Started Mar 03 02:46:28 PM PST 24
Finished Mar 03 02:46:30 PM PST 24
Peak memory 218224 kb
Host smart-c66b43d9-1c73-4af7-b258-7c4f24f24838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797711928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.1797711928
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.430267726
Short name T818
Test name
Test status
Simulation time 46773961 ps
CPU time 1.35 seconds
Started Mar 03 02:46:31 PM PST 24
Finished Mar 03 02:46:33 PM PST 24
Peak memory 216532 kb
Host smart-90efdf80-8ebd-4fc7-a683-049018403090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430267726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.430267726
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.3366982323
Short name T634
Test name
Test status
Simulation time 36279703 ps
CPU time 1.37 seconds
Started Mar 03 02:46:34 PM PST 24
Finished Mar 03 02:46:35 PM PST 24
Peak memory 216376 kb
Host smart-b183030c-fb14-406b-a97f-e0edfbc46b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366982323 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3366982323
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.1751651303
Short name T458
Test name
Test status
Simulation time 39789887 ps
CPU time 1.47 seconds
Started Mar 03 02:46:33 PM PST 24
Finished Mar 03 02:46:35 PM PST 24
Peak memory 218228 kb
Host smart-a4784795-3c24-46ca-8b61-aa483a9ce943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751651303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1751651303
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.1164982217
Short name T791
Test name
Test status
Simulation time 54364368 ps
CPU time 1.42 seconds
Started Mar 03 02:46:38 PM PST 24
Finished Mar 03 02:46:40 PM PST 24
Peak memory 216780 kb
Host smart-60847ec4-4c95-4e6b-963f-95b01a8e0ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164982217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.1164982217
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.1062307157
Short name T723
Test name
Test status
Simulation time 60435432 ps
CPU time 2.35 seconds
Started Mar 03 02:46:35 PM PST 24
Finished Mar 03 02:46:38 PM PST 24
Peak memory 217472 kb
Host smart-534b1aa3-1a44-47e7-9535-4854d7eca614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062307157 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1062307157
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.382562132
Short name T452
Test name
Test status
Simulation time 34009818 ps
CPU time 1.29 seconds
Started Mar 03 02:46:38 PM PST 24
Finished Mar 03 02:46:40 PM PST 24
Peak memory 216392 kb
Host smart-b49aed83-d568-4be2-a28f-69157603cd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382562132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.382562132
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3584313452
Short name T496
Test name
Test status
Simulation time 257995014 ps
CPU time 1.08 seconds
Started Mar 03 02:46:34 PM PST 24
Finished Mar 03 02:46:35 PM PST 24
Peak memory 215308 kb
Host smart-9102c1ef-e04b-4259-ae3c-cfc18849682d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584313452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3584313452
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.1636898873
Short name T435
Test name
Test status
Simulation time 56306366 ps
CPU time 1.25 seconds
Started Mar 03 02:44:57 PM PST 24
Finished Mar 03 02:44:58 PM PST 24
Peak memory 214580 kb
Host smart-1fd93125-6fa6-4cff-8cd4-b2d5f88a3ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636898873 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.1636898873
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.1041027848
Short name T540
Test name
Test status
Simulation time 79252351 ps
CPU time 1.08 seconds
Started Mar 03 02:44:58 PM PST 24
Finished Mar 03 02:44:59 PM PST 24
Peak memory 205456 kb
Host smart-88b54fd3-7d03-4d82-ad20-6d180e3d754d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041027848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1041027848
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.1950067269
Short name T705
Test name
Test status
Simulation time 35468821 ps
CPU time 0.89 seconds
Started Mar 03 02:45:02 PM PST 24
Finished Mar 03 02:45:03 PM PST 24
Peak memory 214328 kb
Host smart-9da50864-9430-4ebd-a4da-405e20b7fd43
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950067269 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1950067269
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_err.1875293456
Short name T715
Test name
Test status
Simulation time 37290542 ps
CPU time 1.14 seconds
Started Mar 03 02:44:59 PM PST 24
Finished Mar 03 02:45:00 PM PST 24
Peak memory 216700 kb
Host smart-457f1e9c-c7e3-4a61-8ae8-80a03e340ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875293456 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1875293456
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.4235967274
Short name T50
Test name
Test status
Simulation time 86425116 ps
CPU time 1.16 seconds
Started Mar 03 02:45:06 PM PST 24
Finished Mar 03 02:45:07 PM PST 24
Peak memory 215236 kb
Host smart-31db1208-ce9a-48e5-a51a-03c378a27d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235967274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.4235967274
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.2815689909
Short name T700
Test name
Test status
Simulation time 20890726 ps
CPU time 1.25 seconds
Started Mar 03 02:44:58 PM PST 24
Finished Mar 03 02:44:59 PM PST 24
Peak memory 222824 kb
Host smart-f318b070-6a2a-4b62-9513-2eb403627ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815689909 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.2815689909
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.138862503
Short name T665
Test name
Test status
Simulation time 24144632 ps
CPU time 0.93 seconds
Started Mar 03 02:45:07 PM PST 24
Finished Mar 03 02:45:08 PM PST 24
Peak memory 214152 kb
Host smart-8ae5c974-aea0-4efc-a2c6-e4df0304d123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138862503 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.138862503
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2135125300
Short name T717
Test name
Test status
Simulation time 102479912 ps
CPU time 1.12 seconds
Started Mar 03 02:44:59 PM PST 24
Finished Mar 03 02:45:00 PM PST 24
Peak memory 215452 kb
Host smart-05bd5f35-f4df-493a-b506-fb1ad92cbbbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135125300 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2135125300
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.1261160783
Short name T267
Test name
Test status
Simulation time 683305788205 ps
CPU time 2259.36 seconds
Started Mar 03 02:44:59 PM PST 24
Finished Mar 03 03:22:39 PM PST 24
Peak memory 227476 kb
Host smart-ab2a487a-fba7-4526-b28e-e845adc99b93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261160783 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.1261160783
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.2470598419
Short name T343
Test name
Test status
Simulation time 49195626 ps
CPU time 1.22 seconds
Started Mar 03 02:46:34 PM PST 24
Finished Mar 03 02:46:35 PM PST 24
Peak memory 215676 kb
Host smart-26951cca-ff7b-43c8-a465-2d0d390116d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470598419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2470598419
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.2687142969
Short name T697
Test name
Test status
Simulation time 58739962 ps
CPU time 1.15 seconds
Started Mar 03 02:46:36 PM PST 24
Finished Mar 03 02:46:37 PM PST 24
Peak memory 215336 kb
Host smart-4d2a6fb2-347a-454e-9df4-ebf5b664256b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687142969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2687142969
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.2448269317
Short name T598
Test name
Test status
Simulation time 72854044 ps
CPU time 1.15 seconds
Started Mar 03 02:46:35 PM PST 24
Finished Mar 03 02:46:36 PM PST 24
Peak memory 215168 kb
Host smart-e80f6ac7-2878-4ff4-aca3-571ba2b2edb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448269317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.2448269317
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.3783399952
Short name T370
Test name
Test status
Simulation time 158875930 ps
CPU time 3.29 seconds
Started Mar 03 02:46:37 PM PST 24
Finished Mar 03 02:46:41 PM PST 24
Peak memory 217576 kb
Host smart-07d8b66a-cd7f-421a-9665-4052e4834feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783399952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3783399952
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.1432345588
Short name T334
Test name
Test status
Simulation time 101296195 ps
CPU time 0.96 seconds
Started Mar 03 02:46:35 PM PST 24
Finished Mar 03 02:46:36 PM PST 24
Peak memory 215412 kb
Host smart-9c2ee263-5f60-4448-b840-b05809709b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432345588 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1432345588
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.690597290
Short name T555
Test name
Test status
Simulation time 57001931 ps
CPU time 1.24 seconds
Started Mar 03 02:46:38 PM PST 24
Finished Mar 03 02:46:39 PM PST 24
Peak memory 214104 kb
Host smart-65779f38-498c-4a09-8393-3710978617fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690597290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.690597290
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.1584408539
Short name T381
Test name
Test status
Simulation time 30397338 ps
CPU time 1.24 seconds
Started Mar 03 02:46:36 PM PST 24
Finished Mar 03 02:46:37 PM PST 24
Peak memory 216384 kb
Host smart-9feb6aed-e249-4f6e-b4e3-345f1ee2ebf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584408539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.1584408539
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.458567665
Short name T382
Test name
Test status
Simulation time 165249432 ps
CPU time 1.65 seconds
Started Mar 03 02:46:38 PM PST 24
Finished Mar 03 02:46:40 PM PST 24
Peak memory 216716 kb
Host smart-76f0cacb-fc3c-4e95-a73f-32c7def6ac82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458567665 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.458567665
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.1540213648
Short name T465
Test name
Test status
Simulation time 50789117 ps
CPU time 0.93 seconds
Started Mar 03 02:45:03 PM PST 24
Finished Mar 03 02:45:05 PM PST 24
Peak memory 205792 kb
Host smart-2affb672-ab98-4068-949b-7d40a132c63f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540213648 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1540213648
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.2759706597
Short name T115
Test name
Test status
Simulation time 16951681 ps
CPU time 0.85 seconds
Started Mar 03 02:45:02 PM PST 24
Finished Mar 03 02:45:03 PM PST 24
Peak memory 214620 kb
Host smart-b36e64c3-f354-4225-8ba4-4dcafbc0b396
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759706597 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.2759706597
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.971037978
Short name T500
Test name
Test status
Simulation time 135032673 ps
CPU time 1.23 seconds
Started Mar 03 02:45:02 PM PST 24
Finished Mar 03 02:45:03 PM PST 24
Peak memory 215516 kb
Host smart-9b77db5e-74ec-408b-b28a-9c64bec155d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971037978 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_di
sable_auto_req_mode.971037978
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.979352161
Short name T771
Test name
Test status
Simulation time 38146013 ps
CPU time 1.17 seconds
Started Mar 03 02:45:03 PM PST 24
Finished Mar 03 02:45:04 PM PST 24
Peak memory 218132 kb
Host smart-b4fadcf7-55b1-40af-b95b-49e69016e882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979352161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.979352161
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2666013820
Short name T709
Test name
Test status
Simulation time 33919383 ps
CPU time 1.28 seconds
Started Mar 03 02:45:00 PM PST 24
Finished Mar 03 02:45:01 PM PST 24
Peak memory 215188 kb
Host smart-78e213e5-94de-47f7-bf71-0cfce4488442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666013820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2666013820
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2297634635
Short name T647
Test name
Test status
Simulation time 25305773 ps
CPU time 1.05 seconds
Started Mar 03 02:44:59 PM PST 24
Finished Mar 03 02:45:00 PM PST 24
Peak memory 221980 kb
Host smart-9a645358-0e3d-48ba-aa4b-346ff5c99f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297634635 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2297634635
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.942567727
Short name T321
Test name
Test status
Simulation time 136206396 ps
CPU time 0.98 seconds
Started Mar 03 02:45:00 PM PST 24
Finished Mar 03 02:45:02 PM PST 24
Peak memory 214032 kb
Host smart-ec1390d0-81fc-404e-ab9f-8a92b42edde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942567727 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.942567727
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.4196842439
Short name T556
Test name
Test status
Simulation time 223363542 ps
CPU time 4.75 seconds
Started Mar 03 02:44:59 PM PST 24
Finished Mar 03 02:45:03 PM PST 24
Peak memory 215288 kb
Host smart-5683862c-75d2-4488-bd4b-86a55d6744a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196842439 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.4196842439
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.2917378916
Short name T453
Test name
Test status
Simulation time 600063753265 ps
CPU time 1222.34 seconds
Started Mar 03 02:45:02 PM PST 24
Finished Mar 03 03:05:24 PM PST 24
Peak memory 220100 kb
Host smart-d3d23c23-5c3c-4016-b1ea-bfce7b2d8760
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917378916 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.2917378916
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.4115498274
Short name T389
Test name
Test status
Simulation time 39423522 ps
CPU time 1.1 seconds
Started Mar 03 02:46:35 PM PST 24
Finished Mar 03 02:46:36 PM PST 24
Peak memory 215252 kb
Host smart-0562579f-81d7-449d-90e1-ca0692673875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115498274 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.4115498274
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.2994913443
Short name T183
Test name
Test status
Simulation time 98466616 ps
CPU time 2.69 seconds
Started Mar 03 02:46:38 PM PST 24
Finished Mar 03 02:46:41 PM PST 24
Peak memory 218140 kb
Host smart-371fada7-1791-43ad-b57d-079ceea20b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994913443 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2994913443
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.1616220070
Short name T71
Test name
Test status
Simulation time 82316671 ps
CPU time 1.22 seconds
Started Mar 03 02:46:35 PM PST 24
Finished Mar 03 02:46:37 PM PST 24
Peak memory 216932 kb
Host smart-7fdc80e0-fb4f-4f06-a369-02614fd7ac9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616220070 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1616220070
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.1428849995
Short name T446
Test name
Test status
Simulation time 46615550 ps
CPU time 1.13 seconds
Started Mar 03 02:46:34 PM PST 24
Finished Mar 03 02:46:36 PM PST 24
Peak memory 215276 kb
Host smart-a91f3c51-6b3a-4b99-bcbf-8d95c58e9112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428849995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1428849995
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.2863507410
Short name T794
Test name
Test status
Simulation time 10971004565 ps
CPU time 146.78 seconds
Started Mar 03 02:46:41 PM PST 24
Finished Mar 03 02:49:08 PM PST 24
Peak memory 217128 kb
Host smart-1027b7bf-e57a-458f-aed7-2b6f867ae4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863507410 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2863507410
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1246247442
Short name T719
Test name
Test status
Simulation time 44539837 ps
CPU time 1.21 seconds
Started Mar 03 02:46:41 PM PST 24
Finished Mar 03 02:46:42 PM PST 24
Peak memory 215288 kb
Host smart-1aa7de89-155f-4e5c-9663-4e147c54dbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246247442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1246247442
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.2621362199
Short name T528
Test name
Test status
Simulation time 48700807 ps
CPU time 1.26 seconds
Started Mar 03 02:46:41 PM PST 24
Finished Mar 03 02:46:43 PM PST 24
Peak memory 215188 kb
Host smart-edfbf579-4dfa-4865-ba84-4100026b0b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621362199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.2621362199
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.980421404
Short name T428
Test name
Test status
Simulation time 63502040 ps
CPU time 1.14 seconds
Started Mar 03 02:46:46 PM PST 24
Finished Mar 03 02:46:48 PM PST 24
Peak memory 215420 kb
Host smart-63806a64-3917-4904-8a92-aaab8a13a747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980421404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.980421404
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3802668130
Short name T760
Test name
Test status
Simulation time 172566083 ps
CPU time 1.26 seconds
Started Mar 03 02:45:03 PM PST 24
Finished Mar 03 02:45:04 PM PST 24
Peak memory 214560 kb
Host smart-21dfa93c-14a3-4f4d-98c2-e0745dae6290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802668130 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3802668130
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.426381304
Short name T431
Test name
Test status
Simulation time 51722853 ps
CPU time 0.91 seconds
Started Mar 03 02:45:03 PM PST 24
Finished Mar 03 02:45:04 PM PST 24
Peak memory 204972 kb
Host smart-1acf2681-2e27-4a7f-a1fa-d7ee6ef36672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426381304 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.426381304
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.3419919916
Short name T800
Test name
Test status
Simulation time 14111634 ps
CPU time 0.97 seconds
Started Mar 03 02:45:04 PM PST 24
Finished Mar 03 02:45:05 PM PST 24
Peak memory 214736 kb
Host smart-0abf8df2-3884-410c-a1d9-c6b0be803757
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419919916 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3419919916
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.4191439186
Short name T511
Test name
Test status
Simulation time 118883511 ps
CPU time 1.17 seconds
Started Mar 03 02:45:05 PM PST 24
Finished Mar 03 02:45:06 PM PST 24
Peak memory 215156 kb
Host smart-78f1c6fc-3026-4e8b-a118-86fb9d9430f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191439186 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.4191439186
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.543572947
Short name T558
Test name
Test status
Simulation time 19167612 ps
CPU time 1.12 seconds
Started Mar 03 02:45:01 PM PST 24
Finished Mar 03 02:45:02 PM PST 24
Peak memory 216928 kb
Host smart-8e398688-7983-47ba-bf08-ce1e18ba7db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543572947 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.543572947
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.2773139960
Short name T504
Test name
Test status
Simulation time 45223354 ps
CPU time 1.3 seconds
Started Mar 03 02:45:01 PM PST 24
Finished Mar 03 02:45:03 PM PST 24
Peak memory 216756 kb
Host smart-6ab49aae-4f1a-4c45-aa29-c5c68783a9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773139960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.2773139960
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2039827607
Short name T803
Test name
Test status
Simulation time 22751028 ps
CPU time 1.15 seconds
Started Mar 03 02:45:03 PM PST 24
Finished Mar 03 02:45:04 PM PST 24
Peak memory 222052 kb
Host smart-7d39c612-1aaa-4160-a497-80cc142543c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039827607 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2039827607
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.3898450585
Short name T527
Test name
Test status
Simulation time 83293104 ps
CPU time 0.88 seconds
Started Mar 03 02:45:02 PM PST 24
Finished Mar 03 02:45:03 PM PST 24
Peak memory 214116 kb
Host smart-7f96de0c-9a3e-4f9f-868f-0bccea16807e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898450585 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.3898450585
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1374529982
Short name T831
Test name
Test status
Simulation time 1541154342 ps
CPU time 5.43 seconds
Started Mar 03 02:45:04 PM PST 24
Finished Mar 03 02:45:10 PM PST 24
Peak memory 215336 kb
Host smart-539a21e1-ca64-4886-a5c4-2d7abdabf6f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374529982 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1374529982
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2589682388
Short name T24
Test name
Test status
Simulation time 93125846084 ps
CPU time 414.43 seconds
Started Mar 03 02:45:05 PM PST 24
Finished Mar 03 02:51:59 PM PST 24
Peak memory 218476 kb
Host smart-e9501ce6-ce6f-4279-9034-642cdfc4771e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589682388 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2589682388
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.1795988265
Short name T587
Test name
Test status
Simulation time 228927855 ps
CPU time 2.73 seconds
Started Mar 03 02:46:42 PM PST 24
Finished Mar 03 02:46:46 PM PST 24
Peak memory 216752 kb
Host smart-6240289b-23e4-4768-b355-3f7411ca8810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795988265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1795988265
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.1705200828
Short name T187
Test name
Test status
Simulation time 24593179 ps
CPU time 1.22 seconds
Started Mar 03 02:46:39 PM PST 24
Finished Mar 03 02:46:41 PM PST 24
Peak memory 216568 kb
Host smart-c66d9b9b-4dfe-4542-ac3b-81ce4ffffab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705200828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1705200828
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.3294623895
Short name T282
Test name
Test status
Simulation time 95379532 ps
CPU time 2.64 seconds
Started Mar 03 02:46:39 PM PST 24
Finished Mar 03 02:46:42 PM PST 24
Peak memory 216968 kb
Host smart-120c9514-9a6f-41f5-99d5-1d8a00ff3a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294623895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3294623895
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.2774509061
Short name T551
Test name
Test status
Simulation time 86626559 ps
CPU time 1.26 seconds
Started Mar 03 02:46:41 PM PST 24
Finished Mar 03 02:46:42 PM PST 24
Peak memory 215532 kb
Host smart-590a464a-4f71-49ac-82f7-a34cc98868e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774509061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2774509061
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.2479519852
Short name T692
Test name
Test status
Simulation time 87078791 ps
CPU time 1.16 seconds
Started Mar 03 02:46:42 PM PST 24
Finished Mar 03 02:46:43 PM PST 24
Peak memory 215396 kb
Host smart-5563e3e6-282b-4260-8ea5-2452ffa34ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479519852 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.2479519852
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.2609126486
Short name T766
Test name
Test status
Simulation time 47066771 ps
CPU time 1.1 seconds
Started Mar 03 02:46:42 PM PST 24
Finished Mar 03 02:46:43 PM PST 24
Peak memory 216436 kb
Host smart-158de952-77a9-4662-966c-98634a8b873b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609126486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2609126486
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.3253271653
Short name T182
Test name
Test status
Simulation time 41123515 ps
CPU time 1.47 seconds
Started Mar 03 02:46:39 PM PST 24
Finished Mar 03 02:46:41 PM PST 24
Peak memory 216764 kb
Host smart-4488c3b7-ce70-4115-8be6-07c94e07f408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253271653 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3253271653
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1696870933
Short name T283
Test name
Test status
Simulation time 56032109 ps
CPU time 1.34 seconds
Started Mar 03 02:46:40 PM PST 24
Finished Mar 03 02:46:42 PM PST 24
Peak memory 214104 kb
Host smart-5eec72fb-2719-4eda-9d8c-c5981add072e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696870933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1696870933
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2479432390
Short name T755
Test name
Test status
Simulation time 26197335 ps
CPU time 1.27 seconds
Started Mar 03 02:45:03 PM PST 24
Finished Mar 03 02:45:04 PM PST 24
Peak memory 214568 kb
Host smart-49a89442-39d1-48e9-b107-7cbea3921658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479432390 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2479432390
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.2579599607
Short name T756
Test name
Test status
Simulation time 26776517 ps
CPU time 0.93 seconds
Started Mar 03 02:45:08 PM PST 24
Finished Mar 03 02:45:09 PM PST 24
Peak memory 205452 kb
Host smart-0a7cfbb6-22b6-48dd-824d-097307fe31cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579599607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.2579599607
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.2366267383
Short name T738
Test name
Test status
Simulation time 16221785 ps
CPU time 0.9 seconds
Started Mar 03 02:45:12 PM PST 24
Finished Mar 03 02:45:13 PM PST 24
Peak memory 214276 kb
Host smart-b0ed6bd6-3c5c-4964-8770-452a0be65aba
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366267383 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.2366267383
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2696671479
Short name T512
Test name
Test status
Simulation time 51572070 ps
CPU time 0.95 seconds
Started Mar 03 02:45:09 PM PST 24
Finished Mar 03 02:45:10 PM PST 24
Peak memory 216484 kb
Host smart-a49ce554-cbe6-4cf5-8c92-f33144cb22d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696671479 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2696671479
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2579012679
Short name T774
Test name
Test status
Simulation time 18145580 ps
CPU time 1.1 seconds
Started Mar 03 02:45:07 PM PST 24
Finished Mar 03 02:45:09 PM PST 24
Peak memory 221868 kb
Host smart-4733889e-a750-40ac-8bfc-f2f755dbb6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579012679 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2579012679
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.274577335
Short name T338
Test name
Test status
Simulation time 36447801 ps
CPU time 1.44 seconds
Started Mar 03 02:45:02 PM PST 24
Finished Mar 03 02:45:03 PM PST 24
Peak memory 215472 kb
Host smart-6eb80bf3-cb9a-44fe-83a0-3b9d6ac316e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274577335 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.274577335
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.677022966
Short name T753
Test name
Test status
Simulation time 25461534 ps
CPU time 0.99 seconds
Started Mar 03 02:45:05 PM PST 24
Finished Mar 03 02:45:06 PM PST 24
Peak memory 214452 kb
Host smart-85db3420-2f8b-47d3-a0b3-851e054af889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677022966 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.677022966
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2340112842
Short name T417
Test name
Test status
Simulation time 15530047 ps
CPU time 0.97 seconds
Started Mar 03 02:45:03 PM PST 24
Finished Mar 03 02:45:04 PM PST 24
Peak memory 214108 kb
Host smart-ba016a99-3ac7-4d83-8362-7f62144f5f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340112842 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2340112842
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.4076665236
Short name T494
Test name
Test status
Simulation time 1944635180 ps
CPU time 3.9 seconds
Started Mar 03 02:45:05 PM PST 24
Finished Mar 03 02:45:09 PM PST 24
Peak memory 215408 kb
Host smart-47f733c2-64f0-4240-b696-004ea818ec9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076665236 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.4076665236
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.4092598594
Short name T735
Test name
Test status
Simulation time 13702330056 ps
CPU time 158.02 seconds
Started Mar 03 02:45:03 PM PST 24
Finished Mar 03 02:47:41 PM PST 24
Peak memory 216524 kb
Host smart-a905e4be-2e24-4dbb-beca-6845b3310d11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092598594 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.4092598594
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.1698899674
Short name T266
Test name
Test status
Simulation time 130507516 ps
CPU time 1.15 seconds
Started Mar 03 02:46:40 PM PST 24
Finished Mar 03 02:46:41 PM PST 24
Peak memory 215460 kb
Host smart-c062869e-39e0-43ee-bc0c-0385704adfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698899674 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.1698899674
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.3607469442
Short name T729
Test name
Test status
Simulation time 38737834 ps
CPU time 1.49 seconds
Started Mar 03 02:46:44 PM PST 24
Finished Mar 03 02:46:46 PM PST 24
Peak memory 216368 kb
Host smart-bbc29104-713a-4abc-9d61-181215341f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607469442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.3607469442
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.3982772320
Short name T272
Test name
Test status
Simulation time 144717021 ps
CPU time 1.05 seconds
Started Mar 03 02:46:43 PM PST 24
Finished Mar 03 02:46:45 PM PST 24
Peak memory 215308 kb
Host smart-3b9c61cf-0a05-4e75-b901-c6db586c02a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982772320 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3982772320
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.2449670637
Short name T41
Test name
Test status
Simulation time 50375192 ps
CPU time 1.71 seconds
Started Mar 03 02:46:41 PM PST 24
Finished Mar 03 02:46:43 PM PST 24
Peak memory 217992 kb
Host smart-4cb65e44-d9aa-4bba-a7c8-d0c7aab429e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449670637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2449670637
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.2327383596
Short name T384
Test name
Test status
Simulation time 43136524 ps
CPU time 1.23 seconds
Started Mar 03 02:46:40 PM PST 24
Finished Mar 03 02:46:41 PM PST 24
Peak memory 216828 kb
Host smart-ce06696a-e942-466a-8f99-dfc22e781e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327383596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2327383596
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.125081541
Short name T707
Test name
Test status
Simulation time 53157795 ps
CPU time 1.16 seconds
Started Mar 03 02:46:42 PM PST 24
Finished Mar 03 02:46:43 PM PST 24
Peak memory 215272 kb
Host smart-042255ed-cf15-460e-9bb3-a2a461bb87af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125081541 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.125081541
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.1726444574
Short name T743
Test name
Test status
Simulation time 69407890 ps
CPU time 1.23 seconds
Started Mar 03 02:46:41 PM PST 24
Finished Mar 03 02:46:42 PM PST 24
Peak memory 215420 kb
Host smart-c1c5a4f8-82d8-425c-9fa9-70c70d82bbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726444574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.1726444574
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.2522041038
Short name T817
Test name
Test status
Simulation time 28647307 ps
CPU time 1.17 seconds
Started Mar 03 02:46:42 PM PST 24
Finished Mar 03 02:46:44 PM PST 24
Peak memory 215156 kb
Host smart-05fe27bc-cb3d-4acf-ad45-9c1e08fa277f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522041038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2522041038
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.6810074
Short name T151
Test name
Test status
Simulation time 24201477 ps
CPU time 1.21 seconds
Started Mar 03 02:45:08 PM PST 24
Finished Mar 03 02:45:10 PM PST 24
Peak memory 214568 kb
Host smart-650961b1-d7cb-40b1-9de0-fede72c74bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6810074 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.6810074
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_err.3087695927
Short name T583
Test name
Test status
Simulation time 44537855 ps
CPU time 1.09 seconds
Started Mar 03 02:45:10 PM PST 24
Finished Mar 03 02:45:12 PM PST 24
Peak memory 218048 kb
Host smart-df03a4ff-707f-4270-b94e-e4e4dbcdc542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087695927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3087695927
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_intr.2423455792
Short name T481
Test name
Test status
Simulation time 24631203 ps
CPU time 1.03 seconds
Started Mar 03 02:45:12 PM PST 24
Finished Mar 03 02:45:13 PM PST 24
Peak memory 221952 kb
Host smart-9db74183-324c-4e44-96b2-8e0a34464da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423455792 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2423455792
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1326084193
Short name T655
Test name
Test status
Simulation time 18755984 ps
CPU time 0.98 seconds
Started Mar 03 02:45:09 PM PST 24
Finished Mar 03 02:45:10 PM PST 24
Peak memory 214020 kb
Host smart-8995009e-f1ae-4c92-aae5-26b177a7399d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326084193 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1326084193
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.3921028243
Short name T331
Test name
Test status
Simulation time 183938466 ps
CPU time 1.22 seconds
Started Mar 03 02:45:10 PM PST 24
Finished Mar 03 02:45:12 PM PST 24
Peak memory 214100 kb
Host smart-057c01ae-e724-454b-ba0b-5aed654e722a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921028243 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.3921028243
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.2362352776
Short name T764
Test name
Test status
Simulation time 26228174568 ps
CPU time 705.96 seconds
Started Mar 03 02:45:09 PM PST 24
Finished Mar 03 02:56:55 PM PST 24
Peak memory 218880 kb
Host smart-fa7c5b80-8e71-483c-9521-6d39a1fc1343
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362352776 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.2362352776
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.406824863
Short name T653
Test name
Test status
Simulation time 61439880 ps
CPU time 1.31 seconds
Started Mar 03 02:46:42 PM PST 24
Finished Mar 03 02:46:44 PM PST 24
Peak memory 216508 kb
Host smart-10fc9550-8608-4a5f-b208-15f6f3d09e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406824863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.406824863
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.2359117990
Short name T451
Test name
Test status
Simulation time 85756306 ps
CPU time 1.19 seconds
Started Mar 03 02:46:43 PM PST 24
Finished Mar 03 02:46:45 PM PST 24
Peak memory 215716 kb
Host smart-e38aac03-b96b-43b4-adad-309325265f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359117990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2359117990
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.3944343910
Short name T177
Test name
Test status
Simulation time 50290871 ps
CPU time 1.49 seconds
Started Mar 03 02:46:43 PM PST 24
Finished Mar 03 02:46:45 PM PST 24
Peak memory 218204 kb
Host smart-4375ddaa-6bcd-4367-95f0-0bc6410aac3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944343910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3944343910
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.976849389
Short name T327
Test name
Test status
Simulation time 50563396 ps
CPU time 1.22 seconds
Started Mar 03 02:46:46 PM PST 24
Finished Mar 03 02:46:48 PM PST 24
Peak memory 216804 kb
Host smart-a0e39fa5-42d7-479b-9892-cee74bc880d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976849389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.976849389
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.514143783
Short name T625
Test name
Test status
Simulation time 69736299 ps
CPU time 1.14 seconds
Started Mar 03 02:46:38 PM PST 24
Finished Mar 03 02:46:39 PM PST 24
Peak memory 215624 kb
Host smart-0a30e12e-4cba-4275-bd3d-280e4988ebfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514143783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.514143783
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.1305466052
Short name T278
Test name
Test status
Simulation time 45456961 ps
CPU time 1.65 seconds
Started Mar 03 02:46:42 PM PST 24
Finished Mar 03 02:46:45 PM PST 24
Peak memory 216936 kb
Host smart-91c507cb-4696-4016-ab79-54b1b00d04e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305466052 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.1305466052
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.58400065
Short name T790
Test name
Test status
Simulation time 65137209 ps
CPU time 1.29 seconds
Started Mar 03 02:46:40 PM PST 24
Finished Mar 03 02:46:42 PM PST 24
Peak memory 216696 kb
Host smart-a38e0351-8888-4e03-a66d-1ea7159e3c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58400065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.58400065
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.2593830726
Short name T350
Test name
Test status
Simulation time 140830467 ps
CPU time 1.64 seconds
Started Mar 03 02:46:44 PM PST 24
Finished Mar 03 02:46:46 PM PST 24
Peak memory 217168 kb
Host smart-65cb2cd0-eb25-442d-b637-3495669fe294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593830726 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.2593830726
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.69625057
Short name T563
Test name
Test status
Simulation time 53635571 ps
CPU time 1.17 seconds
Started Mar 03 02:46:46 PM PST 24
Finished Mar 03 02:46:48 PM PST 24
Peak memory 215172 kb
Host smart-f518c4bd-1c48-4a03-bade-9d3dc40802cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69625057 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.69625057
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.121730139
Short name T545
Test name
Test status
Simulation time 299504477 ps
CPU time 4.48 seconds
Started Mar 03 02:46:42 PM PST 24
Finished Mar 03 02:46:46 PM PST 24
Peak memory 218588 kb
Host smart-58dae3f9-d975-473e-8ff2-699fcbbf552b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121730139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.121730139
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2734380183
Short name T150
Test name
Test status
Simulation time 51636015 ps
CPU time 1.11 seconds
Started Mar 03 02:45:07 PM PST 24
Finished Mar 03 02:45:09 PM PST 24
Peak memory 214560 kb
Host smart-2fbf0c76-a24c-413c-8195-c641b286bb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734380183 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2734380183
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2042199658
Short name T375
Test name
Test status
Simulation time 18372953 ps
CPU time 1 seconds
Started Mar 03 02:45:14 PM PST 24
Finished Mar 03 02:45:15 PM PST 24
Peak memory 205644 kb
Host smart-d8797efd-8dd3-430a-a45c-cf4309583a4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042199658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2042199658
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3204543038
Short name T30
Test name
Test status
Simulation time 17676299 ps
CPU time 0.85 seconds
Started Mar 03 02:45:14 PM PST 24
Finished Mar 03 02:45:15 PM PST 24
Peak memory 214800 kb
Host smart-f7245eec-1afa-47a5-bfc4-6143cdf5b139
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204543038 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3204543038
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.2261681107
Short name T488
Test name
Test status
Simulation time 77942926 ps
CPU time 1.09 seconds
Started Mar 03 02:45:08 PM PST 24
Finished Mar 03 02:45:10 PM PST 24
Peak memory 217964 kb
Host smart-fa4e6856-1641-44a4-bf04-a8f54909e97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261681107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.2261681107
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.562296066
Short name T619
Test name
Test status
Simulation time 32193925 ps
CPU time 1.45 seconds
Started Mar 03 02:45:07 PM PST 24
Finished Mar 03 02:45:09 PM PST 24
Peak memory 216756 kb
Host smart-18ce7edf-01ee-413d-b60b-dd8cd5b0f024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562296066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.562296066
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.3022357091
Short name T140
Test name
Test status
Simulation time 22336354 ps
CPU time 1.05 seconds
Started Mar 03 02:45:08 PM PST 24
Finished Mar 03 02:45:09 PM PST 24
Peak memory 214476 kb
Host smart-46388928-5014-42fe-af0a-cba89ee6d106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022357091 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.3022357091
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.4061836471
Short name T637
Test name
Test status
Simulation time 26108833 ps
CPU time 1 seconds
Started Mar 03 02:45:14 PM PST 24
Finished Mar 03 02:45:15 PM PST 24
Peak memory 214300 kb
Host smart-c8c55895-b77d-41e1-9805-bfb534b8a9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061836471 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.4061836471
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.2994249428
Short name T819
Test name
Test status
Simulation time 253621401 ps
CPU time 5.07 seconds
Started Mar 03 02:45:10 PM PST 24
Finished Mar 03 02:45:15 PM PST 24
Peak memory 216516 kb
Host smart-87d04c78-a5ac-4635-affe-7881529c3be9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994249428 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.2994249428
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.363516914
Short name T624
Test name
Test status
Simulation time 37030942639 ps
CPU time 284.74 seconds
Started Mar 03 02:45:09 PM PST 24
Finished Mar 03 02:49:54 PM PST 24
Peak memory 218748 kb
Host smart-6f1def5d-9779-4929-9be8-32b9b5dbceb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363516914 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.363516914
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.4043721911
Short name T405
Test name
Test status
Simulation time 732676576 ps
CPU time 5.92 seconds
Started Mar 03 02:46:41 PM PST 24
Finished Mar 03 02:46:47 PM PST 24
Peak memory 215756 kb
Host smart-2c4e059a-057e-410b-a472-89905695c933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043721911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.4043721911
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.3175454271
Short name T475
Test name
Test status
Simulation time 69124193 ps
CPU time 1.08 seconds
Started Mar 03 02:46:42 PM PST 24
Finished Mar 03 02:46:44 PM PST 24
Peak memory 215412 kb
Host smart-7208479d-6ff1-4f1a-b43b-262a2fc4262e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175454271 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.3175454271
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.4080064777
Short name T225
Test name
Test status
Simulation time 248368653 ps
CPU time 1.04 seconds
Started Mar 03 02:46:42 PM PST 24
Finished Mar 03 02:46:43 PM PST 24
Peak memory 215348 kb
Host smart-9ef9c200-2e0b-4d32-9331-3ac81a5fa38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080064777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.4080064777
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.4226007455
Short name T295
Test name
Test status
Simulation time 131777950 ps
CPU time 2.95 seconds
Started Mar 03 02:46:46 PM PST 24
Finished Mar 03 02:46:49 PM PST 24
Peak memory 218420 kb
Host smart-cb760e38-12ad-44a3-a981-ce5c8373de1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226007455 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.4226007455
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.591012780
Short name T684
Test name
Test status
Simulation time 94254652 ps
CPU time 1.34 seconds
Started Mar 03 02:46:42 PM PST 24
Finished Mar 03 02:46:44 PM PST 24
Peak memory 217104 kb
Host smart-99a4690b-2da0-43d8-b6f0-18c1ac29dfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591012780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.591012780
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.1157939166
Short name T441
Test name
Test status
Simulation time 33232986 ps
CPU time 1.41 seconds
Started Mar 03 02:46:46 PM PST 24
Finished Mar 03 02:46:48 PM PST 24
Peak memory 215624 kb
Host smart-c0c3ed68-38ab-4ef1-a892-c9d3b4b615be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157939166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1157939166
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.2921734857
Short name T247
Test name
Test status
Simulation time 45091809 ps
CPU time 1.16 seconds
Started Mar 03 02:46:47 PM PST 24
Finished Mar 03 02:46:49 PM PST 24
Peak memory 218092 kb
Host smart-a753df0f-3bd9-44e5-8563-e18734f9b72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921734857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2921734857
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.2293899540
Short name T741
Test name
Test status
Simulation time 45647415 ps
CPU time 1.5 seconds
Started Mar 03 02:46:49 PM PST 24
Finished Mar 03 02:46:50 PM PST 24
Peak memory 216324 kb
Host smart-f09684a5-e0b1-4065-a130-424db965fcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293899540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2293899540
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.1467074111
Short name T60
Test name
Test status
Simulation time 248917842 ps
CPU time 3.32 seconds
Started Mar 03 02:46:48 PM PST 24
Finished Mar 03 02:46:52 PM PST 24
Peak memory 215552 kb
Host smart-b7bd2638-ea5c-4a59-991a-68806678d367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467074111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1467074111
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.159782819
Short name T341
Test name
Test status
Simulation time 91959773 ps
CPU time 1.34 seconds
Started Mar 03 02:46:45 PM PST 24
Finished Mar 03 02:46:47 PM PST 24
Peak memory 216640 kb
Host smart-1fc4c140-c072-4e2b-8f89-f037746cf8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159782819 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.159782819
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.2617034993
Short name T724
Test name
Test status
Simulation time 53224336 ps
CPU time 0.9 seconds
Started Mar 03 02:45:16 PM PST 24
Finished Mar 03 02:45:17 PM PST 24
Peak memory 205752 kb
Host smart-387f15b4-0fb9-4051-ac5e-14a3e7b6e5b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617034993 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2617034993
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.2457090434
Short name T91
Test name
Test status
Simulation time 25617915 ps
CPU time 1.17 seconds
Started Mar 03 02:45:19 PM PST 24
Finished Mar 03 02:45:20 PM PST 24
Peak memory 215056 kb
Host smart-1daace87-b85c-4ece-b42d-34f9cb472de2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457090434 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.2457090434
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2715021258
Short name T758
Test name
Test status
Simulation time 26354906 ps
CPU time 1.22 seconds
Started Mar 03 02:45:11 PM PST 24
Finished Mar 03 02:45:13 PM PST 24
Peak memory 219176 kb
Host smart-72761152-ebd8-44bd-9b1e-41ff46b9028d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715021258 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2715021258
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.295563102
Short name T468
Test name
Test status
Simulation time 71816386 ps
CPU time 1.85 seconds
Started Mar 03 02:45:09 PM PST 24
Finished Mar 03 02:45:12 PM PST 24
Peak memory 215764 kb
Host smart-4fdcfe80-3d0c-43c4-a6b9-ab787cc35aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295563102 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.295563102
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_smoke.2435070001
Short name T603
Test name
Test status
Simulation time 16609794 ps
CPU time 0.99 seconds
Started Mar 03 02:45:09 PM PST 24
Finished Mar 03 02:45:11 PM PST 24
Peak memory 214116 kb
Host smart-a156c1b7-173a-472a-833d-be751a98e73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435070001 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.2435070001
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3573907587
Short name T464
Test name
Test status
Simulation time 219700041 ps
CPU time 1.74 seconds
Started Mar 03 02:45:10 PM PST 24
Finished Mar 03 02:45:12 PM PST 24
Peak memory 215152 kb
Host smart-4524fe12-59c5-4dff-935c-0ceee5e14f2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573907587 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3573907587
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.3090049626
Short name T193
Test name
Test status
Simulation time 258403211366 ps
CPU time 1437.81 seconds
Started Mar 03 02:45:08 PM PST 24
Finished Mar 03 03:09:06 PM PST 24
Peak memory 222280 kb
Host smart-b7869a6d-ede1-433d-96ec-6d1dfc646773
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090049626 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.3090049626
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.1690956013
Short name T690
Test name
Test status
Simulation time 45742643 ps
CPU time 1.55 seconds
Started Mar 03 02:46:47 PM PST 24
Finished Mar 03 02:46:49 PM PST 24
Peak memory 216604 kb
Host smart-ea28f70c-dc78-4dc1-aa35-bb83ba214e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690956013 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.1690956013
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.4093912265
Short name T510
Test name
Test status
Simulation time 155211445 ps
CPU time 3.36 seconds
Started Mar 03 02:46:56 PM PST 24
Finished Mar 03 02:47:00 PM PST 24
Peak memory 216800 kb
Host smart-abcdbcc8-92ff-42a1-9534-ac5ba904c4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093912265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.4093912265
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.4162531769
Short name T698
Test name
Test status
Simulation time 112642568 ps
CPU time 1.49 seconds
Started Mar 03 02:46:47 PM PST 24
Finished Mar 03 02:46:49 PM PST 24
Peak memory 217208 kb
Host smart-75062edd-444f-4681-9ded-dfd92aadb0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162531769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.4162531769
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.1053582820
Short name T513
Test name
Test status
Simulation time 45644348 ps
CPU time 1.68 seconds
Started Mar 03 02:46:56 PM PST 24
Finished Mar 03 02:46:58 PM PST 24
Peak memory 216612 kb
Host smart-ba3c0e64-13c3-4887-bfe3-62548b3b8237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053582820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1053582820
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.2810745801
Short name T32
Test name
Test status
Simulation time 118991178 ps
CPU time 1.19 seconds
Started Mar 03 02:46:56 PM PST 24
Finished Mar 03 02:46:57 PM PST 24
Peak memory 215260 kb
Host smart-f514fe38-29b8-4da3-be00-c3d5d8dd78a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810745801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2810745801
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.2852062929
Short name T337
Test name
Test status
Simulation time 46230827 ps
CPU time 1.19 seconds
Started Mar 03 02:46:46 PM PST 24
Finished Mar 03 02:46:48 PM PST 24
Peak memory 215424 kb
Host smart-cb7393e2-8e30-4878-965b-8fd4c9b6acaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852062929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.2852062929
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.2161089368
Short name T369
Test name
Test status
Simulation time 75086868 ps
CPU time 1.74 seconds
Started Mar 03 02:46:46 PM PST 24
Finished Mar 03 02:46:49 PM PST 24
Peak memory 216712 kb
Host smart-77f189ba-5315-445c-99ee-8ed7de360d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161089368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.2161089368
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.1816885210
Short name T400
Test name
Test status
Simulation time 40693723 ps
CPU time 1.53 seconds
Started Mar 03 02:46:49 PM PST 24
Finished Mar 03 02:46:50 PM PST 24
Peak memory 216600 kb
Host smart-3aa39e78-8b6b-48e9-96be-bcde2d0637d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816885210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.1816885210
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1844263965
Short name T702
Test name
Test status
Simulation time 26506700 ps
CPU time 1.14 seconds
Started Mar 03 02:46:47 PM PST 24
Finished Mar 03 02:46:49 PM PST 24
Peak memory 215232 kb
Host smart-d56f200c-12c5-495c-9a41-e48c37fe39e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844263965 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1844263965
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.504357679
Short name T360
Test name
Test status
Simulation time 49753895 ps
CPU time 1.71 seconds
Started Mar 03 02:46:46 PM PST 24
Finished Mar 03 02:46:48 PM PST 24
Peak memory 216516 kb
Host smart-e89a8a9c-8287-4a73-88e5-b94dd8b14ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504357679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.504357679
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1438790148
Short name T15
Test name
Test status
Simulation time 30032099 ps
CPU time 1.12 seconds
Started Mar 03 02:45:13 PM PST 24
Finished Mar 03 02:45:14 PM PST 24
Peak memory 214568 kb
Host smart-f8ff4dbd-5dd1-46bf-8c68-dbbcf660db26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438790148 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1438790148
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3477020921
Short name T793
Test name
Test status
Simulation time 58751552 ps
CPU time 0.95 seconds
Started Mar 03 02:45:14 PM PST 24
Finished Mar 03 02:45:16 PM PST 24
Peak memory 205460 kb
Host smart-35a13a3f-1d3f-4558-a3a6-6dd2ab93cd56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477020921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3477020921
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1249193912
Short name T33
Test name
Test status
Simulation time 44094431 ps
CPU time 1.03 seconds
Started Mar 03 02:45:12 PM PST 24
Finished Mar 03 02:45:14 PM PST 24
Peak memory 216388 kb
Host smart-d3955ef0-9209-493f-b3b1-349fcb582950
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249193912 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1249193912
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2343545951
Short name T102
Test name
Test status
Simulation time 23274446 ps
CPU time 1 seconds
Started Mar 03 02:45:13 PM PST 24
Finished Mar 03 02:45:14 PM PST 24
Peak memory 216908 kb
Host smart-7e2bfd1b-8467-4970-8dbf-f9c0201ae9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343545951 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2343545951
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.2704004037
Short name T62
Test name
Test status
Simulation time 41480374 ps
CPU time 1.57 seconds
Started Mar 03 02:45:10 PM PST 24
Finished Mar 03 02:45:12 PM PST 24
Peak memory 215540 kb
Host smart-3bfd737c-e079-4ae8-bb41-687c1a3d949b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704004037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2704004037
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3539872682
Short name T364
Test name
Test status
Simulation time 34553553 ps
CPU time 0.9 seconds
Started Mar 03 02:45:14 PM PST 24
Finished Mar 03 02:45:15 PM PST 24
Peak memory 214500 kb
Host smart-61b5fa59-5f90-4c04-becf-58eee8538bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539872682 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3539872682
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.2917187719
Short name T371
Test name
Test status
Simulation time 49627976 ps
CPU time 0.88 seconds
Started Mar 03 02:45:13 PM PST 24
Finished Mar 03 02:45:14 PM PST 24
Peak memory 214128 kb
Host smart-88b81d46-79f3-4d89-91a9-4ae1e9584845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917187719 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.2917187719
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.220099301
Short name T345
Test name
Test status
Simulation time 158295673 ps
CPU time 3.41 seconds
Started Mar 03 02:45:12 PM PST 24
Finished Mar 03 02:45:16 PM PST 24
Peak memory 214124 kb
Host smart-f801e823-f175-4e03-ba9f-bf313e143c20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220099301 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.220099301
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.2492011034
Short name T190
Test name
Test status
Simulation time 1493567923789 ps
CPU time 1849.75 seconds
Started Mar 03 02:45:13 PM PST 24
Finished Mar 03 03:16:03 PM PST 24
Peak memory 223316 kb
Host smart-573904c2-d2b7-4d80-8e1a-a8d4dc4d2bc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492011034 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.2492011034
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.2646137252
Short name T601
Test name
Test status
Simulation time 36279628 ps
CPU time 1.14 seconds
Started Mar 03 02:46:47 PM PST 24
Finished Mar 03 02:46:49 PM PST 24
Peak memory 215712 kb
Host smart-d0e3919a-1b28-4376-baf6-544f0bd4664c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646137252 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.2646137252
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.159764874
Short name T604
Test name
Test status
Simulation time 60225222 ps
CPU time 1.75 seconds
Started Mar 03 02:46:46 PM PST 24
Finished Mar 03 02:46:48 PM PST 24
Peak memory 216528 kb
Host smart-9e73f91d-e9ba-426d-b862-d47631051671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159764874 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.159764874
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.3884285395
Short name T461
Test name
Test status
Simulation time 107772010 ps
CPU time 1.38 seconds
Started Mar 03 02:46:46 PM PST 24
Finished Mar 03 02:46:48 PM PST 24
Peak memory 215452 kb
Host smart-893591f2-6350-4998-9f01-a8ffd633adb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884285395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3884285395
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.1808852644
Short name T298
Test name
Test status
Simulation time 130354418 ps
CPU time 2.72 seconds
Started Mar 03 02:46:56 PM PST 24
Finished Mar 03 02:46:59 PM PST 24
Peak memory 216776 kb
Host smart-f8d9ec8e-3adc-44c8-b9c3-4043033581e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808852644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.1808852644
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.3821607793
Short name T346
Test name
Test status
Simulation time 30971167 ps
CPU time 1.38 seconds
Started Mar 03 02:46:46 PM PST 24
Finished Mar 03 02:46:48 PM PST 24
Peak memory 215412 kb
Host smart-3fbedd1c-8aac-4c5a-8f61-46d213bac310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821607793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.3821607793
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.2697318830
Short name T275
Test name
Test status
Simulation time 83037454 ps
CPU time 1.5 seconds
Started Mar 03 02:46:56 PM PST 24
Finished Mar 03 02:46:58 PM PST 24
Peak memory 216504 kb
Host smart-1925a425-2239-4914-9c07-3330a239f6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697318830 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.2697318830
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.3558300440
Short name T537
Test name
Test status
Simulation time 124651406 ps
CPU time 1.73 seconds
Started Mar 03 02:46:49 PM PST 24
Finished Mar 03 02:46:51 PM PST 24
Peak memory 216936 kb
Host smart-800801b9-55da-46f6-8eba-a16bb8f84df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558300440 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.3558300440
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.1918030783
Short name T745
Test name
Test status
Simulation time 29062307 ps
CPU time 1.24 seconds
Started Mar 03 02:46:56 PM PST 24
Finished Mar 03 02:46:58 PM PST 24
Peak memory 215396 kb
Host smart-4366a2c6-233c-42a8-a93c-03ee10c54b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918030783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1918030783
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.2072654161
Short name T383
Test name
Test status
Simulation time 40333802 ps
CPU time 1.13 seconds
Started Mar 03 02:46:54 PM PST 24
Finished Mar 03 02:46:56 PM PST 24
Peak memory 214148 kb
Host smart-af92a077-3541-4058-8d5c-abf84db0fd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072654161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.2072654161
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert_test.965529520
Short name T315
Test name
Test status
Simulation time 31945144 ps
CPU time 1.01 seconds
Started Mar 03 02:44:39 PM PST 24
Finished Mar 03 02:44:40 PM PST 24
Peak memory 205544 kb
Host smart-31e42cbe-44fd-4d64-aac0-aa98693ca260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965529520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.965529520
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.2535944991
Short name T103
Test name
Test status
Simulation time 41807900 ps
CPU time 0.89 seconds
Started Mar 03 02:44:34 PM PST 24
Finished Mar 03 02:44:35 PM PST 24
Peak memory 214624 kb
Host smart-26d63945-6357-43ea-9ca8-ee5ceca0d4de
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535944991 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.2535944991
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.722985821
Short name T779
Test name
Test status
Simulation time 75639583 ps
CPU time 1.01 seconds
Started Mar 03 02:44:37 PM PST 24
Finished Mar 03 02:44:38 PM PST 24
Peak memory 216584 kb
Host smart-3547efe0-1ec9-4ca5-8d7d-fc6c65458357
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722985821 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.722985821
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.748021486
Short name T163
Test name
Test status
Simulation time 41541721 ps
CPU time 1.09 seconds
Started Mar 03 02:44:42 PM PST 24
Finished Mar 03 02:44:43 PM PST 24
Peak memory 217928 kb
Host smart-9299de55-c260-45e8-95dc-b3361f0dd827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748021486 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.748021486
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.1839797950
Short name T292
Test name
Test status
Simulation time 89519611 ps
CPU time 1.25 seconds
Started Mar 03 02:44:30 PM PST 24
Finished Mar 03 02:44:31 PM PST 24
Peak memory 218048 kb
Host smart-91f66e3f-158c-47c7-abc6-690d860c66db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839797950 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.1839797950
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.4209537106
Short name T359
Test name
Test status
Simulation time 23109178 ps
CPU time 0.93 seconds
Started Mar 03 02:44:35 PM PST 24
Finished Mar 03 02:44:37 PM PST 24
Peak memory 214432 kb
Host smart-574e99c2-eb67-4943-a452-88fdf4eaf7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209537106 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.4209537106
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3913545679
Short name T246
Test name
Test status
Simulation time 33151035 ps
CPU time 0.91 seconds
Started Mar 03 02:44:30 PM PST 24
Finished Mar 03 02:44:31 PM PST 24
Peak memory 205908 kb
Host smart-b0583b3a-67df-4827-98ea-ebb0ed0e4c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913545679 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3913545679
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2319685970
Short name T20
Test name
Test status
Simulation time 2045242021 ps
CPU time 5.85 seconds
Started Mar 03 02:44:35 PM PST 24
Finished Mar 03 02:44:41 PM PST 24
Peak memory 235552 kb
Host smart-80c54fb8-d922-4232-bf9f-7f054a121f4c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319685970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2319685970
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.878947618
Short name T450
Test name
Test status
Simulation time 71975852 ps
CPU time 0.91 seconds
Started Mar 03 02:44:29 PM PST 24
Finished Mar 03 02:44:31 PM PST 24
Peak memory 214104 kb
Host smart-74e05a1c-f523-44da-82b5-399b3456dc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878947618 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.878947618
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.688697684
Short name T633
Test name
Test status
Simulation time 548879031 ps
CPU time 5.85 seconds
Started Mar 03 02:44:36 PM PST 24
Finished Mar 03 02:44:42 PM PST 24
Peak memory 215252 kb
Host smart-3e167646-9efd-424a-b3e9-937f3322e456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688697684 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.688697684
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.774406450
Short name T273
Test name
Test status
Simulation time 94551300648 ps
CPU time 2115.32 seconds
Started Mar 03 02:44:44 PM PST 24
Finished Mar 03 03:19:59 PM PST 24
Peak memory 225868 kb
Host smart-9122be09-4cd1-4671-be47-b0ffc4036093
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774406450 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.774406450
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert_test.1826237941
Short name T344
Test name
Test status
Simulation time 74913187 ps
CPU time 0.85 seconds
Started Mar 03 02:45:15 PM PST 24
Finished Mar 03 02:45:16 PM PST 24
Peak memory 205716 kb
Host smart-1b7e2ccf-5475-45aa-af58-c3ceb08a7379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826237941 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1826237941
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.3543722730
Short name T164
Test name
Test status
Simulation time 26541079 ps
CPU time 0.82 seconds
Started Mar 03 02:45:15 PM PST 24
Finished Mar 03 02:45:16 PM PST 24
Peak memory 214520 kb
Host smart-41e986df-397c-451a-8587-d1c856ac0e57
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543722730 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.3543722730
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.3707471408
Short name T157
Test name
Test status
Simulation time 76216540 ps
CPU time 1.45 seconds
Started Mar 03 02:45:12 PM PST 24
Finished Mar 03 02:45:13 PM PST 24
Peak memory 215244 kb
Host smart-dac43795-1210-4048-8e20-f814e5007edd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707471408 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.3707471408
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.3950070498
Short name T386
Test name
Test status
Simulation time 23904305 ps
CPU time 1.12 seconds
Started Mar 03 02:45:16 PM PST 24
Finished Mar 03 02:45:17 PM PST 24
Peak memory 221876 kb
Host smart-2fa20893-ff55-4148-aa01-19909d5fcda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950070498 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.3950070498
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.1297557843
Short name T397
Test name
Test status
Simulation time 27143029 ps
CPU time 1.14 seconds
Started Mar 03 02:45:13 PM PST 24
Finished Mar 03 02:45:14 PM PST 24
Peak memory 215192 kb
Host smart-09e30996-e018-4976-900b-96a41b2dfacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297557843 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.1297557843
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_smoke.446271634
Short name T679
Test name
Test status
Simulation time 46553603 ps
CPU time 0.96 seconds
Started Mar 03 02:45:16 PM PST 24
Finished Mar 03 02:45:18 PM PST 24
Peak memory 214072 kb
Host smart-a89083e4-b9a8-4fe4-8663-512d0c83e36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446271634 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.446271634
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.68245769
Short name T651
Test name
Test status
Simulation time 854901873 ps
CPU time 4.29 seconds
Started Mar 03 02:45:14 PM PST 24
Finished Mar 03 02:45:18 PM PST 24
Peak memory 215228 kb
Host smart-8307986a-b28c-4ff3-90b9-da4bbdbff843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68245769 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.68245769
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2598219461
Short name T192
Test name
Test status
Simulation time 212172718288 ps
CPU time 926.58 seconds
Started Mar 03 02:45:13 PM PST 24
Finished Mar 03 03:00:40 PM PST 24
Peak memory 218740 kb
Host smart-65e0a740-0c5d-42b3-89d3-a6f9f607e439
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598219461 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2598219461
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.3133873480
Short name T47
Test name
Test status
Simulation time 38666991 ps
CPU time 1.74 seconds
Started Mar 03 02:46:53 PM PST 24
Finished Mar 03 02:46:55 PM PST 24
Peak memory 216548 kb
Host smart-93bb5cea-b796-436d-9c55-c7ceb998700b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133873480 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.3133873480
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2484904460
Short name T289
Test name
Test status
Simulation time 48942452 ps
CPU time 1.22 seconds
Started Mar 03 02:46:52 PM PST 24
Finished Mar 03 02:46:53 PM PST 24
Peak memory 216740 kb
Host smart-74a7e669-5ba9-4458-be41-83d4a6e5dc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484904460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2484904460
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.195327073
Short name T36
Test name
Test status
Simulation time 80278036 ps
CPU time 1.42 seconds
Started Mar 03 02:46:52 PM PST 24
Finished Mar 03 02:46:54 PM PST 24
Peak memory 216728 kb
Host smart-54bfb385-6fe4-40ed-bd63-c0009fd18b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195327073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.195327073
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.1434948061
Short name T586
Test name
Test status
Simulation time 44013660 ps
CPU time 1.77 seconds
Started Mar 03 02:46:52 PM PST 24
Finished Mar 03 02:46:53 PM PST 24
Peak memory 215388 kb
Host smart-7a0580ab-90a5-477d-bb4e-ada695096288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434948061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.1434948061
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2708179149
Short name T443
Test name
Test status
Simulation time 313183939 ps
CPU time 1.1 seconds
Started Mar 03 02:46:52 PM PST 24
Finished Mar 03 02:46:53 PM PST 24
Peak memory 215488 kb
Host smart-d01f01f2-4a42-4798-bffd-64922fcbc30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708179149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2708179149
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.1668083486
Short name T708
Test name
Test status
Simulation time 77019889 ps
CPU time 1.24 seconds
Started Mar 03 02:46:52 PM PST 24
Finished Mar 03 02:46:54 PM PST 24
Peak memory 216920 kb
Host smart-41eb90d3-aab4-47e8-867f-960486927d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668083486 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.1668083486
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.474175062
Short name T815
Test name
Test status
Simulation time 29712372 ps
CPU time 1.46 seconds
Started Mar 03 02:46:55 PM PST 24
Finished Mar 03 02:46:57 PM PST 24
Peak memory 216668 kb
Host smart-3b64d44c-c664-42c5-8f1e-1ee4475f2e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474175062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.474175062
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3395617762
Short name T253
Test name
Test status
Simulation time 32198346 ps
CPU time 1.29 seconds
Started Mar 03 02:45:22 PM PST 24
Finished Mar 03 02:45:24 PM PST 24
Peak memory 214560 kb
Host smart-7d613bc1-1566-4c89-8efc-3df0f0804a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395617762 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3395617762
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.472173900
Short name T757
Test name
Test status
Simulation time 216821141 ps
CPU time 0.91 seconds
Started Mar 03 02:45:23 PM PST 24
Finished Mar 03 02:45:24 PM PST 24
Peak memory 204976 kb
Host smart-236b7db3-9fa2-4fc0-99d8-0d07c82925f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472173900 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.472173900
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.200023378
Short name T773
Test name
Test status
Simulation time 70150489 ps
CPU time 0.91 seconds
Started Mar 03 02:45:22 PM PST 24
Finished Mar 03 02:45:24 PM PST 24
Peak memory 214580 kb
Host smart-a0e97508-44a5-4b89-aab3-4862f707f84a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200023378 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.200023378
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2654868720
Short name T165
Test name
Test status
Simulation time 51265361 ps
CPU time 1.29 seconds
Started Mar 03 02:45:22 PM PST 24
Finished Mar 03 02:45:24 PM PST 24
Peak memory 215308 kb
Host smart-4eb342fe-dc4f-40c8-b884-17b3fc799884
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654868720 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2654868720
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.4192752557
Short name T466
Test name
Test status
Simulation time 22289274 ps
CPU time 1.01 seconds
Started Mar 03 02:45:25 PM PST 24
Finished Mar 03 02:45:27 PM PST 24
Peak memory 222052 kb
Host smart-33c45014-08c4-47b9-a587-18aca786f72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192752557 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.4192752557
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3849232182
Short name T368
Test name
Test status
Simulation time 106137487 ps
CPU time 1.42 seconds
Started Mar 03 02:45:21 PM PST 24
Finished Mar 03 02:45:23 PM PST 24
Peak memory 218076 kb
Host smart-196d893c-c80d-439f-a7a1-c78d4c49e5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849232182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3849232182
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2752715918
Short name T554
Test name
Test status
Simulation time 23426233 ps
CPU time 1.26 seconds
Started Mar 03 02:45:21 PM PST 24
Finished Mar 03 02:45:23 PM PST 24
Peak memory 231344 kb
Host smart-e8c297f3-71a9-487d-82e5-f47c4a2ad3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752715918 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2752715918
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3446851694
Short name T195
Test name
Test status
Simulation time 16174075 ps
CPU time 0.97 seconds
Started Mar 03 02:45:19 PM PST 24
Finished Mar 03 02:45:20 PM PST 24
Peak memory 205852 kb
Host smart-725e73f2-908a-4b64-b584-c0ecf8c6287d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446851694 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3446851694
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.633655552
Short name T832
Test name
Test status
Simulation time 43895912 ps
CPU time 1.39 seconds
Started Mar 03 02:45:19 PM PST 24
Finished Mar 03 02:45:20 PM PST 24
Peak memory 215440 kb
Host smart-9b76b300-548a-412e-829a-693ec8c76a64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633655552 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.633655552
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.470363346
Short name T265
Test name
Test status
Simulation time 890986543814 ps
CPU time 2391.56 seconds
Started Mar 03 02:45:20 PM PST 24
Finished Mar 03 03:25:12 PM PST 24
Peak memory 229132 kb
Host smart-72a5ed26-0225-4c17-beec-ea9590f15d53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470363346 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.470363346
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1170258676
Short name T501
Test name
Test status
Simulation time 38746457 ps
CPU time 1.47 seconds
Started Mar 03 02:46:53 PM PST 24
Finished Mar 03 02:46:54 PM PST 24
Peak memory 216808 kb
Host smart-6c53b8c0-aab2-4c34-907d-80728d357077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170258676 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1170258676
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.394028766
Short name T308
Test name
Test status
Simulation time 81979789 ps
CPU time 1.34 seconds
Started Mar 03 02:46:51 PM PST 24
Finished Mar 03 02:46:52 PM PST 24
Peak memory 216712 kb
Host smart-70d3c7e6-3f40-4973-9104-1efe63ee1bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394028766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.394028766
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2066651784
Short name T725
Test name
Test status
Simulation time 100518509 ps
CPU time 1.25 seconds
Started Mar 03 02:46:56 PM PST 24
Finished Mar 03 02:46:58 PM PST 24
Peak memory 215392 kb
Host smart-6cf96ac8-65b7-40b5-aaa3-df68a1f0c8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066651784 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2066651784
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.2854217580
Short name T329
Test name
Test status
Simulation time 87837307 ps
CPU time 1.11 seconds
Started Mar 03 02:46:53 PM PST 24
Finished Mar 03 02:46:54 PM PST 24
Peak memory 215360 kb
Host smart-e5ed70ad-eb69-4ce2-a934-71f2494ef16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854217580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.2854217580
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.636673766
Short name T622
Test name
Test status
Simulation time 60988190 ps
CPU time 1.46 seconds
Started Mar 03 02:46:55 PM PST 24
Finished Mar 03 02:46:57 PM PST 24
Peak memory 216524 kb
Host smart-781c0cc9-bc64-4f7a-a5a3-c578da75608a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636673766 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.636673766
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3012248426
Short name T445
Test name
Test status
Simulation time 34264106 ps
CPU time 1.39 seconds
Started Mar 03 02:46:57 PM PST 24
Finished Mar 03 02:46:59 PM PST 24
Peak memory 216692 kb
Host smart-5dbd6e1b-8bab-42f6-b8f0-dc746e6f498b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012248426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3012248426
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2574940722
Short name T722
Test name
Test status
Simulation time 33592492 ps
CPU time 1 seconds
Started Mar 03 02:46:53 PM PST 24
Finished Mar 03 02:46:54 PM PST 24
Peak memory 215380 kb
Host smart-7f06173e-9a92-4d4b-8e4f-a587ce733ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574940722 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2574940722
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.656355247
Short name T287
Test name
Test status
Simulation time 116068986 ps
CPU time 2.9 seconds
Started Mar 03 02:46:53 PM PST 24
Finished Mar 03 02:46:56 PM PST 24
Peak memory 218176 kb
Host smart-fb2b6c05-38b9-4b94-be19-c964d79762a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656355247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.656355247
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2140460167
Short name T39
Test name
Test status
Simulation time 104339062 ps
CPU time 1.54 seconds
Started Mar 03 02:46:54 PM PST 24
Finished Mar 03 02:46:56 PM PST 24
Peak memory 216800 kb
Host smart-b068004f-2f29-41fb-b4a8-40a5d13cf921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140460167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2140460167
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.3503327914
Short name T632
Test name
Test status
Simulation time 58138479 ps
CPU time 1.22 seconds
Started Mar 03 02:46:52 PM PST 24
Finished Mar 03 02:46:53 PM PST 24
Peak memory 216584 kb
Host smart-10d23786-cc58-4971-93d0-853226b97eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503327914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.3503327914
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.308923827
Short name T252
Test name
Test status
Simulation time 145930775 ps
CPU time 1.24 seconds
Started Mar 03 02:45:20 PM PST 24
Finished Mar 03 02:45:21 PM PST 24
Peak memory 214576 kb
Host smart-5b7897f6-9bd5-47f4-96ac-3c753799017f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308923827 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.308923827
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2247766823
Short name T152
Test name
Test status
Simulation time 18633880 ps
CPU time 0.95 seconds
Started Mar 03 02:45:26 PM PST 24
Finished Mar 03 02:45:27 PM PST 24
Peak memory 205648 kb
Host smart-a7b7a5d8-d21b-4f04-9689-0a56f4346c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247766823 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2247766823
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.4154352241
Short name T173
Test name
Test status
Simulation time 28509624 ps
CPU time 0.88 seconds
Started Mar 03 02:45:23 PM PST 24
Finished Mar 03 02:45:24 PM PST 24
Peak memory 214336 kb
Host smart-54e58cd1-6ced-48fd-80a2-c32d562ddd7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154352241 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.4154352241
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.766625309
Short name T320
Test name
Test status
Simulation time 55479399 ps
CPU time 1.03 seconds
Started Mar 03 02:45:19 PM PST 24
Finished Mar 03 02:45:20 PM PST 24
Peak memory 215140 kb
Host smart-2b3c36c5-70fd-40c4-a417-00ffed1cfc63
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766625309 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_di
sable_auto_req_mode.766625309
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3395966978
Short name T119
Test name
Test status
Simulation time 55640316 ps
CPU time 0.89 seconds
Started Mar 03 02:45:22 PM PST 24
Finished Mar 03 02:45:24 PM PST 24
Peak memory 216616 kb
Host smart-5ab3fbe7-e341-4476-a29f-172ecab97078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395966978 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3395966978
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1820507708
Short name T579
Test name
Test status
Simulation time 122881548 ps
CPU time 1.59 seconds
Started Mar 03 02:45:22 PM PST 24
Finished Mar 03 02:45:25 PM PST 24
Peak memory 216792 kb
Host smart-40271bb2-40c8-4963-b3f7-fba64ebb57a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820507708 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1820507708
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.994782520
Short name T480
Test name
Test status
Simulation time 28446509 ps
CPU time 0.9 seconds
Started Mar 03 02:45:21 PM PST 24
Finished Mar 03 02:45:23 PM PST 24
Peak memory 214120 kb
Host smart-6c6e5117-c9f5-4dbb-b4ed-50d8878f78f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994782520 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.994782520
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.2365672612
Short name T65
Test name
Test status
Simulation time 24315177 ps
CPU time 0.91 seconds
Started Mar 03 02:45:21 PM PST 24
Finished Mar 03 02:45:23 PM PST 24
Peak memory 214196 kb
Host smart-ee7d6ecb-63d9-4c3c-a7e2-a4ecbd58d10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365672612 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2365672612
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3200205989
Short name T196
Test name
Test status
Simulation time 340433556 ps
CPU time 6.42 seconds
Started Mar 03 02:45:25 PM PST 24
Finished Mar 03 02:45:31 PM PST 24
Peak memory 215232 kb
Host smart-cd6950be-f31f-411d-a9d5-1e696ebef4ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200205989 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3200205989
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2098819071
Short name T263
Test name
Test status
Simulation time 47959911384 ps
CPU time 1239.08 seconds
Started Mar 03 02:45:25 PM PST 24
Finished Mar 03 03:06:04 PM PST 24
Peak memory 220860 kb
Host smart-a38b41a8-1dce-4ecd-b7d1-f90549232ed8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098819071 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2098819071
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.410986199
Short name T483
Test name
Test status
Simulation time 44521618 ps
CPU time 1.71 seconds
Started Mar 03 02:46:52 PM PST 24
Finished Mar 03 02:46:54 PM PST 24
Peak memory 217208 kb
Host smart-2edc52c2-536f-495a-8836-335d9279b531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410986199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.410986199
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.912038922
Short name T683
Test name
Test status
Simulation time 62430499 ps
CPU time 1.35 seconds
Started Mar 03 02:46:55 PM PST 24
Finished Mar 03 02:46:57 PM PST 24
Peak memory 215372 kb
Host smart-138d2130-19cf-4b7c-a579-d5ef187849f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912038922 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.912038922
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3793745559
Short name T798
Test name
Test status
Simulation time 34214684 ps
CPU time 1.3 seconds
Started Mar 03 02:46:55 PM PST 24
Finished Mar 03 02:46:56 PM PST 24
Peak memory 215324 kb
Host smart-f522d29d-ac3c-413d-b34f-4a8f7f350c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793745559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3793745559
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.1155364956
Short name T550
Test name
Test status
Simulation time 58588271 ps
CPU time 1.41 seconds
Started Mar 03 02:46:57 PM PST 24
Finished Mar 03 02:46:59 PM PST 24
Peak memory 215380 kb
Host smart-78f94a3a-faeb-49d9-891c-382bec4e58b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155364956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.1155364956
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2591330667
Short name T822
Test name
Test status
Simulation time 2227372696 ps
CPU time 74.42 seconds
Started Mar 03 02:46:53 PM PST 24
Finished Mar 03 02:48:08 PM PST 24
Peak memory 216688 kb
Host smart-ee998255-4e0d-4ae7-8fb3-514d9119f37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591330667 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2591330667
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2215406212
Short name T11
Test name
Test status
Simulation time 32471372 ps
CPU time 1.51 seconds
Started Mar 03 02:46:55 PM PST 24
Finished Mar 03 02:46:57 PM PST 24
Peak memory 216672 kb
Host smart-27f945fa-59c0-4c5d-96fe-95f38ea79684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215406212 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2215406212
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3938356798
Short name T324
Test name
Test status
Simulation time 60017440 ps
CPU time 0.98 seconds
Started Mar 03 02:46:53 PM PST 24
Finished Mar 03 02:46:54 PM PST 24
Peak memory 215200 kb
Host smart-22100382-4d3b-45b8-bfa5-f2322fe49db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938356798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3938356798
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.3851875302
Short name T352
Test name
Test status
Simulation time 59684011 ps
CPU time 1.65 seconds
Started Mar 03 02:46:57 PM PST 24
Finished Mar 03 02:46:59 PM PST 24
Peak memory 215620 kb
Host smart-e7239852-959b-429d-b7d2-be25488923b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851875302 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.3851875302
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.472832605
Short name T754
Test name
Test status
Simulation time 52981854 ps
CPU time 1.41 seconds
Started Mar 03 02:46:53 PM PST 24
Finished Mar 03 02:46:55 PM PST 24
Peak memory 216304 kb
Host smart-6b28b448-103f-47f8-b7e9-2a980cdf77c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472832605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.472832605
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3744801199
Short name T256
Test name
Test status
Simulation time 189864234 ps
CPU time 1.28 seconds
Started Mar 03 02:45:24 PM PST 24
Finished Mar 03 02:45:26 PM PST 24
Peak memory 214568 kb
Host smart-22cb33e2-fa5d-4f5a-b1fa-a6b3ca20fa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744801199 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3744801199
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.534259897
Short name T48
Test name
Test status
Simulation time 17645611 ps
CPU time 0.97 seconds
Started Mar 03 02:45:26 PM PST 24
Finished Mar 03 02:45:27 PM PST 24
Peak memory 205800 kb
Host smart-a06ab549-9a91-42f2-a556-875cf0b15022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534259897 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.534259897
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.1242115740
Short name T463
Test name
Test status
Simulation time 23893901 ps
CPU time 0.9 seconds
Started Mar 03 02:45:28 PM PST 24
Finished Mar 03 02:45:30 PM PST 24
Peak memory 214740 kb
Host smart-acdadd77-49fb-4f16-b489-f100da443b02
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242115740 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.1242115740
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2986689404
Short name T80
Test name
Test status
Simulation time 32991758 ps
CPU time 1.2 seconds
Started Mar 03 02:45:30 PM PST 24
Finished Mar 03 02:45:32 PM PST 24
Peak memory 215308 kb
Host smart-9b5bd1f4-5aa1-42c8-a83d-cc0545339a48
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986689404 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2986689404
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.890805962
Short name T615
Test name
Test status
Simulation time 27452686 ps
CPU time 0.9 seconds
Started Mar 03 02:45:20 PM PST 24
Finished Mar 03 02:45:22 PM PST 24
Peak memory 216496 kb
Host smart-1cd13d56-02f5-4a41-8c8a-e44f349115ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890805962 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.890805962
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.4152755613
Short name T237
Test name
Test status
Simulation time 176639873 ps
CPU time 1.51 seconds
Started Mar 03 02:45:23 PM PST 24
Finished Mar 03 02:45:25 PM PST 24
Peak memory 217128 kb
Host smart-8867dd86-ab52-4aea-8314-09f76a7e4a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152755613 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.4152755613
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1782688761
Short name T4
Test name
Test status
Simulation time 21781096 ps
CPU time 1.27 seconds
Started Mar 03 02:45:22 PM PST 24
Finished Mar 03 02:45:24 PM PST 24
Peak memory 222832 kb
Host smart-1be30eb9-df42-4783-a686-4c6b30b7aeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782688761 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1782688761
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.3041124541
Short name T427
Test name
Test status
Simulation time 28970666 ps
CPU time 0.97 seconds
Started Mar 03 02:45:22 PM PST 24
Finished Mar 03 02:45:24 PM PST 24
Peak memory 214128 kb
Host smart-b8e2e3a3-ba68-4eee-899b-3cc0c693f03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041124541 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.3041124541
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2787094099
Short name T535
Test name
Test status
Simulation time 603511681 ps
CPU time 4.01 seconds
Started Mar 03 02:45:22 PM PST 24
Finished Mar 03 02:45:27 PM PST 24
Peak memory 215472 kb
Host smart-d90d5278-6ba8-414d-b8ff-22bc5a87449d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787094099 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2787094099
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2656924042
Short name T398
Test name
Test status
Simulation time 63752416208 ps
CPU time 1475.64 seconds
Started Mar 03 02:45:21 PM PST 24
Finished Mar 03 03:09:58 PM PST 24
Peak memory 221160 kb
Host smart-c05298ac-babd-45f0-9935-a8b1c0b3fda3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656924042 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2656924042
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.998487129
Short name T590
Test name
Test status
Simulation time 42138405 ps
CPU time 1.47 seconds
Started Mar 03 02:46:51 PM PST 24
Finished Mar 03 02:46:53 PM PST 24
Peak memory 216340 kb
Host smart-74042ceb-0a97-4bdd-975c-d0a11da16df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998487129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.998487129
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.3857340864
Short name T440
Test name
Test status
Simulation time 90068641 ps
CPU time 1.21 seconds
Started Mar 03 02:46:55 PM PST 24
Finished Mar 03 02:46:57 PM PST 24
Peak memory 217408 kb
Host smart-d645f90f-31ae-4f9e-8b97-3e40a240cd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857340864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.3857340864
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.1045980856
Short name T780
Test name
Test status
Simulation time 115461426 ps
CPU time 1.64 seconds
Started Mar 03 02:46:54 PM PST 24
Finished Mar 03 02:46:56 PM PST 24
Peak memory 216696 kb
Host smart-9f1b6a18-4c87-4379-b3c4-cce0315951c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045980856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.1045980856
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.3427998605
Short name T582
Test name
Test status
Simulation time 58382305 ps
CPU time 1.24 seconds
Started Mar 03 02:46:56 PM PST 24
Finished Mar 03 02:46:57 PM PST 24
Peak memory 214196 kb
Host smart-a84f134b-8059-4f9c-99cf-6a0d830f7748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427998605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.3427998605
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.264948481
Short name T616
Test name
Test status
Simulation time 53540375 ps
CPU time 1.57 seconds
Started Mar 03 02:46:52 PM PST 24
Finished Mar 03 02:46:54 PM PST 24
Peak memory 216904 kb
Host smart-9e9df7d8-ec85-4d20-9edf-ceaa0fc8c289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264948481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.264948481
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2356032331
Short name T438
Test name
Test status
Simulation time 51504386 ps
CPU time 0.96 seconds
Started Mar 03 02:46:52 PM PST 24
Finished Mar 03 02:46:54 PM PST 24
Peak memory 215400 kb
Host smart-fb74d618-6bc7-4a23-981e-8fc7d29aff17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356032331 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2356032331
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.2840380269
Short name T783
Test name
Test status
Simulation time 102574912 ps
CPU time 1.03 seconds
Started Mar 03 02:46:54 PM PST 24
Finished Mar 03 02:46:55 PM PST 24
Peak memory 215312 kb
Host smart-158deb10-d90f-4ba2-83bc-dad02dda4b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840380269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.2840380269
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.3219613240
Short name T430
Test name
Test status
Simulation time 70237509 ps
CPU time 1.08 seconds
Started Mar 03 02:46:56 PM PST 24
Finished Mar 03 02:46:58 PM PST 24
Peak memory 215440 kb
Host smart-0e2ec569-6c46-4fbc-a803-2e3df974b77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219613240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.3219613240
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.3484627095
Short name T732
Test name
Test status
Simulation time 49101918 ps
CPU time 2.08 seconds
Started Mar 03 02:47:05 PM PST 24
Finished Mar 03 02:47:08 PM PST 24
Peak memory 215564 kb
Host smart-8c784b29-b91b-4987-a3c4-b250c8abe271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484627095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.3484627095
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.1787346610
Short name T669
Test name
Test status
Simulation time 86735305 ps
CPU time 1.59 seconds
Started Mar 03 02:46:53 PM PST 24
Finished Mar 03 02:46:55 PM PST 24
Peak memory 218276 kb
Host smart-cc8f208c-9d05-483e-a6e2-b4aea9ba26ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787346610 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.1787346610
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.4050103725
Short name T111
Test name
Test status
Simulation time 24782761 ps
CPU time 1.18 seconds
Started Mar 03 02:45:28 PM PST 24
Finished Mar 03 02:45:30 PM PST 24
Peak memory 214540 kb
Host smart-964e234c-4914-4bff-a0d7-75c83ff88e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050103725 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.4050103725
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2354681732
Short name T354
Test name
Test status
Simulation time 51755254 ps
CPU time 0.89 seconds
Started Mar 03 02:45:26 PM PST 24
Finished Mar 03 02:45:27 PM PST 24
Peak memory 205456 kb
Host smart-7811590a-4759-457e-be0d-8b6ee0048edb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354681732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2354681732
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2237994998
Short name T122
Test name
Test status
Simulation time 9933809 ps
CPU time 0.88 seconds
Started Mar 03 02:45:29 PM PST 24
Finished Mar 03 02:45:31 PM PST 24
Peak memory 214616 kb
Host smart-73b24c83-72ef-439e-9209-3aa504f409b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237994998 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2237994998
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2756492958
Short name T498
Test name
Test status
Simulation time 25192237 ps
CPU time 1.03 seconds
Started Mar 03 02:45:28 PM PST 24
Finished Mar 03 02:45:29 PM PST 24
Peak memory 215236 kb
Host smart-b497f1a5-0fd1-45ae-8498-d4f2146f0a42
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756492958 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2756492958
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_genbits.2315416417
Short name T548
Test name
Test status
Simulation time 60517250 ps
CPU time 1.38 seconds
Started Mar 03 02:45:30 PM PST 24
Finished Mar 03 02:45:32 PM PST 24
Peak memory 217720 kb
Host smart-da7e1caa-80c5-4f38-bb10-a521c29d9bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315416417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.2315416417
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.707966973
Short name T727
Test name
Test status
Simulation time 27233998 ps
CPU time 1 seconds
Started Mar 03 02:45:28 PM PST 24
Finished Mar 03 02:45:30 PM PST 24
Peak memory 214184 kb
Host smart-3bb456f4-8ff2-4f57-9869-3cecd9ed6a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707966973 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.707966973
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.792341869
Short name T561
Test name
Test status
Simulation time 16124480 ps
CPU time 0.99 seconds
Started Mar 03 02:45:26 PM PST 24
Finished Mar 03 02:45:28 PM PST 24
Peak memory 214120 kb
Host smart-e0ccfef1-57c9-477b-86bd-55faf79aa2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792341869 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.792341869
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.3642344441
Short name T562
Test name
Test status
Simulation time 355487099 ps
CPU time 6.94 seconds
Started Mar 03 02:45:30 PM PST 24
Finished Mar 03 02:45:37 PM PST 24
Peak memory 214172 kb
Host smart-0ac632ef-9605-4a2a-a41b-b6a250b07a0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642344441 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.3642344441
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.578000761
Short name T22
Test name
Test status
Simulation time 71334409001 ps
CPU time 571.33 seconds
Started Mar 03 02:45:30 PM PST 24
Finished Mar 03 02:55:02 PM PST 24
Peak memory 216968 kb
Host smart-313bc7ed-8220-4f90-b2f7-ea795b937529
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578000761 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.578000761
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.3040467525
Short name T476
Test name
Test status
Simulation time 34009310 ps
CPU time 1.38 seconds
Started Mar 03 02:46:53 PM PST 24
Finished Mar 03 02:46:55 PM PST 24
Peak memory 216500 kb
Host smart-4ef2aaf4-eb09-40ae-b3cd-a55214f727eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040467525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.3040467525
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.2580488365
Short name T599
Test name
Test status
Simulation time 68373435 ps
CPU time 1.36 seconds
Started Mar 03 02:46:55 PM PST 24
Finished Mar 03 02:46:57 PM PST 24
Peak memory 216480 kb
Host smart-cee00845-ca82-4927-9212-b5b0957a8766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580488365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.2580488365
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3742724778
Short name T648
Test name
Test status
Simulation time 95705846 ps
CPU time 1.61 seconds
Started Mar 03 02:46:54 PM PST 24
Finished Mar 03 02:46:56 PM PST 24
Peak memory 217048 kb
Host smart-529e0aed-b2f3-4eee-8e71-2c33919f0536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742724778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3742724778
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.2816434453
Short name T322
Test name
Test status
Simulation time 78488380 ps
CPU time 1.7 seconds
Started Mar 03 02:46:54 PM PST 24
Finished Mar 03 02:46:56 PM PST 24
Peak memory 216364 kb
Host smart-2cc50499-0839-4b93-b4f9-687ac2fc782e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816434453 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.2816434453
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.4095566290
Short name T404
Test name
Test status
Simulation time 841178607 ps
CPU time 6.79 seconds
Started Mar 03 02:46:57 PM PST 24
Finished Mar 03 02:47:04 PM PST 24
Peak memory 218488 kb
Host smart-459bf88f-29e2-4fea-8850-8fc9f9faf411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095566290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.4095566290
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.4035923998
Short name T769
Test name
Test status
Simulation time 107066649 ps
CPU time 2.57 seconds
Started Mar 03 02:46:52 PM PST 24
Finished Mar 03 02:46:54 PM PST 24
Peak memory 217496 kb
Host smart-b5da8f04-287c-4964-b166-93c817307694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035923998 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.4035923998
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.3036131679
Short name T477
Test name
Test status
Simulation time 43389840 ps
CPU time 1.81 seconds
Started Mar 03 02:46:53 PM PST 24
Finished Mar 03 02:46:55 PM PST 24
Peak memory 216620 kb
Host smart-5690c801-ebdb-4747-855c-c3940b380ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036131679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.3036131679
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1245854419
Short name T317
Test name
Test status
Simulation time 220135990 ps
CPU time 1.08 seconds
Started Mar 03 02:47:04 PM PST 24
Finished Mar 03 02:47:06 PM PST 24
Peak memory 215312 kb
Host smart-cb953e06-5990-4b6e-8736-425cee077ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245854419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1245854419
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.881920705
Short name T577
Test name
Test status
Simulation time 26622318 ps
CPU time 1.12 seconds
Started Mar 03 02:46:59 PM PST 24
Finished Mar 03 02:47:00 PM PST 24
Peak memory 215356 kb
Host smart-506808b5-14e0-4f2c-8ae6-d09fd46c4c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881920705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.881920705
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert_test.3827902732
Short name T332
Test name
Test status
Simulation time 70068227 ps
CPU time 0.89 seconds
Started Mar 03 02:45:31 PM PST 24
Finished Mar 03 02:45:32 PM PST 24
Peak memory 205460 kb
Host smart-4936610f-ef7e-488f-88c9-02a6bdb3006a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827902732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3827902732
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2084817289
Short name T59
Test name
Test status
Simulation time 42636190 ps
CPU time 1.04 seconds
Started Mar 03 02:45:29 PM PST 24
Finished Mar 03 02:45:32 PM PST 24
Peak memory 215196 kb
Host smart-a720313f-096d-442d-8b63-1de16044c9d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084817289 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2084817289
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.219255321
Short name T14
Test name
Test status
Simulation time 18662877 ps
CPU time 1.25 seconds
Started Mar 03 02:45:29 PM PST 24
Finished Mar 03 02:45:32 PM PST 24
Peak memory 221856 kb
Host smart-63cb7e76-bca2-411b-b599-93a821439a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219255321 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.219255321
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.2442226140
Short name T269
Test name
Test status
Simulation time 54727721 ps
CPU time 1.3 seconds
Started Mar 03 02:45:26 PM PST 24
Finished Mar 03 02:45:28 PM PST 24
Peak memory 216704 kb
Host smart-043d1bdf-4995-4a4e-9afa-d679ebc95f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442226140 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.2442226140
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1158461692
Short name T591
Test name
Test status
Simulation time 74011344 ps
CPU time 0.89 seconds
Started Mar 03 02:45:27 PM PST 24
Finished Mar 03 02:45:28 PM PST 24
Peak memory 214084 kb
Host smart-a9478fcb-cec9-4422-bfa4-e11dee632122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158461692 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1158461692
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.29730553
Short name T571
Test name
Test status
Simulation time 19259052 ps
CPU time 0.94 seconds
Started Mar 03 02:45:27 PM PST 24
Finished Mar 03 02:45:28 PM PST 24
Peak memory 214084 kb
Host smart-f6396cfe-c572-41cd-89c3-2ca3cb602ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29730553 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.29730553
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.2593714954
Short name T767
Test name
Test status
Simulation time 663935193 ps
CPU time 3.2 seconds
Started Mar 03 02:45:28 PM PST 24
Finished Mar 03 02:45:31 PM PST 24
Peak memory 215168 kb
Host smart-c8884b01-1689-4bc3-83d6-c2059b594787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593714954 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.2593714954
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2839803668
Short name T392
Test name
Test status
Simulation time 16215471947 ps
CPU time 201.95 seconds
Started Mar 03 02:45:27 PM PST 24
Finished Mar 03 02:48:49 PM PST 24
Peak memory 222432 kb
Host smart-f27e8e19-035b-4246-92b3-09d5bc0fa1ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839803668 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2839803668
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.611916997
Short name T689
Test name
Test status
Simulation time 165846832 ps
CPU time 3.46 seconds
Started Mar 03 02:46:59 PM PST 24
Finished Mar 03 02:47:03 PM PST 24
Peak memory 216664 kb
Host smart-aa3810bf-8f24-4799-a957-99451ebb21fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611916997 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.611916997
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.3962385175
Short name T618
Test name
Test status
Simulation time 89174980 ps
CPU time 1.11 seconds
Started Mar 03 02:47:04 PM PST 24
Finished Mar 03 02:47:06 PM PST 24
Peak memory 215416 kb
Host smart-8060c9d4-7f75-4ab2-843f-d8c60f699027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962385175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.3962385175
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.195314747
Short name T552
Test name
Test status
Simulation time 67811081 ps
CPU time 1.05 seconds
Started Mar 03 02:47:01 PM PST 24
Finished Mar 03 02:47:03 PM PST 24
Peak memory 215360 kb
Host smart-24a167d9-6c88-41bd-a322-bf6ebbd278de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195314747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.195314747
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.899130226
Short name T609
Test name
Test status
Simulation time 76338346 ps
CPU time 2.82 seconds
Started Mar 03 02:47:09 PM PST 24
Finished Mar 03 02:47:12 PM PST 24
Peak memory 218324 kb
Host smart-a3c3895c-9ed9-401c-bce7-ed6133165d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899130226 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.899130226
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.1247718942
Short name T664
Test name
Test status
Simulation time 317295373 ps
CPU time 4.5 seconds
Started Mar 03 02:47:02 PM PST 24
Finished Mar 03 02:47:07 PM PST 24
Peak memory 216676 kb
Host smart-e22b482d-ea0e-4791-bc2d-d5cee167e304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247718942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.1247718942
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.739762907
Short name T473
Test name
Test status
Simulation time 32637392 ps
CPU time 1.4 seconds
Started Mar 03 02:47:01 PM PST 24
Finished Mar 03 02:47:03 PM PST 24
Peak memory 216696 kb
Host smart-fe7a43fc-2436-4f47-a015-adfc21029bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739762907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.739762907
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.2140842309
Short name T43
Test name
Test status
Simulation time 96800812 ps
CPU time 1.57 seconds
Started Mar 03 02:46:59 PM PST 24
Finished Mar 03 02:47:01 PM PST 24
Peak memory 216788 kb
Host smart-2933ba10-9cbc-4c18-aaf8-ec6b7361c399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140842309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.2140842309
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1111393019
Short name T623
Test name
Test status
Simulation time 49770943 ps
CPU time 1.14 seconds
Started Mar 03 02:47:01 PM PST 24
Finished Mar 03 02:47:03 PM PST 24
Peak memory 217600 kb
Host smart-1af470a1-f00a-4d2b-a44e-7113fd6e0938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111393019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1111393019
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.1857652501
Short name T812
Test name
Test status
Simulation time 42776914 ps
CPU time 1.64 seconds
Started Mar 03 02:47:09 PM PST 24
Finished Mar 03 02:47:11 PM PST 24
Peak memory 216696 kb
Host smart-6e2e8f8f-041f-4b20-a831-e7d6bdf5c464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857652501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.1857652501
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.729438888
Short name T713
Test name
Test status
Simulation time 59608328 ps
CPU time 1.08 seconds
Started Mar 03 02:47:00 PM PST 24
Finished Mar 03 02:47:01 PM PST 24
Peak memory 215240 kb
Host smart-42604bb2-0bb1-4140-8b10-4c0c26bcb960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729438888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.729438888
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.2836455843
Short name T148
Test name
Test status
Simulation time 77957832 ps
CPU time 1.14 seconds
Started Mar 03 02:45:27 PM PST 24
Finished Mar 03 02:45:28 PM PST 24
Peak memory 214528 kb
Host smart-bacccd55-df99-47dc-a452-dc3cec8be627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836455843 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.2836455843
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3747929763
Short name T659
Test name
Test status
Simulation time 12900948 ps
CPU time 0.84 seconds
Started Mar 03 02:45:28 PM PST 24
Finished Mar 03 02:45:29 PM PST 24
Peak memory 204628 kb
Host smart-f54efc17-9607-47bc-b57f-7d3fa6590d99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747929763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3747929763
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1358268068
Short name T357
Test name
Test status
Simulation time 35197826 ps
CPU time 0.83 seconds
Started Mar 03 02:45:26 PM PST 24
Finished Mar 03 02:45:27 PM PST 24
Peak memory 214268 kb
Host smart-ce256065-6751-4264-9b57-ad471aca9a20
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358268068 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1358268068
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.2504189909
Short name T667
Test name
Test status
Simulation time 134833654 ps
CPU time 0.99 seconds
Started Mar 03 02:45:28 PM PST 24
Finished Mar 03 02:45:29 PM PST 24
Peak memory 215468 kb
Host smart-825c92bf-d366-4244-bb9a-329e91ec15ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504189909 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.2504189909
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2222939232
Short name T826
Test name
Test status
Simulation time 20582540 ps
CPU time 1.12 seconds
Started Mar 03 02:45:29 PM PST 24
Finished Mar 03 02:45:31 PM PST 24
Peak memory 215732 kb
Host smart-82d45533-cb4c-4213-8890-21de81abdcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222939232 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2222939232
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.3988625423
Short name T502
Test name
Test status
Simulation time 36328810 ps
CPU time 1.06 seconds
Started Mar 03 02:45:28 PM PST 24
Finished Mar 03 02:45:29 PM PST 24
Peak memory 214144 kb
Host smart-30283b44-3cbb-48dd-9989-5fe1d894446d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988625423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.3988625423
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_smoke.977104124
Short name T829
Test name
Test status
Simulation time 65676401 ps
CPU time 0.96 seconds
Started Mar 03 02:45:30 PM PST 24
Finished Mar 03 02:45:32 PM PST 24
Peak memory 214132 kb
Host smart-249514fb-f6a2-4287-84ba-d36e37629b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977104124 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.977104124
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.623981873
Short name T336
Test name
Test status
Simulation time 298177841 ps
CPU time 6.31 seconds
Started Mar 03 02:45:28 PM PST 24
Finished Mar 03 02:45:35 PM PST 24
Peak memory 215192 kb
Host smart-07ac408c-898e-4c2b-a571-98cf7af51cd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623981873 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.623981873
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.1009870413
Short name T507
Test name
Test status
Simulation time 97730165887 ps
CPU time 692.15 seconds
Started Mar 03 02:45:30 PM PST 24
Finished Mar 03 02:57:03 PM PST 24
Peak memory 218756 kb
Host smart-71f48fd2-3bcb-4998-abac-99a28882ee82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009870413 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.1009870413
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.1529233035
Short name T810
Test name
Test status
Simulation time 81603751 ps
CPU time 1.18 seconds
Started Mar 03 02:47:03 PM PST 24
Finished Mar 03 02:47:04 PM PST 24
Peak memory 215584 kb
Host smart-23364e1b-1d7e-4d87-8d7e-d9abfb727c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529233035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.1529233035
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.2831765172
Short name T739
Test name
Test status
Simulation time 59091946 ps
CPU time 1.99 seconds
Started Mar 03 02:47:00 PM PST 24
Finished Mar 03 02:47:02 PM PST 24
Peak memory 216736 kb
Host smart-cc649b27-3348-406d-859c-b1b5a1374a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831765172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.2831765172
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.1771584964
Short name T592
Test name
Test status
Simulation time 47338000 ps
CPU time 1.36 seconds
Started Mar 03 02:47:00 PM PST 24
Finished Mar 03 02:47:02 PM PST 24
Peak memory 216820 kb
Host smart-2e33f192-0a72-45c7-8d99-c52120a85044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771584964 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.1771584964
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.4017712686
Short name T347
Test name
Test status
Simulation time 48504543 ps
CPU time 1.83 seconds
Started Mar 03 02:47:01 PM PST 24
Finished Mar 03 02:47:03 PM PST 24
Peak memory 216384 kb
Host smart-3a911fa4-8271-4e1f-8c79-f0a38fe0a90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017712686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.4017712686
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2985488739
Short name T809
Test name
Test status
Simulation time 63946536 ps
CPU time 1.26 seconds
Started Mar 03 02:47:01 PM PST 24
Finished Mar 03 02:47:02 PM PST 24
Peak memory 215456 kb
Host smart-114c6198-04ed-41ef-9885-7f36a9ac1a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985488739 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2985488739
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.3766829982
Short name T378
Test name
Test status
Simulation time 185266589 ps
CPU time 1.32 seconds
Started Mar 03 02:47:02 PM PST 24
Finished Mar 03 02:47:03 PM PST 24
Peak memory 218040 kb
Host smart-7356773d-4923-4de6-a144-e2392c60e0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766829982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.3766829982
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.4244601391
Short name T414
Test name
Test status
Simulation time 176114524 ps
CPU time 1.28 seconds
Started Mar 03 02:47:02 PM PST 24
Finished Mar 03 02:47:03 PM PST 24
Peak memory 216996 kb
Host smart-f10e2de2-b7cd-4f1f-8ff0-23d2c042c294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244601391 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.4244601391
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2666247247
Short name T748
Test name
Test status
Simulation time 68288251 ps
CPU time 1.74 seconds
Started Mar 03 02:47:01 PM PST 24
Finished Mar 03 02:47:03 PM PST 24
Peak memory 216492 kb
Host smart-674e5f94-3554-4da7-b8ef-4326f15718a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666247247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2666247247
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.3199852310
Short name T799
Test name
Test status
Simulation time 92745707 ps
CPU time 1.4 seconds
Started Mar 03 02:47:01 PM PST 24
Finished Mar 03 02:47:02 PM PST 24
Peak memory 215348 kb
Host smart-6a8e9fe8-aa1f-4c3a-b2d0-e7b5286f3fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199852310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.3199852310
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.3399770701
Short name T531
Test name
Test status
Simulation time 62947713 ps
CPU time 1.34 seconds
Started Mar 03 02:46:59 PM PST 24
Finished Mar 03 02:47:01 PM PST 24
Peak memory 216544 kb
Host smart-867bba99-2cb8-436b-b30d-eea32004d6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399770701 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.3399770701
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert_test.2595482675
Short name T304
Test name
Test status
Simulation time 13518205 ps
CPU time 0.86 seconds
Started Mar 03 02:45:36 PM PST 24
Finished Mar 03 02:45:38 PM PST 24
Peak memory 204892 kb
Host smart-4bcabf94-5475-441b-a0ba-3da56f993e73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595482675 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.2595482675
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.299323316
Short name T681
Test name
Test status
Simulation time 46263516 ps
CPU time 0.88 seconds
Started Mar 03 02:45:33 PM PST 24
Finished Mar 03 02:45:34 PM PST 24
Peak memory 214328 kb
Host smart-4fec7d61-1342-4082-8980-d25cde4cdd36
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299323316 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.299323316
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.1502193599
Short name T657
Test name
Test status
Simulation time 25051508 ps
CPU time 0.99 seconds
Started Mar 03 02:45:38 PM PST 24
Finished Mar 03 02:45:40 PM PST 24
Peak memory 222040 kb
Host smart-50c0cbf0-c0ca-4f2d-aff4-055d08e29862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502193599 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1502193599
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.111766027
Short name T660
Test name
Test status
Simulation time 79603943 ps
CPU time 1.21 seconds
Started Mar 03 02:45:25 PM PST 24
Finished Mar 03 02:45:27 PM PST 24
Peak memory 215448 kb
Host smart-3c229166-0e59-4b5c-af87-c0474e4e8745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111766027 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.111766027
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.3237948653
Short name T67
Test name
Test status
Simulation time 22848961 ps
CPU time 1.03 seconds
Started Mar 03 02:45:30 PM PST 24
Finished Mar 03 02:45:32 PM PST 24
Peak memory 214392 kb
Host smart-bc381d20-6a28-4747-afa4-1a936a1c7403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237948653 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.3237948653
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.381418436
Short name T574
Test name
Test status
Simulation time 27707198 ps
CPU time 0.95 seconds
Started Mar 03 02:45:30 PM PST 24
Finished Mar 03 02:45:32 PM PST 24
Peak memory 214168 kb
Host smart-62f96e0e-1bcd-4928-8908-26f6e98c97cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381418436 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.381418436
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1128188653
Short name T426
Test name
Test status
Simulation time 233730048 ps
CPU time 2.03 seconds
Started Mar 03 02:45:30 PM PST 24
Finished Mar 03 02:45:33 PM PST 24
Peak memory 215300 kb
Host smart-ea58340f-a8ce-49f5-9582-8a33840ab64a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128188653 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1128188653
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.759566582
Short name T813
Test name
Test status
Simulation time 74028758437 ps
CPU time 1689.11 seconds
Started Mar 03 02:45:34 PM PST 24
Finished Mar 03 03:13:43 PM PST 24
Peak memory 221472 kb
Host smart-164d529d-4a76-49aa-9e71-167ebe851f58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759566582 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.759566582
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2728568630
Short name T366
Test name
Test status
Simulation time 51472578 ps
CPU time 1.23 seconds
Started Mar 03 02:47:01 PM PST 24
Finished Mar 03 02:47:02 PM PST 24
Peak memory 216400 kb
Host smart-4232baca-3dd5-468e-a92b-2f6d805321d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728568630 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2728568630
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.3163233015
Short name T280
Test name
Test status
Simulation time 67246385 ps
CPU time 1.38 seconds
Started Mar 03 02:46:59 PM PST 24
Finished Mar 03 02:47:01 PM PST 24
Peak memory 216584 kb
Host smart-575e9237-90d9-458e-936b-a3759f666e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163233015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.3163233015
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.4225711864
Short name T342
Test name
Test status
Simulation time 32974995 ps
CPU time 1.38 seconds
Started Mar 03 02:46:59 PM PST 24
Finished Mar 03 02:47:01 PM PST 24
Peak memory 215540 kb
Host smart-72f956b0-f5b0-43e6-8d76-ae79e1734445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225711864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.4225711864
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.250286854
Short name T775
Test name
Test status
Simulation time 66654491 ps
CPU time 1.84 seconds
Started Mar 03 02:47:01 PM PST 24
Finished Mar 03 02:47:03 PM PST 24
Peak memory 216564 kb
Host smart-f85591f8-6b84-4bb1-873c-f37ad3eead2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250286854 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.250286854
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.437185496
Short name T516
Test name
Test status
Simulation time 43382509 ps
CPU time 1.67 seconds
Started Mar 03 02:47:02 PM PST 24
Finished Mar 03 02:47:03 PM PST 24
Peak memory 216476 kb
Host smart-e2fbfbf1-fca6-4ccd-8820-3b22c85b5982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437185496 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.437185496
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2733442770
Short name T240
Test name
Test status
Simulation time 42991825 ps
CPU time 1.4 seconds
Started Mar 03 02:47:02 PM PST 24
Finished Mar 03 02:47:04 PM PST 24
Peak memory 216644 kb
Host smart-5d770675-3252-4404-8f49-28de6a7b354f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733442770 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2733442770
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.3410025341
Short name T460
Test name
Test status
Simulation time 88614747 ps
CPU time 1.5 seconds
Started Mar 03 02:47:00 PM PST 24
Finished Mar 03 02:47:02 PM PST 24
Peak memory 217056 kb
Host smart-077d1114-4bff-4e8b-884d-820c06de6f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410025341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.3410025341
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2578784793
Short name T436
Test name
Test status
Simulation time 40825401 ps
CPU time 1.46 seconds
Started Mar 03 02:47:01 PM PST 24
Finished Mar 03 02:47:03 PM PST 24
Peak memory 215460 kb
Host smart-2d6bd2b4-c60e-449d-817b-6fa7659df3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578784793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2578784793
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.1639956907
Short name T223
Test name
Test status
Simulation time 189061255 ps
CPU time 2.83 seconds
Started Mar 03 02:47:01 PM PST 24
Finished Mar 03 02:47:04 PM PST 24
Peak memory 217612 kb
Host smart-f6259820-5635-433e-a013-c825f2ef2eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639956907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.1639956907
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.1906606524
Short name T285
Test name
Test status
Simulation time 40501235 ps
CPU time 1.43 seconds
Started Mar 03 02:46:59 PM PST 24
Finished Mar 03 02:47:00 PM PST 24
Peak memory 216792 kb
Host smart-4f36b945-4f57-4699-954f-c01aac3abd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906606524 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.1906606524
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.3472191197
Short name T235
Test name
Test status
Simulation time 28359732 ps
CPU time 1.24 seconds
Started Mar 03 02:45:35 PM PST 24
Finished Mar 03 02:45:37 PM PST 24
Peak memory 214568 kb
Host smart-1b8e3bbc-b1f3-4f56-876c-1721ed5da5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472191197 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.3472191197
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1474225200
Short name T387
Test name
Test status
Simulation time 52406531 ps
CPU time 0.89 seconds
Started Mar 03 02:45:33 PM PST 24
Finished Mar 03 02:45:34 PM PST 24
Peak memory 204968 kb
Host smart-ebd2504f-e008-44e4-9dc2-015862e44e80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474225200 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1474225200
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.3509422219
Short name T162
Test name
Test status
Simulation time 13548481 ps
CPU time 0.91 seconds
Started Mar 03 02:45:37 PM PST 24
Finished Mar 03 02:45:39 PM PST 24
Peak memory 214868 kb
Host smart-ea664aad-7e7d-4dc9-8997-b257cbb1a9ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509422219 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.3509422219
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.2734388498
Short name T610
Test name
Test status
Simulation time 39882104 ps
CPU time 0.95 seconds
Started Mar 03 02:45:36 PM PST 24
Finished Mar 03 02:45:38 PM PST 24
Peak memory 216684 kb
Host smart-1c4a874d-1b38-4d26-8f89-09f6be0480d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734388498 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.2734388498
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/28.edn_err.2174121035
Short name T77
Test name
Test status
Simulation time 35030270 ps
CPU time 1.06 seconds
Started Mar 03 02:45:34 PM PST 24
Finished Mar 03 02:45:35 PM PST 24
Peak memory 219056 kb
Host smart-caa71872-4191-468f-9498-1af0416010e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174121035 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2174121035
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.4151189857
Short name T274
Test name
Test status
Simulation time 33340256 ps
CPU time 1.16 seconds
Started Mar 03 02:45:35 PM PST 24
Finished Mar 03 02:45:36 PM PST 24
Peak memory 216496 kb
Host smart-bbe2ea0c-b555-4ebb-a1b9-ddfec3fe3dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151189857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.4151189857
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3247718206
Short name T66
Test name
Test status
Simulation time 22320943 ps
CPU time 1.11 seconds
Started Mar 03 02:45:34 PM PST 24
Finished Mar 03 02:45:36 PM PST 24
Peak memory 214504 kb
Host smart-46c4255b-2317-4eb2-a278-177c47aa56b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247718206 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3247718206
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1088386461
Short name T567
Test name
Test status
Simulation time 28019420 ps
CPU time 0.99 seconds
Started Mar 03 02:45:36 PM PST 24
Finished Mar 03 02:45:38 PM PST 24
Peak memory 214060 kb
Host smart-72c75611-8dff-423b-bd7b-c8ffaf4c6915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088386461 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1088386461
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.3376614856
Short name T474
Test name
Test status
Simulation time 407347008 ps
CPU time 4.47 seconds
Started Mar 03 02:45:33 PM PST 24
Finished Mar 03 02:45:38 PM PST 24
Peak memory 216528 kb
Host smart-1986e042-9bc3-47ad-ade7-c904f1d5577b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376614856 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.3376614856
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.561357364
Short name T514
Test name
Test status
Simulation time 558551586636 ps
CPU time 1773.62 seconds
Started Mar 03 02:45:33 PM PST 24
Finished Mar 03 03:15:07 PM PST 24
Peak memory 226336 kb
Host smart-95a8dd29-ba89-48b0-acae-b14dbe9e0c2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561357364 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.561357364
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.1233179668
Short name T271
Test name
Test status
Simulation time 222252235 ps
CPU time 3.26 seconds
Started Mar 03 02:46:59 PM PST 24
Finished Mar 03 02:47:02 PM PST 24
Peak memory 215736 kb
Host smart-4f464f43-07e9-4df4-b95e-190bfb226021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233179668 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.1233179668
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.4261387245
Short name T644
Test name
Test status
Simulation time 76382853 ps
CPU time 1.84 seconds
Started Mar 03 02:47:05 PM PST 24
Finished Mar 03 02:47:07 PM PST 24
Peak memory 216732 kb
Host smart-df036962-f693-4634-9401-a4e7476cf229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261387245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.4261387245
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.844912584
Short name T401
Test name
Test status
Simulation time 140925962 ps
CPU time 0.95 seconds
Started Mar 03 02:47:06 PM PST 24
Finished Mar 03 02:47:08 PM PST 24
Peak memory 215412 kb
Host smart-d60b7f09-1ba1-4ca8-aa04-703fa74ed004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844912584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.844912584
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.3835668943
Short name T611
Test name
Test status
Simulation time 184465432 ps
CPU time 1.02 seconds
Started Mar 03 02:47:03 PM PST 24
Finished Mar 03 02:47:04 PM PST 24
Peak memory 215312 kb
Host smart-112ff919-00bb-4fb7-ad71-0c854f4aa466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835668943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.3835668943
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.842345378
Short name T358
Test name
Test status
Simulation time 81648320 ps
CPU time 2.92 seconds
Started Mar 03 02:47:00 PM PST 24
Finished Mar 03 02:47:03 PM PST 24
Peak memory 218360 kb
Host smart-d4dcf130-d1a9-43e1-b40b-0e1946a1ad1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842345378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.842345378
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.1809449768
Short name T597
Test name
Test status
Simulation time 251826913 ps
CPU time 1.15 seconds
Started Mar 03 02:47:00 PM PST 24
Finished Mar 03 02:47:02 PM PST 24
Peak memory 215220 kb
Host smart-dfaae1e7-0021-4ecb-a965-1e33eaf89028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809449768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.1809449768
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.174423084
Short name T654
Test name
Test status
Simulation time 87552224 ps
CPU time 1.17 seconds
Started Mar 03 02:47:00 PM PST 24
Finished Mar 03 02:47:02 PM PST 24
Peak memory 216644 kb
Host smart-dab27d35-d5c4-495a-85a8-fb687d784ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174423084 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.174423084
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.1469129318
Short name T652
Test name
Test status
Simulation time 51521581 ps
CPU time 1.63 seconds
Started Mar 03 02:47:01 PM PST 24
Finished Mar 03 02:47:03 PM PST 24
Peak memory 215432 kb
Host smart-7be5c1e7-354c-46de-b39b-4337369e2a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469129318 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.1469129318
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.4273641733
Short name T390
Test name
Test status
Simulation time 142668543 ps
CPU time 2.42 seconds
Started Mar 03 02:47:02 PM PST 24
Finished Mar 03 02:47:05 PM PST 24
Peak memory 215732 kb
Host smart-2aeb004d-b52b-428f-85da-8de27edd59df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273641733 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.4273641733
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.2694088923
Short name T686
Test name
Test status
Simulation time 413205012 ps
CPU time 3.46 seconds
Started Mar 03 02:47:00 PM PST 24
Finished Mar 03 02:47:04 PM PST 24
Peak memory 216760 kb
Host smart-6e7a1226-a0af-4303-8b08-dd208a62f5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694088923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.2694088923
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.95446892
Short name T251
Test name
Test status
Simulation time 77271270 ps
CPU time 1.22 seconds
Started Mar 03 02:45:35 PM PST 24
Finished Mar 03 02:45:37 PM PST 24
Peak memory 214572 kb
Host smart-ecc024ae-71c1-4d01-a97b-c8470948842f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95446892 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.95446892
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.107774037
Short name T459
Test name
Test status
Simulation time 21434435 ps
CPU time 0.97 seconds
Started Mar 03 02:45:36 PM PST 24
Finished Mar 03 02:45:38 PM PST 24
Peak memory 205812 kb
Host smart-a9e1b7d9-4dfc-4456-bd5a-0a8e11e836d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107774037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.107774037
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2995291553
Short name T663
Test name
Test status
Simulation time 13263179 ps
CPU time 0.9 seconds
Started Mar 03 02:45:36 PM PST 24
Finished Mar 03 02:45:37 PM PST 24
Peak memory 214692 kb
Host smart-7a389c53-0f89-4d07-9d0f-0fc3297da681
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995291553 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2995291553
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.3999842497
Short name T79
Test name
Test status
Simulation time 48465367 ps
CPU time 1.11 seconds
Started Mar 03 02:45:38 PM PST 24
Finished Mar 03 02:45:39 PM PST 24
Peak memory 215344 kb
Host smart-7d26dc05-b7fe-4d34-ab0e-b54b8802f56f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999842497 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.3999842497
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.2562659612
Short name T749
Test name
Test status
Simulation time 46047429 ps
CPU time 0.95 seconds
Started Mar 03 02:45:33 PM PST 24
Finished Mar 03 02:45:34 PM PST 24
Peak memory 218084 kb
Host smart-6af6b2c3-4925-43ea-99a4-64abbd9b5e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562659612 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.2562659612
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.3070569507
Short name T419
Test name
Test status
Simulation time 216707621 ps
CPU time 3.02 seconds
Started Mar 03 02:45:36 PM PST 24
Finished Mar 03 02:45:40 PM PST 24
Peak memory 216556 kb
Host smart-8dfa5b50-c669-4945-a852-c4ad76fc998d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070569507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.3070569507
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.946394165
Short name T693
Test name
Test status
Simulation time 38204671 ps
CPU time 0.86 seconds
Started Mar 03 02:45:34 PM PST 24
Finished Mar 03 02:45:36 PM PST 24
Peak memory 214216 kb
Host smart-8c352e3e-fc70-4cc1-9251-f72b24e25f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946394165 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.946394165
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.922401832
Short name T752
Test name
Test status
Simulation time 62299824 ps
CPU time 0.94 seconds
Started Mar 03 02:45:34 PM PST 24
Finished Mar 03 02:45:36 PM PST 24
Peak memory 214112 kb
Host smart-4550f0ef-6c30-44c1-9b5c-353b14b7cfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922401832 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.922401832
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.1357817326
Short name T824
Test name
Test status
Simulation time 222159822 ps
CPU time 2.98 seconds
Started Mar 03 02:45:33 PM PST 24
Finished Mar 03 02:45:37 PM PST 24
Peak memory 215264 kb
Host smart-ce768066-3d99-4c8c-8012-2abec5be3541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357817326 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.1357817326
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2390457662
Short name T393
Test name
Test status
Simulation time 124342279231 ps
CPU time 1186.16 seconds
Started Mar 03 02:45:33 PM PST 24
Finished Mar 03 03:05:19 PM PST 24
Peak memory 222472 kb
Host smart-c6140c3c-d210-44a0-b3d2-bc767c0c9c8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390457662 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2390457662
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.778081664
Short name T808
Test name
Test status
Simulation time 67289393 ps
CPU time 0.91 seconds
Started Mar 03 02:47:10 PM PST 24
Finished Mar 03 02:47:11 PM PST 24
Peak memory 215316 kb
Host smart-1a6646da-0964-4d4c-81b4-aafd18af0feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778081664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.778081664
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2925244269
Short name T503
Test name
Test status
Simulation time 41101998 ps
CPU time 1.62 seconds
Started Mar 03 02:47:03 PM PST 24
Finished Mar 03 02:47:05 PM PST 24
Peak memory 216832 kb
Host smart-b5c62253-53aa-421e-aee9-4abf04e41a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925244269 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2925244269
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.4011411433
Short name T138
Test name
Test status
Simulation time 58202952 ps
CPU time 1.24 seconds
Started Mar 03 02:47:03 PM PST 24
Finished Mar 03 02:47:05 PM PST 24
Peak memory 216700 kb
Host smart-e664f520-6a13-425b-a709-68f6af2f94e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011411433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.4011411433
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.1826084861
Short name T636
Test name
Test status
Simulation time 50648936 ps
CPU time 1.37 seconds
Started Mar 03 02:47:04 PM PST 24
Finished Mar 03 02:47:06 PM PST 24
Peak memory 216832 kb
Host smart-2ab8b7b6-abc7-456a-bbd9-287a10fbad7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826084861 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.1826084861
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1177733081
Short name T472
Test name
Test status
Simulation time 44814374 ps
CPU time 1.16 seconds
Started Mar 03 02:47:04 PM PST 24
Finished Mar 03 02:47:06 PM PST 24
Peak memory 214108 kb
Host smart-158514a2-565a-47c3-b9a3-a775759a26ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177733081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1177733081
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.944395859
Short name T424
Test name
Test status
Simulation time 60118307 ps
CPU time 2.04 seconds
Started Mar 03 02:47:05 PM PST 24
Finished Mar 03 02:47:07 PM PST 24
Peak memory 217464 kb
Host smart-910ff2d6-dd3a-418c-85e9-f8d6c0dbe3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944395859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.944395859
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1710014039
Short name T544
Test name
Test status
Simulation time 47787150 ps
CPU time 1.34 seconds
Started Mar 03 02:47:04 PM PST 24
Finished Mar 03 02:47:06 PM PST 24
Peak memory 216520 kb
Host smart-3fe47d8f-1126-4cd2-89eb-4b2f36cfbf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710014039 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1710014039
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.508090467
Short name T388
Test name
Test status
Simulation time 82094692 ps
CPU time 1.43 seconds
Started Mar 03 02:47:08 PM PST 24
Finished Mar 03 02:47:10 PM PST 24
Peak memory 216924 kb
Host smart-d44154f3-d053-4ca8-81d7-3a13803a6d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508090467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.508090467
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.1888503181
Short name T293
Test name
Test status
Simulation time 38588196 ps
CPU time 1.41 seconds
Started Mar 03 02:47:04 PM PST 24
Finished Mar 03 02:47:06 PM PST 24
Peak memory 215516 kb
Host smart-4fadb0b5-64b2-4ef0-8a2a-29ae8f6187d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888503181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.1888503181
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3022670418
Short name T564
Test name
Test status
Simulation time 40178049 ps
CPU time 1.2 seconds
Started Mar 03 02:47:05 PM PST 24
Finished Mar 03 02:47:06 PM PST 24
Peak memory 215316 kb
Host smart-3ba74d1c-9407-49eb-8cd1-bd855bcbe9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022670418 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3022670418
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2971014806
Short name T186
Test name
Test status
Simulation time 47570200 ps
CPU time 1.22 seconds
Started Mar 03 02:44:35 PM PST 24
Finished Mar 03 02:44:36 PM PST 24
Peak memory 214560 kb
Host smart-c545e07e-fed0-42d2-865d-f2778de704a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971014806 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2971014806
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.2774511107
Short name T228
Test name
Test status
Simulation time 44538173 ps
CPU time 0.85 seconds
Started Mar 03 02:44:35 PM PST 24
Finished Mar 03 02:44:36 PM PST 24
Peak memory 205360 kb
Host smart-4a8cce72-13a3-48ca-bfc0-2d9b4e044515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774511107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2774511107
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.92981701
Short name T175
Test name
Test status
Simulation time 13164289 ps
CPU time 0.93 seconds
Started Mar 03 02:44:42 PM PST 24
Finished Mar 03 02:44:43 PM PST 24
Peak memory 214724 kb
Host smart-dfc17eea-b78d-4ff0-81df-a026459eee74
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92981701 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.92981701
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_err.887054105
Short name T621
Test name
Test status
Simulation time 18653303 ps
CPU time 1.01 seconds
Started Mar 03 02:44:35 PM PST 24
Finished Mar 03 02:44:36 PM PST 24
Peak memory 216516 kb
Host smart-843f05f7-31cb-47c5-b3a9-33afc9974f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887054105 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.887054105
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.2404273928
Short name T687
Test name
Test status
Simulation time 82156451 ps
CPU time 1.42 seconds
Started Mar 03 02:44:35 PM PST 24
Finished Mar 03 02:44:36 PM PST 24
Peak memory 216536 kb
Host smart-5d2b1431-8674-4a15-8113-8abf089c9832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404273928 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.2404273928
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.964941455
Short name T566
Test name
Test status
Simulation time 23026247 ps
CPU time 1.09 seconds
Started Mar 03 02:44:38 PM PST 24
Finished Mar 03 02:44:39 PM PST 24
Peak memory 214496 kb
Host smart-5a68ec56-52ee-49ee-b276-41673befc9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964941455 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.964941455
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.3893201024
Short name T260
Test name
Test status
Simulation time 131407859 ps
CPU time 0.84 seconds
Started Mar 03 02:44:35 PM PST 24
Finished Mar 03 02:44:36 PM PST 24
Peak memory 205760 kb
Host smart-e2f1fc47-e33e-4fdf-b60b-7de5e95e26af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893201024 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3893201024
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.1585795238
Short name T57
Test name
Test status
Simulation time 400818139 ps
CPU time 3.53 seconds
Started Mar 03 02:44:41 PM PST 24
Finished Mar 03 02:44:45 PM PST 24
Peak memory 234348 kb
Host smart-7c2abf22-855b-4f07-8d2d-6a2864212cb5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585795238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.1585795238
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.1286214387
Short name T314
Test name
Test status
Simulation time 28509024 ps
CPU time 1.05 seconds
Started Mar 03 02:44:41 PM PST 24
Finished Mar 03 02:44:42 PM PST 24
Peak memory 214044 kb
Host smart-1e5fa6fd-15e8-4031-950b-f06ebb61b680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286214387 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.1286214387
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.3345216274
Short name T299
Test name
Test status
Simulation time 2046249070 ps
CPU time 3.71 seconds
Started Mar 03 02:44:44 PM PST 24
Finished Mar 03 02:44:47 PM PST 24
Peak memory 215316 kb
Host smart-0446dfee-5557-45d2-96fb-bf5e3a7ece00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345216274 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.3345216274
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3921392227
Short name T189
Test name
Test status
Simulation time 39254298295 ps
CPU time 741.67 seconds
Started Mar 03 02:44:35 PM PST 24
Finished Mar 03 02:56:57 PM PST 24
Peak memory 216504 kb
Host smart-4e7de73a-53b1-4977-b9c9-06673570b0c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921392227 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3921392227
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.3169157040
Short name T673
Test name
Test status
Simulation time 25683745 ps
CPU time 1.22 seconds
Started Mar 03 02:45:34 PM PST 24
Finished Mar 03 02:45:36 PM PST 24
Peak memory 214564 kb
Host smart-b70316dd-0130-44d0-9b59-c7c37c7b8645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169157040 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3169157040
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1460255578
Short name T319
Test name
Test status
Simulation time 36667441 ps
CPU time 1.21 seconds
Started Mar 03 02:45:41 PM PST 24
Finished Mar 03 02:45:43 PM PST 24
Peak memory 205804 kb
Host smart-c4b73f34-bb74-46a7-baad-75135405e515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460255578 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1460255578
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.1152795814
Short name T536
Test name
Test status
Simulation time 34614015 ps
CPU time 0.86 seconds
Started Mar 03 02:45:39 PM PST 24
Finished Mar 03 02:45:40 PM PST 24
Peak memory 214332 kb
Host smart-24b5075f-aa46-45c5-930c-1f848bf63717
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152795814 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1152795814
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_err.1056744865
Short name T172
Test name
Test status
Simulation time 33752449 ps
CPU time 0.88 seconds
Started Mar 03 02:45:33 PM PST 24
Finished Mar 03 02:45:34 PM PST 24
Peak memory 216868 kb
Host smart-5b10115d-5cd8-4e65-bbfe-b729902ef15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056744865 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1056744865
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3797231368
Short name T740
Test name
Test status
Simulation time 56629732 ps
CPU time 2.13 seconds
Started Mar 03 02:45:37 PM PST 24
Finished Mar 03 02:45:40 PM PST 24
Peak memory 215532 kb
Host smart-c34b408b-f009-4307-96b3-0eb5d0484699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797231368 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3797231368
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2405595495
Short name T627
Test name
Test status
Simulation time 22395312 ps
CPU time 1.13 seconds
Started Mar 03 02:45:36 PM PST 24
Finished Mar 03 02:45:39 PM PST 24
Peak memory 214464 kb
Host smart-d9c615a0-33e3-4b2e-b1d1-ee8b94333ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405595495 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2405595495
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2956425238
Short name T402
Test name
Test status
Simulation time 19320487 ps
CPU time 1.07 seconds
Started Mar 03 02:45:36 PM PST 24
Finished Mar 03 02:45:39 PM PST 24
Peak memory 214104 kb
Host smart-18f8940c-2f52-4794-ab3f-2e042946c19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956425238 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2956425238
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.995505308
Short name T584
Test name
Test status
Simulation time 217177245 ps
CPU time 4.47 seconds
Started Mar 03 02:45:36 PM PST 24
Finished Mar 03 02:45:40 PM PST 24
Peak memory 215408 kb
Host smart-61045b45-18d3-4a5f-b9c3-e7091e207e81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995505308 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.995505308
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3952051853
Short name T515
Test name
Test status
Simulation time 166047552525 ps
CPU time 989.02 seconds
Started Mar 03 02:45:33 PM PST 24
Finished Mar 03 03:02:03 PM PST 24
Peak memory 219492 kb
Host smart-5e314052-44d6-4d4e-9c7d-effc33a0a7cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952051853 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3952051853
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1374859599
Short name T250
Test name
Test status
Simulation time 25641586 ps
CPU time 1.21 seconds
Started Mar 03 02:45:40 PM PST 24
Finished Mar 03 02:45:42 PM PST 24
Peak memory 214560 kb
Host smart-00041700-fc08-4161-b4a8-e6a9ec3c53c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374859599 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1374859599
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.2703639370
Short name T532
Test name
Test status
Simulation time 51987514 ps
CPU time 0.91 seconds
Started Mar 03 02:45:42 PM PST 24
Finished Mar 03 02:45:43 PM PST 24
Peak memory 205804 kb
Host smart-6d8ec2b4-07ef-4e4c-bbe9-ce576456af3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703639370 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.2703639370
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.3675273898
Short name T816
Test name
Test status
Simulation time 10821681 ps
CPU time 0.86 seconds
Started Mar 03 02:45:38 PM PST 24
Finished Mar 03 02:45:39 PM PST 24
Peak memory 214616 kb
Host smart-4a743481-9366-4a8f-9384-920b49e1b400
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675273898 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.3675273898
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.2564082044
Short name T123
Test name
Test status
Simulation time 31804251 ps
CPU time 0.87 seconds
Started Mar 03 02:45:43 PM PST 24
Finished Mar 03 02:45:44 PM PST 24
Peak memory 216792 kb
Host smart-6be57162-2ab7-4f16-b9e0-dc2438821eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564082044 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2564082044
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.3900532389
Short name T339
Test name
Test status
Simulation time 143459607 ps
CPU time 1.11 seconds
Started Mar 03 02:45:38 PM PST 24
Finished Mar 03 02:45:40 PM PST 24
Peak memory 215528 kb
Host smart-7f011543-fee5-41d7-b11d-70caaf3e1798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900532389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.3900532389
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2021865085
Short name T827
Test name
Test status
Simulation time 27996032 ps
CPU time 0.99 seconds
Started Mar 03 02:45:40 PM PST 24
Finished Mar 03 02:45:42 PM PST 24
Peak memory 214316 kb
Host smart-509ce5d6-67f8-4dc6-8cc6-cb0f1bbb3869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021865085 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2021865085
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.559458681
Short name T750
Test name
Test status
Simulation time 16426144 ps
CPU time 0.95 seconds
Started Mar 03 02:45:38 PM PST 24
Finished Mar 03 02:45:40 PM PST 24
Peak memory 214188 kb
Host smart-9f1bdc50-6392-4de1-b701-c57e6b12b957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559458681 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.559458681
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1034870034
Short name T340
Test name
Test status
Simulation time 511865776 ps
CPU time 4.45 seconds
Started Mar 03 02:45:39 PM PST 24
Finished Mar 03 02:45:44 PM PST 24
Peak memory 215232 kb
Host smart-500c49f9-9b62-46d3-9814-24a141eed3c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034870034 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1034870034
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.3241493070
Short name T671
Test name
Test status
Simulation time 153586837128 ps
CPU time 841.13 seconds
Started Mar 03 02:45:40 PM PST 24
Finished Mar 03 02:59:42 PM PST 24
Peak memory 222228 kb
Host smart-fcd8e249-b0c9-4d26-9a6a-c00308744466
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241493070 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.3241493070
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.1997536360
Short name T685
Test name
Test status
Simulation time 26383111 ps
CPU time 1.19 seconds
Started Mar 03 02:45:39 PM PST 24
Finished Mar 03 02:45:40 PM PST 24
Peak memory 214528 kb
Host smart-65732281-08ae-443d-9a45-47db59d1f97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997536360 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1997536360
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.3371470862
Short name T478
Test name
Test status
Simulation time 53024442 ps
CPU time 0.82 seconds
Started Mar 03 02:45:40 PM PST 24
Finished Mar 03 02:45:41 PM PST 24
Peak memory 205304 kb
Host smart-2074fe0a-50f8-4747-a89a-ae9792139aa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371470862 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.3371470862
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.910376179
Short name T391
Test name
Test status
Simulation time 13295991 ps
CPU time 0.96 seconds
Started Mar 03 02:45:40 PM PST 24
Finished Mar 03 02:45:41 PM PST 24
Peak memory 214400 kb
Host smart-188d9c38-1af6-4cad-9d13-32abeadb3376
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910376179 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.910376179
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_err.2860488669
Short name T54
Test name
Test status
Simulation time 93096393 ps
CPU time 1.08 seconds
Started Mar 03 02:45:41 PM PST 24
Finished Mar 03 02:45:42 PM PST 24
Peak memory 228340 kb
Host smart-0a7bea39-84f9-4605-aa74-870dc7780398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860488669 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.2860488669
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.2359172580
Short name T734
Test name
Test status
Simulation time 75701181 ps
CPU time 1 seconds
Started Mar 03 02:45:42 PM PST 24
Finished Mar 03 02:45:43 PM PST 24
Peak memory 215392 kb
Host smart-d0de03c8-ba53-4b10-b7c6-908a434ea49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359172580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.2359172580
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3596238181
Short name T46
Test name
Test status
Simulation time 22400638 ps
CPU time 0.96 seconds
Started Mar 03 02:45:42 PM PST 24
Finished Mar 03 02:45:43 PM PST 24
Peak memory 214484 kb
Host smart-c8b28e81-8f59-4367-b7ad-476a5da3575c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596238181 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3596238181
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1026330060
Short name T680
Test name
Test status
Simulation time 51894438 ps
CPU time 0.93 seconds
Started Mar 03 02:45:41 PM PST 24
Finished Mar 03 02:45:43 PM PST 24
Peak memory 214124 kb
Host smart-16455a17-e35f-41c9-90d4-53044e3d83ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026330060 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1026330060
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.2224393884
Short name T437
Test name
Test status
Simulation time 53880680577 ps
CPU time 1410.3 seconds
Started Mar 03 02:45:37 PM PST 24
Finished Mar 03 03:09:08 PM PST 24
Peak memory 221860 kb
Host smart-5aabe75f-2a11-4306-a36d-26216c27095f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224393884 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.2224393884
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3931957183
Short name T105
Test name
Test status
Simulation time 24993250 ps
CPU time 1.18 seconds
Started Mar 03 02:45:40 PM PST 24
Finished Mar 03 02:45:41 PM PST 24
Peak memory 214460 kb
Host smart-193fcf6f-4ea3-44f0-adf7-96b03cb45190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931957183 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3931957183
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1578419910
Short name T529
Test name
Test status
Simulation time 34817349 ps
CPU time 0.98 seconds
Started Mar 03 02:45:41 PM PST 24
Finished Mar 03 02:45:42 PM PST 24
Peak memory 205804 kb
Host smart-a441e6a5-a8c0-455e-882c-7db53bf7bd3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578419910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1578419910
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1530465366
Short name T716
Test name
Test status
Simulation time 41590329 ps
CPU time 0.91 seconds
Started Mar 03 02:45:38 PM PST 24
Finished Mar 03 02:45:40 PM PST 24
Peak memory 214724 kb
Host smart-4a13ea55-1e0f-4c35-b8d2-1872b01398f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530465366 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1530465366
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_err.2296723967
Short name T112
Test name
Test status
Simulation time 19935826 ps
CPU time 1.09 seconds
Started Mar 03 02:45:43 PM PST 24
Finished Mar 03 02:45:44 PM PST 24
Peak memory 216716 kb
Host smart-241c26bc-1271-40a3-97f6-da8e0858058a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296723967 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.2296723967
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.3389711197
Short name T495
Test name
Test status
Simulation time 83211521 ps
CPU time 1.17 seconds
Started Mar 03 02:45:39 PM PST 24
Finished Mar 03 02:45:40 PM PST 24
Peak memory 215656 kb
Host smart-412981ff-8da7-4fd0-98cc-4d1b385b481d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389711197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.3389711197
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.3371928930
Short name T136
Test name
Test status
Simulation time 41195460 ps
CPU time 0.83 seconds
Started Mar 03 02:45:38 PM PST 24
Finished Mar 03 02:45:39 PM PST 24
Peak memory 214328 kb
Host smart-663da9a7-8ddd-4aa5-bb6c-b6ec06a4ff64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371928930 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.3371928930
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.1808366144
Short name T303
Test name
Test status
Simulation time 15498378 ps
CPU time 0.99 seconds
Started Mar 03 02:45:38 PM PST 24
Finished Mar 03 02:45:40 PM PST 24
Peak memory 214124 kb
Host smart-1f3baee1-a681-4ece-8c3d-cabf80bfdbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808366144 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.1808366144
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.423142631
Short name T377
Test name
Test status
Simulation time 154516279 ps
CPU time 3.42 seconds
Started Mar 03 02:45:38 PM PST 24
Finished Mar 03 02:45:42 PM PST 24
Peak memory 214128 kb
Host smart-fa4d4b2c-a87a-47fc-91e2-662275b1b40f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423142631 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.423142631
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3636877932
Short name T559
Test name
Test status
Simulation time 69451989584 ps
CPU time 1343.66 seconds
Started Mar 03 02:45:43 PM PST 24
Finished Mar 03 03:08:07 PM PST 24
Peak memory 222464 kb
Host smart-4bb7e266-9ae4-4ad3-920e-451cede117fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636877932 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3636877932
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.82085151
Short name T650
Test name
Test status
Simulation time 49067546 ps
CPU time 1.14 seconds
Started Mar 03 02:45:42 PM PST 24
Finished Mar 03 02:45:43 PM PST 24
Peak memory 214572 kb
Host smart-fff135eb-a6ed-4da6-bea2-de1f72c312ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82085151 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.82085151
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.58985561
Short name T374
Test name
Test status
Simulation time 16012559 ps
CPU time 0.88 seconds
Started Mar 03 02:45:47 PM PST 24
Finished Mar 03 02:45:49 PM PST 24
Peak memory 205844 kb
Host smart-4af861b6-1650-4ca6-8e6f-df66615c7e1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58985561 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.58985561
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.4024917295
Short name T104
Test name
Test status
Simulation time 19755528 ps
CPU time 0.83 seconds
Started Mar 03 02:45:45 PM PST 24
Finished Mar 03 02:45:46 PM PST 24
Peak memory 214624 kb
Host smart-669f8566-7d18-489f-891b-8dc51f6f1865
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024917295 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.4024917295
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_err.140391425
Short name T52
Test name
Test status
Simulation time 124525172 ps
CPU time 1.03 seconds
Started Mar 03 02:45:47 PM PST 24
Finished Mar 03 02:45:48 PM PST 24
Peak memory 222020 kb
Host smart-4a3ce69e-b7c2-4446-8d55-da1d797cfd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140391425 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.140391425
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.569972923
Short name T421
Test name
Test status
Simulation time 93738942 ps
CPU time 1.19 seconds
Started Mar 03 02:45:44 PM PST 24
Finished Mar 03 02:45:45 PM PST 24
Peak memory 215320 kb
Host smart-714f036f-a86a-407b-8df6-405d0c47acf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569972923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.569972923
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.3245474602
Short name T415
Test name
Test status
Simulation time 102458630 ps
CPU time 0.82 seconds
Started Mar 03 02:45:44 PM PST 24
Finished Mar 03 02:45:45 PM PST 24
Peak memory 214044 kb
Host smart-0982d373-98bb-418e-88c3-31d85c8382d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245474602 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3245474602
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.1825943727
Short name T672
Test name
Test status
Simulation time 25637815 ps
CPU time 0.92 seconds
Started Mar 03 02:45:46 PM PST 24
Finished Mar 03 02:45:48 PM PST 24
Peak memory 214116 kb
Host smart-9fe6a91d-3cb6-44d1-a594-4a00d95a8750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825943727 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.1825943727
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.469089678
Short name T572
Test name
Test status
Simulation time 196947111 ps
CPU time 2.46 seconds
Started Mar 03 02:45:44 PM PST 24
Finished Mar 03 02:45:46 PM PST 24
Peak memory 214136 kb
Host smart-51f5ac4c-32fe-412c-8441-4622bc30f6d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469089678 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.469089678
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1124813765
Short name T666
Test name
Test status
Simulation time 13815323578 ps
CPU time 338.45 seconds
Started Mar 03 02:45:46 PM PST 24
Finished Mar 03 02:51:25 PM PST 24
Peak memory 217132 kb
Host smart-595a1bd9-cd19-4aeb-8542-0462d231bcdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124813765 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1124813765
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert_test.1469507489
Short name T356
Test name
Test status
Simulation time 27302508 ps
CPU time 0.95 seconds
Started Mar 03 02:45:46 PM PST 24
Finished Mar 03 02:45:47 PM PST 24
Peak memory 205456 kb
Host smart-9cf733aa-2a15-451c-96fb-67d6a14be7ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469507489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.1469507489
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.3124731079
Short name T117
Test name
Test status
Simulation time 31345900 ps
CPU time 0.79 seconds
Started Mar 03 02:45:43 PM PST 24
Finished Mar 03 02:45:44 PM PST 24
Peak memory 214624 kb
Host smart-4bfd223d-4287-42e5-b938-916f69a00bf4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124731079 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3124731079
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3019753373
Short name T455
Test name
Test status
Simulation time 56439255 ps
CPU time 1.18 seconds
Started Mar 03 02:45:48 PM PST 24
Finished Mar 03 02:45:49 PM PST 24
Peak memory 216804 kb
Host smart-13d96cfc-4264-420e-87ae-482e81fe27a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019753373 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3019753373
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2432009204
Short name T712
Test name
Test status
Simulation time 19940650 ps
CPU time 1.09 seconds
Started Mar 03 02:45:47 PM PST 24
Finished Mar 03 02:45:49 PM PST 24
Peak memory 217044 kb
Host smart-678d2901-7a16-468d-8e73-276e8b2cf33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432009204 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2432009204
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.754019899
Short name T530
Test name
Test status
Simulation time 53256102 ps
CPU time 1.89 seconds
Started Mar 03 02:45:48 PM PST 24
Finished Mar 03 02:45:50 PM PST 24
Peak memory 216308 kb
Host smart-bbd94352-638e-45bd-af01-38791ef11569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754019899 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.754019899
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.1366104182
Short name T789
Test name
Test status
Simulation time 20238910 ps
CPU time 1 seconds
Started Mar 03 02:45:46 PM PST 24
Finished Mar 03 02:45:47 PM PST 24
Peak memory 214468 kb
Host smart-d13511ec-b52d-4a12-8bdb-d212f8ace4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366104182 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.1366104182
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3050977413
Short name T736
Test name
Test status
Simulation time 16484652 ps
CPU time 1.04 seconds
Started Mar 03 02:45:46 PM PST 24
Finished Mar 03 02:45:48 PM PST 24
Peak memory 214080 kb
Host smart-c7dda8d2-191c-4ce4-81d8-c9360da5ecaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050977413 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3050977413
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.105373887
Short name T594
Test name
Test status
Simulation time 729497589 ps
CPU time 7.24 seconds
Started Mar 03 02:45:46 PM PST 24
Finished Mar 03 02:45:54 PM PST 24
Peak memory 215412 kb
Host smart-15af6af4-de45-4efc-8d39-89ca59a441ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105373887 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.105373887
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.3382125113
Short name T444
Test name
Test status
Simulation time 51238609321 ps
CPU time 328.33 seconds
Started Mar 03 02:45:47 PM PST 24
Finished Mar 03 02:51:15 PM PST 24
Peak memory 217292 kb
Host smart-9e5f5a6d-a442-4533-863e-35f15deeacc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382125113 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.3382125113
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.3517627539
Short name T249
Test name
Test status
Simulation time 43490717 ps
CPU time 1.11 seconds
Started Mar 03 02:45:43 PM PST 24
Finished Mar 03 02:45:44 PM PST 24
Peak memory 214560 kb
Host smart-6de7cb54-d2ae-4b19-9408-d7b085d76f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517627539 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.3517627539
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.3539172864
Short name T493
Test name
Test status
Simulation time 72011408 ps
CPU time 1.02 seconds
Started Mar 03 02:45:49 PM PST 24
Finished Mar 03 02:45:51 PM PST 24
Peak memory 205376 kb
Host smart-501a12cd-d69f-493f-ad59-714965dbbfc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539172864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.3539172864
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.4124759790
Short name T694
Test name
Test status
Simulation time 40507043 ps
CPU time 0.87 seconds
Started Mar 03 02:45:46 PM PST 24
Finished Mar 03 02:45:48 PM PST 24
Peak memory 214620 kb
Host smart-e42210d3-9aae-4bb3-83e9-dc258cbbacef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124759790 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.4124759790
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1482622442
Short name T70
Test name
Test status
Simulation time 23855114 ps
CPU time 1.06 seconds
Started Mar 03 02:45:51 PM PST 24
Finished Mar 03 02:45:52 PM PST 24
Peak memory 216516 kb
Host smart-ab9e15ae-9c69-4f61-857f-daed6dfca84d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482622442 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1482622442
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1938214086
Short name T333
Test name
Test status
Simulation time 24598120 ps
CPU time 0.96 seconds
Started Mar 03 02:45:48 PM PST 24
Finished Mar 03 02:45:49 PM PST 24
Peak memory 216820 kb
Host smart-4720f46b-cc83-4ced-91b6-f1d3c007277d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938214086 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1938214086
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.2718666456
Short name T276
Test name
Test status
Simulation time 41722525 ps
CPU time 1.34 seconds
Started Mar 03 02:45:47 PM PST 24
Finished Mar 03 02:45:49 PM PST 24
Peak memory 216868 kb
Host smart-64c02831-2e9f-44ce-86b6-821717f13cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718666456 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.2718666456
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2188205944
Short name T51
Test name
Test status
Simulation time 33275926 ps
CPU time 1.01 seconds
Started Mar 03 02:45:46 PM PST 24
Finished Mar 03 02:45:48 PM PST 24
Peak memory 222820 kb
Host smart-3b0f7696-200b-4e2b-9382-008c27b0bd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188205944 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2188205944
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.3031267222
Short name T379
Test name
Test status
Simulation time 24394570 ps
CPU time 0.96 seconds
Started Mar 03 02:45:46 PM PST 24
Finished Mar 03 02:45:47 PM PST 24
Peak memory 214116 kb
Host smart-1b03a28c-1454-447f-9161-a882c9c1b3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031267222 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.3031267222
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2215443255
Short name T313
Test name
Test status
Simulation time 132755460 ps
CPU time 1.36 seconds
Started Mar 03 02:45:48 PM PST 24
Finished Mar 03 02:45:50 PM PST 24
Peak memory 205956 kb
Host smart-a0bca701-a0df-4ffc-bd4e-a059acef290c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215443255 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2215443255
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.2002595646
Short name T194
Test name
Test status
Simulation time 55550552026 ps
CPU time 1266 seconds
Started Mar 03 02:45:47 PM PST 24
Finished Mar 03 03:06:53 PM PST 24
Peak memory 222436 kb
Host smart-74b41ee1-fb06-47f4-8262-1970e3b00c0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002595646 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.2002595646
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1209808694
Short name T432
Test name
Test status
Simulation time 128308390 ps
CPU time 1.28 seconds
Started Mar 03 02:45:49 PM PST 24
Finished Mar 03 02:45:51 PM PST 24
Peak memory 214564 kb
Host smart-94aaa208-9382-46a9-a45c-79be6acf0445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209808694 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1209808694
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.2795424694
Short name T411
Test name
Test status
Simulation time 25118590 ps
CPU time 0.9 seconds
Started Mar 03 02:45:50 PM PST 24
Finished Mar 03 02:45:52 PM PST 24
Peak memory 205816 kb
Host smart-f5c75398-4fdc-4194-8202-5f92bdcd366a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795424694 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.2795424694
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.1451021784
Short name T630
Test name
Test status
Simulation time 21826642 ps
CPU time 0.8 seconds
Started Mar 03 02:45:49 PM PST 24
Finished Mar 03 02:45:50 PM PST 24
Peak memory 214220 kb
Host smart-ce1b952d-6807-4f2e-8183-6b178493f868
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451021784 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.1451021784
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.4024702540
Short name T318
Test name
Test status
Simulation time 49511005 ps
CPU time 1.09 seconds
Started Mar 03 02:45:49 PM PST 24
Finished Mar 03 02:45:51 PM PST 24
Peak memory 216564 kb
Host smart-6c33efb2-4f1e-4b3b-ab35-6965e5b6f066
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024702540 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.4024702540
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.1044757399
Short name T222
Test name
Test status
Simulation time 20688049 ps
CPU time 1.06 seconds
Started Mar 03 02:45:52 PM PST 24
Finished Mar 03 02:45:53 PM PST 24
Peak memory 216644 kb
Host smart-d7f9020f-bcd0-455d-ae49-4df513c754cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044757399 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.1044757399
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.390007454
Short name T807
Test name
Test status
Simulation time 72683495 ps
CPU time 1.55 seconds
Started Mar 03 02:45:47 PM PST 24
Finished Mar 03 02:45:49 PM PST 24
Peak memory 217256 kb
Host smart-1969fdbf-1bfa-4117-aab5-db7f7061f539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390007454 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.390007454
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2621330625
Short name T310
Test name
Test status
Simulation time 72512147 ps
CPU time 0.87 seconds
Started Mar 03 02:45:47 PM PST 24
Finished Mar 03 02:45:48 PM PST 24
Peak memory 214284 kb
Host smart-25cf525a-8961-4568-ac3f-f11f96d9940e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621330625 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2621330625
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.994299235
Short name T462
Test name
Test status
Simulation time 19462795 ps
CPU time 1.02 seconds
Started Mar 03 02:46:09 PM PST 24
Finished Mar 03 02:46:10 PM PST 24
Peak memory 214116 kb
Host smart-f32d6abf-83f2-4135-aca1-eec80b1e44b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994299235 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.994299235
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.1414533291
Short name T573
Test name
Test status
Simulation time 44303699 ps
CPU time 1.48 seconds
Started Mar 03 02:45:50 PM PST 24
Finished Mar 03 02:45:52 PM PST 24
Peak memory 217576 kb
Host smart-3d8051c5-8ab4-46e3-a0a0-e3c8ad1698f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414533291 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.1414533291
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.1623752829
Short name T155
Test name
Test status
Simulation time 257684305025 ps
CPU time 1406.13 seconds
Started Mar 03 02:45:51 PM PST 24
Finished Mar 03 03:09:18 PM PST 24
Peak memory 222224 kb
Host smart-ebe2b889-4e81-4637-ad3b-5c5e6607d992
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623752829 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.1623752829
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1925671070
Short name T255
Test name
Test status
Simulation time 95627767 ps
CPU time 1.32 seconds
Started Mar 03 02:45:50 PM PST 24
Finished Mar 03 02:45:51 PM PST 24
Peak memory 214548 kb
Host smart-4f16c98b-6b18-48f0-a382-ef0cde2e2c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925671070 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1925671070
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3042771891
Short name T363
Test name
Test status
Simulation time 24457841 ps
CPU time 0.88 seconds
Started Mar 03 02:45:48 PM PST 24
Finished Mar 03 02:45:49 PM PST 24
Peak memory 205460 kb
Host smart-f1448e2d-d37f-42f1-a457-93d913607308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042771891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3042771891
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.3173615240
Short name T801
Test name
Test status
Simulation time 13835321 ps
CPU time 0.91 seconds
Started Mar 03 02:45:46 PM PST 24
Finished Mar 03 02:45:48 PM PST 24
Peak memory 214816 kb
Host smart-472c9359-d69a-403b-b6a8-4924649bd652
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173615240 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.3173615240
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_err.3770095960
Short name T737
Test name
Test status
Simulation time 32423255 ps
CPU time 0.82 seconds
Started Mar 03 02:45:47 PM PST 24
Finished Mar 03 02:45:49 PM PST 24
Peak memory 216828 kb
Host smart-7249bd01-b0cb-444e-ba17-a3a0c56ed515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770095960 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.3770095960
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1242326489
Short name T539
Test name
Test status
Simulation time 103382489 ps
CPU time 1.19 seconds
Started Mar 03 02:45:51 PM PST 24
Finished Mar 03 02:45:52 PM PST 24
Peak memory 215396 kb
Host smart-24bfc689-6d44-450b-90fc-b1790c5a84d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242326489 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1242326489
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.376155726
Short name T316
Test name
Test status
Simulation time 25716720 ps
CPU time 0.98 seconds
Started Mar 03 02:45:49 PM PST 24
Finished Mar 03 02:45:51 PM PST 24
Peak memory 214492 kb
Host smart-c39a1371-4e96-4431-aabf-c6be61574456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376155726 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.376155726
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.2490689416
Short name T522
Test name
Test status
Simulation time 16455021 ps
CPU time 0.97 seconds
Started Mar 03 02:45:50 PM PST 24
Finished Mar 03 02:45:51 PM PST 24
Peak memory 214124 kb
Host smart-62ccaa51-9f33-4ccb-8500-39b994f15c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490689416 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.2490689416
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.4255818064
Short name T300
Test name
Test status
Simulation time 313712506 ps
CPU time 6.44 seconds
Started Mar 03 02:45:49 PM PST 24
Finished Mar 03 02:45:56 PM PST 24
Peak memory 215432 kb
Host smart-ece668da-d33a-4ed1-b411-8a0afbbc42b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255818064 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.4255818064
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.320420347
Short name T581
Test name
Test status
Simulation time 34220341810 ps
CPU time 876.1 seconds
Started Mar 03 02:45:49 PM PST 24
Finished Mar 03 03:00:26 PM PST 24
Peak memory 217604 kb
Host smart-87ed5dbb-fbff-49ed-8edd-6e6a79ac3804
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320420347 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.320420347
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2189229402
Short name T258
Test name
Test status
Simulation time 65646488 ps
CPU time 1.16 seconds
Started Mar 03 02:45:49 PM PST 24
Finished Mar 03 02:45:51 PM PST 24
Peak memory 214552 kb
Host smart-548be2b6-8b92-465c-9cef-6086da1010f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189229402 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2189229402
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.436580746
Short name T302
Test name
Test status
Simulation time 15323268 ps
CPU time 0.96 seconds
Started Mar 03 02:45:58 PM PST 24
Finished Mar 03 02:45:59 PM PST 24
Peak memory 205832 kb
Host smart-a6d620d9-155d-4bcf-bcb3-4c9406289ee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436580746 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.436580746
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2686778886
Short name T662
Test name
Test status
Simulation time 18696261 ps
CPU time 0.83 seconds
Started Mar 03 02:45:53 PM PST 24
Finished Mar 03 02:45:54 PM PST 24
Peak memory 214616 kb
Host smart-0f66fe81-4230-4742-ad1f-41075a1a4832
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686778886 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2686778886
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_err.2207824921
Short name T606
Test name
Test status
Simulation time 35089493 ps
CPU time 0.9 seconds
Started Mar 03 02:45:48 PM PST 24
Finished Mar 03 02:45:49 PM PST 24
Peak memory 216724 kb
Host smart-2948889d-e4b0-47ec-b8b3-4cbb602878ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207824921 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.2207824921
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.3346822463
Short name T380
Test name
Test status
Simulation time 78100124 ps
CPU time 1.14 seconds
Started Mar 03 02:45:50 PM PST 24
Finished Mar 03 02:45:52 PM PST 24
Peak memory 214112 kb
Host smart-1bc3422b-f8ca-460b-96b1-fb4b7e47467d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346822463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.3346822463
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.4268150771
Short name T635
Test name
Test status
Simulation time 24885585 ps
CPU time 1.06 seconds
Started Mar 03 02:45:49 PM PST 24
Finished Mar 03 02:45:50 PM PST 24
Peak memory 222008 kb
Host smart-e66dc7d2-7186-4970-8add-2c455a994f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268150771 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.4268150771
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2661564094
Short name T407
Test name
Test status
Simulation time 14453669 ps
CPU time 0.95 seconds
Started Mar 03 02:45:49 PM PST 24
Finished Mar 03 02:45:50 PM PST 24
Peak memory 214108 kb
Host smart-bd034866-aa10-43fd-809f-2c9e2c2996c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661564094 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2661564094
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.2997137886
Short name T406
Test name
Test status
Simulation time 62901286 ps
CPU time 1.27 seconds
Started Mar 03 02:45:49 PM PST 24
Finished Mar 03 02:45:51 PM PST 24
Peak memory 215508 kb
Host smart-6297b5e0-6113-44d0-b6b4-a6e95f52f018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997137886 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.2997137886
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3567943483
Short name T305
Test name
Test status
Simulation time 175068517155 ps
CPU time 990.32 seconds
Started Mar 03 02:45:48 PM PST 24
Finished Mar 03 03:02:19 PM PST 24
Peak memory 219240 kb
Host smart-b540e5c3-988b-4b57-b4c2-de206e1c37be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567943483 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3567943483
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3273527185
Short name T128
Test name
Test status
Simulation time 191027454 ps
CPU time 1.26 seconds
Started Mar 03 02:44:43 PM PST 24
Finished Mar 03 02:44:44 PM PST 24
Peak memory 214468 kb
Host smart-063d86d9-9b6c-4d56-b1c3-5324768003a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273527185 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3273527185
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1995731408
Short name T613
Test name
Test status
Simulation time 24044880 ps
CPU time 0.92 seconds
Started Mar 03 02:44:40 PM PST 24
Finished Mar 03 02:44:41 PM PST 24
Peak memory 205872 kb
Host smart-5db963d0-46db-49bc-843b-d5727fc86034
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995731408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1995731408
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2598167069
Short name T646
Test name
Test status
Simulation time 91565317 ps
CPU time 1.11 seconds
Started Mar 03 02:44:52 PM PST 24
Finished Mar 03 02:44:53 PM PST 24
Peak memory 216760 kb
Host smart-f52398a5-5096-4b57-b97d-278f6c856a39
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598167069 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2598167069
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3900605711
Short name T348
Test name
Test status
Simulation time 21030196 ps
CPU time 0.91 seconds
Started Mar 03 02:44:40 PM PST 24
Finished Mar 03 02:44:41 PM PST 24
Peak memory 216452 kb
Host smart-785fb637-534f-4773-9cca-c5a00ab47f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900605711 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3900605711
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2698235240
Short name T176
Test name
Test status
Simulation time 93401542 ps
CPU time 1.56 seconds
Started Mar 03 02:44:42 PM PST 24
Finished Mar 03 02:44:44 PM PST 24
Peak memory 216884 kb
Host smart-1a363936-06e8-4dc2-b9bb-5c330b3a0169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698235240 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2698235240
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.1265656447
Short name T132
Test name
Test status
Simulation time 27813180 ps
CPU time 0.9 seconds
Started Mar 03 02:44:41 PM PST 24
Finished Mar 03 02:44:42 PM PST 24
Peak memory 214460 kb
Host smart-527d6866-4e3a-4aea-a0fb-bddc002d6192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265656447 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.1265656447
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.1000826074
Short name T129
Test name
Test status
Simulation time 27241484 ps
CPU time 0.99 seconds
Started Mar 03 02:44:43 PM PST 24
Finished Mar 03 02:44:44 PM PST 24
Peak memory 206120 kb
Host smart-3e02ef28-5c40-498a-8a6b-702a4e57b88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000826074 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.1000826074
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.2143964679
Short name T1
Test name
Test status
Simulation time 27858653 ps
CPU time 0.99 seconds
Started Mar 03 02:44:41 PM PST 24
Finished Mar 03 02:44:42 PM PST 24
Peak memory 214060 kb
Host smart-01fa7ac5-38ff-4c41-a4ff-b69f2e196e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143964679 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.2143964679
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.4001120967
Short name T490
Test name
Test status
Simulation time 255398514 ps
CPU time 2.08 seconds
Started Mar 03 02:44:43 PM PST 24
Finished Mar 03 02:44:45 PM PST 24
Peak memory 215460 kb
Host smart-0d0f128a-d70c-4207-86af-4395c9e36981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001120967 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.4001120967
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.593891174
Short name T784
Test name
Test status
Simulation time 167710583339 ps
CPU time 948.66 seconds
Started Mar 03 02:44:40 PM PST 24
Finished Mar 03 03:00:29 PM PST 24
Peak memory 220032 kb
Host smart-fd12fbb9-1179-4b4b-84fd-74c465574457
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593891174 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.593891174
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.3815171771
Short name T418
Test name
Test status
Simulation time 133588883 ps
CPU time 1.22 seconds
Started Mar 03 02:45:55 PM PST 24
Finished Mar 03 02:45:57 PM PST 24
Peak memory 214472 kb
Host smart-84a08de6-eb9e-4e2d-835b-330035302cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815171771 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.3815171771
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2464806571
Short name T524
Test name
Test status
Simulation time 12931917 ps
CPU time 0.89 seconds
Started Mar 03 02:45:53 PM PST 24
Finished Mar 03 02:45:55 PM PST 24
Peak memory 205816 kb
Host smart-cbe3eacf-cfd6-4838-9318-ab80db366d02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464806571 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2464806571
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.4015289519
Short name T423
Test name
Test status
Simulation time 15285066 ps
CPU time 0.82 seconds
Started Mar 03 02:45:57 PM PST 24
Finished Mar 03 02:45:58 PM PST 24
Peak memory 214736 kb
Host smart-b45bd721-0c9d-44e3-a320-c1451f430781
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015289519 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.4015289519
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.3974584405
Short name T88
Test name
Test status
Simulation time 28505336 ps
CPU time 1.15 seconds
Started Mar 03 02:46:00 PM PST 24
Finished Mar 03 02:46:01 PM PST 24
Peak memory 217424 kb
Host smart-113fa6b7-3cf0-4590-b054-62ed7bcc2ea1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974584405 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.3974584405
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.55032972
Short name T124
Test name
Test status
Simulation time 18348331 ps
CPU time 1.12 seconds
Started Mar 03 02:45:53 PM PST 24
Finished Mar 03 02:45:55 PM PST 24
Peak memory 221868 kb
Host smart-fc736176-361f-4713-9000-bcb9e8dbe1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55032972 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.55032972
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_intr.3579143845
Short name T479
Test name
Test status
Simulation time 125684871 ps
CPU time 0.84 seconds
Started Mar 03 02:45:53 PM PST 24
Finished Mar 03 02:45:54 PM PST 24
Peak memory 214116 kb
Host smart-fd1d4155-a2e6-466d-bd9e-0c0cb32c1b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579143845 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.3579143845
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.2155774582
Short name T770
Test name
Test status
Simulation time 15818476 ps
CPU time 0.97 seconds
Started Mar 03 02:45:54 PM PST 24
Finished Mar 03 02:45:55 PM PST 24
Peak memory 214048 kb
Host smart-234c722f-152e-4691-8c62-92b093b7229a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155774582 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.2155774582
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.272941492
Short name T811
Test name
Test status
Simulation time 160830400 ps
CPU time 3.33 seconds
Started Mar 03 02:45:56 PM PST 24
Finished Mar 03 02:45:59 PM PST 24
Peak memory 215128 kb
Host smart-820230e2-1a3a-406c-9385-f1d439b0574e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272941492 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.272941492
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.3231837936
Short name T143
Test name
Test status
Simulation time 269717952703 ps
CPU time 2898.09 seconds
Started Mar 03 02:46:00 PM PST 24
Finished Mar 03 03:34:18 PM PST 24
Peak memory 227704 kb
Host smart-36ae0c62-2d45-4202-b480-78f5b8990283
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231837936 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.3231837936
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2930524812
Short name T109
Test name
Test status
Simulation time 63611730 ps
CPU time 1.12 seconds
Started Mar 03 02:45:58 PM PST 24
Finished Mar 03 02:45:59 PM PST 24
Peak memory 214556 kb
Host smart-7d13e150-13c0-47d3-86c5-78f678abb03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930524812 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2930524812
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.2014196846
Short name T439
Test name
Test status
Simulation time 17451768 ps
CPU time 0.96 seconds
Started Mar 03 02:46:05 PM PST 24
Finished Mar 03 02:46:06 PM PST 24
Peak memory 205816 kb
Host smart-c27e3644-883c-4b8c-bbd9-c9b50a79ecf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014196846 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.2014196846
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3086226878
Short name T631
Test name
Test status
Simulation time 22992335 ps
CPU time 0.86 seconds
Started Mar 03 02:45:58 PM PST 24
Finished Mar 03 02:45:59 PM PST 24
Peak memory 214332 kb
Host smart-d9166de8-9e23-4af5-9040-35f9064902a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086226878 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3086226878
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_err.918399198
Short name T409
Test name
Test status
Simulation time 56238614 ps
CPU time 1.41 seconds
Started Mar 03 02:45:59 PM PST 24
Finished Mar 03 02:46:00 PM PST 24
Peak memory 223008 kb
Host smart-27d6b4bb-7a34-4761-a308-109bbc78cf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918399198 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.918399198
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.475200145
Short name T534
Test name
Test status
Simulation time 70391900 ps
CPU time 1.37 seconds
Started Mar 03 02:45:57 PM PST 24
Finished Mar 03 02:45:59 PM PST 24
Peak memory 217164 kb
Host smart-fade3baf-cd5c-44a4-8876-196044f96af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475200145 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.475200145
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.4047551972
Short name T133
Test name
Test status
Simulation time 34034365 ps
CPU time 0.86 seconds
Started Mar 03 02:45:59 PM PST 24
Finished Mar 03 02:46:00 PM PST 24
Peak memory 214328 kb
Host smart-f507035e-7530-41d0-9416-559b4307b8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047551972 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.4047551972
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3457721940
Short name T569
Test name
Test status
Simulation time 41798741 ps
CPU time 0.9 seconds
Started Mar 03 02:45:55 PM PST 24
Finished Mar 03 02:45:56 PM PST 24
Peak memory 214044 kb
Host smart-d63aa458-369c-430c-ba3c-d4d266521e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457721940 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3457721940
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3672270709
Short name T146
Test name
Test status
Simulation time 249945175 ps
CPU time 1.89 seconds
Started Mar 03 02:45:53 PM PST 24
Finished Mar 03 02:45:56 PM PST 24
Peak memory 215404 kb
Host smart-f355d272-9f2a-467c-9a15-62599dc596cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672270709 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3672270709
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.236124002
Short name T814
Test name
Test status
Simulation time 9315510724 ps
CPU time 236.23 seconds
Started Mar 03 02:46:00 PM PST 24
Finished Mar 03 02:49:56 PM PST 24
Peak memory 216260 kb
Host smart-2de6f9a9-53e1-4a05-90a3-56dec82dd69b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236124002 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.236124002
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3400459876
Short name T107
Test name
Test status
Simulation time 29003505 ps
CPU time 1.18 seconds
Started Mar 03 02:46:00 PM PST 24
Finished Mar 03 02:46:01 PM PST 24
Peak memory 214568 kb
Host smart-96fc4819-5d1c-437c-96b7-cb8fda61828f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400459876 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3400459876
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.351964417
Short name T797
Test name
Test status
Simulation time 19782632 ps
CPU time 0.86 seconds
Started Mar 03 02:46:02 PM PST 24
Finished Mar 03 02:46:03 PM PST 24
Peak memory 204652 kb
Host smart-66c9e33a-2fa5-485c-8c0e-99455df6d39d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351964417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.351964417
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3183381618
Short name T171
Test name
Test status
Simulation time 16141139 ps
CPU time 0.89 seconds
Started Mar 03 02:46:00 PM PST 24
Finished Mar 03 02:46:01 PM PST 24
Peak memory 214628 kb
Host smart-9e9f8e27-d84d-487b-ab7d-4e6a10bd10f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183381618 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3183381618
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_err.2528801845
Short name T98
Test name
Test status
Simulation time 45556826 ps
CPU time 1.12 seconds
Started Mar 03 02:45:59 PM PST 24
Finished Mar 03 02:46:00 PM PST 24
Peak memory 218016 kb
Host smart-1085c299-7c7b-42de-9de5-6b932c9a5da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528801845 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.2528801845
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.1736105795
Short name T497
Test name
Test status
Simulation time 80920521 ps
CPU time 1.06 seconds
Started Mar 03 02:46:05 PM PST 24
Finished Mar 03 02:46:06 PM PST 24
Peak memory 214132 kb
Host smart-1cd67b61-edc1-4899-83e1-20f994e00556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736105795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.1736105795
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.1668177174
Short name T805
Test name
Test status
Simulation time 21497545 ps
CPU time 1.13 seconds
Started Mar 03 02:45:58 PM PST 24
Finished Mar 03 02:46:00 PM PST 24
Peak memory 214480 kb
Host smart-e361d415-bec5-4647-ac32-2bfc8f5e35cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668177174 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.1668177174
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.3299083056
Short name T638
Test name
Test status
Simulation time 25005554 ps
CPU time 0.92 seconds
Started Mar 03 02:45:59 PM PST 24
Finished Mar 03 02:46:00 PM PST 24
Peak memory 214120 kb
Host smart-b234be2e-00d7-48be-a2ec-c4647595c26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299083056 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.3299083056
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3624242336
Short name T422
Test name
Test status
Simulation time 142835739 ps
CPU time 3.31 seconds
Started Mar 03 02:45:59 PM PST 24
Finished Mar 03 02:46:02 PM PST 24
Peak memory 216584 kb
Host smart-f51487b0-5883-4d49-b70a-0b83d5f57d73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624242336 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3624242336
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_alert_test.428305155
Short name T491
Test name
Test status
Simulation time 14190837 ps
CPU time 0.92 seconds
Started Mar 03 02:46:04 PM PST 24
Finished Mar 03 02:46:05 PM PST 24
Peak memory 205364 kb
Host smart-4ea1d927-2dfd-499c-861f-157483330078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428305155 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.428305155
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.728924913
Short name T84
Test name
Test status
Simulation time 318411921 ps
CPU time 1.07 seconds
Started Mar 03 02:46:02 PM PST 24
Finished Mar 03 02:46:03 PM PST 24
Peak memory 215196 kb
Host smart-5da48d4e-9f12-4992-a059-345a608d291a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728924913 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_di
sable_auto_req_mode.728924913
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/43.edn_err.35262195
Short name T72
Test name
Test status
Simulation time 27584389 ps
CPU time 1.25 seconds
Started Mar 03 02:45:58 PM PST 24
Finished Mar 03 02:46:00 PM PST 24
Peak memory 215528 kb
Host smart-f7fe2a93-f6bd-40d1-b158-20fa2ca946ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35262195 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.35262195
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1948724293
Short name T179
Test name
Test status
Simulation time 40555257 ps
CPU time 1.15 seconds
Started Mar 03 02:46:05 PM PST 24
Finished Mar 03 02:46:06 PM PST 24
Peak memory 216552 kb
Host smart-2caf771a-d217-4437-b969-7981811e81e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948724293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1948724293
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.299489476
Short name T612
Test name
Test status
Simulation time 23642472 ps
CPU time 1.01 seconds
Started Mar 03 02:46:02 PM PST 24
Finished Mar 03 02:46:04 PM PST 24
Peak memory 214420 kb
Host smart-b9cf50f6-fc8a-4798-bca9-a9c80b63faaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299489476 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.299489476
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.3632543948
Short name T565
Test name
Test status
Simulation time 48121643 ps
CPU time 0.92 seconds
Started Mar 03 02:46:05 PM PST 24
Finished Mar 03 02:46:06 PM PST 24
Peak memory 214112 kb
Host smart-ed139459-6b93-42e8-bbc7-7f4c3d1ddb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632543948 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.3632543948
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2552826700
Short name T154
Test name
Test status
Simulation time 816676563 ps
CPU time 3.07 seconds
Started Mar 03 02:46:03 PM PST 24
Finished Mar 03 02:46:06 PM PST 24
Peak memory 215308 kb
Host smart-59943247-17a5-49df-82d0-22daba69c306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552826700 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2552826700
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.589886044
Short name T825
Test name
Test status
Simulation time 47242713153 ps
CPU time 652.03 seconds
Started Mar 03 02:45:59 PM PST 24
Finished Mar 03 02:56:51 PM PST 24
Peak memory 217676 kb
Host smart-a3f48771-02e2-4e92-bc11-81315f005c26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589886044 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.589886044
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2785658993
Short name T508
Test name
Test status
Simulation time 25161871 ps
CPU time 1.22 seconds
Started Mar 03 02:46:03 PM PST 24
Finished Mar 03 02:46:04 PM PST 24
Peak memory 214560 kb
Host smart-bf780bfa-1293-495c-b16d-b9bef8fe2b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785658993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2785658993
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.80052930
Short name T509
Test name
Test status
Simulation time 40530459 ps
CPU time 0.85 seconds
Started Mar 03 02:46:05 PM PST 24
Finished Mar 03 02:46:06 PM PST 24
Peak memory 205844 kb
Host smart-f432d3d4-e912-47d2-b122-625e4e1f6a68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80052930 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.80052930
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.1610433531
Short name T168
Test name
Test status
Simulation time 10740099 ps
CPU time 0.83 seconds
Started Mar 03 02:46:04 PM PST 24
Finished Mar 03 02:46:05 PM PST 24
Peak memory 214692 kb
Host smart-f776add9-7f22-40f5-9564-f9d58e859fe3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610433531 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.1610433531
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.327663573
Short name T8
Test name
Test status
Simulation time 29734869 ps
CPU time 1.1 seconds
Started Mar 03 02:46:05 PM PST 24
Finished Mar 03 02:46:06 PM PST 24
Peak memory 216656 kb
Host smart-90b9b7af-79d5-4aa6-a88a-70bdc8eedac9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327663573 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_di
sable_auto_req_mode.327663573
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.573668206
Short name T311
Test name
Test status
Simulation time 27241090 ps
CPU time 0.86 seconds
Started Mar 03 02:46:06 PM PST 24
Finished Mar 03 02:46:07 PM PST 24
Peak memory 216728 kb
Host smart-366109f4-99e2-4e97-bc16-a8bec54b3487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573668206 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.573668206
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3879680303
Short name T486
Test name
Test status
Simulation time 65090283 ps
CPU time 1.36 seconds
Started Mar 03 02:46:03 PM PST 24
Finished Mar 03 02:46:05 PM PST 24
Peak memory 216432 kb
Host smart-dd5c2f28-c8b0-4c3d-8bd8-da114436210c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879680303 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3879680303
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.2151420249
Short name T134
Test name
Test status
Simulation time 31238750 ps
CPU time 0.87 seconds
Started Mar 03 02:46:03 PM PST 24
Finished Mar 03 02:46:05 PM PST 24
Peak memory 214252 kb
Host smart-e06433b4-fd54-428e-a02c-23055e011bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151420249 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.2151420249
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.582914660
Short name T61
Test name
Test status
Simulation time 27675046 ps
CPU time 0.96 seconds
Started Mar 03 02:46:03 PM PST 24
Finished Mar 03 02:46:05 PM PST 24
Peak memory 214124 kb
Host smart-814d3151-26bc-4dc5-9e66-c437200e253c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582914660 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.582914660
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2991782327
Short name T695
Test name
Test status
Simulation time 462607347 ps
CPU time 2.85 seconds
Started Mar 03 02:46:02 PM PST 24
Finished Mar 03 02:46:05 PM PST 24
Peak memory 214116 kb
Host smart-17f9f0b2-66ca-4151-b944-3a7191fc8d60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991782327 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2991782327
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.2359015692
Short name T605
Test name
Test status
Simulation time 60477768454 ps
CPU time 805.25 seconds
Started Mar 03 02:46:05 PM PST 24
Finished Mar 03 02:59:31 PM PST 24
Peak memory 217968 kb
Host smart-1ce2b06e-2565-4b09-9734-a0dc8ecb2d4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359015692 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.2359015692
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.3996233642
Short name T570
Test name
Test status
Simulation time 24112593 ps
CPU time 1.2 seconds
Started Mar 03 02:46:11 PM PST 24
Finished Mar 03 02:46:12 PM PST 24
Peak memory 214576 kb
Host smart-f0cacb36-3abd-4e2d-b122-b437f004330f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996233642 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.3996233642
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.661054848
Short name T600
Test name
Test status
Simulation time 32554251 ps
CPU time 0.93 seconds
Started Mar 03 02:46:03 PM PST 24
Finished Mar 03 02:46:04 PM PST 24
Peak memory 205824 kb
Host smart-fa7140fd-2460-4b22-a52a-ad5a65ce87ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661054848 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.661054848
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.1242302528
Short name T710
Test name
Test status
Simulation time 117534590 ps
CPU time 0.86 seconds
Started Mar 03 02:46:05 PM PST 24
Finished Mar 03 02:46:06 PM PST 24
Peak memory 206124 kb
Host smart-5a6d6431-bbc8-4bbf-9650-58bf41fd342a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242302528 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1242302528
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_err.1763124134
Short name T728
Test name
Test status
Simulation time 31080697 ps
CPU time 0.9 seconds
Started Mar 03 02:46:04 PM PST 24
Finished Mar 03 02:46:05 PM PST 24
Peak memory 216692 kb
Host smart-ff0e41ed-b12b-4be8-b2d3-29e7ba1ab279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763124134 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.1763124134
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3553922888
Short name T353
Test name
Test status
Simulation time 32351089 ps
CPU time 1.29 seconds
Started Mar 03 02:46:03 PM PST 24
Finished Mar 03 02:46:05 PM PST 24
Peak memory 215584 kb
Host smart-ad25d52d-e853-43c1-b11d-25deadb335d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553922888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3553922888
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.87519610
Short name T29
Test name
Test status
Simulation time 22789762 ps
CPU time 1.02 seconds
Started Mar 03 02:46:05 PM PST 24
Finished Mar 03 02:46:06 PM PST 24
Peak memory 214172 kb
Host smart-0677362b-a66f-44c9-a7f5-98fd8b9f1dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87519610 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.87519610
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.3985829147
Short name T410
Test name
Test status
Simulation time 46665043 ps
CPU time 0.95 seconds
Started Mar 03 02:46:04 PM PST 24
Finished Mar 03 02:46:05 PM PST 24
Peak memory 214068 kb
Host smart-d0b6ef57-2e81-4b2d-9b1f-0c7e35b05f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985829147 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.3985829147
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.2882667511
Short name T711
Test name
Test status
Simulation time 1030514532 ps
CPU time 3.62 seconds
Started Mar 03 02:46:07 PM PST 24
Finished Mar 03 02:46:11 PM PST 24
Peak memory 215240 kb
Host smart-2c4c3b4b-42fb-44ec-8b04-c098bc259db9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882667511 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.2882667511
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.132382481
Short name T394
Test name
Test status
Simulation time 18502132200 ps
CPU time 416.05 seconds
Started Mar 03 02:46:04 PM PST 24
Finished Mar 03 02:53:00 PM PST 24
Peak memory 218268 kb
Host smart-f11543be-d3ab-4a08-ba30-1ede0398a182
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132382481 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.132382481
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.2408480870
Short name T229
Test name
Test status
Simulation time 32863070 ps
CPU time 1.32 seconds
Started Mar 03 02:46:03 PM PST 24
Finished Mar 03 02:46:05 PM PST 24
Peak memory 214576 kb
Host smart-c3575b51-fe35-4c2a-a4e6-dfc6b625f0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408480870 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.2408480870
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2457430859
Short name T385
Test name
Test status
Simulation time 16827077 ps
CPU time 0.92 seconds
Started Mar 03 02:46:05 PM PST 24
Finished Mar 03 02:46:06 PM PST 24
Peak memory 205048 kb
Host smart-73963944-25ca-41d7-8890-17235ccc5bce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457430859 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2457430859
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.3599764806
Short name T795
Test name
Test status
Simulation time 13410336 ps
CPU time 0.92 seconds
Started Mar 03 02:46:04 PM PST 24
Finished Mar 03 02:46:05 PM PST 24
Peak memory 214392 kb
Host smart-f34bcdfd-89a6-4d9a-941c-0d7dfff44173
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599764806 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.3599764806
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.1484794378
Short name T639
Test name
Test status
Simulation time 104863954 ps
CPU time 1.24 seconds
Started Mar 03 02:46:05 PM PST 24
Finished Mar 03 02:46:06 PM PST 24
Peak memory 215144 kb
Host smart-98fff0a6-59c7-4496-95a0-0a7872b15e51
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484794378 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.1484794378
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.37050207
Short name T361
Test name
Test status
Simulation time 19562041 ps
CPU time 0.96 seconds
Started Mar 03 02:46:05 PM PST 24
Finished Mar 03 02:46:07 PM PST 24
Peak memory 216860 kb
Host smart-9c03a7d3-2eb4-4be4-8ef6-15d005a4b09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37050207 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.37050207
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.205200929
Short name T239
Test name
Test status
Simulation time 29299294 ps
CPU time 1.33 seconds
Started Mar 03 02:46:04 PM PST 24
Finished Mar 03 02:46:06 PM PST 24
Peak memory 217968 kb
Host smart-ee22e7dc-603b-442c-8934-fcf8e3783240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205200929 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.205200929
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.3901843409
Short name T433
Test name
Test status
Simulation time 24562808 ps
CPU time 0.97 seconds
Started Mar 03 02:46:07 PM PST 24
Finished Mar 03 02:46:08 PM PST 24
Peak memory 214476 kb
Host smart-2cad81e7-1623-4b29-a9c8-a4bac22786bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901843409 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.3901843409
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3192945646
Short name T674
Test name
Test status
Simulation time 21522505 ps
CPU time 0.96 seconds
Started Mar 03 02:46:06 PM PST 24
Finished Mar 03 02:46:07 PM PST 24
Peak memory 214132 kb
Host smart-153ec210-fd8c-425d-bd45-d15d0a163c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192945646 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3192945646
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2162916542
Short name T470
Test name
Test status
Simulation time 459410658 ps
CPU time 2.23 seconds
Started Mar 03 02:46:04 PM PST 24
Finished Mar 03 02:46:06 PM PST 24
Peak memory 214088 kb
Host smart-fc7433a9-76dc-41f9-92b7-7a1b8cac1d80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162916542 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2162916542
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.693500565
Short name T188
Test name
Test status
Simulation time 31350183653 ps
CPU time 719.57 seconds
Started Mar 03 02:46:09 PM PST 24
Finished Mar 03 02:58:09 PM PST 24
Peak memory 222448 kb
Host smart-616c1ef8-a5f1-4d9a-a699-aa6f3f027ac0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693500565 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.693500565
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.4160657532
Short name T776
Test name
Test status
Simulation time 77321202 ps
CPU time 1.21 seconds
Started Mar 03 02:46:11 PM PST 24
Finished Mar 03 02:46:12 PM PST 24
Peak memory 214240 kb
Host smart-6808574f-a63d-4659-9159-d4772456c972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160657532 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.4160657532
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2795015548
Short name T568
Test name
Test status
Simulation time 55189652 ps
CPU time 0.97 seconds
Started Mar 03 02:46:09 PM PST 24
Finished Mar 03 02:46:10 PM PST 24
Peak memory 205820 kb
Host smart-2ecfb02c-1416-4f3d-93fa-abb1c62d99c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795015548 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2795015548
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.745307339
Short name T580
Test name
Test status
Simulation time 55698182 ps
CPU time 1.09 seconds
Started Mar 03 02:46:11 PM PST 24
Finished Mar 03 02:46:12 PM PST 24
Peak memory 215300 kb
Host smart-a8176240-24c4-4449-8375-c12cfdcc21a7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745307339 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_di
sable_auto_req_mode.745307339
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.4023818858
Short name T765
Test name
Test status
Simulation time 27581168 ps
CPU time 1.21 seconds
Started Mar 03 02:46:11 PM PST 24
Finished Mar 03 02:46:12 PM PST 24
Peak memory 214492 kb
Host smart-871cb112-7fae-4a87-8966-b8ba9ad5f6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023818858 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.4023818858
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3145047787
Short name T696
Test name
Test status
Simulation time 76507293 ps
CPU time 1.15 seconds
Started Mar 03 02:46:08 PM PST 24
Finished Mar 03 02:46:09 PM PST 24
Peak memory 215800 kb
Host smart-4083e8a5-8dc0-4488-b851-eee73682d67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145047787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3145047787
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.2840042964
Short name T403
Test name
Test status
Simulation time 28957440 ps
CPU time 1.09 seconds
Started Mar 03 02:46:09 PM PST 24
Finished Mar 03 02:46:10 PM PST 24
Peak memory 221936 kb
Host smart-b7aa9b7b-94fc-4469-9aba-ed5e3dd989d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840042964 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.2840042964
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.2934761795
Short name T485
Test name
Test status
Simulation time 45769081 ps
CPU time 0.87 seconds
Started Mar 03 02:46:08 PM PST 24
Finished Mar 03 02:46:09 PM PST 24
Peak memory 214120 kb
Host smart-411bcdc1-23f2-40e8-9c09-c65c0645ac2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934761795 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.2934761795
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.3911325381
Short name T593
Test name
Test status
Simulation time 360680405 ps
CPU time 2.37 seconds
Started Mar 03 02:46:13 PM PST 24
Finished Mar 03 02:46:15 PM PST 24
Peak memory 214060 kb
Host smart-e8eb168b-70b9-4b35-b5f4-97e7d789b915
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911325381 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.3911325381
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2274219026
Short name T191
Test name
Test status
Simulation time 93900382059 ps
CPU time 2096.03 seconds
Started Mar 03 02:46:09 PM PST 24
Finished Mar 03 03:21:05 PM PST 24
Peak memory 224424 kb
Host smart-9b21c865-6010-457d-935f-c7a25e6d09b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274219026 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2274219026
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1239918889
Short name T149
Test name
Test status
Simulation time 30536435 ps
CPU time 1.33 seconds
Started Mar 03 02:46:10 PM PST 24
Finished Mar 03 02:46:12 PM PST 24
Peak memory 214596 kb
Host smart-a168a97b-fa29-4eed-84c4-ed24fc9f1c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239918889 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1239918889
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.3304283067
Short name T471
Test name
Test status
Simulation time 266561351 ps
CPU time 1.08 seconds
Started Mar 03 02:46:12 PM PST 24
Finished Mar 03 02:46:13 PM PST 24
Peak memory 205500 kb
Host smart-9072df60-7c52-41a2-861d-d27d5fa03040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304283067 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.3304283067
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.1821619621
Short name T93
Test name
Test status
Simulation time 359349109 ps
CPU time 1.07 seconds
Started Mar 03 02:46:11 PM PST 24
Finished Mar 03 02:46:12 PM PST 24
Peak memory 215060 kb
Host smart-cdc95021-72d5-464b-833a-37d07782d28b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821619621 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.1821619621
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3699593306
Short name T248
Test name
Test status
Simulation time 24310904 ps
CPU time 0.99 seconds
Started Mar 03 02:46:13 PM PST 24
Finished Mar 03 02:46:14 PM PST 24
Peak memory 214560 kb
Host smart-0b44bb75-a967-430f-aad3-06fefc820250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699593306 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3699593306
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3553877838
Short name T86
Test name
Test status
Simulation time 148714508 ps
CPU time 1.56 seconds
Started Mar 03 02:46:13 PM PST 24
Finished Mar 03 02:46:15 PM PST 24
Peak memory 215472 kb
Host smart-d5b94012-72ce-451d-b402-e4fde8070c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553877838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3553877838
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.2187722245
Short name T449
Test name
Test status
Simulation time 22826585 ps
CPU time 0.97 seconds
Started Mar 03 02:46:10 PM PST 24
Finished Mar 03 02:46:12 PM PST 24
Peak memory 214480 kb
Host smart-8b9f2584-ebae-48c5-9f67-53d07a199511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187722245 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.2187722245
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.2166508832
Short name T718
Test name
Test status
Simulation time 41541715 ps
CPU time 0.97 seconds
Started Mar 03 02:46:11 PM PST 24
Finished Mar 03 02:46:12 PM PST 24
Peak memory 213816 kb
Host smart-22af8cbc-be78-4d4e-882d-fdfadb0275ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166508832 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.2166508832
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2383567958
Short name T362
Test name
Test status
Simulation time 264308135 ps
CPU time 5.12 seconds
Started Mar 03 02:46:10 PM PST 24
Finished Mar 03 02:46:15 PM PST 24
Peak memory 214204 kb
Host smart-809c161d-db04-4b7d-87c3-7a063a41072a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383567958 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2383567958
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.3912944000
Short name T538
Test name
Test status
Simulation time 57346789811 ps
CPU time 1331.97 seconds
Started Mar 03 02:46:13 PM PST 24
Finished Mar 03 03:08:25 PM PST 24
Peak memory 220068 kb
Host smart-974c5efe-e125-4000-9d02-c125bdc8c304
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912944000 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.3912944000
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.3671180452
Short name T787
Test name
Test status
Simulation time 25373981 ps
CPU time 1.17 seconds
Started Mar 03 02:46:13 PM PST 24
Finished Mar 03 02:46:15 PM PST 24
Peak memory 214564 kb
Host smart-81e81917-5487-4378-9867-6674c17e9a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671180452 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.3671180452
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1266350116
Short name T714
Test name
Test status
Simulation time 13917584 ps
CPU time 0.9 seconds
Started Mar 03 02:46:14 PM PST 24
Finished Mar 03 02:46:15 PM PST 24
Peak memory 205408 kb
Host smart-b0a2458f-7148-4fcb-889d-e048bc0abba5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266350116 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1266350116
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.1389790462
Short name T156
Test name
Test status
Simulation time 74736884 ps
CPU time 0.83 seconds
Started Mar 03 02:46:14 PM PST 24
Finished Mar 03 02:46:15 PM PST 24
Peak memory 214628 kb
Host smart-18304b69-ef4f-4a52-abd8-5567037f360f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389790462 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.1389790462
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_disable_auto_req_mode.3297624891
Short name T328
Test name
Test status
Simulation time 428852797 ps
CPU time 1 seconds
Started Mar 03 02:46:15 PM PST 24
Finished Mar 03 02:46:16 PM PST 24
Peak memory 215200 kb
Host smart-88d3c8a8-8bc9-411b-b567-370f9af7ca45
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297624891 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_d
isable_auto_req_mode.3297624891
Directory /workspace/49.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/49.edn_err.487337301
Short name T120
Test name
Test status
Simulation time 33417057 ps
CPU time 0.88 seconds
Started Mar 03 02:46:13 PM PST 24
Finished Mar 03 02:46:14 PM PST 24
Peak memory 216676 kb
Host smart-602269ee-e52f-447e-aab0-c6f9564544ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487337301 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.487337301
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3775908952
Short name T64
Test name
Test status
Simulation time 48280048 ps
CPU time 1.7 seconds
Started Mar 03 02:46:12 PM PST 24
Finished Mar 03 02:46:14 PM PST 24
Peak memory 216584 kb
Host smart-90ec848c-cff7-44fe-b281-dd43f034fbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775908952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3775908952
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.4179039654
Short name T399
Test name
Test status
Simulation time 24019948 ps
CPU time 1.01 seconds
Started Mar 03 02:46:15 PM PST 24
Finished Mar 03 02:46:16 PM PST 24
Peak memory 214256 kb
Host smart-f1431f2d-d06a-490f-b446-23e9b1d96fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179039654 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.4179039654
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.223371104
Short name T456
Test name
Test status
Simulation time 31802430 ps
CPU time 1 seconds
Started Mar 03 02:46:12 PM PST 24
Finished Mar 03 02:46:13 PM PST 24
Peak memory 214104 kb
Host smart-542ba975-62c1-4e84-85d2-c37dd0af8d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223371104 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.223371104
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.4053496139
Short name T181
Test name
Test status
Simulation time 126651125 ps
CPU time 0.95 seconds
Started Mar 03 02:46:14 PM PST 24
Finished Mar 03 02:46:15 PM PST 24
Peak memory 204536 kb
Host smart-0806741d-c060-467d-b479-e6f3399247c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053496139 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.4053496139
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.708126165
Short name T279
Test name
Test status
Simulation time 3271968951 ps
CPU time 71.17 seconds
Started Mar 03 02:46:19 PM PST 24
Finished Mar 03 02:47:31 PM PST 24
Peak memory 216536 kb
Host smart-cf8eb6de-bdbf-47f1-8ec5-c039c7023705
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708126165 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.708126165
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1509763299
Short name T74
Test name
Test status
Simulation time 85420034 ps
CPU time 1.25 seconds
Started Mar 03 02:44:41 PM PST 24
Finished Mar 03 02:44:42 PM PST 24
Peak memory 214572 kb
Host smart-e2880e29-05a5-4ea6-a4d7-627e48de9702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509763299 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1509763299
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.67995162
Short name T372
Test name
Test status
Simulation time 63674718 ps
CPU time 0.97 seconds
Started Mar 03 02:44:42 PM PST 24
Finished Mar 03 02:44:43 PM PST 24
Peak memory 205792 kb
Host smart-6907231f-5560-4ac5-9507-3595de59762e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67995162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.67995162
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.2184513542
Short name T505
Test name
Test status
Simulation time 43174477 ps
CPU time 0.83 seconds
Started Mar 03 02:44:42 PM PST 24
Finished Mar 03 02:44:43 PM PST 24
Peak memory 214788 kb
Host smart-187a716c-4e8a-40c2-9e84-58f0f9ac09c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184513542 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.2184513542
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_err.3319890525
Short name T830
Test name
Test status
Simulation time 19956848 ps
CPU time 1.08 seconds
Started Mar 03 02:44:42 PM PST 24
Finished Mar 03 02:44:43 PM PST 24
Peak memory 216692 kb
Host smart-ce9f03c8-c9d5-476a-a2f0-7078ce9b324a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319890525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3319890525
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.2694884943
Short name T412
Test name
Test status
Simulation time 35522630 ps
CPU time 1.41 seconds
Started Mar 03 02:44:41 PM PST 24
Finished Mar 03 02:44:43 PM PST 24
Peak memory 216348 kb
Host smart-5cdfe235-3197-4b38-95f8-df347b3f83be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694884943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.2694884943
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.585292353
Short name T792
Test name
Test status
Simulation time 31505827 ps
CPU time 0.92 seconds
Started Mar 03 02:44:42 PM PST 24
Finished Mar 03 02:44:43 PM PST 24
Peak memory 214492 kb
Host smart-88f16927-0b36-4b97-9df7-90cf8574fdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585292353 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.585292353
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.3619975276
Short name T595
Test name
Test status
Simulation time 17958817 ps
CPU time 1.03 seconds
Started Mar 03 02:44:40 PM PST 24
Finished Mar 03 02:44:41 PM PST 24
Peak memory 205912 kb
Host smart-3cf72d1e-4f20-4fd0-90c8-03f19ecc1711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619975276 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.3619975276
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.963663342
Short name T349
Test name
Test status
Simulation time 38718408 ps
CPU time 0.87 seconds
Started Mar 03 02:44:46 PM PST 24
Finished Mar 03 02:44:47 PM PST 24
Peak memory 214104 kb
Host smart-c57e3ed1-54a7-4c49-9d7a-2259e5521dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963663342 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.963663342
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.109840548
Short name T649
Test name
Test status
Simulation time 524408590 ps
CPU time 4.93 seconds
Started Mar 03 02:44:43 PM PST 24
Finished Mar 03 02:44:48 PM PST 24
Peak memory 214044 kb
Host smart-72b37507-dd9a-4bab-951f-280616588455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109840548 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.109840548
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1925580273
Short name T608
Test name
Test status
Simulation time 626098682027 ps
CPU time 1004.59 seconds
Started Mar 03 02:44:39 PM PST 24
Finished Mar 03 03:01:24 PM PST 24
Peak memory 219760 kb
Host smart-a263534f-7926-44d3-b93d-2fc732d99f3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925580273 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1925580273
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.1625397117
Short name T113
Test name
Test status
Simulation time 20960205 ps
CPU time 1.14 seconds
Started Mar 03 02:46:15 PM PST 24
Finished Mar 03 02:46:16 PM PST 24
Peak memory 221988 kb
Host smart-3a427c37-99fd-4c01-847f-28930f53e963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625397117 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1625397117
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.678168720
Short name T351
Test name
Test status
Simulation time 91411913 ps
CPU time 1.14 seconds
Started Mar 03 02:46:16 PM PST 24
Finished Mar 03 02:46:17 PM PST 24
Peak memory 215296 kb
Host smart-c539ce50-c001-4095-9f25-b1eb5a4f50fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678168720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.678168720
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.4200302104
Short name T159
Test name
Test status
Simulation time 93117279 ps
CPU time 1.09 seconds
Started Mar 03 02:46:14 PM PST 24
Finished Mar 03 02:46:15 PM PST 24
Peak memory 218108 kb
Host smart-eeff71b9-bff1-425f-9acd-da96250d3c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200302104 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.4200302104
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1359640225
Short name T768
Test name
Test status
Simulation time 40649209 ps
CPU time 1.83 seconds
Started Mar 03 02:46:13 PM PST 24
Finished Mar 03 02:46:15 PM PST 24
Peak memory 216624 kb
Host smart-841472d6-a0c5-4521-ba9d-cd99036f4c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359640225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1359640225
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.238741375
Short name T34
Test name
Test status
Simulation time 25492043 ps
CPU time 0.81 seconds
Started Mar 03 02:46:17 PM PST 24
Finished Mar 03 02:46:18 PM PST 24
Peak memory 216684 kb
Host smart-da2a670f-6f81-4c07-8dd1-f81211a939d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238741375 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.238741375
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1950999877
Short name T541
Test name
Test status
Simulation time 110571871 ps
CPU time 1.23 seconds
Started Mar 03 02:46:19 PM PST 24
Finished Mar 03 02:46:20 PM PST 24
Peak memory 215560 kb
Host smart-87d8aa72-f749-4159-bd3a-ddab2a63f03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950999877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1950999877
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.3945211031
Short name T781
Test name
Test status
Simulation time 29924524 ps
CPU time 1.26 seconds
Started Mar 03 02:46:14 PM PST 24
Finished Mar 03 02:46:15 PM PST 24
Peak memory 217996 kb
Host smart-703c022e-4443-43fb-afe4-d715cea659e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945211031 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.3945211031
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.3449864500
Short name T434
Test name
Test status
Simulation time 82069031 ps
CPU time 1.2 seconds
Started Mar 03 02:46:18 PM PST 24
Finished Mar 03 02:46:19 PM PST 24
Peak memory 215364 kb
Host smart-d3bcbdc0-27eb-4051-a1c7-4f6ba7b3c120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449864500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.3449864500
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.816435719
Short name T97
Test name
Test status
Simulation time 22440134 ps
CPU time 1.06 seconds
Started Mar 03 02:46:15 PM PST 24
Finished Mar 03 02:46:17 PM PST 24
Peak memory 230144 kb
Host smart-c8a8a66a-fb24-4aac-9149-9c8b0015d8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816435719 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.816435719
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.3480588869
Short name T763
Test name
Test status
Simulation time 46671925 ps
CPU time 1.87 seconds
Started Mar 03 02:46:16 PM PST 24
Finished Mar 03 02:46:17 PM PST 24
Peak memory 216356 kb
Host smart-d2f0009d-98f7-459b-a261-1bf66d2e55b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480588869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.3480588869
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.2916711580
Short name T6
Test name
Test status
Simulation time 32826235 ps
CPU time 1.36 seconds
Started Mar 03 02:46:14 PM PST 24
Finished Mar 03 02:46:16 PM PST 24
Peak memory 218168 kb
Host smart-e13a54e0-6668-477f-bde7-83ed712dfbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916711580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2916711580
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3341023325
Short name T312
Test name
Test status
Simulation time 45219124 ps
CPU time 1.37 seconds
Started Mar 03 02:46:14 PM PST 24
Finished Mar 03 02:46:16 PM PST 24
Peak memory 216628 kb
Host smart-52c47b4b-0994-49e6-9288-393413c08e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341023325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3341023325
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.3679756328
Short name T699
Test name
Test status
Simulation time 32100039 ps
CPU time 1.23 seconds
Started Mar 03 02:46:16 PM PST 24
Finished Mar 03 02:46:17 PM PST 24
Peak memory 230060 kb
Host smart-4a0bf77b-a05f-47c2-a58b-92be0700000a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679756328 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.3679756328
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.4153521829
Short name T744
Test name
Test status
Simulation time 82608654 ps
CPU time 1.39 seconds
Started Mar 03 02:46:16 PM PST 24
Finished Mar 03 02:46:18 PM PST 24
Peak memory 216632 kb
Host smart-0e4d8c37-d0a1-4e62-911d-1a0085754338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153521829 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.4153521829
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.617983305
Short name T160
Test name
Test status
Simulation time 36783895 ps
CPU time 1.3 seconds
Started Mar 03 02:46:14 PM PST 24
Finished Mar 03 02:46:15 PM PST 24
Peak memory 218196 kb
Host smart-dcd6569e-e95c-4f75-ae67-d1f5501cd3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617983305 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.617983305
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3768413705
Short name T448
Test name
Test status
Simulation time 108337571 ps
CPU time 1.75 seconds
Started Mar 03 02:46:15 PM PST 24
Finished Mar 03 02:46:17 PM PST 24
Peak memory 216812 kb
Host smart-99c685d5-a760-47d3-aaa4-19833e24ab04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768413705 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3768413705
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.1646289760
Short name T76
Test name
Test status
Simulation time 42345851 ps
CPU time 1.06 seconds
Started Mar 03 02:46:19 PM PST 24
Finished Mar 03 02:46:20 PM PST 24
Peak memory 218092 kb
Host smart-ddf4ee79-0850-4347-8c93-585c939c452f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646289760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.1646289760
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1391813714
Short name T628
Test name
Test status
Simulation time 55520581 ps
CPU time 1.38 seconds
Started Mar 03 02:46:12 PM PST 24
Finished Mar 03 02:46:14 PM PST 24
Peak memory 216452 kb
Host smart-3efb8aa2-bd7e-4f75-90f6-096e10696029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391813714 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1391813714
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.3929055178
Short name T746
Test name
Test status
Simulation time 25263056 ps
CPU time 0.86 seconds
Started Mar 03 02:46:19 PM PST 24
Finished Mar 03 02:46:20 PM PST 24
Peak memory 216612 kb
Host smart-bcc6a154-1359-4b3c-935b-515236310c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929055178 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3929055178
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.111401132
Short name T575
Test name
Test status
Simulation time 55991242 ps
CPU time 1.5 seconds
Started Mar 03 02:46:18 PM PST 24
Finished Mar 03 02:46:19 PM PST 24
Peak memory 216884 kb
Host smart-eb2f82d2-b21c-4d51-ad03-61df1716f323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111401132 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.111401132
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.3321846175
Short name T147
Test name
Test status
Simulation time 89973519 ps
CPU time 1.3 seconds
Started Mar 03 02:44:46 PM PST 24
Finished Mar 03 02:44:48 PM PST 24
Peak memory 214572 kb
Host smart-5832c352-daaa-41ec-98da-20c46c7beea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321846175 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.3321846175
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.2934441504
Short name T747
Test name
Test status
Simulation time 26714538 ps
CPU time 0.95 seconds
Started Mar 03 02:44:48 PM PST 24
Finished Mar 03 02:44:50 PM PST 24
Peak memory 205452 kb
Host smart-4be58b90-c3ef-4e97-878b-0ebe39f9d36f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934441504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.2934441504
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.2948886975
Short name T174
Test name
Test status
Simulation time 11297822 ps
CPU time 0.87 seconds
Started Mar 03 02:44:47 PM PST 24
Finished Mar 03 02:44:48 PM PST 24
Peak memory 214252 kb
Host smart-16455e1e-a311-4c48-acff-6f3bb4651f47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948886975 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.2948886975
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.548313956
Short name T95
Test name
Test status
Simulation time 106943151 ps
CPU time 1.1 seconds
Started Mar 03 02:44:47 PM PST 24
Finished Mar 03 02:44:48 PM PST 24
Peak memory 215352 kb
Host smart-23ef4056-e58d-4bcd-bf30-cce1dc773510
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548313956 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_dis
able_auto_req_mode.548313956
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.2024403147
Short name T730
Test name
Test status
Simulation time 52105965 ps
CPU time 1.03 seconds
Started Mar 03 02:44:47 PM PST 24
Finished Mar 03 02:44:48 PM PST 24
Peak memory 219216 kb
Host smart-ef89c121-e6af-49d9-93ae-d41c11f64552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024403147 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.2024403147
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.3125118225
Short name T365
Test name
Test status
Simulation time 37209317 ps
CPU time 1.61 seconds
Started Mar 03 02:44:46 PM PST 24
Finished Mar 03 02:44:48 PM PST 24
Peak memory 215604 kb
Host smart-06a07d9e-154a-402f-8324-21aceb64d949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125118225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.3125118225
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.1951789015
Short name T821
Test name
Test status
Simulation time 47438686 ps
CPU time 1.01 seconds
Started Mar 03 02:44:46 PM PST 24
Finished Mar 03 02:44:47 PM PST 24
Peak memory 231312 kb
Host smart-13dee6fc-14c7-470d-a9bd-0250dbf32953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951789015 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.1951789015
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.3032913966
Short name T640
Test name
Test status
Simulation time 38483877 ps
CPU time 0.89 seconds
Started Mar 03 02:44:46 PM PST 24
Finished Mar 03 02:44:47 PM PST 24
Peak memory 214084 kb
Host smart-da161a42-a2e8-4bab-9596-e892c9fd8e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032913966 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3032913966
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1911520747
Short name T454
Test name
Test status
Simulation time 73699435 ps
CPU time 1.39 seconds
Started Mar 03 02:44:50 PM PST 24
Finished Mar 03 02:44:52 PM PST 24
Peak memory 215176 kb
Host smart-a7fcc3c0-b420-4e8a-8ad0-67b4eb2a246a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911520747 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1911520747
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.1736335495
Short name T482
Test name
Test status
Simulation time 713611523134 ps
CPU time 3008.55 seconds
Started Mar 03 02:44:46 PM PST 24
Finished Mar 03 03:34:55 PM PST 24
Peak memory 232280 kb
Host smart-ebe382bf-16f6-468e-80e8-9ebdd8a10d04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736335495 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.1736335495
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_genbits.2132893093
Short name T688
Test name
Test status
Simulation time 33452748 ps
CPU time 1.33 seconds
Started Mar 03 02:46:16 PM PST 24
Finished Mar 03 02:46:17 PM PST 24
Peak memory 215260 kb
Host smart-68f1a972-b5d0-4189-aee9-d3c6a144f4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132893093 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.2132893093
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.3957987119
Short name T82
Test name
Test status
Simulation time 32893541 ps
CPU time 1.18 seconds
Started Mar 03 02:46:16 PM PST 24
Finished Mar 03 02:46:18 PM PST 24
Peak memory 228348 kb
Host smart-60d440a6-601e-44cd-9202-a519728b9dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957987119 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3957987119
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2833610194
Short name T27
Test name
Test status
Simulation time 49676157 ps
CPU time 1.19 seconds
Started Mar 03 02:46:16 PM PST 24
Finished Mar 03 02:46:17 PM PST 24
Peak memory 215440 kb
Host smart-c7c84300-fc43-4dcc-9964-fb76a8f182d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833610194 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2833610194
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.3190272639
Short name T677
Test name
Test status
Simulation time 80479373 ps
CPU time 0.83 seconds
Started Mar 03 02:46:15 PM PST 24
Finished Mar 03 02:46:16 PM PST 24
Peak memory 216756 kb
Host smart-8ad5d2b5-52e3-4af6-9c3e-60a87ba324f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190272639 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3190272639
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.3433746460
Short name T296
Test name
Test status
Simulation time 45022976 ps
CPU time 1.38 seconds
Started Mar 03 02:46:18 PM PST 24
Finished Mar 03 02:46:19 PM PST 24
Peak memory 218080 kb
Host smart-b52d6e80-edc5-420b-bb9d-f8d8cda704e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433746460 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.3433746460
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.790019206
Short name T224
Test name
Test status
Simulation time 19011678 ps
CPU time 0.96 seconds
Started Mar 03 02:46:18 PM PST 24
Finished Mar 03 02:46:19 PM PST 24
Peak memory 216932 kb
Host smart-db9a6eac-9b04-49fd-87f1-c10ef72ed6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790019206 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.790019206
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.7790089
Short name T268
Test name
Test status
Simulation time 35148508 ps
CPU time 1.57 seconds
Started Mar 03 02:46:14 PM PST 24
Finished Mar 03 02:46:16 PM PST 24
Peak memory 216816 kb
Host smart-cf51b1b2-fdf5-4f85-9622-88bcac9fb8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7790089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.7790089
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.860735756
Short name T413
Test name
Test status
Simulation time 18258324 ps
CPU time 1.03 seconds
Started Mar 03 02:46:13 PM PST 24
Finished Mar 03 02:46:14 PM PST 24
Peak memory 217016 kb
Host smart-09a00633-cf55-4780-aefc-234a9f6dcb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860735756 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.860735756
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3420893710
Short name T576
Test name
Test status
Simulation time 67689590 ps
CPU time 1.09 seconds
Started Mar 03 02:46:16 PM PST 24
Finished Mar 03 02:46:17 PM PST 24
Peak memory 215428 kb
Host smart-4121cd4b-bbe9-4cea-9278-7e8b2a6a5024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420893710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3420893710
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.3968945954
Short name T114
Test name
Test status
Simulation time 37772457 ps
CPU time 0.96 seconds
Started Mar 03 02:46:13 PM PST 24
Finished Mar 03 02:46:14 PM PST 24
Peak memory 221724 kb
Host smart-1ba37ddb-7afe-4841-b53d-e705f686ce23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968945954 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.3968945954
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.1863223425
Short name T467
Test name
Test status
Simulation time 125244731 ps
CPU time 1.22 seconds
Started Mar 03 02:46:19 PM PST 24
Finished Mar 03 02:46:20 PM PST 24
Peak memory 215268 kb
Host smart-d89236e7-51aa-450e-b33b-cb57bdd2ddaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863223425 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.1863223425
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.3116156179
Short name T617
Test name
Test status
Simulation time 23592251 ps
CPU time 1.03 seconds
Started Mar 03 02:46:15 PM PST 24
Finished Mar 03 02:46:16 PM PST 24
Peak memory 221936 kb
Host smart-9b31db36-dd3d-4c36-b521-cd4ec2f2e1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116156179 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.3116156179
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3621650143
Short name T288
Test name
Test status
Simulation time 86654136 ps
CPU time 1.46 seconds
Started Mar 03 02:46:18 PM PST 24
Finished Mar 03 02:46:19 PM PST 24
Peak memory 216896 kb
Host smart-9cbd9fd1-8345-4da7-bdc5-2a68f390e76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621650143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3621650143
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.4052427636
Short name T489
Test name
Test status
Simulation time 18165412 ps
CPU time 1.09 seconds
Started Mar 03 02:46:19 PM PST 24
Finished Mar 03 02:46:20 PM PST 24
Peak memory 216656 kb
Host smart-7739bbbb-6cfa-4a60-8e1d-6118888ac74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052427636 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.4052427636
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1935744804
Short name T721
Test name
Test status
Simulation time 44751370 ps
CPU time 1.44 seconds
Started Mar 03 02:46:20 PM PST 24
Finished Mar 03 02:46:22 PM PST 24
Peak memory 216320 kb
Host smart-cf5f77f2-72b4-45f6-a7ef-f0cefd7af00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935744804 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1935744804
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.4087114785
Short name T778
Test name
Test status
Simulation time 29350826 ps
CPU time 1.18 seconds
Started Mar 03 02:46:24 PM PST 24
Finished Mar 03 02:46:25 PM PST 24
Peak memory 218104 kb
Host smart-683dc7c0-057f-465e-87ee-7d716386c37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087114785 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.4087114785
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2746770554
Short name T777
Test name
Test status
Simulation time 333057197 ps
CPU time 3.73 seconds
Started Mar 03 02:46:20 PM PST 24
Finished Mar 03 02:46:24 PM PST 24
Peak memory 215444 kb
Host smart-fee648da-5f95-42f7-95cb-b3c4c84a1327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746770554 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2746770554
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.2190935364
Short name T78
Test name
Test status
Simulation time 24815777 ps
CPU time 1 seconds
Started Mar 03 02:46:20 PM PST 24
Finished Mar 03 02:46:21 PM PST 24
Peak memory 217968 kb
Host smart-deedde41-b249-416e-9c44-70e244352091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190935364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2190935364
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.3443462414
Short name T726
Test name
Test status
Simulation time 44376221 ps
CPU time 1.66 seconds
Started Mar 03 02:46:20 PM PST 24
Finished Mar 03 02:46:21 PM PST 24
Peak memory 218104 kb
Host smart-ef332148-269c-492b-ba7f-597760ff26d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443462414 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3443462414
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1613456978
Short name T772
Test name
Test status
Simulation time 29335260 ps
CPU time 1.26 seconds
Started Mar 03 02:44:48 PM PST 24
Finished Mar 03 02:44:49 PM PST 24
Peak memory 214556 kb
Host smart-62814773-74dd-4343-a2b4-aa8e8b8a06ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613456978 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1613456978
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1086293868
Short name T355
Test name
Test status
Simulation time 26095964 ps
CPU time 0.93 seconds
Started Mar 03 02:44:48 PM PST 24
Finished Mar 03 02:44:49 PM PST 24
Peak memory 205824 kb
Host smart-55ff3021-3109-4311-bc19-d6396740aa7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086293868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1086293868
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_err.1021598818
Short name T553
Test name
Test status
Simulation time 28562288 ps
CPU time 0.96 seconds
Started Mar 03 02:44:48 PM PST 24
Finished Mar 03 02:44:49 PM PST 24
Peak memory 221780 kb
Host smart-0e878473-b250-4858-a8c3-880170f4d5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021598818 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.1021598818
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2030126091
Short name T701
Test name
Test status
Simulation time 21451384 ps
CPU time 1.13 seconds
Started Mar 03 02:44:47 PM PST 24
Finished Mar 03 02:44:48 PM PST 24
Peak memory 216568 kb
Host smart-08fed5c5-407a-47d1-99a6-fed1ae1e0297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030126091 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2030126091
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1681107937
Short name T135
Test name
Test status
Simulation time 29515546 ps
CPU time 0.83 seconds
Started Mar 03 02:44:47 PM PST 24
Finished Mar 03 02:44:48 PM PST 24
Peak memory 214308 kb
Host smart-70d52669-f9a4-4b88-b0c6-6d30b185345a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681107937 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1681107937
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.1510436279
Short name T261
Test name
Test status
Simulation time 28595241 ps
CPU time 0.89 seconds
Started Mar 03 02:44:48 PM PST 24
Finished Mar 03 02:44:49 PM PST 24
Peak memory 205908 kb
Host smart-b326bf8d-49cd-4312-8ea2-7cc2fa4e8835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510436279 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.1510436279
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1378802335
Short name T487
Test name
Test status
Simulation time 14951651 ps
CPU time 0.94 seconds
Started Mar 03 02:44:48 PM PST 24
Finished Mar 03 02:44:49 PM PST 24
Peak memory 214088 kb
Host smart-26cbdd0f-8c8e-45b6-86de-7d15571f9d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378802335 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1378802335
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.2539907595
Short name T262
Test name
Test status
Simulation time 141998864 ps
CPU time 2.2 seconds
Started Mar 03 02:44:52 PM PST 24
Finished Mar 03 02:44:54 PM PST 24
Peak memory 215252 kb
Host smart-2e86b209-c7cb-46af-a42f-4633fb913a5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539907595 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.2539907595
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.271387670
Short name T589
Test name
Test status
Simulation time 45665485286 ps
CPU time 607.04 seconds
Started Mar 03 02:44:48 PM PST 24
Finished Mar 03 02:54:55 PM PST 24
Peak memory 222428 kb
Host smart-91943725-d277-456b-a236-c6e2e188e735
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271387670 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.271387670
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.3883813012
Short name T645
Test name
Test status
Simulation time 28839109 ps
CPU time 1.4 seconds
Started Mar 03 02:46:19 PM PST 24
Finished Mar 03 02:46:20 PM PST 24
Peak memory 222972 kb
Host smart-bdde870b-8be1-4ff1-8c66-c341f301793d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883813012 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.3883813012
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.3837634919
Short name T309
Test name
Test status
Simulation time 38476753 ps
CPU time 1.34 seconds
Started Mar 03 02:46:21 PM PST 24
Finished Mar 03 02:46:22 PM PST 24
Peak memory 216528 kb
Host smart-71d652b5-d8cd-47ee-b4ef-1fdada5a2307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837634919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.3837634919
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.3843145723
Short name T83
Test name
Test status
Simulation time 24842754 ps
CPU time 1.27 seconds
Started Mar 03 02:46:20 PM PST 24
Finished Mar 03 02:46:22 PM PST 24
Peak memory 228620 kb
Host smart-3a23a1c9-7bea-4ff3-adba-fe63edbbad10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843145723 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3843145723
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1147824855
Short name T828
Test name
Test status
Simulation time 68090982 ps
CPU time 1.17 seconds
Started Mar 03 02:46:21 PM PST 24
Finished Mar 03 02:46:22 PM PST 24
Peak memory 214048 kb
Host smart-8f0ebd3f-9e3a-418c-b10e-b10697872895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147824855 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1147824855
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.211733484
Short name T796
Test name
Test status
Simulation time 32170663 ps
CPU time 1.09 seconds
Started Mar 03 02:46:21 PM PST 24
Finished Mar 03 02:46:23 PM PST 24
Peak memory 217072 kb
Host smart-3e477478-9998-459c-9b9d-95dbfa657824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211733484 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.211733484
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1088856563
Short name T658
Test name
Test status
Simulation time 51925445 ps
CPU time 1.22 seconds
Started Mar 03 02:46:18 PM PST 24
Finished Mar 03 02:46:19 PM PST 24
Peak memory 215280 kb
Host smart-ba1d683f-5669-4f11-bf10-d1ed4df21a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088856563 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1088856563
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.94585846
Short name T330
Test name
Test status
Simulation time 18213058 ps
CPU time 1.02 seconds
Started Mar 03 02:46:19 PM PST 24
Finished Mar 03 02:46:21 PM PST 24
Peak memory 216748 kb
Host smart-e446b8e8-54bd-42b7-bafe-bd563dbf540e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94585846 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.94585846
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2063522473
Short name T546
Test name
Test status
Simulation time 59075545 ps
CPU time 2.1 seconds
Started Mar 03 02:46:20 PM PST 24
Finished Mar 03 02:46:22 PM PST 24
Peak memory 216848 kb
Host smart-0983e61e-ee11-4a95-b5a0-e260c6210a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063522473 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2063522473
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.166128545
Short name T614
Test name
Test status
Simulation time 27959855 ps
CPU time 0.87 seconds
Started Mar 03 02:46:22 PM PST 24
Finished Mar 03 02:46:23 PM PST 24
Peak memory 216372 kb
Host smart-3149e070-b9fb-4600-9666-f2338f2c7e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166128545 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.166128545
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.2765478877
Short name T376
Test name
Test status
Simulation time 195307082 ps
CPU time 1.1 seconds
Started Mar 03 02:46:21 PM PST 24
Finished Mar 03 02:46:22 PM PST 24
Peak memory 215300 kb
Host smart-0f113cc7-2d3e-48ad-835c-049818190797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765478877 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.2765478877
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.3676339967
Short name T230
Test name
Test status
Simulation time 19595529 ps
CPU time 1.11 seconds
Started Mar 03 02:46:20 PM PST 24
Finished Mar 03 02:46:21 PM PST 24
Peak memory 216776 kb
Host smart-ea42a88c-a086-4861-9a88-541af2f84a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676339967 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3676339967
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1191317
Short name T678
Test name
Test status
Simulation time 63501848 ps
CPU time 1.64 seconds
Started Mar 03 02:46:21 PM PST 24
Finished Mar 03 02:46:22 PM PST 24
Peak memory 216668 kb
Host smart-9891fa61-63c9-4fe6-9621-6feb04bc59e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191317 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1191317
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.2299455402
Short name T557
Test name
Test status
Simulation time 17950695 ps
CPU time 1.08 seconds
Started Mar 03 02:46:18 PM PST 24
Finished Mar 03 02:46:20 PM PST 24
Peak memory 216840 kb
Host smart-27e851bd-e361-41b1-9d0e-91fb8ae8d66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299455402 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.2299455402
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.3085392520
Short name T58
Test name
Test status
Simulation time 70449381 ps
CPU time 1.06 seconds
Started Mar 03 02:46:19 PM PST 24
Finished Mar 03 02:46:20 PM PST 24
Peak memory 215204 kb
Host smart-fe68e99e-c830-4503-806e-87cd99b6a3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085392520 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.3085392520
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.1565367304
Short name T656
Test name
Test status
Simulation time 29715330 ps
CPU time 0.89 seconds
Started Mar 03 02:46:28 PM PST 24
Finished Mar 03 02:46:29 PM PST 24
Peak memory 216428 kb
Host smart-383155bf-7fb7-441f-8d0f-86cd94084132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565367304 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.1565367304
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.458129281
Short name T326
Test name
Test status
Simulation time 50676651 ps
CPU time 1.3 seconds
Started Mar 03 02:46:21 PM PST 24
Finished Mar 03 02:46:22 PM PST 24
Peak memory 216720 kb
Host smart-0abdbd53-00ca-428e-abe8-fd75f0dcd84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458129281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.458129281
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.2057415548
Short name T620
Test name
Test status
Simulation time 24158673 ps
CPU time 1.18 seconds
Started Mar 03 02:46:23 PM PST 24
Finished Mar 03 02:46:24 PM PST 24
Peak memory 215736 kb
Host smart-d68b29dc-6383-4a71-806e-ad25022259ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057415548 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2057415548
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.2978534895
Short name T806
Test name
Test status
Simulation time 52951643 ps
CPU time 1.92 seconds
Started Mar 03 02:46:24 PM PST 24
Finished Mar 03 02:46:26 PM PST 24
Peak memory 216740 kb
Host smart-672e663f-7278-4757-9fb6-794076e5b91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978534895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.2978534895
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.3326020934
Short name T373
Test name
Test status
Simulation time 21272130 ps
CPU time 0.87 seconds
Started Mar 03 02:46:25 PM PST 24
Finished Mar 03 02:46:26 PM PST 24
Peak memory 216452 kb
Host smart-723148e2-a8fc-41c8-be34-deea0ca6946d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326020934 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3326020934
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/8.edn_alert.1923578895
Short name T227
Test name
Test status
Simulation time 89773550 ps
CPU time 1.22 seconds
Started Mar 03 02:44:55 PM PST 24
Finished Mar 03 02:44:56 PM PST 24
Peak memory 214580 kb
Host smart-baf4d498-64cb-4fad-b46e-daba059b09c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923578895 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.1923578895
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3022677576
Short name T802
Test name
Test status
Simulation time 53784013 ps
CPU time 0.96 seconds
Started Mar 03 02:44:56 PM PST 24
Finished Mar 03 02:44:57 PM PST 24
Peak memory 205816 kb
Host smart-527d7856-a2d5-4f28-9985-c2026c0b853d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022677576 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3022677576
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.3131371870
Short name T116
Test name
Test status
Simulation time 39510046 ps
CPU time 0.91 seconds
Started Mar 03 02:44:53 PM PST 24
Finished Mar 03 02:44:54 PM PST 24
Peak memory 214724 kb
Host smart-e817f0d4-7e58-467d-94ac-441847a46f31
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131371870 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.3131371870
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_err.1066811876
Short name T588
Test name
Test status
Simulation time 20432303 ps
CPU time 1 seconds
Started Mar 03 02:44:52 PM PST 24
Finished Mar 03 02:44:53 PM PST 24
Peak memory 216644 kb
Host smart-6edf208d-3ff4-4a5e-84d1-b672bad4e69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066811876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.1066811876
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.3834036369
Short name T682
Test name
Test status
Simulation time 105715275 ps
CPU time 1.11 seconds
Started Mar 03 02:44:46 PM PST 24
Finished Mar 03 02:44:47 PM PST 24
Peak memory 215464 kb
Host smart-4f4ff053-e23d-486d-9e47-07bb30b84123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834036369 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.3834036369
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1537580546
Short name T492
Test name
Test status
Simulation time 22448580 ps
CPU time 0.99 seconds
Started Mar 03 02:44:47 PM PST 24
Finished Mar 03 02:44:48 PM PST 24
Peak memory 214304 kb
Host smart-829f2a93-8600-4a8a-9717-6e6e34dc9765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537580546 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1537580546
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.2238836333
Short name T259
Test name
Test status
Simulation time 17618158 ps
CPU time 0.99 seconds
Started Mar 03 02:44:48 PM PST 24
Finished Mar 03 02:44:49 PM PST 24
Peak memory 205908 kb
Host smart-2dd1450d-5948-4872-ae65-e1250b16ad77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238836333 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.2238836333
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.414582753
Short name T788
Test name
Test status
Simulation time 177621477 ps
CPU time 0.92 seconds
Started Mar 03 02:44:47 PM PST 24
Finished Mar 03 02:44:48 PM PST 24
Peak memory 214108 kb
Host smart-f47a2ae7-c1e6-43a6-bf25-3afcdb4ac00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414582753 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.414582753
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.486405363
Short name T542
Test name
Test status
Simulation time 435312235 ps
CPU time 2.89 seconds
Started Mar 03 02:44:47 PM PST 24
Finished Mar 03 02:44:50 PM PST 24
Peak memory 215168 kb
Host smart-e5cbd380-f3e2-4e05-880d-dac1bacb2ba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486405363 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.486405363
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.4091634962
Short name T301
Test name
Test status
Simulation time 22081070257 ps
CPU time 590.2 seconds
Started Mar 03 02:44:47 PM PST 24
Finished Mar 03 02:54:37 PM PST 24
Peak memory 215916 kb
Host smart-1db84745-a664-4469-b5cb-2c1a9b7c52c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091634962 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.4091634962
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.2335639205
Short name T517
Test name
Test status
Simulation time 24640358 ps
CPU time 0.92 seconds
Started Mar 03 02:46:26 PM PST 24
Finished Mar 03 02:46:27 PM PST 24
Peak memory 216836 kb
Host smart-0563af78-e50c-4db4-bdcc-ac4c08b3d51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335639205 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2335639205
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3284359679
Short name T178
Test name
Test status
Simulation time 60123778 ps
CPU time 1.72 seconds
Started Mar 03 02:46:26 PM PST 24
Finished Mar 03 02:46:28 PM PST 24
Peak memory 216572 kb
Host smart-f5cdf1f7-6ed3-470c-914f-eceefc299d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284359679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3284359679
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.1185204456
Short name T87
Test name
Test status
Simulation time 31495045 ps
CPU time 1.21 seconds
Started Mar 03 02:46:30 PM PST 24
Finished Mar 03 02:46:31 PM PST 24
Peak memory 228464 kb
Host smart-c9ecaa26-756b-491d-9f01-bccabe4fe514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185204456 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1185204456
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.1435559795
Short name T533
Test name
Test status
Simulation time 64863125 ps
CPU time 1.04 seconds
Started Mar 03 02:46:28 PM PST 24
Finished Mar 03 02:46:29 PM PST 24
Peak memory 215300 kb
Host smart-2d02bb57-f322-4676-b7c0-f60ec97791ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435559795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.1435559795
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.2928921024
Short name T73
Test name
Test status
Simulation time 40016876 ps
CPU time 1.07 seconds
Started Mar 03 02:46:25 PM PST 24
Finished Mar 03 02:46:26 PM PST 24
Peak memory 215564 kb
Host smart-bebf1d01-9c9c-4f0a-a42d-38b7b49501b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928921024 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.2928921024
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3453633927
Short name T759
Test name
Test status
Simulation time 93497143 ps
CPU time 1.52 seconds
Started Mar 03 02:46:23 PM PST 24
Finished Mar 03 02:46:25 PM PST 24
Peak memory 216932 kb
Host smart-f1e80cc4-241a-4fb2-8b45-c6c03c04ccba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453633927 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3453633927
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.3185608043
Short name T733
Test name
Test status
Simulation time 18979252 ps
CPU time 1.06 seconds
Started Mar 03 02:46:23 PM PST 24
Finished Mar 03 02:46:25 PM PST 24
Peak memory 216724 kb
Host smart-cdd0fce4-508a-4749-94ae-21e23cfc0272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185608043 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.3185608043
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2140323592
Short name T484
Test name
Test status
Simulation time 128970732 ps
CPU time 1.66 seconds
Started Mar 03 02:46:26 PM PST 24
Finished Mar 03 02:46:27 PM PST 24
Peak memory 217336 kb
Host smart-f3fb8e0d-51cd-4f10-95e2-7328735f40cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140323592 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2140323592
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.2930436052
Short name T607
Test name
Test status
Simulation time 42673109 ps
CPU time 1.2 seconds
Started Mar 03 02:46:27 PM PST 24
Finished Mar 03 02:46:29 PM PST 24
Peak memory 231144 kb
Host smart-35e1ecc1-e9cc-4f20-be89-0d16b356cb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930436052 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2930436052
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1087313753
Short name T396
Test name
Test status
Simulation time 47532897 ps
CPU time 1.88 seconds
Started Mar 03 02:46:24 PM PST 24
Finished Mar 03 02:46:26 PM PST 24
Peak memory 215580 kb
Host smart-97639f6a-94bb-424c-88b4-913a1f077175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087313753 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1087313753
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.3084290177
Short name T596
Test name
Test status
Simulation time 103956789 ps
CPU time 0.95 seconds
Started Mar 03 02:46:25 PM PST 24
Finished Mar 03 02:46:26 PM PST 24
Peak memory 229912 kb
Host smart-33a96e62-67af-4a59-ad6a-b6485761c8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084290177 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.3084290177
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1049833168
Short name T731
Test name
Test status
Simulation time 50098041 ps
CPU time 2.08 seconds
Started Mar 03 02:46:28 PM PST 24
Finished Mar 03 02:46:30 PM PST 24
Peak memory 215648 kb
Host smart-23143524-679e-4d88-8b41-da7613962330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049833168 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1049833168
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.1760376607
Short name T429
Test name
Test status
Simulation time 27486565 ps
CPU time 0.95 seconds
Started Mar 03 02:46:24 PM PST 24
Finished Mar 03 02:46:25 PM PST 24
Peak memory 221640 kb
Host smart-33f69099-7638-475a-910c-121a3b6c470b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760376607 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.1760376607
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3421152495
Short name T520
Test name
Test status
Simulation time 44547383 ps
CPU time 1.41 seconds
Started Mar 03 02:46:29 PM PST 24
Finished Mar 03 02:46:30 PM PST 24
Peak memory 216800 kb
Host smart-7b15b858-6467-4484-b534-c02528e51ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421152495 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3421152495
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1678776531
Short name T101
Test name
Test status
Simulation time 27676190 ps
CPU time 0.98 seconds
Started Mar 03 02:46:24 PM PST 24
Finished Mar 03 02:46:25 PM PST 24
Peak memory 229916 kb
Host smart-ecc02dd5-1a65-40a2-89f3-b26b079dfc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678776531 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1678776531
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.2415758641
Short name T294
Test name
Test status
Simulation time 66897209 ps
CPU time 2.41 seconds
Started Mar 03 02:46:26 PM PST 24
Finished Mar 03 02:46:29 PM PST 24
Peak memory 216688 kb
Host smart-f7806135-afe8-46e1-a232-989bd087e3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415758641 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.2415758641
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.2862544326
Short name T118
Test name
Test status
Simulation time 27747149 ps
CPU time 0.98 seconds
Started Mar 03 02:46:23 PM PST 24
Finished Mar 03 02:46:24 PM PST 24
Peak memory 221716 kb
Host smart-71213f74-4695-4f3a-a944-76e8cb79132f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862544326 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2862544326
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3885806688
Short name T226
Test name
Test status
Simulation time 63820668 ps
CPU time 1.61 seconds
Started Mar 03 02:46:28 PM PST 24
Finished Mar 03 02:46:30 PM PST 24
Peak memory 217028 kb
Host smart-de7afd16-7a4a-4284-b79e-8873f67233e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885806688 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3885806688
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.1605540888
Short name T395
Test name
Test status
Simulation time 45207456 ps
CPU time 1.13 seconds
Started Mar 03 02:46:25 PM PST 24
Finished Mar 03 02:46:26 PM PST 24
Peak memory 218080 kb
Host smart-c1217bc3-0914-4401-bda4-5a978256bb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605540888 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1605540888
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2067535098
Short name T31
Test name
Test status
Simulation time 42599545 ps
CPU time 1.84 seconds
Started Mar 03 02:46:25 PM PST 24
Finished Mar 03 02:46:27 PM PST 24
Peak memory 216744 kb
Host smart-3b87b958-26cf-4da7-b74e-6e15df790b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067535098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2067535098
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.224139327
Short name T691
Test name
Test status
Simulation time 27418905 ps
CPU time 1.25 seconds
Started Mar 03 02:44:56 PM PST 24
Finished Mar 03 02:44:58 PM PST 24
Peak memory 214616 kb
Host smart-0f8a6e23-fdad-4435-89fa-b636682a47fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224139327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.224139327
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.18108724
Short name T49
Test name
Test status
Simulation time 49096758 ps
CPU time 0.87 seconds
Started Mar 03 02:44:53 PM PST 24
Finished Mar 03 02:44:54 PM PST 24
Peak memory 205828 kb
Host smart-d321c584-2ffe-4bf6-8896-ce3be3a91864
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18108724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.18108724
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1861462049
Short name T185
Test name
Test status
Simulation time 20138099 ps
CPU time 0.85 seconds
Started Mar 03 02:44:53 PM PST 24
Finished Mar 03 02:44:54 PM PST 24
Peak memory 214344 kb
Host smart-abd1b6e9-87b1-4e7a-8f92-16913ce9ed8e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861462049 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1861462049
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_genbits.2386170923
Short name T629
Test name
Test status
Simulation time 32319584 ps
CPU time 1.52 seconds
Started Mar 03 02:44:57 PM PST 24
Finished Mar 03 02:44:59 PM PST 24
Peak memory 216464 kb
Host smart-673ff190-be6c-4fe1-8003-76081a59e3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386170923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.2386170923
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2386968616
Short name T53
Test name
Test status
Simulation time 20520157 ps
CPU time 1.16 seconds
Started Mar 03 02:44:54 PM PST 24
Finished Mar 03 02:44:55 PM PST 24
Peak memory 221952 kb
Host smart-135533a4-6be1-4f4f-8088-9551af3b13c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386968616 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2386968616
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2432640068
Short name T641
Test name
Test status
Simulation time 42209610 ps
CPU time 0.89 seconds
Started Mar 03 02:44:54 PM PST 24
Finished Mar 03 02:44:55 PM PST 24
Peak memory 205904 kb
Host smart-9bb8d756-ae2d-4820-9628-a0866905f43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432640068 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2432640068
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1603140148
Short name T425
Test name
Test status
Simulation time 18380795 ps
CPU time 1 seconds
Started Mar 03 02:44:53 PM PST 24
Finished Mar 03 02:44:54 PM PST 24
Peak memory 214104 kb
Host smart-944f2ad7-a3b2-40f8-9f7c-16ceb152e179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603140148 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1603140148
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.1514363039
Short name T21
Test name
Test status
Simulation time 666786953 ps
CPU time 4.08 seconds
Started Mar 03 02:44:53 PM PST 24
Finished Mar 03 02:44:57 PM PST 24
Peak memory 217840 kb
Host smart-06b296d9-ae40-40fc-bd49-08feea1e9f42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514363039 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.1514363039
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.327930517
Short name T144
Test name
Test status
Simulation time 30348785018 ps
CPU time 517.22 seconds
Started Mar 03 02:44:53 PM PST 24
Finished Mar 03 02:53:30 PM PST 24
Peak memory 215292 kb
Host smart-279f3a4e-2f31-4767-90fd-cf1ed8b3e3b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327930517 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.327930517
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.3599996068
Short name T547
Test name
Test status
Simulation time 23141751 ps
CPU time 1.13 seconds
Started Mar 03 02:46:25 PM PST 24
Finished Mar 03 02:46:26 PM PST 24
Peak memory 230148 kb
Host smart-612d2985-405a-4c63-bdf4-693fa02252cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599996068 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3599996068
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3747253412
Short name T42
Test name
Test status
Simulation time 81162878 ps
CPU time 1.61 seconds
Started Mar 03 02:46:24 PM PST 24
Finished Mar 03 02:46:26 PM PST 24
Peak memory 216504 kb
Host smart-522973b6-be58-4744-998c-abe02d2fce96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747253412 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3747253412
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.3274358274
Short name T169
Test name
Test status
Simulation time 35792288 ps
CPU time 0.85 seconds
Started Mar 03 02:46:26 PM PST 24
Finished Mar 03 02:46:27 PM PST 24
Peak memory 216908 kb
Host smart-585dc949-0597-4e70-8b1b-91c4c0eb5230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274358274 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3274358274
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.4255823122
Short name T238
Test name
Test status
Simulation time 212754585 ps
CPU time 1.17 seconds
Started Mar 03 02:46:27 PM PST 24
Finished Mar 03 02:46:28 PM PST 24
Peak memory 214192 kb
Host smart-e3d6f87a-24cc-44b9-afc8-b8a5b8f06517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255823122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.4255823122
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.712565301
Short name T7
Test name
Test status
Simulation time 28073205 ps
CPU time 1.04 seconds
Started Mar 03 02:46:25 PM PST 24
Finished Mar 03 02:46:26 PM PST 24
Peak memory 215576 kb
Host smart-f9b433d2-f985-4548-95a3-9f270bc4e4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712565301 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.712565301
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.688071183
Short name T416
Test name
Test status
Simulation time 29166584 ps
CPU time 1.29 seconds
Started Mar 03 02:46:29 PM PST 24
Finished Mar 03 02:46:31 PM PST 24
Peak memory 216400 kb
Host smart-ba7c03d5-eb58-45e3-9681-dd3dc86dd19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688071183 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.688071183
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.2988961858
Short name T90
Test name
Test status
Simulation time 38871331 ps
CPU time 1.15 seconds
Started Mar 03 02:46:28 PM PST 24
Finished Mar 03 02:46:29 PM PST 24
Peak memory 218936 kb
Host smart-a7f02959-fd34-47b8-9798-533b1446ad2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988961858 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2988961858
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2000202015
Short name T626
Test name
Test status
Simulation time 52550390 ps
CPU time 1.8 seconds
Started Mar 03 02:46:29 PM PST 24
Finished Mar 03 02:46:31 PM PST 24
Peak memory 217280 kb
Host smart-2ca0247e-aef4-4781-86fb-b0acaa00ba36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000202015 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2000202015
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.3019180688
Short name T2
Test name
Test status
Simulation time 29770348 ps
CPU time 0.85 seconds
Started Mar 03 02:46:22 PM PST 24
Finished Mar 03 02:46:23 PM PST 24
Peak memory 216560 kb
Host smart-8f1b748d-e1ff-4f34-a0c8-32fc1246815f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019180688 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.3019180688
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1845590971
Short name T560
Test name
Test status
Simulation time 92187452 ps
CPU time 1.19 seconds
Started Mar 03 02:46:24 PM PST 24
Finished Mar 03 02:46:25 PM PST 24
Peak memory 215264 kb
Host smart-2bb65965-4e04-4371-a3fb-4e75c5ac3dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845590971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1845590971
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.2546028497
Short name T3
Test name
Test status
Simulation time 49535394 ps
CPU time 0.9 seconds
Started Mar 03 02:46:26 PM PST 24
Finished Mar 03 02:46:27 PM PST 24
Peak memory 221804 kb
Host smart-2431ec6e-ab57-4dab-9347-8462e247c721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546028497 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.2546028497
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1097641284
Short name T642
Test name
Test status
Simulation time 67804794 ps
CPU time 1.22 seconds
Started Mar 03 02:46:26 PM PST 24
Finished Mar 03 02:46:28 PM PST 24
Peak memory 216724 kb
Host smart-2b8f408e-411f-4481-9386-8b426e4a3181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097641284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1097641284
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3375499253
Short name T408
Test name
Test status
Simulation time 30377302 ps
CPU time 0.84 seconds
Started Mar 03 02:46:27 PM PST 24
Finished Mar 03 02:46:28 PM PST 24
Peak memory 216836 kb
Host smart-419722d0-31d4-48a3-85ae-826970a6ab45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375499253 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3375499253
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.1654798209
Short name T447
Test name
Test status
Simulation time 58382491 ps
CPU time 1.46 seconds
Started Mar 03 02:46:27 PM PST 24
Finished Mar 03 02:46:29 PM PST 24
Peak memory 217660 kb
Host smart-17451336-8464-4f12-b5d5-db85722b32e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654798209 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.1654798209
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.2374278798
Short name T323
Test name
Test status
Simulation time 28529623 ps
CPU time 0.89 seconds
Started Mar 03 02:46:28 PM PST 24
Finished Mar 03 02:46:29 PM PST 24
Peak memory 216496 kb
Host smart-a37eaec5-bc3a-479a-b4d8-a9c30cd0cc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374278798 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.2374278798
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3865380606
Short name T306
Test name
Test status
Simulation time 70780372 ps
CPU time 2.56 seconds
Started Mar 03 02:46:27 PM PST 24
Finished Mar 03 02:46:30 PM PST 24
Peak memory 215688 kb
Host smart-9dade545-4536-4c90-a4a0-756b1b6e7398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865380606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3865380606
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1916818009
Short name T69
Test name
Test status
Simulation time 21714328 ps
CPU time 0.92 seconds
Started Mar 03 02:46:28 PM PST 24
Finished Mar 03 02:46:29 PM PST 24
Peak memory 216900 kb
Host smart-86146452-3c9f-45d6-aea5-ba24ab8265b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916818009 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1916818009
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.4246367529
Short name T180
Test name
Test status
Simulation time 37423031 ps
CPU time 1.36 seconds
Started Mar 03 02:46:27 PM PST 24
Finished Mar 03 02:46:29 PM PST 24
Peak memory 216388 kb
Host smart-b1527a89-c152-485e-9073-a45f91d59204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246367529 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.4246367529
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.3249042770
Short name T108
Test name
Test status
Simulation time 29885382 ps
CPU time 0.87 seconds
Started Mar 03 02:46:34 PM PST 24
Finished Mar 03 02:46:35 PM PST 24
Peak memory 216692 kb
Host smart-0eca8ac5-7334-49ea-bede-f3366c252c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249042770 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.3249042770
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.3082518376
Short name T782
Test name
Test status
Simulation time 35226473 ps
CPU time 1.33 seconds
Started Mar 03 02:46:31 PM PST 24
Finished Mar 03 02:46:32 PM PST 24
Peak memory 216452 kb
Host smart-db6d1492-9bb4-4a25-9306-4d0820aeda04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082518376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.3082518376
Directory /workspace/99.edn_genbits/latest
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