Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	2	0	2	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_intr

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

7873

1

T5

120

T6

8

T37

35

all_values[1]

7873

1

T5

120

T6

8

T37

35

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8079

1

T5

117

T6

9

T37

38

auto[1]

7667

1

T5

123

T6

7

T37

32

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6175

1

T5

92

T6

10

T37

34

auto[1]

9571

1

T5

148

T6

6

T37

36

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9265

1

T5

141

T6

12

T37

46

auto[1]

6481

1

T5

99

T6

4

T37

24

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	12	0	12	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

1650

1

T5

20

T6

2

T37

12

all_values[0]

auto[0]

auto[0]

auto[1]

779

1

T5

13

T6

1

T37

1

all_values[0]

auto[0]

auto[1]

auto[0]

1464

1

T5

25

T6

3

T37

7

all_values[0]

auto[0]

auto[1]

auto[1]

769

1

T5

9

T37

4

T23

23

all_values[0]

auto[1]

auto[0]

auto[1]

1639

1

T5

25

T37

5

T23

38

all_values[0]

auto[1]

auto[1]

auto[1]

1572

1

T5

28

T6

2

T37

6

all_values[1]

auto[0]

auto[0]

auto[0]

1548

1

T5

25

T6

4

T37

10

all_values[1]

auto[0]

auto[0]

auto[1]

775

1

T5

12

T6

1

T37

4

all_values[1]

auto[0]

auto[1]

auto[0]

1513

1

T5

22

T6

1

T37

5

all_values[1]

auto[0]

auto[1]

auto[1]

767

1

T5

15

T37

3

T23

19

all_values[1]

auto[1]

auto[0]

auto[1]

1688

1

T5

22

T6

1

T37

6

all_values[1]

auto[1]

auto[1]

auto[1]

1582

1

T5

24

T6

1

T37

7

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal