Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.94 98.27 93.63 96.79 82.08 96.87 96.58 93.35


Total test records in report: 970
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T788 /workspace/coverage/default/235.edn_genbits.1304162094 Mar 05 01:51:08 PM PST 24 Mar 05 01:51:10 PM PST 24 34880854 ps
T789 /workspace/coverage/default/26.edn_disable_auto_req_mode.1621853607 Mar 05 01:49:50 PM PST 24 Mar 05 01:49:51 PM PST 24 118532741 ps
T790 /workspace/coverage/default/7.edn_alert_test.1932910810 Mar 05 01:49:32 PM PST 24 Mar 05 01:49:33 PM PST 24 23269342 ps
T791 /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3925503188 Mar 05 01:49:51 PM PST 24 Mar 05 01:58:45 PM PST 24 126283296881 ps
T792 /workspace/coverage/default/269.edn_genbits.4107124175 Mar 05 01:51:07 PM PST 24 Mar 05 01:51:09 PM PST 24 36100879 ps
T793 /workspace/coverage/default/18.edn_intr.2355325363 Mar 05 01:49:48 PM PST 24 Mar 05 01:49:50 PM PST 24 23328505 ps
T794 /workspace/coverage/default/277.edn_genbits.3660942755 Mar 05 01:50:56 PM PST 24 Mar 05 01:50:58 PM PST 24 156768199 ps
T795 /workspace/coverage/default/170.edn_genbits.4290349543 Mar 05 01:50:42 PM PST 24 Mar 05 01:50:49 PM PST 24 137910274 ps
T796 /workspace/coverage/default/81.edn_err.1010494542 Mar 05 01:50:44 PM PST 24 Mar 05 01:50:48 PM PST 24 25095896 ps
T797 /workspace/coverage/default/160.edn_genbits.2600589307 Mar 05 01:50:45 PM PST 24 Mar 05 01:50:50 PM PST 24 57548908 ps
T798 /workspace/coverage/default/215.edn_genbits.3829070130 Mar 05 01:51:14 PM PST 24 Mar 05 01:51:15 PM PST 24 37959721 ps
T799 /workspace/coverage/default/248.edn_genbits.375823058 Mar 05 01:51:04 PM PST 24 Mar 05 01:51:06 PM PST 24 100585467 ps
T800 /workspace/coverage/default/131.edn_genbits.1494372452 Mar 05 01:50:41 PM PST 24 Mar 05 01:50:46 PM PST 24 41675815 ps
T801 /workspace/coverage/default/7.edn_stress_all.1586996834 Mar 05 01:49:13 PM PST 24 Mar 05 01:49:20 PM PST 24 950878197 ps
T802 /workspace/coverage/default/111.edn_genbits.2558432691 Mar 05 01:50:44 PM PST 24 Mar 05 01:50:48 PM PST 24 94582695 ps
T803 /workspace/coverage/default/117.edn_genbits.1339294268 Mar 05 01:50:51 PM PST 24 Mar 05 01:50:53 PM PST 24 55557829 ps
T804 /workspace/coverage/default/263.edn_genbits.3074949620 Mar 05 01:51:05 PM PST 24 Mar 05 01:51:07 PM PST 24 77683266 ps
T805 /workspace/coverage/default/4.edn_err.3820990268 Mar 05 01:49:07 PM PST 24 Mar 05 01:49:09 PM PST 24 25283465 ps
T806 /workspace/coverage/default/28.edn_genbits.1204217457 Mar 05 01:49:47 PM PST 24 Mar 05 01:49:49 PM PST 24 83969823 ps
T807 /workspace/coverage/default/48.edn_genbits.3844553659 Mar 05 01:50:08 PM PST 24 Mar 05 01:50:11 PM PST 24 57101963 ps
T808 /workspace/coverage/default/102.edn_genbits.180704961 Mar 05 01:50:40 PM PST 24 Mar 05 01:50:41 PM PST 24 58955775 ps
T255 /workspace/coverage/default/0.edn_alert.3279043185 Mar 05 01:49:06 PM PST 24 Mar 05 01:49:07 PM PST 24 50936175 ps
T809 /workspace/coverage/default/201.edn_genbits.3190707537 Mar 05 01:50:45 PM PST 24 Mar 05 01:50:51 PM PST 24 54611229 ps
T810 /workspace/coverage/default/4.edn_disable.2950207779 Mar 05 01:49:15 PM PST 24 Mar 05 01:49:17 PM PST 24 13969399 ps
T127 /workspace/coverage/default/40.edn_intr.738153297 Mar 05 01:50:05 PM PST 24 Mar 05 01:50:07 PM PST 24 21693322 ps
T811 /workspace/coverage/default/23.edn_genbits.2615771935 Mar 05 01:49:51 PM PST 24 Mar 05 01:49:52 PM PST 24 39797631 ps
T812 /workspace/coverage/default/86.edn_err.2048522092 Mar 05 01:50:26 PM PST 24 Mar 05 01:50:28 PM PST 24 37105137 ps
T813 /workspace/coverage/default/33.edn_smoke.292027818 Mar 05 01:49:50 PM PST 24 Mar 05 01:49:51 PM PST 24 40863121 ps
T814 /workspace/coverage/default/272.edn_genbits.1581971253 Mar 05 01:50:58 PM PST 24 Mar 05 01:50:59 PM PST 24 38101607 ps
T815 /workspace/coverage/default/88.edn_genbits.1292122236 Mar 05 01:50:34 PM PST 24 Mar 05 01:50:36 PM PST 24 66431330 ps
T816 /workspace/coverage/default/132.edn_genbits.3559686606 Mar 05 01:50:33 PM PST 24 Mar 05 01:50:34 PM PST 24 46807855 ps
T817 /workspace/coverage/default/14.edn_stress_all_with_rand_reset.73880189 Mar 05 01:49:27 PM PST 24 Mar 05 01:53:14 PM PST 24 94113507175 ps
T818 /workspace/coverage/default/0.edn_genbits.1859670334 Mar 05 01:48:58 PM PST 24 Mar 05 01:49:00 PM PST 24 28820743 ps
T819 /workspace/coverage/default/251.edn_genbits.95992059 Mar 05 01:50:43 PM PST 24 Mar 05 01:50:48 PM PST 24 47788849 ps
T820 /workspace/coverage/default/185.edn_genbits.490675890 Mar 05 01:50:44 PM PST 24 Mar 05 01:50:51 PM PST 24 134511615 ps
T821 /workspace/coverage/default/1.edn_disable_auto_req_mode.3638929728 Mar 05 01:49:07 PM PST 24 Mar 05 01:49:09 PM PST 24 39830227 ps
T822 /workspace/coverage/default/44.edn_smoke.1240408636 Mar 05 01:50:03 PM PST 24 Mar 05 01:50:04 PM PST 24 25469119 ps
T49 /workspace/coverage/default/4.edn_sec_cm.40942413 Mar 05 01:49:03 PM PST 24 Mar 05 01:49:08 PM PST 24 709387286 ps
T823 /workspace/coverage/default/247.edn_genbits.490522991 Mar 05 01:50:55 PM PST 24 Mar 05 01:51:02 PM PST 24 963991825 ps
T824 /workspace/coverage/default/31.edn_err.1813000944 Mar 05 01:49:58 PM PST 24 Mar 05 01:49:59 PM PST 24 33430186 ps
T825 /workspace/coverage/default/16.edn_smoke.1714970541 Mar 05 01:49:36 PM PST 24 Mar 05 01:49:37 PM PST 24 17161030 ps
T826 /workspace/coverage/default/52.edn_err.2395975586 Mar 05 01:50:34 PM PST 24 Mar 05 01:50:40 PM PST 24 42637808 ps
T827 /workspace/coverage/default/80.edn_err.2247340408 Mar 05 01:50:39 PM PST 24 Mar 05 01:50:41 PM PST 24 54029720 ps
T828 /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1239634626 Mar 05 01:50:03 PM PST 24 Mar 05 02:02:27 PM PST 24 60503305129 ps
T829 /workspace/coverage/default/183.edn_genbits.4193190955 Mar 05 01:50:41 PM PST 24 Mar 05 01:50:47 PM PST 24 33787420 ps
T830 /workspace/coverage/default/229.edn_genbits.3709539000 Mar 05 01:51:00 PM PST 24 Mar 05 01:51:02 PM PST 24 80554447 ps
T831 /workspace/coverage/default/3.edn_err.2179530783 Mar 05 01:49:11 PM PST 24 Mar 05 01:49:12 PM PST 24 29365231 ps
T832 /workspace/coverage/default/9.edn_genbits.4065731148 Mar 05 01:49:26 PM PST 24 Mar 05 01:49:28 PM PST 24 64236111 ps
T833 /workspace/coverage/default/11.edn_stress_all.4136444115 Mar 05 01:49:32 PM PST 24 Mar 05 01:49:40 PM PST 24 376215105 ps
T834 /workspace/coverage/default/85.edn_genbits.414684580 Mar 05 01:50:30 PM PST 24 Mar 05 01:50:32 PM PST 24 58497299 ps
T109 /workspace/coverage/default/10.edn_err.2648651950 Mar 05 01:49:33 PM PST 24 Mar 05 01:49:34 PM PST 24 18567821 ps
T835 /workspace/coverage/default/34.edn_disable.976778581 Mar 05 01:50:09 PM PST 24 Mar 05 01:50:10 PM PST 24 24598099 ps
T165 /workspace/coverage/default/47.edn_disable_auto_req_mode.3049666876 Mar 05 01:50:19 PM PST 24 Mar 05 01:50:21 PM PST 24 61252697 ps
T836 /workspace/coverage/default/167.edn_genbits.3301187108 Mar 05 01:50:56 PM PST 24 Mar 05 01:50:57 PM PST 24 245391170 ps
T837 /workspace/coverage/default/166.edn_genbits.2079531452 Mar 05 01:50:57 PM PST 24 Mar 05 01:50:58 PM PST 24 87710743 ps
T838 /workspace/coverage/cover_reg_top/41.edn_intr_test.413872139 Mar 05 12:44:18 PM PST 24 Mar 05 12:44:19 PM PST 24 25869250 ps
T238 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3476191886 Mar 05 12:44:00 PM PST 24 Mar 05 12:44:02 PM PST 24 428575443 ps
T211 /workspace/coverage/cover_reg_top/5.edn_csr_rw.3907401767 Mar 05 12:43:46 PM PST 24 Mar 05 12:43:47 PM PST 24 21869955 ps
T839 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2927412715 Mar 05 12:43:58 PM PST 24 Mar 05 12:43:59 PM PST 24 26110605 ps
T840 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1342344152 Mar 05 12:43:58 PM PST 24 Mar 05 12:44:05 PM PST 24 77685274 ps
T841 /workspace/coverage/cover_reg_top/45.edn_intr_test.1744619721 Mar 05 12:44:01 PM PST 24 Mar 05 12:44:02 PM PST 24 103570590 ps
T239 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4103232934 Mar 05 12:44:00 PM PST 24 Mar 05 12:44:02 PM PST 24 696773159 ps
T842 /workspace/coverage/cover_reg_top/12.edn_tl_errors.3134880092 Mar 05 12:43:48 PM PST 24 Mar 05 12:43:52 PM PST 24 105256363 ps
T843 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2022936447 Mar 05 12:43:56 PM PST 24 Mar 05 12:43:57 PM PST 24 50797783 ps
T240 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1810508475 Mar 05 12:43:53 PM PST 24 Mar 05 12:43:56 PM PST 24 101308638 ps
T844 /workspace/coverage/cover_reg_top/39.edn_intr_test.251417794 Mar 05 12:44:15 PM PST 24 Mar 05 12:44:16 PM PST 24 30909691 ps
T212 /workspace/coverage/cover_reg_top/15.edn_csr_rw.1920238297 Mar 05 12:43:54 PM PST 24 Mar 05 12:43:55 PM PST 24 22960204 ps
T845 /workspace/coverage/cover_reg_top/25.edn_intr_test.3076900129 Mar 05 12:43:51 PM PST 24 Mar 05 12:43:52 PM PST 24 19258454 ps
T846 /workspace/coverage/cover_reg_top/44.edn_intr_test.2961512914 Mar 05 12:43:58 PM PST 24 Mar 05 12:43:59 PM PST 24 174489129 ps
T847 /workspace/coverage/cover_reg_top/5.edn_tl_errors.4149765184 Mar 05 12:43:54 PM PST 24 Mar 05 12:43:59 PM PST 24 127891788 ps
T228 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.899729450 Mar 05 12:43:50 PM PST 24 Mar 05 12:43:52 PM PST 24 148033690 ps
T848 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2370158708 Mar 05 12:44:02 PM PST 24 Mar 05 12:44:04 PM PST 24 144125876 ps
T236 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1381504014 Mar 05 12:43:50 PM PST 24 Mar 05 12:43:53 PM PST 24 469969509 ps
T849 /workspace/coverage/cover_reg_top/34.edn_intr_test.3675071060 Mar 05 12:44:10 PM PST 24 Mar 05 12:44:11 PM PST 24 42587470 ps
T850 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1661686800 Mar 05 12:44:05 PM PST 24 Mar 05 12:44:08 PM PST 24 96509569 ps
T213 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1110023417 Mar 05 12:43:54 PM PST 24 Mar 05 12:44:01 PM PST 24 86139742 ps
T229 /workspace/coverage/cover_reg_top/19.edn_csr_rw.295436856 Mar 05 12:43:54 PM PST 24 Mar 05 12:43:55 PM PST 24 27177470 ps
T851 /workspace/coverage/cover_reg_top/2.edn_intr_test.2230110487 Mar 05 12:43:37 PM PST 24 Mar 05 12:43:43 PM PST 24 33069685 ps
T852 /workspace/coverage/cover_reg_top/40.edn_intr_test.71798416 Mar 05 12:44:01 PM PST 24 Mar 05 12:44:02 PM PST 24 13271551 ps
T853 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2696335390 Mar 05 12:43:54 PM PST 24 Mar 05 12:44:01 PM PST 24 99515192 ps
T854 /workspace/coverage/cover_reg_top/20.edn_intr_test.49571885 Mar 05 12:43:58 PM PST 24 Mar 05 12:43:59 PM PST 24 156429723 ps
T855 /workspace/coverage/cover_reg_top/5.edn_intr_test.2724443714 Mar 05 12:43:50 PM PST 24 Mar 05 12:43:52 PM PST 24 18186200 ps
T214 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2763277262 Mar 05 12:43:52 PM PST 24 Mar 05 12:43:54 PM PST 24 132942546 ps
T856 /workspace/coverage/cover_reg_top/23.edn_intr_test.3208240676 Mar 05 12:44:01 PM PST 24 Mar 05 12:44:02 PM PST 24 26896736 ps
T857 /workspace/coverage/cover_reg_top/46.edn_intr_test.931114636 Mar 05 12:44:04 PM PST 24 Mar 05 12:44:05 PM PST 24 120889430 ps
T858 /workspace/coverage/cover_reg_top/31.edn_intr_test.2333219490 Mar 05 12:44:00 PM PST 24 Mar 05 12:44:02 PM PST 24 47542328 ps
T243 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1143811038 Mar 05 12:43:54 PM PST 24 Mar 05 12:43:56 PM PST 24 250795278 ps
T859 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2254924593 Mar 05 12:44:00 PM PST 24 Mar 05 12:44:02 PM PST 24 114218300 ps
T860 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2640393127 Mar 05 12:43:52 PM PST 24 Mar 05 12:43:53 PM PST 24 36135663 ps
T861 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2892958299 Mar 05 12:43:56 PM PST 24 Mar 05 12:43:57 PM PST 24 77834714 ps
T862 /workspace/coverage/cover_reg_top/3.edn_intr_test.1933852118 Mar 05 12:43:42 PM PST 24 Mar 05 12:43:43 PM PST 24 16047157 ps
T863 /workspace/coverage/cover_reg_top/21.edn_intr_test.1038097448 Mar 05 12:43:46 PM PST 24 Mar 05 12:43:47 PM PST 24 44420530 ps
T864 /workspace/coverage/cover_reg_top/9.edn_tl_errors.770703302 Mar 05 12:44:01 PM PST 24 Mar 05 12:44:04 PM PST 24 329163578 ps
T215 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.282438773 Mar 05 12:43:53 PM PST 24 Mar 05 12:43:55 PM PST 24 18028764 ps
T865 /workspace/coverage/cover_reg_top/30.edn_intr_test.538946357 Mar 05 12:44:02 PM PST 24 Mar 05 12:44:03 PM PST 24 18191133 ps
T246 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1223175126 Mar 05 12:43:51 PM PST 24 Mar 05 12:43:53 PM PST 24 281932218 ps
T866 /workspace/coverage/cover_reg_top/24.edn_intr_test.1867439282 Mar 05 12:44:01 PM PST 24 Mar 05 12:44:03 PM PST 24 15901756 ps
T867 /workspace/coverage/cover_reg_top/26.edn_intr_test.1618097288 Mar 05 12:44:00 PM PST 24 Mar 05 12:44:02 PM PST 24 40769996 ps
T868 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.899228636 Mar 05 12:43:54 PM PST 24 Mar 05 12:43:56 PM PST 24 427014727 ps
T869 /workspace/coverage/cover_reg_top/13.edn_intr_test.769756384 Mar 05 12:43:57 PM PST 24 Mar 05 12:43:58 PM PST 24 16158821 ps
T216 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.369270438 Mar 05 12:43:58 PM PST 24 Mar 05 12:44:04 PM PST 24 990346712 ps
T237 /workspace/coverage/cover_reg_top/13.edn_csr_rw.600842477 Mar 05 12:43:56 PM PST 24 Mar 05 12:43:57 PM PST 24 179997358 ps
T870 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2267974665 Mar 05 12:44:00 PM PST 24 Mar 05 12:44:02 PM PST 24 200150275 ps
T871 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2703162560 Mar 05 12:43:53 PM PST 24 Mar 05 12:43:55 PM PST 24 301091787 ps
T217 /workspace/coverage/cover_reg_top/0.edn_csr_rw.395933117 Mar 05 12:44:08 PM PST 24 Mar 05 12:44:09 PM PST 24 28801859 ps
T872 /workspace/coverage/cover_reg_top/1.edn_tl_errors.2997829986 Mar 05 12:43:56 PM PST 24 Mar 05 12:43:58 PM PST 24 79679131 ps
T873 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2836869299 Mar 05 12:43:47 PM PST 24 Mar 05 12:43:48 PM PST 24 15386447 ps
T874 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.771790703 Mar 05 12:43:53 PM PST 24 Mar 05 12:43:55 PM PST 24 50788079 ps
T218 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1260660566 Mar 05 12:43:58 PM PST 24 Mar 05 12:44:06 PM PST 24 264296742 ps
T219 /workspace/coverage/cover_reg_top/3.edn_csr_rw.3217276309 Mar 05 12:44:01 PM PST 24 Mar 05 12:44:03 PM PST 24 17290847 ps
T220 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3788424908 Mar 05 12:43:36 PM PST 24 Mar 05 12:43:37 PM PST 24 419052473 ps
T221 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2114700786 Mar 05 12:43:42 PM PST 24 Mar 05 12:43:43 PM PST 24 22450772 ps
T875 /workspace/coverage/cover_reg_top/13.edn_tl_errors.598744908 Mar 05 12:44:07 PM PST 24 Mar 05 12:44:11 PM PST 24 194747202 ps
T876 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2250283666 Mar 05 12:43:54 PM PST 24 Mar 05 12:43:57 PM PST 24 121592346 ps
T877 /workspace/coverage/cover_reg_top/17.edn_tl_errors.570655909 Mar 05 12:43:44 PM PST 24 Mar 05 12:43:47 PM PST 24 90393830 ps
T230 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3548485531 Mar 05 12:43:43 PM PST 24 Mar 05 12:43:44 PM PST 24 23742280 ps
T878 /workspace/coverage/cover_reg_top/6.edn_intr_test.3187346166 Mar 05 12:43:48 PM PST 24 Mar 05 12:43:49 PM PST 24 40185525 ps
T879 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1253634932 Mar 05 12:44:01 PM PST 24 Mar 05 12:44:03 PM PST 24 26741894 ps
T880 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1753166529 Mar 05 12:43:48 PM PST 24 Mar 05 12:43:49 PM PST 24 17843238 ps
T231 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.465763474 Mar 05 12:43:48 PM PST 24 Mar 05 12:43:50 PM PST 24 18801561 ps
T881 /workspace/coverage/cover_reg_top/43.edn_intr_test.2903220985 Mar 05 12:44:04 PM PST 24 Mar 05 12:44:05 PM PST 24 16309449 ps
T232 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3283659533 Mar 05 12:43:37 PM PST 24 Mar 05 12:43:39 PM PST 24 74763714 ps
T882 /workspace/coverage/cover_reg_top/37.edn_intr_test.4189921982 Mar 05 12:44:01 PM PST 24 Mar 05 12:44:02 PM PST 24 12576502 ps
T883 /workspace/coverage/cover_reg_top/4.edn_tl_errors.3025565202 Mar 05 12:43:48 PM PST 24 Mar 05 12:43:51 PM PST 24 95979230 ps
T233 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2944567171 Mar 05 12:43:51 PM PST 24 Mar 05 12:43:53 PM PST 24 14520968 ps
T884 /workspace/coverage/cover_reg_top/1.edn_intr_test.2003667584 Mar 05 12:43:49 PM PST 24 Mar 05 12:43:50 PM PST 24 20947898 ps
T885 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2313689606 Mar 05 12:43:49 PM PST 24 Mar 05 12:43:51 PM PST 24 446210185 ps
T886 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3166894504 Mar 05 12:43:50 PM PST 24 Mar 05 12:43:51 PM PST 24 30531566 ps
T887 /workspace/coverage/cover_reg_top/33.edn_intr_test.2186474482 Mar 05 12:44:06 PM PST 24 Mar 05 12:44:07 PM PST 24 16656406 ps
T888 /workspace/coverage/cover_reg_top/36.edn_intr_test.4088196568 Mar 05 12:44:00 PM PST 24 Mar 05 12:44:02 PM PST 24 27335462 ps
T889 /workspace/coverage/cover_reg_top/2.edn_tl_errors.2680614716 Mar 05 12:43:59 PM PST 24 Mar 05 12:44:02 PM PST 24 171065889 ps
T890 /workspace/coverage/cover_reg_top/15.edn_intr_test.1948161660 Mar 05 12:43:51 PM PST 24 Mar 05 12:43:52 PM PST 24 16089123 ps
T891 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1690494171 Mar 05 12:43:38 PM PST 24 Mar 05 12:43:40 PM PST 24 24527906 ps
T892 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2049132062 Mar 05 12:43:55 PM PST 24 Mar 05 12:43:56 PM PST 24 58947457 ps
T222 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3485031928 Mar 05 12:43:46 PM PST 24 Mar 05 12:43:47 PM PST 24 115507662 ps
T893 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.788968740 Mar 05 12:43:51 PM PST 24 Mar 05 12:43:52 PM PST 24 35659675 ps
T894 /workspace/coverage/cover_reg_top/7.edn_intr_test.4148462673 Mar 05 12:43:45 PM PST 24 Mar 05 12:43:46 PM PST 24 37398407 ps
T895 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.348667819 Mar 05 12:43:52 PM PST 24 Mar 05 12:43:53 PM PST 24 19880004 ps
T896 /workspace/coverage/cover_reg_top/19.edn_intr_test.883124281 Mar 05 12:43:45 PM PST 24 Mar 05 12:43:46 PM PST 24 10628249 ps
T897 /workspace/coverage/cover_reg_top/19.edn_tl_errors.3610521418 Mar 05 12:43:51 PM PST 24 Mar 05 12:43:53 PM PST 24 111660328 ps
T898 /workspace/coverage/cover_reg_top/48.edn_intr_test.2870523160 Mar 05 12:44:01 PM PST 24 Mar 05 12:44:02 PM PST 24 13771177 ps
T899 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2822210987 Mar 05 12:43:47 PM PST 24 Mar 05 12:43:51 PM PST 24 208552954 ps
T223 /workspace/coverage/cover_reg_top/14.edn_csr_rw.3915876855 Mar 05 12:43:55 PM PST 24 Mar 05 12:43:56 PM PST 24 13863726 ps
T900 /workspace/coverage/cover_reg_top/11.edn_tl_errors.4059674482 Mar 05 12:43:49 PM PST 24 Mar 05 12:43:51 PM PST 24 38569718 ps
T901 /workspace/coverage/cover_reg_top/47.edn_intr_test.1960838429 Mar 05 12:44:07 PM PST 24 Mar 05 12:44:08 PM PST 24 14268895 ps
T902 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2351338893 Mar 05 12:43:43 PM PST 24 Mar 05 12:43:44 PM PST 24 59958498 ps
T903 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4071818360 Mar 05 12:43:59 PM PST 24 Mar 05 12:44:01 PM PST 24 20809861 ps
T244 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.4292053747 Mar 05 12:43:56 PM PST 24 Mar 05 12:43:58 PM PST 24 129714646 ps
T904 /workspace/coverage/cover_reg_top/9.edn_csr_rw.319545626 Mar 05 12:43:58 PM PST 24 Mar 05 12:43:59 PM PST 24 59314597 ps
T905 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.595293442 Mar 05 12:43:48 PM PST 24 Mar 05 12:43:50 PM PST 24 384582081 ps
T906 /workspace/coverage/cover_reg_top/32.edn_intr_test.1531051833 Mar 05 12:43:58 PM PST 24 Mar 05 12:43:59 PM PST 24 21839751 ps
T907 /workspace/coverage/cover_reg_top/16.edn_intr_test.3447815457 Mar 05 12:43:49 PM PST 24 Mar 05 12:43:49 PM PST 24 18807594 ps
T908 /workspace/coverage/cover_reg_top/16.edn_csr_rw.3819637817 Mar 05 12:44:09 PM PST 24 Mar 05 12:44:10 PM PST 24 40563384 ps
T909 /workspace/coverage/cover_reg_top/22.edn_intr_test.1518081754 Mar 05 12:44:02 PM PST 24 Mar 05 12:44:03 PM PST 24 18575019 ps
T910 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2089027066 Mar 05 12:43:56 PM PST 24 Mar 05 12:43:58 PM PST 24 136561855 ps
T911 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1309796958 Mar 05 12:43:56 PM PST 24 Mar 05 12:43:57 PM PST 24 195788483 ps
T912 /workspace/coverage/cover_reg_top/42.edn_intr_test.1907288154 Mar 05 12:43:55 PM PST 24 Mar 05 12:43:56 PM PST 24 13323030 ps
T913 /workspace/coverage/cover_reg_top/8.edn_csr_rw.192129884 Mar 05 12:43:53 PM PST 24 Mar 05 12:43:54 PM PST 24 51502240 ps
T914 /workspace/coverage/cover_reg_top/16.edn_tl_errors.3593588479 Mar 05 12:44:07 PM PST 24 Mar 05 12:44:09 PM PST 24 28259075 ps
T915 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.531265013 Mar 05 12:43:55 PM PST 24 Mar 05 12:43:56 PM PST 24 33847574 ps
T245 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1099853320 Mar 05 12:43:54 PM PST 24 Mar 05 12:43:56 PM PST 24 344460790 ps
T224 /workspace/coverage/cover_reg_top/12.edn_csr_rw.787411609 Mar 05 12:43:56 PM PST 24 Mar 05 12:43:57 PM PST 24 35330403 ps
T916 /workspace/coverage/cover_reg_top/7.edn_tl_errors.2488343513 Mar 05 12:43:33 PM PST 24 Mar 05 12:43:36 PM PST 24 331680050 ps
T917 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1915677415 Mar 05 12:43:54 PM PST 24 Mar 05 12:43:56 PM PST 24 196473216 ps
T918 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2296809931 Mar 05 12:43:57 PM PST 24 Mar 05 12:43:59 PM PST 24 51335153 ps
T919 /workspace/coverage/cover_reg_top/7.edn_csr_rw.3434316884 Mar 05 12:43:43 PM PST 24 Mar 05 12:43:44 PM PST 24 29600803 ps
T920 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.313439952 Mar 05 12:43:56 PM PST 24 Mar 05 12:43:58 PM PST 24 21860791 ps
T921 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.249539124 Mar 05 12:43:49 PM PST 24 Mar 05 12:43:50 PM PST 24 74034724 ps
T922 /workspace/coverage/cover_reg_top/9.edn_intr_test.1146269166 Mar 05 12:43:57 PM PST 24 Mar 05 12:43:58 PM PST 24 29332142 ps
T923 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3566703749 Mar 05 12:43:53 PM PST 24 Mar 05 12:43:54 PM PST 24 16611561 ps
T924 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3312728505 Mar 05 12:43:52 PM PST 24 Mar 05 12:43:53 PM PST 24 26426591 ps
T925 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3224577088 Mar 05 12:43:52 PM PST 24 Mar 05 12:43:53 PM PST 24 34369080 ps
T926 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1027536146 Mar 05 12:43:42 PM PST 24 Mar 05 12:43:43 PM PST 24 30141870 ps
T927 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.894509711 Mar 05 12:44:11 PM PST 24 Mar 05 12:44:13 PM PST 24 39699800 ps
T225 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1918527512 Mar 05 12:43:45 PM PST 24 Mar 05 12:43:45 PM PST 24 30267406 ps
T928 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3347769844 Mar 05 12:43:55 PM PST 24 Mar 05 12:43:56 PM PST 24 76119881 ps
T929 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2856805110 Mar 05 12:43:52 PM PST 24 Mar 05 12:43:53 PM PST 24 137977331 ps
T930 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2342450189 Mar 05 12:44:01 PM PST 24 Mar 05 12:44:04 PM PST 24 78606668 ps
T931 /workspace/coverage/cover_reg_top/8.edn_intr_test.2503715691 Mar 05 12:43:55 PM PST 24 Mar 05 12:43:56 PM PST 24 52045464 ps
T932 /workspace/coverage/cover_reg_top/18.edn_csr_rw.2659601644 Mar 05 12:43:54 PM PST 24 Mar 05 12:43:55 PM PST 24 14266439 ps
T933 /workspace/coverage/cover_reg_top/11.edn_csr_rw.4050786805 Mar 05 12:44:04 PM PST 24 Mar 05 12:44:10 PM PST 24 28229515 ps
T934 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2008729994 Mar 05 12:43:52 PM PST 24 Mar 05 12:43:53 PM PST 24 27092116 ps
T935 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1981622577 Mar 05 12:43:41 PM PST 24 Mar 05 12:43:43 PM PST 24 173448334 ps
T936 /workspace/coverage/cover_reg_top/17.edn_csr_rw.2187650927 Mar 05 12:43:52 PM PST 24 Mar 05 12:43:53 PM PST 24 14165082 ps
T226 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2838660039 Mar 05 12:43:44 PM PST 24 Mar 05 12:43:45 PM PST 24 16884039 ps
T937 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3412723678 Mar 05 12:44:00 PM PST 24 Mar 05 12:44:02 PM PST 24 100504000 ps
T938 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.102100759 Mar 05 12:43:58 PM PST 24 Mar 05 12:43:59 PM PST 24 37554951 ps
T939 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2245541002 Mar 05 12:44:02 PM PST 24 Mar 05 12:44:04 PM PST 24 40873875 ps
T940 /workspace/coverage/cover_reg_top/38.edn_intr_test.2176055789 Mar 05 12:43:56 PM PST 24 Mar 05 12:43:57 PM PST 24 25604116 ps
T941 /workspace/coverage/cover_reg_top/11.edn_intr_test.1721591119 Mar 05 12:43:52 PM PST 24 Mar 05 12:43:53 PM PST 24 40030663 ps
T942 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2567624000 Mar 05 12:43:47 PM PST 24 Mar 05 12:43:48 PM PST 24 100002764 ps
T943 /workspace/coverage/cover_reg_top/28.edn_intr_test.1188329928 Mar 05 12:44:10 PM PST 24 Mar 05 12:44:11 PM PST 24 121276157 ps
T944 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3720370495 Mar 05 12:44:03 PM PST 24 Mar 05 12:44:05 PM PST 24 194448479 ps
T945 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.965300770 Mar 05 12:43:47 PM PST 24 Mar 05 12:43:51 PM PST 24 117364632 ps
T227 /workspace/coverage/cover_reg_top/1.edn_csr_rw.3538607443 Mar 05 12:43:59 PM PST 24 Mar 05 12:44:00 PM PST 24 13005147 ps
T946 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3744545439 Mar 05 12:43:43 PM PST 24 Mar 05 12:43:48 PM PST 24 1011075482 ps
T947 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.148977208 Mar 05 12:43:50 PM PST 24 Mar 05 12:43:52 PM PST 24 14448243 ps
T948 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4179903841 Mar 05 12:43:42 PM PST 24 Mar 05 12:43:43 PM PST 24 64413708 ps
T949 /workspace/coverage/cover_reg_top/18.edn_intr_test.2355165726 Mar 05 12:43:53 PM PST 24 Mar 05 12:43:54 PM PST 24 19804420 ps
T950 /workspace/coverage/cover_reg_top/35.edn_intr_test.3477726936 Mar 05 12:44:00 PM PST 24 Mar 05 12:44:02 PM PST 24 14336657 ps
T951 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3100816134 Mar 05 12:44:06 PM PST 24 Mar 05 12:44:07 PM PST 24 62288281 ps
T952 /workspace/coverage/cover_reg_top/0.edn_tl_errors.3510141392 Mar 05 12:43:31 PM PST 24 Mar 05 12:43:34 PM PST 24 43821578 ps
T953 /workspace/coverage/cover_reg_top/27.edn_intr_test.1176627720 Mar 05 12:43:46 PM PST 24 Mar 05 12:43:47 PM PST 24 40812448 ps
T954 /workspace/coverage/cover_reg_top/14.edn_intr_test.2321295471 Mar 05 12:43:44 PM PST 24 Mar 05 12:43:45 PM PST 24 55578004 ps
T955 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3751206165 Mar 05 12:43:52 PM PST 24 Mar 05 12:43:54 PM PST 24 30926444 ps
T956 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3935693408 Mar 05 12:43:36 PM PST 24 Mar 05 12:43:37 PM PST 24 404678293 ps
T957 /workspace/coverage/cover_reg_top/17.edn_intr_test.4048301337 Mar 05 12:43:48 PM PST 24 Mar 05 12:43:49 PM PST 24 40907123 ps
T958 /workspace/coverage/cover_reg_top/29.edn_intr_test.1355318377 Mar 05 12:44:07 PM PST 24 Mar 05 12:44:08 PM PST 24 14931660 ps
T959 /workspace/coverage/cover_reg_top/49.edn_intr_test.1112358071 Mar 05 12:44:01 PM PST 24 Mar 05 12:44:03 PM PST 24 14240565 ps
T960 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.492814162 Mar 05 12:43:53 PM PST 24 Mar 05 12:43:54 PM PST 24 23454800 ps
T961 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3383402811 Mar 05 12:44:05 PM PST 24 Mar 05 12:44:07 PM PST 24 244996074 ps
T962 /workspace/coverage/cover_reg_top/0.edn_intr_test.125911500 Mar 05 12:44:00 PM PST 24 Mar 05 12:44:02 PM PST 24 15289580 ps
T963 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.137630114 Mar 05 12:43:43 PM PST 24 Mar 05 12:43:44 PM PST 24 31008275 ps
T964 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.170135730 Mar 05 12:43:56 PM PST 24 Mar 05 12:43:58 PM PST 24 281656871 ps
T965 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1156484656 Mar 05 12:43:40 PM PST 24 Mar 05 12:43:41 PM PST 24 19203393 ps
T966 /workspace/coverage/cover_reg_top/12.edn_intr_test.2860479115 Mar 05 12:43:57 PM PST 24 Mar 05 12:43:58 PM PST 24 37929035 ps
T967 /workspace/coverage/cover_reg_top/10.edn_tl_errors.3985064395 Mar 05 12:43:55 PM PST 24 Mar 05 12:43:57 PM PST 24 132146118 ps
T968 /workspace/coverage/cover_reg_top/10.edn_intr_test.685185249 Mar 05 12:43:56 PM PST 24 Mar 05 12:43:57 PM PST 24 23034302 ps
T969 /workspace/coverage/cover_reg_top/4.edn_intr_test.1231234701 Mar 05 12:43:55 PM PST 24 Mar 05 12:43:56 PM PST 24 15512483 ps
T970 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2850700447 Mar 05 12:44:02 PM PST 24 Mar 05 12:44:04 PM PST 24 144813468 ps

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.1982664806
Short name T5
Test name
Test status
Simulation time 84807656566 ps
CPU time 1749.84 seconds
Started Mar 05 01:50:22 PM PST 24
Finished Mar 05 02:19:32 PM PST 24
Peak memory 226764 kb
Host smart-608c349c-6145-45b5-9ae6-d24fc577b263
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982664806 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.1982664806
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_genbits.2355227371
Short name T28
Test name
Test status
Simulation time 303457719 ps
CPU time 3.55 seconds
Started Mar 05 01:49:59 PM PST 24
Finished Mar 05 01:50:03 PM PST 24
Peak memory 217004 kb
Host smart-83bf34e2-7192-439f-b5fb-a109df710c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355227371 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.2355227371
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_err.1191024927
Short name T4
Test name
Test status
Simulation time 23803328 ps
CPU time 0.97 seconds
Started Mar 05 01:50:07 PM PST 24
Finished Mar 05 01:50:08 PM PST 24
Peak memory 217036 kb
Host smart-9c1340f6-0b64-4334-8b1a-9e8bdc777825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191024927 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.1191024927
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/2.edn_sec_cm.1781344550
Short name T19
Test name
Test status
Simulation time 731449122 ps
CPU time 6.6 seconds
Started Mar 05 01:49:14 PM PST 24
Finished Mar 05 01:49:21 PM PST 24
Peak memory 233252 kb
Host smart-39a043c9-38a9-4d93-b14e-9ca946478488
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781344550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.1781344550
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/48.edn_alert.2994651831
Short name T18
Test name
Test status
Simulation time 86398416 ps
CPU time 1.23 seconds
Started Mar 05 01:50:13 PM PST 24
Finished Mar 05 01:50:16 PM PST 24
Peak memory 214840 kb
Host smart-128c3379-72b7-4fa3-bf74-cb5efdfd3b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994651831 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.2994651831
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/4.edn_intr.841814191
Short name T15
Test name
Test status
Simulation time 37251365 ps
CPU time 0.99 seconds
Started Mar 05 01:49:06 PM PST 24
Finished Mar 05 01:49:07 PM PST 24
Peak memory 222460 kb
Host smart-63500361-662e-440a-923e-dff77a20f898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841814191 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.841814191
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/16.edn_disable.2646242957
Short name T22
Test name
Test status
Simulation time 24464602 ps
CPU time 0.79 seconds
Started Mar 05 01:49:51 PM PST 24
Finished Mar 05 01:49:52 PM PST 24
Peak memory 214992 kb
Host smart-7d220254-e90c-446b-bc01-2c7cef5782f3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646242957 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.2646242957
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/28.edn_disable_auto_req_mode.3495524125
Short name T35
Test name
Test status
Simulation time 46794754 ps
CPU time 1.1 seconds
Started Mar 05 01:49:52 PM PST 24
Finished Mar 05 01:49:53 PM PST 24
Peak memory 215596 kb
Host smart-ca065ceb-a0a8-4e5b-a727-b56aa91f7f05
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495524125 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_d
isable_auto_req_mode.3495524125
Directory /workspace/28.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_alert.2283842461
Short name T99
Test name
Test status
Simulation time 46798635 ps
CPU time 1.17 seconds
Started Mar 05 01:49:48 PM PST 24
Finished Mar 05 01:49:49 PM PST 24
Peak memory 214796 kb
Host smart-93a68d47-9967-484a-a39a-2382d428aae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283842461 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.2283842461
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/0.edn_intr.3335759776
Short name T51
Test name
Test status
Simulation time 73001838 ps
CPU time 0.82 seconds
Started Mar 05 01:49:07 PM PST 24
Finished Mar 05 01:49:09 PM PST 24
Peak memory 214736 kb
Host smart-30a216e5-2f1f-42ed-a0a6-a55aab3c1ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335759776 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.3335759776
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_regwen.1849467171
Short name T115
Test name
Test status
Simulation time 19454318 ps
CPU time 1.01 seconds
Started Mar 05 01:49:03 PM PST 24
Finished Mar 05 01:49:04 PM PST 24
Peak memory 206224 kb
Host smart-717db809-fa4b-408c-90b9-32ddd7010643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849467171 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.1849467171
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.382008151
Short name T196
Test name
Test status
Simulation time 18196089451 ps
CPU time 345.5 seconds
Started Mar 05 01:50:02 PM PST 24
Finished Mar 05 01:55:47 PM PST 24
Peak memory 216216 kb
Host smart-bd7da01d-056e-4170-b45e-b2b00fb98a59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382008151 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.382008151
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.3589320627
Short name T113
Test name
Test status
Simulation time 29550117 ps
CPU time 1.32 seconds
Started Mar 05 01:49:17 PM PST 24
Finished Mar 05 01:49:19 PM PST 24
Peak memory 214816 kb
Host smart-f4f2af10-3643-4784-98c0-c21bffacdc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589320627 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.3589320627
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert.434960544
Short name T92
Test name
Test status
Simulation time 39407543 ps
CPU time 1.11 seconds
Started Mar 05 01:49:56 PM PST 24
Finished Mar 05 01:49:58 PM PST 24
Peak memory 214812 kb
Host smart-6ffe84f7-6301-4b40-b052-7f7c19d7f4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434960544 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.434960544
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4103232934
Short name T239
Test name
Test status
Simulation time 696773159 ps
CPU time 2.4 seconds
Started Mar 05 12:44:00 PM PST 24
Finished Mar 05 12:44:02 PM PST 24
Peak memory 206264 kb
Host smart-f3958851-ae05-48eb-b175-b4b08343ac0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103232934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.4103232934
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/default/49.edn_disable.205823670
Short name T150
Test name
Test status
Simulation time 65423588 ps
CPU time 0.82 seconds
Started Mar 05 01:50:30 PM PST 24
Finished Mar 05 01:50:31 PM PST 24
Peak memory 214944 kb
Host smart-84b93cd4-ded5-4f83-ac40-6f8376167209
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205823670 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.205823670
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.2763277262
Short name T214
Test name
Test status
Simulation time 132942546 ps
CPU time 1.47 seconds
Started Mar 05 12:43:52 PM PST 24
Finished Mar 05 12:43:54 PM PST 24
Peak memory 206212 kb
Host smart-4b44bb98-1bbd-476a-9f3f-28286c24c8cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763277262 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.2763277262
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.1924023456
Short name T61
Test name
Test status
Simulation time 59831189 ps
CPU time 1.16 seconds
Started Mar 05 01:49:15 PM PST 24
Finished Mar 05 01:49:17 PM PST 24
Peak memory 215448 kb
Host smart-8bb1810f-fa04-43ae-bc04-8c6c46d04f31
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924023456 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_di
sable_auto_req_mode.1924023456
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/56.edn_genbits.254271466
Short name T2
Test name
Test status
Simulation time 45199081 ps
CPU time 1.63 seconds
Started Mar 05 01:50:38 PM PST 24
Finished Mar 05 01:50:40 PM PST 24
Peak memory 217764 kb
Host smart-f22a0c56-8f13-4d4e-b0a0-ccd5263ac298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254271466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.254271466
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_disable.1998287997
Short name T448
Test name
Test status
Simulation time 25715937 ps
CPU time 0.84 seconds
Started Mar 05 01:49:16 PM PST 24
Finished Mar 05 01:49:18 PM PST 24
Peak memory 214992 kb
Host smart-0fc9e41a-affd-4d7a-9681-d011cc20b9f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998287997 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1998287997
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable.906508992
Short name T615
Test name
Test status
Simulation time 11677263 ps
CPU time 0.87 seconds
Started Mar 05 01:49:22 PM PST 24
Finished Mar 05 01:49:23 PM PST 24
Peak memory 215020 kb
Host smart-c76e0049-e34b-4686-81aa-0541d036c896
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906508992 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.906508992
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/37.edn_intr.1569358318
Short name T119
Test name
Test status
Simulation time 64437418 ps
CPU time 0.94 seconds
Started Mar 05 01:50:10 PM PST 24
Finished Mar 05 01:50:11 PM PST 24
Peak memory 214840 kb
Host smart-d19ae5b8-c150-409d-ac4b-e49ad1e11ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569358318 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.1569358318
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/22.edn_alert.270255420
Short name T577
Test name
Test status
Simulation time 96768463 ps
CPU time 1.21 seconds
Started Mar 05 01:49:45 PM PST 24
Finished Mar 05 01:49:46 PM PST 24
Peak memory 214856 kb
Host smart-4c756760-6bc7-43f1-b9cb-381f3ca83226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270255420 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.270255420
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable.12289381
Short name T1
Test name
Test status
Simulation time 15827111 ps
CPU time 0.84 seconds
Started Mar 05 01:49:29 PM PST 24
Finished Mar 05 01:49:30 PM PST 24
Peak memory 206480 kb
Host smart-e7ad593b-9d4e-4a73-800c-975c1032e418
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12289381 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.12289381
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/142.edn_genbits.1282386821
Short name T10
Test name
Test status
Simulation time 128270624 ps
CPU time 1.33 seconds
Started Mar 05 01:50:41 PM PST 24
Finished Mar 05 01:50:44 PM PST 24
Peak memory 218768 kb
Host smart-feb3cf36-0723-42a4-aece-1e847b3e5f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282386821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.1282386821
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.1676019896
Short name T26
Test name
Test status
Simulation time 81219623 ps
CPU time 1.45 seconds
Started Mar 05 01:50:49 PM PST 24
Finished Mar 05 01:50:51 PM PST 24
Peak memory 217140 kb
Host smart-9f6ab1d8-fe8d-40a4-b0ec-cb9fe0ec4bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676019896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.1676019896
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.2080076884
Short name T468
Test name
Test status
Simulation time 44258808 ps
CPU time 1.09 seconds
Started Mar 05 01:49:38 PM PST 24
Finished Mar 05 01:49:39 PM PST 24
Peak memory 215440 kb
Host smart-8eb97292-df9b-4ee3-bb56-9f8c990bf816
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080076884 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.2080076884
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_disable.483984077
Short name T152
Test name
Test status
Simulation time 30754302 ps
CPU time 0.81 seconds
Started Mar 05 01:49:57 PM PST 24
Finished Mar 05 01:49:58 PM PST 24
Peak memory 215024 kb
Host smart-a397f0d1-b470-4c53-a123-654c81e22548
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483984077 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.483984077
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable.2280359245
Short name T163
Test name
Test status
Simulation time 12316395 ps
CPU time 0.89 seconds
Started Mar 05 01:49:33 PM PST 24
Finished Mar 05 01:49:34 PM PST 24
Peak memory 214900 kb
Host smart-cf5336e4-364f-4836-9848-4e98de4159b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280359245 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.2280359245
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.1682716040
Short name T58
Test name
Test status
Simulation time 74721023 ps
CPU time 1.26 seconds
Started Mar 05 01:49:43 PM PST 24
Finished Mar 05 01:49:44 PM PST 24
Peak memory 215416 kb
Host smart-4869a719-2370-4dd1-9971-13b83ce4b242
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682716040 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.1682716040
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.2424600881
Short name T161
Test name
Test status
Simulation time 45377054 ps
CPU time 1.45 seconds
Started Mar 05 01:49:49 PM PST 24
Finished Mar 05 01:49:51 PM PST 24
Peak memory 215540 kb
Host smart-6742e893-28fc-42fb-919e-a9c2658c72f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424600881 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.2424600881
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_disable.1084065905
Short name T171
Test name
Test status
Simulation time 22470090 ps
CPU time 0.85 seconds
Started Mar 05 01:50:05 PM PST 24
Finished Mar 05 01:50:06 PM PST 24
Peak memory 214976 kb
Host smart-e43236ed-71cb-44ec-b643-87def3d9891b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084065905 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.1084065905
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/43.edn_disable_auto_req_mode.1353689803
Short name T66
Test name
Test status
Simulation time 52843841 ps
CPU time 1.22 seconds
Started Mar 05 01:50:03 PM PST 24
Finished Mar 05 01:50:05 PM PST 24
Peak memory 214720 kb
Host smart-a974417e-4564-493e-8da1-43a4e19c6d47
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353689803 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_d
isable_auto_req_mode.1353689803
Directory /workspace/43.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_alert_test.2470729978
Short name T313
Test name
Test status
Simulation time 24077526 ps
CPU time 0.84 seconds
Started Mar 05 01:49:20 PM PST 24
Finished Mar 05 01:49:21 PM PST 24
Peak memory 205804 kb
Host smart-f35ec2f5-013c-433a-9269-d370b80f7084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470729978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2470729978
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/267.edn_genbits.1302894587
Short name T270
Test name
Test status
Simulation time 111664708 ps
CPU time 1.26 seconds
Started Mar 05 01:51:12 PM PST 24
Finished Mar 05 01:51:13 PM PST 24
Peak memory 217776 kb
Host smart-7f13ebce-86e4-4295-9c6c-9fdbc3ed2a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302894587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1302894587
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_regwen.2507975078
Short name T764
Test name
Test status
Simulation time 46490699 ps
CPU time 0.95 seconds
Started Mar 05 01:49:08 PM PST 24
Finished Mar 05 01:49:10 PM PST 24
Peak memory 206268 kb
Host smart-244519f1-e12f-4aea-a82a-9e8796d9da14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507975078 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.2507975078
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/106.edn_genbits.1996749128
Short name T263
Test name
Test status
Simulation time 46034702 ps
CPU time 0.95 seconds
Started Mar 05 01:50:43 PM PST 24
Finished Mar 05 01:50:49 PM PST 24
Peak memory 215624 kb
Host smart-dc941164-d320-476d-93d2-266687a7e7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996749128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1996749128
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_genbits.1299806248
Short name T31
Test name
Test status
Simulation time 57121087 ps
CPU time 1.55 seconds
Started Mar 05 01:49:39 PM PST 24
Finished Mar 05 01:49:40 PM PST 24
Peak memory 217240 kb
Host smart-311da143-9e78-45d2-83a7-0cb4057a8262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299806248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1299806248
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.3305644203
Short name T193
Test name
Test status
Simulation time 42159318 ps
CPU time 1.65 seconds
Started Mar 05 01:50:31 PM PST 24
Finished Mar 05 01:50:33 PM PST 24
Peak memory 216700 kb
Host smart-c7461187-fafd-459d-a2cc-58ea9771f86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305644203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.3305644203
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.2521510787
Short name T101
Test name
Test status
Simulation time 210805255 ps
CPU time 1.16 seconds
Started Mar 05 01:49:49 PM PST 24
Finished Mar 05 01:49:50 PM PST 24
Peak memory 214864 kb
Host smart-6c9ffe4c-8e97-483a-b74f-460fc586e4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521510787 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.2521510787
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/2.edn_regwen.1973585520
Short name T758
Test name
Test status
Simulation time 39942876 ps
CPU time 0.89 seconds
Started Mar 05 01:49:15 PM PST 24
Finished Mar 05 01:49:17 PM PST 24
Peak memory 206240 kb
Host smart-a7f0771f-ecae-4b5d-a1af-5333000dc951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973585520 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1973585520
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_intr.3175279353
Short name T121
Test name
Test status
Simulation time 38868548 ps
CPU time 0.86 seconds
Started Mar 05 01:48:59 PM PST 24
Finished Mar 05 01:49:01 PM PST 24
Peak memory 214636 kb
Host smart-63cb5dc7-2cad-4501-a402-e70706d9112a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175279353 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3175279353
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/66.edn_err.993807959
Short name T40
Test name
Test status
Simulation time 21112248 ps
CPU time 1.18 seconds
Started Mar 05 01:50:39 PM PST 24
Finished Mar 05 01:50:40 PM PST 24
Peak memory 229040 kb
Host smart-659ab73b-243a-4d2c-b9f0-469b42934484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993807959 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.993807959
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.3283659533
Short name T232
Test name
Test status
Simulation time 74763714 ps
CPU time 1 seconds
Started Mar 05 12:43:37 PM PST 24
Finished Mar 05 12:43:39 PM PST 24
Peak memory 206184 kb
Host smart-4fe4bfb2-97d1-4107-b35c-09b4b9aaadb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283659533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.3283659533
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.4292053747
Short name T244
Test name
Test status
Simulation time 129714646 ps
CPU time 2.17 seconds
Started Mar 05 12:43:56 PM PST 24
Finished Mar 05 12:43:58 PM PST 24
Peak memory 206212 kb
Host smart-e0eb8f34-6ff0-48bc-a1bb-9ff09c6d5c46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292053747 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.4292053747
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.3279043185
Short name T255
Test name
Test status
Simulation time 50936175 ps
CPU time 1.16 seconds
Started Mar 05 01:49:06 PM PST 24
Finished Mar 05 01:49:07 PM PST 24
Peak memory 214848 kb
Host smart-55db3837-c2df-4549-b6a8-2a524b474098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279043185 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.3279043185
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/10.edn_genbits.4274848761
Short name T265
Test name
Test status
Simulation time 20430326 ps
CPU time 1.15 seconds
Started Mar 05 01:49:36 PM PST 24
Finished Mar 05 01:49:37 PM PST 24
Peak memory 215988 kb
Host smart-99ff2b43-35d6-4275-a702-a9a05b0d3307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274848761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.4274848761
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_smoke.4028720601
Short name T38
Test name
Test status
Simulation time 19080726 ps
CPU time 0.96 seconds
Started Mar 05 01:49:20 PM PST 24
Finished Mar 05 01:49:21 PM PST 24
Peak memory 214440 kb
Host smart-50216f6f-0552-486e-bd3a-65a45d0eeee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028720601 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.4028720601
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/107.edn_genbits.1492736649
Short name T705
Test name
Test status
Simulation time 51038149 ps
CPU time 1.58 seconds
Started Mar 05 01:50:44 PM PST 24
Finished Mar 05 01:50:49 PM PST 24
Peak memory 216780 kb
Host smart-e70953b0-3169-4fa5-85ec-ddc47b23e7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492736649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1492736649
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.3037052864
Short name T258
Test name
Test status
Simulation time 75278296 ps
CPU time 1.17 seconds
Started Mar 05 01:49:29 PM PST 24
Finished Mar 05 01:49:31 PM PST 24
Peak memory 214852 kb
Host smart-05792d34-1f76-4656-a924-d3b5a16bbe6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037052864 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3037052864
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/110.edn_genbits.121114350
Short name T327
Test name
Test status
Simulation time 98299510 ps
CPU time 1.52 seconds
Started Mar 05 01:50:44 PM PST 24
Finished Mar 05 01:50:49 PM PST 24
Peak memory 217324 kb
Host smart-95f8b486-2411-4131-ad1e-179939664dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121114350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.121114350
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_genbits.654501842
Short name T277
Test name
Test status
Simulation time 147421911 ps
CPU time 1.69 seconds
Started Mar 05 01:49:32 PM PST 24
Finished Mar 05 01:49:34 PM PST 24
Peak memory 218672 kb
Host smart-69a92ac3-6b43-4bab-a46a-1df81e7c02aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654501842 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.654501842
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.229229406
Short name T285
Test name
Test status
Simulation time 26469962 ps
CPU time 1.24 seconds
Started Mar 05 01:50:42 PM PST 24
Finished Mar 05 01:50:47 PM PST 24
Peak memory 215996 kb
Host smart-f4a62455-5bd5-408a-b9f9-1ec2ccc26f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229229406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.229229406
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/140.edn_genbits.1798378198
Short name T485
Test name
Test status
Simulation time 52975108 ps
CPU time 1.26 seconds
Started Mar 05 01:50:45 PM PST 24
Finished Mar 05 01:50:50 PM PST 24
Peak memory 215736 kb
Host smart-b5581646-56c1-4d4f-b9ac-f1edd0f54c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798378198 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.1798378198
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_stress_all.2300601965
Short name T709
Test name
Test status
Simulation time 175900044 ps
CPU time 3.73 seconds
Started Mar 05 01:49:47 PM PST 24
Finished Mar 05 01:49:51 PM PST 24
Peak memory 215608 kb
Host smart-cf0d57db-663b-4d81-beb7-49ad8f7759e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300601965 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2300601965
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/171.edn_genbits.1585485734
Short name T275
Test name
Test status
Simulation time 62713016 ps
CPU time 1.54 seconds
Started Mar 05 01:51:02 PM PST 24
Finished Mar 05 01:51:03 PM PST 24
Peak memory 217112 kb
Host smart-a6a583da-fa98-4154-98f3-424922f0a38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585485734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1585485734
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_genbits.2105544690
Short name T289
Test name
Test status
Simulation time 191225963 ps
CPU time 2.54 seconds
Started Mar 05 01:49:53 PM PST 24
Finished Mar 05 01:49:55 PM PST 24
Peak memory 216912 kb
Host smart-a1fa1ee3-3c48-4486-80d7-80a43b1f396c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105544690 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.2105544690
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2398458614
Short name T774
Test name
Test status
Simulation time 27893144 ps
CPU time 1.29 seconds
Started Mar 05 01:50:08 PM PST 24
Finished Mar 05 01:50:09 PM PST 24
Peak memory 214860 kb
Host smart-b30bc902-46d9-41e0-930a-fb026f4ce910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398458614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2398458614
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/11.edn_intr.2400198061
Short name T126
Test name
Test status
Simulation time 30552821 ps
CPU time 0.9 seconds
Started Mar 05 01:49:33 PM PST 24
Finished Mar 05 01:49:34 PM PST 24
Peak memory 214728 kb
Host smart-bba27314-de84-4f08-97ff-415ae64d90dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400198061 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.2400198061
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/19.edn_disable.1736722966
Short name T110
Test name
Test status
Simulation time 11105836 ps
CPU time 0.87 seconds
Started Mar 05 01:49:46 PM PST 24
Finished Mar 05 01:49:47 PM PST 24
Peak memory 215052 kb
Host smart-7539899d-f9dc-4898-8364-554d6357c548
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736722966 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.1736722966
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/165.edn_genbits.2197914978
Short name T320
Test name
Test status
Simulation time 45240145 ps
CPU time 1.71 seconds
Started Mar 05 01:50:45 PM PST 24
Finished Mar 05 01:50:51 PM PST 24
Peak memory 217032 kb
Host smart-c28b19c4-f956-4d0e-9b2f-97f7aeabccc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197914978 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2197914978
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.3788424908
Short name T220
Test name
Test status
Simulation time 419052473 ps
CPU time 1.55 seconds
Started Mar 05 12:43:36 PM PST 24
Finished Mar 05 12:43:37 PM PST 24
Peak memory 206272 kb
Host smart-7cdcd948-3983-4703-a7ab-a0bab0ac91c7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788424908 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.3788424908
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.1381504014
Short name T236
Test name
Test status
Simulation time 469969509 ps
CPU time 3.17 seconds
Started Mar 05 12:43:50 PM PST 24
Finished Mar 05 12:43:53 PM PST 24
Peak memory 206160 kb
Host smart-d10d71db-e1b2-4823-8da3-8c92ff08c357
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381504014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.1381504014
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.137630114
Short name T963
Test name
Test status
Simulation time 31008275 ps
CPU time 0.92 seconds
Started Mar 05 12:43:43 PM PST 24
Finished Mar 05 12:43:44 PM PST 24
Peak memory 206108 kb
Host smart-fe7139be-d3e7-45f9-ae87-79c1353c5060
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137630114 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.137630114
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.3347769844
Short name T928
Test name
Test status
Simulation time 76119881 ps
CPU time 1.31 seconds
Started Mar 05 12:43:55 PM PST 24
Finished Mar 05 12:43:56 PM PST 24
Peak memory 222748 kb
Host smart-84448857-00ab-44e0-a11c-3ad39315a56d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347769844 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.3347769844
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.395933117
Short name T217
Test name
Test status
Simulation time 28801859 ps
CPU time 0.96 seconds
Started Mar 05 12:44:08 PM PST 24
Finished Mar 05 12:44:09 PM PST 24
Peak memory 206220 kb
Host smart-52e29fc8-7435-485f-a787-5e29b912a2dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395933117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.395933117
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.125911500
Short name T962
Test name
Test status
Simulation time 15289580 ps
CPU time 0.91 seconds
Started Mar 05 12:44:00 PM PST 24
Finished Mar 05 12:44:02 PM PST 24
Peak memory 206000 kb
Host smart-1ec38a41-09f2-42cc-8dba-015748656445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125911500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.125911500
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.3510141392
Short name T952
Test name
Test status
Simulation time 43821578 ps
CPU time 2.99 seconds
Started Mar 05 12:43:31 PM PST 24
Finished Mar 05 12:43:34 PM PST 24
Peak memory 214580 kb
Host smart-34d06b4e-76d7-4e75-be87-0175ee454f21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510141392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.3510141392
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3744545439
Short name T946
Test name
Test status
Simulation time 1011075482 ps
CPU time 5.03 seconds
Started Mar 05 12:43:43 PM PST 24
Finished Mar 05 12:43:48 PM PST 24
Peak memory 206212 kb
Host smart-0967ec72-e0cc-4060-aa43-1ed11d8deb25
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744545439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3744545439
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.1753166529
Short name T880
Test name
Test status
Simulation time 17843238 ps
CPU time 0.95 seconds
Started Mar 05 12:43:48 PM PST 24
Finished Mar 05 12:43:49 PM PST 24
Peak memory 206204 kb
Host smart-a0ea9c5e-774b-4af7-a744-9c1777796738
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753166529 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.1753166529
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.313439952
Short name T920
Test name
Test status
Simulation time 21860791 ps
CPU time 1.42 seconds
Started Mar 05 12:43:56 PM PST 24
Finished Mar 05 12:43:58 PM PST 24
Peak memory 214548 kb
Host smart-3e57c7d4-390f-40af-b7e8-c70a1e303e91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313439952 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.313439952
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.3538607443
Short name T227
Test name
Test status
Simulation time 13005147 ps
CPU time 0.91 seconds
Started Mar 05 12:43:59 PM PST 24
Finished Mar 05 12:44:00 PM PST 24
Peak memory 206192 kb
Host smart-1adc0b59-48a6-4720-bd99-cc71623d4d32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538607443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.3538607443
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2003667584
Short name T884
Test name
Test status
Simulation time 20947898 ps
CPU time 0.82 seconds
Started Mar 05 12:43:49 PM PST 24
Finished Mar 05 12:43:50 PM PST 24
Peak memory 206204 kb
Host smart-b80de695-eefd-424f-84ea-d495edeb9d85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003667584 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2003667584
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.899729450
Short name T228
Test name
Test status
Simulation time 148033690 ps
CPU time 1.53 seconds
Started Mar 05 12:43:50 PM PST 24
Finished Mar 05 12:43:52 PM PST 24
Peak memory 206252 kb
Host smart-5b32b2ac-f06e-4d78-b36d-2fb118c99623
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899729450 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_out
standing.899729450
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2997829986
Short name T872
Test name
Test status
Simulation time 79679131 ps
CPU time 2.58 seconds
Started Mar 05 12:43:56 PM PST 24
Finished Mar 05 12:43:58 PM PST 24
Peak memory 214572 kb
Host smart-ba3f0fe9-8d6d-44df-b136-a124fd4b6564
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997829986 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2997829986
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.595293442
Short name T905
Test name
Test status
Simulation time 384582081 ps
CPU time 2.19 seconds
Started Mar 05 12:43:48 PM PST 24
Finished Mar 05 12:43:50 PM PST 24
Peak memory 206268 kb
Host smart-74cc6a31-14fe-42ec-8c33-4b9ca3ff0fe5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595293442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.595293442
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2927412715
Short name T839
Test name
Test status
Simulation time 26110605 ps
CPU time 1.12 seconds
Started Mar 05 12:43:58 PM PST 24
Finished Mar 05 12:43:59 PM PST 24
Peak memory 206284 kb
Host smart-b328bbdc-e9cb-436f-ae98-777f8ff62fb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927412715 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2927412715
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2944567171
Short name T233
Test name
Test status
Simulation time 14520968 ps
CPU time 0.92 seconds
Started Mar 05 12:43:51 PM PST 24
Finished Mar 05 12:43:53 PM PST 24
Peak memory 206196 kb
Host smart-8033dbab-2300-46f3-9931-23e304a341d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944567171 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2944567171
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.685185249
Short name T968
Test name
Test status
Simulation time 23034302 ps
CPU time 0.86 seconds
Started Mar 05 12:43:56 PM PST 24
Finished Mar 05 12:43:57 PM PST 24
Peak memory 206032 kb
Host smart-b774e82f-ee59-4e94-867e-f19c2448baaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685185249 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.685185249
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3566703749
Short name T923
Test name
Test status
Simulation time 16611561 ps
CPU time 1.08 seconds
Started Mar 05 12:43:53 PM PST 24
Finished Mar 05 12:43:54 PM PST 24
Peak memory 206296 kb
Host smart-8c8504d5-c7b3-419a-ba68-fa60fdae1c11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566703749 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3566703749
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.3985064395
Short name T967
Test name
Test status
Simulation time 132146118 ps
CPU time 2.63 seconds
Started Mar 05 12:43:55 PM PST 24
Finished Mar 05 12:43:57 PM PST 24
Peak memory 214368 kb
Host smart-16f0b9d5-f110-444a-9f03-507a40df8157
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985064395 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.3985064395
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1810508475
Short name T240
Test name
Test status
Simulation time 101308638 ps
CPU time 2.66 seconds
Started Mar 05 12:43:53 PM PST 24
Finished Mar 05 12:43:56 PM PST 24
Peak memory 206196 kb
Host smart-ffea202e-db78-4649-b9e2-bd92949889ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810508475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1810508475
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.894509711
Short name T927
Test name
Test status
Simulation time 39699800 ps
CPU time 1.25 seconds
Started Mar 05 12:44:11 PM PST 24
Finished Mar 05 12:44:13 PM PST 24
Peak memory 216184 kb
Host smart-f92ab924-2afb-4953-92df-2e26e5f7a6a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894509711 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.894509711
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.4050786805
Short name T933
Test name
Test status
Simulation time 28229515 ps
CPU time 0.92 seconds
Started Mar 05 12:44:04 PM PST 24
Finished Mar 05 12:44:10 PM PST 24
Peak memory 206204 kb
Host smart-ad56588a-ae4b-4f6b-9a45-09b8e428f121
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050786805 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.4050786805
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.1721591119
Short name T941
Test name
Test status
Simulation time 40030663 ps
CPU time 0.78 seconds
Started Mar 05 12:43:52 PM PST 24
Finished Mar 05 12:43:53 PM PST 24
Peak memory 206048 kb
Host smart-4c59ead0-7a64-4043-844f-d75228493350
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721591119 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.1721591119
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.531265013
Short name T915
Test name
Test status
Simulation time 33847574 ps
CPU time 1.35 seconds
Started Mar 05 12:43:55 PM PST 24
Finished Mar 05 12:43:56 PM PST 24
Peak memory 206188 kb
Host smart-e298dc16-5ca5-4bb1-a2bc-9ba485b9e984
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531265013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou
tstanding.531265013
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.4059674482
Short name T900
Test name
Test status
Simulation time 38569718 ps
CPU time 2.5 seconds
Started Mar 05 12:43:49 PM PST 24
Finished Mar 05 12:43:51 PM PST 24
Peak memory 214272 kb
Host smart-09ce8ade-bff3-4178-bb09-8a315c333c6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059674482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.4059674482
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1223175126
Short name T246
Test name
Test status
Simulation time 281932218 ps
CPU time 2.27 seconds
Started Mar 05 12:43:51 PM PST 24
Finished Mar 05 12:43:53 PM PST 24
Peak memory 206272 kb
Host smart-b39c5b2f-6589-46ab-93cb-7799e8109fe0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223175126 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1223175126
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.2696335390
Short name T853
Test name
Test status
Simulation time 99515192 ps
CPU time 1.92 seconds
Started Mar 05 12:43:54 PM PST 24
Finished Mar 05 12:44:01 PM PST 24
Peak memory 214552 kb
Host smart-93445bf9-213b-46e9-be9f-ca37fa43ae61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696335390 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.2696335390
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.787411609
Short name T224
Test name
Test status
Simulation time 35330403 ps
CPU time 0.8 seconds
Started Mar 05 12:43:56 PM PST 24
Finished Mar 05 12:43:57 PM PST 24
Peak memory 206052 kb
Host smart-3f9f77ef-4afa-43b4-bd73-f5528e429409
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787411609 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.787411609
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2860479115
Short name T966
Test name
Test status
Simulation time 37929035 ps
CPU time 0.85 seconds
Started Mar 05 12:43:57 PM PST 24
Finished Mar 05 12:43:58 PM PST 24
Peak memory 206052 kb
Host smart-58b4dba5-128b-451a-a359-9b88bebec576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860479115 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2860479115
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.465763474
Short name T231
Test name
Test status
Simulation time 18801561 ps
CPU time 1.12 seconds
Started Mar 05 12:43:48 PM PST 24
Finished Mar 05 12:43:50 PM PST 24
Peak memory 206200 kb
Host smart-d5f62440-a1fc-43dd-83cb-bf83b9d7d81b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465763474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.465763474
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.3134880092
Short name T842
Test name
Test status
Simulation time 105256363 ps
CPU time 3.76 seconds
Started Mar 05 12:43:48 PM PST 24
Finished Mar 05 12:43:52 PM PST 24
Peak memory 214584 kb
Host smart-8053d9ab-cb60-4659-b8a5-2494865ccb98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134880092 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.3134880092
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.771790703
Short name T874
Test name
Test status
Simulation time 50788079 ps
CPU time 1.02 seconds
Started Mar 05 12:43:53 PM PST 24
Finished Mar 05 12:43:55 PM PST 24
Peak memory 214452 kb
Host smart-cb86c17b-d7aa-4354-8367-56c08eda086b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771790703 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.771790703
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.600842477
Short name T237
Test name
Test status
Simulation time 179997358 ps
CPU time 0.85 seconds
Started Mar 05 12:43:56 PM PST 24
Finished Mar 05 12:43:57 PM PST 24
Peak memory 206196 kb
Host smart-4fa82623-5a2f-43c0-90b0-7d427ed51fa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600842477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.600842477
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.769756384
Short name T869
Test name
Test status
Simulation time 16158821 ps
CPU time 0.9 seconds
Started Mar 05 12:43:57 PM PST 24
Finished Mar 05 12:43:58 PM PST 24
Peak memory 206216 kb
Host smart-0a4f836a-6b26-4f92-98ae-d7fe5aee5fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769756384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.769756384
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2856805110
Short name T929
Test name
Test status
Simulation time 137977331 ps
CPU time 1.25 seconds
Started Mar 05 12:43:52 PM PST 24
Finished Mar 05 12:43:53 PM PST 24
Peak memory 206252 kb
Host smart-ab88af11-7d42-4d1e-9655-8c9d8cf6c797
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856805110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2856805110
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.598744908
Short name T875
Test name
Test status
Simulation time 194747202 ps
CPU time 3.59 seconds
Started Mar 05 12:44:07 PM PST 24
Finished Mar 05 12:44:11 PM PST 24
Peak memory 214620 kb
Host smart-bf457ed3-9cda-4c11-8770-bae43667fcf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598744908 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.598744908
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.2296809931
Short name T918
Test name
Test status
Simulation time 51335153 ps
CPU time 1.67 seconds
Started Mar 05 12:43:57 PM PST 24
Finished Mar 05 12:43:59 PM PST 24
Peak memory 206096 kb
Host smart-c040b66b-21c9-41f1-beaa-d37d80305756
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296809931 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.2296809931
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.1309796958
Short name T911
Test name
Test status
Simulation time 195788483 ps
CPU time 0.98 seconds
Started Mar 05 12:43:56 PM PST 24
Finished Mar 05 12:43:57 PM PST 24
Peak memory 206144 kb
Host smart-6c274711-8b22-44b7-8979-98d15c2ed3de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309796958 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.1309796958
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.3915876855
Short name T223
Test name
Test status
Simulation time 13863726 ps
CPU time 0.95 seconds
Started Mar 05 12:43:55 PM PST 24
Finished Mar 05 12:43:56 PM PST 24
Peak memory 206192 kb
Host smart-5b1ade32-7eb4-42fc-afd7-af0145083252
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915876855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.3915876855
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.2321295471
Short name T954
Test name
Test status
Simulation time 55578004 ps
CPU time 0.79 seconds
Started Mar 05 12:43:44 PM PST 24
Finished Mar 05 12:43:45 PM PST 24
Peak memory 206048 kb
Host smart-5bf28ed9-9611-49df-97f6-d5cc47473e28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321295471 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.2321295471
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.2313689606
Short name T885
Test name
Test status
Simulation time 446210185 ps
CPU time 1.35 seconds
Started Mar 05 12:43:49 PM PST 24
Finished Mar 05 12:43:51 PM PST 24
Peak memory 206188 kb
Host smart-91b1dd79-688e-45e7-b782-75b483be8ada
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313689606 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.2313689606
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3383402811
Short name T961
Test name
Test status
Simulation time 244996074 ps
CPU time 1.47 seconds
Started Mar 05 12:44:05 PM PST 24
Finished Mar 05 12:44:07 PM PST 24
Peak memory 214368 kb
Host smart-e81cda4c-6f37-4fb1-911d-f4699dc16fe4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383402811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3383402811
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.3476191886
Short name T238
Test name
Test status
Simulation time 428575443 ps
CPU time 1.55 seconds
Started Mar 05 12:44:00 PM PST 24
Finished Mar 05 12:44:02 PM PST 24
Peak memory 206100 kb
Host smart-1bc6f7e0-beaf-407e-a55b-21d5c3bc75ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476191886 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.3476191886
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.2351338893
Short name T902
Test name
Test status
Simulation time 59958498 ps
CPU time 1.05 seconds
Started Mar 05 12:43:43 PM PST 24
Finished Mar 05 12:43:44 PM PST 24
Peak memory 214420 kb
Host smart-c01592ed-d2fb-432d-9fe6-df8463f18e37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351338893 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.2351338893
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.1920238297
Short name T212
Test name
Test status
Simulation time 22960204 ps
CPU time 0.93 seconds
Started Mar 05 12:43:54 PM PST 24
Finished Mar 05 12:43:55 PM PST 24
Peak memory 206204 kb
Host smart-84286182-ac79-41b4-b78d-ec2637fd6bb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920238297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.1920238297
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.1948161660
Short name T890
Test name
Test status
Simulation time 16089123 ps
CPU time 0.8 seconds
Started Mar 05 12:43:51 PM PST 24
Finished Mar 05 12:43:52 PM PST 24
Peak memory 206048 kb
Host smart-da7918b5-8575-4c24-b69f-f7dea29202d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948161660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.1948161660
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.348667819
Short name T895
Test name
Test status
Simulation time 19880004 ps
CPU time 1.2 seconds
Started Mar 05 12:43:52 PM PST 24
Finished Mar 05 12:43:53 PM PST 24
Peak memory 206104 kb
Host smart-56fc9dfc-594e-4bbf-b45d-53b79e97ff76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348667819 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.348667819
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1253634932
Short name T879
Test name
Test status
Simulation time 26741894 ps
CPU time 1.74 seconds
Started Mar 05 12:44:01 PM PST 24
Finished Mar 05 12:44:03 PM PST 24
Peak memory 214408 kb
Host smart-f40a1c98-27c4-4417-8796-5f343b959f4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253634932 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1253634932
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2049132062
Short name T892
Test name
Test status
Simulation time 58947457 ps
CPU time 1.46 seconds
Started Mar 05 12:43:55 PM PST 24
Finished Mar 05 12:43:56 PM PST 24
Peak memory 206148 kb
Host smart-ac827e8f-52a8-480c-8078-416ee760e023
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049132062 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2049132062
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2640393127
Short name T860
Test name
Test status
Simulation time 36135663 ps
CPU time 1.51 seconds
Started Mar 05 12:43:52 PM PST 24
Finished Mar 05 12:43:53 PM PST 24
Peak memory 214372 kb
Host smart-0c08dac5-e256-4a04-991b-5389a3436452
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640393127 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2640393127
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.3819637817
Short name T908
Test name
Test status
Simulation time 40563384 ps
CPU time 0.89 seconds
Started Mar 05 12:44:09 PM PST 24
Finished Mar 05 12:44:10 PM PST 24
Peak memory 206048 kb
Host smart-fb759b55-f6d1-468b-b7fd-1de4ad033624
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819637817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.3819637817
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3447815457
Short name T907
Test name
Test status
Simulation time 18807594 ps
CPU time 0.84 seconds
Started Mar 05 12:43:49 PM PST 24
Finished Mar 05 12:43:49 PM PST 24
Peak memory 205932 kb
Host smart-7203e293-8b14-4e53-a5a1-7b347c9614ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447815457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3447815457
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2567624000
Short name T942
Test name
Test status
Simulation time 100002764 ps
CPU time 1.27 seconds
Started Mar 05 12:43:47 PM PST 24
Finished Mar 05 12:43:48 PM PST 24
Peak memory 206208 kb
Host smart-2644c74a-5d44-4167-9725-00716395294b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567624000 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2567624000
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.3593588479
Short name T914
Test name
Test status
Simulation time 28259075 ps
CPU time 1.89 seconds
Started Mar 05 12:44:07 PM PST 24
Finished Mar 05 12:44:09 PM PST 24
Peak memory 214512 kb
Host smart-ceee0990-94bb-4fcc-be9e-712e102a784e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593588479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.3593588479
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.1099853320
Short name T245
Test name
Test status
Simulation time 344460790 ps
CPU time 2.47 seconds
Started Mar 05 12:43:54 PM PST 24
Finished Mar 05 12:43:56 PM PST 24
Peak memory 206192 kb
Host smart-5617305d-54bd-4c7a-bea1-232633ef7188
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099853320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.1099853320
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1342344152
Short name T840
Test name
Test status
Simulation time 77685274 ps
CPU time 1.42 seconds
Started Mar 05 12:43:58 PM PST 24
Finished Mar 05 12:44:05 PM PST 24
Peak memory 214480 kb
Host smart-4b5b6752-736e-4ede-83b5-a1d496c682aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342344152 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1342344152
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.2187650927
Short name T936
Test name
Test status
Simulation time 14165082 ps
CPU time 0.89 seconds
Started Mar 05 12:43:52 PM PST 24
Finished Mar 05 12:43:53 PM PST 24
Peak memory 206204 kb
Host smart-4f501eed-e90c-4e34-b63b-0d382b5791a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187650927 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.2187650927
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.4048301337
Short name T957
Test name
Test status
Simulation time 40907123 ps
CPU time 0.8 seconds
Started Mar 05 12:43:48 PM PST 24
Finished Mar 05 12:43:49 PM PST 24
Peak memory 206200 kb
Host smart-e22c95e1-7317-4005-bc74-00c8c620494e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048301337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.4048301337
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3224577088
Short name T925
Test name
Test status
Simulation time 34369080 ps
CPU time 1.13 seconds
Started Mar 05 12:43:52 PM PST 24
Finished Mar 05 12:43:53 PM PST 24
Peak memory 206192 kb
Host smart-5f180cd1-0e73-4b0c-8ac2-6da0d5f4c688
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224577088 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3224577088
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.570655909
Short name T877
Test name
Test status
Simulation time 90393830 ps
CPU time 2.74 seconds
Started Mar 05 12:43:44 PM PST 24
Finished Mar 05 12:43:47 PM PST 24
Peak memory 214556 kb
Host smart-7c89a980-9be8-481e-a36a-ac1deff4007e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570655909 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.570655909
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.965300770
Short name T945
Test name
Test status
Simulation time 117364632 ps
CPU time 2.93 seconds
Started Mar 05 12:43:47 PM PST 24
Finished Mar 05 12:43:51 PM PST 24
Peak memory 206264 kb
Host smart-2a4a4ca8-91b1-4855-99ec-f11db0485c24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965300770 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.965300770
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.2267974665
Short name T870
Test name
Test status
Simulation time 200150275 ps
CPU time 1.06 seconds
Started Mar 05 12:44:00 PM PST 24
Finished Mar 05 12:44:02 PM PST 24
Peak memory 214392 kb
Host smart-5f652a89-7c12-4b7b-880a-c736625a1590
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267974665 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.2267974665
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.2659601644
Short name T932
Test name
Test status
Simulation time 14266439 ps
CPU time 0.89 seconds
Started Mar 05 12:43:54 PM PST 24
Finished Mar 05 12:43:55 PM PST 24
Peak memory 206196 kb
Host smart-63d57aad-07e6-4073-91b4-b26e5f074ec1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659601644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.2659601644
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2355165726
Short name T949
Test name
Test status
Simulation time 19804420 ps
CPU time 0.81 seconds
Started Mar 05 12:43:53 PM PST 24
Finished Mar 05 12:43:54 PM PST 24
Peak memory 206056 kb
Host smart-bcb4976c-ae95-4416-93fa-908da788fe3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355165726 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2355165726
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.4071818360
Short name T903
Test name
Test status
Simulation time 20809861 ps
CPU time 1.15 seconds
Started Mar 05 12:43:59 PM PST 24
Finished Mar 05 12:44:01 PM PST 24
Peak memory 206200 kb
Host smart-ec0b692f-707b-484e-b556-1f1fc199e1f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071818360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.4071818360
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2342450189
Short name T930
Test name
Test status
Simulation time 78606668 ps
CPU time 2.86 seconds
Started Mar 05 12:44:01 PM PST 24
Finished Mar 05 12:44:04 PM PST 24
Peak memory 214680 kb
Host smart-e64a3072-33d2-40c4-89d8-b5516c947c58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342450189 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2342450189
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.2703162560
Short name T871
Test name
Test status
Simulation time 301091787 ps
CPU time 2.35 seconds
Started Mar 05 12:43:53 PM PST 24
Finished Mar 05 12:43:55 PM PST 24
Peak memory 206320 kb
Host smart-79331020-87bb-4ea0-89cc-0584dc6d92ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703162560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.2703162560
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3100816134
Short name T951
Test name
Test status
Simulation time 62288281 ps
CPU time 1 seconds
Started Mar 05 12:44:06 PM PST 24
Finished Mar 05 12:44:07 PM PST 24
Peak memory 206272 kb
Host smart-c8b4accd-0ab4-49bc-ac47-a26f29b57adf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100816134 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3100816134
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.295436856
Short name T229
Test name
Test status
Simulation time 27177470 ps
CPU time 0.79 seconds
Started Mar 05 12:43:54 PM PST 24
Finished Mar 05 12:43:55 PM PST 24
Peak memory 206040 kb
Host smart-54d983f9-4f94-45fd-9ea8-44828c90b3bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295436856 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.295436856
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.883124281
Short name T896
Test name
Test status
Simulation time 10628249 ps
CPU time 0.84 seconds
Started Mar 05 12:43:45 PM PST 24
Finished Mar 05 12:43:46 PM PST 24
Peak memory 206216 kb
Host smart-399674e6-c0eb-4144-956f-9e8eb5cc72f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883124281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.883124281
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.3412723678
Short name T937
Test name
Test status
Simulation time 100504000 ps
CPU time 1.12 seconds
Started Mar 05 12:44:00 PM PST 24
Finished Mar 05 12:44:02 PM PST 24
Peak memory 206216 kb
Host smart-c011534a-e263-48cc-bef7-b13ff0b71b9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412723678 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_o
utstanding.3412723678
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.3610521418
Short name T897
Test name
Test status
Simulation time 111660328 ps
CPU time 1.94 seconds
Started Mar 05 12:43:51 PM PST 24
Finished Mar 05 12:43:53 PM PST 24
Peak memory 214420 kb
Host smart-5ede4e67-c1c1-4f6a-a486-076c77107180
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610521418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.3610521418
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2254924593
Short name T859
Test name
Test status
Simulation time 114218300 ps
CPU time 1.79 seconds
Started Mar 05 12:44:00 PM PST 24
Finished Mar 05 12:44:02 PM PST 24
Peak memory 206268 kb
Host smart-5ca0127e-0c94-43fc-8563-8a063e4815bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254924593 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2254924593
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.2245541002
Short name T939
Test name
Test status
Simulation time 40873875 ps
CPU time 1.02 seconds
Started Mar 05 12:44:02 PM PST 24
Finished Mar 05 12:44:04 PM PST 24
Peak memory 206156 kb
Host smart-d162a7c7-282e-41bb-b62a-641451b4fa17
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245541002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.2245541002
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.1260660566
Short name T218
Test name
Test status
Simulation time 264296742 ps
CPU time 6.47 seconds
Started Mar 05 12:43:58 PM PST 24
Finished Mar 05 12:44:06 PM PST 24
Peak memory 206248 kb
Host smart-2e10e92a-f4e7-436f-b41c-8e7da08fe61c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260660566 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.1260660566
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.102100759
Short name T938
Test name
Test status
Simulation time 37554951 ps
CPU time 0.85 seconds
Started Mar 05 12:43:58 PM PST 24
Finished Mar 05 12:43:59 PM PST 24
Peak memory 206092 kb
Host smart-0303a23a-6e8f-410c-9209-31385052365e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102100759 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.102100759
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2892958299
Short name T861
Test name
Test status
Simulation time 77834714 ps
CPU time 1.14 seconds
Started Mar 05 12:43:56 PM PST 24
Finished Mar 05 12:43:57 PM PST 24
Peak memory 214568 kb
Host smart-42378289-8d8c-4871-9531-a8a8d4d80ab6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892958299 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2892958299
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1918527512
Short name T225
Test name
Test status
Simulation time 30267406 ps
CPU time 0.77 seconds
Started Mar 05 12:43:45 PM PST 24
Finished Mar 05 12:43:45 PM PST 24
Peak memory 206024 kb
Host smart-92fdda0d-1888-4881-b4cd-08f3ec5f4221
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918527512 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1918527512
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.2230110487
Short name T851
Test name
Test status
Simulation time 33069685 ps
CPU time 0.83 seconds
Started Mar 05 12:43:37 PM PST 24
Finished Mar 05 12:43:43 PM PST 24
Peak memory 206000 kb
Host smart-122a9de7-9b3b-4465-bd5a-de2f2b83bc98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230110487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.2230110487
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.4179903841
Short name T948
Test name
Test status
Simulation time 64413708 ps
CPU time 1.35 seconds
Started Mar 05 12:43:42 PM PST 24
Finished Mar 05 12:43:43 PM PST 24
Peak memory 206216 kb
Host smart-ec22a86a-237f-478b-84fa-d583641438ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179903841 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.4179903841
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.2680614716
Short name T889
Test name
Test status
Simulation time 171065889 ps
CPU time 1.96 seconds
Started Mar 05 12:43:59 PM PST 24
Finished Mar 05 12:44:02 PM PST 24
Peak memory 214576 kb
Host smart-c759e40f-aea8-4943-816c-71af5c4c562e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680614716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.2680614716
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3720370495
Short name T944
Test name
Test status
Simulation time 194448479 ps
CPU time 1.65 seconds
Started Mar 05 12:44:03 PM PST 24
Finished Mar 05 12:44:05 PM PST 24
Peak memory 206280 kb
Host smart-266b48c9-d7b5-4107-80c4-b68294667caf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720370495 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3720370495
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.49571885
Short name T854
Test name
Test status
Simulation time 156429723 ps
CPU time 0.85 seconds
Started Mar 05 12:43:58 PM PST 24
Finished Mar 05 12:43:59 PM PST 24
Peak memory 206204 kb
Host smart-621212fc-585e-4b18-ac41-854e7ebfe4a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49571885 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.49571885
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1038097448
Short name T863
Test name
Test status
Simulation time 44420530 ps
CPU time 0.82 seconds
Started Mar 05 12:43:46 PM PST 24
Finished Mar 05 12:43:47 PM PST 24
Peak memory 206208 kb
Host smart-deb29c2b-239e-462e-ad09-2be32b321e27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038097448 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1038097448
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1518081754
Short name T909
Test name
Test status
Simulation time 18575019 ps
CPU time 0.96 seconds
Started Mar 05 12:44:02 PM PST 24
Finished Mar 05 12:44:03 PM PST 24
Peak memory 206196 kb
Host smart-a9de0611-8827-46af-8b7b-00dcee1291e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518081754 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1518081754
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3208240676
Short name T856
Test name
Test status
Simulation time 26896736 ps
CPU time 0.84 seconds
Started Mar 05 12:44:01 PM PST 24
Finished Mar 05 12:44:02 PM PST 24
Peak memory 206200 kb
Host smart-260beebb-32e7-42d8-85a7-63458e33eec8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208240676 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3208240676
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1867439282
Short name T866
Test name
Test status
Simulation time 15901756 ps
CPU time 0.92 seconds
Started Mar 05 12:44:01 PM PST 24
Finished Mar 05 12:44:03 PM PST 24
Peak memory 206216 kb
Host smart-be8669e8-05ea-42f4-9916-740338cea5f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867439282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1867439282
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3076900129
Short name T845
Test name
Test status
Simulation time 19258454 ps
CPU time 0.87 seconds
Started Mar 05 12:43:51 PM PST 24
Finished Mar 05 12:43:52 PM PST 24
Peak memory 206204 kb
Host smart-96e86a5f-e95d-4d78-97c2-1b1ec2752c36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076900129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3076900129
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.1618097288
Short name T867
Test name
Test status
Simulation time 40769996 ps
CPU time 0.79 seconds
Started Mar 05 12:44:00 PM PST 24
Finished Mar 05 12:44:02 PM PST 24
Peak memory 206212 kb
Host smart-36816436-d2c0-4019-bd66-9e0ac425ef87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618097288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.1618097288
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.1176627720
Short name T953
Test name
Test status
Simulation time 40812448 ps
CPU time 0.77 seconds
Started Mar 05 12:43:46 PM PST 24
Finished Mar 05 12:43:47 PM PST 24
Peak memory 205940 kb
Host smart-06983c82-d8db-480c-8023-79b560697cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176627720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.1176627720
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.1188329928
Short name T943
Test name
Test status
Simulation time 121276157 ps
CPU time 0.89 seconds
Started Mar 05 12:44:10 PM PST 24
Finished Mar 05 12:44:11 PM PST 24
Peak memory 205948 kb
Host smart-929ffe81-6608-4386-ad66-7ff0a0c389b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188329928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.1188329928
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.1355318377
Short name T958
Test name
Test status
Simulation time 14931660 ps
CPU time 0.92 seconds
Started Mar 05 12:44:07 PM PST 24
Finished Mar 05 12:44:08 PM PST 24
Peak memory 206248 kb
Host smart-c6ed75aa-a5cc-45ed-96f4-b5e39fe49d9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355318377 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.1355318377
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.3485031928
Short name T222
Test name
Test status
Simulation time 115507662 ps
CPU time 1.17 seconds
Started Mar 05 12:43:46 PM PST 24
Finished Mar 05 12:43:47 PM PST 24
Peak memory 206268 kb
Host smart-1a723d4a-6bb0-4ffe-8f78-67d33354a704
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485031928 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.3485031928
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1981622577
Short name T935
Test name
Test status
Simulation time 173448334 ps
CPU time 1.95 seconds
Started Mar 05 12:43:41 PM PST 24
Finished Mar 05 12:43:43 PM PST 24
Peak memory 206216 kb
Host smart-c7236fa9-e9cb-4ce4-ac41-86b02e243885
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981622577 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1981622577
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.282438773
Short name T215
Test name
Test status
Simulation time 18028764 ps
CPU time 0.93 seconds
Started Mar 05 12:43:53 PM PST 24
Finished Mar 05 12:43:55 PM PST 24
Peak memory 206252 kb
Host smart-9aa86bfa-6e9e-4d22-b021-eee81fedfe90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282438773 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.282438773
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.1690494171
Short name T891
Test name
Test status
Simulation time 24527906 ps
CPU time 1.41 seconds
Started Mar 05 12:43:38 PM PST 24
Finished Mar 05 12:43:40 PM PST 24
Peak memory 214372 kb
Host smart-8c3ef3f7-d514-4c45-9c8b-31a724c7212f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690494171 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.1690494171
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.3217276309
Short name T219
Test name
Test status
Simulation time 17290847 ps
CPU time 0.97 seconds
Started Mar 05 12:44:01 PM PST 24
Finished Mar 05 12:44:03 PM PST 24
Peak memory 206196 kb
Host smart-84a3bb94-87d2-4a25-882c-51c0ba15ea27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217276309 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.3217276309
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.1933852118
Short name T862
Test name
Test status
Simulation time 16047157 ps
CPU time 0.82 seconds
Started Mar 05 12:43:42 PM PST 24
Finished Mar 05 12:43:43 PM PST 24
Peak memory 206112 kb
Host smart-882025bb-5f37-4cf4-9b0a-103aef6a09e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933852118 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.1933852118
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.3751206165
Short name T955
Test name
Test status
Simulation time 30926444 ps
CPU time 1.32 seconds
Started Mar 05 12:43:52 PM PST 24
Finished Mar 05 12:43:54 PM PST 24
Peak memory 206328 kb
Host smart-f1733c85-bf64-437f-8f52-2e0c381c867b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751206165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.3751206165
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2822210987
Short name T899
Test name
Test status
Simulation time 208552954 ps
CPU time 3.77 seconds
Started Mar 05 12:43:47 PM PST 24
Finished Mar 05 12:43:51 PM PST 24
Peak memory 214640 kb
Host smart-5f262eb7-2352-4112-b591-8f213b51ac17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822210987 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2822210987
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.1915677415
Short name T917
Test name
Test status
Simulation time 196473216 ps
CPU time 2.55 seconds
Started Mar 05 12:43:54 PM PST 24
Finished Mar 05 12:43:56 PM PST 24
Peak memory 206160 kb
Host smart-ba1cd735-8d5b-414c-8424-38b4603c1650
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915677415 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.1915677415
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.538946357
Short name T865
Test name
Test status
Simulation time 18191133 ps
CPU time 0.95 seconds
Started Mar 05 12:44:02 PM PST 24
Finished Mar 05 12:44:03 PM PST 24
Peak memory 206212 kb
Host smart-5d99ef1d-1a82-4461-8608-130c749ec871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538946357 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.538946357
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.2333219490
Short name T858
Test name
Test status
Simulation time 47542328 ps
CPU time 0.85 seconds
Started Mar 05 12:44:00 PM PST 24
Finished Mar 05 12:44:02 PM PST 24
Peak memory 206104 kb
Host smart-f93da202-a559-4e4d-8127-8c69bb8ba764
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333219490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.2333219490
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.1531051833
Short name T906
Test name
Test status
Simulation time 21839751 ps
CPU time 0.81 seconds
Started Mar 05 12:43:58 PM PST 24
Finished Mar 05 12:43:59 PM PST 24
Peak memory 206204 kb
Host smart-de965445-e801-4d5a-84ea-82a6e0f11577
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531051833 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.1531051833
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2186474482
Short name T887
Test name
Test status
Simulation time 16656406 ps
CPU time 0.92 seconds
Started Mar 05 12:44:06 PM PST 24
Finished Mar 05 12:44:07 PM PST 24
Peak memory 206100 kb
Host smart-bd958e64-4207-41d1-a899-a17c53f7d2b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186474482 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2186474482
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.3675071060
Short name T849
Test name
Test status
Simulation time 42587470 ps
CPU time 0.84 seconds
Started Mar 05 12:44:10 PM PST 24
Finished Mar 05 12:44:11 PM PST 24
Peak memory 205948 kb
Host smart-ac71b57e-3ad4-4dff-9367-6bc86e7420e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675071060 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.3675071060
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3477726936
Short name T950
Test name
Test status
Simulation time 14336657 ps
CPU time 0.87 seconds
Started Mar 05 12:44:00 PM PST 24
Finished Mar 05 12:44:02 PM PST 24
Peak memory 206208 kb
Host smart-dbedf107-3352-4ce8-876c-bde00d2778d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477726936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3477726936
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.4088196568
Short name T888
Test name
Test status
Simulation time 27335462 ps
CPU time 0.85 seconds
Started Mar 05 12:44:00 PM PST 24
Finished Mar 05 12:44:02 PM PST 24
Peak memory 206092 kb
Host smart-b0a5d8a8-6148-4907-bd74-e9a1cec5d84c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088196568 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.4088196568
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.4189921982
Short name T882
Test name
Test status
Simulation time 12576502 ps
CPU time 0.87 seconds
Started Mar 05 12:44:01 PM PST 24
Finished Mar 05 12:44:02 PM PST 24
Peak memory 206204 kb
Host smart-ac9c3f6a-bc1b-497b-ad2c-093843a00275
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189921982 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.4189921982
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.2176055789
Short name T940
Test name
Test status
Simulation time 25604116 ps
CPU time 0.91 seconds
Started Mar 05 12:43:56 PM PST 24
Finished Mar 05 12:43:57 PM PST 24
Peak memory 206156 kb
Host smart-5d54d9bf-8ad5-47a5-b044-3710b1e73667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176055789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.2176055789
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.251417794
Short name T844
Test name
Test status
Simulation time 30909691 ps
CPU time 0.81 seconds
Started Mar 05 12:44:15 PM PST 24
Finished Mar 05 12:44:16 PM PST 24
Peak memory 206116 kb
Host smart-1649405e-2791-4cc3-af41-7bd299b36ce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251417794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.251417794
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.249539124
Short name T921
Test name
Test status
Simulation time 74034724 ps
CPU time 1.1 seconds
Started Mar 05 12:43:49 PM PST 24
Finished Mar 05 12:43:50 PM PST 24
Peak memory 206076 kb
Host smart-0885edd2-9897-408f-afb2-3316b58c4c4c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249539124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.249539124
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.369270438
Short name T216
Test name
Test status
Simulation time 990346712 ps
CPU time 6.15 seconds
Started Mar 05 12:43:58 PM PST 24
Finished Mar 05 12:44:04 PM PST 24
Peak memory 206204 kb
Host smart-b9aa722a-af79-4bf8-95ec-50f0251204ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369270438 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.369270438
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.3166894504
Short name T886
Test name
Test status
Simulation time 30531566 ps
CPU time 0.82 seconds
Started Mar 05 12:43:50 PM PST 24
Finished Mar 05 12:43:51 PM PST 24
Peak memory 206160 kb
Host smart-571dcb20-a158-4d7d-9e65-ba5915b3090b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166894504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.3166894504
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.3312728505
Short name T924
Test name
Test status
Simulation time 26426591 ps
CPU time 1.07 seconds
Started Mar 05 12:43:52 PM PST 24
Finished Mar 05 12:43:53 PM PST 24
Peak memory 214348 kb
Host smart-d923f5c2-ae43-431f-9d19-d3cb763eeb54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312728505 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.3312728505
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2114700786
Short name T221
Test name
Test status
Simulation time 22450772 ps
CPU time 0.85 seconds
Started Mar 05 12:43:42 PM PST 24
Finished Mar 05 12:43:43 PM PST 24
Peak memory 206200 kb
Host smart-440fab84-36c2-4a29-a614-f401351abddd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114700786 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2114700786
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.1231234701
Short name T969
Test name
Test status
Simulation time 15512483 ps
CPU time 0.82 seconds
Started Mar 05 12:43:55 PM PST 24
Finished Mar 05 12:43:56 PM PST 24
Peak memory 206228 kb
Host smart-8a2ae904-a494-469c-9429-ef7943d116d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231234701 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.1231234701
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.148977208
Short name T947
Test name
Test status
Simulation time 14448243 ps
CPU time 0.92 seconds
Started Mar 05 12:43:50 PM PST 24
Finished Mar 05 12:43:52 PM PST 24
Peak memory 206276 kb
Host smart-0031c18a-218c-4cf8-ad3a-49323101176e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148977208 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_out
standing.148977208
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.3025565202
Short name T883
Test name
Test status
Simulation time 95979230 ps
CPU time 3.35 seconds
Started Mar 05 12:43:48 PM PST 24
Finished Mar 05 12:43:51 PM PST 24
Peak memory 214552 kb
Host smart-d59fccac-b9be-410c-a917-be5aab3f43f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025565202 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.3025565202
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1143811038
Short name T243
Test name
Test status
Simulation time 250795278 ps
CPU time 1.38 seconds
Started Mar 05 12:43:54 PM PST 24
Finished Mar 05 12:43:56 PM PST 24
Peak memory 206260 kb
Host smart-755dd69c-3a9e-45d4-a121-094de36240b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143811038 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1143811038
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.71798416
Short name T852
Test name
Test status
Simulation time 13271551 ps
CPU time 0.87 seconds
Started Mar 05 12:44:01 PM PST 24
Finished Mar 05 12:44:02 PM PST 24
Peak memory 206204 kb
Host smart-fbc7ece7-4148-4c88-a6f2-8259e353f283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71798416 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.71798416
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.413872139
Short name T838
Test name
Test status
Simulation time 25869250 ps
CPU time 0.95 seconds
Started Mar 05 12:44:18 PM PST 24
Finished Mar 05 12:44:19 PM PST 24
Peak memory 206216 kb
Host smart-d94b0534-b90b-4612-b658-c90aab8ced04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413872139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.413872139
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1907288154
Short name T912
Test name
Test status
Simulation time 13323030 ps
CPU time 0.87 seconds
Started Mar 05 12:43:55 PM PST 24
Finished Mar 05 12:43:56 PM PST 24
Peak memory 206252 kb
Host smart-6fe4f5af-9ec6-49e7-af39-c67514d1c35b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907288154 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1907288154
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2903220985
Short name T881
Test name
Test status
Simulation time 16309449 ps
CPU time 0.85 seconds
Started Mar 05 12:44:04 PM PST 24
Finished Mar 05 12:44:05 PM PST 24
Peak memory 206332 kb
Host smart-57c4801a-86af-42b4-b7fb-674150083fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903220985 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2903220985
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.2961512914
Short name T846
Test name
Test status
Simulation time 174489129 ps
CPU time 0.85 seconds
Started Mar 05 12:43:58 PM PST 24
Finished Mar 05 12:43:59 PM PST 24
Peak memory 206264 kb
Host smart-dedc6ebf-2d46-46f1-81f3-ac1fd73f9276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961512914 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.2961512914
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1744619721
Short name T841
Test name
Test status
Simulation time 103570590 ps
CPU time 0.88 seconds
Started Mar 05 12:44:01 PM PST 24
Finished Mar 05 12:44:02 PM PST 24
Peak memory 206052 kb
Host smart-9d5c9ed0-2818-41f2-9b19-5c592dc92e0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744619721 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1744619721
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.931114636
Short name T857
Test name
Test status
Simulation time 120889430 ps
CPU time 0.85 seconds
Started Mar 05 12:44:04 PM PST 24
Finished Mar 05 12:44:05 PM PST 24
Peak memory 206216 kb
Host smart-aec93ba7-1335-44f8-a999-3a2253af69e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931114636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.931114636
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1960838429
Short name T901
Test name
Test status
Simulation time 14268895 ps
CPU time 0.87 seconds
Started Mar 05 12:44:07 PM PST 24
Finished Mar 05 12:44:08 PM PST 24
Peak memory 206204 kb
Host smart-44894d5e-f0ca-4e21-a27c-efa216b8ceab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960838429 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1960838429
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.2870523160
Short name T898
Test name
Test status
Simulation time 13771177 ps
CPU time 0.88 seconds
Started Mar 05 12:44:01 PM PST 24
Finished Mar 05 12:44:02 PM PST 24
Peak memory 206208 kb
Host smart-5d19f8cc-c8b3-457a-a7e2-d2ccddb9eb7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870523160 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.2870523160
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1112358071
Short name T959
Test name
Test status
Simulation time 14240565 ps
CPU time 0.96 seconds
Started Mar 05 12:44:01 PM PST 24
Finished Mar 05 12:44:03 PM PST 24
Peak memory 206144 kb
Host smart-60e683c8-6a71-491c-ae1d-e1995e10d2af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112358071 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1112358071
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.2008729994
Short name T934
Test name
Test status
Simulation time 27092116 ps
CPU time 1.07 seconds
Started Mar 05 12:43:52 PM PST 24
Finished Mar 05 12:43:53 PM PST 24
Peak memory 214448 kb
Host smart-5129c1e2-3b89-46bd-9654-2c393471cbeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008729994 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.2008729994
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3907401767
Short name T211
Test name
Test status
Simulation time 21869955 ps
CPU time 0.88 seconds
Started Mar 05 12:43:46 PM PST 24
Finished Mar 05 12:43:47 PM PST 24
Peak memory 206320 kb
Host smart-705a081e-8498-4136-b60a-a75dfb80b01a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907401767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3907401767
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2724443714
Short name T855
Test name
Test status
Simulation time 18186200 ps
CPU time 0.92 seconds
Started Mar 05 12:43:50 PM PST 24
Finished Mar 05 12:43:52 PM PST 24
Peak memory 206116 kb
Host smart-a76b617e-fa8c-4621-af2f-247b786e58c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724443714 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2724443714
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.788968740
Short name T893
Test name
Test status
Simulation time 35659675 ps
CPU time 0.97 seconds
Started Mar 05 12:43:51 PM PST 24
Finished Mar 05 12:43:52 PM PST 24
Peak memory 206092 kb
Host smart-d082fddb-0b3f-4014-8ef0-9f1d4025ba50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788968740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_out
standing.788968740
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.4149765184
Short name T847
Test name
Test status
Simulation time 127891788 ps
CPU time 4.2 seconds
Started Mar 05 12:43:54 PM PST 24
Finished Mar 05 12:43:59 PM PST 24
Peak memory 214380 kb
Host smart-045f7aa3-c4d4-4aa3-a289-349fc8b70696
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149765184 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.4149765184
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.170135730
Short name T964
Test name
Test status
Simulation time 281656871 ps
CPU time 1.46 seconds
Started Mar 05 12:43:56 PM PST 24
Finished Mar 05 12:43:58 PM PST 24
Peak memory 206220 kb
Host smart-4a01102e-6aab-4d4d-a2c3-22a4bd0bde0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170135730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.170135730
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.1027536146
Short name T926
Test name
Test status
Simulation time 30141870 ps
CPU time 0.94 seconds
Started Mar 05 12:43:42 PM PST 24
Finished Mar 05 12:43:43 PM PST 24
Peak memory 206172 kb
Host smart-8cea74fa-cc90-45ac-b36d-7d5646abc680
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027536146 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.1027536146
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2838660039
Short name T226
Test name
Test status
Simulation time 16884039 ps
CPU time 0.91 seconds
Started Mar 05 12:43:44 PM PST 24
Finished Mar 05 12:43:45 PM PST 24
Peak memory 206096 kb
Host smart-bc2a09ce-440d-41df-8473-0ad6feede847
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838660039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2838660039
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.3187346166
Short name T878
Test name
Test status
Simulation time 40185525 ps
CPU time 0.8 seconds
Started Mar 05 12:43:48 PM PST 24
Finished Mar 05 12:43:49 PM PST 24
Peak memory 205932 kb
Host smart-556f342d-a5ed-4a26-b163-039c7e2376f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187346166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.3187346166
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.3548485531
Short name T230
Test name
Test status
Simulation time 23742280 ps
CPU time 1.15 seconds
Started Mar 05 12:43:43 PM PST 24
Finished Mar 05 12:43:44 PM PST 24
Peak memory 206288 kb
Host smart-4ae1f210-16c0-40fd-95d3-31592fc28013
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548485531 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.3548485531
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2250283666
Short name T876
Test name
Test status
Simulation time 121592346 ps
CPU time 2.97 seconds
Started Mar 05 12:43:54 PM PST 24
Finished Mar 05 12:43:57 PM PST 24
Peak memory 217672 kb
Host smart-b54c2be5-d451-4c70-8f48-69f01badaa8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250283666 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2250283666
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.899228636
Short name T868
Test name
Test status
Simulation time 427014727 ps
CPU time 1.65 seconds
Started Mar 05 12:43:54 PM PST 24
Finished Mar 05 12:43:56 PM PST 24
Peak memory 206188 kb
Host smart-d172905a-b191-467c-80a2-a6b8fd443845
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899228636 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.899228636
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2022936447
Short name T843
Test name
Test status
Simulation time 50797783 ps
CPU time 0.93 seconds
Started Mar 05 12:43:56 PM PST 24
Finished Mar 05 12:43:57 PM PST 24
Peak memory 206284 kb
Host smart-9992b3f9-8359-4081-9c61-3032f033053c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022936447 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2022936447
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3434316884
Short name T919
Test name
Test status
Simulation time 29600803 ps
CPU time 0.91 seconds
Started Mar 05 12:43:43 PM PST 24
Finished Mar 05 12:43:44 PM PST 24
Peak memory 206192 kb
Host smart-53c9e222-99d5-48ad-99e7-1ddcb8134fef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434316884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3434316884
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.4148462673
Short name T894
Test name
Test status
Simulation time 37398407 ps
CPU time 0.8 seconds
Started Mar 05 12:43:45 PM PST 24
Finished Mar 05 12:43:46 PM PST 24
Peak memory 206064 kb
Host smart-749601bb-0706-49d2-a536-5a45602fc99a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148462673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.4148462673
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.1110023417
Short name T213
Test name
Test status
Simulation time 86139742 ps
CPU time 1.46 seconds
Started Mar 05 12:43:54 PM PST 24
Finished Mar 05 12:44:01 PM PST 24
Peak memory 206248 kb
Host smart-7d5bba3a-cf9f-45f4-a34e-88b9a95afd31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110023417 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.1110023417
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.2488343513
Short name T916
Test name
Test status
Simulation time 331680050 ps
CPU time 2.1 seconds
Started Mar 05 12:43:33 PM PST 24
Finished Mar 05 12:43:36 PM PST 24
Peak memory 214496 kb
Host smart-8d65a811-2823-43ef-9b83-4c81d16da8c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488343513 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.2488343513
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.3935693408
Short name T956
Test name
Test status
Simulation time 404678293 ps
CPU time 1.47 seconds
Started Mar 05 12:43:36 PM PST 24
Finished Mar 05 12:43:37 PM PST 24
Peak memory 206268 kb
Host smart-98091810-0077-4b03-b700-c093f6d445d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935693408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.3935693408
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2836869299
Short name T873
Test name
Test status
Simulation time 15386447 ps
CPU time 0.95 seconds
Started Mar 05 12:43:47 PM PST 24
Finished Mar 05 12:43:48 PM PST 24
Peak memory 206288 kb
Host smart-1098c43f-9c44-4914-ba9c-94651a99bccb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836869299 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2836869299
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.192129884
Short name T913
Test name
Test status
Simulation time 51502240 ps
CPU time 0.89 seconds
Started Mar 05 12:43:53 PM PST 24
Finished Mar 05 12:43:54 PM PST 24
Peak memory 206244 kb
Host smart-8e2c70e6-897b-44df-8962-1f3ff01857bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192129884 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.192129884
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.2503715691
Short name T931
Test name
Test status
Simulation time 52045464 ps
CPU time 0.86 seconds
Started Mar 05 12:43:55 PM PST 24
Finished Mar 05 12:43:56 PM PST 24
Peak memory 206224 kb
Host smart-21a21d17-30c8-4716-912b-bd448d35ddd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503715691 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.2503715691
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.492814162
Short name T960
Test name
Test status
Simulation time 23454800 ps
CPU time 0.93 seconds
Started Mar 05 12:43:53 PM PST 24
Finished Mar 05 12:43:54 PM PST 24
Peak memory 206288 kb
Host smart-dc11520f-0add-4479-80bf-22725d5d9d67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492814162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_out
standing.492814162
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1661686800
Short name T850
Test name
Test status
Simulation time 96509569 ps
CPU time 1.9 seconds
Started Mar 05 12:44:05 PM PST 24
Finished Mar 05 12:44:08 PM PST 24
Peak memory 214472 kb
Host smart-2ccb1932-821c-4a8c-bf49-e5873d09a279
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661686800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1661686800
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2370158708
Short name T848
Test name
Test status
Simulation time 144125876 ps
CPU time 1.39 seconds
Started Mar 05 12:44:02 PM PST 24
Finished Mar 05 12:44:04 PM PST 24
Peak memory 206164 kb
Host smart-89e93f4b-d63f-49d8-92ce-6ff9ddd2aa06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370158708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2370158708
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1156484656
Short name T965
Test name
Test status
Simulation time 19203393 ps
CPU time 1.23 seconds
Started Mar 05 12:43:40 PM PST 24
Finished Mar 05 12:43:41 PM PST 24
Peak memory 214464 kb
Host smart-16276650-5527-418d-b3e0-5bcfb3ae25f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156484656 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1156484656
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.319545626
Short name T904
Test name
Test status
Simulation time 59314597 ps
CPU time 0.92 seconds
Started Mar 05 12:43:58 PM PST 24
Finished Mar 05 12:43:59 PM PST 24
Peak memory 206060 kb
Host smart-465476f0-3326-4754-ac17-9f9f65263fdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319545626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.319545626
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1146269166
Short name T922
Test name
Test status
Simulation time 29332142 ps
CPU time 0.76 seconds
Started Mar 05 12:43:57 PM PST 24
Finished Mar 05 12:43:58 PM PST 24
Peak memory 206056 kb
Host smart-f687f93c-8723-45d5-8a08-f7f402bad9bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146269166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1146269166
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.2089027066
Short name T910
Test name
Test status
Simulation time 136561855 ps
CPU time 1.35 seconds
Started Mar 05 12:43:56 PM PST 24
Finished Mar 05 12:43:58 PM PST 24
Peak memory 206300 kb
Host smart-76514ef1-8166-4567-b838-6a71e70fee95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089027066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.2089027066
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.770703302
Short name T864
Test name
Test status
Simulation time 329163578 ps
CPU time 2.06 seconds
Started Mar 05 12:44:01 PM PST 24
Finished Mar 05 12:44:04 PM PST 24
Peak memory 214368 kb
Host smart-f6856a7c-0d4d-4483-87d1-ce7781321b4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770703302 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.770703302
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.2850700447
Short name T970
Test name
Test status
Simulation time 144813468 ps
CPU time 1.45 seconds
Started Mar 05 12:44:02 PM PST 24
Finished Mar 05 12:44:04 PM PST 24
Peak memory 206224 kb
Host smart-2994e5ca-5365-4d0f-9326-7a4526b9d90f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850700447 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.2850700447
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert_test.3861358001
Short name T572
Test name
Test status
Simulation time 24986851 ps
CPU time 0.95 seconds
Started Mar 05 01:49:04 PM PST 24
Finished Mar 05 01:49:05 PM PST 24
Peak memory 206168 kb
Host smart-f4ada778-8002-4a76-b565-85b96d42d4ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861358001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.3861358001
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.2323934828
Short name T108
Test name
Test status
Simulation time 12457357 ps
CPU time 0.91 seconds
Started Mar 05 01:49:10 PM PST 24
Finished Mar 05 01:49:11 PM PST 24
Peak memory 215008 kb
Host smart-0309a73c-f6a7-45b0-be32-11490f246579
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323934828 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.2323934828
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.257896980
Short name T73
Test name
Test status
Simulation time 24799067 ps
CPU time 1.07 seconds
Started Mar 05 01:49:05 PM PST 24
Finished Mar 05 01:49:06 PM PST 24
Peak memory 215468 kb
Host smart-06147d48-94f7-4ef6-9c78-88ba7ce134ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257896980 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_dis
able_auto_req_mode.257896980
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.2018343654
Short name T684
Test name
Test status
Simulation time 29537717 ps
CPU time 0.86 seconds
Started Mar 05 01:48:58 PM PST 24
Finished Mar 05 01:48:59 PM PST 24
Peak memory 217268 kb
Host smart-19a0e1cd-55ae-459e-9673-4a6e35b9d00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018343654 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.2018343654
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.1859670334
Short name T818
Test name
Test status
Simulation time 28820743 ps
CPU time 1.26 seconds
Started Mar 05 01:48:58 PM PST 24
Finished Mar 05 01:49:00 PM PST 24
Peak memory 218240 kb
Host smart-c4e4354d-6947-4553-98e6-6428787852a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859670334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.1859670334
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1583831831
Short name T48
Test name
Test status
Simulation time 183171548 ps
CPU time 3.41 seconds
Started Mar 05 01:48:57 PM PST 24
Finished Mar 05 01:49:01 PM PST 24
Peak memory 234968 kb
Host smart-4122c852-c59d-4207-85f2-6b2c35f5a985
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583831831 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1583831831
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2229941458
Short name T300
Test name
Test status
Simulation time 30281534 ps
CPU time 0.93 seconds
Started Mar 05 01:49:00 PM PST 24
Finished Mar 05 01:49:01 PM PST 24
Peak memory 214444 kb
Host smart-af69bd5a-38dd-4c22-a633-2dfb619dce16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229941458 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2229941458
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.1562178644
Short name T383
Test name
Test status
Simulation time 837005110 ps
CPU time 3.74 seconds
Started Mar 05 01:48:53 PM PST 24
Finished Mar 05 01:48:58 PM PST 24
Peak memory 214548 kb
Host smart-04165845-6ee1-442a-ab3d-140edce543eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562178644 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.1562178644
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.729136095
Short name T636
Test name
Test status
Simulation time 260384417859 ps
CPU time 646.28 seconds
Started Mar 05 01:49:05 PM PST 24
Finished Mar 05 01:59:52 PM PST 24
Peak memory 218420 kb
Host smart-d162b3b3-6630-4722-8529-f3fe1a795508
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729136095 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.729136095
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert_test.3638008794
Short name T593
Test name
Test status
Simulation time 21325768 ps
CPU time 1 seconds
Started Mar 05 01:49:01 PM PST 24
Finished Mar 05 01:49:02 PM PST 24
Peak memory 206136 kb
Host smart-15909d78-d0f7-43f6-a3d0-e03dd0a12d40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638008794 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.3638008794
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.3638929728
Short name T821
Test name
Test status
Simulation time 39830227 ps
CPU time 1.28 seconds
Started Mar 05 01:49:07 PM PST 24
Finished Mar 05 01:49:09 PM PST 24
Peak memory 215560 kb
Host smart-cc66f069-e2d4-4fe9-95e0-8c06f381e7fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638929728 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.3638929728
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.2574678495
Short name T89
Test name
Test status
Simulation time 25128705 ps
CPU time 0.95 seconds
Started Mar 05 01:49:13 PM PST 24
Finished Mar 05 01:49:15 PM PST 24
Peak memory 217248 kb
Host smart-20ddc5c7-1461-4a42-957a-5876fd38dcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574678495 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.2574678495
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2545061362
Short name T701
Test name
Test status
Simulation time 51889288 ps
CPU time 1.45 seconds
Started Mar 05 01:49:02 PM PST 24
Finished Mar 05 01:49:03 PM PST 24
Peak memory 218120 kb
Host smart-9f669bbb-40ae-4a8f-af6f-579d544d9fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545061362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2545061362
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_sec_cm.3566288528
Short name T20
Test name
Test status
Simulation time 749844246 ps
CPU time 6.56 seconds
Started Mar 05 01:49:12 PM PST 24
Finished Mar 05 01:49:19 PM PST 24
Peak memory 235840 kb
Host smart-de58f2bc-973c-4b84-9d5f-8b9bfc20b834
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566288528 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.3566288528
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.800842174
Short name T361
Test name
Test status
Simulation time 16565056 ps
CPU time 1.02 seconds
Started Mar 05 01:49:02 PM PST 24
Finished Mar 05 01:49:03 PM PST 24
Peak memory 214476 kb
Host smart-63981d45-a7f8-483f-8ff1-5e48e729ceb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800842174 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.800842174
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.754287208
Short name T132
Test name
Test status
Simulation time 215278796 ps
CPU time 3.95 seconds
Started Mar 05 01:49:18 PM PST 24
Finished Mar 05 01:49:22 PM PST 24
Peak memory 215448 kb
Host smart-7222d8fb-fd04-4000-a71a-4fa1636edcdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754287208 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.754287208
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.2411874994
Short name T512
Test name
Test status
Simulation time 96836841624 ps
CPU time 2447.72 seconds
Started Mar 05 01:49:00 PM PST 24
Finished Mar 05 02:29:49 PM PST 24
Peak memory 230160 kb
Host smart-fd12482b-6754-40bc-992a-7c8f2b7d83cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411874994 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.2411874994
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1100338591
Short name T251
Test name
Test status
Simulation time 78267530 ps
CPU time 1.15 seconds
Started Mar 05 01:49:30 PM PST 24
Finished Mar 05 01:49:31 PM PST 24
Peak memory 214796 kb
Host smart-b5638c3c-08cb-41bf-bd3f-f28d3a78b3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100338591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1100338591
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_disable.239881022
Short name T548
Test name
Test status
Simulation time 16718154 ps
CPU time 0.85 seconds
Started Mar 05 01:49:40 PM PST 24
Finished Mar 05 01:49:41 PM PST 24
Peak memory 214952 kb
Host smart-40ed187c-5b3c-4841-8c5a-3998fe529acd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239881022 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.239881022
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_err.2648651950
Short name T109
Test name
Test status
Simulation time 18567821 ps
CPU time 1.16 seconds
Started Mar 05 01:49:33 PM PST 24
Finished Mar 05 01:49:34 PM PST 24
Peak memory 230572 kb
Host smart-5d980968-1d55-4b4c-8061-249237f3f7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648651950 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2648651950
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_intr.1316015440
Short name T129
Test name
Test status
Simulation time 27618587 ps
CPU time 0.92 seconds
Started Mar 05 01:49:33 PM PST 24
Finished Mar 05 01:49:34 PM PST 24
Peak memory 214908 kb
Host smart-17e907d1-db68-4cce-bed0-7cdd35539824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316015440 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.1316015440
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_stress_all.3415684998
Short name T455
Test name
Test status
Simulation time 97030215 ps
CPU time 2.5 seconds
Started Mar 05 01:49:30 PM PST 24
Finished Mar 05 01:49:33 PM PST 24
Peak memory 215420 kb
Host smart-f34c053c-f56e-4f76-b775-4c2cb42a1ce6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415684998 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3415684998
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1635422322
Short name T201
Test name
Test status
Simulation time 163879003405 ps
CPU time 1802.84 seconds
Started Mar 05 01:49:33 PM PST 24
Finished Mar 05 02:19:36 PM PST 24
Peak memory 224412 kb
Host smart-87708e98-15c1-40fd-9771-674ad7fff930
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635422322 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1635422322
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.1344579947
Short name T301
Test name
Test status
Simulation time 47819551 ps
CPU time 1.7 seconds
Started Mar 05 01:50:30 PM PST 24
Finished Mar 05 01:50:31 PM PST 24
Peak memory 215752 kb
Host smart-71d68008-5757-4c60-9c39-d2f8761a578d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344579947 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1344579947
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.3093428353
Short name T136
Test name
Test status
Simulation time 34064692 ps
CPU time 1.32 seconds
Started Mar 05 01:50:42 PM PST 24
Finished Mar 05 01:50:47 PM PST 24
Peak memory 217928 kb
Host smart-96ff5856-fd3f-45bd-8966-d5251e798bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093428353 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3093428353
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.180704961
Short name T808
Test name
Test status
Simulation time 58955775 ps
CPU time 1.47 seconds
Started Mar 05 01:50:40 PM PST 24
Finished Mar 05 01:50:41 PM PST 24
Peak memory 216836 kb
Host smart-9f1c83e3-1068-4c31-b7b8-1a7b87b651fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180704961 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.180704961
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.4268733662
Short name T318
Test name
Test status
Simulation time 40739016 ps
CPU time 1.41 seconds
Started Mar 05 01:50:45 PM PST 24
Finished Mar 05 01:50:51 PM PST 24
Peak memory 216172 kb
Host smart-5aafeea4-4aae-4b0b-a86d-72aad20e98ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268733662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.4268733662
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.308867239
Short name T638
Test name
Test status
Simulation time 81935787 ps
CPU time 1.68 seconds
Started Mar 05 01:50:38 PM PST 24
Finished Mar 05 01:50:40 PM PST 24
Peak memory 216932 kb
Host smart-ad9b5104-7e3b-42cb-bcc3-ba4f2765ddac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308867239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.308867239
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.871775526
Short name T397
Test name
Test status
Simulation time 49009819 ps
CPU time 1.19 seconds
Started Mar 05 01:50:41 PM PST 24
Finished Mar 05 01:50:45 PM PST 24
Peak memory 218428 kb
Host smart-697b1bda-1d99-4857-8467-31fbd772dd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871775526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.871775526
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.1676905572
Short name T284
Test name
Test status
Simulation time 95228195 ps
CPU time 1.34 seconds
Started Mar 05 01:50:35 PM PST 24
Finished Mar 05 01:50:36 PM PST 24
Peak memory 217092 kb
Host smart-6d2f4096-3fc2-4f49-8a77-a018ec1ba3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676905572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.1676905572
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.607028166
Short name T564
Test name
Test status
Simulation time 27377665 ps
CPU time 1.2 seconds
Started Mar 05 01:50:48 PM PST 24
Finished Mar 05 01:50:56 PM PST 24
Peak memory 215916 kb
Host smart-ad427e04-84f9-48e7-851f-b8e4e22392a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607028166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.607028166
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.1788702159
Short name T745
Test name
Test status
Simulation time 16462351 ps
CPU time 0.99 seconds
Started Mar 05 01:49:34 PM PST 24
Finished Mar 05 01:49:35 PM PST 24
Peak memory 205808 kb
Host smart-6d743494-889c-4903-b8fa-8e4d2a50c8b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788702159 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1788702159
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.1500854304
Short name T591
Test name
Test status
Simulation time 22839667 ps
CPU time 0.83 seconds
Started Mar 05 01:49:21 PM PST 24
Finished Mar 05 01:49:22 PM PST 24
Peak memory 214692 kb
Host smart-d97d2808-4ef0-4ea6-8af2-a8504d1b9b15
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500854304 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.1500854304
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_err.1863755661
Short name T769
Test name
Test status
Simulation time 22298387 ps
CPU time 1.26 seconds
Started Mar 05 01:49:34 PM PST 24
Finished Mar 05 01:49:35 PM PST 24
Peak memory 222448 kb
Host smart-42fe776d-d881-48f9-bbde-c5adab3a3ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863755661 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.1863755661
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_smoke.3289065712
Short name T539
Test name
Test status
Simulation time 18619469 ps
CPU time 0.98 seconds
Started Mar 05 01:49:32 PM PST 24
Finished Mar 05 01:49:33 PM PST 24
Peak memory 214476 kb
Host smart-0d265662-19d9-44c5-b2e6-41914c72820a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289065712 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.3289065712
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.4136444115
Short name T833
Test name
Test status
Simulation time 376215105 ps
CPU time 7.77 seconds
Started Mar 05 01:49:32 PM PST 24
Finished Mar 05 01:49:40 PM PST 24
Peak memory 215784 kb
Host smart-ab4ea70d-6898-45ff-b8e9-9c19b64ea1ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136444115 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.4136444115
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.913789180
Short name T197
Test name
Test status
Simulation time 222251584124 ps
CPU time 2565.66 seconds
Started Mar 05 01:49:27 PM PST 24
Finished Mar 05 02:32:13 PM PST 24
Peak memory 228068 kb
Host smart-8d9c6748-cbb0-4bea-a1f1-5a864a37381d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913789180 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.913789180
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.edn_genbits.2558432691
Short name T802
Test name
Test status
Simulation time 94582695 ps
CPU time 1.22 seconds
Started Mar 05 01:50:44 PM PST 24
Finished Mar 05 01:50:48 PM PST 24
Peak memory 215752 kb
Host smart-3c82d79d-1348-4b45-b222-bb096b026501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558432691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.2558432691
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2557987507
Short name T305
Test name
Test status
Simulation time 66162632 ps
CPU time 1.46 seconds
Started Mar 05 01:50:33 PM PST 24
Finished Mar 05 01:50:34 PM PST 24
Peak memory 216908 kb
Host smart-86c8f21b-bdee-46b4-b473-051c2dc240c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557987507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2557987507
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.1616038355
Short name T283
Test name
Test status
Simulation time 52726120 ps
CPU time 1.61 seconds
Started Mar 05 01:50:40 PM PST 24
Finished Mar 05 01:50:42 PM PST 24
Peak memory 215772 kb
Host smart-2fdc90eb-5dda-44e6-b2ce-c0d5835b73e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616038355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.1616038355
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.2587943523
Short name T441
Test name
Test status
Simulation time 49411731 ps
CPU time 0.99 seconds
Started Mar 05 01:50:40 PM PST 24
Finished Mar 05 01:50:41 PM PST 24
Peak memory 217136 kb
Host smart-6230fbd3-0910-4265-95e6-6d90a3673b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587943523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.2587943523
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.359773906
Short name T537
Test name
Test status
Simulation time 61737457 ps
CPU time 1.57 seconds
Started Mar 05 01:50:44 PM PST 24
Finished Mar 05 01:50:49 PM PST 24
Peak memory 216740 kb
Host smart-8206789e-0d1c-492e-ab6f-3537d9012305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359773906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.359773906
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.299613022
Short name T631
Test name
Test status
Simulation time 105056560 ps
CPU time 1.4 seconds
Started Mar 05 01:50:43 PM PST 24
Finished Mar 05 01:50:47 PM PST 24
Peak memory 217304 kb
Host smart-34206058-c828-49ef-836b-072e20267d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299613022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.299613022
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.1339294268
Short name T803
Test name
Test status
Simulation time 55557829 ps
CPU time 1.35 seconds
Started Mar 05 01:50:51 PM PST 24
Finished Mar 05 01:50:53 PM PST 24
Peak memory 218048 kb
Host smart-c713eca3-5271-4018-8dac-f5228a9bf6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339294268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.1339294268
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3700898211
Short name T787
Test name
Test status
Simulation time 62619525 ps
CPU time 1.39 seconds
Started Mar 05 01:50:33 PM PST 24
Finished Mar 05 01:50:34 PM PST 24
Peak memory 217128 kb
Host smart-418daf84-8acb-4bc9-bb03-647bfee98d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700898211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3700898211
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3614139280
Short name T710
Test name
Test status
Simulation time 76554645 ps
CPU time 1.1 seconds
Started Mar 05 01:50:45 PM PST 24
Finished Mar 05 01:50:50 PM PST 24
Peak memory 214520 kb
Host smart-ff2d4b09-c35a-4531-8f5a-ea2aef61d254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614139280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3614139280
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.4122456784
Short name T188
Test name
Test status
Simulation time 25185534 ps
CPU time 1.26 seconds
Started Mar 05 01:49:33 PM PST 24
Finished Mar 05 01:49:34 PM PST 24
Peak memory 214692 kb
Host smart-7ecea58c-6de5-428e-a7d7-050f3c22c5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122456784 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.4122456784
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.2412947055
Short name T328
Test name
Test status
Simulation time 13023330 ps
CPU time 0.93 seconds
Started Mar 05 01:49:20 PM PST 24
Finished Mar 05 01:49:21 PM PST 24
Peak memory 206136 kb
Host smart-aff58827-4175-4e21-a937-4996341bbe04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412947055 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.2412947055
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.1356766200
Short name T686
Test name
Test status
Simulation time 31903210 ps
CPU time 1.24 seconds
Started Mar 05 01:49:38 PM PST 24
Finished Mar 05 01:49:39 PM PST 24
Peak memory 218032 kb
Host smart-e3e2338e-ffaa-422f-90a9-962005601767
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356766200 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.1356766200
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.2655200050
Short name T420
Test name
Test status
Simulation time 18338286 ps
CPU time 1.17 seconds
Started Mar 05 01:49:19 PM PST 24
Finished Mar 05 01:49:21 PM PST 24
Peak memory 222464 kb
Host smart-1455e3cf-0566-42de-b778-7f43e43ecdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655200050 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.2655200050
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_intr.1076812013
Short name T122
Test name
Test status
Simulation time 25593532 ps
CPU time 0.97 seconds
Started Mar 05 01:49:37 PM PST 24
Finished Mar 05 01:49:38 PM PST 24
Peak memory 214772 kb
Host smart-52c017e9-d7ff-4cd6-901d-2847074987aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076812013 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.1076812013
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1559154068
Short name T562
Test name
Test status
Simulation time 17345408 ps
CPU time 1 seconds
Started Mar 05 01:49:24 PM PST 24
Finished Mar 05 01:49:25 PM PST 24
Peak memory 214328 kb
Host smart-55c90e0f-b5ef-4f51-a6d8-92496c841a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559154068 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1559154068
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.4175847821
Short name T421
Test name
Test status
Simulation time 30341696 ps
CPU time 1.08 seconds
Started Mar 05 01:49:30 PM PST 24
Finished Mar 05 01:49:32 PM PST 24
Peak memory 214488 kb
Host smart-dfb1c197-7e59-47a5-950f-204fd2af49d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175847821 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.4175847821
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.3345017018
Short name T24
Test name
Test status
Simulation time 130582682772 ps
CPU time 1068.68 seconds
Started Mar 05 01:49:28 PM PST 24
Finished Mar 05 02:07:17 PM PST 24
Peak memory 223056 kb
Host smart-793fd306-20a2-4f41-bba4-f2ffa2e070f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345017018 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.3345017018
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.3777976339
Short name T648
Test name
Test status
Simulation time 493230500 ps
CPU time 4.21 seconds
Started Mar 05 01:50:39 PM PST 24
Finished Mar 05 01:50:44 PM PST 24
Peak memory 217208 kb
Host smart-835f72f6-82bc-45aa-a817-4e21a9b2282b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777976339 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.3777976339
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.4038500481
Short name T433
Test name
Test status
Simulation time 79390237 ps
CPU time 1.12 seconds
Started Mar 05 01:50:42 PM PST 24
Finished Mar 05 01:50:47 PM PST 24
Peak memory 216980 kb
Host smart-9e08c31e-849b-4ad7-add8-a5b31fee1861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038500481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.4038500481
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.2215472737
Short name T541
Test name
Test status
Simulation time 84815015 ps
CPU time 1.01 seconds
Started Mar 05 01:50:39 PM PST 24
Finished Mar 05 01:50:41 PM PST 24
Peak memory 215860 kb
Host smart-a5d69499-36f4-437e-9619-8a4fdd434f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215472737 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.2215472737
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.1924959606
Short name T339
Test name
Test status
Simulation time 170442415 ps
CPU time 1.14 seconds
Started Mar 05 01:50:48 PM PST 24
Finished Mar 05 01:50:51 PM PST 24
Peak memory 215712 kb
Host smart-9d64f3e0-44db-4f48-b6e0-418b4265770b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924959606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.1924959606
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.3352589022
Short name T652
Test name
Test status
Simulation time 57601820 ps
CPU time 1.98 seconds
Started Mar 05 01:50:34 PM PST 24
Finished Mar 05 01:50:36 PM PST 24
Peak memory 217040 kb
Host smart-641d55d9-19a7-4102-8bc1-bd288509db81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352589022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3352589022
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.3376479221
Short name T436
Test name
Test status
Simulation time 63750102 ps
CPU time 1.58 seconds
Started Mar 05 01:50:42 PM PST 24
Finished Mar 05 01:50:47 PM PST 24
Peak memory 216980 kb
Host smart-1e339978-3aa7-41bc-b5cb-dcd6379db16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376479221 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3376479221
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.1418465081
Short name T34
Test name
Test status
Simulation time 158394193 ps
CPU time 1.56 seconds
Started Mar 05 01:50:30 PM PST 24
Finished Mar 05 01:50:31 PM PST 24
Peak memory 215476 kb
Host smart-697313ed-abc6-4c9d-b805-d3b8f2354f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418465081 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1418465081
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.198167789
Short name T334
Test name
Test status
Simulation time 243019082 ps
CPU time 1.27 seconds
Started Mar 05 01:50:41 PM PST 24
Finished Mar 05 01:50:45 PM PST 24
Peak memory 216000 kb
Host smart-4b748553-c066-478c-acee-51dc5e05b24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198167789 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.198167789
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.1782654376
Short name T141
Test name
Test status
Simulation time 30115108 ps
CPU time 1.33 seconds
Started Mar 05 01:49:30 PM PST 24
Finished Mar 05 01:49:32 PM PST 24
Peak memory 214792 kb
Host smart-8fb16e34-763d-4816-9f59-8f6829b5b3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782654376 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.1782654376
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.1223566164
Short name T464
Test name
Test status
Simulation time 54317248 ps
CPU time 0.93 seconds
Started Mar 05 01:49:24 PM PST 24
Finished Mar 05 01:49:25 PM PST 24
Peak memory 206172 kb
Host smart-f1424357-c6b9-4ae6-b5d3-072096e85d4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223566164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.1223566164
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.1573089880
Short name T683
Test name
Test status
Simulation time 56017393 ps
CPU time 1.21 seconds
Started Mar 05 01:49:27 PM PST 24
Finished Mar 05 01:49:28 PM PST 24
Peak memory 215760 kb
Host smart-2938015d-9b6d-4a40-b871-9eb6af68c928
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573089880 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.1573089880
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.6439986
Short name T70
Test name
Test status
Simulation time 65285256 ps
CPU time 1.04 seconds
Started Mar 05 01:49:19 PM PST 24
Finished Mar 05 01:49:21 PM PST 24
Peak memory 219008 kb
Host smart-f4a00652-c92f-4c60-92ea-8b1772fb407d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6439986 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.6439986
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.3123278677
Short name T731
Test name
Test status
Simulation time 71182785 ps
CPU time 1.47 seconds
Started Mar 05 01:49:35 PM PST 24
Finished Mar 05 01:49:37 PM PST 24
Peak memory 215892 kb
Host smart-43a0bd2e-0ae1-4719-a9f9-f38cf15eaa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123278677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.3123278677
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.3838372980
Short name T120
Test name
Test status
Simulation time 19770428 ps
CPU time 1.12 seconds
Started Mar 05 01:49:35 PM PST 24
Finished Mar 05 01:49:36 PM PST 24
Peak memory 214820 kb
Host smart-8c204874-ffba-4964-95a1-8f965a9060e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838372980 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.3838372980
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.282416426
Short name T338
Test name
Test status
Simulation time 42038175 ps
CPU time 0.91 seconds
Started Mar 05 01:49:34 PM PST 24
Finished Mar 05 01:49:35 PM PST 24
Peak memory 214560 kb
Host smart-3af1f5de-620c-465e-aada-1c4c3eac228f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282416426 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.282416426
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1002949124
Short name T741
Test name
Test status
Simulation time 530096589 ps
CPU time 3.39 seconds
Started Mar 05 01:49:33 PM PST 24
Finished Mar 05 01:49:37 PM PST 24
Peak memory 215584 kb
Host smart-ae3ef5ce-340a-4ab1-9a92-355372dbb771
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002949124 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1002949124
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.4084391013
Short name T23
Test name
Test status
Simulation time 381490347366 ps
CPU time 1378.21 seconds
Started Mar 05 01:49:25 PM PST 24
Finished Mar 05 02:12:23 PM PST 24
Peak memory 222836 kb
Host smart-99c71bcb-9362-4c75-8dfb-93ccd41db20f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084391013 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.4084391013
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.1293340483
Short name T616
Test name
Test status
Simulation time 77763888 ps
CPU time 1.31 seconds
Started Mar 05 01:50:50 PM PST 24
Finished Mar 05 01:50:52 PM PST 24
Peak memory 217096 kb
Host smart-3ea06f2e-b01c-4d5c-ba39-c3971cc62371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293340483 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.1293340483
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.1494372452
Short name T800
Test name
Test status
Simulation time 41675815 ps
CPU time 1.46 seconds
Started Mar 05 01:50:41 PM PST 24
Finished Mar 05 01:50:46 PM PST 24
Peak memory 217036 kb
Host smart-17de7feb-8f74-4625-b5a2-e7f1afe9107a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494372452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1494372452
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.3559686606
Short name T816
Test name
Test status
Simulation time 46807855 ps
CPU time 0.96 seconds
Started Mar 05 01:50:33 PM PST 24
Finished Mar 05 01:50:34 PM PST 24
Peak memory 215696 kb
Host smart-0b43a54d-6a71-4089-b3fd-6ec42c0330e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559686606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.3559686606
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.3334295898
Short name T425
Test name
Test status
Simulation time 82471076 ps
CPU time 1.17 seconds
Started Mar 05 01:50:45 PM PST 24
Finished Mar 05 01:50:50 PM PST 24
Peak memory 218628 kb
Host smart-4bf06eb5-205b-4cb9-954a-bba98717247a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334295898 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3334295898
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2289640790
Short name T721
Test name
Test status
Simulation time 63172343 ps
CPU time 1.31 seconds
Started Mar 05 01:50:37 PM PST 24
Finished Mar 05 01:50:39 PM PST 24
Peak memory 217148 kb
Host smart-56a02792-c626-4591-86fe-d65f4f983bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289640790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2289640790
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.958057791
Short name T293
Test name
Test status
Simulation time 32848302 ps
CPU time 1.27 seconds
Started Mar 05 01:50:42 PM PST 24
Finished Mar 05 01:50:45 PM PST 24
Peak memory 216852 kb
Host smart-93398eb6-3a56-4b1d-bafe-478feb31a085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958057791 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.958057791
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.2968219528
Short name T372
Test name
Test status
Simulation time 76178517 ps
CPU time 1.26 seconds
Started Mar 05 01:50:45 PM PST 24
Finished Mar 05 01:50:50 PM PST 24
Peak memory 216832 kb
Host smart-1a081c32-f0a3-4e9a-b165-b7701bcca156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968219528 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.2968219528
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1337924762
Short name T782
Test name
Test status
Simulation time 47224665 ps
CPU time 1.25 seconds
Started Mar 05 01:50:41 PM PST 24
Finished Mar 05 01:50:45 PM PST 24
Peak memory 216944 kb
Host smart-edd15ce3-e440-4dd5-ac57-9c08c5af3b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337924762 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1337924762
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.452814631
Short name T269
Test name
Test status
Simulation time 31878411 ps
CPU time 1.32 seconds
Started Mar 05 01:50:36 PM PST 24
Finished Mar 05 01:50:37 PM PST 24
Peak memory 217184 kb
Host smart-8df81160-bcf4-4670-b4f1-ac112b5ad711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452814631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.452814631
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.2756706634
Short name T490
Test name
Test status
Simulation time 75907804 ps
CPU time 1.44 seconds
Started Mar 05 01:50:45 PM PST 24
Finished Mar 05 01:50:50 PM PST 24
Peak memory 217420 kb
Host smart-0db59a79-3183-44fa-9634-c4edeb5e00d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756706634 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.2756706634
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.1826662803
Short name T142
Test name
Test status
Simulation time 43269241 ps
CPU time 1.17 seconds
Started Mar 05 01:49:37 PM PST 24
Finished Mar 05 01:49:38 PM PST 24
Peak memory 214860 kb
Host smart-163dd89f-61e1-4f5f-9292-d47d8862c3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826662803 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.1826662803
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.73664547
Short name T373
Test name
Test status
Simulation time 165050105 ps
CPU time 0.88 seconds
Started Mar 05 01:49:22 PM PST 24
Finished Mar 05 01:49:23 PM PST 24
Peak memory 206100 kb
Host smart-47261b93-d7d6-4108-9723-36117b7ae752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73664547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.73664547
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1043439862
Short name T27
Test name
Test status
Simulation time 12634616 ps
CPU time 0.89 seconds
Started Mar 05 01:49:36 PM PST 24
Finished Mar 05 01:49:37 PM PST 24
Peak memory 214720 kb
Host smart-57b6632f-c390-456c-a1a1-be541b1e9eeb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043439862 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1043439862
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_err.1062235436
Short name T394
Test name
Test status
Simulation time 19214711 ps
CPU time 1.17 seconds
Started Mar 05 01:49:30 PM PST 24
Finished Mar 05 01:49:31 PM PST 24
Peak memory 222392 kb
Host smart-c55a6601-c745-47c8-bc7b-6cad7fb13eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062235436 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1062235436
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.285973777
Short name T501
Test name
Test status
Simulation time 138869874 ps
CPU time 3.42 seconds
Started Mar 05 01:49:34 PM PST 24
Finished Mar 05 01:49:37 PM PST 24
Peak memory 216084 kb
Host smart-d98e997b-98ee-4168-9e44-aee6888a104f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285973777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.285973777
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.4135641428
Short name T118
Test name
Test status
Simulation time 27163091 ps
CPU time 0.88 seconds
Started Mar 05 01:49:22 PM PST 24
Finished Mar 05 01:49:23 PM PST 24
Peak memory 214748 kb
Host smart-7f1ed050-6ca7-466f-ab2f-a0ae5cf44acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135641428 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.4135641428
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2997618299
Short name T740
Test name
Test status
Simulation time 36972985 ps
CPU time 0.87 seconds
Started Mar 05 01:49:27 PM PST 24
Finished Mar 05 01:49:28 PM PST 24
Peak memory 214468 kb
Host smart-11cbd2d4-59f9-4c01-b9ab-829e4e9eab41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997618299 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2997618299
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1869376819
Short name T626
Test name
Test status
Simulation time 173435117 ps
CPU time 2.15 seconds
Started Mar 05 01:49:30 PM PST 24
Finished Mar 05 01:49:33 PM PST 24
Peak memory 214472 kb
Host smart-b4342f81-3a59-494d-b6fa-51d317f84573
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869376819 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1869376819
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.73880189
Short name T817
Test name
Test status
Simulation time 94113507175 ps
CPU time 225.82 seconds
Started Mar 05 01:49:27 PM PST 24
Finished Mar 05 01:53:14 PM PST 24
Peak memory 217028 kb
Host smart-7e971db1-da0b-47f7-8d31-13d6a6e491d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73880189 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.73880189
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.edn_genbits.1639131305
Short name T46
Test name
Test status
Simulation time 45925347 ps
CPU time 1.55 seconds
Started Mar 05 01:50:44 PM PST 24
Finished Mar 05 01:50:49 PM PST 24
Peak memory 215732 kb
Host smart-d22f0282-c2da-4eae-94bc-a239211f5a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639131305 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1639131305
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.19275785
Short name T670
Test name
Test status
Simulation time 42018454 ps
CPU time 1.61 seconds
Started Mar 05 01:50:41 PM PST 24
Finished Mar 05 01:50:44 PM PST 24
Peak memory 217188 kb
Host smart-c4c37d1a-4ef5-41cd-af2d-68bd9d7ae590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19275785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.19275785
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.278636715
Short name T578
Test name
Test status
Simulation time 165466245 ps
CPU time 3.19 seconds
Started Mar 05 01:51:04 PM PST 24
Finished Mar 05 01:51:08 PM PST 24
Peak memory 218424 kb
Host smart-dea70ca7-8621-49f9-8b0d-e243903d9f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278636715 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.278636715
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.864769730
Short name T608
Test name
Test status
Simulation time 76949801 ps
CPU time 1.09 seconds
Started Mar 05 01:50:41 PM PST 24
Finished Mar 05 01:50:45 PM PST 24
Peak memory 215584 kb
Host smart-8d045c30-c1e2-4078-8738-c2a6419bbe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864769730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.864769730
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.2721701963
Short name T312
Test name
Test status
Simulation time 89050656 ps
CPU time 1.24 seconds
Started Mar 05 01:50:42 PM PST 24
Finished Mar 05 01:50:47 PM PST 24
Peak memory 217148 kb
Host smart-078eea2d-0c38-4804-b29e-a6926cabe1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721701963 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2721701963
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.1952091253
Short name T280
Test name
Test status
Simulation time 195584124 ps
CPU time 1.35 seconds
Started Mar 05 01:50:50 PM PST 24
Finished Mar 05 01:50:56 PM PST 24
Peak memory 217060 kb
Host smart-3d4be64a-326a-4bdb-81b8-4dedfa6ad54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952091253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.1952091253
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.2134291475
Short name T538
Test name
Test status
Simulation time 24092178 ps
CPU time 1.23 seconds
Started Mar 05 01:50:51 PM PST 24
Finished Mar 05 01:50:53 PM PST 24
Peak memory 216932 kb
Host smart-91d05d2d-79c5-48db-aba7-29240e0059f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134291475 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.2134291475
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.1151153990
Short name T528
Test name
Test status
Simulation time 332675270 ps
CPU time 1.53 seconds
Started Mar 05 01:50:44 PM PST 24
Finished Mar 05 01:50:49 PM PST 24
Peak memory 215884 kb
Host smart-0fb1ec08-b636-44d6-b0fd-474a083fddd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151153990 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.1151153990
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2100182796
Short name T437
Test name
Test status
Simulation time 27065083 ps
CPU time 1.15 seconds
Started Mar 05 01:49:37 PM PST 24
Finished Mar 05 01:49:38 PM PST 24
Peak memory 214812 kb
Host smart-dd34731a-9996-42dc-ba39-39bafcdec191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100182796 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2100182796
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.86654836
Short name T329
Test name
Test status
Simulation time 41752224 ps
CPU time 0.82 seconds
Started Mar 05 01:49:50 PM PST 24
Finished Mar 05 01:49:51 PM PST 24
Peak memory 206124 kb
Host smart-d46292b0-f1e2-464e-96cf-1329779196a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86654836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.86654836
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable.624782180
Short name T477
Test name
Test status
Simulation time 11959910 ps
CPU time 0.82 seconds
Started Mar 05 01:49:46 PM PST 24
Finished Mar 05 01:49:47 PM PST 24
Peak memory 214736 kb
Host smart-87d577a0-c9fd-4a92-bb99-0da4181443f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624782180 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.624782180
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.1653092829
Short name T72
Test name
Test status
Simulation time 23935285 ps
CPU time 1.03 seconds
Started Mar 05 01:49:36 PM PST 24
Finished Mar 05 01:49:37 PM PST 24
Peak memory 216852 kb
Host smart-c6d17f17-71ae-43aa-a5a5-91b3a980ce1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653092829 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.1653092829
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2837551150
Short name T754
Test name
Test status
Simulation time 24370485 ps
CPU time 0.92 seconds
Started Mar 05 01:49:44 PM PST 24
Finished Mar 05 01:49:45 PM PST 24
Peak memory 217288 kb
Host smart-4f4b9f33-755f-4d7b-a9d1-3d2f89a67ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837551150 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2837551150
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.645339494
Short name T429
Test name
Test status
Simulation time 71234525 ps
CPU time 1.61 seconds
Started Mar 05 01:49:30 PM PST 24
Finished Mar 05 01:49:32 PM PST 24
Peak memory 218612 kb
Host smart-c7dbe7eb-4215-4169-880d-06f5ff7b28c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645339494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.645339494
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.2585016977
Short name T42
Test name
Test status
Simulation time 40412755 ps
CPU time 0.95 seconds
Started Mar 05 01:49:36 PM PST 24
Finished Mar 05 01:49:37 PM PST 24
Peak memory 222436 kb
Host smart-168a350b-43f1-4f00-9a6e-add80cda483e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585016977 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.2585016977
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.2195147786
Short name T582
Test name
Test status
Simulation time 76906778 ps
CPU time 0.93 seconds
Started Mar 05 01:49:19 PM PST 24
Finished Mar 05 01:49:20 PM PST 24
Peak memory 214480 kb
Host smart-0d3f09e4-6966-4d4a-af78-a64bb91c6017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195147786 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.2195147786
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.752036239
Short name T611
Test name
Test status
Simulation time 269054040 ps
CPU time 2.23 seconds
Started Mar 05 01:49:46 PM PST 24
Finished Mar 05 01:49:48 PM PST 24
Peak memory 215584 kb
Host smart-dd3d1df5-fd79-4506-b3ce-4da14bd829d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752036239 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.752036239
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.247995533
Short name T622
Test name
Test status
Simulation time 60393002277 ps
CPU time 803.96 seconds
Started Mar 05 01:49:46 PM PST 24
Finished Mar 05 02:03:10 PM PST 24
Peak memory 219372 kb
Host smart-d227dbf7-683f-40cc-8dc1-4da5f05cabf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247995533 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.247995533
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.2441835126
Short name T712
Test name
Test status
Simulation time 142022669 ps
CPU time 2.05 seconds
Started Mar 05 01:50:46 PM PST 24
Finished Mar 05 01:50:51 PM PST 24
Peak memory 216076 kb
Host smart-1193331e-bf67-48ef-97cb-8023228f39bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441835126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.2441835126
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.2591857118
Short name T743
Test name
Test status
Simulation time 160256974 ps
CPU time 2.1 seconds
Started Mar 05 01:51:07 PM PST 24
Finished Mar 05 01:51:09 PM PST 24
Peak memory 215708 kb
Host smart-98ae46e0-221c-43bb-b378-fce842d87cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591857118 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2591857118
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.3053680203
Short name T675
Test name
Test status
Simulation time 147451727 ps
CPU time 3.23 seconds
Started Mar 05 01:50:46 PM PST 24
Finished Mar 05 01:50:53 PM PST 24
Peak memory 215976 kb
Host smart-ad3e14db-235a-4514-9935-5c985a3ba2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053680203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.3053680203
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.1449550531
Short name T492
Test name
Test status
Simulation time 93320155 ps
CPU time 1.2 seconds
Started Mar 05 01:50:37 PM PST 24
Finished Mar 05 01:50:38 PM PST 24
Peak memory 218368 kb
Host smart-13143c54-cde9-49d3-b976-d3068dca9e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449550531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.1449550531
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.3639844487
Short name T768
Test name
Test status
Simulation time 79955391 ps
CPU time 1.13 seconds
Started Mar 05 01:50:48 PM PST 24
Finished Mar 05 01:50:51 PM PST 24
Peak memory 215580 kb
Host smart-041add48-446e-4208-b917-6e92e19d5b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639844487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3639844487
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.1794034176
Short name T450
Test name
Test status
Simulation time 78275163 ps
CPU time 1.29 seconds
Started Mar 05 01:50:57 PM PST 24
Finished Mar 05 01:50:58 PM PST 24
Peak memory 215840 kb
Host smart-84851273-e4c6-4ab2-9f49-16060dc70692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794034176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.1794034176
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.2395591396
Short name T516
Test name
Test status
Simulation time 108111143 ps
CPU time 1.32 seconds
Started Mar 05 01:50:45 PM PST 24
Finished Mar 05 01:50:51 PM PST 24
Peak memory 218352 kb
Host smart-bd44dada-fd49-4d62-84c2-76f23eb58bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395591396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.2395591396
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.3905033139
Short name T190
Test name
Test status
Simulation time 112403291 ps
CPU time 1.48 seconds
Started Mar 05 01:50:56 PM PST 24
Finished Mar 05 01:51:02 PM PST 24
Peak memory 217244 kb
Host smart-8bf95fd0-d97a-4680-802f-20eb348c0d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905033139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3905033139
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2027867664
Short name T521
Test name
Test status
Simulation time 90721866 ps
CPU time 1.33 seconds
Started Mar 05 01:50:54 PM PST 24
Finished Mar 05 01:50:55 PM PST 24
Peak memory 216972 kb
Host smart-8008cb7e-37d8-499d-8e69-6a35b1a992e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027867664 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2027867664
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.3798328112
Short name T349
Test name
Test status
Simulation time 99189031 ps
CPU time 1.17 seconds
Started Mar 05 01:50:52 PM PST 24
Finished Mar 05 01:50:54 PM PST 24
Peak memory 215700 kb
Host smart-8e817ef7-69de-46c1-87b3-47a02789ec6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798328112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3798328112
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.2891078126
Short name T144
Test name
Test status
Simulation time 98453681 ps
CPU time 1.23 seconds
Started Mar 05 01:49:30 PM PST 24
Finished Mar 05 01:49:31 PM PST 24
Peak memory 214860 kb
Host smart-e67e48c6-6030-47f3-b694-8aac1d8e5065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891078126 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.2891078126
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1205082894
Short name T307
Test name
Test status
Simulation time 29350531 ps
CPU time 0.78 seconds
Started Mar 05 01:49:42 PM PST 24
Finished Mar 05 01:49:43 PM PST 24
Peak memory 204964 kb
Host smart-21c1e8cc-6433-4ceb-aca8-9848e6776c6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205082894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1205082894
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1405194196
Short name T77
Test name
Test status
Simulation time 44323581 ps
CPU time 1.13 seconds
Started Mar 05 01:49:42 PM PST 24
Finished Mar 05 01:49:43 PM PST 24
Peak memory 215428 kb
Host smart-c5027771-55bf-4d0c-b8c7-c930bb59c312
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405194196 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1405194196
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.3731259774
Short name T50
Test name
Test status
Simulation time 31849349 ps
CPU time 0.88 seconds
Started Mar 05 01:49:34 PM PST 24
Finished Mar 05 01:49:35 PM PST 24
Peak memory 217136 kb
Host smart-99b6cf84-6876-4f28-9f7b-a324bce5312c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731259774 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.3731259774
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.473240282
Short name T3
Test name
Test status
Simulation time 64667266 ps
CPU time 1.21 seconds
Started Mar 05 01:49:47 PM PST 24
Finished Mar 05 01:49:48 PM PST 24
Peak memory 216896 kb
Host smart-46af2f1f-66ca-4008-a4bd-f0f9951ff5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473240282 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.473240282
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.1031393195
Short name T348
Test name
Test status
Simulation time 24745056 ps
CPU time 0.99 seconds
Started Mar 05 01:49:41 PM PST 24
Finished Mar 05 01:49:42 PM PST 24
Peak memory 214772 kb
Host smart-07a3957c-f025-4706-a3fd-fe8b9b93193b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031393195 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.1031393195
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.1714970541
Short name T825
Test name
Test status
Simulation time 17161030 ps
CPU time 0.98 seconds
Started Mar 05 01:49:36 PM PST 24
Finished Mar 05 01:49:37 PM PST 24
Peak memory 214464 kb
Host smart-a9142135-59c1-48ce-9846-1c7149de9826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714970541 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.1714970541
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.502726980
Short name T659
Test name
Test status
Simulation time 192446637950 ps
CPU time 1341.89 seconds
Started Mar 05 01:50:03 PM PST 24
Finished Mar 05 02:12:25 PM PST 24
Peak memory 223308 kb
Host smart-a7455c41-6eed-4306-b575-2179702719d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502726980 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.502726980
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.2600589307
Short name T797
Test name
Test status
Simulation time 57548908 ps
CPU time 1.42 seconds
Started Mar 05 01:50:45 PM PST 24
Finished Mar 05 01:50:50 PM PST 24
Peak memory 217268 kb
Host smart-e4087dc8-f0c0-48c3-a84a-8e79b754933c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600589307 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2600589307
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.849739270
Short name T194
Test name
Test status
Simulation time 41031354 ps
CPU time 1.17 seconds
Started Mar 05 01:50:44 PM PST 24
Finished Mar 05 01:50:49 PM PST 24
Peak memory 215744 kb
Host smart-ba31c0b2-6a22-4478-b6aa-79d79aea62b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849739270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.849739270
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.3019445196
Short name T409
Test name
Test status
Simulation time 40950467 ps
CPU time 1.35 seconds
Started Mar 05 01:50:44 PM PST 24
Finished Mar 05 01:50:49 PM PST 24
Peak memory 214464 kb
Host smart-f4cfbd16-e42b-4c7b-9ec1-1ef5c75f0c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019445196 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.3019445196
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.1656446695
Short name T54
Test name
Test status
Simulation time 54635714 ps
CPU time 1.17 seconds
Started Mar 05 01:50:40 PM PST 24
Finished Mar 05 01:50:42 PM PST 24
Peak memory 216908 kb
Host smart-ffb7d6ab-b206-4ed5-91ae-103aa48b5130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656446695 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1656446695
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.4277144856
Short name T52
Test name
Test status
Simulation time 64588509 ps
CPU time 1.17 seconds
Started Mar 05 01:51:09 PM PST 24
Finished Mar 05 01:51:10 PM PST 24
Peak memory 217072 kb
Host smart-869ae150-63ba-4b3d-b402-01b1602eefe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277144856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.4277144856
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.2079531452
Short name T837
Test name
Test status
Simulation time 87710743 ps
CPU time 1.52 seconds
Started Mar 05 01:50:57 PM PST 24
Finished Mar 05 01:50:58 PM PST 24
Peak memory 216860 kb
Host smart-29b66404-446b-4ef2-9101-8ce4151c4fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079531452 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2079531452
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.3301187108
Short name T836
Test name
Test status
Simulation time 245391170 ps
CPU time 1.25 seconds
Started Mar 05 01:50:56 PM PST 24
Finished Mar 05 01:50:57 PM PST 24
Peak memory 217112 kb
Host smart-bb6b5b0a-9732-47d2-95a1-93aa861ac260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301187108 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3301187108
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.4286487079
Short name T497
Test name
Test status
Simulation time 54174254 ps
CPU time 1.03 seconds
Started Mar 05 01:50:42 PM PST 24
Finished Mar 05 01:50:47 PM PST 24
Peak memory 215728 kb
Host smart-5bedce0d-a635-4f5a-a080-772ff80f06d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286487079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.4286487079
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.2309329406
Short name T588
Test name
Test status
Simulation time 26160595 ps
CPU time 1.12 seconds
Started Mar 05 01:50:45 PM PST 24
Finished Mar 05 01:50:50 PM PST 24
Peak memory 216880 kb
Host smart-585aa288-ca0c-4dbd-b805-7e29061cfc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309329406 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.2309329406
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.1939786450
Short name T254
Test name
Test status
Simulation time 44587600 ps
CPU time 1.29 seconds
Started Mar 05 01:49:37 PM PST 24
Finished Mar 05 01:49:39 PM PST 24
Peak memory 214856 kb
Host smart-7d50f53d-270c-4294-a068-232e95b6ca56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939786450 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.1939786450
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.776039162
Short name T491
Test name
Test status
Simulation time 54281528 ps
CPU time 0.93 seconds
Started Mar 05 01:49:43 PM PST 24
Finished Mar 05 01:49:44 PM PST 24
Peak memory 206144 kb
Host smart-9b6aefe5-62f2-41ae-a8c2-46a912e44b88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776039162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.776039162
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.3212877621
Short name T595
Test name
Test status
Simulation time 79960294 ps
CPU time 0.98 seconds
Started Mar 05 01:49:29 PM PST 24
Finished Mar 05 01:49:31 PM PST 24
Peak memory 215492 kb
Host smart-aacd2b7b-4f74-409c-bf39-a800b2dea0d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212877621 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_d
isable_auto_req_mode.3212877621
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.246096525
Short name T65
Test name
Test status
Simulation time 70808045 ps
CPU time 0.98 seconds
Started Mar 05 01:49:38 PM PST 24
Finished Mar 05 01:49:39 PM PST 24
Peak memory 215892 kb
Host smart-cb6d4614-dd14-425e-8f66-2e20f1dc0005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246096525 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.246096525
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.3605616514
Short name T182
Test name
Test status
Simulation time 40252203 ps
CPU time 1.49 seconds
Started Mar 05 01:49:33 PM PST 24
Finished Mar 05 01:49:35 PM PST 24
Peak memory 216952 kb
Host smart-c806a3d1-85c8-41ab-b8b3-1fc96c74c1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605616514 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.3605616514
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1539980116
Short name T722
Test name
Test status
Simulation time 22324919 ps
CPU time 0.93 seconds
Started Mar 05 01:49:42 PM PST 24
Finished Mar 05 01:49:43 PM PST 24
Peak memory 214736 kb
Host smart-5ab455f5-2c62-4f6e-b45f-e0c2b54e1ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539980116 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1539980116
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3150319630
Short name T517
Test name
Test status
Simulation time 16369563 ps
CPU time 1.02 seconds
Started Mar 05 01:49:35 PM PST 24
Finished Mar 05 01:49:36 PM PST 24
Peak memory 214532 kb
Host smart-d90ca9a0-decf-484e-b0f5-450a138400cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150319630 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3150319630
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3300264658
Short name T364
Test name
Test status
Simulation time 521661742 ps
CPU time 5.06 seconds
Started Mar 05 01:49:43 PM PST 24
Finished Mar 05 01:49:49 PM PST 24
Peak memory 214440 kb
Host smart-f4f134c5-7c92-4fa6-8000-491d9678315e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300264658 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3300264658
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.1299918099
Short name T460
Test name
Test status
Simulation time 79171069709 ps
CPU time 1641.26 seconds
Started Mar 05 01:49:40 PM PST 24
Finished Mar 05 02:17:02 PM PST 24
Peak memory 225324 kb
Host smart-62571dc8-629a-4f71-a7a6-a918ee67bda3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299918099 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.1299918099
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.4290349543
Short name T795
Test name
Test status
Simulation time 137910274 ps
CPU time 3.24 seconds
Started Mar 05 01:50:42 PM PST 24
Finished Mar 05 01:50:49 PM PST 24
Peak memory 218516 kb
Host smart-22171041-cf66-4b49-838f-c347921b2636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290349543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.4290349543
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.560793779
Short name T430
Test name
Test status
Simulation time 44754609 ps
CPU time 1.12 seconds
Started Mar 05 01:50:50 PM PST 24
Finished Mar 05 01:50:54 PM PST 24
Peak memory 215700 kb
Host smart-d1770c20-2239-4a84-9b68-839a40af1d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560793779 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.560793779
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.3747900426
Short name T542
Test name
Test status
Simulation time 47703031 ps
CPU time 1.06 seconds
Started Mar 05 01:51:29 PM PST 24
Finished Mar 05 01:51:31 PM PST 24
Peak memory 215640 kb
Host smart-921f431f-14f1-4ccd-a804-68aa3caa9f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747900426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3747900426
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.2371312851
Short name T189
Test name
Test status
Simulation time 49165939 ps
CPU time 1.49 seconds
Started Mar 05 01:50:43 PM PST 24
Finished Mar 05 01:50:47 PM PST 24
Peak memory 216860 kb
Host smart-53350c2b-014c-4a6e-baf7-53073176a42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371312851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2371312851
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.2987384155
Short name T767
Test name
Test status
Simulation time 177540233 ps
CPU time 1.06 seconds
Started Mar 05 01:50:46 PM PST 24
Finished Mar 05 01:50:50 PM PST 24
Peak memory 215768 kb
Host smart-26890971-d2b9-4a35-bd64-6113097c3bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987384155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.2987384155
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.336927229
Short name T494
Test name
Test status
Simulation time 29994106 ps
CPU time 1.29 seconds
Started Mar 05 01:50:44 PM PST 24
Finished Mar 05 01:50:49 PM PST 24
Peak memory 214528 kb
Host smart-00dd925c-5b4f-493f-a712-7962b134f8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336927229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.336927229
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.111715687
Short name T389
Test name
Test status
Simulation time 117820498 ps
CPU time 1.59 seconds
Started Mar 05 01:50:40 PM PST 24
Finished Mar 05 01:50:41 PM PST 24
Peak memory 217348 kb
Host smart-6af54a15-6880-4a25-86c5-96c0526d74c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111715687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.111715687
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.1926216703
Short name T415
Test name
Test status
Simulation time 38877340 ps
CPU time 1.03 seconds
Started Mar 05 01:50:59 PM PST 24
Finished Mar 05 01:51:00 PM PST 24
Peak memory 215780 kb
Host smart-0bc02d58-ada3-43d8-b27e-63ac6c265422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926216703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.1926216703
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.2997116742
Short name T534
Test name
Test status
Simulation time 184069226 ps
CPU time 1.07 seconds
Started Mar 05 01:50:44 PM PST 24
Finished Mar 05 01:50:49 PM PST 24
Peak memory 215784 kb
Host smart-940dc1fc-21b4-4d47-8c25-46f2460087e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997116742 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2997116742
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert_test.1251444626
Short name T363
Test name
Test status
Simulation time 234407540 ps
CPU time 0.98 seconds
Started Mar 05 01:49:47 PM PST 24
Finished Mar 05 01:49:48 PM PST 24
Peak memory 206156 kb
Host smart-3542b30e-e636-4d19-be46-9bb29e51e919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251444626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.1251444626
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.1961800100
Short name T155
Test name
Test status
Simulation time 12053863 ps
CPU time 0.85 seconds
Started Mar 05 01:49:48 PM PST 24
Finished Mar 05 01:49:49 PM PST 24
Peak memory 215008 kb
Host smart-da9474bc-f095-4599-b4ab-f898d5650d4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961800100 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.1961800100
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.4121584584
Short name T78
Test name
Test status
Simulation time 218550398 ps
CPU time 0.99 seconds
Started Mar 05 01:49:46 PM PST 24
Finished Mar 05 01:49:47 PM PST 24
Peak memory 215372 kb
Host smart-ce49a090-bd7f-422b-8479-5f7eb630fc8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121584584 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.4121584584
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.2178689483
Short name T663
Test name
Test status
Simulation time 18270998 ps
CPU time 1.04 seconds
Started Mar 05 01:49:29 PM PST 24
Finished Mar 05 01:49:30 PM PST 24
Peak memory 216936 kb
Host smart-97d088b4-e598-44ec-8f6c-803c5b054892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178689483 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.2178689483
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.4074284306
Short name T176
Test name
Test status
Simulation time 74833463 ps
CPU time 1.14 seconds
Started Mar 05 01:49:38 PM PST 24
Finished Mar 05 01:49:40 PM PST 24
Peak memory 215908 kb
Host smart-c6ffb67e-6621-4843-9a46-fcb916f97d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074284306 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.4074284306
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_intr.2355325363
Short name T793
Test name
Test status
Simulation time 23328505 ps
CPU time 1.21 seconds
Started Mar 05 01:49:48 PM PST 24
Finished Mar 05 01:49:50 PM PST 24
Peak memory 231856 kb
Host smart-7fe96ea6-fa0a-4011-901b-5fdd3d2e9cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355325363 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.2355325363
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/18.edn_smoke.4083184627
Short name T315
Test name
Test status
Simulation time 21426109 ps
CPU time 0.95 seconds
Started Mar 05 01:49:34 PM PST 24
Finished Mar 05 01:49:35 PM PST 24
Peak memory 214424 kb
Host smart-5c8e376a-61c8-4d98-b047-7965c9f21ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083184627 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.4083184627
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.4209344963
Short name T729
Test name
Test status
Simulation time 152605818 ps
CPU time 1.99 seconds
Started Mar 05 01:49:36 PM PST 24
Finished Mar 05 01:49:38 PM PST 24
Peak memory 215456 kb
Host smart-e4e8dc4a-1810-49c2-8abe-4b1f42af896a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209344963 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.4209344963
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.1083742395
Short name T738
Test name
Test status
Simulation time 78139089896 ps
CPU time 2054.18 seconds
Started Mar 05 01:49:45 PM PST 24
Finished Mar 05 02:24:00 PM PST 24
Peak memory 227208 kb
Host smart-5b6c87d4-c725-4bfd-a315-83b008b1b73c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083742395 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.1083742395
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.2686898768
Short name T484
Test name
Test status
Simulation time 106124394 ps
CPU time 2.64 seconds
Started Mar 05 01:50:38 PM PST 24
Finished Mar 05 01:50:50 PM PST 24
Peak memory 215968 kb
Host smart-4346b937-32e1-48b2-a635-bbda4250b16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686898768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2686898768
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.3370423326
Short name T314
Test name
Test status
Simulation time 42207611 ps
CPU time 1.21 seconds
Started Mar 05 01:50:44 PM PST 24
Finished Mar 05 01:50:49 PM PST 24
Peak memory 215864 kb
Host smart-437d94b5-28ef-447e-a31e-f3bdc34a36c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370423326 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.3370423326
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.2536333824
Short name T698
Test name
Test status
Simulation time 42453618 ps
CPU time 1.47 seconds
Started Mar 05 01:51:18 PM PST 24
Finished Mar 05 01:51:19 PM PST 24
Peak memory 216716 kb
Host smart-e2eb822d-d3d3-4ad3-855c-74b7fe23ac72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536333824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2536333824
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.4193190955
Short name T829
Test name
Test status
Simulation time 33787420 ps
CPU time 1.31 seconds
Started Mar 05 01:50:41 PM PST 24
Finished Mar 05 01:50:47 PM PST 24
Peak memory 215752 kb
Host smart-663cb5db-89a7-41ad-990c-1d40d94b559b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193190955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.4193190955
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.3749017783
Short name T635
Test name
Test status
Simulation time 72070203 ps
CPU time 1.11 seconds
Started Mar 05 01:50:45 PM PST 24
Finished Mar 05 01:50:50 PM PST 24
Peak memory 215212 kb
Host smart-234a96a4-fb12-41ff-ae67-10f22935d98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749017783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3749017783
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.490675890
Short name T820
Test name
Test status
Simulation time 134511615 ps
CPU time 3 seconds
Started Mar 05 01:50:44 PM PST 24
Finished Mar 05 01:50:51 PM PST 24
Peak memory 218700 kb
Host smart-c690af56-0e5b-4796-8a69-3df27a367beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490675890 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.490675890
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.3085548943
Short name T294
Test name
Test status
Simulation time 73349551 ps
CPU time 1.09 seconds
Started Mar 05 01:50:52 PM PST 24
Finished Mar 05 01:50:53 PM PST 24
Peak memory 217588 kb
Host smart-c7a1eedb-f1f9-45b7-a14d-e113bacce74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085548943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.3085548943
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.3457674273
Short name T488
Test name
Test status
Simulation time 56798687 ps
CPU time 1.3 seconds
Started Mar 05 01:50:48 PM PST 24
Finished Mar 05 01:50:51 PM PST 24
Peak memory 217164 kb
Host smart-546c9ec5-04d9-4884-90b0-40dff3e2ade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457674273 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.3457674273
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.192982403
Short name T695
Test name
Test status
Simulation time 79766089 ps
CPU time 1.17 seconds
Started Mar 05 01:50:58 PM PST 24
Finished Mar 05 01:50:59 PM PST 24
Peak memory 216028 kb
Host smart-36e2aecf-08d6-468f-9c26-5734b30b52b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192982403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.192982403
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.4197125304
Short name T451
Test name
Test status
Simulation time 45556351 ps
CPU time 1.16 seconds
Started Mar 05 01:50:44 PM PST 24
Finished Mar 05 01:50:49 PM PST 24
Peak memory 214448 kb
Host smart-29bad148-2568-43b4-95c9-d026e29c9639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197125304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.4197125304
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2723277321
Short name T93
Test name
Test status
Simulation time 23097765 ps
CPU time 1.1 seconds
Started Mar 05 01:49:42 PM PST 24
Finished Mar 05 01:49:44 PM PST 24
Peak memory 214816 kb
Host smart-d45c28a9-1b34-4682-8ffb-fd3f4950ac3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723277321 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2723277321
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.3990607969
Short name T467
Test name
Test status
Simulation time 13019449 ps
CPU time 0.86 seconds
Started Mar 05 01:49:49 PM PST 24
Finished Mar 05 01:49:50 PM PST 24
Peak memory 205272 kb
Host smart-e25c1bc5-eb74-4c4b-a3ca-37ff8f7a46e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990607969 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.3990607969
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_err.3213728253
Short name T435
Test name
Test status
Simulation time 28886645 ps
CPU time 0.88 seconds
Started Mar 05 01:49:30 PM PST 24
Finished Mar 05 01:49:31 PM PST 24
Peak memory 216744 kb
Host smart-98235720-9481-4420-8c5d-bb10acc8981f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213728253 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3213728253
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_intr.1202171787
Short name T624
Test name
Test status
Simulation time 22583271 ps
CPU time 1 seconds
Started Mar 05 01:49:37 PM PST 24
Finished Mar 05 01:49:38 PM PST 24
Peak memory 214764 kb
Host smart-6526ef14-dafb-4735-bd6b-d066c46e581f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202171787 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.1202171787
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.308150830
Short name T702
Test name
Test status
Simulation time 25994468 ps
CPU time 0.97 seconds
Started Mar 05 01:49:51 PM PST 24
Finished Mar 05 01:49:52 PM PST 24
Peak memory 214444 kb
Host smart-0704d1e3-d4a4-4ffa-b3e9-2ba150ca26e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308150830 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.308150830
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1983147189
Short name T653
Test name
Test status
Simulation time 393555119 ps
CPU time 2.65 seconds
Started Mar 05 01:49:43 PM PST 24
Finished Mar 05 01:49:46 PM PST 24
Peak memory 215700 kb
Host smart-ba543fa6-f038-4349-91b2-fc27348c502e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983147189 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1983147189
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3301536256
Short name T752
Test name
Test status
Simulation time 380825577014 ps
CPU time 1738.68 seconds
Started Mar 05 01:49:49 PM PST 24
Finished Mar 05 02:18:48 PM PST 24
Peak memory 223596 kb
Host smart-a6735e18-200d-4fee-b073-084b27092a61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301536256 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3301536256
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.1196977983
Short name T545
Test name
Test status
Simulation time 142887745 ps
CPU time 2.92 seconds
Started Mar 05 01:50:42 PM PST 24
Finished Mar 05 01:50:48 PM PST 24
Peak memory 218292 kb
Host smart-d5dca63c-f00b-43d8-b61f-3a3488de26bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196977983 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1196977983
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.58644011
Short name T330
Test name
Test status
Simulation time 55598315 ps
CPU time 1.37 seconds
Started Mar 05 01:50:52 PM PST 24
Finished Mar 05 01:50:53 PM PST 24
Peak memory 216080 kb
Host smart-bd777838-8c4b-4c8c-9ded-3a73d5cae800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58644011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.58644011
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.3888168510
Short name T274
Test name
Test status
Simulation time 103865472 ps
CPU time 1.3 seconds
Started Mar 05 01:50:52 PM PST 24
Finished Mar 05 01:50:54 PM PST 24
Peak memory 217420 kb
Host smart-664fc690-25f7-4bd3-871d-0130b9b69942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888168510 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.3888168510
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.2196279
Short name T377
Test name
Test status
Simulation time 46246124 ps
CPU time 1.49 seconds
Started Mar 05 01:51:00 PM PST 24
Finished Mar 05 01:51:01 PM PST 24
Peak memory 216760 kb
Host smart-8c39b7e6-26fb-4a2d-be62-d32227e23512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.2196279
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.646726325
Short name T279
Test name
Test status
Simulation time 51778430 ps
CPU time 1.25 seconds
Started Mar 05 01:50:57 PM PST 24
Finished Mar 05 01:50:58 PM PST 24
Peak memory 217300 kb
Host smart-fcbc9955-cec8-414f-bf58-d8a457492aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646726325 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.646726325
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.3483540838
Short name T567
Test name
Test status
Simulation time 39783466 ps
CPU time 1.36 seconds
Started Mar 05 01:50:45 PM PST 24
Finished Mar 05 01:50:50 PM PST 24
Peak memory 216712 kb
Host smart-7064acba-2a0d-4621-a8a7-8f7131bac69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483540838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.3483540838
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.1920985033
Short name T297
Test name
Test status
Simulation time 74937918 ps
CPU time 1.85 seconds
Started Mar 05 01:50:45 PM PST 24
Finished Mar 05 01:50:51 PM PST 24
Peak memory 218988 kb
Host smart-92089f7b-46b8-422b-97f8-bfac842d9358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920985033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1920985033
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.2151883821
Short name T609
Test name
Test status
Simulation time 71857813 ps
CPU time 1.06 seconds
Started Mar 05 01:50:46 PM PST 24
Finished Mar 05 01:50:50 PM PST 24
Peak memory 215844 kb
Host smart-c2d4a0b7-3d63-49be-acb8-866f1dd4aacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151883821 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.2151883821
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.594224280
Short name T763
Test name
Test status
Simulation time 35588089 ps
CPU time 1.54 seconds
Started Mar 05 01:50:45 PM PST 24
Finished Mar 05 01:50:50 PM PST 24
Peak memory 216328 kb
Host smart-289a8b99-0021-4453-b25e-86dc372d4390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594224280 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.594224280
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.1162356206
Short name T645
Test name
Test status
Simulation time 95861103 ps
CPU time 1.13 seconds
Started Mar 05 01:50:44 PM PST 24
Finished Mar 05 01:50:49 PM PST 24
Peak memory 215724 kb
Host smart-0f0d818d-302d-40c8-a1a2-41ae5ff7655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162356206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1162356206
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.2693687874
Short name T428
Test name
Test status
Simulation time 66484034 ps
CPU time 1.27 seconds
Started Mar 05 01:49:08 PM PST 24
Finished Mar 05 01:49:10 PM PST 24
Peak memory 214864 kb
Host smart-a3281355-132f-4a5b-8c81-f770fa04397a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693687874 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.2693687874
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2372982346
Short name T440
Test name
Test status
Simulation time 18432070 ps
CPU time 0.94 seconds
Started Mar 05 01:49:09 PM PST 24
Finished Mar 05 01:49:10 PM PST 24
Peak memory 205292 kb
Host smart-72dc54d6-1b31-41e0-b0fd-069b45b7b084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372982346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2372982346
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.3002102075
Short name T195
Test name
Test status
Simulation time 12019998 ps
CPU time 0.95 seconds
Started Mar 05 01:48:59 PM PST 24
Finished Mar 05 01:49:00 PM PST 24
Peak memory 215076 kb
Host smart-8ee5902c-9715-440b-8c65-b456845437bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002102075 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.3002102075
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.164974492
Short name T744
Test name
Test status
Simulation time 68547334 ps
CPU time 1.25 seconds
Started Mar 05 01:49:15 PM PST 24
Finished Mar 05 01:49:17 PM PST 24
Peak memory 216800 kb
Host smart-7fde3cc6-f1e0-4a94-a127-3748071f642b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164974492 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_dis
able_auto_req_mode.164974492
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1495324700
Short name T660
Test name
Test status
Simulation time 38609540 ps
CPU time 0.83 seconds
Started Mar 05 01:49:05 PM PST 24
Finished Mar 05 01:49:06 PM PST 24
Peak memory 216836 kb
Host smart-0d853bae-f12b-430b-9f5f-fb28f438205e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495324700 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1495324700
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.2117473464
Short name T316
Test name
Test status
Simulation time 28817120 ps
CPU time 1.35 seconds
Started Mar 05 01:49:05 PM PST 24
Finished Mar 05 01:49:06 PM PST 24
Peak memory 217024 kb
Host smart-839a8b88-a799-42db-922f-7e0b30a114fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117473464 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2117473464
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.4169139266
Short name T706
Test name
Test status
Simulation time 22868711 ps
CPU time 1.13 seconds
Started Mar 05 01:49:02 PM PST 24
Finished Mar 05 01:49:03 PM PST 24
Peak memory 214588 kb
Host smart-977355de-7cc9-4a45-852e-595c9806ffb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169139266 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.4169139266
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_smoke.1166130589
Short name T716
Test name
Test status
Simulation time 16974466 ps
CPU time 1.02 seconds
Started Mar 05 01:49:06 PM PST 24
Finished Mar 05 01:49:07 PM PST 24
Peak memory 214508 kb
Host smart-4ffd31f4-6b01-4e89-aed7-f533df29298a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166130589 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.1166130589
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.1635169912
Short name T6
Test name
Test status
Simulation time 158568041 ps
CPU time 2.11 seconds
Started Mar 05 01:49:29 PM PST 24
Finished Mar 05 01:49:32 PM PST 24
Peak memory 216824 kb
Host smart-3d15e99a-c1f7-452c-9bbb-1298ace4fa13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635169912 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.1635169912
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.3110015089
Short name T644
Test name
Test status
Simulation time 35140221665 ps
CPU time 774.47 seconds
Started Mar 05 01:49:09 PM PST 24
Finished Mar 05 02:02:04 PM PST 24
Peak memory 216372 kb
Host smart-15e7f67e-2629-4633-b161-861c8ac1d384
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110015089 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.3110015089
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.1988530428
Short name T773
Test name
Test status
Simulation time 25549517 ps
CPU time 1.23 seconds
Started Mar 05 01:49:36 PM PST 24
Finished Mar 05 01:49:37 PM PST 24
Peak memory 214852 kb
Host smart-34fe5947-0b5d-4d07-a148-ed66bf2466bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988530428 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.1988530428
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.524354925
Short name T303
Test name
Test status
Simulation time 17965722 ps
CPU time 1.09 seconds
Started Mar 05 01:49:37 PM PST 24
Finished Mar 05 01:49:38 PM PST 24
Peak memory 206168 kb
Host smart-bf6fb3d1-0cb1-4188-86fd-09cc3f4c5dc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524354925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.524354925
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.1389459944
Short name T85
Test name
Test status
Simulation time 31337532 ps
CPU time 0.84 seconds
Started Mar 05 01:49:35 PM PST 24
Finished Mar 05 01:49:36 PM PST 24
Peak memory 214700 kb
Host smart-11a0eedc-0b95-4019-9fea-696414753a98
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389459944 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.1389459944
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.4011905294
Short name T207
Test name
Test status
Simulation time 60911330 ps
CPU time 1.12 seconds
Started Mar 05 01:49:44 PM PST 24
Finished Mar 05 01:49:45 PM PST 24
Peak memory 215532 kb
Host smart-dfd4059c-bd06-48d2-9fbf-4ba4ce316e43
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011905294 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_d
isable_auto_req_mode.4011905294
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/20.edn_err.2382048511
Short name T67
Test name
Test status
Simulation time 33260349 ps
CPU time 1.08 seconds
Started Mar 05 01:49:44 PM PST 24
Finished Mar 05 01:49:46 PM PST 24
Peak memory 215820 kb
Host smart-7882b630-93cb-4b0e-865a-57cb5233caa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382048511 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.2382048511
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.2821279796
Short name T405
Test name
Test status
Simulation time 34637668 ps
CPU time 1.32 seconds
Started Mar 05 01:49:46 PM PST 24
Finished Mar 05 01:49:48 PM PST 24
Peak memory 215712 kb
Host smart-d1f9e56e-0297-4b9c-8246-420be9e85ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821279796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.2821279796
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.609824215
Short name T632
Test name
Test status
Simulation time 24266896 ps
CPU time 0.93 seconds
Started Mar 05 01:49:37 PM PST 24
Finished Mar 05 01:49:38 PM PST 24
Peak memory 214600 kb
Host smart-dec7d521-482f-4d30-80b6-64d680927503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609824215 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.609824215
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.709515160
Short name T53
Test name
Test status
Simulation time 53441637 ps
CPU time 0.9 seconds
Started Mar 05 01:49:34 PM PST 24
Finished Mar 05 01:49:35 PM PST 24
Peak memory 214440 kb
Host smart-8526f4a5-7ecf-431a-8a2d-cd8fa36ee9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709515160 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.709515160
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.3198778469
Short name T618
Test name
Test status
Simulation time 417692612 ps
CPU time 4.45 seconds
Started Mar 05 01:49:33 PM PST 24
Finished Mar 05 01:49:38 PM PST 24
Peak memory 215464 kb
Host smart-a9a50a44-ad24-4625-be38-a7adcf11941d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198778469 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.3198778469
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2086633300
Short name T643
Test name
Test status
Simulation time 72781777547 ps
CPU time 1257.57 seconds
Started Mar 05 01:49:42 PM PST 24
Finished Mar 05 02:10:40 PM PST 24
Peak memory 220888 kb
Host smart-a904c79a-d549-47e9-bf6c-f7e670dee6a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086633300 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2086633300
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.213019258
Short name T520
Test name
Test status
Simulation time 154135782 ps
CPU time 3.17 seconds
Started Mar 05 01:50:47 PM PST 24
Finished Mar 05 01:50:53 PM PST 24
Peak memory 218720 kb
Host smart-0a990a47-05f2-4ca1-a54b-bd26056e3139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213019258 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.213019258
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3190707537
Short name T809
Test name
Test status
Simulation time 54611229 ps
CPU time 1.65 seconds
Started Mar 05 01:50:45 PM PST 24
Finished Mar 05 01:50:51 PM PST 24
Peak memory 216828 kb
Host smart-4267a121-d1c3-4d01-b69e-9f19981274f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190707537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3190707537
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.2568781488
Short name T398
Test name
Test status
Simulation time 33723821 ps
CPU time 1.04 seconds
Started Mar 05 01:51:03 PM PST 24
Finished Mar 05 01:51:04 PM PST 24
Peak memory 215584 kb
Host smart-96592987-21c6-418b-9f74-3616c39392f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568781488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.2568781488
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2832404165
Short name T678
Test name
Test status
Simulation time 73755402 ps
CPU time 1.46 seconds
Started Mar 05 01:50:47 PM PST 24
Finished Mar 05 01:50:51 PM PST 24
Peak memory 217164 kb
Host smart-dd51de7f-4cf6-456a-bfba-20b15296e57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832404165 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2832404165
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.1693458046
Short name T775
Test name
Test status
Simulation time 89896739 ps
CPU time 1.2 seconds
Started Mar 05 01:50:45 PM PST 24
Finished Mar 05 01:50:50 PM PST 24
Peak memory 217764 kb
Host smart-531d687a-6b5d-415b-af4e-bdd2fa0bee41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693458046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.1693458046
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.298602863
Short name T286
Test name
Test status
Simulation time 841353280 ps
CPU time 5.8 seconds
Started Mar 05 01:50:39 PM PST 24
Finished Mar 05 01:50:45 PM PST 24
Peak memory 218540 kb
Host smart-10aa692a-1697-4108-ba7e-f9f1484b57ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298602863 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.298602863
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.953049663
Short name T267
Test name
Test status
Simulation time 98818388 ps
CPU time 1.25 seconds
Started Mar 05 01:50:56 PM PST 24
Finished Mar 05 01:50:57 PM PST 24
Peak memory 218080 kb
Host smart-87a1bf9e-912e-48c0-8c7a-e5d500f8cb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953049663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.953049663
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.750866617
Short name T747
Test name
Test status
Simulation time 583669976 ps
CPU time 5.05 seconds
Started Mar 05 01:50:37 PM PST 24
Finished Mar 05 01:50:43 PM PST 24
Peak memory 216968 kb
Host smart-87fb5199-7143-4d4e-96d0-17b9bf7adb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750866617 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.750866617
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2863215193
Short name T605
Test name
Test status
Simulation time 23525735 ps
CPU time 1.28 seconds
Started Mar 05 01:50:44 PM PST 24
Finished Mar 05 01:50:49 PM PST 24
Peak memory 215704 kb
Host smart-9f225e02-c5ba-4d9d-a8d0-5156402a7df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863215193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2863215193
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.983280537
Short name T272
Test name
Test status
Simulation time 78231507 ps
CPU time 1.09 seconds
Started Mar 05 01:50:52 PM PST 24
Finished Mar 05 01:50:53 PM PST 24
Peak memory 215796 kb
Host smart-7fd5e67f-8a66-4cec-aa4b-c624b11d24b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983280537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.983280537
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert_test.3106189560
Short name T146
Test name
Test status
Simulation time 24531372 ps
CPU time 0.86 seconds
Started Mar 05 01:49:39 PM PST 24
Finished Mar 05 01:49:40 PM PST 24
Peak memory 206156 kb
Host smart-295f8990-eced-4429-8275-f4f92ba79e10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106189560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3106189560
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.121725779
Short name T691
Test name
Test status
Simulation time 37022186 ps
CPU time 0.85 seconds
Started Mar 05 01:49:47 PM PST 24
Finished Mar 05 01:49:48 PM PST 24
Peak memory 215084 kb
Host smart-a4fc0ffe-e79d-4e8f-954e-7987778a3000
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121725779 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.121725779
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_err.1085250569
Short name T708
Test name
Test status
Simulation time 22725638 ps
CPU time 1.15 seconds
Started Mar 05 01:49:33 PM PST 24
Finished Mar 05 01:49:34 PM PST 24
Peak memory 217352 kb
Host smart-2303b6e2-85d0-4547-8092-454a98ee771f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085250569 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1085250569
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.3423332255
Short name T422
Test name
Test status
Simulation time 174520530 ps
CPU time 1.09 seconds
Started Mar 05 01:49:48 PM PST 24
Finished Mar 05 01:49:49 PM PST 24
Peak memory 215640 kb
Host smart-738bea91-6359-4744-b947-6a0e7bb906e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423332255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.3423332255
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.1390964938
Short name T515
Test name
Test status
Simulation time 21957585 ps
CPU time 1.07 seconds
Started Mar 05 01:49:50 PM PST 24
Finished Mar 05 01:49:52 PM PST 24
Peak memory 214628 kb
Host smart-ef83c889-2eef-4abe-9103-311031fcff61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390964938 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.1390964938
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.94558266
Short name T21
Test name
Test status
Simulation time 18506323 ps
CPU time 0.99 seconds
Started Mar 05 01:49:51 PM PST 24
Finished Mar 05 01:49:52 PM PST 24
Peak memory 214384 kb
Host smart-3b88cb88-3fc7-4ea4-8ca7-422165fdce42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94558266 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.94558266
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.2026364016
Short name T713
Test name
Test status
Simulation time 174901958 ps
CPU time 3.12 seconds
Started Mar 05 01:49:49 PM PST 24
Finished Mar 05 01:49:53 PM PST 24
Peak memory 218364 kb
Host smart-47964d08-07ff-4a6f-8385-3f5ca1747504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026364016 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.2026364016
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.25409591
Short name T443
Test name
Test status
Simulation time 93241754571 ps
CPU time 1044.01 seconds
Started Mar 05 01:49:48 PM PST 24
Finished Mar 05 02:07:12 PM PST 24
Peak memory 222868 kb
Host smart-36813cb7-0ff3-4e72-a2ad-7207280bfc64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25409591 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.25409591
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1463266730
Short name T192
Test name
Test status
Simulation time 129359195 ps
CPU time 1.99 seconds
Started Mar 05 01:50:51 PM PST 24
Finished Mar 05 01:50:53 PM PST 24
Peak memory 217448 kb
Host smart-71913d93-7123-4944-9a62-8ae17aa52e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463266730 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1463266730
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.3568831449
Short name T139
Test name
Test status
Simulation time 40233442 ps
CPU time 1.45 seconds
Started Mar 05 01:50:45 PM PST 24
Finished Mar 05 01:50:51 PM PST 24
Peak memory 215728 kb
Host smart-35ef02b3-3906-43a0-86a8-c4a5e2231e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568831449 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.3568831449
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3543253078
Short name T761
Test name
Test status
Simulation time 47285696 ps
CPU time 1.51 seconds
Started Mar 05 01:50:52 PM PST 24
Finished Mar 05 01:50:54 PM PST 24
Peak memory 217172 kb
Host smart-22d0f3ed-1a2b-4e6c-b27f-55520f973cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543253078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3543253078
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.1062178124
Short name T610
Test name
Test status
Simulation time 44685602 ps
CPU time 1.55 seconds
Started Mar 05 01:50:45 PM PST 24
Finished Mar 05 01:50:51 PM PST 24
Peak memory 217948 kb
Host smart-0f505b03-798e-4dee-bc0e-552bbbea9ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062178124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.1062178124
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.1781237500
Short name T134
Test name
Test status
Simulation time 43746118 ps
CPU time 1.53 seconds
Started Mar 05 01:50:57 PM PST 24
Finished Mar 05 01:50:59 PM PST 24
Peak memory 215832 kb
Host smart-d7f2362f-1488-44e0-9e67-eb38903540be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781237500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.1781237500
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.3829070130
Short name T798
Test name
Test status
Simulation time 37959721 ps
CPU time 1.45 seconds
Started Mar 05 01:51:14 PM PST 24
Finished Mar 05 01:51:15 PM PST 24
Peak memory 215792 kb
Host smart-c79cd14d-0f84-431e-bfc5-e007920040d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829070130 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.3829070130
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2255809725
Short name T523
Test name
Test status
Simulation time 256082951 ps
CPU time 1.21 seconds
Started Mar 05 01:51:08 PM PST 24
Finished Mar 05 01:51:09 PM PST 24
Peak memory 217612 kb
Host smart-851ec445-ad5d-4b37-bd1c-ea7b17f38b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255809725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2255809725
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2509534100
Short name T273
Test name
Test status
Simulation time 39389820 ps
CPU time 1.57 seconds
Started Mar 05 01:51:04 PM PST 24
Finished Mar 05 01:51:05 PM PST 24
Peak memory 215736 kb
Host smart-0c6ff4cb-093a-446f-9382-9003c2778407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509534100 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2509534100
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.1095488407
Short name T264
Test name
Test status
Simulation time 75956997 ps
CPU time 1.79 seconds
Started Mar 05 01:51:13 PM PST 24
Finished Mar 05 01:51:15 PM PST 24
Peak memory 217176 kb
Host smart-21893c94-af71-43fd-aac5-9c2330fc3b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095488407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.1095488407
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.2878923176
Short name T513
Test name
Test status
Simulation time 54482998 ps
CPU time 1.76 seconds
Started Mar 05 01:50:52 PM PST 24
Finished Mar 05 01:50:55 PM PST 24
Peak memory 216976 kb
Host smart-37411c15-60ba-4bd6-91e9-d2d048f6e0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878923176 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2878923176
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert_test.1268913491
Short name T489
Test name
Test status
Simulation time 20247459 ps
CPU time 1.01 seconds
Started Mar 05 01:49:47 PM PST 24
Finished Mar 05 01:49:48 PM PST 24
Peak memory 205988 kb
Host smart-bcaa840c-7ae2-48db-b85b-995c367e58d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268913491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.1268913491
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3060805158
Short name T340
Test name
Test status
Simulation time 29179543 ps
CPU time 0.81 seconds
Started Mar 05 01:49:42 PM PST 24
Finished Mar 05 01:49:43 PM PST 24
Peak memory 214916 kb
Host smart-6d0c4455-7821-41fd-aa5f-e910c8b116b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060805158 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3060805158
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_err.1685687020
Short name T734
Test name
Test status
Simulation time 19437170 ps
CPU time 1.08 seconds
Started Mar 05 01:49:52 PM PST 24
Finished Mar 05 01:49:53 PM PST 24
Peak memory 222440 kb
Host smart-27ccfce7-57cb-460d-a07f-6deaa8d56bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685687020 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.1685687020
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.353613085
Short name T302
Test name
Test status
Simulation time 35422003 ps
CPU time 1.31 seconds
Started Mar 05 01:49:43 PM PST 24
Finished Mar 05 01:49:44 PM PST 24
Peak memory 215636 kb
Host smart-6054499a-26a8-4d7a-975d-43f3b4d43513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353613085 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.353613085
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.436172000
Short name T125
Test name
Test status
Simulation time 21432571 ps
CPU time 1.07 seconds
Started Mar 05 01:49:57 PM PST 24
Finished Mar 05 01:49:58 PM PST 24
Peak memory 214780 kb
Host smart-1f11ba46-a0d2-482b-8db5-3461765b08fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436172000 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.436172000
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3526950704
Short name T308
Test name
Test status
Simulation time 17627614 ps
CPU time 1 seconds
Started Mar 05 01:49:49 PM PST 24
Finished Mar 05 01:49:51 PM PST 24
Peak memory 214452 kb
Host smart-63ef1052-df21-41a9-9872-79c6746961f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526950704 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3526950704
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.3633211316
Short name T138
Test name
Test status
Simulation time 363740350 ps
CPU time 3.94 seconds
Started Mar 05 01:49:50 PM PST 24
Finished Mar 05 01:49:54 PM PST 24
Peak memory 215664 kb
Host smart-d9d695b0-4419-456e-a37f-7bf14e17c25e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633211316 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.3633211316
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2909786152
Short name T765
Test name
Test status
Simulation time 22415224269 ps
CPU time 510.39 seconds
Started Mar 05 01:49:45 PM PST 24
Finished Mar 05 01:58:17 PM PST 24
Peak memory 217108 kb
Host smart-48eaece6-c1b8-4475-98ea-1aa060ebad64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909786152 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2909786152
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.1463312381
Short name T614
Test name
Test status
Simulation time 25327489 ps
CPU time 1.1 seconds
Started Mar 05 01:50:42 PM PST 24
Finished Mar 05 01:50:47 PM PST 24
Peak memory 215528 kb
Host smart-aedd1ed6-dad5-4258-adc6-ca5dde3fa0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463312381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.1463312381
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.3898403315
Short name T585
Test name
Test status
Simulation time 99201276 ps
CPU time 1.08 seconds
Started Mar 05 01:50:55 PM PST 24
Finished Mar 05 01:50:56 PM PST 24
Peak memory 215712 kb
Host smart-c82c7d32-ca7c-4444-9811-f005bd42c8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898403315 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.3898403315
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3521090790
Short name T386
Test name
Test status
Simulation time 42303595 ps
CPU time 1.46 seconds
Started Mar 05 01:50:44 PM PST 24
Finished Mar 05 01:50:50 PM PST 24
Peak memory 216960 kb
Host smart-50c70fa7-21c4-4173-9a45-b6eba40fbae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521090790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3521090790
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.4018883982
Short name T290
Test name
Test status
Simulation time 52591460 ps
CPU time 1.79 seconds
Started Mar 05 01:50:57 PM PST 24
Finished Mar 05 01:50:59 PM PST 24
Peak memory 216836 kb
Host smart-58705c05-5c5c-484c-beaa-9336328b32e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018883982 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.4018883982
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3621623008
Short name T191
Test name
Test status
Simulation time 116045477 ps
CPU time 1.15 seconds
Started Mar 05 01:51:04 PM PST 24
Finished Mar 05 01:51:05 PM PST 24
Peak memory 218364 kb
Host smart-7f3de514-38fd-4d82-a755-a26b60ef602a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621623008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3621623008
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.814134680
Short name T414
Test name
Test status
Simulation time 74439257 ps
CPU time 1.17 seconds
Started Mar 05 01:51:01 PM PST 24
Finished Mar 05 01:51:02 PM PST 24
Peak memory 215628 kb
Host smart-34d683ae-7e87-44e8-ace6-b0ef85cf860d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814134680 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.814134680
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2079561893
Short name T356
Test name
Test status
Simulation time 164834295 ps
CPU time 1.76 seconds
Started Mar 05 01:50:51 PM PST 24
Finished Mar 05 01:50:53 PM PST 24
Peak memory 217888 kb
Host smart-7c8583c0-025b-40bd-b7fe-7aaf06b98b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079561893 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2079561893
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.197731265
Short name T365
Test name
Test status
Simulation time 36017658 ps
CPU time 1.07 seconds
Started Mar 05 01:51:12 PM PST 24
Finished Mar 05 01:51:13 PM PST 24
Peak memory 215672 kb
Host smart-2eb204ef-b33f-4146-b2cd-138beae94465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197731265 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.197731265
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.1134717623
Short name T370
Test name
Test status
Simulation time 45598047 ps
CPU time 1.79 seconds
Started Mar 05 01:50:44 PM PST 24
Finished Mar 05 01:50:49 PM PST 24
Peak memory 217084 kb
Host smart-8ab0b855-211e-400a-af7d-e67f0fac6ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134717623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.1134717623
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3709539000
Short name T830
Test name
Test status
Simulation time 80554447 ps
CPU time 1.48 seconds
Started Mar 05 01:51:00 PM PST 24
Finished Mar 05 01:51:02 PM PST 24
Peak memory 217296 kb
Host smart-b8cead9f-7ad4-4d30-b6aa-0c812ab305d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709539000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3709539000
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.3102206945
Short name T486
Test name
Test status
Simulation time 64467335 ps
CPU time 1.09 seconds
Started Mar 05 01:49:48 PM PST 24
Finished Mar 05 01:49:49 PM PST 24
Peak memory 214856 kb
Host smart-2082db97-7c80-481f-92a3-71fecb2e4c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102206945 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.3102206945
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.1681325559
Short name T306
Test name
Test status
Simulation time 16968381 ps
CPU time 0.92 seconds
Started Mar 05 01:49:43 PM PST 24
Finished Mar 05 01:49:44 PM PST 24
Peak memory 206168 kb
Host smart-bbdf14ff-c38f-419d-9bec-5f4108c3f114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681325559 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.1681325559
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.4012571865
Short name T90
Test name
Test status
Simulation time 89375078 ps
CPU time 0.84 seconds
Started Mar 05 01:49:47 PM PST 24
Finished Mar 05 01:49:48 PM PST 24
Peak memory 214872 kb
Host smart-703b4ab8-f993-46d4-9112-547eec866dd7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012571865 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.4012571865
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.3462025055
Short name T81
Test name
Test status
Simulation time 38677703 ps
CPU time 1.3 seconds
Started Mar 05 01:49:50 PM PST 24
Finished Mar 05 01:49:52 PM PST 24
Peak memory 215648 kb
Host smart-cf1a9151-4f4b-48cd-ba40-8ddd8979af4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462025055 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.3462025055
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/23.edn_err.227734393
Short name T753
Test name
Test status
Simulation time 58393945 ps
CPU time 0.9 seconds
Started Mar 05 01:49:42 PM PST 24
Finished Mar 05 01:49:43 PM PST 24
Peak memory 218464 kb
Host smart-13681588-65ad-499d-a682-b5f036e22bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227734393 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.227734393
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2615771935
Short name T811
Test name
Test status
Simulation time 39797631 ps
CPU time 1.27 seconds
Started Mar 05 01:49:51 PM PST 24
Finished Mar 05 01:49:52 PM PST 24
Peak memory 216696 kb
Host smart-4328aea6-8c28-4121-af72-28d83661a2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615771935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2615771935
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3303885198
Short name T114
Test name
Test status
Simulation time 60366674 ps
CPU time 0.87 seconds
Started Mar 05 01:49:46 PM PST 24
Finished Mar 05 01:49:47 PM PST 24
Peak memory 214516 kb
Host smart-3cd6362f-799d-40cc-afae-3490fa244c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303885198 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3303885198
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.2221866154
Short name T401
Test name
Test status
Simulation time 92859260 ps
CPU time 0.85 seconds
Started Mar 05 01:49:47 PM PST 24
Finished Mar 05 01:49:48 PM PST 24
Peak memory 214448 kb
Host smart-052c0d84-2548-42ac-bc0f-c69150e6c485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221866154 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.2221866154
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2255715263
Short name T746
Test name
Test status
Simulation time 190993604 ps
CPU time 4.12 seconds
Started Mar 05 01:49:45 PM PST 24
Finished Mar 05 01:49:49 PM PST 24
Peak memory 215412 kb
Host smart-dd244a11-0fb0-4cbd-be43-21558e7bf8ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255715263 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2255715263
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.920745821
Short name T474
Test name
Test status
Simulation time 243081727044 ps
CPU time 1662.95 seconds
Started Mar 05 01:49:41 PM PST 24
Finished Mar 05 02:17:24 PM PST 24
Peak memory 225352 kb
Host smart-825d2e40-bb43-447f-91fc-ad4a622de378
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920745821 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.920745821
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.927018313
Short name T473
Test name
Test status
Simulation time 51486215 ps
CPU time 0.96 seconds
Started Mar 05 01:50:46 PM PST 24
Finished Mar 05 01:50:50 PM PST 24
Peak memory 215656 kb
Host smart-9bffc6b7-86fa-460c-b739-21d15ce80178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927018313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.927018313
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.4197081795
Short name T382
Test name
Test status
Simulation time 40374286 ps
CPU time 1.48 seconds
Started Mar 05 01:50:50 PM PST 24
Finished Mar 05 01:50:52 PM PST 24
Peak memory 218440 kb
Host smart-a99eda0a-844b-4a36-867b-d324ac744c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197081795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.4197081795
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2813271166
Short name T463
Test name
Test status
Simulation time 330537549 ps
CPU time 1.33 seconds
Started Mar 05 01:50:58 PM PST 24
Finished Mar 05 01:50:59 PM PST 24
Peak memory 215844 kb
Host smart-f946e530-4d76-41a1-adc8-c87bba718ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813271166 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2813271166
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.2113999188
Short name T781
Test name
Test status
Simulation time 33076841 ps
CPU time 1.22 seconds
Started Mar 05 01:50:58 PM PST 24
Finished Mar 05 01:50:59 PM PST 24
Peak memory 216808 kb
Host smart-a4a05c79-fef2-4e52-a0e1-034b46c278f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113999188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.2113999188
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.106635662
Short name T524
Test name
Test status
Simulation time 46420583 ps
CPU time 1.29 seconds
Started Mar 05 01:51:13 PM PST 24
Finished Mar 05 01:51:15 PM PST 24
Peak memory 215728 kb
Host smart-18711deb-504c-4f53-b4db-7b0d9e2e8049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106635662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.106635662
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1304162094
Short name T788
Test name
Test status
Simulation time 34880854 ps
CPU time 1.78 seconds
Started Mar 05 01:51:08 PM PST 24
Finished Mar 05 01:51:10 PM PST 24
Peak memory 216984 kb
Host smart-2d4d40c1-b87d-49b2-b58b-d7a563081545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304162094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1304162094
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1963527792
Short name T590
Test name
Test status
Simulation time 32013143 ps
CPU time 1.51 seconds
Started Mar 05 01:51:03 PM PST 24
Finished Mar 05 01:51:04 PM PST 24
Peak memory 217020 kb
Host smart-c6a8416c-6200-4eeb-92cb-a12b0e92a791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963527792 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1963527792
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.674513072
Short name T406
Test name
Test status
Simulation time 36082326 ps
CPU time 1.23 seconds
Started Mar 05 01:50:57 PM PST 24
Finished Mar 05 01:50:58 PM PST 24
Peak memory 216912 kb
Host smart-55b27293-c6c8-41e3-a654-2abf92a48856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674513072 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.674513072
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.1601566570
Short name T601
Test name
Test status
Simulation time 63914175 ps
CPU time 1.34 seconds
Started Mar 05 01:50:56 PM PST 24
Finished Mar 05 01:50:58 PM PST 24
Peak memory 217012 kb
Host smart-a211f360-f720-4029-a303-2c6512d1a804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601566570 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.1601566570
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.183741244
Short name T662
Test name
Test status
Simulation time 94645686 ps
CPU time 1.53 seconds
Started Mar 05 01:50:49 PM PST 24
Finished Mar 05 01:50:51 PM PST 24
Peak memory 215904 kb
Host smart-05ea5df1-2ddb-4c8d-8388-6c0c943ef282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183741244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.183741244
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3970566758
Short name T257
Test name
Test status
Simulation time 139691493 ps
CPU time 1.33 seconds
Started Mar 05 01:49:43 PM PST 24
Finished Mar 05 01:49:44 PM PST 24
Peak memory 214844 kb
Host smart-6e5afecb-48d5-4a8b-860f-cc98be3e8876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970566758 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3970566758
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.1589445113
Short name T665
Test name
Test status
Simulation time 41179591 ps
CPU time 0.89 seconds
Started Mar 05 01:49:53 PM PST 24
Finished Mar 05 01:49:54 PM PST 24
Peak memory 205428 kb
Host smart-b345e11d-b0ab-4c2d-bcf2-6e92e5189070
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589445113 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1589445113
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.3741720393
Short name T465
Test name
Test status
Simulation time 24172164 ps
CPU time 0.89 seconds
Started Mar 05 01:49:45 PM PST 24
Finished Mar 05 01:49:46 PM PST 24
Peak memory 215048 kb
Host smart-b0e2400f-bd12-42d0-a154-0ed93c9cc93d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741720393 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.3741720393
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_err.337773766
Short name T76
Test name
Test status
Simulation time 52820324 ps
CPU time 1.1 seconds
Started Mar 05 01:49:50 PM PST 24
Finished Mar 05 01:49:52 PM PST 24
Peak memory 229052 kb
Host smart-b3504c3c-6d51-448d-9660-b40a63aa970f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337773766 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.337773766
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.3395483133
Short name T687
Test name
Test status
Simulation time 94148973 ps
CPU time 1.03 seconds
Started Mar 05 01:49:51 PM PST 24
Finished Mar 05 01:49:53 PM PST 24
Peak memory 215828 kb
Host smart-fe5fb769-49b6-4389-8707-3b65dc1e9de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395483133 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.3395483133
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.675253496
Short name T404
Test name
Test status
Simulation time 33319071 ps
CPU time 0.88 seconds
Started Mar 05 01:49:54 PM PST 24
Finished Mar 05 01:49:55 PM PST 24
Peak memory 214720 kb
Host smart-d837906d-6326-4f2d-8b91-080d367764ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675253496 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.675253496
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2122917775
Short name T447
Test name
Test status
Simulation time 123024231 ps
CPU time 0.93 seconds
Started Mar 05 01:49:43 PM PST 24
Finished Mar 05 01:49:44 PM PST 24
Peak memory 214316 kb
Host smart-1cf0e428-432a-469a-b284-bf62e948aa51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122917775 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2122917775
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.397310458
Short name T540
Test name
Test status
Simulation time 499066416 ps
CPU time 5.26 seconds
Started Mar 05 01:49:47 PM PST 24
Finished Mar 05 01:49:53 PM PST 24
Peak memory 215660 kb
Host smart-d6d5c891-00e7-4227-b64c-5db60b02c63a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397310458 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.397310458
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3449485043
Short name T203
Test name
Test status
Simulation time 6256781232 ps
CPU time 73.78 seconds
Started Mar 05 01:49:46 PM PST 24
Finished Mar 05 01:51:00 PM PST 24
Peak memory 217684 kb
Host smart-43b8fd89-000d-4364-8925-939c0c02b43b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449485043 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3449485043
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.1973503328
Short name T530
Test name
Test status
Simulation time 143862056 ps
CPU time 1.61 seconds
Started Mar 05 01:51:03 PM PST 24
Finished Mar 05 01:51:05 PM PST 24
Peak memory 217060 kb
Host smart-75368ec3-b4e4-48c6-8c2c-0293b29a1052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973503328 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.1973503328
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.289991543
Short name T762
Test name
Test status
Simulation time 41984014 ps
CPU time 1.44 seconds
Started Mar 05 01:50:57 PM PST 24
Finished Mar 05 01:50:58 PM PST 24
Peak memory 216852 kb
Host smart-4752fec3-d895-42c7-9d66-4b835a7b3bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289991543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.289991543
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/242.edn_genbits.3572093881
Short name T378
Test name
Test status
Simulation time 56491742 ps
CPU time 1.27 seconds
Started Mar 05 01:50:57 PM PST 24
Finished Mar 05 01:50:58 PM PST 24
Peak memory 215712 kb
Host smart-5a065ef4-a3cb-47ab-ae56-88f455a8ba21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572093881 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.3572093881
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.1127368669
Short name T650
Test name
Test status
Simulation time 74807747 ps
CPU time 1.24 seconds
Started Mar 05 01:51:18 PM PST 24
Finished Mar 05 01:51:19 PM PST 24
Peak memory 216956 kb
Host smart-71c39e19-1a0a-4bb1-b9f5-ace43d602297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127368669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.1127368669
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.309208205
Short name T749
Test name
Test status
Simulation time 41133978 ps
CPU time 1.77 seconds
Started Mar 05 01:51:13 PM PST 24
Finished Mar 05 01:51:15 PM PST 24
Peak memory 215924 kb
Host smart-522e96dc-1f7b-4bc1-a8ff-59f6bf416d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309208205 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.309208205
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2888238884
Short name T493
Test name
Test status
Simulation time 182822561 ps
CPU time 1.21 seconds
Started Mar 05 01:51:09 PM PST 24
Finished Mar 05 01:51:10 PM PST 24
Peak memory 217692 kb
Host smart-68eaa098-746a-488e-87bc-c91104494ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888238884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2888238884
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.2260273953
Short name T514
Test name
Test status
Simulation time 45860430 ps
CPU time 1.13 seconds
Started Mar 05 01:51:00 PM PST 24
Finished Mar 05 01:51:01 PM PST 24
Peak memory 215800 kb
Host smart-b5c134ec-b98b-4406-b849-7db62354d49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260273953 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.2260273953
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.490522991
Short name T823
Test name
Test status
Simulation time 963991825 ps
CPU time 6.99 seconds
Started Mar 05 01:50:55 PM PST 24
Finished Mar 05 01:51:02 PM PST 24
Peak memory 218460 kb
Host smart-d9c30311-8a20-424c-9a15-1e2fea1f7c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490522991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.490522991
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.375823058
Short name T799
Test name
Test status
Simulation time 100585467 ps
CPU time 1.24 seconds
Started Mar 05 01:51:04 PM PST 24
Finished Mar 05 01:51:06 PM PST 24
Peak memory 217260 kb
Host smart-302a30b3-8573-4412-bec4-45c0df3d1fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375823058 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.375823058
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2848493580
Short name T560
Test name
Test status
Simulation time 47705956 ps
CPU time 1.34 seconds
Started Mar 05 01:51:04 PM PST 24
Finished Mar 05 01:51:05 PM PST 24
Peak memory 218064 kb
Host smart-45813518-959e-417b-b160-4dadc991ba21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848493580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2848493580
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert_test.910566487
Short name T550
Test name
Test status
Simulation time 25212498 ps
CPU time 1.12 seconds
Started Mar 05 01:50:12 PM PST 24
Finished Mar 05 01:50:16 PM PST 24
Peak memory 206160 kb
Host smart-90d31b13-48f2-4518-aa47-4bd4634749e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910566487 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.910566487
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.1441506589
Short name T771
Test name
Test status
Simulation time 41299467 ps
CPU time 0.91 seconds
Started Mar 05 01:49:51 PM PST 24
Finished Mar 05 01:49:52 PM PST 24
Peak memory 214636 kb
Host smart-40454255-4338-4265-a6db-3ed4d468bc2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441506589 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1441506589
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_err.89083571
Short name T170
Test name
Test status
Simulation time 42205790 ps
CPU time 0.96 seconds
Started Mar 05 01:49:43 PM PST 24
Finished Mar 05 01:49:44 PM PST 24
Peak memory 230432 kb
Host smart-af77d94b-4497-4217-8f0a-41ec3475d550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89083571 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.89083571
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3435895561
Short name T581
Test name
Test status
Simulation time 38597392 ps
CPU time 1.67 seconds
Started Mar 05 01:49:59 PM PST 24
Finished Mar 05 01:50:01 PM PST 24
Peak memory 215708 kb
Host smart-7c61ddc4-ad71-4627-90fc-9bea9d5afba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435895561 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3435895561
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3081007373
Short name T655
Test name
Test status
Simulation time 27315360 ps
CPU time 0.98 seconds
Started Mar 05 01:50:05 PM PST 24
Finished Mar 05 01:50:07 PM PST 24
Peak memory 214736 kb
Host smart-5b598e2c-5f86-42fb-80cd-609da800e888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081007373 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3081007373
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2870253640
Short name T697
Test name
Test status
Simulation time 37030610 ps
CPU time 0.89 seconds
Started Mar 05 01:49:50 PM PST 24
Finished Mar 05 01:49:52 PM PST 24
Peak memory 214508 kb
Host smart-08d5be0a-cd39-4a8b-881f-12e47bbb6ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870253640 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2870253640
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3230794592
Short name T342
Test name
Test status
Simulation time 855934327 ps
CPU time 4.57 seconds
Started Mar 05 01:49:49 PM PST 24
Finished Mar 05 01:49:53 PM PST 24
Peak memory 214548 kb
Host smart-7bf9bb78-f5a8-4e84-98ba-7531f6f36d19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230794592 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3230794592
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.929079692
Short name T755
Test name
Test status
Simulation time 1071531920313 ps
CPU time 1392.17 seconds
Started Mar 05 01:50:04 PM PST 24
Finished Mar 05 02:13:16 PM PST 24
Peak memory 222956 kb
Host smart-a5ea306b-3273-4417-b03e-b36a43918d50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929079692 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.929079692
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.2213604871
Short name T282
Test name
Test status
Simulation time 60168117 ps
CPU time 1.06 seconds
Started Mar 05 01:51:04 PM PST 24
Finished Mar 05 01:51:05 PM PST 24
Peak memory 215756 kb
Host smart-5b5d1f5d-11a8-401a-b0f4-10e54d640b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213604871 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.2213604871
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.95992059
Short name T819
Test name
Test status
Simulation time 47788849 ps
CPU time 1.22 seconds
Started Mar 05 01:50:43 PM PST 24
Finished Mar 05 01:50:48 PM PST 24
Peak memory 215812 kb
Host smart-13bf1b7d-4514-4b02-bc4b-878a3f63006d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95992059 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.95992059
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.1525260225
Short name T296
Test name
Test status
Simulation time 66988210 ps
CPU time 2.43 seconds
Started Mar 05 01:50:56 PM PST 24
Finished Mar 05 01:50:58 PM PST 24
Peak memory 218748 kb
Host smart-538c1b4c-6fa9-4c80-be47-610b1b64bf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525260225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.1525260225
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3034792357
Short name T559
Test name
Test status
Simulation time 26772840 ps
CPU time 1.28 seconds
Started Mar 05 01:51:00 PM PST 24
Finished Mar 05 01:51:01 PM PST 24
Peak memory 216960 kb
Host smart-59570299-57ea-402a-b916-c05be319e3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034792357 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3034792357
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2323748164
Short name T323
Test name
Test status
Simulation time 64469550 ps
CPU time 1.04 seconds
Started Mar 05 01:50:49 PM PST 24
Finished Mar 05 01:50:51 PM PST 24
Peak memory 216836 kb
Host smart-82556f21-03df-4d82-9b80-f84498c25023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323748164 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2323748164
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3853864147
Short name T580
Test name
Test status
Simulation time 137791271 ps
CPU time 1.29 seconds
Started Mar 05 01:50:47 PM PST 24
Finished Mar 05 01:50:51 PM PST 24
Peak memory 214480 kb
Host smart-b5dad149-93a7-45d7-928d-3e8abd5347af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853864147 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3853864147
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.2983718778
Short name T291
Test name
Test status
Simulation time 67642787 ps
CPU time 1 seconds
Started Mar 05 01:50:55 PM PST 24
Finished Mar 05 01:50:56 PM PST 24
Peak memory 215544 kb
Host smart-2cfc2f01-27d5-41bf-953a-b527f32b2fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983718778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.2983718778
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.4018787609
Short name T639
Test name
Test status
Simulation time 28807134 ps
CPU time 1.4 seconds
Started Mar 05 01:51:13 PM PST 24
Finished Mar 05 01:51:15 PM PST 24
Peak memory 217056 kb
Host smart-3f4950e2-f5cd-47d4-9fd1-98fe96e94afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018787609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.4018787609
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3976935026
Short name T446
Test name
Test status
Simulation time 48418810 ps
CPU time 0.98 seconds
Started Mar 05 01:50:59 PM PST 24
Finished Mar 05 01:51:00 PM PST 24
Peak memory 215836 kb
Host smart-2ad8ddd4-3835-487a-9fe2-0cecfbea0c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976935026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3976935026
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.999829822
Short name T256
Test name
Test status
Simulation time 101383785 ps
CPU time 1.31 seconds
Started Mar 05 01:49:53 PM PST 24
Finished Mar 05 01:49:54 PM PST 24
Peak memory 214852 kb
Host smart-cace7253-1546-47a1-b348-98b6d32a86de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999829822 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.999829822
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.3377448651
Short name T759
Test name
Test status
Simulation time 55157563 ps
CPU time 0.89 seconds
Started Mar 05 01:50:01 PM PST 24
Finished Mar 05 01:50:02 PM PST 24
Peak memory 206148 kb
Host smart-f591171a-587a-4818-a05d-9664612aa78e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377448651 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.3377448651
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2778094751
Short name T168
Test name
Test status
Simulation time 20451057 ps
CPU time 0.86 seconds
Started Mar 05 01:49:48 PM PST 24
Finished Mar 05 01:49:49 PM PST 24
Peak memory 215064 kb
Host smart-4c2fe2ee-b191-49da-bbdf-f11efe5aebcf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778094751 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2778094751
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1621853607
Short name T789
Test name
Test status
Simulation time 118532741 ps
CPU time 0.99 seconds
Started Mar 05 01:49:50 PM PST 24
Finished Mar 05 01:49:51 PM PST 24
Peak memory 215588 kb
Host smart-b7933f6f-467f-439b-936b-6567e22a8218
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621853607 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1621853607
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.4207795678
Short name T766
Test name
Test status
Simulation time 29557527 ps
CPU time 1.23 seconds
Started Mar 05 01:49:51 PM PST 24
Finished Mar 05 01:49:53 PM PST 24
Peak memory 218524 kb
Host smart-139a08e0-80ef-4006-99f6-b6577130c34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207795678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.4207795678
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.93904614
Short name T657
Test name
Test status
Simulation time 296662860 ps
CPU time 1.9 seconds
Started Mar 05 01:49:53 PM PST 24
Finished Mar 05 01:49:55 PM PST 24
Peak memory 217168 kb
Host smart-ad87daf3-20c8-4be6-86fa-b88818c50ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93904614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.93904614
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2626692571
Short name T29
Test name
Test status
Simulation time 26960460 ps
CPU time 0.96 seconds
Started Mar 05 01:49:49 PM PST 24
Finished Mar 05 01:49:50 PM PST 24
Peak memory 214836 kb
Host smart-be91a42d-061d-4ef2-b7e3-971903989a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626692571 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2626692571
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.2059101734
Short name T371
Test name
Test status
Simulation time 25931733 ps
CPU time 0.94 seconds
Started Mar 05 01:49:48 PM PST 24
Finished Mar 05 01:49:49 PM PST 24
Peak memory 206256 kb
Host smart-4962f182-fbd2-4ea8-8149-8f0cb625bfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059101734 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.2059101734
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.1317380366
Short name T502
Test name
Test status
Simulation time 277931117 ps
CPU time 3.28 seconds
Started Mar 05 01:49:51 PM PST 24
Finished Mar 05 01:49:55 PM PST 24
Peak memory 215572 kb
Host smart-85a2b075-d258-42a5-8176-f3036e088bcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317380366 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.1317380366
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.3925503188
Short name T791
Test name
Test status
Simulation time 126283296881 ps
CPU time 533.37 seconds
Started Mar 05 01:49:51 PM PST 24
Finished Mar 05 01:58:45 PM PST 24
Peak memory 218004 kb
Host smart-31fb6ce3-36f8-4e24-a052-d83c77f17898
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925503188 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.3925503188
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.4074897818
Short name T569
Test name
Test status
Simulation time 53093628 ps
CPU time 1.68 seconds
Started Mar 05 01:51:20 PM PST 24
Finished Mar 05 01:51:22 PM PST 24
Peak memory 217820 kb
Host smart-ee483fd6-35ce-492e-96df-bd10aa124de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074897818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.4074897818
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3014586878
Short name T505
Test name
Test status
Simulation time 99402285 ps
CPU time 1.18 seconds
Started Mar 05 01:50:59 PM PST 24
Finished Mar 05 01:51:01 PM PST 24
Peak memory 215872 kb
Host smart-0d543708-624e-4893-a9ff-4337227e0d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014586878 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3014586878
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.2231773156
Short name T459
Test name
Test status
Simulation time 38578061 ps
CPU time 1.37 seconds
Started Mar 05 01:51:08 PM PST 24
Finished Mar 05 01:51:10 PM PST 24
Peak memory 215796 kb
Host smart-bcba5deb-458e-4b52-8d38-b51cc73a1d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231773156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.2231773156
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.3074949620
Short name T804
Test name
Test status
Simulation time 77683266 ps
CPU time 1.3 seconds
Started Mar 05 01:51:05 PM PST 24
Finished Mar 05 01:51:07 PM PST 24
Peak memory 217348 kb
Host smart-e2b04f91-a419-482c-ade7-72a0f94566ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074949620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.3074949620
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.415334888
Short name T281
Test name
Test status
Simulation time 63609459 ps
CPU time 2.33 seconds
Started Mar 05 01:51:19 PM PST 24
Finished Mar 05 01:51:21 PM PST 24
Peak memory 218556 kb
Host smart-69c2e54b-ad02-404d-aa37-70c48f9d86db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415334888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.415334888
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.2542472424
Short name T298
Test name
Test status
Simulation time 70756586 ps
CPU time 2.71 seconds
Started Mar 05 01:51:17 PM PST 24
Finished Mar 05 01:51:20 PM PST 24
Peak memory 217016 kb
Host smart-1f72a3a0-b044-4ae8-8640-5ebe6df5dcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542472424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.2542472424
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.4056674448
Short name T358
Test name
Test status
Simulation time 32666654 ps
CPU time 1.16 seconds
Started Mar 05 01:51:04 PM PST 24
Finished Mar 05 01:51:05 PM PST 24
Peak memory 215644 kb
Host smart-1c7615a6-128a-417e-9965-b5f21a7debb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056674448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.4056674448
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2510108599
Short name T183
Test name
Test status
Simulation time 27266791 ps
CPU time 1.15 seconds
Started Mar 05 01:51:00 PM PST 24
Finished Mar 05 01:51:01 PM PST 24
Peak memory 215784 kb
Host smart-3c3677c5-9655-4784-be05-495e90c7cf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510108599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2510108599
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.4107124175
Short name T792
Test name
Test status
Simulation time 36100879 ps
CPU time 1.47 seconds
Started Mar 05 01:51:07 PM PST 24
Finished Mar 05 01:51:09 PM PST 24
Peak memory 216776 kb
Host smart-cc585373-c756-49c6-914a-709a4eb03d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107124175 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.4107124175
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert_test.3490762413
Short name T620
Test name
Test status
Simulation time 59851956 ps
CPU time 0.88 seconds
Started Mar 05 01:49:50 PM PST 24
Finished Mar 05 01:49:51 PM PST 24
Peak memory 205176 kb
Host smart-b57381b7-3265-46c2-9fb4-a17d64f0f2e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490762413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.3490762413
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1772768951
Short name T156
Test name
Test status
Simulation time 27421829 ps
CPU time 0.83 seconds
Started Mar 05 01:49:53 PM PST 24
Finished Mar 05 01:49:54 PM PST 24
Peak memory 214952 kb
Host smart-434f9f58-cd70-4d7c-bfb1-fa17db9b1836
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772768951 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1772768951
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.278690255
Short name T164
Test name
Test status
Simulation time 29701659 ps
CPU time 1.18 seconds
Started Mar 05 01:49:47 PM PST 24
Finished Mar 05 01:49:48 PM PST 24
Peak memory 215608 kb
Host smart-a6fd550e-9406-4d81-99cf-bb7f3e5bff05
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278690255 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.278690255
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.3595710375
Short name T107
Test name
Test status
Simulation time 24649701 ps
CPU time 0.96 seconds
Started Mar 05 01:49:49 PM PST 24
Finished Mar 05 01:49:50 PM PST 24
Peak memory 222284 kb
Host smart-7737519d-cd42-4fb0-8cc5-8da1a7cc7561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595710375 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.3595710375
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.781280704
Short name T566
Test name
Test status
Simulation time 61542482 ps
CPU time 1.2 seconds
Started Mar 05 01:49:59 PM PST 24
Finished Mar 05 01:50:00 PM PST 24
Peak memory 217940 kb
Host smart-823a6706-abb7-467c-8436-d55fa5e02e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781280704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.781280704
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.3309904420
Short name T16
Test name
Test status
Simulation time 24042449 ps
CPU time 1.05 seconds
Started Mar 05 01:50:07 PM PST 24
Finished Mar 05 01:50:09 PM PST 24
Peak memory 222348 kb
Host smart-18a7ec28-7592-4478-8c78-b9157df5784b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309904420 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.3309904420
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1563295997
Short name T469
Test name
Test status
Simulation time 145657756 ps
CPU time 0.91 seconds
Started Mar 05 01:50:10 PM PST 24
Finished Mar 05 01:50:11 PM PST 24
Peak memory 214476 kb
Host smart-cf8f4cd0-922e-486e-b4aa-f5f751e457e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563295997 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1563295997
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1872604121
Short name T510
Test name
Test status
Simulation time 464038662 ps
CPU time 4.85 seconds
Started Mar 05 01:49:51 PM PST 24
Finished Mar 05 01:49:56 PM PST 24
Peak memory 214512 kb
Host smart-622b45ca-0351-4d94-9a37-4057c0370cae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872604121 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1872604121
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.2430855937
Short name T649
Test name
Test status
Simulation time 15929989905 ps
CPU time 415.91 seconds
Started Mar 05 01:50:00 PM PST 24
Finished Mar 05 01:56:56 PM PST 24
Peak memory 216616 kb
Host smart-07091bea-14dd-48b0-909e-b0b49f4c5552
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430855937 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.2430855937
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.2179893138
Short name T607
Test name
Test status
Simulation time 38915581 ps
CPU time 1.06 seconds
Started Mar 05 01:50:59 PM PST 24
Finished Mar 05 01:51:00 PM PST 24
Peak memory 215856 kb
Host smart-3c3928fa-e4dc-4ba8-abd1-79153b8b2475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179893138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.2179893138
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.509900488
Short name T402
Test name
Test status
Simulation time 128658569 ps
CPU time 1.24 seconds
Started Mar 05 01:51:03 PM PST 24
Finished Mar 05 01:51:04 PM PST 24
Peak memory 216904 kb
Host smart-55daaf19-219b-4ba5-876a-c6d74d4c0772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509900488 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.509900488
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.1581971253
Short name T814
Test name
Test status
Simulation time 38101607 ps
CPU time 1.37 seconds
Started Mar 05 01:50:58 PM PST 24
Finished Mar 05 01:50:59 PM PST 24
Peak memory 215616 kb
Host smart-67b0b9df-9f77-4fad-8742-cf63b8e9c0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581971253 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.1581971253
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2219603362
Short name T369
Test name
Test status
Simulation time 74122435 ps
CPU time 2.62 seconds
Started Mar 05 01:51:05 PM PST 24
Finished Mar 05 01:51:07 PM PST 24
Peak memory 218564 kb
Host smart-df013215-462f-4804-a35c-29d4fef1c8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219603362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2219603362
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.2912411926
Short name T646
Test name
Test status
Simulation time 49012984 ps
CPU time 1.35 seconds
Started Mar 05 01:51:03 PM PST 24
Finished Mar 05 01:51:05 PM PST 24
Peak memory 216016 kb
Host smart-6d306806-3148-4e77-a573-94f6c8391f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912411926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.2912411926
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3630247376
Short name T353
Test name
Test status
Simulation time 39843202 ps
CPU time 1.58 seconds
Started Mar 05 01:51:01 PM PST 24
Finished Mar 05 01:51:02 PM PST 24
Peak memory 218720 kb
Host smart-8fbb8e03-cf1f-4f4c-b1c2-b90b9c26b9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630247376 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3630247376
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.1960942725
Short name T137
Test name
Test status
Simulation time 34290158 ps
CPU time 1.52 seconds
Started Mar 05 01:51:04 PM PST 24
Finished Mar 05 01:51:05 PM PST 24
Peak memory 216832 kb
Host smart-0e1983b4-eb54-464a-8387-d5d48636f9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960942725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.1960942725
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.3660942755
Short name T794
Test name
Test status
Simulation time 156768199 ps
CPU time 1.28 seconds
Started Mar 05 01:50:56 PM PST 24
Finished Mar 05 01:50:58 PM PST 24
Peak memory 215788 kb
Host smart-6c99280b-7d62-4949-94e9-88c1f9de5be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660942755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.3660942755
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.2300724851
Short name T613
Test name
Test status
Simulation time 110746315 ps
CPU time 1.18 seconds
Started Mar 05 01:50:54 PM PST 24
Finished Mar 05 01:50:55 PM PST 24
Peak memory 214552 kb
Host smart-b47202c6-42de-4f9e-9b40-36541c6cf063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300724851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.2300724851
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2455859422
Short name T185
Test name
Test status
Simulation time 28429891 ps
CPU time 1.17 seconds
Started Mar 05 01:50:55 PM PST 24
Finished Mar 05 01:50:56 PM PST 24
Peak memory 215784 kb
Host smart-352272d5-5ed0-4df5-b61a-38a66d29f794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455859422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2455859422
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.304709644
Short name T253
Test name
Test status
Simulation time 72517962 ps
CPU time 1.19 seconds
Started Mar 05 01:49:50 PM PST 24
Finished Mar 05 01:49:52 PM PST 24
Peak memory 214812 kb
Host smart-0ff32966-e23d-472c-ae95-520a85e691e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304709644 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.304709644
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1988217952
Short name T145
Test name
Test status
Simulation time 15160427 ps
CPU time 0.86 seconds
Started Mar 05 01:49:46 PM PST 24
Finished Mar 05 01:49:46 PM PST 24
Peak memory 206156 kb
Host smart-e6775e26-e782-4a21-80fc-55171228b0e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988217952 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1988217952
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2472663118
Short name T106
Test name
Test status
Simulation time 38255069 ps
CPU time 0.8 seconds
Started Mar 05 01:49:47 PM PST 24
Finished Mar 05 01:49:48 PM PST 24
Peak memory 214964 kb
Host smart-ab64e588-fefd-4e62-acf9-8724ef1fb9a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472663118 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2472663118
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.232795917
Short name T162
Test name
Test status
Simulation time 30824040 ps
CPU time 1.01 seconds
Started Mar 05 01:49:59 PM PST 24
Finished Mar 05 01:50:00 PM PST 24
Peak memory 217324 kb
Host smart-8ec42ab3-5655-44ec-b1c3-08d1b89a62ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232795917 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.232795917
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.1204217457
Short name T806
Test name
Test status
Simulation time 83969823 ps
CPU time 1.91 seconds
Started Mar 05 01:49:47 PM PST 24
Finished Mar 05 01:49:49 PM PST 24
Peak memory 216016 kb
Host smart-73dcfabe-28ed-4dd2-ad67-2482ad9ef5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204217457 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1204217457
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.3017978673
Short name T351
Test name
Test status
Simulation time 39513523 ps
CPU time 0.88 seconds
Started Mar 05 01:49:48 PM PST 24
Finished Mar 05 01:49:49 PM PST 24
Peak memory 214592 kb
Host smart-b67f615b-38fd-40fd-80bb-4db66b5db406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017978673 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.3017978673
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.962914911
Short name T503
Test name
Test status
Simulation time 29447102 ps
CPU time 0.97 seconds
Started Mar 05 01:50:11 PM PST 24
Finished Mar 05 01:50:12 PM PST 24
Peak memory 214428 kb
Host smart-025fe40d-86a1-43dd-84be-873400fb4c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962914911 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.962914911
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.408864859
Short name T379
Test name
Test status
Simulation time 311969952 ps
CPU time 2.12 seconds
Started Mar 05 01:49:50 PM PST 24
Finished Mar 05 01:49:52 PM PST 24
Peak memory 215724 kb
Host smart-a8b95229-1469-4d91-b5a9-726121179772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408864859 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.408864859
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.3742570884
Short name T679
Test name
Test status
Simulation time 210310042842 ps
CPU time 2451.01 seconds
Started Mar 05 01:50:12 PM PST 24
Finished Mar 05 02:31:04 PM PST 24
Peak memory 226668 kb
Host smart-fa3dc327-db3b-428b-8561-5ed30aeaac7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742570884 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.3742570884
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.3491398215
Short name T757
Test name
Test status
Simulation time 121052850 ps
CPU time 1.38 seconds
Started Mar 05 01:51:03 PM PST 24
Finished Mar 05 01:51:05 PM PST 24
Peak memory 215640 kb
Host smart-0108d43f-2c30-4589-b1cf-1164a95095f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491398215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.3491398215
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.2631740448
Short name T780
Test name
Test status
Simulation time 182394694 ps
CPU time 3.21 seconds
Started Mar 05 01:50:59 PM PST 24
Finished Mar 05 01:51:03 PM PST 24
Peak memory 216112 kb
Host smart-d07ed5cb-9efb-4e14-9200-125c583f853a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631740448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.2631740448
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1797314392
Short name T395
Test name
Test status
Simulation time 94880846 ps
CPU time 1.73 seconds
Started Mar 05 01:51:00 PM PST 24
Finished Mar 05 01:51:07 PM PST 24
Peak memory 216996 kb
Host smart-4ae27a73-54c5-4647-88f6-e61c1bb106a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797314392 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1797314392
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.1355103155
Short name T533
Test name
Test status
Simulation time 94637742 ps
CPU time 1.24 seconds
Started Mar 05 01:51:06 PM PST 24
Finished Mar 05 01:51:08 PM PST 24
Peak memory 215696 kb
Host smart-907333f4-35ea-4b7b-9a37-b601576c9439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355103155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.1355103155
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2811200996
Short name T25
Test name
Test status
Simulation time 617092097 ps
CPU time 5.53 seconds
Started Mar 05 01:51:06 PM PST 24
Finished Mar 05 01:51:12 PM PST 24
Peak memory 216092 kb
Host smart-c1bb7d43-8221-4e81-9820-4f70ecf68fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811200996 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2811200996
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2959232115
Short name T589
Test name
Test status
Simulation time 41554923 ps
CPU time 1.68 seconds
Started Mar 05 01:51:05 PM PST 24
Finished Mar 05 01:51:07 PM PST 24
Peak memory 217152 kb
Host smart-33072cd0-40f6-425a-a7c1-4ffad80562f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959232115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2959232115
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.911722885
Short name T711
Test name
Test status
Simulation time 61551868 ps
CPU time 1.15 seconds
Started Mar 05 01:50:59 PM PST 24
Finished Mar 05 01:51:00 PM PST 24
Peak memory 216712 kb
Host smart-b287bc84-9f43-4d44-ba3b-567b17bf730b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911722885 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.911722885
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.469358254
Short name T337
Test name
Test status
Simulation time 63845399 ps
CPU time 1.28 seconds
Started Mar 05 01:50:53 PM PST 24
Finished Mar 05 01:50:54 PM PST 24
Peak memory 215696 kb
Host smart-0edb0b2a-a34d-4c60-815a-03961cd06fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469358254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.469358254
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.743129375
Short name T718
Test name
Test status
Simulation time 127645125 ps
CPU time 1.53 seconds
Started Mar 05 01:51:09 PM PST 24
Finished Mar 05 01:51:11 PM PST 24
Peak memory 217196 kb
Host smart-bf1510c9-adc3-4bd7-8bec-c79569ff99cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743129375 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.743129375
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3073226973
Short name T299
Test name
Test status
Simulation time 64211391 ps
CPU time 1.32 seconds
Started Mar 05 01:51:15 PM PST 24
Finished Mar 05 01:51:16 PM PST 24
Peak memory 217156 kb
Host smart-ceb9fbab-54ca-4074-898a-42bd11bcd4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073226973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3073226973
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.213735324
Short name T783
Test name
Test status
Simulation time 155965187 ps
CPU time 1.21 seconds
Started Mar 05 01:49:52 PM PST 24
Finished Mar 05 01:49:53 PM PST 24
Peak memory 214812 kb
Host smart-b6d50bda-f3cc-42ea-ac3b-39ef85c4b179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213735324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.213735324
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.111294122
Short name T551
Test name
Test status
Simulation time 11502333 ps
CPU time 0.82 seconds
Started Mar 05 01:49:57 PM PST 24
Finished Mar 05 01:49:58 PM PST 24
Peak memory 205036 kb
Host smart-58124692-639b-490a-af0f-2d9e69417346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111294122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.111294122
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.872496754
Short name T700
Test name
Test status
Simulation time 12417174 ps
CPU time 0.88 seconds
Started Mar 05 01:49:51 PM PST 24
Finished Mar 05 01:49:52 PM PST 24
Peak memory 214820 kb
Host smart-6cce99c0-b9ac-49b0-87d2-1624052db19c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872496754 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.872496754
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.337879854
Short name T423
Test name
Test status
Simulation time 60727208 ps
CPU time 1.28 seconds
Started Mar 05 01:50:00 PM PST 24
Finished Mar 05 01:50:01 PM PST 24
Peak memory 215456 kb
Host smart-8dbb44f2-62ba-4700-a9fe-1f86ca46f264
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337879854 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_di
sable_auto_req_mode.337879854
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.415472942
Short name T157
Test name
Test status
Simulation time 19651822 ps
CPU time 1.06 seconds
Started Mar 05 01:49:50 PM PST 24
Finished Mar 05 01:49:52 PM PST 24
Peak memory 217388 kb
Host smart-71758d81-ddec-40d9-9295-2cdf6181bac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415472942 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.415472942
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.1269066153
Short name T175
Test name
Test status
Simulation time 65975166 ps
CPU time 1.44 seconds
Started Mar 05 01:49:42 PM PST 24
Finished Mar 05 01:49:43 PM PST 24
Peak memory 215700 kb
Host smart-42d07b1a-ee7c-48b4-8c5c-83b3122a03fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269066153 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.1269066153
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2918534919
Short name T352
Test name
Test status
Simulation time 22148484 ps
CPU time 1.05 seconds
Started Mar 05 01:49:57 PM PST 24
Finished Mar 05 01:49:58 PM PST 24
Peak memory 214556 kb
Host smart-91bcfe3e-df6b-48ce-9d79-fc81f6ace669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918534919 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2918534919
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.3337558542
Short name T417
Test name
Test status
Simulation time 19928795 ps
CPU time 1.05 seconds
Started Mar 05 01:49:56 PM PST 24
Finished Mar 05 01:49:57 PM PST 24
Peak memory 214468 kb
Host smart-9dca99a8-3817-4b78-8e20-5cbc567848cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337558542 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.3337558542
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3902579457
Short name T544
Test name
Test status
Simulation time 632807056 ps
CPU time 3.66 seconds
Started Mar 05 01:49:54 PM PST 24
Finished Mar 05 01:49:58 PM PST 24
Peak memory 214464 kb
Host smart-e1ba0f84-9fea-4bc2-af15-d51e9723e41e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902579457 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3902579457
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.40701706
Short name T699
Test name
Test status
Simulation time 45918845788 ps
CPU time 769.38 seconds
Started Mar 05 01:50:00 PM PST 24
Finished Mar 05 02:02:49 PM PST 24
Peak memory 217144 kb
Host smart-e0cb64d0-8e4b-411d-ae02-31ca3ebe7970
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40701706 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.40701706
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.1590034370
Short name T518
Test name
Test status
Simulation time 47692147 ps
CPU time 1.44 seconds
Started Mar 05 01:50:59 PM PST 24
Finished Mar 05 01:51:00 PM PST 24
Peak memory 216908 kb
Host smart-f73776db-c54e-4071-9483-248c5812906d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590034370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.1590034370
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.433767909
Short name T628
Test name
Test status
Simulation time 47462086 ps
CPU time 1.44 seconds
Started Mar 05 01:51:16 PM PST 24
Finished Mar 05 01:51:17 PM PST 24
Peak memory 216160 kb
Host smart-a3b9b46a-1653-4b1e-b397-f0ae0852c810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433767909 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.433767909
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.1683194763
Short name T480
Test name
Test status
Simulation time 51213100 ps
CPU time 1.93 seconds
Started Mar 05 01:50:59 PM PST 24
Finished Mar 05 01:51:01 PM PST 24
Peak memory 217820 kb
Host smart-8fee5837-25d5-43e0-b866-72093a83ad7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683194763 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.1683194763
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.3601942780
Short name T375
Test name
Test status
Simulation time 77522847 ps
CPU time 1.3 seconds
Started Mar 05 01:51:02 PM PST 24
Finished Mar 05 01:51:04 PM PST 24
Peak memory 217508 kb
Host smart-43a2a760-6a47-4eb2-99ac-4f5ab7226375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601942780 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.3601942780
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.3144741160
Short name T654
Test name
Test status
Simulation time 50493687 ps
CPU time 1.26 seconds
Started Mar 05 01:50:49 PM PST 24
Finished Mar 05 01:50:51 PM PST 24
Peak memory 217172 kb
Host smart-c8b58575-e870-4412-ad53-5e8817c4a82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144741160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.3144741160
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.4049487467
Short name T685
Test name
Test status
Simulation time 65112653 ps
CPU time 1 seconds
Started Mar 05 01:51:08 PM PST 24
Finished Mar 05 01:51:09 PM PST 24
Peak memory 216200 kb
Host smart-84c41c3b-7263-4599-85a1-493699b4fd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049487467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.4049487467
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1078440778
Short name T719
Test name
Test status
Simulation time 70267057 ps
CPU time 1.26 seconds
Started Mar 05 01:51:00 PM PST 24
Finished Mar 05 01:51:06 PM PST 24
Peak memory 217772 kb
Host smart-36fdf610-1c05-43fe-a493-a3fdb50a6961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078440778 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1078440778
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1811652960
Short name T476
Test name
Test status
Simulation time 57452446 ps
CPU time 1.1 seconds
Started Mar 05 01:51:09 PM PST 24
Finished Mar 05 01:51:10 PM PST 24
Peak memory 217172 kb
Host smart-e5b37a9a-4796-4627-84cb-beb5073f94c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811652960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1811652960
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.194811492
Short name T393
Test name
Test status
Simulation time 52094315 ps
CPU time 1.22 seconds
Started Mar 05 01:51:08 PM PST 24
Finished Mar 05 01:51:10 PM PST 24
Peak memory 216012 kb
Host smart-eb7732fd-1cc6-41d8-88f6-f3800b0076c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194811492 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.194811492
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.842052625
Short name T288
Test name
Test status
Simulation time 59231604 ps
CPU time 1.38 seconds
Started Mar 05 01:51:13 PM PST 24
Finished Mar 05 01:51:14 PM PST 24
Peak memory 216920 kb
Host smart-a30b1c55-11ca-4138-9e86-52af316e6053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842052625 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.842052625
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.1896925917
Short name T677
Test name
Test status
Simulation time 121803907 ps
CPU time 1.23 seconds
Started Mar 05 01:49:14 PM PST 24
Finished Mar 05 01:49:16 PM PST 24
Peak memory 214896 kb
Host smart-16cadb72-3add-4f45-9652-793985549873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896925917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.1896925917
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3012742032
Short name T584
Test name
Test status
Simulation time 14719284 ps
CPU time 0.95 seconds
Started Mar 05 01:49:02 PM PST 24
Finished Mar 05 01:49:03 PM PST 24
Peak memory 206276 kb
Host smart-267c7dc6-0c58-446a-9a07-d59cd617a815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012742032 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3012742032
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1290149006
Short name T32
Test name
Test status
Simulation time 14439659 ps
CPU time 0.86 seconds
Started Mar 05 01:49:08 PM PST 24
Finished Mar 05 01:49:09 PM PST 24
Peak memory 215076 kb
Host smart-0fc699c7-3f1b-4ce6-b4ee-6fd362144ac9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290149006 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1290149006
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.3696871656
Short name T495
Test name
Test status
Simulation time 41529846 ps
CPU time 1.09 seconds
Started Mar 05 01:49:01 PM PST 24
Finished Mar 05 01:49:02 PM PST 24
Peak memory 215556 kb
Host smart-876da375-b997-41ba-8ad4-708de6b026fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696871656 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_di
sable_auto_req_mode.3696871656
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.2179530783
Short name T831
Test name
Test status
Simulation time 29365231 ps
CPU time 0.95 seconds
Started Mar 05 01:49:11 PM PST 24
Finished Mar 05 01:49:12 PM PST 24
Peak memory 222152 kb
Host smart-5269b2fd-c01e-4438-9c38-a56f430bad02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179530783 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.2179530783
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1724225535
Short name T522
Test name
Test status
Simulation time 140381565 ps
CPU time 1.19 seconds
Started Mar 05 01:49:20 PM PST 24
Finished Mar 05 01:49:21 PM PST 24
Peak memory 215588 kb
Host smart-f68e7486-dfb9-4d64-9aa0-1ae8a7d62a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724225535 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1724225535
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3374765965
Short name T466
Test name
Test status
Simulation time 21899133 ps
CPU time 1.05 seconds
Started Mar 05 01:49:06 PM PST 24
Finished Mar 05 01:49:08 PM PST 24
Peak memory 214576 kb
Host smart-9ff61cae-eb3f-4a2f-b795-67d25c88d30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374765965 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3374765965
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.2037394373
Short name T248
Test name
Test status
Simulation time 28265244 ps
CPU time 0.91 seconds
Started Mar 05 01:48:59 PM PST 24
Finished Mar 05 01:49:00 PM PST 24
Peak memory 206252 kb
Host smart-adb365f2-c84d-4df1-a02e-7dbd8a31e547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037394373 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.2037394373
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.4043767276
Short name T14
Test name
Test status
Simulation time 378199591 ps
CPU time 6.11 seconds
Started Mar 05 01:49:05 PM PST 24
Finished Mar 05 01:49:11 PM PST 24
Peak memory 241408 kb
Host smart-292d2d1d-aa6d-4fc0-ab50-0ee0be259378
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043767276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.4043767276
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.226635387
Short name T471
Test name
Test status
Simulation time 28187847 ps
CPU time 0.97 seconds
Started Mar 05 01:49:09 PM PST 24
Finished Mar 05 01:49:10 PM PST 24
Peak memory 214404 kb
Host smart-f8657cb8-8a40-4cbc-8bf1-46f82440f71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226635387 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.226635387
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1938840434
Short name T391
Test name
Test status
Simulation time 109747878 ps
CPU time 2.62 seconds
Started Mar 05 01:49:01 PM PST 24
Finished Mar 05 01:49:05 PM PST 24
Peak memory 216840 kb
Host smart-937bccbe-be6a-43c4-b02d-322cc68538bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938840434 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1938840434
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3049159280
Short name T693
Test name
Test status
Simulation time 104847036186 ps
CPU time 765.18 seconds
Started Mar 05 01:49:07 PM PST 24
Finished Mar 05 02:01:53 PM PST 24
Peak memory 219096 kb
Host smart-5445e61a-90dc-42ac-a363-d4ca14f8709f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049159280 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3049159280
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert.1408001379
Short name T17
Test name
Test status
Simulation time 66246994 ps
CPU time 1.21 seconds
Started Mar 05 01:49:54 PM PST 24
Finished Mar 05 01:49:55 PM PST 24
Peak memory 214808 kb
Host smart-bc42ecf6-ea5e-478d-87f8-684558f97c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408001379 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.1408001379
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/30.edn_alert_test.1559206826
Short name T431
Test name
Test status
Simulation time 24845322 ps
CPU time 0.95 seconds
Started Mar 05 01:49:50 PM PST 24
Finished Mar 05 01:49:51 PM PST 24
Peak memory 205332 kb
Host smart-860bed70-ca05-4713-967b-3ef79491993a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559206826 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1559206826
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable.3159112928
Short name T399
Test name
Test status
Simulation time 27319538 ps
CPU time 0.82 seconds
Started Mar 05 01:49:50 PM PST 24
Finished Mar 05 01:49:51 PM PST 24
Peak memory 214616 kb
Host smart-95fcfcca-7907-4eac-80e8-17a0c421624a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159112928 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.3159112928
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.1228059125
Short name T739
Test name
Test status
Simulation time 57651176 ps
CPU time 1.11 seconds
Started Mar 05 01:49:52 PM PST 24
Finished Mar 05 01:49:59 PM PST 24
Peak memory 216828 kb
Host smart-d16887d3-1611-4cbe-aff2-7c21bfbdcc10
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228059125 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.1228059125
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.1126192854
Short name T454
Test name
Test status
Simulation time 22390863 ps
CPU time 1.02 seconds
Started Mar 05 01:49:51 PM PST 24
Finished Mar 05 01:49:52 PM PST 24
Peak memory 215924 kb
Host smart-0ab40555-c072-4814-a7e5-f10eca5658a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126192854 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.1126192854
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3434423783
Short name T552
Test name
Test status
Simulation time 58989059 ps
CPU time 1.48 seconds
Started Mar 05 01:49:43 PM PST 24
Finished Mar 05 01:49:45 PM PST 24
Peak memory 217052 kb
Host smart-3d1c2c31-65f5-4d3d-bddd-81116b8ae8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434423783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3434423783
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.2862657753
Short name T130
Test name
Test status
Simulation time 22599330 ps
CPU time 0.93 seconds
Started Mar 05 01:49:41 PM PST 24
Finished Mar 05 01:49:42 PM PST 24
Peak memory 214768 kb
Host smart-ed01463c-21e2-4652-8a47-a2dd1d61b99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862657753 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.2862657753
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.608138472
Short name T235
Test name
Test status
Simulation time 29517509 ps
CPU time 0.95 seconds
Started Mar 05 01:49:49 PM PST 24
Finished Mar 05 01:49:50 PM PST 24
Peak memory 214476 kb
Host smart-4bf1d53d-12b6-48f3-90a1-a1ee274158ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608138472 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.608138472
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.197646800
Short name T412
Test name
Test status
Simulation time 303484689 ps
CPU time 5.5 seconds
Started Mar 05 01:49:56 PM PST 24
Finished Mar 05 01:50:02 PM PST 24
Peak memory 215468 kb
Host smart-3da50219-c1e4-4788-b201-1325347bab2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197646800 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.197646800
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3146615094
Short name T362
Test name
Test status
Simulation time 177935997625 ps
CPU time 1742.7 seconds
Started Mar 05 01:49:54 PM PST 24
Finished Mar 05 02:18:57 PM PST 24
Peak memory 225668 kb
Host smart-25807cbd-b5bf-453d-a420-358a946dfeae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146615094 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3146615094
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.977997099
Short name T112
Test name
Test status
Simulation time 39229344 ps
CPU time 1.15 seconds
Started Mar 05 01:50:08 PM PST 24
Finished Mar 05 01:50:09 PM PST 24
Peak memory 214808 kb
Host smart-687c1068-439f-46a9-b582-d460b847e5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977997099 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.977997099
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3324043902
Short name T692
Test name
Test status
Simulation time 36319950 ps
CPU time 0.76 seconds
Started Mar 05 01:49:58 PM PST 24
Finished Mar 05 01:49:59 PM PST 24
Peak memory 203932 kb
Host smart-6884bedd-8ada-4309-80d6-e41499455a29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324043902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3324043902
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.1429490664
Short name T91
Test name
Test status
Simulation time 36586223 ps
CPU time 0.92 seconds
Started Mar 05 01:50:05 PM PST 24
Finished Mar 05 01:50:06 PM PST 24
Peak memory 214704 kb
Host smart-b5e8d241-170b-48f2-a3cf-03291fd6dc97
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429490664 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.1429490664
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.1813000944
Short name T824
Test name
Test status
Simulation time 33430186 ps
CPU time 1.06 seconds
Started Mar 05 01:49:58 PM PST 24
Finished Mar 05 01:49:59 PM PST 24
Peak memory 219236 kb
Host smart-87a82261-3012-47b5-a9e2-5730a0db8ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813000944 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1813000944
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.460940571
Short name T424
Test name
Test status
Simulation time 51772711 ps
CPU time 1.43 seconds
Started Mar 05 01:49:59 PM PST 24
Finished Mar 05 01:50:01 PM PST 24
Peak memory 217180 kb
Host smart-3380db62-e6a1-4a12-befa-7ad553623d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460940571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.460940571
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.206646847
Short name T457
Test name
Test status
Simulation time 23315351 ps
CPU time 1.14 seconds
Started Mar 05 01:50:01 PM PST 24
Finished Mar 05 01:50:08 PM PST 24
Peak memory 214720 kb
Host smart-8716bd3f-349a-4ead-bfda-c24570d7c889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206646847 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.206646847
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1954998944
Short name T304
Test name
Test status
Simulation time 22950822 ps
CPU time 0.94 seconds
Started Mar 05 01:49:49 PM PST 24
Finished Mar 05 01:49:50 PM PST 24
Peak memory 214472 kb
Host smart-6bc9ea10-646f-41f3-b0ff-77c1cc5b79d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954998944 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1954998944
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1005319111
Short name T324
Test name
Test status
Simulation time 236558723 ps
CPU time 4.64 seconds
Started Mar 05 01:49:55 PM PST 24
Finished Mar 05 01:50:00 PM PST 24
Peak memory 214488 kb
Host smart-fa3664fd-fbb2-4a29-956f-b0eafaff4a6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005319111 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1005319111
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.2847363687
Short name T205
Test name
Test status
Simulation time 195996845844 ps
CPU time 2244.38 seconds
Started Mar 05 01:50:10 PM PST 24
Finished Mar 05 02:27:40 PM PST 24
Peak memory 225656 kb
Host smart-226ee712-1043-44bd-91ae-508919a91376
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847363687 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.2847363687
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert.2484234980
Short name T583
Test name
Test status
Simulation time 50872102 ps
CPU time 1.19 seconds
Started Mar 05 01:50:05 PM PST 24
Finished Mar 05 01:50:11 PM PST 24
Peak memory 214900 kb
Host smart-48967fdb-007f-41cf-8072-6ba5d8151b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484234980 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.2484234980
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/32.edn_alert_test.904543238
Short name T778
Test name
Test status
Simulation time 32544700 ps
CPU time 0.96 seconds
Started Mar 05 01:49:53 PM PST 24
Finished Mar 05 01:49:54 PM PST 24
Peak memory 205764 kb
Host smart-77e5ba60-a276-4aae-8e8d-37abca65ff2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904543238 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.904543238
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2943353150
Short name T570
Test name
Test status
Simulation time 12835998 ps
CPU time 0.87 seconds
Started Mar 05 01:49:54 PM PST 24
Finished Mar 05 01:49:55 PM PST 24
Peak memory 214960 kb
Host smart-73ec329f-30d8-472a-974f-4f97ab94ee99
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943353150 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2943353150
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.3698997321
Short name T153
Test name
Test status
Simulation time 31328529 ps
CPU time 1.24 seconds
Started Mar 05 01:49:52 PM PST 24
Finished Mar 05 01:49:54 PM PST 24
Peak memory 215520 kb
Host smart-14d3378b-a584-45f9-8994-fea5cd2ab35d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698997321 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.3698997321
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/32.edn_err.3428979102
Short name T509
Test name
Test status
Simulation time 23255140 ps
CPU time 0.92 seconds
Started Mar 05 01:49:48 PM PST 24
Finished Mar 05 01:49:49 PM PST 24
Peak memory 216948 kb
Host smart-7209386d-65b8-4456-aefd-9b2abc8f8a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428979102 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3428979102
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.974554208
Short name T271
Test name
Test status
Simulation time 232291606 ps
CPU time 1.09 seconds
Started Mar 05 01:50:09 PM PST 24
Finished Mar 05 01:50:10 PM PST 24
Peak memory 215580 kb
Host smart-4ba14e2f-90fa-4ed2-9e53-3201f04c9969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974554208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.974554208
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.1980450872
Short name T347
Test name
Test status
Simulation time 22888765 ps
CPU time 1.11 seconds
Started Mar 05 01:50:19 PM PST 24
Finished Mar 05 01:50:20 PM PST 24
Peak memory 214664 kb
Host smart-8d3a3186-275f-451d-b2ad-a4c8f789832b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980450872 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.1980450872
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.1753100415
Short name T723
Test name
Test status
Simulation time 22461886 ps
CPU time 0.87 seconds
Started Mar 05 01:50:04 PM PST 24
Finished Mar 05 01:50:05 PM PST 24
Peak memory 214328 kb
Host smart-d8d12c8d-8acb-4ae7-ab7d-b2ffcbf20ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753100415 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.1753100415
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.1962645731
Short name T210
Test name
Test status
Simulation time 215659009 ps
CPU time 4.43 seconds
Started Mar 05 01:50:07 PM PST 24
Finished Mar 05 01:50:11 PM PST 24
Peak memory 216916 kb
Host smart-fda5278d-e860-4a18-b727-170c7cbd1b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962645731 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.1962645731
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.337009318
Short name T354
Test name
Test status
Simulation time 24197385169 ps
CPU time 627.15 seconds
Started Mar 05 01:50:03 PM PST 24
Finished Mar 05 02:00:30 PM PST 24
Peak memory 216572 kb
Host smart-cd6e96be-d02b-4ec4-a87c-e68a77e11d94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337009318 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.337009318
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.3967650706
Short name T341
Test name
Test status
Simulation time 125596180 ps
CPU time 1.08 seconds
Started Mar 05 01:50:04 PM PST 24
Finished Mar 05 01:50:05 PM PST 24
Peak memory 214824 kb
Host smart-3f76837d-b232-4a03-8270-90efba1fb236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967650706 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.3967650706
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.1415411704
Short name T350
Test name
Test status
Simulation time 15487250 ps
CPU time 0.95 seconds
Started Mar 05 01:50:05 PM PST 24
Finished Mar 05 01:50:06 PM PST 24
Peak memory 205784 kb
Host smart-6f8aff5f-31c6-4385-bb81-9d23607cb649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415411704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.1415411704
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.4199553792
Short name T180
Test name
Test status
Simulation time 133000457 ps
CPU time 0.89 seconds
Started Mar 05 01:49:59 PM PST 24
Finished Mar 05 01:50:00 PM PST 24
Peak memory 214532 kb
Host smart-32d8159b-ed07-4f40-ba40-2545647a6221
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199553792 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.4199553792
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.2683320579
Short name T325
Test name
Test status
Simulation time 31792929 ps
CPU time 1.25 seconds
Started Mar 05 01:50:04 PM PST 24
Finished Mar 05 01:50:05 PM PST 24
Peak memory 215512 kb
Host smart-951d8316-52f4-4389-ab0a-f82c5cfcd5e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683320579 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_d
isable_auto_req_mode.2683320579
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.798328094
Short name T166
Test name
Test status
Simulation time 44571177 ps
CPU time 1.15 seconds
Started Mar 05 01:49:51 PM PST 24
Finished Mar 05 01:49:53 PM PST 24
Peak memory 218480 kb
Host smart-d96522f9-9768-4a06-b874-3751cfedbe08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798328094 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.798328094
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.1060281137
Short name T637
Test name
Test status
Simulation time 53296582 ps
CPU time 1.59 seconds
Started Mar 05 01:50:16 PM PST 24
Finished Mar 05 01:50:18 PM PST 24
Peak memory 216832 kb
Host smart-954e51e5-3719-45ad-9154-bda434e89060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060281137 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.1060281137
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.692869645
Short name T326
Test name
Test status
Simulation time 29061170 ps
CPU time 0.9 seconds
Started Mar 05 01:49:55 PM PST 24
Finished Mar 05 01:49:56 PM PST 24
Peak memory 214568 kb
Host smart-e974dec1-1d25-4527-b526-5b0f448aadd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692869645 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.692869645
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.292027818
Short name T813
Test name
Test status
Simulation time 40863121 ps
CPU time 0.87 seconds
Started Mar 05 01:49:50 PM PST 24
Finished Mar 05 01:49:51 PM PST 24
Peak memory 214436 kb
Host smart-e8f930fe-ea56-4f63-bdda-af137448c0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292027818 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.292027818
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.3180699074
Short name T481
Test name
Test status
Simulation time 416095362 ps
CPU time 2.96 seconds
Started Mar 05 01:50:01 PM PST 24
Finished Mar 05 01:50:04 PM PST 24
Peak memory 214480 kb
Host smart-f24230b6-a03f-49d1-afe3-0709c49d780e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180699074 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.3180699074
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3264470671
Short name T634
Test name
Test status
Simulation time 113115272321 ps
CPU time 510.09 seconds
Started Mar 05 01:49:52 PM PST 24
Finished Mar 05 01:58:22 PM PST 24
Peak memory 217740 kb
Host smart-156d5ee8-d010-4707-93f0-38e024c41174
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264470671 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3264470671
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.1470710687
Short name T242
Test name
Test status
Simulation time 29194981 ps
CPU time 1.25 seconds
Started Mar 05 01:49:51 PM PST 24
Finished Mar 05 01:49:53 PM PST 24
Peak memory 214856 kb
Host smart-032885d1-1eb8-4b75-a3cd-d2fad3f1707f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470710687 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.1470710687
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.2782844094
Short name T452
Test name
Test status
Simulation time 156992159 ps
CPU time 0.84 seconds
Started Mar 05 01:49:51 PM PST 24
Finished Mar 05 01:49:52 PM PST 24
Peak memory 206204 kb
Host smart-2de358a5-82ee-4dd5-8a7c-fd1be8dc5fbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782844094 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2782844094
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.976778581
Short name T835
Test name
Test status
Simulation time 24598099 ps
CPU time 0.89 seconds
Started Mar 05 01:50:09 PM PST 24
Finished Mar 05 01:50:10 PM PST 24
Peak memory 214784 kb
Host smart-bf6d73c8-9f3e-49fe-9d99-fc208c8f265f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976778581 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.976778581
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.202247283
Short name T292
Test name
Test status
Simulation time 34812099 ps
CPU time 1.07 seconds
Started Mar 05 01:49:56 PM PST 24
Finished Mar 05 01:49:57 PM PST 24
Peak memory 216740 kb
Host smart-e91f1979-d345-44ce-90c3-95a822ecf15b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202247283 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_di
sable_auto_req_mode.202247283
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.36051667
Short name T174
Test name
Test status
Simulation time 68229101 ps
CPU time 1.07 seconds
Started Mar 05 01:49:52 PM PST 24
Finished Mar 05 01:49:53 PM PST 24
Peak memory 216028 kb
Host smart-4989041e-28a9-4d01-8064-8531896a1955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36051667 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.36051667
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3749487559
Short name T640
Test name
Test status
Simulation time 81514278 ps
CPU time 1 seconds
Started Mar 05 01:50:04 PM PST 24
Finished Mar 05 01:50:05 PM PST 24
Peak memory 215752 kb
Host smart-2a921705-2ed6-4aa6-a18a-0f1b4df24c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749487559 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3749487559
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.1143033853
Short name T535
Test name
Test status
Simulation time 22254843 ps
CPU time 1.04 seconds
Started Mar 05 01:49:59 PM PST 24
Finished Mar 05 01:50:00 PM PST 24
Peak memory 214620 kb
Host smart-d09df083-7038-4015-9353-44f0c80c26ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143033853 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.1143033853
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.2994148894
Short name T598
Test name
Test status
Simulation time 23123245 ps
CPU time 0.9 seconds
Started Mar 05 01:50:10 PM PST 24
Finished Mar 05 01:50:11 PM PST 24
Peak memory 214476 kb
Host smart-78772db1-411f-46bb-981f-3e8ea2899c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994148894 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.2994148894
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.4186662534
Short name T37
Test name
Test status
Simulation time 179112143 ps
CPU time 4.03 seconds
Started Mar 05 01:49:50 PM PST 24
Finished Mar 05 01:49:55 PM PST 24
Peak memory 214388 kb
Host smart-5723d993-35b2-4c86-93bf-c66e96cb2cf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186662534 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.4186662534
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.392235868
Short name T336
Test name
Test status
Simulation time 146151372695 ps
CPU time 477.21 seconds
Started Mar 05 01:50:08 PM PST 24
Finished Mar 05 01:58:06 PM PST 24
Peak memory 218396 kb
Host smart-bc5a6c63-6c29-480a-8251-7ac3d5cfde8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392235868 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.392235868
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3777602170
Short name T249
Test name
Test status
Simulation time 42413544 ps
CPU time 1.18 seconds
Started Mar 05 01:49:50 PM PST 24
Finished Mar 05 01:49:52 PM PST 24
Peak memory 214764 kb
Host smart-c92d54f1-7ad5-41c6-89c8-a3a6c3ea790f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777602170 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3777602170
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.2340745319
Short name T527
Test name
Test status
Simulation time 28369138 ps
CPU time 0.95 seconds
Started Mar 05 01:50:02 PM PST 24
Finished Mar 05 01:50:03 PM PST 24
Peak memory 205784 kb
Host smart-07314ff1-5746-469d-a5a9-e4277aa2cb9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340745319 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.2340745319
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.4081215008
Short name T177
Test name
Test status
Simulation time 18331298 ps
CPU time 0.87 seconds
Started Mar 05 01:50:01 PM PST 24
Finished Mar 05 01:50:02 PM PST 24
Peak memory 214972 kb
Host smart-e31cc1f8-cf76-40a4-bd50-b928d7b2e1c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081215008 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.4081215008
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.3341166361
Short name T594
Test name
Test status
Simulation time 83567608 ps
CPU time 1.05 seconds
Started Mar 05 01:49:50 PM PST 24
Finished Mar 05 01:49:51 PM PST 24
Peak memory 215536 kb
Host smart-41a1d32d-c774-4007-9ad2-586dad85534d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341166361 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_d
isable_auto_req_mode.3341166361
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.2972045102
Short name T98
Test name
Test status
Simulation time 18912632 ps
CPU time 1.07 seconds
Started Mar 05 01:50:02 PM PST 24
Finished Mar 05 01:50:03 PM PST 24
Peak memory 217288 kb
Host smart-e03d14f1-15e4-4a5f-a8eb-31c3f279cc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972045102 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.2972045102
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.1286868451
Short name T181
Test name
Test status
Simulation time 35885192 ps
CPU time 1.23 seconds
Started Mar 05 01:49:49 PM PST 24
Finished Mar 05 01:49:50 PM PST 24
Peak memory 216920 kb
Host smart-d161af2e-8806-4574-a957-1e4c0f24a902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286868451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.1286868451
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.204463304
Short name T571
Test name
Test status
Simulation time 45834418 ps
CPU time 0.96 seconds
Started Mar 05 01:50:07 PM PST 24
Finished Mar 05 01:50:09 PM PST 24
Peak memory 222364 kb
Host smart-92a92ab6-3df0-4940-ba88-12ff57147c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204463304 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.204463304
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.2033864727
Short name T750
Test name
Test status
Simulation time 22110079 ps
CPU time 0.96 seconds
Started Mar 05 01:49:50 PM PST 24
Finished Mar 05 01:49:51 PM PST 24
Peak memory 214476 kb
Host smart-3e9e777c-1e77-4f16-9c15-3903f8c897f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033864727 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.2033864727
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.4039223731
Short name T206
Test name
Test status
Simulation time 357305461 ps
CPU time 6.82 seconds
Started Mar 05 01:49:59 PM PST 24
Finished Mar 05 01:50:05 PM PST 24
Peak memory 214468 kb
Host smart-1f616fb5-fe30-4a71-87bb-f12f3a19293c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039223731 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.4039223731
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.1239634626
Short name T828
Test name
Test status
Simulation time 60503305129 ps
CPU time 744.01 seconds
Started Mar 05 01:50:03 PM PST 24
Finished Mar 05 02:02:27 PM PST 24
Peak memory 219272 kb
Host smart-b1fc91ea-3a4d-4621-919f-e1272630436d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239634626 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.1239634626
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.1970343394
Short name T259
Test name
Test status
Simulation time 26778544 ps
CPU time 1.22 seconds
Started Mar 05 01:50:07 PM PST 24
Finished Mar 05 01:50:09 PM PST 24
Peak memory 214860 kb
Host smart-877e243d-31e6-46ed-881b-80df7be10007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970343394 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.1970343394
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.1259482231
Short name T487
Test name
Test status
Simulation time 54140410 ps
CPU time 0.9 seconds
Started Mar 05 01:50:07 PM PST 24
Finished Mar 05 01:50:08 PM PST 24
Peak memory 205748 kb
Host smart-37e0f0e9-ba8a-4c0f-856d-99604590069d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259482231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.1259482231
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3614510061
Short name T760
Test name
Test status
Simulation time 36251230 ps
CPU time 0.79 seconds
Started Mar 05 01:50:07 PM PST 24
Finished Mar 05 01:50:08 PM PST 24
Peak memory 214700 kb
Host smart-5a1fba02-acad-4bf8-b550-66cec305ef6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614510061 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3614510061
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.1452783128
Short name T579
Test name
Test status
Simulation time 45638211 ps
CPU time 0.96 seconds
Started Mar 05 01:50:07 PM PST 24
Finished Mar 05 01:50:09 PM PST 24
Peak memory 216492 kb
Host smart-f13a94fb-1c4f-45ad-8731-60e27bc356e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452783128 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.1452783128
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.29253940
Short name T449
Test name
Test status
Simulation time 39553543 ps
CPU time 1.08 seconds
Started Mar 05 01:50:01 PM PST 24
Finished Mar 05 01:50:02 PM PST 24
Peak memory 216116 kb
Host smart-82409d76-a93f-4765-9225-685eedd45022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29253940 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.29253940
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1205215448
Short name T602
Test name
Test status
Simulation time 129129529 ps
CPU time 1.25 seconds
Started Mar 05 01:49:53 PM PST 24
Finished Mar 05 01:49:54 PM PST 24
Peak memory 215992 kb
Host smart-e555ec0e-3f07-4258-bb04-cc7cc3db5e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205215448 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1205215448
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.2741948171
Short name T546
Test name
Test status
Simulation time 33298002 ps
CPU time 0.88 seconds
Started Mar 05 01:50:02 PM PST 24
Finished Mar 05 01:50:03 PM PST 24
Peak memory 214720 kb
Host smart-83630f48-8bc4-479c-b9d3-7b44945059dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741948171 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.2741948171
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/36.edn_smoke.776679052
Short name T388
Test name
Test status
Simulation time 48773876 ps
CPU time 0.92 seconds
Started Mar 05 01:50:18 PM PST 24
Finished Mar 05 01:50:19 PM PST 24
Peak memory 214488 kb
Host smart-0f69ffd0-e135-4772-af07-b509ce5b6973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776679052 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.776679052
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2780402314
Short name T209
Test name
Test status
Simulation time 62939348 ps
CPU time 0.95 seconds
Started Mar 05 01:50:00 PM PST 24
Finished Mar 05 01:50:01 PM PST 24
Peak memory 205088 kb
Host smart-6320c4c0-826d-405d-bbfe-cfbaa1ddeaae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780402314 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2780402314
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_alert.2887954985
Short name T11
Test name
Test status
Simulation time 43141784 ps
CPU time 1.24 seconds
Started Mar 05 01:50:09 PM PST 24
Finished Mar 05 01:50:10 PM PST 24
Peak memory 214800 kb
Host smart-31395e4d-1526-4fce-a61c-14903b0119ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887954985 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.2887954985
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1328656936
Short name T470
Test name
Test status
Simulation time 64380639 ps
CPU time 0.9 seconds
Started Mar 05 01:49:50 PM PST 24
Finished Mar 05 01:49:52 PM PST 24
Peak memory 205316 kb
Host smart-a2acc022-d6a6-4254-ac90-e03176534754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328656936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1328656936
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.2280654077
Short name T664
Test name
Test status
Simulation time 55778393 ps
CPU time 1.14 seconds
Started Mar 05 01:50:07 PM PST 24
Finished Mar 05 01:50:08 PM PST 24
Peak memory 217064 kb
Host smart-6aa67819-72a0-45e9-b793-91e7bc60d615
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280654077 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.2280654077
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.3081497417
Short name T83
Test name
Test status
Simulation time 43290600 ps
CPU time 1.23 seconds
Started Mar 05 01:50:06 PM PST 24
Finished Mar 05 01:50:07 PM PST 24
Peak memory 223424 kb
Host smart-62c5cd64-eb25-4b0a-8abe-692f01b68be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081497417 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.3081497417
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.1851925122
Short name T519
Test name
Test status
Simulation time 50998331 ps
CPU time 1.25 seconds
Started Mar 05 01:50:03 PM PST 24
Finished Mar 05 01:50:05 PM PST 24
Peak memory 217016 kb
Host smart-7eefbfa0-2e09-4ef6-acda-ed1d5181e093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851925122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.1851925122
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_smoke.701351939
Short name T629
Test name
Test status
Simulation time 36939033 ps
CPU time 0.89 seconds
Started Mar 05 01:49:53 PM PST 24
Finished Mar 05 01:49:54 PM PST 24
Peak memory 214472 kb
Host smart-cadca49e-31d5-4844-ad78-73a095837e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701351939 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.701351939
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.918318326
Short name T776
Test name
Test status
Simulation time 898281972 ps
CPU time 2.48 seconds
Started Mar 05 01:50:08 PM PST 24
Finished Mar 05 01:50:10 PM PST 24
Peak memory 215756 kb
Host smart-1bbd68cb-d752-4d79-8911-9ec19a8d48c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918318326 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.918318326
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.569416680
Short name T554
Test name
Test status
Simulation time 91546085521 ps
CPU time 2018.28 seconds
Started Mar 05 01:49:55 PM PST 24
Finished Mar 05 02:23:34 PM PST 24
Peak memory 225048 kb
Host smart-21e45dae-1d3f-40d7-9be5-f57a668189f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569416680 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.569416680
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.1997668708
Short name T553
Test name
Test status
Simulation time 38705510 ps
CPU time 1.11 seconds
Started Mar 05 01:49:58 PM PST 24
Finished Mar 05 01:49:59 PM PST 24
Peak memory 214924 kb
Host smart-70f39941-ac24-49e6-9ee6-9f332f84a138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997668708 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.1997668708
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.4013453475
Short name T565
Test name
Test status
Simulation time 24698794 ps
CPU time 0.85 seconds
Started Mar 05 01:50:01 PM PST 24
Finished Mar 05 01:50:02 PM PST 24
Peak memory 206108 kb
Host smart-dfd9d15c-42ce-4c7d-8ee1-85c04f23bd66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013453475 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.4013453475
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2371178958
Short name T376
Test name
Test status
Simulation time 11400572 ps
CPU time 0.86 seconds
Started Mar 05 01:50:03 PM PST 24
Finished Mar 05 01:50:04 PM PST 24
Peak memory 215116 kb
Host smart-bb9214a1-da24-4fe9-a3fb-9ba1db16f94b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371178958 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2371178958
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2751946920
Short name T187
Test name
Test status
Simulation time 33097413 ps
CPU time 1.06 seconds
Started Mar 05 01:49:56 PM PST 24
Finished Mar 05 01:49:57 PM PST 24
Peak memory 215664 kb
Host smart-95519107-6319-4270-b980-d4f7166a4d69
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751946920 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2751946920
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1873950137
Short name T703
Test name
Test status
Simulation time 61481450 ps
CPU time 1.03 seconds
Started Mar 05 01:50:04 PM PST 24
Finished Mar 05 01:50:05 PM PST 24
Peak memory 219416 kb
Host smart-05dfad46-e4e8-4b40-b24b-b5ae54a476f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873950137 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1873950137
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.3716398089
Short name T496
Test name
Test status
Simulation time 55685387 ps
CPU time 1.12 seconds
Started Mar 05 01:50:19 PM PST 24
Finished Mar 05 01:50:21 PM PST 24
Peak memory 215804 kb
Host smart-a22923c7-6de5-4fa4-8063-d784b2817c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716398089 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.3716398089
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1900540132
Short name T779
Test name
Test status
Simulation time 24791580 ps
CPU time 0.95 seconds
Started Mar 05 01:49:58 PM PST 24
Finished Mar 05 01:49:59 PM PST 24
Peak memory 214780 kb
Host smart-8489e1d8-fa00-432f-9b28-f602e5a2a9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900540132 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1900540132
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.1440501021
Short name T47
Test name
Test status
Simulation time 18014685 ps
CPU time 0.99 seconds
Started Mar 05 01:49:55 PM PST 24
Finished Mar 05 01:49:56 PM PST 24
Peak memory 214468 kb
Host smart-109128df-b698-4c3c-bb93-43c803cd639f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440501021 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.1440501021
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.2097442824
Short name T667
Test name
Test status
Simulation time 354488040 ps
CPU time 3.75 seconds
Started Mar 05 01:49:55 PM PST 24
Finished Mar 05 01:49:58 PM PST 24
Peak memory 214564 kb
Host smart-bca3584f-e9d9-4d52-8113-8b09b0cda412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097442824 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.2097442824
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.3869200285
Short name T199
Test name
Test status
Simulation time 59645339631 ps
CPU time 1136.34 seconds
Started Mar 05 01:50:12 PM PST 24
Finished Mar 05 02:09:11 PM PST 24
Peak memory 218612 kb
Host smart-1d614e42-61d9-44c9-acc8-5d1eb07dfc6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869200285 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.3869200285
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.3579953531
Short name T100
Test name
Test status
Simulation time 92987225 ps
CPU time 1.11 seconds
Started Mar 05 01:50:07 PM PST 24
Finished Mar 05 01:50:09 PM PST 24
Peak memory 214708 kb
Host smart-5f2fc150-2973-45f4-a922-960bf046d2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579953531 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.3579953531
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3631459806
Short name T661
Test name
Test status
Simulation time 24684982 ps
CPU time 0.88 seconds
Started Mar 05 01:50:15 PM PST 24
Finished Mar 05 01:50:17 PM PST 24
Peak memory 205700 kb
Host smart-fe84a1b9-10ab-42f7-b18f-c02501a9bf32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631459806 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3631459806
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.4095562276
Short name T63
Test name
Test status
Simulation time 42033081 ps
CPU time 1.33 seconds
Started Mar 05 01:50:21 PM PST 24
Finished Mar 05 01:50:23 PM PST 24
Peak memory 215440 kb
Host smart-9217fbf7-8fe4-4738-a849-08d668424bb1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095562276 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.4095562276
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1389286228
Short name T8
Test name
Test status
Simulation time 24956267 ps
CPU time 0.95 seconds
Started Mar 05 01:50:18 PM PST 24
Finished Mar 05 01:50:19 PM PST 24
Peak memory 216024 kb
Host smart-6bf966ea-3342-4253-8609-3052e4b91357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389286228 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1389286228
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_intr.3449063274
Short name T131
Test name
Test status
Simulation time 36498186 ps
CPU time 0.88 seconds
Started Mar 05 01:50:14 PM PST 24
Finished Mar 05 01:50:16 PM PST 24
Peak memory 214684 kb
Host smart-580264aa-3fcc-4042-af0a-70a083aa8d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449063274 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.3449063274
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.4148306581
Short name T385
Test name
Test status
Simulation time 31814245 ps
CPU time 0.97 seconds
Started Mar 05 01:49:54 PM PST 24
Finished Mar 05 01:49:55 PM PST 24
Peak memory 214476 kb
Host smart-cae2fabe-e94a-420d-9469-4eeb104216c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148306581 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.4148306581
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3257360603
Short name T317
Test name
Test status
Simulation time 386693298 ps
CPU time 4.02 seconds
Started Mar 05 01:50:04 PM PST 24
Finished Mar 05 01:50:08 PM PST 24
Peak memory 214480 kb
Host smart-2ed8f138-387f-4633-a176-739fd9d3e721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257360603 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3257360603
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.3660350671
Short name T204
Test name
Test status
Simulation time 62874986932 ps
CPU time 1438.53 seconds
Started Mar 05 01:50:06 PM PST 24
Finished Mar 05 02:14:05 PM PST 24
Peak memory 222808 kb
Host smart-7aa35d85-2ff8-4cb5-9f65-6887a692d42c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660350671 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.3660350671
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.1173934510
Short name T140
Test name
Test status
Simulation time 30524282 ps
CPU time 1.35 seconds
Started Mar 05 01:49:11 PM PST 24
Finished Mar 05 01:49:13 PM PST 24
Peak memory 214704 kb
Host smart-705f1fb0-5ee3-4a9a-8e11-01266c639658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173934510 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.1173934510
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2777353783
Short name T413
Test name
Test status
Simulation time 50804859 ps
CPU time 0.9 seconds
Started Mar 05 01:49:12 PM PST 24
Finished Mar 05 01:49:13 PM PST 24
Peak memory 205784 kb
Host smart-a0233b96-ea1f-4efe-bd97-15fc646bc952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777353783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2777353783
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.2950207779
Short name T810
Test name
Test status
Simulation time 13969399 ps
CPU time 0.89 seconds
Started Mar 05 01:49:15 PM PST 24
Finished Mar 05 01:49:17 PM PST 24
Peak memory 215072 kb
Host smart-0ea906b4-39c8-48b5-97de-e7a63a31c3ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950207779 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.2950207779
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.750965260
Short name T432
Test name
Test status
Simulation time 67463355 ps
CPU time 1.08 seconds
Started Mar 05 01:49:08 PM PST 24
Finished Mar 05 01:49:10 PM PST 24
Peak memory 215436 kb
Host smart-645fea53-43ac-4511-ac02-11e0df282fa7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750965260 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_dis
able_auto_req_mode.750965260
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3820990268
Short name T805
Test name
Test status
Simulation time 25283465 ps
CPU time 1.01 seconds
Started Mar 05 01:49:07 PM PST 24
Finished Mar 05 01:49:09 PM PST 24
Peak memory 218536 kb
Host smart-2bae1cc9-7a76-4b3e-98ce-6e044bdb1099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820990268 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3820990268
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.3023080870
Short name T756
Test name
Test status
Simulation time 203995109 ps
CPU time 2.9 seconds
Started Mar 05 01:48:59 PM PST 24
Finished Mar 05 01:49:02 PM PST 24
Peak memory 218436 kb
Host smart-6d4d6364-34b4-4072-a827-14291b300581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023080870 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.3023080870
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_regwen.155269593
Short name T247
Test name
Test status
Simulation time 34665294 ps
CPU time 1.09 seconds
Started Mar 05 01:49:02 PM PST 24
Finished Mar 05 01:49:03 PM PST 24
Peak memory 206248 kb
Host smart-8e58c4a0-8f34-41d2-ad84-34b059d000d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155269593 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.155269593
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_sec_cm.40942413
Short name T49
Test name
Test status
Simulation time 709387286 ps
CPU time 4.05 seconds
Started Mar 05 01:49:03 PM PST 24
Finished Mar 05 01:49:08 PM PST 24
Peak memory 234980 kb
Host smart-c21ea9ca-4f42-42af-b2f7-1b1f042e1032
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40942413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.40942413
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/4.edn_smoke.768390915
Short name T668
Test name
Test status
Simulation time 49418638 ps
CPU time 0.89 seconds
Started Mar 05 01:49:12 PM PST 24
Finished Mar 05 01:49:14 PM PST 24
Peak memory 214488 kb
Host smart-1a615016-b52b-4ed0-98e7-b8167affe941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768390915 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.768390915
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1391188072
Short name T208
Test name
Test status
Simulation time 691008100 ps
CPU time 3.8 seconds
Started Mar 05 01:49:04 PM PST 24
Finished Mar 05 01:49:08 PM PST 24
Peak memory 215608 kb
Host smart-04d28dbf-871d-4ea4-8c5e-acc8d483af6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391188072 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1391188072
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.1096318839
Short name T596
Test name
Test status
Simulation time 49666446721 ps
CPU time 1139.33 seconds
Started Mar 05 01:49:09 PM PST 24
Finished Mar 05 02:08:09 PM PST 24
Peak memory 222884 kb
Host smart-72c6448a-207e-452f-9424-7e04dfb958ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096318839 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.1096318839
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.4062423090
Short name T149
Test name
Test status
Simulation time 25202671 ps
CPU time 1.19 seconds
Started Mar 05 01:50:08 PM PST 24
Finished Mar 05 01:50:10 PM PST 24
Peak memory 214948 kb
Host smart-69022c96-bfe9-4af8-9fed-ec7b86a8ac3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062423090 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.4062423090
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.3356092527
Short name T332
Test name
Test status
Simulation time 213784407 ps
CPU time 0.84 seconds
Started Mar 05 01:50:18 PM PST 24
Finished Mar 05 01:50:20 PM PST 24
Peak memory 205604 kb
Host smart-dc84a950-8551-4f16-a965-5a133deb8684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356092527 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.3356092527
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2877984602
Short name T104
Test name
Test status
Simulation time 12776751 ps
CPU time 0.92 seconds
Started Mar 05 01:50:06 PM PST 24
Finished Mar 05 01:50:07 PM PST 24
Peak memory 215168 kb
Host smart-6c3cef73-02ed-4586-aca9-13c026ca2180
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877984602 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2877984602
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.845800196
Short name T173
Test name
Test status
Simulation time 23383131 ps
CPU time 1.01 seconds
Started Mar 05 01:50:14 PM PST 24
Finished Mar 05 01:50:16 PM PST 24
Peak memory 215832 kb
Host smart-331ca66f-f0bb-4156-b6b7-f25875009619
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845800196 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.845800196
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.1004636943
Short name T80
Test name
Test status
Simulation time 25713164 ps
CPU time 1.1 seconds
Started Mar 05 01:50:11 PM PST 24
Finished Mar 05 01:50:13 PM PST 24
Peak memory 228920 kb
Host smart-48c77f7a-85bb-4ff9-86e2-b5a2cf28691f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004636943 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.1004636943
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.1525296939
Short name T374
Test name
Test status
Simulation time 30425586 ps
CPU time 1.26 seconds
Started Mar 05 01:50:12 PM PST 24
Finished Mar 05 01:50:14 PM PST 24
Peak memory 215804 kb
Host smart-088fb068-8c24-4983-a4b4-b7f9abce539e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525296939 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.1525296939
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.738153297
Short name T127
Test name
Test status
Simulation time 21693322 ps
CPU time 1.09 seconds
Started Mar 05 01:50:05 PM PST 24
Finished Mar 05 01:50:07 PM PST 24
Peak memory 214828 kb
Host smart-0261df74-6e75-4999-8150-531033f1d9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738153297 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.738153297
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.777859079
Short name T360
Test name
Test status
Simulation time 17053437 ps
CPU time 0.97 seconds
Started Mar 05 01:50:18 PM PST 24
Finished Mar 05 01:50:19 PM PST 24
Peak memory 214468 kb
Host smart-dbe096bf-3785-4c95-9c0f-f05a82b4e8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777859079 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.777859079
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3780262919
Short name T416
Test name
Test status
Simulation time 1074542168 ps
CPU time 4.46 seconds
Started Mar 05 01:50:22 PM PST 24
Finished Mar 05 01:50:27 PM PST 24
Peak memory 215804 kb
Host smart-9df40284-4a5d-4eed-9f26-fa958255e449
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780262919 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3780262919
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_alert.118098355
Short name T672
Test name
Test status
Simulation time 92720136 ps
CPU time 1.11 seconds
Started Mar 05 01:50:13 PM PST 24
Finished Mar 05 01:50:16 PM PST 24
Peak memory 214856 kb
Host smart-1c7e635e-ed85-427f-8847-79c753ed202e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118098355 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.118098355
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.713990402
Short name T592
Test name
Test status
Simulation time 23650501 ps
CPU time 0.87 seconds
Started Mar 05 01:50:14 PM PST 24
Finished Mar 05 01:50:16 PM PST 24
Peak memory 206144 kb
Host smart-03b644a8-89e2-457e-8ace-725d577a0c02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713990402 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.713990402
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3388908537
Short name T732
Test name
Test status
Simulation time 22909418 ps
CPU time 0.91 seconds
Started Mar 05 01:50:12 PM PST 24
Finished Mar 05 01:50:15 PM PST 24
Peak memory 214636 kb
Host smart-ec2f5bf1-66d1-4ee1-a7a5-d7730ad3ce24
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388908537 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3388908537
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_err.3124871744
Short name T453
Test name
Test status
Simulation time 41575756 ps
CPU time 1.14 seconds
Started Mar 05 01:50:12 PM PST 24
Finished Mar 05 01:50:14 PM PST 24
Peak memory 230628 kb
Host smart-e86d2e7a-75ad-4da6-b0e8-c5d26cc1d09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124871744 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.3124871744
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.3141936642
Short name T724
Test name
Test status
Simulation time 50253361 ps
CPU time 1.24 seconds
Started Mar 05 01:50:17 PM PST 24
Finished Mar 05 01:50:19 PM PST 24
Peak memory 217072 kb
Host smart-939bb401-a487-49a3-a1e2-40400084f73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141936642 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.3141936642
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.792647709
Short name T411
Test name
Test status
Simulation time 22128797 ps
CPU time 1.19 seconds
Started Mar 05 01:50:14 PM PST 24
Finished Mar 05 01:50:16 PM PST 24
Peak memory 231808 kb
Host smart-c93ae265-9f6d-4c4a-b6de-6bbd8da78abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792647709 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.792647709
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1960149464
Short name T483
Test name
Test status
Simulation time 20809947 ps
CPU time 0.94 seconds
Started Mar 05 01:50:08 PM PST 24
Finished Mar 05 01:50:09 PM PST 24
Peak memory 214476 kb
Host smart-db0792e1-9285-4ab7-9651-48a8a498fd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960149464 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1960149464
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.3469305496
Short name T310
Test name
Test status
Simulation time 2380854491 ps
CPU time 3.45 seconds
Started Mar 05 01:50:06 PM PST 24
Finished Mar 05 01:50:10 PM PST 24
Peak memory 214660 kb
Host smart-7ae96c31-163f-4546-b083-fc9f8dc531af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469305496 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.3469305496
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.3520256175
Short name T135
Test name
Test status
Simulation time 44823703382 ps
CPU time 1027.26 seconds
Started Mar 05 01:50:08 PM PST 24
Finished Mar 05 02:07:15 PM PST 24
Peak memory 217156 kb
Host smart-2334f39f-864f-4f40-b5ab-65b15f3c85e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520256175 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.3520256175
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2398866405
Short name T143
Test name
Test status
Simulation time 77484681 ps
CPU time 1.25 seconds
Started Mar 05 01:49:59 PM PST 24
Finished Mar 05 01:50:01 PM PST 24
Peak memory 214832 kb
Host smart-02f9de9f-715e-4f8a-bd35-af26aeceb4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398866405 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2398866405
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.1854250478
Short name T147
Test name
Test status
Simulation time 47455567 ps
CPU time 0.92 seconds
Started Mar 05 01:50:25 PM PST 24
Finished Mar 05 01:50:26 PM PST 24
Peak memory 205688 kb
Host smart-85e00818-62ae-4ae1-9ad9-388cbf473d52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854250478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.1854250478
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3164313374
Short name T105
Test name
Test status
Simulation time 53477268 ps
CPU time 0.84 seconds
Started Mar 05 01:50:04 PM PST 24
Finished Mar 05 01:50:05 PM PST 24
Peak memory 215104 kb
Host smart-b45229e3-a3d5-4403-8c68-1bb3510d3508
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164313374 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3164313374
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.4214678392
Short name T154
Test name
Test status
Simulation time 41465469 ps
CPU time 1.28 seconds
Started Mar 05 01:50:21 PM PST 24
Finished Mar 05 01:50:23 PM PST 24
Peak memory 216824 kb
Host smart-20206360-1bcc-44ba-8400-faf161a7d447
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214678392 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.4214678392
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.3088962969
Short name T658
Test name
Test status
Simulation time 31554469 ps
CPU time 1.04 seconds
Started Mar 05 01:50:16 PM PST 24
Finished Mar 05 01:50:18 PM PST 24
Peak memory 217212 kb
Host smart-e762e1bf-eb9a-4189-9332-9a95c26b80b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088962969 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.3088962969
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.2427400503
Short name T384
Test name
Test status
Simulation time 40648412 ps
CPU time 1.14 seconds
Started Mar 05 01:50:11 PM PST 24
Finished Mar 05 01:50:13 PM PST 24
Peak memory 216936 kb
Host smart-85fbf535-2490-442f-96ae-f29756b0b7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427400503 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.2427400503
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.2166010768
Short name T445
Test name
Test status
Simulation time 21039583 ps
CPU time 1.06 seconds
Started Mar 05 01:50:05 PM PST 24
Finished Mar 05 01:50:07 PM PST 24
Peak memory 214776 kb
Host smart-7fe60221-eaf5-4a34-9ad6-0aa76b1862d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166010768 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.2166010768
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2336345067
Short name T133
Test name
Test status
Simulation time 18218228 ps
CPU time 1 seconds
Started Mar 05 01:50:00 PM PST 24
Finished Mar 05 01:50:01 PM PST 24
Peak memory 214544 kb
Host smart-af9dfb6b-260e-4b1a-93ca-cc704e354357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336345067 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2336345067
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.3354099333
Short name T434
Test name
Test status
Simulation time 199369131 ps
CPU time 4.19 seconds
Started Mar 05 01:50:09 PM PST 24
Finished Mar 05 01:50:13 PM PST 24
Peak memory 217048 kb
Host smart-a44580db-6a6b-4f70-8794-d6a841585962
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354099333 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.3354099333
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.3292993583
Short name T736
Test name
Test status
Simulation time 180008984067 ps
CPU time 947.29 seconds
Started Mar 05 01:50:12 PM PST 24
Finished Mar 05 02:06:00 PM PST 24
Peak memory 219668 kb
Host smart-d7706cec-6a80-4145-b4d5-680c04af2b4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292993583 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.3292993583
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.731271381
Short name T262
Test name
Test status
Simulation time 26847233 ps
CPU time 1.17 seconds
Started Mar 05 01:50:07 PM PST 24
Finished Mar 05 01:50:08 PM PST 24
Peak memory 214952 kb
Host smart-132a2383-497a-41ad-b66a-69ed44980875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731271381 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.731271381
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.3669700451
Short name T456
Test name
Test status
Simulation time 42939987 ps
CPU time 0.89 seconds
Started Mar 05 01:50:15 PM PST 24
Finished Mar 05 01:50:17 PM PST 24
Peak memory 205280 kb
Host smart-72b6897c-31e9-4367-85dc-267ded96f193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669700451 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.3669700451
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.1829206334
Short name T151
Test name
Test status
Simulation time 99869420 ps
CPU time 0.81 seconds
Started Mar 05 01:50:07 PM PST 24
Finished Mar 05 01:50:08 PM PST 24
Peak memory 214908 kb
Host smart-8b77cb27-f932-4aa4-86da-e8b2512095c9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829206334 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.1829206334
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_err.3733267532
Short name T461
Test name
Test status
Simulation time 18705791 ps
CPU time 1.12 seconds
Started Mar 05 01:50:18 PM PST 24
Finished Mar 05 01:50:20 PM PST 24
Peak memory 217144 kb
Host smart-5e0708ac-e6c0-4cc9-bfd1-fc7eacfdb6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733267532 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3733267532
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.389864872
Short name T12
Test name
Test status
Simulation time 33543025 ps
CPU time 1.34 seconds
Started Mar 05 01:50:08 PM PST 24
Finished Mar 05 01:50:10 PM PST 24
Peak memory 217932 kb
Host smart-7a88ee40-2b64-429e-9a6f-dc80c7eb3e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389864872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.389864872
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.2862154188
Short name T676
Test name
Test status
Simulation time 31446691 ps
CPU time 0.87 seconds
Started Mar 05 01:50:15 PM PST 24
Finished Mar 05 01:50:17 PM PST 24
Peak memory 214764 kb
Host smart-29bf0ddf-5d64-406b-b9d6-e4839075d3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862154188 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.2862154188
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1155088858
Short name T500
Test name
Test status
Simulation time 35723044 ps
CPU time 0.86 seconds
Started Mar 05 01:50:07 PM PST 24
Finished Mar 05 01:50:08 PM PST 24
Peak memory 214424 kb
Host smart-f7b45642-1120-405b-9470-f145b2895631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155088858 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1155088858
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.4100050116
Short name T392
Test name
Test status
Simulation time 376619340 ps
CPU time 7.3 seconds
Started Mar 05 01:50:18 PM PST 24
Finished Mar 05 01:50:26 PM PST 24
Peak memory 214440 kb
Host smart-fc7e0ab2-6baf-45f7-8e9f-33779ed469bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100050116 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.4100050116
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_alert.3820493841
Short name T606
Test name
Test status
Simulation time 53278247 ps
CPU time 1.31 seconds
Started Mar 05 01:50:07 PM PST 24
Finished Mar 05 01:50:09 PM PST 24
Peak memory 214840 kb
Host smart-21155e10-ff5d-4eb4-92ba-fdaf44f396d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820493841 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.3820493841
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2091747481
Short name T499
Test name
Test status
Simulation time 12419107 ps
CPU time 0.86 seconds
Started Mar 05 01:50:11 PM PST 24
Finished Mar 05 01:50:13 PM PST 24
Peak memory 205240 kb
Host smart-e51650a7-6827-4597-b81f-ee159758ae8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091747481 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2091747481
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.171804220
Short name T160
Test name
Test status
Simulation time 89369136 ps
CPU time 0.86 seconds
Started Mar 05 01:50:10 PM PST 24
Finished Mar 05 01:50:11 PM PST 24
Peak memory 214920 kb
Host smart-2767b48c-594e-4e86-9ef0-09b29297c415
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171804220 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.171804220
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.4160582103
Short name T714
Test name
Test status
Simulation time 30115620 ps
CPU time 1.18 seconds
Started Mar 05 01:50:09 PM PST 24
Finished Mar 05 01:50:10 PM PST 24
Peak memory 216752 kb
Host smart-206f0c8e-bb71-4af1-983f-97a654d84317
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160582103 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.4160582103
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.1150839615
Short name T367
Test name
Test status
Simulation time 19799731 ps
CPU time 0.94 seconds
Started Mar 05 01:50:20 PM PST 24
Finished Mar 05 01:50:22 PM PST 24
Peak memory 216908 kb
Host smart-a77a2f66-54ae-4abe-a590-592c4574833e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150839615 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.1150839615
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1163531445
Short name T36
Test name
Test status
Simulation time 85764439 ps
CPU time 1.24 seconds
Started Mar 05 01:50:08 PM PST 24
Finished Mar 05 01:50:09 PM PST 24
Peak memory 217464 kb
Host smart-cadb34cd-ccec-41b9-aaff-d843bc728cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163531445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1163531445
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.4044603877
Short name T681
Test name
Test status
Simulation time 36329501 ps
CPU time 0.97 seconds
Started Mar 05 01:50:07 PM PST 24
Finished Mar 05 01:50:08 PM PST 24
Peak memory 222368 kb
Host smart-601ccfe6-aaa1-45b5-9dfe-2d6cc2a59cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044603877 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.4044603877
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.1240408636
Short name T822
Test name
Test status
Simulation time 25469119 ps
CPU time 0.89 seconds
Started Mar 05 01:50:03 PM PST 24
Finished Mar 05 01:50:04 PM PST 24
Peak memory 214472 kb
Host smart-ca90018c-5c0e-4c0a-8f55-e58f29492f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240408636 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.1240408636
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.2649627655
Short name T410
Test name
Test status
Simulation time 116443393 ps
CPU time 2.19 seconds
Started Mar 05 01:50:12 PM PST 24
Finished Mar 05 01:50:17 PM PST 24
Peak memory 214492 kb
Host smart-51b00c9d-6cd0-41c8-8341-edd06aaaee23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649627655 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.2649627655
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.825918201
Short name T343
Test name
Test status
Simulation time 76721890578 ps
CPU time 2073.27 seconds
Started Mar 05 01:50:15 PM PST 24
Finished Mar 05 02:24:49 PM PST 24
Peak memory 227656 kb
Host smart-0daa6855-dd62-491e-b478-805ec248d78b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825918201 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.825918201
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.782623012
Short name T506
Test name
Test status
Simulation time 83828203 ps
CPU time 1.12 seconds
Started Mar 05 01:50:13 PM PST 24
Finished Mar 05 01:50:16 PM PST 24
Peak memory 214848 kb
Host smart-4d6c9729-d2cc-452a-a170-99f6ce98c94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782623012 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.782623012
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.3490324479
Short name T751
Test name
Test status
Simulation time 18724922 ps
CPU time 0.97 seconds
Started Mar 05 01:50:11 PM PST 24
Finished Mar 05 01:50:13 PM PST 24
Peak memory 206172 kb
Host smart-27abac57-6430-46df-93db-0fe1a34ee46f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490324479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.3490324479
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2119655758
Short name T178
Test name
Test status
Simulation time 56790981 ps
CPU time 0.86 seconds
Started Mar 05 01:49:59 PM PST 24
Finished Mar 05 01:50:00 PM PST 24
Peak memory 214696 kb
Host smart-a5269d8f-4d73-4f54-b94d-2282fe5fae05
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119655758 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2119655758
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_err.2119413654
Short name T44
Test name
Test status
Simulation time 22299114 ps
CPU time 1.03 seconds
Started Mar 05 01:50:29 PM PST 24
Finished Mar 05 01:50:31 PM PST 24
Peak memory 222328 kb
Host smart-f382108e-5269-4498-84fa-17aa3ec4e206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119413654 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2119413654
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3000009248
Short name T574
Test name
Test status
Simulation time 34597114 ps
CPU time 1 seconds
Started Mar 05 01:50:12 PM PST 24
Finished Mar 05 01:50:15 PM PST 24
Peak memory 215844 kb
Host smart-4d34c664-76a8-4f68-95a2-4f3c371f12c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000009248 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3000009248
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.4040197029
Short name T39
Test name
Test status
Simulation time 21233721 ps
CPU time 1.18 seconds
Started Mar 05 01:50:23 PM PST 24
Finished Mar 05 01:50:24 PM PST 24
Peak memory 222456 kb
Host smart-82027bc9-258d-48f6-bc4c-a6a2ec6026fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040197029 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.4040197029
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.2615722061
Short name T346
Test name
Test status
Simulation time 18968090 ps
CPU time 1.02 seconds
Started Mar 05 01:50:23 PM PST 24
Finished Mar 05 01:50:24 PM PST 24
Peak memory 214440 kb
Host smart-689c3f54-a3bf-4822-8cc7-4abd2674567a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615722061 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.2615722061
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1030558828
Short name T478
Test name
Test status
Simulation time 292212712 ps
CPU time 3.32 seconds
Started Mar 05 01:50:01 PM PST 24
Finished Mar 05 01:50:04 PM PST 24
Peak memory 215680 kb
Host smart-5145992f-294b-4992-8272-d89e4deeeb98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030558828 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1030558828
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.4134329191
Short name T656
Test name
Test status
Simulation time 16336950627 ps
CPU time 339.16 seconds
Started Mar 05 01:50:21 PM PST 24
Finished Mar 05 01:56:00 PM PST 24
Peak memory 216956 kb
Host smart-0b5562c0-9081-4136-aca1-7549987e5ada
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134329191 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.4134329191
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1905815227
Short name T536
Test name
Test status
Simulation time 87654264 ps
CPU time 1.19 seconds
Started Mar 05 01:50:11 PM PST 24
Finished Mar 05 01:50:14 PM PST 24
Peak memory 214848 kb
Host smart-32a2848d-8c68-467e-813c-c20407e57585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905815227 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1905815227
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.1576710730
Short name T557
Test name
Test status
Simulation time 21589677 ps
CPU time 0.91 seconds
Started Mar 05 01:50:25 PM PST 24
Finished Mar 05 01:50:26 PM PST 24
Peak memory 205740 kb
Host smart-3c4826ec-ba69-40fc-a7d8-4e5aafb5c550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576710730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.1576710730
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.241259024
Short name T671
Test name
Test status
Simulation time 83066410 ps
CPU time 0.87 seconds
Started Mar 05 01:50:19 PM PST 24
Finished Mar 05 01:50:21 PM PST 24
Peak memory 214784 kb
Host smart-165a2e0f-e762-4f10-ae9c-55dd4801171b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241259024 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.241259024
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3757886244
Short name T568
Test name
Test status
Simulation time 24795843 ps
CPU time 1.04 seconds
Started Mar 05 01:50:14 PM PST 24
Finished Mar 05 01:50:16 PM PST 24
Peak memory 216804 kb
Host smart-14e3773d-d2ff-4893-b82f-725f6b442b19
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757886244 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3757886244
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.4253220836
Short name T547
Test name
Test status
Simulation time 18451338 ps
CPU time 1.09 seconds
Started Mar 05 01:50:22 PM PST 24
Finished Mar 05 01:50:24 PM PST 24
Peak memory 222332 kb
Host smart-623df39e-dec0-4bd7-97c0-5ac7f9b3cdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253220836 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.4253220836
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.3240784650
Short name T532
Test name
Test status
Simulation time 317571580 ps
CPU time 1.74 seconds
Started Mar 05 01:50:11 PM PST 24
Finished Mar 05 01:50:14 PM PST 24
Peak memory 217216 kb
Host smart-6896e601-85e6-4893-b46e-78f09321a004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240784650 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.3240784650
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.407469487
Short name T621
Test name
Test status
Simulation time 23042307 ps
CPU time 1.11 seconds
Started Mar 05 01:50:06 PM PST 24
Finished Mar 05 01:50:17 PM PST 24
Peak memory 214608 kb
Host smart-f7eecab9-b9ce-4cdb-acf5-d0b5b052b32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407469487 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.407469487
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.727915704
Short name T344
Test name
Test status
Simulation time 18344250 ps
CPU time 1.02 seconds
Started Mar 05 01:50:20 PM PST 24
Finished Mar 05 01:50:22 PM PST 24
Peak memory 214472 kb
Host smart-239b33a1-3eb8-4a59-862f-0f29381b93f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727915704 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.727915704
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1394808278
Short name T576
Test name
Test status
Simulation time 343544268 ps
CPU time 6.71 seconds
Started Mar 05 01:50:16 PM PST 24
Finished Mar 05 01:50:23 PM PST 24
Peak memory 215724 kb
Host smart-203ba4b1-3bd3-4645-b6a8-04177fb6e1d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394808278 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1394808278
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1936459094
Short name T669
Test name
Test status
Simulation time 112143960536 ps
CPU time 1138.57 seconds
Started Mar 05 01:50:12 PM PST 24
Finished Mar 05 02:09:13 PM PST 24
Peak memory 220668 kb
Host smart-af6f99e1-3fb5-445b-8466-97359c32a145
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936459094 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1936459094
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.3845101072
Short name T694
Test name
Test status
Simulation time 74070417 ps
CPU time 1.23 seconds
Started Mar 05 01:50:12 PM PST 24
Finished Mar 05 01:50:14 PM PST 24
Peak memory 214848 kb
Host smart-f9df1dfb-307a-4d8e-b725-6b0b704ffa65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845101072 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.3845101072
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.939810318
Short name T319
Test name
Test status
Simulation time 20595044 ps
CPU time 0.89 seconds
Started Mar 05 01:50:25 PM PST 24
Finished Mar 05 01:50:26 PM PST 24
Peak memory 205784 kb
Host smart-71681902-d4c0-48d7-b8dc-c1e200991d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939810318 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.939810318
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.1682020292
Short name T587
Test name
Test status
Simulation time 11134319 ps
CPU time 0.86 seconds
Started Mar 05 01:50:02 PM PST 24
Finished Mar 05 01:50:03 PM PST 24
Peak memory 214656 kb
Host smart-a12512ba-ccf0-45d8-8bf9-ffa1be121a1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682020292 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1682020292
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.3049666876
Short name T165
Test name
Test status
Simulation time 61252697 ps
CPU time 1.13 seconds
Started Mar 05 01:50:19 PM PST 24
Finished Mar 05 01:50:21 PM PST 24
Peak memory 216936 kb
Host smart-c816e1f3-a221-44fa-9724-c02ce665eb23
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049666876 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.3049666876
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.1169150956
Short name T95
Test name
Test status
Simulation time 28708278 ps
CPU time 0.95 seconds
Started Mar 05 01:50:30 PM PST 24
Finished Mar 05 01:50:31 PM PST 24
Peak memory 222336 kb
Host smart-968ce2b0-d325-463c-a8f6-c3cbe3c80e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169150956 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.1169150956
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.2521796605
Short name T403
Test name
Test status
Simulation time 35936881 ps
CPU time 1.52 seconds
Started Mar 05 01:50:22 PM PST 24
Finished Mar 05 01:50:29 PM PST 24
Peak memory 216984 kb
Host smart-5fc8247d-19bd-41ac-9a1e-00fa03397274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521796605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.2521796605
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.1062043225
Short name T407
Test name
Test status
Simulation time 20944564 ps
CPU time 1.04 seconds
Started Mar 05 01:50:12 PM PST 24
Finished Mar 05 01:50:14 PM PST 24
Peak memory 214728 kb
Host smart-86223e16-79d4-4ac5-a561-836d9bc8d6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062043225 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.1062043225
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.3416675214
Short name T426
Test name
Test status
Simulation time 55969433 ps
CPU time 0.91 seconds
Started Mar 05 01:50:11 PM PST 24
Finished Mar 05 01:50:13 PM PST 24
Peak memory 214464 kb
Host smart-afbd41f8-88de-4664-8d7a-db8dca37f9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416675214 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.3416675214
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.1435298151
Short name T442
Test name
Test status
Simulation time 951812942 ps
CPU time 3.3 seconds
Started Mar 05 01:50:16 PM PST 24
Finished Mar 05 01:50:20 PM PST 24
Peak memory 214496 kb
Host smart-3a4a9c47-cd06-4669-aa90-69201c98847e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435298151 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.1435298151
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3187981091
Short name T704
Test name
Test status
Simulation time 220100132415 ps
CPU time 1514.43 seconds
Started Mar 05 01:50:08 PM PST 24
Finished Mar 05 02:15:23 PM PST 24
Peak memory 224564 kb
Host smart-c895006b-8133-4359-aaaf-786d0f804bd0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187981091 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3187981091
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert_test.1135131510
Short name T573
Test name
Test status
Simulation time 50398732 ps
CPU time 1.46 seconds
Started Mar 05 01:50:16 PM PST 24
Finished Mar 05 01:50:18 PM PST 24
Peak memory 205312 kb
Host smart-5fe9d2b1-6cf1-4f6e-a9db-9350ce9ddf75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135131510 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1135131510
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.3190695768
Short name T531
Test name
Test status
Simulation time 37606107 ps
CPU time 0.87 seconds
Started Mar 05 01:50:19 PM PST 24
Finished Mar 05 01:50:21 PM PST 24
Peak memory 214652 kb
Host smart-b3fd6035-ab9f-4fbe-a8aa-2b7d2336c26a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190695768 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.3190695768
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.785968596
Short name T62
Test name
Test status
Simulation time 62639501 ps
CPU time 1.23 seconds
Started Mar 05 01:50:17 PM PST 24
Finished Mar 05 01:50:19 PM PST 24
Peak memory 215568 kb
Host smart-cc20a725-293d-4b0c-b0a9-29bd5fee731f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785968596 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.785968596
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_genbits.3844553659
Short name T807
Test name
Test status
Simulation time 57101963 ps
CPU time 2.24 seconds
Started Mar 05 01:50:08 PM PST 24
Finished Mar 05 01:50:11 PM PST 24
Peak memory 218492 kb
Host smart-06d9d370-3690-491f-bb0e-c58faf0f4317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844553659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3844553659
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.1852149634
Short name T627
Test name
Test status
Simulation time 35925453 ps
CPU time 0.88 seconds
Started Mar 05 01:50:12 PM PST 24
Finished Mar 05 01:50:14 PM PST 24
Peak memory 214536 kb
Host smart-e92e38a9-b271-4f92-b956-e88f38a9ac19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852149634 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.1852149634
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1478541918
Short name T479
Test name
Test status
Simulation time 47915585 ps
CPU time 0.97 seconds
Started Mar 05 01:50:14 PM PST 24
Finished Mar 05 01:50:16 PM PST 24
Peak memory 214468 kb
Host smart-c79eacad-ff74-4e5f-be1d-f1da6862fb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478541918 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1478541918
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2365605082
Short name T472
Test name
Test status
Simulation time 770429222 ps
CPU time 3.65 seconds
Started Mar 05 01:50:12 PM PST 24
Finished Mar 05 01:50:17 PM PST 24
Peak memory 215536 kb
Host smart-7dfe722c-7c71-4b73-8249-20cbf7c43944
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365605082 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2365605082
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1183308836
Short name T202
Test name
Test status
Simulation time 165503588317 ps
CPU time 970.88 seconds
Started Mar 05 01:50:15 PM PST 24
Finished Mar 05 02:06:27 PM PST 24
Peak memory 219192 kb
Host smart-a290e0ee-3a21-4eaf-a027-df6ba986101c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183308836 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1183308836
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.2993180303
Short name T599
Test name
Test status
Simulation time 54511350 ps
CPU time 1.11 seconds
Started Mar 05 01:50:40 PM PST 24
Finished Mar 05 01:50:42 PM PST 24
Peak memory 214940 kb
Host smart-70a3f049-20e4-4e3e-b431-910f8dcc6902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993180303 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.2993180303
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1031597069
Short name T381
Test name
Test status
Simulation time 45313423 ps
CPU time 1.05 seconds
Started Mar 05 01:50:42 PM PST 24
Finished Mar 05 01:50:47 PM PST 24
Peak memory 205368 kb
Host smart-809ec167-9b20-4637-9c9c-3e6cade61d62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031597069 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1031597069
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_err.1590095647
Short name T97
Test name
Test status
Simulation time 18203519 ps
CPU time 1.16 seconds
Started Mar 05 01:50:31 PM PST 24
Finished Mar 05 01:50:33 PM PST 24
Peak memory 222448 kb
Host smart-02fe2760-6941-4594-b16e-80fce31d3911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590095647 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.1590095647
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.3438343692
Short name T507
Test name
Test status
Simulation time 50437291 ps
CPU time 1.64 seconds
Started Mar 05 01:50:16 PM PST 24
Finished Mar 05 01:50:18 PM PST 24
Peak memory 216644 kb
Host smart-635af37d-7d34-4c73-adb5-93d79bd6b4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438343692 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3438343692
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1658813954
Short name T123
Test name
Test status
Simulation time 21952027 ps
CPU time 1.07 seconds
Started Mar 05 01:50:36 PM PST 24
Finished Mar 05 01:50:37 PM PST 24
Peak memory 214820 kb
Host smart-ab041bb5-9ffa-4d5a-8ebc-487a1aabbaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658813954 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1658813954
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2112145658
Short name T355
Test name
Test status
Simulation time 43490790 ps
CPU time 0.9 seconds
Started Mar 05 01:50:13 PM PST 24
Finished Mar 05 01:50:16 PM PST 24
Peak memory 214456 kb
Host smart-f214ee5b-3be9-465b-abdd-277236a98321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112145658 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2112145658
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.4018855377
Short name T359
Test name
Test status
Simulation time 136622761 ps
CPU time 2.89 seconds
Started Mar 05 01:50:11 PM PST 24
Finished Mar 05 01:50:15 PM PST 24
Peak memory 215424 kb
Host smart-dd5fccb6-a452-4937-9d5a-58b93ce27a29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018855377 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.4018855377
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.3365266493
Short name T200
Test name
Test status
Simulation time 25232478408 ps
CPU time 150.75 seconds
Started Mar 05 01:50:39 PM PST 24
Finished Mar 05 01:53:10 PM PST 24
Peak memory 216976 kb
Host smart-807cafc8-b621-41bd-8846-4cb7dcff2567
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365266493 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.3365266493
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.4215528213
Short name T111
Test name
Test status
Simulation time 39072217 ps
CPU time 1.18 seconds
Started Mar 05 01:49:08 PM PST 24
Finished Mar 05 01:49:10 PM PST 24
Peak memory 214948 kb
Host smart-9bd307cb-3e1c-4b2b-b106-669462912c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215528213 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.4215528213
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.4257785215
Short name T625
Test name
Test status
Simulation time 68195469 ps
CPU time 0.89 seconds
Started Mar 05 01:49:25 PM PST 24
Finished Mar 05 01:49:26 PM PST 24
Peak memory 206224 kb
Host smart-c4d48745-cf3e-4bf2-855e-d0f28e9c65c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257785215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.4257785215
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3260698109
Short name T86
Test name
Test status
Simulation time 26805025 ps
CPU time 0.81 seconds
Started Mar 05 01:49:22 PM PST 24
Finished Mar 05 01:49:23 PM PST 24
Peak memory 214696 kb
Host smart-0c781567-1ae0-44ab-a473-a430e371aa02
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260698109 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3260698109
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3786418444
Short name T475
Test name
Test status
Simulation time 29718108 ps
CPU time 0.95 seconds
Started Mar 05 01:48:59 PM PST 24
Finished Mar 05 01:49:00 PM PST 24
Peak memory 216592 kb
Host smart-a75a1adf-86af-461f-856e-18a485b3dabb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786418444 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3786418444
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3863997439
Short name T427
Test name
Test status
Simulation time 38280910 ps
CPU time 0.85 seconds
Started Mar 05 01:49:15 PM PST 24
Finished Mar 05 01:49:16 PM PST 24
Peak memory 217076 kb
Host smart-4d8f0eee-a786-4efb-9f04-dbf99c658a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863997439 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3863997439
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1895284860
Short name T730
Test name
Test status
Simulation time 95577704 ps
CPU time 1.48 seconds
Started Mar 05 01:49:07 PM PST 24
Finished Mar 05 01:49:08 PM PST 24
Peak memory 217280 kb
Host smart-71ed465c-2088-42ed-969e-ba0b52c4d73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895284860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1895284860
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3877633788
Short name T400
Test name
Test status
Simulation time 26748183 ps
CPU time 1 seconds
Started Mar 05 01:49:18 PM PST 24
Finished Mar 05 01:49:20 PM PST 24
Peak memory 222532 kb
Host smart-2d8ddcd2-d691-4e81-b452-b5bd64a70dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877633788 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3877633788
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.492556608
Short name T116
Test name
Test status
Simulation time 17841953 ps
CPU time 0.99 seconds
Started Mar 05 01:49:04 PM PST 24
Finished Mar 05 01:49:05 PM PST 24
Peak memory 206280 kb
Host smart-88fbd515-2b34-43a9-bde8-07b1af0b2d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492556608 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.492556608
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.950799735
Short name T597
Test name
Test status
Simulation time 53300459 ps
CPU time 0.89 seconds
Started Mar 05 01:49:04 PM PST 24
Finished Mar 05 01:49:06 PM PST 24
Peak memory 214384 kb
Host smart-6db8a8d0-0814-41a8-acc9-73a32b84e3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950799735 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.950799735
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2313246056
Short name T728
Test name
Test status
Simulation time 581288358 ps
CPU time 2.83 seconds
Started Mar 05 01:49:08 PM PST 24
Finished Mar 05 01:49:11 PM PST 24
Peak memory 215744 kb
Host smart-ba542c82-91db-49b6-82e2-94817893a7e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313246056 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2313246056
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.855318993
Short name T647
Test name
Test status
Simulation time 143155762447 ps
CPU time 1495.51 seconds
Started Mar 05 01:49:00 PM PST 24
Finished Mar 05 02:13:56 PM PST 24
Peak memory 225148 kb
Host smart-4784f899-06ff-4c10-a120-73064d2ecf9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855318993 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.855318993
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.3040433286
Short name T79
Test name
Test status
Simulation time 21352747 ps
CPU time 1.19 seconds
Started Mar 05 01:50:36 PM PST 24
Finished Mar 05 01:50:38 PM PST 24
Peak memory 228968 kb
Host smart-d84a4400-ecbb-40c5-a8b7-01dcb335b18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040433286 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.3040433286
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.1859945802
Short name T725
Test name
Test status
Simulation time 27456569 ps
CPU time 1.21 seconds
Started Mar 05 01:50:26 PM PST 24
Finished Mar 05 01:50:27 PM PST 24
Peak memory 215688 kb
Host smart-18fb2b5d-9e5b-43db-8e12-ba12859704e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859945802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.1859945802
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.312037578
Short name T74
Test name
Test status
Simulation time 35406396 ps
CPU time 0.98 seconds
Started Mar 05 01:50:33 PM PST 24
Finished Mar 05 01:50:34 PM PST 24
Peak memory 217268 kb
Host smart-a48e7744-ff60-4343-9b86-61bdae730bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312037578 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.312037578
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.3267677499
Short name T511
Test name
Test status
Simulation time 34223413 ps
CPU time 1.35 seconds
Started Mar 05 01:50:24 PM PST 24
Finished Mar 05 01:50:26 PM PST 24
Peak memory 214572 kb
Host smart-02b9cde7-45fe-49ed-a7d8-10ffc1c5da6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267677499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.3267677499
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.2395975586
Short name T826
Test name
Test status
Simulation time 42637808 ps
CPU time 1.35 seconds
Started Mar 05 01:50:34 PM PST 24
Finished Mar 05 01:50:40 PM PST 24
Peak memory 231572 kb
Host smart-a28169fe-7a5c-47ee-bee0-6de4b60572d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395975586 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2395975586
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.2033144793
Short name T234
Test name
Test status
Simulation time 59788821 ps
CPU time 1.33 seconds
Started Mar 05 01:50:33 PM PST 24
Finished Mar 05 01:50:34 PM PST 24
Peak memory 217212 kb
Host smart-7fd5d550-4c4e-4352-9d2e-0b41e762c6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033144793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.2033144793
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.1559050212
Short name T444
Test name
Test status
Simulation time 30975997 ps
CPU time 0.88 seconds
Started Mar 05 01:50:34 PM PST 24
Finished Mar 05 01:50:35 PM PST 24
Peak memory 214668 kb
Host smart-e6098608-334a-476d-921c-d69f343ac302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559050212 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1559050212
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.2677204472
Short name T331
Test name
Test status
Simulation time 123606699 ps
CPU time 2.81 seconds
Started Mar 05 01:50:32 PM PST 24
Finished Mar 05 01:50:36 PM PST 24
Peak memory 215928 kb
Host smart-9a0d7865-9c0d-4901-ac40-4f0f6aade10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677204472 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.2677204472
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.740676359
Short name T612
Test name
Test status
Simulation time 18893401 ps
CPU time 1.07 seconds
Started Mar 05 01:50:21 PM PST 24
Finished Mar 05 01:50:22 PM PST 24
Peak memory 217080 kb
Host smart-7edf9fe6-62cc-4a74-9294-699d91c60097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740676359 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.740676359
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2003169958
Short name T715
Test name
Test status
Simulation time 35595100 ps
CPU time 1.35 seconds
Started Mar 05 01:50:13 PM PST 24
Finished Mar 05 01:50:16 PM PST 24
Peak memory 216796 kb
Host smart-5603dd41-1351-4415-9862-fda6fb5ca9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003169958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2003169958
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.970844212
Short name T785
Test name
Test status
Simulation time 20582764 ps
CPU time 1.2 seconds
Started Mar 05 01:50:40 PM PST 24
Finished Mar 05 01:50:42 PM PST 24
Peak memory 228972 kb
Host smart-c1a34e26-05f9-4710-888e-428a30ff77cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970844212 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.970844212
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1745849776
Short name T543
Test name
Test status
Simulation time 55543011 ps
CPU time 1.06 seconds
Started Mar 05 01:50:41 PM PST 24
Finished Mar 05 01:50:43 PM PST 24
Peak memory 215520 kb
Host smart-7ee4b6a1-aa19-42dd-bdcf-e89e2138eef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745849776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1745849776
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.1435574856
Short name T64
Test name
Test status
Simulation time 46659823 ps
CPU time 1.01 seconds
Started Mar 05 01:50:38 PM PST 24
Finished Mar 05 01:50:40 PM PST 24
Peak memory 215932 kb
Host smart-f63f1b45-1bf9-4d03-a6c2-170d9bc5e36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435574856 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1435574856
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/57.edn_err.2000585233
Short name T43
Test name
Test status
Simulation time 20159379 ps
CPU time 1.17 seconds
Started Mar 05 01:50:20 PM PST 24
Finished Mar 05 01:50:22 PM PST 24
Peak memory 222432 kb
Host smart-fb0e911a-1fbe-4663-b098-546da8f2c46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000585233 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.2000585233
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1019913707
Short name T408
Test name
Test status
Simulation time 35624296 ps
CPU time 1.54 seconds
Started Mar 05 01:50:33 PM PST 24
Finished Mar 05 01:50:35 PM PST 24
Peak memory 216792 kb
Host smart-76f62158-7266-45e8-adc8-a1d037c95e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019913707 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1019913707
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.3956207464
Short name T439
Test name
Test status
Simulation time 36741081 ps
CPU time 1.08 seconds
Started Mar 05 01:50:28 PM PST 24
Finished Mar 05 01:50:29 PM PST 24
Peak memory 217368 kb
Host smart-03d4ef86-175d-48f9-9698-98f6dfe628e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956207464 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3956207464
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1511728445
Short name T462
Test name
Test status
Simulation time 32186903 ps
CPU time 1.27 seconds
Started Mar 05 01:50:38 PM PST 24
Finished Mar 05 01:50:40 PM PST 24
Peak memory 216964 kb
Host smart-ded71ef6-ae08-4325-bb6b-bc638127fdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511728445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1511728445
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.3363070205
Short name T82
Test name
Test status
Simulation time 33231818 ps
CPU time 0.98 seconds
Started Mar 05 01:50:31 PM PST 24
Finished Mar 05 01:50:32 PM PST 24
Peak memory 230464 kb
Host smart-8053d596-e78b-401f-bde1-0b93150b3f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363070205 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3363070205
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.507779993
Short name T345
Test name
Test status
Simulation time 185906708 ps
CPU time 1.14 seconds
Started Mar 05 01:50:24 PM PST 24
Finished Mar 05 01:50:25 PM PST 24
Peak memory 218432 kb
Host smart-19683098-0cb1-44c2-8ad7-3c1d721fbab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507779993 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.507779993
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.126106491
Short name T742
Test name
Test status
Simulation time 22029675 ps
CPU time 1.09 seconds
Started Mar 05 01:49:08 PM PST 24
Finished Mar 05 01:49:10 PM PST 24
Peak memory 214844 kb
Host smart-25fc2426-39de-48f3-b873-927a7d65ea6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126106491 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.126106491
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3634515642
Short name T311
Test name
Test status
Simulation time 241568387 ps
CPU time 0.92 seconds
Started Mar 05 01:49:08 PM PST 24
Finished Mar 05 01:49:10 PM PST 24
Peak memory 205340 kb
Host smart-182c2f7c-e5e5-4c73-8ac0-4649a42383f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634515642 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3634515642
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1803159461
Short name T179
Test name
Test status
Simulation time 114864424 ps
CPU time 0.86 seconds
Started Mar 05 01:49:08 PM PST 24
Finished Mar 05 01:49:09 PM PST 24
Peak memory 214960 kb
Host smart-f0d6299e-d524-43b6-afd0-302506a62b07
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803159461 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1803159461
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.3278922983
Short name T680
Test name
Test status
Simulation time 83910482 ps
CPU time 1.03 seconds
Started Mar 05 01:49:09 PM PST 24
Finished Mar 05 01:49:10 PM PST 24
Peak memory 216904 kb
Host smart-998101fa-4e3d-446f-8e55-29ed3b5c71ec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278922983 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.3278922983
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.155928716
Short name T673
Test name
Test status
Simulation time 17806038 ps
CPU time 1.07 seconds
Started Mar 05 01:49:26 PM PST 24
Finished Mar 05 01:49:27 PM PST 24
Peak memory 217172 kb
Host smart-4a37858c-944a-4170-971b-28bf4c2f48c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155928716 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.155928716
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.912476958
Short name T770
Test name
Test status
Simulation time 54110440 ps
CPU time 1.67 seconds
Started Mar 05 01:49:05 PM PST 24
Finished Mar 05 01:49:07 PM PST 24
Peak memory 217000 kb
Host smart-8a8a5db4-ae9e-4528-b01a-6c3fec1d5aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912476958 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.912476958
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.578272656
Short name T128
Test name
Test status
Simulation time 29177982 ps
CPU time 0.86 seconds
Started Mar 05 01:49:07 PM PST 24
Finished Mar 05 01:49:08 PM PST 24
Peak memory 214736 kb
Host smart-2e5f5bc4-416a-4f11-888d-04e373c27061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578272656 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.578272656
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.3531215744
Short name T260
Test name
Test status
Simulation time 30414078 ps
CPU time 0.97 seconds
Started Mar 05 01:49:02 PM PST 24
Finished Mar 05 01:49:03 PM PST 24
Peak memory 206300 kb
Host smart-d2793000-68cb-4bbe-b5f4-860f43848347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531215744 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.3531215744
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3676714666
Short name T498
Test name
Test status
Simulation time 49534257 ps
CPU time 0.99 seconds
Started Mar 05 01:49:12 PM PST 24
Finished Mar 05 01:49:14 PM PST 24
Peak memory 214488 kb
Host smart-0066d5eb-48bb-4a69-bc16-a62d0958c541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676714666 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3676714666
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.4161399090
Short name T642
Test name
Test status
Simulation time 207875643 ps
CPU time 2.59 seconds
Started Mar 05 01:49:05 PM PST 24
Finished Mar 05 01:49:08 PM PST 24
Peak memory 215672 kb
Host smart-afdd39cc-ec3a-4c8b-aa80-1789a9faabbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161399090 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.4161399090
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.3313029365
Short name T748
Test name
Test status
Simulation time 43288653091 ps
CPU time 264.87 seconds
Started Mar 05 01:49:08 PM PST 24
Finished Mar 05 01:53:34 PM PST 24
Peak memory 217896 kb
Host smart-fc83ab59-e4e9-4c14-bf14-16604c769512
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313029365 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.3313029365
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.1508160413
Short name T772
Test name
Test status
Simulation time 29341056 ps
CPU time 0.82 seconds
Started Mar 05 01:50:32 PM PST 24
Finished Mar 05 01:50:33 PM PST 24
Peak memory 217044 kb
Host smart-eb17a907-fb03-4068-a9fb-352df5d1d0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508160413 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1508160413
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1092936824
Short name T278
Test name
Test status
Simulation time 79145095 ps
CPU time 1.12 seconds
Started Mar 05 01:50:18 PM PST 24
Finished Mar 05 01:50:20 PM PST 24
Peak memory 217056 kb
Host smart-492f3b0d-3c18-481d-9d1f-63e38fa638d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092936824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1092936824
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.3520796431
Short name T7
Test name
Test status
Simulation time 28230003 ps
CPU time 1.18 seconds
Started Mar 05 01:50:33 PM PST 24
Finished Mar 05 01:50:34 PM PST 24
Peak memory 215864 kb
Host smart-f5336bf1-7b4b-4960-8c9f-13c9f20d0e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520796431 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.3520796431
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.1355240744
Short name T268
Test name
Test status
Simulation time 48886997 ps
CPU time 1.3 seconds
Started Mar 05 01:50:34 PM PST 24
Finished Mar 05 01:50:35 PM PST 24
Peak memory 217216 kb
Host smart-ab173ee4-34d1-45bb-9213-231aafcdbe8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355240744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.1355240744
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.3233619234
Short name T563
Test name
Test status
Simulation time 82995957 ps
CPU time 0.9 seconds
Started Mar 05 01:50:39 PM PST 24
Finished Mar 05 01:50:40 PM PST 24
Peak memory 217392 kb
Host smart-3ddb22f7-d8eb-4990-888b-5890e8a50a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233619234 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.3233619234
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.2874376428
Short name T674
Test name
Test status
Simulation time 131889422 ps
CPU time 1.67 seconds
Started Mar 05 01:50:27 PM PST 24
Finished Mar 05 01:50:29 PM PST 24
Peak memory 215956 kb
Host smart-7f94ff4f-470a-456d-83ab-e45c87c37e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874376428 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.2874376428
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.2795458741
Short name T68
Test name
Test status
Simulation time 39270683 ps
CPU time 1.07 seconds
Started Mar 05 01:50:33 PM PST 24
Finished Mar 05 01:50:34 PM PST 24
Peak memory 215884 kb
Host smart-e258347b-d996-4d3a-82de-49832ea3671f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795458741 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.2795458741
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.522258080
Short name T690
Test name
Test status
Simulation time 37330692 ps
CPU time 1.16 seconds
Started Mar 05 01:50:34 PM PST 24
Finished Mar 05 01:50:35 PM PST 24
Peak memory 216712 kb
Host smart-cef3158f-d9af-4551-b3aa-1c8be7ab3027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522258080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.522258080
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.2494252045
Short name T148
Test name
Test status
Simulation time 19351212 ps
CPU time 1 seconds
Started Mar 05 01:50:34 PM PST 24
Finished Mar 05 01:50:35 PM PST 24
Peak memory 217380 kb
Host smart-7ecdc2e3-6ace-4fa0-bc89-b25b21a3d012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494252045 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.2494252045
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.3951459316
Short name T184
Test name
Test status
Simulation time 154522413 ps
CPU time 1.74 seconds
Started Mar 05 01:50:23 PM PST 24
Finished Mar 05 01:50:25 PM PST 24
Peak memory 217084 kb
Host smart-b8311a53-793d-44a9-9fcf-21a5a514f7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951459316 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.3951459316
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.4124155596
Short name T633
Test name
Test status
Simulation time 22277150 ps
CPU time 0.93 seconds
Started Mar 05 01:50:33 PM PST 24
Finished Mar 05 01:50:34 PM PST 24
Peak memory 217360 kb
Host smart-3247c428-1172-4592-8824-644558c42338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124155596 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.4124155596
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.2809415437
Short name T733
Test name
Test status
Simulation time 45223623 ps
CPU time 1.35 seconds
Started Mar 05 01:50:41 PM PST 24
Finished Mar 05 01:50:44 PM PST 24
Peak memory 215868 kb
Host smart-14de5db7-ee53-42ff-9d03-9583653e6096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809415437 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.2809415437
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_genbits.347241543
Short name T727
Test name
Test status
Simulation time 64564474 ps
CPU time 0.99 seconds
Started Mar 05 01:50:29 PM PST 24
Finished Mar 05 01:50:30 PM PST 24
Peak memory 215624 kb
Host smart-4f1f07cb-fd3b-44cf-b1d7-76ec7d8d4c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347241543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.347241543
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.3578938295
Short name T600
Test name
Test status
Simulation time 34044457 ps
CPU time 0.89 seconds
Started Mar 05 01:50:26 PM PST 24
Finished Mar 05 01:50:27 PM PST 24
Peak memory 216980 kb
Host smart-29a2e448-b76b-4c6f-9464-97e0897a8f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578938295 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3578938295
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.1691202582
Short name T504
Test name
Test status
Simulation time 84202595 ps
CPU time 2.04 seconds
Started Mar 05 01:50:27 PM PST 24
Finished Mar 05 01:50:29 PM PST 24
Peak memory 218464 kb
Host smart-8ace0142-cd40-46d8-ae9f-798386229f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691202582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.1691202582
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.1214064720
Short name T45
Test name
Test status
Simulation time 33124057 ps
CPU time 1.06 seconds
Started Mar 05 01:50:24 PM PST 24
Finished Mar 05 01:50:26 PM PST 24
Peak memory 230616 kb
Host smart-c764f104-0ffd-436c-9b5b-663f37e6fd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214064720 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.1214064720
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2480912987
Short name T526
Test name
Test status
Simulation time 22782665 ps
CPU time 0.99 seconds
Started Mar 05 01:50:35 PM PST 24
Finished Mar 05 01:50:36 PM PST 24
Peak memory 215620 kb
Host smart-1b5d12c5-70d1-49af-b41d-01fabb4f21f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480912987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2480912987
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.3956877119
Short name T458
Test name
Test status
Simulation time 49145110 ps
CPU time 1.02 seconds
Started Mar 05 01:50:32 PM PST 24
Finished Mar 05 01:50:33 PM PST 24
Peak memory 216036 kb
Host smart-ef8897a4-4097-4817-988f-e20094c43786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956877119 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.3956877119
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.1211609040
Short name T295
Test name
Test status
Simulation time 209938401 ps
CPU time 2.88 seconds
Started Mar 05 01:50:32 PM PST 24
Finished Mar 05 01:50:35 PM PST 24
Peak memory 218128 kb
Host smart-8483cb90-3f46-48c5-b04b-e66f075a4ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211609040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.1211609040
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.4143559457
Short name T261
Test name
Test status
Simulation time 241686970 ps
CPU time 1.47 seconds
Started Mar 05 01:49:32 PM PST 24
Finished Mar 05 01:49:34 PM PST 24
Peak memory 214868 kb
Host smart-228b5bcd-1fcd-4eb9-a2dd-26fe02586ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143559457 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.4143559457
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.1932910810
Short name T790
Test name
Test status
Simulation time 23269342 ps
CPU time 0.83 seconds
Started Mar 05 01:49:32 PM PST 24
Finished Mar 05 01:49:33 PM PST 24
Peak memory 205288 kb
Host smart-5b4b8358-13a4-4aa7-96a0-0e50d2c68768
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932910810 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.1932910810
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1431091704
Short name T172
Test name
Test status
Simulation time 17082475 ps
CPU time 0.79 seconds
Started Mar 05 01:49:41 PM PST 24
Finished Mar 05 01:49:42 PM PST 24
Peak memory 214972 kb
Host smart-aed1b825-a221-4236-9c6d-eafcbb2ffe89
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431091704 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1431091704
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_err.3521008769
Short name T604
Test name
Test status
Simulation time 41972918 ps
CPU time 1.13 seconds
Started Mar 05 01:49:27 PM PST 24
Finished Mar 05 01:49:28 PM PST 24
Peak memory 218528 kb
Host smart-0b0e2242-4adb-4a2f-9953-70d44bc52536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521008769 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3521008769
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.2789046232
Short name T390
Test name
Test status
Simulation time 82444384 ps
CPU time 1.32 seconds
Started Mar 05 01:49:05 PM PST 24
Finished Mar 05 01:49:07 PM PST 24
Peak memory 217104 kb
Host smart-38755349-b810-4946-a918-35ed06b833f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789046232 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.2789046232
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.4106811628
Short name T419
Test name
Test status
Simulation time 63224833 ps
CPU time 0.88 seconds
Started Mar 05 01:49:11 PM PST 24
Finished Mar 05 01:49:13 PM PST 24
Peak memory 214500 kb
Host smart-1f823d15-ee86-4930-b046-4dc8c3a253bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106811628 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.4106811628
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.4150846497
Short name T555
Test name
Test status
Simulation time 29421811 ps
CPU time 0.97 seconds
Started Mar 05 01:49:07 PM PST 24
Finished Mar 05 01:49:09 PM PST 24
Peak memory 206272 kb
Host smart-a125df9f-9003-4a43-a75a-3ffc5d3b4699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150846497 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.4150846497
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.2892387629
Short name T186
Test name
Test status
Simulation time 23049611 ps
CPU time 0.94 seconds
Started Mar 05 01:49:07 PM PST 24
Finished Mar 05 01:49:09 PM PST 24
Peak memory 214484 kb
Host smart-bdf97f7e-ae74-4e9b-943e-d3d4d9be9209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892387629 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.2892387629
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.1586996834
Short name T801
Test name
Test status
Simulation time 950878197 ps
CPU time 5.85 seconds
Started Mar 05 01:49:13 PM PST 24
Finished Mar 05 01:49:20 PM PST 24
Peak memory 214560 kb
Host smart-a8d74add-01d4-4074-a597-baea9f683402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586996834 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.1586996834
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.614157765
Short name T726
Test name
Test status
Simulation time 325053757198 ps
CPU time 962.72 seconds
Started Mar 05 01:49:23 PM PST 24
Finished Mar 05 02:05:26 PM PST 24
Peak memory 220316 kb
Host smart-99b5050f-9680-402c-b84a-f5159870f947
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614157765 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.614157765
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.1400384161
Short name T575
Test name
Test status
Simulation time 33503361 ps
CPU time 0.95 seconds
Started Mar 05 01:50:38 PM PST 24
Finished Mar 05 01:50:40 PM PST 24
Peak memory 217036 kb
Host smart-63b23633-190d-4a24-804c-fa783eacae0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400384161 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.1400384161
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2463073420
Short name T366
Test name
Test status
Simulation time 104951179 ps
CPU time 1.19 seconds
Started Mar 05 01:50:34 PM PST 24
Finished Mar 05 01:50:35 PM PST 24
Peak memory 215620 kb
Host smart-6770c657-3edb-4701-b995-33fbc8d0ec83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463073420 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2463073420
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.3846435334
Short name T75
Test name
Test status
Simulation time 67775636 ps
CPU time 1.05 seconds
Started Mar 05 01:50:33 PM PST 24
Finished Mar 05 01:50:34 PM PST 24
Peak memory 215964 kb
Host smart-a049acf5-f867-46ae-9a22-3bfce61d63b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846435334 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.3846435334
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.90090442
Short name T717
Test name
Test status
Simulation time 97340173 ps
CPU time 1.2 seconds
Started Mar 05 01:50:35 PM PST 24
Finished Mar 05 01:50:36 PM PST 24
Peak memory 217080 kb
Host smart-1567830c-452e-48b4-ba9e-83a7fbec7fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90090442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.90090442
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.1466545284
Short name T87
Test name
Test status
Simulation time 18965477 ps
CPU time 1.18 seconds
Started Mar 05 01:50:29 PM PST 24
Finished Mar 05 01:50:31 PM PST 24
Peak memory 222344 kb
Host smart-c33b6fa0-d6f9-46f3-8342-798d2cd02dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466545284 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.1466545284
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.1719396710
Short name T13
Test name
Test status
Simulation time 33559893 ps
CPU time 1.37 seconds
Started Mar 05 01:50:30 PM PST 24
Finished Mar 05 01:50:31 PM PST 24
Peak memory 217932 kb
Host smart-f6effd39-1032-4d19-9135-364abab913dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719396710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.1719396710
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.3460494576
Short name T169
Test name
Test status
Simulation time 338960042 ps
CPU time 1.13 seconds
Started Mar 05 01:50:32 PM PST 24
Finished Mar 05 01:50:33 PM PST 24
Peak memory 218324 kb
Host smart-05ffd700-059a-4ed2-bf87-01a282f13e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460494576 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.3460494576
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.2829863902
Short name T666
Test name
Test status
Simulation time 258291486 ps
CPU time 3.28 seconds
Started Mar 05 01:50:25 PM PST 24
Finished Mar 05 01:50:29 PM PST 24
Peak memory 217928 kb
Host smart-8d51c6b3-4a31-4758-92c5-eace1c5401cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829863902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.2829863902
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.4052457123
Short name T688
Test name
Test status
Simulation time 73028063 ps
CPU time 0.96 seconds
Started Mar 05 01:50:33 PM PST 24
Finished Mar 05 01:50:34 PM PST 24
Peak memory 216104 kb
Host smart-38b3d9a4-56a4-472b-9239-c4c7e1b01480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052457123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.4052457123
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1856293840
Short name T380
Test name
Test status
Simulation time 40635560 ps
CPU time 1.52 seconds
Started Mar 05 01:50:34 PM PST 24
Finished Mar 05 01:50:36 PM PST 24
Peak memory 216968 kb
Host smart-c2d3573e-1c81-4597-951c-390ccadac2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856293840 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1856293840
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.3642874405
Short name T60
Test name
Test status
Simulation time 54971648 ps
CPU time 1 seconds
Started Mar 05 01:50:38 PM PST 24
Finished Mar 05 01:50:39 PM PST 24
Peak memory 218392 kb
Host smart-c8ddf79c-bab0-4786-89ba-86bb0cd8555c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642874405 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.3642874405
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1411795018
Short name T558
Test name
Test status
Simulation time 63204201 ps
CPU time 1.37 seconds
Started Mar 05 01:50:39 PM PST 24
Finished Mar 05 01:50:41 PM PST 24
Peak memory 218196 kb
Host smart-c19a2968-c3bb-4031-be87-401aac9fe38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411795018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1411795018
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.537538709
Short name T55
Test name
Test status
Simulation time 26488716 ps
CPU time 1.18 seconds
Started Mar 05 01:50:30 PM PST 24
Finished Mar 05 01:50:31 PM PST 24
Peak memory 219188 kb
Host smart-08f81a12-e2da-449e-ae8b-81a2ced026fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537538709 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.537538709
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.1484169991
Short name T309
Test name
Test status
Simulation time 38075999 ps
CPU time 1.35 seconds
Started Mar 05 01:50:43 PM PST 24
Finished Mar 05 01:50:49 PM PST 24
Peak memory 215736 kb
Host smart-23d43597-497d-4f8f-8b26-ce4b0a799f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484169991 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1484169991
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.349284759
Short name T103
Test name
Test status
Simulation time 55612174 ps
CPU time 0.93 seconds
Started Mar 05 01:50:32 PM PST 24
Finished Mar 05 01:50:34 PM PST 24
Peak memory 230528 kb
Host smart-945fd42f-6867-4d7d-9c57-61808d1a15e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349284759 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.349284759
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.2221386649
Short name T623
Test name
Test status
Simulation time 178610418 ps
CPU time 1.23 seconds
Started Mar 05 01:50:39 PM PST 24
Finished Mar 05 01:50:41 PM PST 24
Peak memory 217412 kb
Host smart-10eb599d-136e-474f-a555-363b71cd8044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221386649 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.2221386649
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.2763299301
Short name T88
Test name
Test status
Simulation time 20226674 ps
CPU time 1.03 seconds
Started Mar 05 01:50:36 PM PST 24
Finished Mar 05 01:50:38 PM PST 24
Peak memory 217124 kb
Host smart-75734e59-8a9e-4938-ba59-73c3608e23a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763299301 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2763299301
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.1318300324
Short name T603
Test name
Test status
Simulation time 74798070 ps
CPU time 1.44 seconds
Started Mar 05 01:50:40 PM PST 24
Finished Mar 05 01:50:42 PM PST 24
Peak memory 217240 kb
Host smart-2b782d99-b0e2-47f7-bb5a-cf0251e752ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318300324 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.1318300324
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.3848984919
Short name T696
Test name
Test status
Simulation time 20770403 ps
CPU time 0.9 seconds
Started Mar 05 01:50:40 PM PST 24
Finished Mar 05 01:50:41 PM PST 24
Peak memory 217252 kb
Host smart-6c902516-fab7-479e-94ee-78a1acb08463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848984919 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3848984919
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2740184793
Short name T276
Test name
Test status
Simulation time 46059739 ps
CPU time 1.93 seconds
Started Mar 05 01:50:31 PM PST 24
Finished Mar 05 01:50:34 PM PST 24
Peak memory 215972 kb
Host smart-9e6e0d88-b6ea-4e13-a0bd-93913ba25909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740184793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2740184793
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.3396968468
Short name T94
Test name
Test status
Simulation time 74509668 ps
CPU time 1.19 seconds
Started Mar 05 01:49:25 PM PST 24
Finished Mar 05 01:49:26 PM PST 24
Peak memory 214864 kb
Host smart-62068ce3-cf1f-4390-b12b-6a972483f055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396968468 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.3396968468
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3177969435
Short name T786
Test name
Test status
Simulation time 19357698 ps
CPU time 0.97 seconds
Started Mar 05 01:49:36 PM PST 24
Finished Mar 05 01:49:37 PM PST 24
Peak memory 205808 kb
Host smart-1de344f2-c37c-473b-883c-8a4dfac828ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177969435 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3177969435
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1532294613
Short name T556
Test name
Test status
Simulation time 66685836 ps
CPU time 0.85 seconds
Started Mar 05 01:49:14 PM PST 24
Finished Mar 05 01:49:16 PM PST 24
Peak memory 215056 kb
Host smart-edc78dfa-c5b0-4fa8-8a1e-f2223b18b462
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532294613 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1532294613
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1172936035
Short name T57
Test name
Test status
Simulation time 151828108 ps
CPU time 1.23 seconds
Started Mar 05 01:49:20 PM PST 24
Finished Mar 05 01:49:21 PM PST 24
Peak memory 215464 kb
Host smart-b24206de-477b-4105-b8c8-01097cf465d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172936035 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1172936035
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2321644897
Short name T630
Test name
Test status
Simulation time 74684920 ps
CPU time 1.04 seconds
Started Mar 05 01:49:15 PM PST 24
Finished Mar 05 01:49:17 PM PST 24
Peak memory 218456 kb
Host smart-d1161e7c-5c35-441a-9535-f272ff51ef67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321644897 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2321644897
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1206165106
Short name T418
Test name
Test status
Simulation time 66432906 ps
CPU time 1.16 seconds
Started Mar 05 01:49:22 PM PST 24
Finished Mar 05 01:49:23 PM PST 24
Peak memory 215612 kb
Host smart-9c971e92-eecd-4867-8c81-26f2bb10bd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206165106 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1206165106
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.1455215069
Short name T438
Test name
Test status
Simulation time 77887978 ps
CPU time 0.83 seconds
Started Mar 05 01:49:30 PM PST 24
Finished Mar 05 01:49:31 PM PST 24
Peak memory 214384 kb
Host smart-5bacd55f-be83-43b8-8bc4-cc7038704700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455215069 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.1455215069
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.3809079068
Short name T250
Test name
Test status
Simulation time 39321614 ps
CPU time 0.92 seconds
Started Mar 05 01:49:24 PM PST 24
Finished Mar 05 01:49:25 PM PST 24
Peak memory 206284 kb
Host smart-99b19be2-232a-4bed-8d6a-65ed24548a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809079068 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.3809079068
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1116710781
Short name T720
Test name
Test status
Simulation time 15920291 ps
CPU time 0.94 seconds
Started Mar 05 01:49:30 PM PST 24
Finished Mar 05 01:49:31 PM PST 24
Peak memory 214364 kb
Host smart-8ef74866-23c2-455e-83b7-1d7669e2671b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116710781 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1116710781
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.4181310395
Short name T266
Test name
Test status
Simulation time 320616704 ps
CPU time 6.33 seconds
Started Mar 05 01:49:17 PM PST 24
Finished Mar 05 01:49:24 PM PST 24
Peak memory 215632 kb
Host smart-19854680-b5d4-41f9-ab4d-40c15e24a9fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181310395 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.4181310395
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.3118911019
Short name T335
Test name
Test status
Simulation time 25610175567 ps
CPU time 656.73 seconds
Started Mar 05 01:49:34 PM PST 24
Finished Mar 05 02:00:31 PM PST 24
Peak memory 222840 kb
Host smart-212ef7a2-2ae3-4579-8b39-4e4b90ee2fdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118911019 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.3118911019
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.2247340408
Short name T827
Test name
Test status
Simulation time 54029720 ps
CPU time 0.83 seconds
Started Mar 05 01:50:39 PM PST 24
Finished Mar 05 01:50:41 PM PST 24
Peak memory 217312 kb
Host smart-2b315466-bb66-4799-af1f-4f88401a1435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247340408 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.2247340408
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3537864481
Short name T549
Test name
Test status
Simulation time 50510207 ps
CPU time 1.01 seconds
Started Mar 05 01:50:40 PM PST 24
Finished Mar 05 01:50:48 PM PST 24
Peak memory 215704 kb
Host smart-6c730ba2-8700-4238-91c0-9eead480c216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537864481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3537864481
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.1010494542
Short name T796
Test name
Test status
Simulation time 25095896 ps
CPU time 1.25 seconds
Started Mar 05 01:50:44 PM PST 24
Finished Mar 05 01:50:48 PM PST 24
Peak memory 219220 kb
Host smart-35650b74-bcef-4c5f-89cb-66f868fe63ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010494542 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.1010494542
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.706401923
Short name T641
Test name
Test status
Simulation time 43291233 ps
CPU time 1.35 seconds
Started Mar 05 01:50:37 PM PST 24
Finished Mar 05 01:50:39 PM PST 24
Peak memory 217108 kb
Host smart-e4a1bc51-3be9-4305-94f4-9d41d731c8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706401923 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.706401923
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.1184749364
Short name T737
Test name
Test status
Simulation time 74979733 ps
CPU time 0.95 seconds
Started Mar 05 01:50:34 PM PST 24
Finished Mar 05 01:50:36 PM PST 24
Peak memory 222252 kb
Host smart-70547b99-ee69-4859-982e-f51a05cee490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184749364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1184749364
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.3330161233
Short name T368
Test name
Test status
Simulation time 69728132 ps
CPU time 1.13 seconds
Started Mar 05 01:50:37 PM PST 24
Finished Mar 05 01:50:38 PM PST 24
Peak memory 217224 kb
Host smart-6efa5ef0-1061-4d30-a72c-d5bdad08bbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330161233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.3330161233
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.706976163
Short name T56
Test name
Test status
Simulation time 38664601 ps
CPU time 1.03 seconds
Started Mar 05 01:50:34 PM PST 24
Finished Mar 05 01:50:35 PM PST 24
Peak memory 229000 kb
Host smart-e2a34a86-c819-419f-9440-2754cc764b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706976163 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.706976163
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.3939007139
Short name T333
Test name
Test status
Simulation time 51411642 ps
CPU time 1.16 seconds
Started Mar 05 01:50:32 PM PST 24
Finished Mar 05 01:50:34 PM PST 24
Peak memory 217116 kb
Host smart-6bb72624-af6b-42c9-acfd-ac4838350f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939007139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.3939007139
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.1704424359
Short name T159
Test name
Test status
Simulation time 23927569 ps
CPU time 1.1 seconds
Started Mar 05 01:50:29 PM PST 24
Finished Mar 05 01:50:30 PM PST 24
Peak memory 228964 kb
Host smart-9ded0b75-2698-4b47-9515-ea7650c6903f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704424359 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1704424359
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.3212048150
Short name T777
Test name
Test status
Simulation time 98992135 ps
CPU time 1.21 seconds
Started Mar 05 01:50:36 PM PST 24
Finished Mar 05 01:50:38 PM PST 24
Peak memory 218060 kb
Host smart-b675d542-abc1-46bf-9380-cb6c47523461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212048150 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.3212048150
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.2325146910
Short name T96
Test name
Test status
Simulation time 49129697 ps
CPU time 0.99 seconds
Started Mar 05 01:50:33 PM PST 24
Finished Mar 05 01:50:34 PM PST 24
Peak memory 230440 kb
Host smart-711b12f5-739b-4393-8039-98d6adfaf8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325146910 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.2325146910
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.414684580
Short name T834
Test name
Test status
Simulation time 58497299 ps
CPU time 1.65 seconds
Started Mar 05 01:50:30 PM PST 24
Finished Mar 05 01:50:32 PM PST 24
Peak memory 216712 kb
Host smart-07c1f80e-4271-428f-8e47-c51792a92893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414684580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.414684580
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.2048522092
Short name T812
Test name
Test status
Simulation time 37105137 ps
CPU time 0.91 seconds
Started Mar 05 01:50:26 PM PST 24
Finished Mar 05 01:50:28 PM PST 24
Peak memory 217280 kb
Host smart-991d8fac-5daa-4885-8db5-ae14ee3405a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048522092 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2048522092
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.267710143
Short name T396
Test name
Test status
Simulation time 30916648 ps
CPU time 1.27 seconds
Started Mar 05 01:50:22 PM PST 24
Finished Mar 05 01:50:24 PM PST 24
Peak memory 215640 kb
Host smart-9fa0be2a-2392-4752-a08c-94cb21cb27a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267710143 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.267710143
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.4204673460
Short name T59
Test name
Test status
Simulation time 52733732 ps
CPU time 1.05 seconds
Started Mar 05 01:50:33 PM PST 24
Finished Mar 05 01:50:34 PM PST 24
Peak memory 228796 kb
Host smart-97e97952-7bbd-4905-9f5c-6aeb49c78655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204673460 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.4204673460
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.4122332129
Short name T321
Test name
Test status
Simulation time 42314896 ps
CPU time 1.18 seconds
Started Mar 05 01:50:33 PM PST 24
Finished Mar 05 01:50:34 PM PST 24
Peak memory 218340 kb
Host smart-a619e01d-9d63-4684-932f-cf0ae85d98c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122332129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.4122332129
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.3139279346
Short name T102
Test name
Test status
Simulation time 33657534 ps
CPU time 0.87 seconds
Started Mar 05 01:50:42 PM PST 24
Finished Mar 05 01:50:46 PM PST 24
Peak memory 216924 kb
Host smart-a38581c9-d76e-4e3c-8f3f-c7dab25abaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139279346 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3139279346
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1292122236
Short name T815
Test name
Test status
Simulation time 66431330 ps
CPU time 1.38 seconds
Started Mar 05 01:50:34 PM PST 24
Finished Mar 05 01:50:36 PM PST 24
Peak memory 216976 kb
Host smart-a5ef80fd-9421-4737-8f83-e8f32f3943bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292122236 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1292122236
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.1019489088
Short name T784
Test name
Test status
Simulation time 55844014 ps
CPU time 1.12 seconds
Started Mar 05 01:50:59 PM PST 24
Finished Mar 05 01:51:00 PM PST 24
Peak memory 229048 kb
Host smart-609dfa53-7c05-424e-bafd-0ce9aaf73bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019489088 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1019489088
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.2214536880
Short name T689
Test name
Test status
Simulation time 33070139 ps
CPU time 1.39 seconds
Started Mar 05 01:50:50 PM PST 24
Finished Mar 05 01:50:51 PM PST 24
Peak memory 217020 kb
Host smart-571da9df-573e-433f-b733-d8ef8bf4d04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214536880 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2214536880
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1066005034
Short name T252
Test name
Test status
Simulation time 34004218 ps
CPU time 1.29 seconds
Started Mar 05 01:49:35 PM PST 24
Finished Mar 05 01:49:36 PM PST 24
Peak memory 214864 kb
Host smart-2216d519-dd41-4a21-b7f7-94e29e221b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066005034 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1066005034
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2085928283
Short name T357
Test name
Test status
Simulation time 29051918 ps
CPU time 1.13 seconds
Started Mar 05 01:49:20 PM PST 24
Finished Mar 05 01:49:21 PM PST 24
Peak memory 205364 kb
Host smart-1b07118a-6966-41d7-be10-c09b5698a8a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085928283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2085928283
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.2554775106
Short name T33
Test name
Test status
Simulation time 13013070 ps
CPU time 0.91 seconds
Started Mar 05 01:49:24 PM PST 24
Finished Mar 05 01:49:25 PM PST 24
Peak memory 215064 kb
Host smart-24d67e15-0093-4a93-9a70-6bc660879bb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554775106 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.2554775106
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.2132390421
Short name T71
Test name
Test status
Simulation time 21555273 ps
CPU time 1 seconds
Started Mar 05 01:49:30 PM PST 24
Finished Mar 05 01:49:31 PM PST 24
Peak memory 216988 kb
Host smart-3422ba8b-af05-41ab-a50c-0422e19ec7c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132390421 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.2132390421
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.706553231
Short name T619
Test name
Test status
Simulation time 53685586 ps
CPU time 1.02 seconds
Started Mar 05 01:49:18 PM PST 24
Finished Mar 05 01:49:20 PM PST 24
Peak memory 217548 kb
Host smart-f4bf034b-0066-4e91-84bf-82ed94042a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706553231 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.706553231
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.4065731148
Short name T832
Test name
Test status
Simulation time 64236111 ps
CPU time 1.36 seconds
Started Mar 05 01:49:26 PM PST 24
Finished Mar 05 01:49:28 PM PST 24
Peak memory 215796 kb
Host smart-e2987653-6483-4a79-ad6d-eed860dff22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065731148 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.4065731148
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.2440486412
Short name T30
Test name
Test status
Simulation time 66038543 ps
CPU time 0.85 seconds
Started Mar 05 01:49:15 PM PST 24
Finished Mar 05 01:49:17 PM PST 24
Peak memory 214668 kb
Host smart-32bbe55d-0fbe-42a4-af3d-bd1d627aecd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440486412 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.2440486412
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.2157261023
Short name T117
Test name
Test status
Simulation time 18923699 ps
CPU time 1.01 seconds
Started Mar 05 01:49:14 PM PST 24
Finished Mar 05 01:49:16 PM PST 24
Peak memory 206252 kb
Host smart-880e19e0-fd07-47ff-b2d2-0ca8d88ffc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157261023 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2157261023
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1372102939
Short name T617
Test name
Test status
Simulation time 16745200 ps
CPU time 0.99 seconds
Started Mar 05 01:49:24 PM PST 24
Finished Mar 05 01:49:25 PM PST 24
Peak memory 214476 kb
Host smart-717978ed-9857-4a87-bd42-e26d5155f495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372102939 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1372102939
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.4117606250
Short name T241
Test name
Test status
Simulation time 146509751 ps
CPU time 2.11 seconds
Started Mar 05 01:49:20 PM PST 24
Finished Mar 05 01:49:23 PM PST 24
Peak memory 214428 kb
Host smart-fba5ffd0-3878-4954-bcf5-d15be814f082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117606250 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.4117606250
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.3828879892
Short name T198
Test name
Test status
Simulation time 86864823157 ps
CPU time 928.28 seconds
Started Mar 05 01:49:30 PM PST 24
Finished Mar 05 02:04:59 PM PST 24
Peak memory 219112 kb
Host smart-4f3fc04c-40c5-4668-8c8c-af3a556f1174
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828879892 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.3828879892
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.3239942617
Short name T69
Test name
Test status
Simulation time 46884672 ps
CPU time 1.09 seconds
Started Mar 05 01:50:41 PM PST 24
Finished Mar 05 01:50:45 PM PST 24
Peak memory 215852 kb
Host smart-52ab133a-f446-4abd-b6fd-5f101a4228f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239942617 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3239942617
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3056460686
Short name T387
Test name
Test status
Simulation time 62724380 ps
CPU time 1.29 seconds
Started Mar 05 01:50:41 PM PST 24
Finished Mar 05 01:50:45 PM PST 24
Peak memory 217144 kb
Host smart-b187c15c-68f2-462b-822f-ab374605c61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056460686 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3056460686
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.3882247631
Short name T167
Test name
Test status
Simulation time 35639518 ps
CPU time 1.04 seconds
Started Mar 05 01:50:43 PM PST 24
Finished Mar 05 01:50:47 PM PST 24
Peak memory 216032 kb
Host smart-21e40520-20c9-42bf-97d6-4a4f0c39d01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882247631 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3882247631
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.443198193
Short name T482
Test name
Test status
Simulation time 41564578 ps
CPU time 1.16 seconds
Started Mar 05 01:50:39 PM PST 24
Finished Mar 05 01:50:41 PM PST 24
Peak memory 217048 kb
Host smart-57c9b712-8458-46a1-9330-edf4dc6021a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443198193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.443198193
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.2043717283
Short name T9
Test name
Test status
Simulation time 19068291 ps
CPU time 1.09 seconds
Started Mar 05 01:50:40 PM PST 24
Finished Mar 05 01:50:42 PM PST 24
Peak memory 217152 kb
Host smart-c4ae5fde-3e54-4a53-996f-792854fe8279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043717283 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.2043717283
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.1694534364
Short name T586
Test name
Test status
Simulation time 155213836 ps
CPU time 1.3 seconds
Started Mar 05 01:50:43 PM PST 24
Finished Mar 05 01:50:49 PM PST 24
Peak memory 218308 kb
Host smart-9bcad2ea-202c-47e2-be6a-07a7d6be1000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694534364 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.1694534364
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.24130924
Short name T158
Test name
Test status
Simulation time 20010837 ps
CPU time 1.02 seconds
Started Mar 05 01:50:30 PM PST 24
Finished Mar 05 01:50:32 PM PST 24
Peak memory 217424 kb
Host smart-4692e647-2298-4d58-a743-ddeb3aae5a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24130924 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.24130924
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2254580300
Short name T682
Test name
Test status
Simulation time 2215845373 ps
CPU time 69.32 seconds
Started Mar 05 01:50:38 PM PST 24
Finished Mar 05 01:51:48 PM PST 24
Peak memory 216972 kb
Host smart-599bf64d-55bc-4348-a508-787300efc3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254580300 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2254580300
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.513369527
Short name T322
Test name
Test status
Simulation time 19106018 ps
CPU time 1.04 seconds
Started Mar 05 01:50:40 PM PST 24
Finished Mar 05 01:50:42 PM PST 24
Peak memory 216980 kb
Host smart-ddc5322c-ad7f-4f72-b3e9-fdc1aee8ab07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513369527 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.513369527
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.2991144338
Short name T124
Test name
Test status
Simulation time 137689332 ps
CPU time 1.16 seconds
Started Mar 05 01:50:30 PM PST 24
Finished Mar 05 01:50:31 PM PST 24
Peak memory 215932 kb
Host smart-7272bc83-6a80-4f30-8c6d-4589da041c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991144338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.2991144338
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.1183002412
Short name T84
Test name
Test status
Simulation time 73332740 ps
CPU time 1.16 seconds
Started Mar 05 01:50:38 PM PST 24
Finished Mar 05 01:50:39 PM PST 24
Peak memory 231572 kb
Host smart-f6ada75b-c22b-4dd2-9871-f9702e547d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183002412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1183002412
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.1547880585
Short name T525
Test name
Test status
Simulation time 47058268 ps
CPU time 1.09 seconds
Started Mar 05 01:50:38 PM PST 24
Finished Mar 05 01:50:39 PM PST 24
Peak memory 215896 kb
Host smart-ad800d22-10b8-450d-ba25-432da4378ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547880585 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.1547880585
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.1303924155
Short name T508
Test name
Test status
Simulation time 25991058 ps
CPU time 1.3 seconds
Started Mar 05 01:50:37 PM PST 24
Finished Mar 05 01:50:38 PM PST 24
Peak memory 230532 kb
Host smart-aadcc3fb-e345-48ef-9578-0444293edf3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303924155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.1303924155
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.394221725
Short name T287
Test name
Test status
Simulation time 58809869 ps
CPU time 1.3 seconds
Started Mar 05 01:50:33 PM PST 24
Finished Mar 05 01:50:35 PM PST 24
Peak memory 216956 kb
Host smart-fad66af7-2764-4a00-80df-c89d27d9c3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394221725 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.394221725
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.4057205577
Short name T735
Test name
Test status
Simulation time 32725870 ps
CPU time 1.07 seconds
Started Mar 05 01:50:34 PM PST 24
Finished Mar 05 01:50:35 PM PST 24
Peak memory 219192 kb
Host smart-4f588009-6963-42c9-92ff-b17eaa06a6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057205577 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.4057205577
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3965566374
Short name T529
Test name
Test status
Simulation time 111693306 ps
CPU time 2.18 seconds
Started Mar 05 01:50:33 PM PST 24
Finished Mar 05 01:50:35 PM PST 24
Peak memory 217460 kb
Host smart-b836f130-2baf-4d8d-a694-13ec67114e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965566374 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3965566374
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.1483420247
Short name T41
Test name
Test status
Simulation time 165599534 ps
CPU time 1.06 seconds
Started Mar 05 01:50:44 PM PST 24
Finished Mar 05 01:50:48 PM PST 24
Peak memory 222396 kb
Host smart-6d6ec4a0-929d-4d36-aba0-23be695f03da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483420247 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.1483420247
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2624270845
Short name T561
Test name
Test status
Simulation time 41232575 ps
CPU time 1.62 seconds
Started Mar 05 01:50:43 PM PST 24
Finished Mar 05 01:50:48 PM PST 24
Peak memory 217088 kb
Host smart-a4e4c085-3319-44f3-a41e-2ed4eeda031d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624270845 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2624270845
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.1164897637
Short name T707
Test name
Test status
Simulation time 24482124 ps
CPU time 0.92 seconds
Started Mar 05 01:50:42 PM PST 24
Finished Mar 05 01:50:46 PM PST 24
Peak memory 217212 kb
Host smart-8e6f4adf-5a21-4527-b0cb-44acdbe3df9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164897637 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1164897637
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.126358170
Short name T651
Test name
Test status
Simulation time 81371381 ps
CPU time 1.5 seconds
Started Mar 05 01:50:31 PM PST 24
Finished Mar 05 01:50:33 PM PST 24
Peak memory 217024 kb
Host smart-86d374a7-ed80-4c8d-a448-565fe430a699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126358170 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.126358170
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%