Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.00 98.27 93.63 96.84 82.66 96.87 96.58 93.15


Total test records in report: 967
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T791 /workspace/coverage/default/35.edn_err.4133035533 Mar 07 02:40:36 PM PST 24 Mar 07 02:40:37 PM PST 24 76290337 ps
T792 /workspace/coverage/default/113.edn_genbits.4043500019 Mar 07 02:41:58 PM PST 24 Mar 07 02:41:59 PM PST 24 46241861 ps
T793 /workspace/coverage/default/46.edn_alert.1399984901 Mar 07 02:41:17 PM PST 24 Mar 07 02:41:18 PM PST 24 72939007 ps
T794 /workspace/coverage/default/12.edn_genbits.2236558033 Mar 07 02:39:28 PM PST 24 Mar 07 02:39:31 PM PST 24 38818714 ps
T795 /workspace/coverage/default/278.edn_genbits.4137793857 Mar 07 02:42:42 PM PST 24 Mar 07 02:42:43 PM PST 24 40767253 ps
T796 /workspace/coverage/default/11.edn_alert_test.1475299850 Mar 07 02:39:28 PM PST 24 Mar 07 02:39:30 PM PST 24 81079092 ps
T797 /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1376650149 Mar 07 02:40:18 PM PST 24 Mar 07 02:47:54 PM PST 24 17874262990 ps
T798 /workspace/coverage/default/33.edn_stress_all_with_rand_reset.594518629 Mar 07 02:40:34 PM PST 24 Mar 07 03:00:10 PM PST 24 44860932959 ps
T799 /workspace/coverage/default/38.edn_smoke.696761961 Mar 07 02:40:45 PM PST 24 Mar 07 02:40:46 PM PST 24 22722285 ps
T800 /workspace/coverage/default/51.edn_err.853192903 Mar 07 02:41:37 PM PST 24 Mar 07 02:41:39 PM PST 24 31595792 ps
T265 /workspace/coverage/default/0.edn_regwen.788537538 Mar 07 02:38:29 PM PST 24 Mar 07 02:38:34 PM PST 24 20836316 ps
T801 /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2648768911 Mar 07 02:40:02 PM PST 24 Mar 07 02:41:32 PM PST 24 8559911094 ps
T802 /workspace/coverage/default/1.edn_alert_test.990646439 Mar 07 02:38:43 PM PST 24 Mar 07 02:38:44 PM PST 24 55575655 ps
T803 /workspace/coverage/default/4.edn_regwen.116613447 Mar 07 02:38:51 PM PST 24 Mar 07 02:38:52 PM PST 24 19091861 ps
T804 /workspace/coverage/default/202.edn_genbits.249190992 Mar 07 02:42:19 PM PST 24 Mar 07 02:42:21 PM PST 24 41258937 ps
T805 /workspace/coverage/default/7.edn_intr.2178203397 Mar 07 02:39:07 PM PST 24 Mar 07 02:39:09 PM PST 24 21934263 ps
T806 /workspace/coverage/default/153.edn_genbits.2280940532 Mar 07 02:42:07 PM PST 24 Mar 07 02:42:09 PM PST 24 45920488 ps
T807 /workspace/coverage/default/38.edn_err.2659925071 Mar 07 02:40:44 PM PST 24 Mar 07 02:40:45 PM PST 24 18721290 ps
T808 /workspace/coverage/default/24.edn_disable_auto_req_mode.4226483615 Mar 07 02:40:02 PM PST 24 Mar 07 02:40:03 PM PST 24 28693232 ps
T809 /workspace/coverage/default/43.edn_smoke.1220390388 Mar 07 02:41:04 PM PST 24 Mar 07 02:41:05 PM PST 24 160133558 ps
T90 /workspace/coverage/default/68.edn_err.2799019292 Mar 07 02:41:29 PM PST 24 Mar 07 02:41:30 PM PST 24 55914283 ps
T810 /workspace/coverage/default/212.edn_genbits.3986189618 Mar 07 02:42:19 PM PST 24 Mar 07 02:42:20 PM PST 24 44465081 ps
T811 /workspace/coverage/default/16.edn_smoke.4106105656 Mar 07 02:39:38 PM PST 24 Mar 07 02:39:40 PM PST 24 36425742 ps
T812 /workspace/coverage/default/2.edn_alert_test.778090373 Mar 07 02:38:43 PM PST 24 Mar 07 02:38:44 PM PST 24 22107506 ps
T813 /workspace/coverage/default/21.edn_alert.3627171855 Mar 07 02:39:55 PM PST 24 Mar 07 02:39:57 PM PST 24 26856240 ps
T814 /workspace/coverage/default/10.edn_genbits.2286323897 Mar 07 02:39:18 PM PST 24 Mar 07 02:39:19 PM PST 24 171922924 ps
T815 /workspace/coverage/default/163.edn_genbits.1614315720 Mar 07 02:42:09 PM PST 24 Mar 07 02:42:11 PM PST 24 33419796 ps
T816 /workspace/coverage/default/107.edn_genbits.1221958544 Mar 07 02:41:56 PM PST 24 Mar 07 02:41:57 PM PST 24 30604509 ps
T66 /workspace/coverage/default/74.edn_err.1809662413 Mar 07 02:41:30 PM PST 24 Mar 07 02:41:31 PM PST 24 35501254 ps
T817 /workspace/coverage/default/264.edn_genbits.2325924774 Mar 07 02:42:36 PM PST 24 Mar 07 02:42:37 PM PST 24 129035448 ps
T818 /workspace/coverage/default/249.edn_genbits.2087299251 Mar 07 02:42:28 PM PST 24 Mar 07 02:42:29 PM PST 24 59134742 ps
T99 /workspace/coverage/default/4.edn_err.3401633461 Mar 07 02:38:52 PM PST 24 Mar 07 02:38:53 PM PST 24 33985854 ps
T819 /workspace/coverage/default/33.edn_alert_test.2726028329 Mar 07 02:40:35 PM PST 24 Mar 07 02:40:37 PM PST 24 48585351 ps
T820 /workspace/coverage/default/25.edn_genbits.142577914 Mar 07 02:40:05 PM PST 24 Mar 07 02:40:07 PM PST 24 61901875 ps
T821 /workspace/coverage/default/149.edn_genbits.3639662587 Mar 07 02:42:07 PM PST 24 Mar 07 02:42:09 PM PST 24 85617767 ps
T822 /workspace/coverage/default/14.edn_err.1803124175 Mar 07 02:39:42 PM PST 24 Mar 07 02:39:44 PM PST 24 31664623 ps
T823 /workspace/coverage/default/15.edn_smoke.3678024823 Mar 07 02:39:37 PM PST 24 Mar 07 02:39:38 PM PST 24 32001391 ps
T824 /workspace/coverage/default/268.edn_genbits.1027785571 Mar 07 02:42:37 PM PST 24 Mar 07 02:42:40 PM PST 24 81831738 ps
T825 /workspace/coverage/default/6.edn_genbits.1502032074 Mar 07 02:39:00 PM PST 24 Mar 07 02:39:02 PM PST 24 80947331 ps
T826 /workspace/coverage/default/115.edn_genbits.1569236550 Mar 07 02:41:57 PM PST 24 Mar 07 02:41:59 PM PST 24 46825963 ps
T827 /workspace/coverage/default/1.edn_genbits.2186030139 Mar 07 02:38:35 PM PST 24 Mar 07 02:38:38 PM PST 24 43372590 ps
T828 /workspace/coverage/default/298.edn_genbits.2824481556 Mar 07 02:42:41 PM PST 24 Mar 07 02:42:42 PM PST 24 25461839 ps
T829 /workspace/coverage/default/15.edn_disable_auto_req_mode.2430705169 Mar 07 02:39:40 PM PST 24 Mar 07 02:39:42 PM PST 24 46014071 ps
T830 /workspace/coverage/default/41.edn_err.2782342584 Mar 07 02:40:53 PM PST 24 Mar 07 02:40:54 PM PST 24 34939223 ps
T831 /workspace/coverage/default/43.edn_err.3751324001 Mar 07 02:41:06 PM PST 24 Mar 07 02:41:07 PM PST 24 23296284 ps
T832 /workspace/coverage/default/39.edn_alert.2525437111 Mar 07 02:40:54 PM PST 24 Mar 07 02:40:56 PM PST 24 99210059 ps
T833 /workspace/coverage/default/26.edn_intr.3487568118 Mar 07 02:40:14 PM PST 24 Mar 07 02:40:16 PM PST 24 34065259 ps
T834 /workspace/coverage/default/9.edn_genbits.1671380943 Mar 07 02:39:19 PM PST 24 Mar 07 02:39:20 PM PST 24 56350215 ps
T835 /workspace/coverage/default/43.edn_genbits.3521127531 Mar 07 02:41:05 PM PST 24 Mar 07 02:41:06 PM PST 24 75033702 ps
T836 /workspace/coverage/default/54.edn_genbits.2484129523 Mar 07 02:41:30 PM PST 24 Mar 07 02:41:33 PM PST 24 77579168 ps
T837 /workspace/coverage/default/31.edn_disable.2436333517 Mar 07 02:40:28 PM PST 24 Mar 07 02:40:29 PM PST 24 77056035 ps
T838 /workspace/coverage/default/233.edn_genbits.853085017 Mar 07 02:42:37 PM PST 24 Mar 07 02:42:38 PM PST 24 204528779 ps
T236 /workspace/coverage/cover_reg_top/18.edn_csr_rw.3460933542 Mar 07 01:18:29 PM PST 24 Mar 07 01:18:30 PM PST 24 60412234 ps
T237 /workspace/coverage/cover_reg_top/15.edn_csr_rw.181952406 Mar 07 01:18:18 PM PST 24 Mar 07 01:18:19 PM PST 24 22921378 ps
T238 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2067727368 Mar 07 01:18:17 PM PST 24 Mar 07 01:18:20 PM PST 24 378875859 ps
T208 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2905138472 Mar 07 01:18:04 PM PST 24 Mar 07 01:18:05 PM PST 24 23150817 ps
T226 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.433934373 Mar 07 01:18:04 PM PST 24 Mar 07 01:18:05 PM PST 24 77165374 ps
T196 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1754493490 Mar 07 01:17:47 PM PST 24 Mar 07 01:17:49 PM PST 24 61875780 ps
T198 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.602265003 Mar 07 01:18:16 PM PST 24 Mar 07 01:18:18 PM PST 24 18481854 ps
T839 /workspace/coverage/cover_reg_top/39.edn_intr_test.3321220303 Mar 07 01:18:36 PM PST 24 Mar 07 01:18:37 PM PST 24 45128033 ps
T209 /workspace/coverage/cover_reg_top/8.edn_csr_rw.51945560 Mar 07 01:18:06 PM PST 24 Mar 07 01:18:08 PM PST 24 43410450 ps
T197 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.135833864 Mar 07 01:18:05 PM PST 24 Mar 07 01:18:06 PM PST 24 55307438 ps
T840 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3340216640 Mar 07 01:18:05 PM PST 24 Mar 07 01:18:07 PM PST 24 22574088 ps
T210 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.119751740 Mar 07 01:18:16 PM PST 24 Mar 07 01:18:18 PM PST 24 195119261 ps
T841 /workspace/coverage/cover_reg_top/46.edn_intr_test.2834248960 Mar 07 01:18:38 PM PST 24 Mar 07 01:18:39 PM PST 24 30109958 ps
T842 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3768652485 Mar 07 01:18:33 PM PST 24 Mar 07 01:18:36 PM PST 24 289032538 ps
T211 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1750242297 Mar 07 01:18:05 PM PST 24 Mar 07 01:18:06 PM PST 24 52248317 ps
T843 /workspace/coverage/cover_reg_top/24.edn_intr_test.1801690889 Mar 07 01:18:35 PM PST 24 Mar 07 01:18:37 PM PST 24 15583672 ps
T844 /workspace/coverage/cover_reg_top/35.edn_intr_test.692845504 Mar 07 01:18:31 PM PST 24 Mar 07 01:18:32 PM PST 24 36530636 ps
T212 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.378665136 Mar 07 01:17:50 PM PST 24 Mar 07 01:17:52 PM PST 24 97861272 ps
T845 /workspace/coverage/cover_reg_top/26.edn_intr_test.694717053 Mar 07 01:18:35 PM PST 24 Mar 07 01:18:36 PM PST 24 32245964 ps
T239 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3420752388 Mar 07 01:18:08 PM PST 24 Mar 07 01:18:10 PM PST 24 92989775 ps
T846 /workspace/coverage/cover_reg_top/47.edn_intr_test.3010484490 Mar 07 01:18:31 PM PST 24 Mar 07 01:18:32 PM PST 24 12502033 ps
T227 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1894915523 Mar 07 01:18:36 PM PST 24 Mar 07 01:18:37 PM PST 24 60751308 ps
T847 /workspace/coverage/cover_reg_top/48.edn_intr_test.1684211916 Mar 07 01:18:33 PM PST 24 Mar 07 01:18:34 PM PST 24 24249851 ps
T848 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.711971654 Mar 07 01:17:49 PM PST 24 Mar 07 01:17:50 PM PST 24 22466871 ps
T849 /workspace/coverage/cover_reg_top/14.edn_tl_errors.3201764663 Mar 07 01:18:18 PM PST 24 Mar 07 01:18:22 PM PST 24 464659808 ps
T850 /workspace/coverage/cover_reg_top/17.edn_intr_test.2681292207 Mar 07 01:18:32 PM PST 24 Mar 07 01:18:33 PM PST 24 26205312 ps
T851 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.4282284993 Mar 07 01:18:02 PM PST 24 Mar 07 01:18:03 PM PST 24 35076077 ps
T852 /workspace/coverage/cover_reg_top/37.edn_intr_test.4168459977 Mar 07 01:18:32 PM PST 24 Mar 07 01:18:33 PM PST 24 23588060 ps
T853 /workspace/coverage/cover_reg_top/18.edn_intr_test.228782203 Mar 07 01:18:30 PM PST 24 Mar 07 01:18:31 PM PST 24 73352998 ps
T854 /workspace/coverage/cover_reg_top/2.edn_tl_errors.1597971781 Mar 07 01:17:54 PM PST 24 Mar 07 01:17:56 PM PST 24 63630989 ps
T855 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.355820716 Mar 07 01:18:04 PM PST 24 Mar 07 01:18:05 PM PST 24 49872058 ps
T213 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.862824207 Mar 07 01:18:17 PM PST 24 Mar 07 01:18:18 PM PST 24 34481001 ps
T228 /workspace/coverage/cover_reg_top/17.edn_csr_rw.3683959230 Mar 07 01:18:39 PM PST 24 Mar 07 01:18:40 PM PST 24 41640504 ps
T240 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.486328656 Mar 07 01:18:38 PM PST 24 Mar 07 01:18:41 PM PST 24 86176557 ps
T214 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2044202632 Mar 07 01:18:04 PM PST 24 Mar 07 01:18:05 PM PST 24 25658616 ps
T856 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2448958502 Mar 07 01:18:09 PM PST 24 Mar 07 01:18:10 PM PST 24 35094649 ps
T215 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2389200989 Mar 07 01:18:03 PM PST 24 Mar 07 01:18:06 PM PST 24 272776804 ps
T229 /workspace/coverage/cover_reg_top/11.edn_csr_rw.3754695400 Mar 07 01:18:17 PM PST 24 Mar 07 01:18:18 PM PST 24 13231222 ps
T857 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.559653345 Mar 07 01:18:05 PM PST 24 Mar 07 01:18:06 PM PST 24 42466384 ps
T858 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1774564332 Mar 07 01:18:17 PM PST 24 Mar 07 01:18:19 PM PST 24 247051320 ps
T248 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.4030467614 Mar 07 01:18:16 PM PST 24 Mar 07 01:18:25 PM PST 24 1158373543 ps
T230 /workspace/coverage/cover_reg_top/9.edn_csr_rw.2308673592 Mar 07 01:18:05 PM PST 24 Mar 07 01:18:06 PM PST 24 44248863 ps
T859 /workspace/coverage/cover_reg_top/30.edn_intr_test.2778887750 Mar 07 01:18:36 PM PST 24 Mar 07 01:18:37 PM PST 24 41156864 ps
T231 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.804388427 Mar 07 01:18:16 PM PST 24 Mar 07 01:18:18 PM PST 24 25549671 ps
T860 /workspace/coverage/cover_reg_top/20.edn_intr_test.1460034066 Mar 07 01:18:32 PM PST 24 Mar 07 01:18:32 PM PST 24 40697176 ps
T861 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2613157520 Mar 07 01:18:05 PM PST 24 Mar 07 01:18:07 PM PST 24 167596237 ps
T862 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1007156139 Mar 07 01:17:54 PM PST 24 Mar 07 01:17:57 PM PST 24 183693363 ps
T232 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2879574165 Mar 07 01:18:18 PM PST 24 Mar 07 01:18:20 PM PST 24 404845715 ps
T863 /workspace/coverage/cover_reg_top/3.edn_intr_test.3810921282 Mar 07 01:18:03 PM PST 24 Mar 07 01:18:04 PM PST 24 13787819 ps
T864 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1992937390 Mar 07 01:18:19 PM PST 24 Mar 07 01:18:20 PM PST 24 23424916 ps
T865 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1771467616 Mar 07 01:18:04 PM PST 24 Mar 07 01:18:07 PM PST 24 92569219 ps
T866 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3031668629 Mar 07 01:18:34 PM PST 24 Mar 07 01:18:35 PM PST 24 47214642 ps
T867 /workspace/coverage/cover_reg_top/34.edn_intr_test.2758773934 Mar 07 01:18:36 PM PST 24 Mar 07 01:18:37 PM PST 24 14434348 ps
T868 /workspace/coverage/cover_reg_top/28.edn_intr_test.835732398 Mar 07 01:18:39 PM PST 24 Mar 07 01:18:41 PM PST 24 30369552 ps
T869 /workspace/coverage/cover_reg_top/12.edn_intr_test.2554692813 Mar 07 01:18:18 PM PST 24 Mar 07 01:18:19 PM PST 24 36964515 ps
T870 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4128880643 Mar 07 01:18:04 PM PST 24 Mar 07 01:18:05 PM PST 24 114625878 ps
T871 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1265673500 Mar 07 01:18:06 PM PST 24 Mar 07 01:18:08 PM PST 24 92571587 ps
T872 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3285173839 Mar 07 01:18:18 PM PST 24 Mar 07 01:18:19 PM PST 24 58068015 ps
T873 /workspace/coverage/cover_reg_top/7.edn_intr_test.3063845778 Mar 07 01:18:05 PM PST 24 Mar 07 01:18:06 PM PST 24 17139729 ps
T874 /workspace/coverage/cover_reg_top/21.edn_intr_test.1814951151 Mar 07 01:18:36 PM PST 24 Mar 07 01:18:37 PM PST 24 17656723 ps
T875 /workspace/coverage/cover_reg_top/12.edn_tl_errors.2275456388 Mar 07 01:18:18 PM PST 24 Mar 07 01:18:22 PM PST 24 109781472 ps
T876 /workspace/coverage/cover_reg_top/13.edn_intr_test.42650633 Mar 07 01:18:19 PM PST 24 Mar 07 01:18:20 PM PST 24 47940905 ps
T877 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.827068783 Mar 07 01:18:32 PM PST 24 Mar 07 01:18:33 PM PST 24 24179631 ps
T878 /workspace/coverage/cover_reg_top/7.edn_csr_rw.1231920361 Mar 07 01:18:02 PM PST 24 Mar 07 01:18:04 PM PST 24 14415216 ps
T879 /workspace/coverage/cover_reg_top/3.edn_tl_errors.1087210344 Mar 07 01:18:04 PM PST 24 Mar 07 01:18:10 PM PST 24 2053180822 ps
T216 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1132289013 Mar 07 01:18:03 PM PST 24 Mar 07 01:18:04 PM PST 24 136185665 ps
T217 /workspace/coverage/cover_reg_top/19.edn_csr_rw.3646399173 Mar 07 01:18:37 PM PST 24 Mar 07 01:18:38 PM PST 24 14859701 ps
T880 /workspace/coverage/cover_reg_top/41.edn_intr_test.2900379822 Mar 07 01:18:35 PM PST 24 Mar 07 01:18:36 PM PST 24 13083599 ps
T881 /workspace/coverage/cover_reg_top/43.edn_intr_test.1915578687 Mar 07 01:18:33 PM PST 24 Mar 07 01:18:34 PM PST 24 41868276 ps
T882 /workspace/coverage/cover_reg_top/5.edn_tl_errors.1414654375 Mar 07 01:18:05 PM PST 24 Mar 07 01:18:07 PM PST 24 62674220 ps
T883 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1893380434 Mar 07 01:18:36 PM PST 24 Mar 07 01:18:39 PM PST 24 175305046 ps
T884 /workspace/coverage/cover_reg_top/29.edn_intr_test.942617216 Mar 07 01:18:33 PM PST 24 Mar 07 01:18:34 PM PST 24 21070182 ps
T885 /workspace/coverage/cover_reg_top/9.edn_tl_errors.2762385845 Mar 07 01:18:07 PM PST 24 Mar 07 01:18:12 PM PST 24 1225578877 ps
T886 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1698552345 Mar 07 01:18:01 PM PST 24 Mar 07 01:18:03 PM PST 24 116063370 ps
T218 /workspace/coverage/cover_reg_top/14.edn_csr_rw.392785276 Mar 07 01:18:19 PM PST 24 Mar 07 01:18:20 PM PST 24 61267198 ps
T887 /workspace/coverage/cover_reg_top/4.edn_intr_test.2862703767 Mar 07 01:18:02 PM PST 24 Mar 07 01:18:03 PM PST 24 13442097 ps
T888 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2444570717 Mar 07 01:17:51 PM PST 24 Mar 07 01:18:01 PM PST 24 641137851 ps
T889 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.795759288 Mar 07 01:18:03 PM PST 24 Mar 07 01:18:06 PM PST 24 123739915 ps
T890 /workspace/coverage/cover_reg_top/49.edn_intr_test.666198777 Mar 07 01:18:30 PM PST 24 Mar 07 01:18:31 PM PST 24 11625869 ps
T891 /workspace/coverage/cover_reg_top/27.edn_intr_test.3340341280 Mar 07 01:18:31 PM PST 24 Mar 07 01:18:31 PM PST 24 28955368 ps
T892 /workspace/coverage/cover_reg_top/0.edn_tl_errors.178104247 Mar 07 01:17:53 PM PST 24 Mar 07 01:17:58 PM PST 24 143452286 ps
T893 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.752915730 Mar 07 01:17:50 PM PST 24 Mar 07 01:17:54 PM PST 24 365719456 ps
T894 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2636482538 Mar 07 01:18:18 PM PST 24 Mar 07 01:18:19 PM PST 24 22912139 ps
T895 /workspace/coverage/cover_reg_top/23.edn_intr_test.898008683 Mar 07 01:18:32 PM PST 24 Mar 07 01:18:33 PM PST 24 83349272 ps
T896 /workspace/coverage/cover_reg_top/15.edn_intr_test.2238886039 Mar 07 01:18:17 PM PST 24 Mar 07 01:18:18 PM PST 24 24189822 ps
T897 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.345845463 Mar 07 01:18:18 PM PST 24 Mar 07 01:18:19 PM PST 24 107140132 ps
T898 /workspace/coverage/cover_reg_top/16.edn_intr_test.3321418945 Mar 07 01:18:31 PM PST 24 Mar 07 01:18:32 PM PST 24 27782817 ps
T899 /workspace/coverage/cover_reg_top/10.edn_csr_rw.3779441443 Mar 07 01:18:18 PM PST 24 Mar 07 01:18:19 PM PST 24 12699374 ps
T900 /workspace/coverage/cover_reg_top/0.edn_intr_test.559886684 Mar 07 01:17:47 PM PST 24 Mar 07 01:17:48 PM PST 24 23688780 ps
T901 /workspace/coverage/cover_reg_top/11.edn_tl_errors.3392952650 Mar 07 01:18:19 PM PST 24 Mar 07 01:18:24 PM PST 24 511115380 ps
T902 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2458076822 Mar 07 01:17:49 PM PST 24 Mar 07 01:17:51 PM PST 24 64812100 ps
T219 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2735471410 Mar 07 01:17:54 PM PST 24 Mar 07 01:17:55 PM PST 24 27530385 ps
T249 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1245042479 Mar 07 01:18:19 PM PST 24 Mar 07 01:18:23 PM PST 24 299544283 ps
T223 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2852904719 Mar 07 01:18:03 PM PST 24 Mar 07 01:18:06 PM PST 24 223999675 ps
T903 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1487405013 Mar 07 01:17:49 PM PST 24 Mar 07 01:17:51 PM PST 24 378166695 ps
T904 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4020937217 Mar 07 01:18:31 PM PST 24 Mar 07 01:18:34 PM PST 24 159442886 ps
T905 /workspace/coverage/cover_reg_top/44.edn_intr_test.3665908401 Mar 07 01:18:30 PM PST 24 Mar 07 01:18:31 PM PST 24 15177086 ps
T906 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3686868013 Mar 07 01:18:09 PM PST 24 Mar 07 01:18:11 PM PST 24 97723025 ps
T907 /workspace/coverage/cover_reg_top/11.edn_intr_test.2391060793 Mar 07 01:18:17 PM PST 24 Mar 07 01:18:18 PM PST 24 31183502 ps
T908 /workspace/coverage/cover_reg_top/14.edn_intr_test.409689716 Mar 07 01:18:18 PM PST 24 Mar 07 01:18:19 PM PST 24 33660130 ps
T909 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3344881594 Mar 07 01:18:19 PM PST 24 Mar 07 01:18:20 PM PST 24 36310802 ps
T910 /workspace/coverage/cover_reg_top/18.edn_tl_errors.2607877226 Mar 07 01:18:31 PM PST 24 Mar 07 01:18:36 PM PST 24 286002180 ps
T911 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.420253501 Mar 07 01:18:09 PM PST 24 Mar 07 01:18:11 PM PST 24 268592200 ps
T912 /workspace/coverage/cover_reg_top/36.edn_intr_test.2103595256 Mar 07 01:18:33 PM PST 24 Mar 07 01:18:34 PM PST 24 41323250 ps
T913 /workspace/coverage/cover_reg_top/25.edn_intr_test.3692709918 Mar 07 01:18:31 PM PST 24 Mar 07 01:18:32 PM PST 24 43990956 ps
T914 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2674132925 Mar 07 01:18:32 PM PST 24 Mar 07 01:18:34 PM PST 24 115039485 ps
T915 /workspace/coverage/cover_reg_top/0.edn_csr_rw.1715266273 Mar 07 01:17:53 PM PST 24 Mar 07 01:17:54 PM PST 24 27006105 ps
T916 /workspace/coverage/cover_reg_top/10.edn_intr_test.3069044767 Mar 07 01:18:21 PM PST 24 Mar 07 01:18:22 PM PST 24 25202959 ps
T917 /workspace/coverage/cover_reg_top/42.edn_intr_test.2988389110 Mar 07 01:18:31 PM PST 24 Mar 07 01:18:32 PM PST 24 39772899 ps
T918 /workspace/coverage/cover_reg_top/33.edn_intr_test.2790403176 Mar 07 01:18:32 PM PST 24 Mar 07 01:18:33 PM PST 24 46923698 ps
T220 /workspace/coverage/cover_reg_top/6.edn_csr_rw.3084670121 Mar 07 01:18:08 PM PST 24 Mar 07 01:18:09 PM PST 24 40998624 ps
T919 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2522893234 Mar 07 01:18:04 PM PST 24 Mar 07 01:18:05 PM PST 24 67599912 ps
T920 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1575141076 Mar 07 01:18:04 PM PST 24 Mar 07 01:18:06 PM PST 24 52962021 ps
T921 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1250598135 Mar 07 01:17:51 PM PST 24 Mar 07 01:17:53 PM PST 24 92418584 ps
T922 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4177302308 Mar 07 01:18:17 PM PST 24 Mar 07 01:18:18 PM PST 24 35895739 ps
T923 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.4096286423 Mar 07 01:18:02 PM PST 24 Mar 07 01:18:03 PM PST 24 59029727 ps
T221 /workspace/coverage/cover_reg_top/2.edn_csr_rw.2276161359 Mar 07 01:18:02 PM PST 24 Mar 07 01:18:03 PM PST 24 14020110 ps
T924 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1791807359 Mar 07 01:18:18 PM PST 24 Mar 07 01:18:21 PM PST 24 291778124 ps
T222 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.4042895408 Mar 07 01:18:03 PM PST 24 Mar 07 01:18:04 PM PST 24 34950643 ps
T925 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1817982641 Mar 07 01:18:34 PM PST 24 Mar 07 01:18:36 PM PST 24 25374894 ps
T926 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2193288478 Mar 07 01:18:05 PM PST 24 Mar 07 01:18:07 PM PST 24 240053328 ps
T927 /workspace/coverage/cover_reg_top/16.edn_tl_errors.484028082 Mar 07 01:18:17 PM PST 24 Mar 07 01:18:20 PM PST 24 179144050 ps
T928 /workspace/coverage/cover_reg_top/6.edn_intr_test.2889800346 Mar 07 01:18:05 PM PST 24 Mar 07 01:18:06 PM PST 24 22892620 ps
T929 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2935973544 Mar 07 01:17:47 PM PST 24 Mar 07 01:17:49 PM PST 24 39728372 ps
T930 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2470106400 Mar 07 01:18:05 PM PST 24 Mar 07 01:18:06 PM PST 24 61440942 ps
T931 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3680798536 Mar 07 01:17:50 PM PST 24 Mar 07 01:17:53 PM PST 24 307299715 ps
T932 /workspace/coverage/cover_reg_top/19.edn_intr_test.2044422612 Mar 07 01:18:34 PM PST 24 Mar 07 01:18:35 PM PST 24 12404393 ps
T933 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3031576162 Mar 07 01:18:18 PM PST 24 Mar 07 01:18:19 PM PST 24 116733377 ps
T934 /workspace/coverage/cover_reg_top/16.edn_csr_rw.561335046 Mar 07 01:18:36 PM PST 24 Mar 07 01:18:37 PM PST 24 25300131 ps
T935 /workspace/coverage/cover_reg_top/31.edn_intr_test.3177622618 Mar 07 01:18:36 PM PST 24 Mar 07 01:18:37 PM PST 24 14267285 ps
T936 /workspace/coverage/cover_reg_top/8.edn_tl_errors.1315570197 Mar 07 01:18:05 PM PST 24 Mar 07 01:18:09 PM PST 24 102205642 ps
T937 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2926889173 Mar 07 01:18:03 PM PST 24 Mar 07 01:18:04 PM PST 24 199347257 ps
T938 /workspace/coverage/cover_reg_top/1.edn_tl_errors.2433976083 Mar 07 01:17:51 PM PST 24 Mar 07 01:17:54 PM PST 24 99535055 ps
T939 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1695157289 Mar 07 01:18:06 PM PST 24 Mar 07 01:18:08 PM PST 24 20483464 ps
T940 /workspace/coverage/cover_reg_top/13.edn_tl_errors.895422424 Mar 07 01:18:17 PM PST 24 Mar 07 01:18:20 PM PST 24 155434944 ps
T941 /workspace/coverage/cover_reg_top/2.edn_intr_test.3411432413 Mar 07 01:17:53 PM PST 24 Mar 07 01:17:54 PM PST 24 36748112 ps
T942 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1632031489 Mar 07 01:17:50 PM PST 24 Mar 07 01:17:52 PM PST 24 214262896 ps
T943 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2561813474 Mar 07 01:18:03 PM PST 24 Mar 07 01:18:05 PM PST 24 142906582 ps
T944 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1356385553 Mar 07 01:18:19 PM PST 24 Mar 07 01:18:21 PM PST 24 291659887 ps
T945 /workspace/coverage/cover_reg_top/10.edn_tl_errors.18034789 Mar 07 01:18:18 PM PST 24 Mar 07 01:18:21 PM PST 24 106642215 ps
T946 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.4141775321 Mar 07 01:18:17 PM PST 24 Mar 07 01:18:19 PM PST 24 22442624 ps
T947 /workspace/coverage/cover_reg_top/32.edn_intr_test.836645355 Mar 07 01:18:33 PM PST 24 Mar 07 01:18:34 PM PST 24 18855497 ps
T225 /workspace/coverage/cover_reg_top/13.edn_csr_rw.842801633 Mar 07 01:18:16 PM PST 24 Mar 07 01:18:18 PM PST 24 20062349 ps
T948 /workspace/coverage/cover_reg_top/1.edn_csr_rw.4072446624 Mar 07 01:17:53 PM PST 24 Mar 07 01:17:54 PM PST 24 104311002 ps
T949 /workspace/coverage/cover_reg_top/40.edn_intr_test.905649569 Mar 07 01:18:33 PM PST 24 Mar 07 01:18:34 PM PST 24 40962678 ps
T250 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4271302188 Mar 07 01:18:19 PM PST 24 Mar 07 01:18:22 PM PST 24 312913651 ps
T950 /workspace/coverage/cover_reg_top/45.edn_intr_test.1287354396 Mar 07 01:18:31 PM PST 24 Mar 07 01:18:32 PM PST 24 25670880 ps
T951 /workspace/coverage/cover_reg_top/22.edn_intr_test.1399380743 Mar 07 01:18:36 PM PST 24 Mar 07 01:18:37 PM PST 24 69408165 ps
T952 /workspace/coverage/cover_reg_top/1.edn_intr_test.2270319961 Mar 07 01:17:53 PM PST 24 Mar 07 01:17:54 PM PST 24 13935715 ps
T953 /workspace/coverage/cover_reg_top/38.edn_intr_test.1287843477 Mar 07 01:18:36 PM PST 24 Mar 07 01:18:37 PM PST 24 11079695 ps
T954 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2325055501 Mar 07 01:18:19 PM PST 24 Mar 07 01:18:21 PM PST 24 114905865 ps
T224 /workspace/coverage/cover_reg_top/12.edn_csr_rw.3051923108 Mar 07 01:18:15 PM PST 24 Mar 07 01:18:16 PM PST 24 32226664 ps
T955 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3322571145 Mar 07 01:18:56 PM PST 24 Mar 07 01:19:00 PM PST 24 69773005 ps
T956 /workspace/coverage/cover_reg_top/5.edn_csr_rw.559623557 Mar 07 01:18:06 PM PST 24 Mar 07 01:18:07 PM PST 24 15548945 ps
T957 /workspace/coverage/cover_reg_top/5.edn_intr_test.4204646641 Mar 07 01:18:03 PM PST 24 Mar 07 01:18:04 PM PST 24 29895744 ps
T958 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3230250647 Mar 07 01:18:05 PM PST 24 Mar 07 01:18:08 PM PST 24 145782542 ps
T959 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3076257978 Mar 07 01:18:33 PM PST 24 Mar 07 01:18:35 PM PST 24 51048944 ps
T960 /workspace/coverage/cover_reg_top/9.edn_intr_test.1833292924 Mar 07 01:18:08 PM PST 24 Mar 07 01:18:09 PM PST 24 78916947 ps
T961 /workspace/coverage/cover_reg_top/15.edn_tl_errors.1358959655 Mar 07 01:18:17 PM PST 24 Mar 07 01:18:19 PM PST 24 49319853 ps
T962 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2972949799 Mar 07 01:18:03 PM PST 24 Mar 07 01:18:04 PM PST 24 181360211 ps
T963 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3203421577 Mar 07 01:18:35 PM PST 24 Mar 07 01:18:37 PM PST 24 60460196 ps
T964 /workspace/coverage/cover_reg_top/7.edn_tl_errors.558363828 Mar 07 01:18:05 PM PST 24 Mar 07 01:18:07 PM PST 24 403915527 ps
T965 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2220030715 Mar 07 01:18:33 PM PST 24 Mar 07 01:18:35 PM PST 24 41363023 ps
T966 /workspace/coverage/cover_reg_top/8.edn_intr_test.3719977169 Mar 07 01:18:09 PM PST 24 Mar 07 01:18:10 PM PST 24 17557755 ps
T967 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3070420464 Mar 07 01:18:09 PM PST 24 Mar 07 01:18:10 PM PST 24 29556551 ps

Test location /workspace/coverage/default/242.edn_genbits.297835463
Short name T21
Test name
Test status
Simulation time 81582876 ps
CPU time 1.23 seconds
Started Mar 07 02:42:36 PM PST 24
Finished Mar 07 02:42:38 PM PST 24
Peak memory 215884 kb
Host smart-c4e82ffe-cca9-4ae1-9c34-dd7a734dc0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297835463 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.297835463
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/90.edn_err.3537496029
Short name T5
Test name
Test status
Simulation time 48646583 ps
CPU time 1.07 seconds
Started Mar 07 02:41:41 PM PST 24
Finished Mar 07 02:41:43 PM PST 24
Peak memory 228896 kb
Host smart-2aec3f6d-a444-4ceb-8b7e-bd23fc78053d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537496029 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.3537496029
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.1547531939
Short name T22
Test name
Test status
Simulation time 70845992808 ps
CPU time 1106.13 seconds
Started Mar 07 02:40:40 PM PST 24
Finished Mar 07 02:59:06 PM PST 24
Peak memory 222908 kb
Host smart-fb2b9985-16f7-41b1-9990-4032d2b7ccd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547531939 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.1547531939
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.edn_genbits.604846178
Short name T27
Test name
Test status
Simulation time 29429622 ps
CPU time 1.47 seconds
Started Mar 07 02:42:07 PM PST 24
Finished Mar 07 02:42:10 PM PST 24
Peak memory 216940 kb
Host smart-a154b95c-276a-4e5d-8282-b1c98dcda32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604846178 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.604846178
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_sec_cm.1075190177
Short name T17
Test name
Test status
Simulation time 3212401858 ps
CPU time 6.97 seconds
Started Mar 07 02:38:52 PM PST 24
Finished Mar 07 02:38:59 PM PST 24
Peak memory 236724 kb
Host smart-8601c675-936e-4868-b822-024f8b5828cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075190177 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.1075190177
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/25.edn_alert.2080921678
Short name T15
Test name
Test status
Simulation time 44238950 ps
CPU time 1.17 seconds
Started Mar 07 02:40:14 PM PST 24
Finished Mar 07 02:40:17 PM PST 24
Peak memory 214748 kb
Host smart-47b11318-1507-404a-aaf9-bc55e11377f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080921678 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.2080921678
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.4078289320
Short name T82
Test name
Test status
Simulation time 20309505 ps
CPU time 0.97 seconds
Started Mar 07 02:40:36 PM PST 24
Finished Mar 07 02:40:37 PM PST 24
Peak memory 216428 kb
Host smart-d83ca7f1-1b74-43eb-9953-fd589ad45468
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078289320 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.4078289320
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/76.edn_genbits.1860588004
Short name T148
Test name
Test status
Simulation time 56972380 ps
CPU time 1.35 seconds
Started Mar 07 02:41:31 PM PST 24
Finished Mar 07 02:41:33 PM PST 24
Peak memory 217708 kb
Host smart-dc096b57-c9f9-4be8-80f9-33035a6e00a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860588004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.1860588004
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert.267538374
Short name T63
Test name
Test status
Simulation time 89304830 ps
CPU time 1.31 seconds
Started Mar 07 02:38:23 PM PST 24
Finished Mar 07 02:38:24 PM PST 24
Peak memory 214804 kb
Host smart-0a600e08-f07a-4877-9072-afbcfd193a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267538374 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.267538374
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.1754493490
Short name T196
Test name
Test status
Simulation time 61875780 ps
CPU time 1.48 seconds
Started Mar 07 01:17:47 PM PST 24
Finished Mar 07 01:17:49 PM PST 24
Peak memory 206412 kb
Host smart-cb51455f-f3da-4c06-9285-a61c536bf666
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754493490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.1754493490
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/default/15.edn_intr.3333084871
Short name T132
Test name
Test status
Simulation time 25724335 ps
CPU time 0.91 seconds
Started Mar 07 02:39:39 PM PST 24
Finished Mar 07 02:39:40 PM PST 24
Peak memory 214776 kb
Host smart-d461d31b-9d9f-4a6d-8e2d-fa61747646f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333084871 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.3333084871
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.621372915
Short name T125
Test name
Test status
Simulation time 23296349 ps
CPU time 0.96 seconds
Started Mar 07 02:39:01 PM PST 24
Finished Mar 07 02:39:02 PM PST 24
Peak memory 206228 kb
Host smart-53d5851e-5373-47be-8d6e-e38b317650b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621372915 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.621372915
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/30.edn_alert.3772170424
Short name T256
Test name
Test status
Simulation time 27656803 ps
CPU time 1.2 seconds
Started Mar 07 02:40:25 PM PST 24
Finished Mar 07 02:40:28 PM PST 24
Peak memory 214812 kb
Host smart-3c5fb7a0-f7e3-4d26-aa1a-26d209b05d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772170424 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.3772170424
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/45.edn_disable.1747403500
Short name T30
Test name
Test status
Simulation time 17301140 ps
CPU time 0.89 seconds
Started Mar 07 02:41:18 PM PST 24
Finished Mar 07 02:41:19 PM PST 24
Peak memory 214996 kb
Host smart-6580ce48-4c2e-4d3d-8ca5-ce18842301f2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747403500 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.1747403500
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.2067727368
Short name T238
Test name
Test status
Simulation time 378875859 ps
CPU time 2.59 seconds
Started Mar 07 01:18:17 PM PST 24
Finished Mar 07 01:18:20 PM PST 24
Peak memory 206388 kb
Host smart-b5eee9b9-d1d2-4007-9406-24cff255cc23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067727368 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.2067727368
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/default/32.edn_alert.3467250907
Short name T143
Test name
Test status
Simulation time 23926977 ps
CPU time 1.25 seconds
Started Mar 07 02:40:34 PM PST 24
Finished Mar 07 02:40:36 PM PST 24
Peak memory 214812 kb
Host smart-4eadcdef-1873-4556-9a86-5f0388aa2cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467250907 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.3467250907
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/13.edn_disable.1744848934
Short name T705
Test name
Test status
Simulation time 10833579 ps
CPU time 0.87 seconds
Started Mar 07 02:39:28 PM PST 24
Finished Mar 07 02:39:30 PM PST 24
Peak memory 214840 kb
Host smart-6b5cda8f-ea6b-444b-a7fb-3b201707fafd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744848934 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.1744848934
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable.906704407
Short name T151
Test name
Test status
Simulation time 15221884 ps
CPU time 0.84 seconds
Started Mar 07 02:39:39 PM PST 24
Finished Mar 07 02:39:41 PM PST 24
Peak memory 214796 kb
Host smart-7a8678de-50ad-4263-9127-3c655eacc4ad
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906704407 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.906704407
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/32.edn_disable_auto_req_mode.1899893230
Short name T87
Test name
Test status
Simulation time 171027291 ps
CPU time 1.09 seconds
Started Mar 07 02:40:35 PM PST 24
Finished Mar 07 02:40:37 PM PST 24
Peak memory 215616 kb
Host smart-b05af9a6-79ed-4ef6-a11f-1850bc3f0a05
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899893230 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_d
isable_auto_req_mode.1899893230
Directory /workspace/32.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_disable.4267018902
Short name T111
Test name
Test status
Simulation time 28472913 ps
CPU time 0.88 seconds
Started Mar 07 02:39:41 PM PST 24
Finished Mar 07 02:39:43 PM PST 24
Peak memory 214892 kb
Host smart-4841baa5-dcea-4f87-80b9-2c27ae801aa4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267018902 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.4267018902
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/20.edn_disable_auto_req_mode.404720510
Short name T155
Test name
Test status
Simulation time 101703272 ps
CPU time 1.28 seconds
Started Mar 07 02:39:49 PM PST 24
Finished Mar 07 02:39:51 PM PST 24
Peak memory 215336 kb
Host smart-065aef72-b5c0-4bc4-887d-864e1a4ce4e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404720510 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_di
sable_auto_req_mode.404720510
Directory /workspace/20.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.972431526
Short name T185
Test name
Test status
Simulation time 79419954782 ps
CPU time 876.07 seconds
Started Mar 07 02:39:08 PM PST 24
Finished Mar 07 02:53:44 PM PST 24
Peak memory 222788 kb
Host smart-a69ba96f-c14c-4189-906a-fe9c28a890fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972431526 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.972431526
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_intr.4211709427
Short name T137
Test name
Test status
Simulation time 27523497 ps
CPU time 0.87 seconds
Started Mar 07 02:40:39 PM PST 24
Finished Mar 07 02:40:40 PM PST 24
Peak memory 214156 kb
Host smart-757e0906-6358-4d82-ba02-a7a8ecc4ed73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211709427 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.4211709427
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/30.edn_disable.1598346140
Short name T179
Test name
Test status
Simulation time 32092879 ps
CPU time 0.83 seconds
Started Mar 07 02:40:24 PM PST 24
Finished Mar 07 02:40:28 PM PST 24
Peak memory 214600 kb
Host smart-41682f34-4a01-474f-b2c7-457f14d8c845
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598346140 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.1598346140
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/179.edn_genbits.3945966501
Short name T268
Test name
Test status
Simulation time 32100318 ps
CPU time 1.32 seconds
Started Mar 07 02:42:16 PM PST 24
Finished Mar 07 02:42:18 PM PST 24
Peak memory 217644 kb
Host smart-5776abf1-af06-4557-a5c7-3bf89d7becfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945966501 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.3945966501
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.2898493759
Short name T244
Test name
Test status
Simulation time 71734833 ps
CPU time 1.44 seconds
Started Mar 07 02:41:57 PM PST 24
Finished Mar 07 02:41:59 PM PST 24
Peak memory 216996 kb
Host smart-c10f179d-1783-411a-8bd6-e5d8f9295395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898493759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.2898493759
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.823016981
Short name T77
Test name
Test status
Simulation time 24324134 ps
CPU time 1.08 seconds
Started Mar 07 02:39:45 PM PST 24
Finished Mar 07 02:39:47 PM PST 24
Peak memory 215364 kb
Host smart-8ae3e6ce-57e9-44f3-aa3c-f30b01a9b327
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823016981 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_di
sable_auto_req_mode.823016981
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_alert.3913624501
Short name T694
Test name
Test status
Simulation time 72127705 ps
CPU time 1.21 seconds
Started Mar 07 02:39:28 PM PST 24
Finished Mar 07 02:39:31 PM PST 24
Peak memory 214812 kb
Host smart-c6dbb124-9508-4f37-b6d3-afca22f8337f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913624501 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.3913624501
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/138.edn_genbits.3459845713
Short name T246
Test name
Test status
Simulation time 45551717 ps
CPU time 1.5 seconds
Started Mar 07 02:42:11 PM PST 24
Finished Mar 07 02:42:13 PM PST 24
Peak memory 215548 kb
Host smart-c017d3ba-431a-488d-92fb-1672b3c3238d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459845713 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.3459845713
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.1980055931
Short name T91
Test name
Test status
Simulation time 35760324 ps
CPU time 1.02 seconds
Started Mar 07 02:39:51 PM PST 24
Finished Mar 07 02:39:52 PM PST 24
Peak memory 215620 kb
Host smart-1583458a-595b-47a4-a330-9f4140659a9a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980055931 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_d
isable_auto_req_mode.1980055931
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_disable.92731737
Short name T152
Test name
Test status
Simulation time 10401687 ps
CPU time 0.89 seconds
Started Mar 07 02:38:52 PM PST 24
Finished Mar 07 02:38:53 PM PST 24
Peak memory 214884 kb
Host smart-e6fd25c6-17bb-4fcf-bde9-e9bbe58b279e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92731737 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.92731737
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable.3814495310
Short name T167
Test name
Test status
Simulation time 101032323 ps
CPU time 0.79 seconds
Started Mar 07 02:41:04 PM PST 24
Finished Mar 07 02:41:04 PM PST 24
Peak memory 214904 kb
Host smart-6c44d7a0-0bfe-4930-979a-745a54c29d01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814495310 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3814495310
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable.2221826050
Short name T540
Test name
Test status
Simulation time 49943934 ps
CPU time 0.87 seconds
Started Mar 07 02:39:31 PM PST 24
Finished Mar 07 02:39:32 PM PST 24
Peak memory 215064 kb
Host smart-61367877-d662-4e5f-830d-cae16ad01d00
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221826050 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.2221826050
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/29.edn_disable.2578072617
Short name T161
Test name
Test status
Simulation time 34584729 ps
CPU time 0.86 seconds
Started Mar 07 02:40:24 PM PST 24
Finished Mar 07 02:40:28 PM PST 24
Peak memory 214924 kb
Host smart-b3985f54-6d02-476b-92a6-5647c99f0a1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578072617 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2578072617
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.248171027
Short name T169
Test name
Test status
Simulation time 45231613 ps
CPU time 1 seconds
Started Mar 07 02:40:34 PM PST 24
Finished Mar 07 02:40:35 PM PST 24
Peak memory 215320 kb
Host smart-903f59e5-80c8-409c-8497-f4bd1fe55d81
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248171027 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.248171027
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.893588391
Short name T71
Test name
Test status
Simulation time 140860380 ps
CPU time 1.08 seconds
Started Mar 07 02:40:42 PM PST 24
Finished Mar 07 02:40:43 PM PST 24
Peak memory 215400 kb
Host smart-a9986a95-ae61-4e12-a877-b0a78e947b27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893588391 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_di
sable_auto_req_mode.893588391
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_regwen.2626721313
Short name T257
Test name
Test status
Simulation time 18226258 ps
CPU time 1.02 seconds
Started Mar 07 02:39:08 PM PST 24
Finished Mar 07 02:39:09 PM PST 24
Peak memory 206208 kb
Host smart-e9753293-0a4f-43c7-971f-a70f7032b234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626721313 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.2626721313
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/265.edn_genbits.1166775794
Short name T182
Test name
Test status
Simulation time 83230161 ps
CPU time 1.59 seconds
Started Mar 07 02:42:36 PM PST 24
Finished Mar 07 02:42:38 PM PST 24
Peak memory 217196 kb
Host smart-9d8c6f02-b120-4238-afa0-35aad872b99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166775794 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.1166775794
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_alert_test.1018849974
Short name T364
Test name
Test status
Simulation time 17794116 ps
CPU time 0.91 seconds
Started Mar 07 02:38:37 PM PST 24
Finished Mar 07 02:38:39 PM PST 24
Peak memory 205696 kb
Host smart-a4102972-695a-4553-8694-485493b169df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018849974 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1018849974
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/151.edn_genbits.2162241040
Short name T346
Test name
Test status
Simulation time 38047658 ps
CPU time 1.1 seconds
Started Mar 07 02:42:05 PM PST 24
Finished Mar 07 02:42:06 PM PST 24
Peak memory 216792 kb
Host smart-36257bf1-c03d-4f73-aa7c-0e8c1e22d7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162241040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.2162241040
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.3479709785
Short name T286
Test name
Test status
Simulation time 128682345 ps
CPU time 2.68 seconds
Started Mar 07 02:42:18 PM PST 24
Finished Mar 07 02:42:20 PM PST 24
Peak memory 218248 kb
Host smart-2e681e63-9670-4eff-99f3-5aa907179518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479709785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.3479709785
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3647595940
Short name T136
Test name
Test status
Simulation time 47148676 ps
CPU time 0.81 seconds
Started Mar 07 02:39:49 PM PST 24
Finished Mar 07 02:39:51 PM PST 24
Peak memory 214656 kb
Host smart-14e7e894-64a3-4b62-b176-c2fcfac4a203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647595940 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3647595940
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.2735471410
Short name T219
Test name
Test status
Simulation time 27530385 ps
CPU time 0.99 seconds
Started Mar 07 01:17:54 PM PST 24
Finished Mar 07 01:17:55 PM PST 24
Peak memory 206396 kb
Host smart-5cd42d77-b3e5-4ccb-aff1-33dd1a4a34e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735471410 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.2735471410
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.3754695400
Short name T229
Test name
Test status
Simulation time 13231222 ps
CPU time 0.87 seconds
Started Mar 07 01:18:17 PM PST 24
Finished Mar 07 01:18:18 PM PST 24
Peak memory 206272 kb
Host smart-1756ade8-b368-40f2-9b1d-76ff7922d214
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754695400 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.3754695400
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.4030467614
Short name T248
Test name
Test status
Simulation time 1158373543 ps
CPU time 9.17 seconds
Started Mar 07 01:18:16 PM PST 24
Finished Mar 07 01:18:25 PM PST 24
Peak memory 206380 kb
Host smart-3b0a9381-8d91-4bae-a19f-9e4fb0300a89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030467614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.4030467614
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_regwen.788537538
Short name T265
Test name
Test status
Simulation time 20836316 ps
CPU time 0.97 seconds
Started Mar 07 02:38:29 PM PST 24
Finished Mar 07 02:38:34 PM PST 24
Peak memory 206204 kb
Host smart-f136d70e-c965-4f23-a414-5cf2691d6496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788537538 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.788537538
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/1.edn_regwen.1765166020
Short name T261
Test name
Test status
Simulation time 16490925 ps
CPU time 1.08 seconds
Started Mar 07 02:38:36 PM PST 24
Finished Mar 07 02:38:38 PM PST 24
Peak memory 206164 kb
Host smart-d2309428-46a7-4c22-8264-4df0f79e3783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765166020 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1765166020
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/10.edn_genbits.2286323897
Short name T814
Test name
Test status
Simulation time 171922924 ps
CPU time 1.26 seconds
Started Mar 07 02:39:18 PM PST 24
Finished Mar 07 02:39:19 PM PST 24
Peak memory 217292 kb
Host smart-1bd9ecaa-ae93-40dc-8db5-9f7fd7df2260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286323897 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.2286323897
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.3150768896
Short name T292
Test name
Test status
Simulation time 105603697 ps
CPU time 1.24 seconds
Started Mar 07 02:41:58 PM PST 24
Finished Mar 07 02:41:59 PM PST 24
Peak memory 215892 kb
Host smart-8339fc73-4a69-43a4-ad66-c220d674e827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150768896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.3150768896
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/110.edn_genbits.140101041
Short name T47
Test name
Test status
Simulation time 45965355 ps
CPU time 1.7 seconds
Started Mar 07 02:41:54 PM PST 24
Finished Mar 07 02:41:57 PM PST 24
Peak memory 216948 kb
Host smart-93b29189-bda4-42ff-bb96-dae213c08485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140101041 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.140101041
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.3397237613
Short name T258
Test name
Test status
Simulation time 26300692 ps
CPU time 1.22 seconds
Started Mar 07 02:39:30 PM PST 24
Finished Mar 07 02:39:31 PM PST 24
Peak memory 214832 kb
Host smart-ba26219c-3e30-40e6-ae83-041a0940003b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397237613 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.3397237613
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.4111136685
Short name T187
Test name
Test status
Simulation time 134751233636 ps
CPU time 1782.68 seconds
Started Mar 07 02:39:30 PM PST 24
Finished Mar 07 03:09:14 PM PST 24
Peak memory 226920 kb
Host smart-fb4c4c0d-2d0c-4c9e-a54e-57b97fc0344e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111136685 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.4111136685
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/133.edn_genbits.3774513838
Short name T717
Test name
Test status
Simulation time 92190688 ps
CPU time 1.17 seconds
Started Mar 07 02:42:08 PM PST 24
Finished Mar 07 02:42:10 PM PST 24
Peak memory 215688 kb
Host smart-958a4e13-c965-49c3-930b-6f17f7989cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774513838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.3774513838
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.4086139776
Short name T283
Test name
Test status
Simulation time 122516466 ps
CPU time 1.46 seconds
Started Mar 07 02:42:18 PM PST 24
Finished Mar 07 02:42:19 PM PST 24
Peak memory 217456 kb
Host smart-745f2822-7a9c-4898-a241-77433029001d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086139776 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.4086139776
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.2797135064
Short name T245
Test name
Test status
Simulation time 73629324 ps
CPU time 1.32 seconds
Started Mar 07 02:42:17 PM PST 24
Finished Mar 07 02:42:19 PM PST 24
Peak memory 215916 kb
Host smart-61f9dbf8-2abf-443c-9c36-6319ba0f2ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797135064 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2797135064
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.992403009
Short name T278
Test name
Test status
Simulation time 358401369 ps
CPU time 2.31 seconds
Started Mar 07 02:42:19 PM PST 24
Finished Mar 07 02:42:22 PM PST 24
Peak memory 216056 kb
Host smart-6668efaa-defc-489a-a5d6-daad1d95f461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992403009 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.992403009
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/200.edn_genbits.1783494833
Short name T289
Test name
Test status
Simulation time 25501814 ps
CPU time 1.32 seconds
Started Mar 07 02:42:21 PM PST 24
Finished Mar 07 02:42:23 PM PST 24
Peak memory 216996 kb
Host smart-341312c6-4d07-4d35-b91d-95415ecce05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783494833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.1783494833
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.3723661921
Short name T274
Test name
Test status
Simulation time 75413712 ps
CPU time 1.23 seconds
Started Mar 07 02:42:23 PM PST 24
Finished Mar 07 02:42:24 PM PST 24
Peak memory 216972 kb
Host smart-bf788116-80cb-4fec-b073-19f077f43302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723661921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.3723661921
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.2587057347
Short name T260
Test name
Test status
Simulation time 51432567 ps
CPU time 1.23 seconds
Started Mar 07 02:38:51 PM PST 24
Finished Mar 07 02:38:52 PM PST 24
Peak memory 214816 kb
Host smart-caa3218a-151c-4126-8d01-473e278ae749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587057347 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.2587057347
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/18.edn_intr.3321643929
Short name T135
Test name
Test status
Simulation time 32586620 ps
CPU time 0.83 seconds
Started Mar 07 02:39:51 PM PST 24
Finished Mar 07 02:39:52 PM PST 24
Peak memory 214616 kb
Host smart-22450d8c-5090-4e71-bd62-dc27842f437a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321643929 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3321643929
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/19.edn_disable.2180127926
Short name T176
Test name
Test status
Simulation time 20859590 ps
CPU time 0.97 seconds
Started Mar 07 02:39:50 PM PST 24
Finished Mar 07 02:39:51 PM PST 24
Peak memory 214652 kb
Host smart-8ed6d944-07ba-4939-9c8e-558770caa4b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180127926 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.2180127926
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/240.edn_genbits.552523888
Short name T617
Test name
Test status
Simulation time 90476700 ps
CPU time 1.65 seconds
Started Mar 07 02:42:30 PM PST 24
Finished Mar 07 02:42:32 PM PST 24
Peak memory 218292 kb
Host smart-1ada354a-fbdb-4204-8d67-df0f6443ca4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552523888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.552523888
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.752915730
Short name T893
Test name
Test status
Simulation time 365719456 ps
CPU time 3.38 seconds
Started Mar 07 01:17:50 PM PST 24
Finished Mar 07 01:17:54 PM PST 24
Peak memory 206344 kb
Host smart-a7fbc89d-9d07-4510-82ae-4ccd62d5cbae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752915730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.752915730
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.2935973544
Short name T929
Test name
Test status
Simulation time 39728372 ps
CPU time 1.23 seconds
Started Mar 07 01:17:47 PM PST 24
Finished Mar 07 01:17:49 PM PST 24
Peak memory 214744 kb
Host smart-15047522-bacf-4de7-940c-011bc7d03c80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935973544 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.2935973544
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.1715266273
Short name T915
Test name
Test status
Simulation time 27006105 ps
CPU time 0.99 seconds
Started Mar 07 01:17:53 PM PST 24
Finished Mar 07 01:17:54 PM PST 24
Peak memory 206396 kb
Host smart-4b6fbbdb-aad5-4879-af12-56fed8929df6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715266273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.1715266273
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.559886684
Short name T900
Test name
Test status
Simulation time 23688780 ps
CPU time 0.82 seconds
Started Mar 07 01:17:47 PM PST 24
Finished Mar 07 01:17:48 PM PST 24
Peak memory 206380 kb
Host smart-9f2de9d1-7f91-423f-975b-c1936f44fb0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559886684 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.559886684
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1632031489
Short name T942
Test name
Test status
Simulation time 214262896 ps
CPU time 1.11 seconds
Started Mar 07 01:17:50 PM PST 24
Finished Mar 07 01:17:52 PM PST 24
Peak memory 206444 kb
Host smart-66b8d3c1-f4a3-4682-8255-5bb8d5f33bcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632031489 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1632031489
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.178104247
Short name T892
Test name
Test status
Simulation time 143452286 ps
CPU time 4.85 seconds
Started Mar 07 01:17:53 PM PST 24
Finished Mar 07 01:17:58 PM PST 24
Peak memory 214760 kb
Host smart-87aba4f8-a5c5-47f7-b3c0-94451587ee1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178104247 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.178104247
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.1250598135
Short name T921
Test name
Test status
Simulation time 92418584 ps
CPU time 1.71 seconds
Started Mar 07 01:17:51 PM PST 24
Finished Mar 07 01:17:53 PM PST 24
Peak memory 206296 kb
Host smart-66c432a9-b034-4b52-849a-2d710796cc3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250598135 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.1250598135
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.378665136
Short name T212
Test name
Test status
Simulation time 97861272 ps
CPU time 1.16 seconds
Started Mar 07 01:17:50 PM PST 24
Finished Mar 07 01:17:52 PM PST 24
Peak memory 206408 kb
Host smart-7263866c-b6e6-4d82-ba47-de04fb5f6160
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378665136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.378665136
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.3680798536
Short name T931
Test name
Test status
Simulation time 307299715 ps
CPU time 3.29 seconds
Started Mar 07 01:17:50 PM PST 24
Finished Mar 07 01:17:53 PM PST 24
Peak memory 206556 kb
Host smart-0fdc8f47-4d8e-4477-9424-014687eff896
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680798536 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.3680798536
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.711971654
Short name T848
Test name
Test status
Simulation time 22466871 ps
CPU time 0.85 seconds
Started Mar 07 01:17:49 PM PST 24
Finished Mar 07 01:17:50 PM PST 24
Peak memory 206392 kb
Host smart-b2aafea0-53e6-490f-984d-6d058e84ce3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711971654 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.711971654
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.2458076822
Short name T902
Test name
Test status
Simulation time 64812100 ps
CPU time 1.22 seconds
Started Mar 07 01:17:49 PM PST 24
Finished Mar 07 01:17:51 PM PST 24
Peak memory 214680 kb
Host smart-45d47b0c-30ce-438f-a04a-75b60c7e65cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458076822 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.2458076822
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.4072446624
Short name T948
Test name
Test status
Simulation time 104311002 ps
CPU time 0.84 seconds
Started Mar 07 01:17:53 PM PST 24
Finished Mar 07 01:17:54 PM PST 24
Peak memory 206236 kb
Host smart-3944557a-83d1-4412-b715-25a8a2eac17c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072446624 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.4072446624
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.2270319961
Short name T952
Test name
Test status
Simulation time 13935715 ps
CPU time 0.9 seconds
Started Mar 07 01:17:53 PM PST 24
Finished Mar 07 01:17:54 PM PST 24
Peak memory 206404 kb
Host smart-48d280d4-513a-4492-8318-efd9a150216f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270319961 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.2270319961
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.1487405013
Short name T903
Test name
Test status
Simulation time 378166695 ps
CPU time 1.27 seconds
Started Mar 07 01:17:49 PM PST 24
Finished Mar 07 01:17:51 PM PST 24
Peak memory 206368 kb
Host smart-f59090ea-c988-46eb-a89b-5defd206cb9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487405013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.1487405013
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.2433976083
Short name T938
Test name
Test status
Simulation time 99535055 ps
CPU time 2.72 seconds
Started Mar 07 01:17:51 PM PST 24
Finished Mar 07 01:17:54 PM PST 24
Peak memory 214692 kb
Host smart-c8e68768-b9b1-4989-94a1-f68938cc0749
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433976083 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.2433976083
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.1007156139
Short name T862
Test name
Test status
Simulation time 183693363 ps
CPU time 2.56 seconds
Started Mar 07 01:17:54 PM PST 24
Finished Mar 07 01:17:57 PM PST 24
Peak memory 206396 kb
Host smart-0da08fbd-fb8d-4801-b4a9-33bf7c841f70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007156139 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.1007156139
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.345845463
Short name T897
Test name
Test status
Simulation time 107140132 ps
CPU time 1.29 seconds
Started Mar 07 01:18:18 PM PST 24
Finished Mar 07 01:18:19 PM PST 24
Peak memory 214632 kb
Host smart-d9d10cbd-82f4-4899-9e74-234a5b3d5884
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345845463 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.345845463
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.3779441443
Short name T899
Test name
Test status
Simulation time 12699374 ps
CPU time 0.86 seconds
Started Mar 07 01:18:18 PM PST 24
Finished Mar 07 01:18:19 PM PST 24
Peak memory 206296 kb
Host smart-3c058892-6a48-41f9-a794-cf8533b64764
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779441443 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.3779441443
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3069044767
Short name T916
Test name
Test status
Simulation time 25202959 ps
CPU time 0.89 seconds
Started Mar 07 01:18:21 PM PST 24
Finished Mar 07 01:18:22 PM PST 24
Peak memory 206420 kb
Host smart-be95e5b8-adec-4773-88e6-4249296c65e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069044767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3069044767
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.3031576162
Short name T933
Test name
Test status
Simulation time 116733377 ps
CPU time 1.48 seconds
Started Mar 07 01:18:18 PM PST 24
Finished Mar 07 01:18:19 PM PST 24
Peak memory 206484 kb
Host smart-788e17b1-9334-423e-8b85-495957b35ac7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031576162 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.3031576162
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.18034789
Short name T945
Test name
Test status
Simulation time 106642215 ps
CPU time 2.99 seconds
Started Mar 07 01:18:18 PM PST 24
Finished Mar 07 01:18:21 PM PST 24
Peak memory 214660 kb
Host smart-a4ba148f-0642-4043-817f-ed61c728211b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18034789 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.18034789
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.1791807359
Short name T924
Test name
Test status
Simulation time 291778124 ps
CPU time 2.5 seconds
Started Mar 07 01:18:18 PM PST 24
Finished Mar 07 01:18:21 PM PST 24
Peak memory 206480 kb
Host smart-96455312-e616-4a95-824e-51cd24c48984
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791807359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.1791807359
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3344881594
Short name T909
Test name
Test status
Simulation time 36310802 ps
CPU time 1.31 seconds
Started Mar 07 01:18:19 PM PST 24
Finished Mar 07 01:18:20 PM PST 24
Peak memory 214644 kb
Host smart-466337f2-7b25-4b9d-ada8-a860c8e53d12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344881594 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3344881594
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2391060793
Short name T907
Test name
Test status
Simulation time 31183502 ps
CPU time 0.86 seconds
Started Mar 07 01:18:17 PM PST 24
Finished Mar 07 01:18:18 PM PST 24
Peak memory 206352 kb
Host smart-16adfb03-3346-4d97-9fc5-f3820fa99c96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391060793 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2391060793
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.804388427
Short name T231
Test name
Test status
Simulation time 25549671 ps
CPU time 0.93 seconds
Started Mar 07 01:18:16 PM PST 24
Finished Mar 07 01:18:18 PM PST 24
Peak memory 206344 kb
Host smart-2565ac4e-4b43-4c23-bf09-87e1a9176fce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804388427 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou
tstanding.804388427
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.3392952650
Short name T901
Test name
Test status
Simulation time 511115380 ps
CPU time 5.13 seconds
Started Mar 07 01:18:19 PM PST 24
Finished Mar 07 01:18:24 PM PST 24
Peak memory 214652 kb
Host smart-54940e4f-4ae8-4a0e-bbfa-4869c52969d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392952650 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.3392952650
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.1356385553
Short name T944
Test name
Test status
Simulation time 291659887 ps
CPU time 1.41 seconds
Started Mar 07 01:18:19 PM PST 24
Finished Mar 07 01:18:21 PM PST 24
Peak memory 214636 kb
Host smart-aacf4c7f-d934-42ee-8a8b-b6ea4393e21d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356385553 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.1356385553
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3051923108
Short name T224
Test name
Test status
Simulation time 32226664 ps
CPU time 0.81 seconds
Started Mar 07 01:18:15 PM PST 24
Finished Mar 07 01:18:16 PM PST 24
Peak memory 206208 kb
Host smart-efbd0322-52e8-4311-a006-8fdee2018ada
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051923108 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3051923108
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.2554692813
Short name T869
Test name
Test status
Simulation time 36964515 ps
CPU time 0.81 seconds
Started Mar 07 01:18:18 PM PST 24
Finished Mar 07 01:18:19 PM PST 24
Peak memory 206300 kb
Host smart-85ef9cfe-57ac-4cb1-9685-b95838390e41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554692813 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.2554692813
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.862824207
Short name T213
Test name
Test status
Simulation time 34481001 ps
CPU time 1.03 seconds
Started Mar 07 01:18:17 PM PST 24
Finished Mar 07 01:18:18 PM PST 24
Peak memory 206328 kb
Host smart-b93accc2-7f12-4680-8824-fc50957e9280
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862824207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_ou
tstanding.862824207
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.2275456388
Short name T875
Test name
Test status
Simulation time 109781472 ps
CPU time 4.32 seconds
Started Mar 07 01:18:18 PM PST 24
Finished Mar 07 01:18:22 PM PST 24
Peak memory 214700 kb
Host smart-9f99226f-aa3c-439c-a10a-06584126021c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275456388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.2275456388
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.4141775321
Short name T946
Test name
Test status
Simulation time 22442624 ps
CPU time 1.41 seconds
Started Mar 07 01:18:17 PM PST 24
Finished Mar 07 01:18:19 PM PST 24
Peak memory 214712 kb
Host smart-b023d9dc-cbbb-46e7-aac8-d96499186d7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141775321 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.4141775321
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.842801633
Short name T225
Test name
Test status
Simulation time 20062349 ps
CPU time 0.88 seconds
Started Mar 07 01:18:16 PM PST 24
Finished Mar 07 01:18:18 PM PST 24
Peak memory 206336 kb
Host smart-63e295e2-e29e-4996-b2e1-8baff90ce89a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842801633 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.842801633
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.42650633
Short name T876
Test name
Test status
Simulation time 47940905 ps
CPU time 0.79 seconds
Started Mar 07 01:18:19 PM PST 24
Finished Mar 07 01:18:20 PM PST 24
Peak memory 206260 kb
Host smart-cfb0608a-9018-4643-ab4a-e22b0a9c7f3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42650633 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.42650633
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.2879574165
Short name T232
Test name
Test status
Simulation time 404845715 ps
CPU time 1.12 seconds
Started Mar 07 01:18:18 PM PST 24
Finished Mar 07 01:18:20 PM PST 24
Peak memory 206484 kb
Host smart-f1fd6661-873b-4ccd-88df-e09b9cbcea6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879574165 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.2879574165
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.895422424
Short name T940
Test name
Test status
Simulation time 155434944 ps
CPU time 2.73 seconds
Started Mar 07 01:18:17 PM PST 24
Finished Mar 07 01:18:20 PM PST 24
Peak memory 217864 kb
Host smart-f86b39a9-12be-446c-9213-11237af94df7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895422424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.895422424
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1774564332
Short name T858
Test name
Test status
Simulation time 247051320 ps
CPU time 1.58 seconds
Started Mar 07 01:18:17 PM PST 24
Finished Mar 07 01:18:19 PM PST 24
Peak memory 206392 kb
Host smart-5a35ef87-3263-4c26-ba04-5ebf0485b337
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774564332 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1774564332
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3285173839
Short name T872
Test name
Test status
Simulation time 58068015 ps
CPU time 1.07 seconds
Started Mar 07 01:18:18 PM PST 24
Finished Mar 07 01:18:19 PM PST 24
Peak memory 216700 kb
Host smart-dbea1107-c7fc-48d4-b454-01de77bd3e58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285173839 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3285173839
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.392785276
Short name T218
Test name
Test status
Simulation time 61267198 ps
CPU time 0.82 seconds
Started Mar 07 01:18:19 PM PST 24
Finished Mar 07 01:18:20 PM PST 24
Peak memory 206260 kb
Host smart-0cad17f0-c660-4c37-b718-e2f5fe507ae4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392785276 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.392785276
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.409689716
Short name T908
Test name
Test status
Simulation time 33660130 ps
CPU time 0.82 seconds
Started Mar 07 01:18:18 PM PST 24
Finished Mar 07 01:18:19 PM PST 24
Peak memory 206132 kb
Host smart-868bf5bc-336e-4340-becb-540259d57c0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409689716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.409689716
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.119751740
Short name T210
Test name
Test status
Simulation time 195119261 ps
CPU time 1.54 seconds
Started Mar 07 01:18:16 PM PST 24
Finished Mar 07 01:18:18 PM PST 24
Peak memory 206340 kb
Host smart-8997c73f-d56a-4091-a2ec-df1d047f3ae5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119751740 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_ou
tstanding.119751740
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.3201764663
Short name T849
Test name
Test status
Simulation time 464659808 ps
CPU time 4.15 seconds
Started Mar 07 01:18:18 PM PST 24
Finished Mar 07 01:18:22 PM PST 24
Peak memory 214672 kb
Host smart-9d314077-7a82-4237-a141-0f2c4dc994f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201764663 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.3201764663
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1245042479
Short name T249
Test name
Test status
Simulation time 299544283 ps
CPU time 3.93 seconds
Started Mar 07 01:18:19 PM PST 24
Finished Mar 07 01:18:23 PM PST 24
Peak memory 206480 kb
Host smart-4a2ae093-e4ad-4a9b-907e-fe2915072829
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245042479 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1245042479
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.602265003
Short name T198
Test name
Test status
Simulation time 18481854 ps
CPU time 1.09 seconds
Started Mar 07 01:18:16 PM PST 24
Finished Mar 07 01:18:18 PM PST 24
Peak memory 214668 kb
Host smart-ca11b4d0-df99-4549-ad5d-74c88b4cbd80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602265003 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.602265003
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.181952406
Short name T237
Test name
Test status
Simulation time 22921378 ps
CPU time 0.88 seconds
Started Mar 07 01:18:18 PM PST 24
Finished Mar 07 01:18:19 PM PST 24
Peak memory 206476 kb
Host smart-f6010746-0049-4342-8215-39017fe89715
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181952406 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.181952406
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.2238886039
Short name T896
Test name
Test status
Simulation time 24189822 ps
CPU time 0.89 seconds
Started Mar 07 01:18:17 PM PST 24
Finished Mar 07 01:18:18 PM PST 24
Peak memory 206372 kb
Host smart-66d60653-ab67-49ca-98f8-be7aba822218
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238886039 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.2238886039
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.2636482538
Short name T894
Test name
Test status
Simulation time 22912139 ps
CPU time 0.9 seconds
Started Mar 07 01:18:18 PM PST 24
Finished Mar 07 01:18:19 PM PST 24
Peak memory 206388 kb
Host smart-8f04e871-91af-4190-968d-411762a10d8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636482538 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_o
utstanding.2636482538
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.1358959655
Short name T961
Test name
Test status
Simulation time 49319853 ps
CPU time 1.88 seconds
Started Mar 07 01:18:17 PM PST 24
Finished Mar 07 01:18:19 PM PST 24
Peak memory 214724 kb
Host smart-2a851b75-5319-446d-87b1-5121b650e12d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358959655 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.1358959655
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.2325055501
Short name T954
Test name
Test status
Simulation time 114905865 ps
CPU time 2.65 seconds
Started Mar 07 01:18:19 PM PST 24
Finished Mar 07 01:18:21 PM PST 24
Peak memory 206500 kb
Host smart-8e4df20b-a84e-4c85-970c-88de03a86a03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325055501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.2325055501
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.1817982641
Short name T925
Test name
Test status
Simulation time 25374894 ps
CPU time 1.64 seconds
Started Mar 07 01:18:34 PM PST 24
Finished Mar 07 01:18:36 PM PST 24
Peak memory 214744 kb
Host smart-0956b406-dbe0-4767-92b2-3041e253e6e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817982641 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.1817982641
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.561335046
Short name T934
Test name
Test status
Simulation time 25300131 ps
CPU time 0.89 seconds
Started Mar 07 01:18:36 PM PST 24
Finished Mar 07 01:18:37 PM PST 24
Peak memory 206420 kb
Host smart-82f45088-e7fa-43f8-94f3-c06f396ab8fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561335046 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.561335046
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3321418945
Short name T898
Test name
Test status
Simulation time 27782817 ps
CPU time 0.79 seconds
Started Mar 07 01:18:31 PM PST 24
Finished Mar 07 01:18:32 PM PST 24
Peak memory 206240 kb
Host smart-f432329d-6073-4145-8287-36502546eb85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321418945 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3321418945
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2674132925
Short name T914
Test name
Test status
Simulation time 115039485 ps
CPU time 1.26 seconds
Started Mar 07 01:18:32 PM PST 24
Finished Mar 07 01:18:34 PM PST 24
Peak memory 206388 kb
Host smart-b63b0abc-ba45-4308-8608-35f86c3868b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674132925 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2674132925
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.484028082
Short name T927
Test name
Test status
Simulation time 179144050 ps
CPU time 2 seconds
Started Mar 07 01:18:17 PM PST 24
Finished Mar 07 01:18:20 PM PST 24
Peak memory 214584 kb
Host smart-e4577787-becc-4f3a-947c-b3bb4f05b9ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484028082 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.484028082
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.4271302188
Short name T250
Test name
Test status
Simulation time 312913651 ps
CPU time 2.46 seconds
Started Mar 07 01:18:19 PM PST 24
Finished Mar 07 01:18:22 PM PST 24
Peak memory 206488 kb
Host smart-3d35b52d-cb47-43db-af0d-63115bc69ffb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271302188 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.4271302188
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.3203421577
Short name T963
Test name
Test status
Simulation time 60460196 ps
CPU time 1.18 seconds
Started Mar 07 01:18:35 PM PST 24
Finished Mar 07 01:18:37 PM PST 24
Peak memory 217040 kb
Host smart-6852ebe8-b5d2-4e92-ac05-bd066f0a71c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203421577 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.3203421577
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.3683959230
Short name T228
Test name
Test status
Simulation time 41640504 ps
CPU time 0.91 seconds
Started Mar 07 01:18:39 PM PST 24
Finished Mar 07 01:18:40 PM PST 24
Peak memory 206400 kb
Host smart-07f745ca-2e91-4d8e-824d-6bbae7919a23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683959230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.3683959230
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.2681292207
Short name T850
Test name
Test status
Simulation time 26205312 ps
CPU time 0.89 seconds
Started Mar 07 01:18:32 PM PST 24
Finished Mar 07 01:18:33 PM PST 24
Peak memory 206368 kb
Host smart-109e1cfe-13cb-47ed-b534-4fa32ffe01d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681292207 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.2681292207
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.1894915523
Short name T227
Test name
Test status
Simulation time 60751308 ps
CPU time 1.06 seconds
Started Mar 07 01:18:36 PM PST 24
Finished Mar 07 01:18:37 PM PST 24
Peak memory 206480 kb
Host smart-c8739dfb-9d78-491b-92a4-b6ef40942f11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894915523 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.1894915523
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3322571145
Short name T955
Test name
Test status
Simulation time 69773005 ps
CPU time 2.47 seconds
Started Mar 07 01:18:56 PM PST 24
Finished Mar 07 01:19:00 PM PST 24
Peak memory 214676 kb
Host smart-47a434f6-8273-45c8-a2aa-366ad3772cba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322571145 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3322571145
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.486328656
Short name T240
Test name
Test status
Simulation time 86176557 ps
CPU time 2.54 seconds
Started Mar 07 01:18:38 PM PST 24
Finished Mar 07 01:18:41 PM PST 24
Peak memory 206404 kb
Host smart-b7bfa730-a00b-4370-8a24-e98f3ef29359
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486328656 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.486328656
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.3076257978
Short name T959
Test name
Test status
Simulation time 51048944 ps
CPU time 1.34 seconds
Started Mar 07 01:18:33 PM PST 24
Finished Mar 07 01:18:35 PM PST 24
Peak memory 214636 kb
Host smart-a52d1bf4-51bd-4070-8827-c87475541571
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076257978 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.3076257978
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.3460933542
Short name T236
Test name
Test status
Simulation time 60412234 ps
CPU time 0.89 seconds
Started Mar 07 01:18:29 PM PST 24
Finished Mar 07 01:18:30 PM PST 24
Peak memory 206336 kb
Host smart-9ed733b9-2d96-43b8-bdbf-ceb6c9541a65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460933542 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.3460933542
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.228782203
Short name T853
Test name
Test status
Simulation time 73352998 ps
CPU time 0.78 seconds
Started Mar 07 01:18:30 PM PST 24
Finished Mar 07 01:18:31 PM PST 24
Peak memory 206256 kb
Host smart-b941fb44-4a9f-4147-8a53-4a27728db51c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228782203 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.228782203
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.3031668629
Short name T866
Test name
Test status
Simulation time 47214642 ps
CPU time 1.22 seconds
Started Mar 07 01:18:34 PM PST 24
Finished Mar 07 01:18:35 PM PST 24
Peak memory 206408 kb
Host smart-71b11546-b014-4f4a-b97e-e7668e931386
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031668629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.3031668629
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.2607877226
Short name T910
Test name
Test status
Simulation time 286002180 ps
CPU time 4.56 seconds
Started Mar 07 01:18:31 PM PST 24
Finished Mar 07 01:18:36 PM PST 24
Peak memory 214744 kb
Host smart-37ffac6a-c67a-4fb4-b965-589ca26ee5f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607877226 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.2607877226
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.4020937217
Short name T904
Test name
Test status
Simulation time 159442886 ps
CPU time 2.45 seconds
Started Mar 07 01:18:31 PM PST 24
Finished Mar 07 01:18:34 PM PST 24
Peak memory 206404 kb
Host smart-80ab9ab7-190f-4339-bbf1-733295a0c151
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020937217 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.4020937217
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.3768652485
Short name T842
Test name
Test status
Simulation time 289032538 ps
CPU time 1.44 seconds
Started Mar 07 01:18:33 PM PST 24
Finished Mar 07 01:18:36 PM PST 24
Peak memory 214708 kb
Host smart-483a4aca-2175-4de2-9fbb-3a18f9c41cdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768652485 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.3768652485
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.3646399173
Short name T217
Test name
Test status
Simulation time 14859701 ps
CPU time 0.91 seconds
Started Mar 07 01:18:37 PM PST 24
Finished Mar 07 01:18:38 PM PST 24
Peak memory 206428 kb
Host smart-dcd3e600-e4bc-4cd7-9249-791b9813877b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646399173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.3646399173
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.2044422612
Short name T932
Test name
Test status
Simulation time 12404393 ps
CPU time 0.81 seconds
Started Mar 07 01:18:34 PM PST 24
Finished Mar 07 01:18:35 PM PST 24
Peak memory 206368 kb
Host smart-7e7a086a-868f-43ff-86b4-d4a95e91f1fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044422612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.2044422612
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.827068783
Short name T877
Test name
Test status
Simulation time 24179631 ps
CPU time 0.91 seconds
Started Mar 07 01:18:32 PM PST 24
Finished Mar 07 01:18:33 PM PST 24
Peak memory 206356 kb
Host smart-c3492cdb-84c3-40b6-b04f-3780b2e1179f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827068783 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.827068783
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1893380434
Short name T883
Test name
Test status
Simulation time 175305046 ps
CPU time 2.77 seconds
Started Mar 07 01:18:36 PM PST 24
Finished Mar 07 01:18:39 PM PST 24
Peak memory 214696 kb
Host smart-c95df4fd-ffd2-48f9-aaaf-8156cebbfbb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893380434 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1893380434
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.2220030715
Short name T965
Test name
Test status
Simulation time 41363023 ps
CPU time 1.53 seconds
Started Mar 07 01:18:33 PM PST 24
Finished Mar 07 01:18:35 PM PST 24
Peak memory 206408 kb
Host smart-15a62336-b6f6-4da5-83be-acbf66c7a7bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220030715 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.2220030715
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.135833864
Short name T197
Test name
Test status
Simulation time 55307438 ps
CPU time 1.2 seconds
Started Mar 07 01:18:05 PM PST 24
Finished Mar 07 01:18:06 PM PST 24
Peak memory 206432 kb
Host smart-4cf77667-a6c6-4c2a-bbfe-db690847a65a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135833864 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.135833864
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.2852904719
Short name T223
Test name
Test status
Simulation time 223999675 ps
CPU time 3.48 seconds
Started Mar 07 01:18:03 PM PST 24
Finished Mar 07 01:18:06 PM PST 24
Peak memory 206380 kb
Host smart-6bb8db3f-91cd-493b-a8c9-6f40547e3354
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852904719 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.2852904719
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.2044202632
Short name T214
Test name
Test status
Simulation time 25658616 ps
CPU time 0.88 seconds
Started Mar 07 01:18:04 PM PST 24
Finished Mar 07 01:18:05 PM PST 24
Peak memory 206396 kb
Host smart-fd29f0a2-23e0-4982-95be-478bb543feb2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044202632 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.2044202632
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2522893234
Short name T919
Test name
Test status
Simulation time 67599912 ps
CPU time 1.06 seconds
Started Mar 07 01:18:04 PM PST 24
Finished Mar 07 01:18:05 PM PST 24
Peak memory 214636 kb
Host smart-324d95c7-dafa-4502-a938-680bae46fbc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522893234 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2522893234
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.2276161359
Short name T221
Test name
Test status
Simulation time 14020110 ps
CPU time 0.93 seconds
Started Mar 07 01:18:02 PM PST 24
Finished Mar 07 01:18:03 PM PST 24
Peak memory 206396 kb
Host smart-3113e6d3-b160-4b46-a78f-efe42f42a347
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276161359 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.2276161359
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3411432413
Short name T941
Test name
Test status
Simulation time 36748112 ps
CPU time 0.85 seconds
Started Mar 07 01:17:53 PM PST 24
Finished Mar 07 01:17:54 PM PST 24
Peak memory 206240 kb
Host smart-6d084bc8-f9d4-4182-a12a-dc15e912809b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411432413 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3411432413
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1698552345
Short name T886
Test name
Test status
Simulation time 116063370 ps
CPU time 1.3 seconds
Started Mar 07 01:18:01 PM PST 24
Finished Mar 07 01:18:03 PM PST 24
Peak memory 206436 kb
Host smart-42b86c02-b3a4-433f-b3de-0c021b9897d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698552345 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1698552345
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.1597971781
Short name T854
Test name
Test status
Simulation time 63630989 ps
CPU time 2.42 seconds
Started Mar 07 01:17:54 PM PST 24
Finished Mar 07 01:17:56 PM PST 24
Peak memory 214652 kb
Host smart-0a5b5870-e195-4df7-b8c3-905524037f4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597971781 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.1597971781
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.2444570717
Short name T888
Test name
Test status
Simulation time 641137851 ps
CPU time 9.55 seconds
Started Mar 07 01:17:51 PM PST 24
Finished Mar 07 01:18:01 PM PST 24
Peak memory 206364 kb
Host smart-f14a0d94-6779-475d-9c73-39110c367d43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444570717 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.2444570717
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.1460034066
Short name T860
Test name
Test status
Simulation time 40697176 ps
CPU time 0.8 seconds
Started Mar 07 01:18:32 PM PST 24
Finished Mar 07 01:18:32 PM PST 24
Peak memory 206236 kb
Host smart-2e1f65da-313f-4c1e-85b2-1a2a686bbcc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460034066 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.1460034066
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.1814951151
Short name T874
Test name
Test status
Simulation time 17656723 ps
CPU time 0.79 seconds
Started Mar 07 01:18:36 PM PST 24
Finished Mar 07 01:18:37 PM PST 24
Peak memory 206216 kb
Host smart-f73538f5-10f2-479b-9dab-8fac735cc134
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814951151 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.1814951151
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.1399380743
Short name T951
Test name
Test status
Simulation time 69408165 ps
CPU time 0.84 seconds
Started Mar 07 01:18:36 PM PST 24
Finished Mar 07 01:18:37 PM PST 24
Peak memory 206228 kb
Host smart-f8f2ffe1-cb25-46d2-82b9-7feae9ae565b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399380743 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.1399380743
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.898008683
Short name T895
Test name
Test status
Simulation time 83349272 ps
CPU time 0.88 seconds
Started Mar 07 01:18:32 PM PST 24
Finished Mar 07 01:18:33 PM PST 24
Peak memory 206304 kb
Host smart-05259148-84e3-4e4a-b188-f9a8644f6088
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898008683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.898008683
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1801690889
Short name T843
Test name
Test status
Simulation time 15583672 ps
CPU time 0.96 seconds
Started Mar 07 01:18:35 PM PST 24
Finished Mar 07 01:18:37 PM PST 24
Peak memory 206372 kb
Host smart-a2b2c937-a94e-460b-ac6f-52d4df08e36e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801690889 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1801690889
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.3692709918
Short name T913
Test name
Test status
Simulation time 43990956 ps
CPU time 0.82 seconds
Started Mar 07 01:18:31 PM PST 24
Finished Mar 07 01:18:32 PM PST 24
Peak memory 206236 kb
Host smart-16e2e059-9f7b-4d23-ad3f-e2982657d3de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692709918 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.3692709918
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.694717053
Short name T845
Test name
Test status
Simulation time 32245964 ps
CPU time 0.76 seconds
Started Mar 07 01:18:35 PM PST 24
Finished Mar 07 01:18:36 PM PST 24
Peak memory 206160 kb
Host smart-04ced49e-85c0-405a-9ed0-66a992b668fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694717053 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.694717053
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.3340341280
Short name T891
Test name
Test status
Simulation time 28955368 ps
CPU time 0.75 seconds
Started Mar 07 01:18:31 PM PST 24
Finished Mar 07 01:18:31 PM PST 24
Peak memory 206320 kb
Host smart-c63726f9-580b-4ee1-838b-59d33a16d4f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340341280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.3340341280
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.835732398
Short name T868
Test name
Test status
Simulation time 30369552 ps
CPU time 0.85 seconds
Started Mar 07 01:18:39 PM PST 24
Finished Mar 07 01:18:41 PM PST 24
Peak memory 206196 kb
Host smart-d3fb2a75-e03d-4480-a276-4ba9b9577b32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835732398 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.835732398
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.942617216
Short name T884
Test name
Test status
Simulation time 21070182 ps
CPU time 0.93 seconds
Started Mar 07 01:18:33 PM PST 24
Finished Mar 07 01:18:34 PM PST 24
Peak memory 206376 kb
Host smart-852c7968-f4b5-401e-ac48-3e4df44675fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942617216 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.942617216
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.4042895408
Short name T222
Test name
Test status
Simulation time 34950643 ps
CPU time 1.55 seconds
Started Mar 07 01:18:03 PM PST 24
Finished Mar 07 01:18:04 PM PST 24
Peak memory 206432 kb
Host smart-b67ac872-1bd5-4720-98c6-f63e952b2167
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042895408 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.4042895408
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.1771467616
Short name T865
Test name
Test status
Simulation time 92569219 ps
CPU time 2.95 seconds
Started Mar 07 01:18:04 PM PST 24
Finished Mar 07 01:18:07 PM PST 24
Peak memory 206388 kb
Host smart-06ab6776-c39f-4707-b43b-860614d4f1c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771467616 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.1771467616
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.355820716
Short name T855
Test name
Test status
Simulation time 49872058 ps
CPU time 0.84 seconds
Started Mar 07 01:18:04 PM PST 24
Finished Mar 07 01:18:05 PM PST 24
Peak memory 206296 kb
Host smart-050a4bee-05f7-404d-9849-79d4a2a9dbe4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355820716 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.355820716
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.2972949799
Short name T962
Test name
Test status
Simulation time 181360211 ps
CPU time 1.32 seconds
Started Mar 07 01:18:03 PM PST 24
Finished Mar 07 01:18:04 PM PST 24
Peak memory 216536 kb
Host smart-bc1c60a0-e5f9-42c5-b491-922dd89ce467
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972949799 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.2972949799
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1132289013
Short name T216
Test name
Test status
Simulation time 136185665 ps
CPU time 0.93 seconds
Started Mar 07 01:18:03 PM PST 24
Finished Mar 07 01:18:04 PM PST 24
Peak memory 206472 kb
Host smart-3a934b6b-d787-4b92-aefb-7102dbe7c59f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132289013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1132289013
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.3810921282
Short name T863
Test name
Test status
Simulation time 13787819 ps
CPU time 0.88 seconds
Started Mar 07 01:18:03 PM PST 24
Finished Mar 07 01:18:04 PM PST 24
Peak memory 206368 kb
Host smart-2ef8e042-7558-4b3b-bc84-e6ea1cb22f3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810921282 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.3810921282
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.433934373
Short name T226
Test name
Test status
Simulation time 77165374 ps
CPU time 1.06 seconds
Started Mar 07 01:18:04 PM PST 24
Finished Mar 07 01:18:05 PM PST 24
Peak memory 206456 kb
Host smart-7ca049fe-6a02-4da7-a197-c831dbf6447d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433934373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_out
standing.433934373
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.1087210344
Short name T879
Test name
Test status
Simulation time 2053180822 ps
CPU time 5.49 seconds
Started Mar 07 01:18:04 PM PST 24
Finished Mar 07 01:18:10 PM PST 24
Peak memory 214552 kb
Host smart-4b5c88ac-6370-425d-9ffc-3c82c4991107
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087210344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.1087210344
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.795759288
Short name T889
Test name
Test status
Simulation time 123739915 ps
CPU time 2.48 seconds
Started Mar 07 01:18:03 PM PST 24
Finished Mar 07 01:18:06 PM PST 24
Peak memory 206388 kb
Host smart-1ee91041-2411-49f4-98a0-4f3ea8fc8ee8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795759288 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.795759288
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.2778887750
Short name T859
Test name
Test status
Simulation time 41156864 ps
CPU time 0.81 seconds
Started Mar 07 01:18:36 PM PST 24
Finished Mar 07 01:18:37 PM PST 24
Peak memory 206172 kb
Host smart-80946f5a-f30f-44c8-baa7-3dc0b96276b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778887750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.2778887750
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3177622618
Short name T935
Test name
Test status
Simulation time 14267285 ps
CPU time 0.91 seconds
Started Mar 07 01:18:36 PM PST 24
Finished Mar 07 01:18:37 PM PST 24
Peak memory 206456 kb
Host smart-dd7a9c86-850a-48ea-a438-1e0892dbb832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177622618 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3177622618
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.836645355
Short name T947
Test name
Test status
Simulation time 18855497 ps
CPU time 0.81 seconds
Started Mar 07 01:18:33 PM PST 24
Finished Mar 07 01:18:34 PM PST 24
Peak memory 206252 kb
Host smart-bf0c095a-b62a-4b8a-a3fe-297aadeefdc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836645355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.836645355
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2790403176
Short name T918
Test name
Test status
Simulation time 46923698 ps
CPU time 0.84 seconds
Started Mar 07 01:18:32 PM PST 24
Finished Mar 07 01:18:33 PM PST 24
Peak memory 206368 kb
Host smart-4db56a17-03b8-4c7c-bae8-bce2aad07ea8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790403176 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2790403176
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2758773934
Short name T867
Test name
Test status
Simulation time 14434348 ps
CPU time 0.85 seconds
Started Mar 07 01:18:36 PM PST 24
Finished Mar 07 01:18:37 PM PST 24
Peak memory 206332 kb
Host smart-1c4886d3-e97e-4988-b846-06816663826d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758773934 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2758773934
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.692845504
Short name T844
Test name
Test status
Simulation time 36530636 ps
CPU time 0.79 seconds
Started Mar 07 01:18:31 PM PST 24
Finished Mar 07 01:18:32 PM PST 24
Peak memory 206204 kb
Host smart-8b6df294-709a-4f8d-bbe3-7aee1717605f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692845504 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.692845504
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.2103595256
Short name T912
Test name
Test status
Simulation time 41323250 ps
CPU time 0.83 seconds
Started Mar 07 01:18:33 PM PST 24
Finished Mar 07 01:18:34 PM PST 24
Peak memory 206196 kb
Host smart-2ce0540f-db88-4a3c-aeea-11db5ee6200c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103595256 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.2103595256
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.4168459977
Short name T852
Test name
Test status
Simulation time 23588060 ps
CPU time 0.86 seconds
Started Mar 07 01:18:32 PM PST 24
Finished Mar 07 01:18:33 PM PST 24
Peak memory 206384 kb
Host smart-6a51249c-3c8d-4e66-8d6b-ac21b6222068
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168459977 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.4168459977
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.1287843477
Short name T953
Test name
Test status
Simulation time 11079695 ps
CPU time 0.84 seconds
Started Mar 07 01:18:36 PM PST 24
Finished Mar 07 01:18:37 PM PST 24
Peak memory 206328 kb
Host smart-dc440435-a3a8-431f-900a-b5cfc0b01d62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287843477 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.1287843477
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3321220303
Short name T839
Test name
Test status
Simulation time 45128033 ps
CPU time 0.84 seconds
Started Mar 07 01:18:36 PM PST 24
Finished Mar 07 01:18:37 PM PST 24
Peak memory 206384 kb
Host smart-3d4d6200-af7b-4a25-a9c7-d64db7226de9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321220303 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3321220303
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.4096286423
Short name T923
Test name
Test status
Simulation time 59029727 ps
CPU time 1.15 seconds
Started Mar 07 01:18:02 PM PST 24
Finished Mar 07 01:18:03 PM PST 24
Peak memory 206472 kb
Host smart-d2104fe3-31f7-4fac-bed5-2cd475e65000
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096286423 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.4096286423
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2389200989
Short name T215
Test name
Test status
Simulation time 272776804 ps
CPU time 3.23 seconds
Started Mar 07 01:18:03 PM PST 24
Finished Mar 07 01:18:06 PM PST 24
Peak memory 206472 kb
Host smart-065a37bf-74a9-4718-b111-b7bd5ed29487
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389200989 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2389200989
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.1750242297
Short name T211
Test name
Test status
Simulation time 52248317 ps
CPU time 0.89 seconds
Started Mar 07 01:18:05 PM PST 24
Finished Mar 07 01:18:06 PM PST 24
Peak memory 206360 kb
Host smart-c3697a7b-02d5-446b-bdc0-1e1defd82163
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750242297 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.1750242297
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.559653345
Short name T857
Test name
Test status
Simulation time 42466384 ps
CPU time 1.08 seconds
Started Mar 07 01:18:05 PM PST 24
Finished Mar 07 01:18:06 PM PST 24
Peak memory 214708 kb
Host smart-ffa5486a-b1ee-4862-9efa-082e027d4d13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559653345 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.559653345
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2905138472
Short name T208
Test name
Test status
Simulation time 23150817 ps
CPU time 0.86 seconds
Started Mar 07 01:18:04 PM PST 24
Finished Mar 07 01:18:05 PM PST 24
Peak memory 206428 kb
Host smart-d79441d7-49e6-464e-a5f0-07df11fbe194
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905138472 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2905138472
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2862703767
Short name T887
Test name
Test status
Simulation time 13442097 ps
CPU time 0.92 seconds
Started Mar 07 01:18:02 PM PST 24
Finished Mar 07 01:18:03 PM PST 24
Peak memory 206400 kb
Host smart-030a66f9-6c76-4187-bdd1-b98eba2409ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862703767 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2862703767
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.4128880643
Short name T870
Test name
Test status
Simulation time 114625878 ps
CPU time 1.31 seconds
Started Mar 07 01:18:04 PM PST 24
Finished Mar 07 01:18:05 PM PST 24
Peak memory 206424 kb
Host smart-acaaaa3a-c405-4475-afcb-a666cb7bff94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128880643 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.4128880643
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2561813474
Short name T943
Test name
Test status
Simulation time 142906582 ps
CPU time 2.52 seconds
Started Mar 07 01:18:03 PM PST 24
Finished Mar 07 01:18:05 PM PST 24
Peak memory 214728 kb
Host smart-e61778dc-fed5-4087-bc29-38ddfec7e4e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561813474 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2561813474
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.2926889173
Short name T937
Test name
Test status
Simulation time 199347257 ps
CPU time 1.7 seconds
Started Mar 07 01:18:03 PM PST 24
Finished Mar 07 01:18:04 PM PST 24
Peak memory 206464 kb
Host smart-fa84dc57-32ec-4a33-8b53-a7cd67c5f6a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926889173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.2926889173
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.905649569
Short name T949
Test name
Test status
Simulation time 40962678 ps
CPU time 0.87 seconds
Started Mar 07 01:18:33 PM PST 24
Finished Mar 07 01:18:34 PM PST 24
Peak memory 206244 kb
Host smart-62a74485-2706-4237-a59f-9e7ad449320a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905649569 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.905649569
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.2900379822
Short name T880
Test name
Test status
Simulation time 13083599 ps
CPU time 0.85 seconds
Started Mar 07 01:18:35 PM PST 24
Finished Mar 07 01:18:36 PM PST 24
Peak memory 206372 kb
Host smart-8cb36f50-27d7-4bd8-9564-cb5767d74945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900379822 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.2900379822
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.2988389110
Short name T917
Test name
Test status
Simulation time 39772899 ps
CPU time 0.84 seconds
Started Mar 07 01:18:31 PM PST 24
Finished Mar 07 01:18:32 PM PST 24
Peak memory 206300 kb
Host smart-cba0c834-3546-409c-9692-2af159f9bbed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988389110 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.2988389110
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.1915578687
Short name T881
Test name
Test status
Simulation time 41868276 ps
CPU time 0.85 seconds
Started Mar 07 01:18:33 PM PST 24
Finished Mar 07 01:18:34 PM PST 24
Peak memory 206392 kb
Host smart-2ea0ac07-1120-4f45-a75f-850d9d684cb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915578687 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.1915578687
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.3665908401
Short name T905
Test name
Test status
Simulation time 15177086 ps
CPU time 0.88 seconds
Started Mar 07 01:18:30 PM PST 24
Finished Mar 07 01:18:31 PM PST 24
Peak memory 206460 kb
Host smart-9738f531-ff10-4fc8-9fd8-46adcdf4a224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665908401 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.3665908401
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.1287354396
Short name T950
Test name
Test status
Simulation time 25670880 ps
CPU time 0.85 seconds
Started Mar 07 01:18:31 PM PST 24
Finished Mar 07 01:18:32 PM PST 24
Peak memory 206336 kb
Host smart-4d0a588d-c961-4377-a89d-ca131904d037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287354396 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.1287354396
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.2834248960
Short name T841
Test name
Test status
Simulation time 30109958 ps
CPU time 0.86 seconds
Started Mar 07 01:18:38 PM PST 24
Finished Mar 07 01:18:39 PM PST 24
Peak memory 206236 kb
Host smart-c32470c9-4a37-4568-85bd-282422100634
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834248960 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.2834248960
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.3010484490
Short name T846
Test name
Test status
Simulation time 12502033 ps
CPU time 0.86 seconds
Started Mar 07 01:18:31 PM PST 24
Finished Mar 07 01:18:32 PM PST 24
Peak memory 206352 kb
Host smart-0817143e-c77a-486e-8997-b4c0e20d3912
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010484490 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.3010484490
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.1684211916
Short name T847
Test name
Test status
Simulation time 24249851 ps
CPU time 0.84 seconds
Started Mar 07 01:18:33 PM PST 24
Finished Mar 07 01:18:34 PM PST 24
Peak memory 206464 kb
Host smart-3d39c039-5c6f-481a-9e44-766a560b5eaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684211916 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.1684211916
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.666198777
Short name T890
Test name
Test status
Simulation time 11625869 ps
CPU time 0.83 seconds
Started Mar 07 01:18:30 PM PST 24
Finished Mar 07 01:18:31 PM PST 24
Peak memory 206364 kb
Host smart-b0724f2f-4c57-4aaf-b40c-d62df4ca7f54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666198777 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.666198777
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.4282284993
Short name T851
Test name
Test status
Simulation time 35076077 ps
CPU time 1.08 seconds
Started Mar 07 01:18:02 PM PST 24
Finished Mar 07 01:18:03 PM PST 24
Peak memory 206480 kb
Host smart-6b83ad88-5583-48eb-a461-03e6c7516532
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282284993 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.4282284993
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.559623557
Short name T956
Test name
Test status
Simulation time 15548945 ps
CPU time 1 seconds
Started Mar 07 01:18:06 PM PST 24
Finished Mar 07 01:18:07 PM PST 24
Peak memory 206472 kb
Host smart-843c5bcc-a9d8-43e5-82f1-52f74813ae7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559623557 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.559623557
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.4204646641
Short name T957
Test name
Test status
Simulation time 29895744 ps
CPU time 0.84 seconds
Started Mar 07 01:18:03 PM PST 24
Finished Mar 07 01:18:04 PM PST 24
Peak memory 206220 kb
Host smart-ea48ce16-3035-40f8-a917-82692a07a324
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204646641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.4204646641
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.1575141076
Short name T920
Test name
Test status
Simulation time 52962021 ps
CPU time 1.05 seconds
Started Mar 07 01:18:04 PM PST 24
Finished Mar 07 01:18:06 PM PST 24
Peak memory 206444 kb
Host smart-90328777-28a6-41ed-86f9-09376dc2bd34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575141076 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.1575141076
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1414654375
Short name T882
Test name
Test status
Simulation time 62674220 ps
CPU time 1.51 seconds
Started Mar 07 01:18:05 PM PST 24
Finished Mar 07 01:18:07 PM PST 24
Peak memory 214732 kb
Host smart-3461c726-8d9c-4dc6-be52-336faff8577d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414654375 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1414654375
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.3230250647
Short name T958
Test name
Test status
Simulation time 145782542 ps
CPU time 2.71 seconds
Started Mar 07 01:18:05 PM PST 24
Finished Mar 07 01:18:08 PM PST 24
Peak memory 206488 kb
Host smart-44b0dad8-a50d-4fb8-8c92-cb3f387c644a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230250647 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.3230250647
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3340216640
Short name T840
Test name
Test status
Simulation time 22574088 ps
CPU time 1.43 seconds
Started Mar 07 01:18:05 PM PST 24
Finished Mar 07 01:18:07 PM PST 24
Peak memory 214628 kb
Host smart-5f9bd5d8-29c1-43e9-a89a-54b99d72eb5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340216640 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3340216640
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.3084670121
Short name T220
Test name
Test status
Simulation time 40998624 ps
CPU time 0.95 seconds
Started Mar 07 01:18:08 PM PST 24
Finished Mar 07 01:18:09 PM PST 24
Peak memory 206404 kb
Host smart-3b9a344d-9e31-4a44-be78-80ac204920ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084670121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.3084670121
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.2889800346
Short name T928
Test name
Test status
Simulation time 22892620 ps
CPU time 0.84 seconds
Started Mar 07 01:18:05 PM PST 24
Finished Mar 07 01:18:06 PM PST 24
Peak memory 206332 kb
Host smart-a8e97f6f-4b59-40bb-8830-fbd4cedd8c45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889800346 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.2889800346
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.1695157289
Short name T939
Test name
Test status
Simulation time 20483464 ps
CPU time 1.15 seconds
Started Mar 07 01:18:06 PM PST 24
Finished Mar 07 01:18:08 PM PST 24
Peak memory 206408 kb
Host smart-0ad275c3-a6f7-4d4d-ad99-b9a318b4154e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695157289 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.1695157289
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2613157520
Short name T861
Test name
Test status
Simulation time 167596237 ps
CPU time 1.96 seconds
Started Mar 07 01:18:05 PM PST 24
Finished Mar 07 01:18:07 PM PST 24
Peak memory 214580 kb
Host smart-5489e5ab-55ed-4623-918e-b9e27d48560c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613157520 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2613157520
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.3420752388
Short name T239
Test name
Test status
Simulation time 92989775 ps
CPU time 1.72 seconds
Started Mar 07 01:18:08 PM PST 24
Finished Mar 07 01:18:10 PM PST 24
Peak memory 206428 kb
Host smart-c23ede77-3fc2-43c6-819b-e55b7a682ba9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420752388 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.3420752388
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.3686868013
Short name T906
Test name
Test status
Simulation time 97723025 ps
CPU time 2.13 seconds
Started Mar 07 01:18:09 PM PST 24
Finished Mar 07 01:18:11 PM PST 24
Peak memory 214668 kb
Host smart-ac917135-bcc7-4019-b80f-8fe10137882c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686868013 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.3686868013
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.1231920361
Short name T878
Test name
Test status
Simulation time 14415216 ps
CPU time 0.97 seconds
Started Mar 07 01:18:02 PM PST 24
Finished Mar 07 01:18:04 PM PST 24
Peak memory 206420 kb
Host smart-bf7e0eef-8cc8-4534-a49f-6e0ff7ab6cdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231920361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.1231920361
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.3063845778
Short name T873
Test name
Test status
Simulation time 17139729 ps
CPU time 0.83 seconds
Started Mar 07 01:18:05 PM PST 24
Finished Mar 07 01:18:06 PM PST 24
Peak memory 206472 kb
Host smart-acd99a43-1b33-4661-820e-cc7d9782b65f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063845778 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.3063845778
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.2470106400
Short name T930
Test name
Test status
Simulation time 61440942 ps
CPU time 1.24 seconds
Started Mar 07 01:18:05 PM PST 24
Finished Mar 07 01:18:06 PM PST 24
Peak memory 206340 kb
Host smart-7bddee9c-9b12-43b6-9e77-bea018122c35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470106400 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_ou
tstanding.2470106400
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.558363828
Short name T964
Test name
Test status
Simulation time 403915527 ps
CPU time 2.14 seconds
Started Mar 07 01:18:05 PM PST 24
Finished Mar 07 01:18:07 PM PST 24
Peak memory 214808 kb
Host smart-4dfa2389-5ad7-4b28-8597-08bd84d9b574
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558363828 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.558363828
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1265673500
Short name T871
Test name
Test status
Simulation time 92571587 ps
CPU time 2.26 seconds
Started Mar 07 01:18:06 PM PST 24
Finished Mar 07 01:18:08 PM PST 24
Peak memory 206504 kb
Host smart-8c124a36-9cc6-40f7-8da1-0387a0f5b9bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265673500 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1265673500
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.2448958502
Short name T856
Test name
Test status
Simulation time 35094649 ps
CPU time 1.47 seconds
Started Mar 07 01:18:09 PM PST 24
Finished Mar 07 01:18:10 PM PST 24
Peak memory 214680 kb
Host smart-6175e15f-52e0-430f-870e-c0d5495e41ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448958502 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.2448958502
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.51945560
Short name T209
Test name
Test status
Simulation time 43410450 ps
CPU time 0.85 seconds
Started Mar 07 01:18:06 PM PST 24
Finished Mar 07 01:18:08 PM PST 24
Peak memory 206248 kb
Host smart-a9e0d9b0-40a3-4074-8605-bcb9d5273a08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51945560 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.51945560
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3719977169
Short name T966
Test name
Test status
Simulation time 17557755 ps
CPU time 0.91 seconds
Started Mar 07 01:18:09 PM PST 24
Finished Mar 07 01:18:10 PM PST 24
Peak memory 206420 kb
Host smart-b813fac6-f4b9-4d4c-80c0-fb66420820a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719977169 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3719977169
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.3070420464
Short name T967
Test name
Test status
Simulation time 29556551 ps
CPU time 1.16 seconds
Started Mar 07 01:18:09 PM PST 24
Finished Mar 07 01:18:10 PM PST 24
Peak memory 206464 kb
Host smart-13a6ef46-af89-4c96-97c3-92a0fb46ddde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070420464 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.3070420464
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.1315570197
Short name T936
Test name
Test status
Simulation time 102205642 ps
CPU time 2.99 seconds
Started Mar 07 01:18:05 PM PST 24
Finished Mar 07 01:18:09 PM PST 24
Peak memory 214600 kb
Host smart-ed004920-1fbc-4c7a-b6d1-5792f6898ac4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315570197 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.1315570197
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.2193288478
Short name T926
Test name
Test status
Simulation time 240053328 ps
CPU time 1.98 seconds
Started Mar 07 01:18:05 PM PST 24
Finished Mar 07 01:18:07 PM PST 24
Peak memory 206384 kb
Host smart-85b27ab9-314e-4381-857a-8d5176daf7df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193288478 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.2193288478
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.4177302308
Short name T922
Test name
Test status
Simulation time 35895739 ps
CPU time 1.5 seconds
Started Mar 07 01:18:17 PM PST 24
Finished Mar 07 01:18:18 PM PST 24
Peak memory 214604 kb
Host smart-f6a56edf-8145-4139-8e7a-dbfc05a2b8f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177302308 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.4177302308
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.2308673592
Short name T230
Test name
Test status
Simulation time 44248863 ps
CPU time 0.89 seconds
Started Mar 07 01:18:05 PM PST 24
Finished Mar 07 01:18:06 PM PST 24
Peak memory 206384 kb
Host smart-25e0d066-39ee-4943-9d5d-28483f41d89a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308673592 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.2308673592
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1833292924
Short name T960
Test name
Test status
Simulation time 78916947 ps
CPU time 0.79 seconds
Started Mar 07 01:18:08 PM PST 24
Finished Mar 07 01:18:09 PM PST 24
Peak memory 206236 kb
Host smart-a8341769-48fd-4c50-b0f9-0120d9a5aa87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833292924 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1833292924
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.1992937390
Short name T864
Test name
Test status
Simulation time 23424916 ps
CPU time 0.93 seconds
Started Mar 07 01:18:19 PM PST 24
Finished Mar 07 01:18:20 PM PST 24
Peak memory 206428 kb
Host smart-b6241f26-7c85-494b-90b1-411efe04c3be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992937390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.1992937390
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.2762385845
Short name T885
Test name
Test status
Simulation time 1225578877 ps
CPU time 5.02 seconds
Started Mar 07 01:18:07 PM PST 24
Finished Mar 07 01:18:12 PM PST 24
Peak memory 214736 kb
Host smart-e3e8559a-f431-40f9-beda-aa2f0306d3a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762385845 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.2762385845
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.420253501
Short name T911
Test name
Test status
Simulation time 268592200 ps
CPU time 2.04 seconds
Started Mar 07 01:18:09 PM PST 24
Finished Mar 07 01:18:11 PM PST 24
Peak memory 206424 kb
Host smart-35b7eb6d-1f6b-409b-ab6b-6fb71d258894
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420253501 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.420253501
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_disable.3218511035
Short name T389
Test name
Test status
Simulation time 13148592 ps
CPU time 0.9 seconds
Started Mar 07 02:38:27 PM PST 24
Finished Mar 07 02:38:28 PM PST 24
Peak memory 214696 kb
Host smart-87e6c094-4700-401c-ad33-46ebab145afc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218511035 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.3218511035
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_err.694255470
Short name T171
Test name
Test status
Simulation time 298865003 ps
CPU time 1.36 seconds
Started Mar 07 02:38:24 PM PST 24
Finished Mar 07 02:38:26 PM PST 24
Peak memory 214676 kb
Host smart-a313c06a-9827-4da0-bc0f-bc1146ced41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694255470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.694255470
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.3637360043
Short name T711
Test name
Test status
Simulation time 72675065 ps
CPU time 1.34 seconds
Started Mar 07 02:38:23 PM PST 24
Finished Mar 07 02:38:24 PM PST 24
Peak memory 217200 kb
Host smart-54694c1b-5778-4489-882f-ca7f5d51e1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637360043 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.3637360043
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.218827614
Short name T134
Test name
Test status
Simulation time 39319227 ps
CPU time 0.86 seconds
Started Mar 07 02:38:25 PM PST 24
Finished Mar 07 02:38:26 PM PST 24
Peak memory 214684 kb
Host smart-34bd40fb-2de8-466a-b06c-6ab0f812e862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218827614 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.218827614
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.1687432452
Short name T50
Test name
Test status
Simulation time 381275151 ps
CPU time 3.76 seconds
Started Mar 07 02:38:35 PM PST 24
Finished Mar 07 02:38:40 PM PST 24
Peak memory 234592 kb
Host smart-44bd348c-c1e8-49ff-b1cd-acd506d36efe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687432452 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.1687432452
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.3409645806
Short name T461
Test name
Test status
Simulation time 23722787 ps
CPU time 0.92 seconds
Started Mar 07 02:38:25 PM PST 24
Finished Mar 07 02:38:26 PM PST 24
Peak memory 214452 kb
Host smart-1854b245-f8e4-447c-ad74-b73affbfe26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409645806 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.3409645806
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.3133782294
Short name T416
Test name
Test status
Simulation time 415223694 ps
CPU time 5.95 seconds
Started Mar 07 02:38:29 PM PST 24
Finished Mar 07 02:38:39 PM PST 24
Peak memory 217896 kb
Host smart-f0ac3dd0-0215-427a-8319-1a50febbe1f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133782294 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.3133782294
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.922175283
Short name T776
Test name
Test status
Simulation time 199002427948 ps
CPU time 1326.77 seconds
Started Mar 07 02:38:22 PM PST 24
Finished Mar 07 03:00:29 PM PST 24
Peak memory 222248 kb
Host smart-6fcfc86f-b88b-4592-a531-ef6f85129f98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922175283 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.922175283
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.3390327809
Short name T770
Test name
Test status
Simulation time 38540017 ps
CPU time 1.11 seconds
Started Mar 07 02:38:36 PM PST 24
Finished Mar 07 02:38:38 PM PST 24
Peak memory 214764 kb
Host smart-6fc5eb73-748e-4264-a720-07ff0f027959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390327809 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.3390327809
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.990646439
Short name T802
Test name
Test status
Simulation time 55575655 ps
CPU time 1.07 seconds
Started Mar 07 02:38:43 PM PST 24
Finished Mar 07 02:38:44 PM PST 24
Peak memory 205340 kb
Host smart-e1e83bc4-be67-4cfe-a2dd-9a28109b2f93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990646439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.990646439
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.3799091544
Short name T671
Test name
Test status
Simulation time 11609472 ps
CPU time 0.88 seconds
Started Mar 07 02:38:43 PM PST 24
Finished Mar 07 02:38:44 PM PST 24
Peak memory 214848 kb
Host smart-4816cc53-290c-4896-923e-c575cf4aca73
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799091544 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3799091544
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.1177419502
Short name T2
Test name
Test status
Simulation time 60371001 ps
CPU time 0.92 seconds
Started Mar 07 02:38:42 PM PST 24
Finished Mar 07 02:38:43 PM PST 24
Peak memory 215688 kb
Host smart-30e951b9-c33c-444d-9934-5c2e6525d466
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177419502 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_di
sable_auto_req_mode.1177419502
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.1207655377
Short name T42
Test name
Test status
Simulation time 30909272 ps
CPU time 1 seconds
Started Mar 07 02:38:35 PM PST 24
Finished Mar 07 02:38:37 PM PST 24
Peak memory 222208 kb
Host smart-ad4f50d1-e901-4695-bdb9-226895919fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207655377 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.1207655377
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2186030139
Short name T827
Test name
Test status
Simulation time 43372590 ps
CPU time 1.49 seconds
Started Mar 07 02:38:35 PM PST 24
Finished Mar 07 02:38:38 PM PST 24
Peak memory 216836 kb
Host smart-b574f78b-ebe0-43d3-9610-ad172c00ab6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186030139 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2186030139
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.3720107608
Short name T732
Test name
Test status
Simulation time 35422484 ps
CPU time 0.84 seconds
Started Mar 07 02:38:37 PM PST 24
Finished Mar 07 02:38:40 PM PST 24
Peak memory 214532 kb
Host smart-88fab54f-9046-48f1-a446-d0c06731d42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720107608 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.3720107608
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.2490859230
Short name T18
Test name
Test status
Simulation time 368004261 ps
CPU time 6.54 seconds
Started Mar 07 02:38:41 PM PST 24
Finished Mar 07 02:38:48 PM PST 24
Peak memory 235840 kb
Host smart-5e96eb27-501b-4c78-a746-6fd0856fefa7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490859230 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.2490859230
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.2317729432
Short name T490
Test name
Test status
Simulation time 71600109 ps
CPU time 0.9 seconds
Started Mar 07 02:38:33 PM PST 24
Finished Mar 07 02:38:36 PM PST 24
Peak memory 214412 kb
Host smart-ca1eb9e9-1f85-41c6-a314-76772a51f0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317729432 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.2317729432
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.1470735393
Short name T310
Test name
Test status
Simulation time 409932004 ps
CPU time 2.71 seconds
Started Mar 07 02:38:35 PM PST 24
Finished Mar 07 02:38:38 PM PST 24
Peak memory 214336 kb
Host smart-62254758-2202-4671-81a8-7c7e37563c16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470735393 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1470735393
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.3855595995
Short name T411
Test name
Test status
Simulation time 64632246546 ps
CPU time 1543.57 seconds
Started Mar 07 02:38:34 PM PST 24
Finished Mar 07 03:04:20 PM PST 24
Peak memory 224792 kb
Host smart-092666f8-e2c5-4d45-9232-ee1f627e1c33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855595995 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.3855595995
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert.1448644793
Short name T106
Test name
Test status
Simulation time 122447025 ps
CPU time 1.13 seconds
Started Mar 07 02:39:18 PM PST 24
Finished Mar 07 02:39:19 PM PST 24
Peak memory 214784 kb
Host smart-202b2e2a-d22e-461b-86bd-c0b6ddb5c9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448644793 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.1448644793
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/default/10.edn_alert_test.2246832507
Short name T555
Test name
Test status
Simulation time 22949653 ps
CPU time 1.03 seconds
Started Mar 07 02:39:28 PM PST 24
Finished Mar 07 02:39:31 PM PST 24
Peak memory 205648 kb
Host smart-be12d34e-b494-4acf-80c9-81fba3426085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246832507 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2246832507
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable.2937110986
Short name T100
Test name
Test status
Simulation time 23381888 ps
CPU time 0.87 seconds
Started Mar 07 02:39:19 PM PST 24
Finished Mar 07 02:39:20 PM PST 24
Peak memory 214976 kb
Host smart-25823dee-14fb-4673-8e12-6fd25deed4fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937110986 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2937110986
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.1220158805
Short name T437
Test name
Test status
Simulation time 82034500 ps
CPU time 1.01 seconds
Started Mar 07 02:39:21 PM PST 24
Finished Mar 07 02:39:22 PM PST 24
Peak memory 216772 kb
Host smart-e90353f0-0ca6-4e48-acab-0d32a69e11d2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220158805 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.1220158805
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_err.140378259
Short name T72
Test name
Test status
Simulation time 28399393 ps
CPU time 1.06 seconds
Started Mar 07 02:39:21 PM PST 24
Finished Mar 07 02:39:22 PM PST 24
Peak memory 215748 kb
Host smart-598b1553-3d61-4f3d-a3f6-869a1d9cb7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140378259 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.140378259
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/10.edn_intr.2344091314
Short name T488
Test name
Test status
Simulation time 21905873 ps
CPU time 1.04 seconds
Started Mar 07 02:39:19 PM PST 24
Finished Mar 07 02:39:20 PM PST 24
Peak memory 214772 kb
Host smart-fb5629dd-9128-43ca-83da-ffbf643f33a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344091314 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.2344091314
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.2401664663
Short name T1
Test name
Test status
Simulation time 82850880 ps
CPU time 0.93 seconds
Started Mar 07 02:39:20 PM PST 24
Finished Mar 07 02:39:21 PM PST 24
Peak memory 214408 kb
Host smart-e1c0513a-1594-4f34-a2f6-9e73ca4426e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401664663 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.2401664663
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.3404172821
Short name T541
Test name
Test status
Simulation time 557811889 ps
CPU time 3.33 seconds
Started Mar 07 02:39:20 PM PST 24
Finished Mar 07 02:39:23 PM PST 24
Peak memory 215528 kb
Host smart-91c38c60-ea28-4c83-8c14-ec5a331e9b42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404172821 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.3404172821
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1649465276
Short name T357
Test name
Test status
Simulation time 21579041851 ps
CPU time 461.76 seconds
Started Mar 07 02:39:17 PM PST 24
Finished Mar 07 02:46:59 PM PST 24
Peak memory 222608 kb
Host smart-8d0a8a8c-48bb-43c5-ba42-7de014dd3123
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649465276 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1649465276
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.2348182422
Short name T761
Test name
Test status
Simulation time 56517063 ps
CPU time 1.27 seconds
Started Mar 07 02:41:55 PM PST 24
Finished Mar 07 02:41:56 PM PST 24
Peak memory 215656 kb
Host smart-4acdcddd-f052-486b-bfab-d976904e9102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348182422 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.2348182422
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.2343731242
Short name T37
Test name
Test status
Simulation time 97717860 ps
CPU time 1.44 seconds
Started Mar 07 02:41:55 PM PST 24
Finished Mar 07 02:41:57 PM PST 24
Peak memory 217216 kb
Host smart-f056efb2-d4fc-4cef-8f13-f3d397ed9c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343731242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.2343731242
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/102.edn_genbits.3562305511
Short name T400
Test name
Test status
Simulation time 75355546 ps
CPU time 1.79 seconds
Started Mar 07 02:41:54 PM PST 24
Finished Mar 07 02:41:56 PM PST 24
Peak memory 217116 kb
Host smart-7e8c910a-b547-4eda-b499-3e1c8939500c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562305511 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3562305511
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.1564776336
Short name T396
Test name
Test status
Simulation time 44688634 ps
CPU time 1.46 seconds
Started Mar 07 02:41:55 PM PST 24
Finished Mar 07 02:41:57 PM PST 24
Peak memory 215700 kb
Host smart-7a8b64d5-cd81-411b-97b5-ab5ea958f3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564776336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.1564776336
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.4241686894
Short name T370
Test name
Test status
Simulation time 109586132 ps
CPU time 1.36 seconds
Started Mar 07 02:41:58 PM PST 24
Finished Mar 07 02:41:59 PM PST 24
Peak memory 215900 kb
Host smart-3b448a80-0979-4ca8-8607-450cc27540aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241686894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.4241686894
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.3015761995
Short name T703
Test name
Test status
Simulation time 64785444 ps
CPU time 1.42 seconds
Started Mar 07 02:41:55 PM PST 24
Finished Mar 07 02:41:57 PM PST 24
Peak memory 214348 kb
Host smart-5d17d2de-5941-4329-9b00-430dcd04f226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015761995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.3015761995
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.1221958544
Short name T816
Test name
Test status
Simulation time 30604509 ps
CPU time 1.07 seconds
Started Mar 07 02:41:56 PM PST 24
Finished Mar 07 02:41:57 PM PST 24
Peak memory 216016 kb
Host smart-f527b409-ba87-436d-94d2-f8cd91be2457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221958544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.1221958544
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.355286517
Short name T501
Test name
Test status
Simulation time 52777525 ps
CPU time 1.17 seconds
Started Mar 07 02:41:53 PM PST 24
Finished Mar 07 02:41:54 PM PST 24
Peak memory 215568 kb
Host smart-08a2fd03-0ff7-4ab6-859e-c7fd9b42947a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355286517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.355286517
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.3755576735
Short name T757
Test name
Test status
Simulation time 47964864 ps
CPU time 1.46 seconds
Started Mar 07 02:41:54 PM PST 24
Finished Mar 07 02:41:55 PM PST 24
Peak memory 217208 kb
Host smart-47eb7b1b-6c99-401d-830a-d4a96529b7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755576735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3755576735
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.1475299850
Short name T796
Test name
Test status
Simulation time 81079092 ps
CPU time 0.9 seconds
Started Mar 07 02:39:28 PM PST 24
Finished Mar 07 02:39:30 PM PST 24
Peak memory 206040 kb
Host smart-53c4c24a-08da-472c-97af-7fb736e1d449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475299850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.1475299850
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_disable.749772490
Short name T55
Test name
Test status
Simulation time 14909272 ps
CPU time 0.82 seconds
Started Mar 07 02:39:29 PM PST 24
Finished Mar 07 02:39:31 PM PST 24
Peak memory 214632 kb
Host smart-cf84c6fe-6181-4c48-9ad2-cb3b9a2fc20e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749772490 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.749772490
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2657865521
Short name T69
Test name
Test status
Simulation time 22792418 ps
CPU time 0.95 seconds
Started Mar 07 02:39:29 PM PST 24
Finished Mar 07 02:39:31 PM PST 24
Peak memory 215452 kb
Host smart-c746465a-d9cb-44c3-87cb-8934c40c6e1a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657865521 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2657865521
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/11.edn_err.2270481974
Short name T493
Test name
Test status
Simulation time 26299868 ps
CPU time 0.91 seconds
Started Mar 07 02:39:31 PM PST 24
Finished Mar 07 02:39:32 PM PST 24
Peak memory 217232 kb
Host smart-699fdc0d-c506-4c0c-9e9d-0965540401fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270481974 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.2270481974
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_genbits.1974622828
Short name T623
Test name
Test status
Simulation time 24282855 ps
CPU time 1.17 seconds
Started Mar 07 02:39:28 PM PST 24
Finished Mar 07 02:39:31 PM PST 24
Peak memory 215812 kb
Host smart-5d0a5519-2918-4339-8861-7c454d67879a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974622828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.1974622828
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_intr.240779886
Short name T363
Test name
Test status
Simulation time 31211433 ps
CPU time 0.83 seconds
Started Mar 07 02:39:28 PM PST 24
Finished Mar 07 02:39:30 PM PST 24
Peak memory 214772 kb
Host smart-803bf5aa-97e8-486c-bbb9-0e1be64aaf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240779886 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.240779886
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.802884202
Short name T527
Test name
Test status
Simulation time 49968660 ps
CPU time 0.91 seconds
Started Mar 07 02:39:30 PM PST 24
Finished Mar 07 02:39:31 PM PST 24
Peak memory 206180 kb
Host smart-a7923c0c-f7de-4529-9f0f-64870427742e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802884202 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.802884202
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.1932469134
Short name T664
Test name
Test status
Simulation time 103907444 ps
CPU time 2.28 seconds
Started Mar 07 02:39:27 PM PST 24
Finished Mar 07 02:39:29 PM PST 24
Peak memory 214356 kb
Host smart-3c1ab0ed-fbe0-4f22-99b6-77b423efd424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932469134 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.1932469134
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.2514714336
Short name T190
Test name
Test status
Simulation time 28146529679 ps
CPU time 568.01 seconds
Started Mar 07 02:39:28 PM PST 24
Finished Mar 07 02:48:58 PM PST 24
Peak memory 222716 kb
Host smart-47f6ce09-6550-414a-bcfc-915ab5b0f308
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514714336 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.2514714336
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.edn_genbits.1128687247
Short name T753
Test name
Test status
Simulation time 39689809 ps
CPU time 1.75 seconds
Started Mar 07 02:41:55 PM PST 24
Finished Mar 07 02:41:57 PM PST 24
Peak memory 215860 kb
Host smart-8fbfabee-39d9-4622-a57f-66d96ca03e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128687247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1128687247
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.2560221507
Short name T36
Test name
Test status
Simulation time 79665140 ps
CPU time 1.38 seconds
Started Mar 07 02:41:58 PM PST 24
Finished Mar 07 02:41:59 PM PST 24
Peak memory 217108 kb
Host smart-5b4af2e3-599e-4ef4-995b-3a6fd66c9a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560221507 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.2560221507
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.4043500019
Short name T792
Test name
Test status
Simulation time 46241861 ps
CPU time 1.19 seconds
Started Mar 07 02:41:58 PM PST 24
Finished Mar 07 02:41:59 PM PST 24
Peak memory 217640 kb
Host smart-88115d48-0ec2-4d8b-8824-2ec8e926a2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043500019 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.4043500019
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.3224767891
Short name T726
Test name
Test status
Simulation time 61995343 ps
CPU time 1.81 seconds
Started Mar 07 02:41:58 PM PST 24
Finished Mar 07 02:42:00 PM PST 24
Peak memory 216952 kb
Host smart-68e3d874-dcc8-4fd3-a7bc-652f2527ce0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224767891 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3224767891
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.1569236550
Short name T826
Test name
Test status
Simulation time 46825963 ps
CPU time 1.45 seconds
Started Mar 07 02:41:57 PM PST 24
Finished Mar 07 02:41:59 PM PST 24
Peak memory 215716 kb
Host smart-e5051986-5103-47d9-88f0-2cf3a5734888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569236550 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.1569236550
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.4104828314
Short name T700
Test name
Test status
Simulation time 76308907 ps
CPU time 2.58 seconds
Started Mar 07 02:41:55 PM PST 24
Finished Mar 07 02:41:57 PM PST 24
Peak memory 218084 kb
Host smart-5b0b4855-7876-45da-9a43-d31854613628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104828314 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.4104828314
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.3624160741
Short name T713
Test name
Test status
Simulation time 72848011 ps
CPU time 1.42 seconds
Started Mar 07 02:41:56 PM PST 24
Finished Mar 07 02:41:58 PM PST 24
Peak memory 216968 kb
Host smart-b4f2ab14-c6f7-41e6-9e1b-c5d23fc5a060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624160741 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3624160741
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.652610595
Short name T647
Test name
Test status
Simulation time 37390040 ps
CPU time 1.44 seconds
Started Mar 07 02:41:57 PM PST 24
Finished Mar 07 02:41:59 PM PST 24
Peak memory 216988 kb
Host smart-8c3b0762-0ea6-485d-b45b-6a8d8cc0d214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652610595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.652610595
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.43027188
Short name T145
Test name
Test status
Simulation time 30122087 ps
CPU time 1.32 seconds
Started Mar 07 02:39:30 PM PST 24
Finished Mar 07 02:39:32 PM PST 24
Peak memory 214768 kb
Host smart-b322c6ba-f60f-4a42-a40e-c001f5d16856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43027188 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.43027188
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.246493660
Short name T509
Test name
Test status
Simulation time 120621744 ps
CPU time 0.79 seconds
Started Mar 07 02:39:30 PM PST 24
Finished Mar 07 02:39:31 PM PST 24
Peak memory 204840 kb
Host smart-daf4b8c7-0657-4dbb-892e-21e5aa95110e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246493660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.246493660
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_err.1611901078
Short name T736
Test name
Test status
Simulation time 20577373 ps
CPU time 1.12 seconds
Started Mar 07 02:39:28 PM PST 24
Finished Mar 07 02:39:31 PM PST 24
Peak memory 222260 kb
Host smart-3e1e64c5-d346-41c3-8e67-e540bf1eafbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611901078 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.1611901078
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.2236558033
Short name T794
Test name
Test status
Simulation time 38818714 ps
CPU time 1.33 seconds
Started Mar 07 02:39:28 PM PST 24
Finished Mar 07 02:39:31 PM PST 24
Peak memory 217048 kb
Host smart-727c3aec-f60c-43ae-8e98-eac6ca5872cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236558033 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.2236558033
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.3573236310
Short name T670
Test name
Test status
Simulation time 22330528 ps
CPU time 1.18 seconds
Started Mar 07 02:39:28 PM PST 24
Finished Mar 07 02:39:29 PM PST 24
Peak memory 223204 kb
Host smart-e3f54dbd-5ee9-4378-8f17-e90369f11ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573236310 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.3573236310
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.1726994721
Short name T311
Test name
Test status
Simulation time 44726722 ps
CPU time 0.91 seconds
Started Mar 07 02:39:29 PM PST 24
Finished Mar 07 02:39:31 PM PST 24
Peak memory 214416 kb
Host smart-6952ef0b-81e0-4b71-a475-a4c6c647dd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726994721 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.1726994721
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.2902463933
Short name T6
Test name
Test status
Simulation time 962616658 ps
CPU time 2.63 seconds
Started Mar 07 02:39:29 PM PST 24
Finished Mar 07 02:39:33 PM PST 24
Peak memory 215476 kb
Host smart-4fd14aca-06c2-4e91-9360-1d0641b51066
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902463933 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.2902463933
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.401918540
Short name T441
Test name
Test status
Simulation time 23115554054 ps
CPU time 591.22 seconds
Started Mar 07 02:39:31 PM PST 24
Finished Mar 07 02:49:22 PM PST 24
Peak memory 216652 kb
Host smart-7011af39-193b-480f-9728-0627013416d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401918540 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.401918540
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.795635811
Short name T300
Test name
Test status
Simulation time 41077451 ps
CPU time 1.09 seconds
Started Mar 07 02:41:57 PM PST 24
Finished Mar 07 02:41:58 PM PST 24
Peak memory 215480 kb
Host smart-b163543b-30d4-4d9d-bb27-27883f2f8a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795635811 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.795635811
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.977208217
Short name T513
Test name
Test status
Simulation time 48164185 ps
CPU time 1.6 seconds
Started Mar 07 02:42:09 PM PST 24
Finished Mar 07 02:42:11 PM PST 24
Peak memory 215560 kb
Host smart-cf335a50-82c4-4636-86c0-a091b66bf4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977208217 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.977208217
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.4123087245
Short name T553
Test name
Test status
Simulation time 102426963 ps
CPU time 1.26 seconds
Started Mar 07 02:42:07 PM PST 24
Finished Mar 07 02:42:09 PM PST 24
Peak memory 217116 kb
Host smart-a893ff5e-b63c-4445-8df9-74453be90550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123087245 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.4123087245
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.549161512
Short name T525
Test name
Test status
Simulation time 68338352 ps
CPU time 1.63 seconds
Started Mar 07 02:42:04 PM PST 24
Finished Mar 07 02:42:06 PM PST 24
Peak memory 217204 kb
Host smart-5ccd20ef-435b-4699-b2df-d62ee5bdafc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549161512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.549161512
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.3466226242
Short name T721
Test name
Test status
Simulation time 87928112 ps
CPU time 1.47 seconds
Started Mar 07 02:42:05 PM PST 24
Finished Mar 07 02:42:06 PM PST 24
Peak memory 217132 kb
Host smart-520ca134-6dcb-486b-8d60-eddc832b99fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466226242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3466226242
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.682701362
Short name T650
Test name
Test status
Simulation time 135909933 ps
CPU time 1.09 seconds
Started Mar 07 02:42:06 PM PST 24
Finished Mar 07 02:42:07 PM PST 24
Peak memory 215600 kb
Host smart-c26cc6a9-7a69-4082-b04e-c25d054eae52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682701362 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.682701362
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.3791439263
Short name T35
Test name
Test status
Simulation time 54910863 ps
CPU time 1.05 seconds
Started Mar 07 02:42:05 PM PST 24
Finished Mar 07 02:42:07 PM PST 24
Peak memory 215560 kb
Host smart-47a695aa-8aba-4976-822d-ee21c522bbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791439263 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.3791439263
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.3519132519
Short name T474
Test name
Test status
Simulation time 142164544 ps
CPU time 3.15 seconds
Started Mar 07 02:42:09 PM PST 24
Finished Mar 07 02:42:13 PM PST 24
Peak memory 216856 kb
Host smart-534fa801-3efc-46c8-bf5e-fbdbdf995250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519132519 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.3519132519
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.3041505250
Short name T570
Test name
Test status
Simulation time 55531598 ps
CPU time 1.49 seconds
Started Mar 07 02:42:08 PM PST 24
Finished Mar 07 02:42:10 PM PST 24
Peak memory 217172 kb
Host smart-34d1aca4-7506-4728-9a91-7947cf654015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041505250 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.3041505250
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/129.edn_genbits.687248479
Short name T498
Test name
Test status
Simulation time 60083115 ps
CPU time 1.53 seconds
Started Mar 07 02:42:09 PM PST 24
Finished Mar 07 02:42:11 PM PST 24
Peak memory 218000 kb
Host smart-8434de3d-d0d8-413e-bc29-7ce7d9faa61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687248479 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.687248479
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert_test.2000479631
Short name T387
Test name
Test status
Simulation time 81071467 ps
CPU time 1.02 seconds
Started Mar 07 02:39:39 PM PST 24
Finished Mar 07 02:39:42 PM PST 24
Peak memory 206072 kb
Host smart-b7c89250-a776-45f1-bab4-c892285ecabf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000479631 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.2000479631
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.2741394699
Short name T412
Test name
Test status
Simulation time 43086674 ps
CPU time 1.37 seconds
Started Mar 07 02:39:40 PM PST 24
Finished Mar 07 02:39:42 PM PST 24
Peak memory 215520 kb
Host smart-f3189452-d7c1-4b94-9801-7ebb670b9a58
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741394699 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.2741394699
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.1472731395
Short name T557
Test name
Test status
Simulation time 30123849 ps
CPU time 1.34 seconds
Started Mar 07 02:39:28 PM PST 24
Finished Mar 07 02:39:31 PM PST 24
Peak memory 223544 kb
Host smart-713506b5-3b26-4ad3-94bc-cb74c3e17245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472731395 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.1472731395
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2676299683
Short name T328
Test name
Test status
Simulation time 29382456 ps
CPU time 1.14 seconds
Started Mar 07 02:39:30 PM PST 24
Finished Mar 07 02:39:31 PM PST 24
Peak memory 218484 kb
Host smart-123a664d-d491-442a-8686-e6bf8810cb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676299683 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2676299683
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_intr.2290091602
Short name T351
Test name
Test status
Simulation time 31684638 ps
CPU time 0.87 seconds
Started Mar 07 02:39:31 PM PST 24
Finished Mar 07 02:39:32 PM PST 24
Peak memory 214412 kb
Host smart-983f75a3-e8dd-430d-90a3-774f39b2b999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290091602 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.2290091602
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/13.edn_smoke.3265091517
Short name T775
Test name
Test status
Simulation time 31045791 ps
CPU time 0.99 seconds
Started Mar 07 02:39:29 PM PST 24
Finished Mar 07 02:39:31 PM PST 24
Peak memory 214408 kb
Host smart-04603f54-0257-497e-926b-4d05a857e441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265091517 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.3265091517
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1820948572
Short name T153
Test name
Test status
Simulation time 278057942 ps
CPU time 2.86 seconds
Started Mar 07 02:39:30 PM PST 24
Finished Mar 07 02:39:33 PM PST 24
Peak memory 215388 kb
Host smart-a481ce80-ed7a-4883-9983-8c83798a981e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820948572 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1820948572
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/130.edn_genbits.2239041803
Short name T695
Test name
Test status
Simulation time 52484520 ps
CPU time 0.94 seconds
Started Mar 07 02:42:07 PM PST 24
Finished Mar 07 02:42:09 PM PST 24
Peak memory 215748 kb
Host smart-65e1b9d7-84f1-4181-9194-2290c27f101e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239041803 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2239041803
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.2302748470
Short name T609
Test name
Test status
Simulation time 35088465 ps
CPU time 1.37 seconds
Started Mar 07 02:42:08 PM PST 24
Finished Mar 07 02:42:10 PM PST 24
Peak memory 216616 kb
Host smart-70ccfa39-8fb4-4dd6-bff7-3a7d20374e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302748470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.2302748470
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2267211577
Short name T429
Test name
Test status
Simulation time 69763216 ps
CPU time 1.47 seconds
Started Mar 07 02:42:11 PM PST 24
Finished Mar 07 02:42:12 PM PST 24
Peak memory 216992 kb
Host smart-20fde736-08f7-4037-90f8-c68cb19b4718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267211577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2267211577
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.1442969838
Short name T33
Test name
Test status
Simulation time 54253759 ps
CPU time 1.35 seconds
Started Mar 07 02:42:07 PM PST 24
Finished Mar 07 02:42:09 PM PST 24
Peak memory 215792 kb
Host smart-e1ea0b35-ad8b-4537-b662-38e814f75642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442969838 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1442969838
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.3159154251
Short name T769
Test name
Test status
Simulation time 56815484 ps
CPU time 1.11 seconds
Started Mar 07 02:42:08 PM PST 24
Finished Mar 07 02:42:10 PM PST 24
Peak memory 217288 kb
Host smart-6b3594a6-207b-4139-96d7-0f84510ff9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159154251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3159154251
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1292184210
Short name T579
Test name
Test status
Simulation time 40915624 ps
CPU time 1.49 seconds
Started Mar 07 02:42:09 PM PST 24
Finished Mar 07 02:42:11 PM PST 24
Peak memory 217024 kb
Host smart-334305ea-0373-4c25-8c6e-2cba4178f9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292184210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1292184210
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.1964872350
Short name T593
Test name
Test status
Simulation time 68663130 ps
CPU time 1.47 seconds
Started Mar 07 02:42:08 PM PST 24
Finished Mar 07 02:42:10 PM PST 24
Peak memory 216996 kb
Host smart-46175d80-2cb7-46f3-b5dc-e8332f2bc37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964872350 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1964872350
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.3891869540
Short name T62
Test name
Test status
Simulation time 100434200 ps
CPU time 1.18 seconds
Started Mar 07 02:39:37 PM PST 24
Finished Mar 07 02:39:39 PM PST 24
Peak memory 214796 kb
Host smart-b774571f-0686-41ca-a416-5345299d061d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891869540 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.3891869540
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.1459034281
Short name T550
Test name
Test status
Simulation time 88259593 ps
CPU time 0.97 seconds
Started Mar 07 02:39:39 PM PST 24
Finished Mar 07 02:39:41 PM PST 24
Peak memory 205704 kb
Host smart-c38f6355-cfd6-4f1f-9cda-b6265c82e133
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459034281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.1459034281
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.1149763706
Short name T692
Test name
Test status
Simulation time 12873118 ps
CPU time 0.91 seconds
Started Mar 07 02:39:38 PM PST 24
Finished Mar 07 02:39:40 PM PST 24
Peak memory 214836 kb
Host smart-6f4e5c92-450c-41ca-9d7b-5fc69d2ebef0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149763706 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.1149763706
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.361530022
Short name T592
Test name
Test status
Simulation time 54335827 ps
CPU time 1.1 seconds
Started Mar 07 02:39:37 PM PST 24
Finished Mar 07 02:39:39 PM PST 24
Peak memory 215564 kb
Host smart-c758fee2-0e80-4de4-96fd-c2a5800639b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361530022 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_di
sable_auto_req_mode.361530022
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.1803124175
Short name T822
Test name
Test status
Simulation time 31664623 ps
CPU time 1.23 seconds
Started Mar 07 02:39:42 PM PST 24
Finished Mar 07 02:39:44 PM PST 24
Peak memory 218220 kb
Host smart-8abdabed-411b-4859-b7f9-8bdf58cec995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803124175 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.1803124175
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3997056115
Short name T543
Test name
Test status
Simulation time 65116981 ps
CPU time 1.12 seconds
Started Mar 07 02:39:38 PM PST 24
Finished Mar 07 02:39:39 PM PST 24
Peak memory 217236 kb
Host smart-7c9f5d38-3bfe-4dae-806a-0a61e780f9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997056115 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3997056115
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.2211506864
Short name T654
Test name
Test status
Simulation time 57331621 ps
CPU time 0.85 seconds
Started Mar 07 02:39:36 PM PST 24
Finished Mar 07 02:39:37 PM PST 24
Peak memory 214704 kb
Host smart-72324abc-3e0e-4740-8742-af157ab945ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211506864 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.2211506864
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.1614609905
Short name T456
Test name
Test status
Simulation time 15496540 ps
CPU time 1 seconds
Started Mar 07 02:39:40 PM PST 24
Finished Mar 07 02:39:42 PM PST 24
Peak memory 214400 kb
Host smart-c4d66757-0c96-43bd-93d0-8af88ccd95bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614609905 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.1614609905
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.3674758066
Short name T442
Test name
Test status
Simulation time 422697272 ps
CPU time 4.35 seconds
Started Mar 07 02:39:38 PM PST 24
Finished Mar 07 02:39:43 PM PST 24
Peak memory 216828 kb
Host smart-b9761dec-2349-4506-a266-8730073fa092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674758066 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.3674758066
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.11992954
Short name T479
Test name
Test status
Simulation time 65860524778 ps
CPU time 1659.83 seconds
Started Mar 07 02:39:40 PM PST 24
Finished Mar 07 03:07:21 PM PST 24
Peak memory 224600 kb
Host smart-e53773f9-536d-4fa9-9c82-7c899f6e1daf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11992954 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.11992954
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.edn_genbits.2243584599
Short name T241
Test name
Test status
Simulation time 35536463 ps
CPU time 1.35 seconds
Started Mar 07 02:42:07 PM PST 24
Finished Mar 07 02:42:09 PM PST 24
Peak memory 215552 kb
Host smart-50dd4033-9bed-4c70-a9ce-84b1f24ec96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243584599 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2243584599
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/141.edn_genbits.1452837279
Short name T680
Test name
Test status
Simulation time 35968309 ps
CPU time 1.45 seconds
Started Mar 07 02:42:07 PM PST 24
Finished Mar 07 02:42:10 PM PST 24
Peak memory 216816 kb
Host smart-0f1959f9-936f-4875-b629-dd1201ea4370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452837279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.1452837279
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.2318507197
Short name T539
Test name
Test status
Simulation time 111240842 ps
CPU time 1.17 seconds
Started Mar 07 02:42:06 PM PST 24
Finished Mar 07 02:42:07 PM PST 24
Peak memory 216976 kb
Host smart-b54611bb-9d27-4e6b-8945-5d768b823d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318507197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.2318507197
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.4096932322
Short name T740
Test name
Test status
Simulation time 100432886 ps
CPU time 1.52 seconds
Started Mar 07 02:42:07 PM PST 24
Finished Mar 07 02:42:10 PM PST 24
Peak memory 216796 kb
Host smart-7a7a8905-8d47-4679-a2ec-ab4362bd7c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096932322 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.4096932322
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.3604672068
Short name T333
Test name
Test status
Simulation time 65046763 ps
CPU time 1.45 seconds
Started Mar 07 02:42:06 PM PST 24
Finished Mar 07 02:42:08 PM PST 24
Peak memory 217204 kb
Host smart-4637874a-d5bc-4835-be33-20f627d5876b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604672068 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.3604672068
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.600882643
Short name T453
Test name
Test status
Simulation time 29748179 ps
CPU time 1.27 seconds
Started Mar 07 02:42:08 PM PST 24
Finished Mar 07 02:42:09 PM PST 24
Peak memory 215924 kb
Host smart-c62a34cf-5420-4b22-aa3a-93b6e26e99f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600882643 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.600882643
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.2930049291
Short name T291
Test name
Test status
Simulation time 210008856 ps
CPU time 2.55 seconds
Started Mar 07 02:42:06 PM PST 24
Finished Mar 07 02:42:08 PM PST 24
Peak memory 217264 kb
Host smart-2c7d17d2-b03d-4695-b6c3-e1102be62a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930049291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.2930049291
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.2148654128
Short name T646
Test name
Test status
Simulation time 39171527 ps
CPU time 1.38 seconds
Started Mar 07 02:42:10 PM PST 24
Finished Mar 07 02:42:12 PM PST 24
Peak memory 217116 kb
Host smart-c8e14902-8975-4202-883f-727a15774012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148654128 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.2148654128
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.1589497190
Short name T674
Test name
Test status
Simulation time 49363060 ps
CPU time 1.93 seconds
Started Mar 07 02:42:05 PM PST 24
Finished Mar 07 02:42:07 PM PST 24
Peak memory 218752 kb
Host smart-b8068b3b-3f9c-4544-8f37-4d4ada2b79f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589497190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.1589497190
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.3639662587
Short name T821
Test name
Test status
Simulation time 85617767 ps
CPU time 1.1 seconds
Started Mar 07 02:42:07 PM PST 24
Finished Mar 07 02:42:09 PM PST 24
Peak memory 215660 kb
Host smart-c3c23f7d-ea04-44dc-bfda-785c0748fd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639662587 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.3639662587
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.2220140993
Short name T103
Test name
Test status
Simulation time 36248307 ps
CPU time 1.13 seconds
Started Mar 07 02:39:38 PM PST 24
Finished Mar 07 02:39:39 PM PST 24
Peak memory 214768 kb
Host smart-a9934bd8-cf3b-4788-af81-279192833cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220140993 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.2220140993
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_alert_test.3637478970
Short name T407
Test name
Test status
Simulation time 18842836 ps
CPU time 0.88 seconds
Started Mar 07 02:39:37 PM PST 24
Finished Mar 07 02:39:39 PM PST 24
Peak memory 206116 kb
Host smart-2a527203-7cd8-437f-9ca7-b9ff730fbc5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637478970 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3637478970
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.2430705169
Short name T829
Test name
Test status
Simulation time 46014071 ps
CPU time 1.09 seconds
Started Mar 07 02:39:40 PM PST 24
Finished Mar 07 02:39:42 PM PST 24
Peak memory 215380 kb
Host smart-7e0ab65c-cc07-414a-9d90-8a39cccfd6d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430705169 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.2430705169
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/15.edn_err.2263188520
Short name T454
Test name
Test status
Simulation time 19618024 ps
CPU time 0.92 seconds
Started Mar 07 02:39:38 PM PST 24
Finished Mar 07 02:39:40 PM PST 24
Peak memory 216988 kb
Host smart-9e4200a5-655c-4ac2-b5c6-265ab786c26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263188520 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2263188520
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.3458750659
Short name T417
Test name
Test status
Simulation time 87822471 ps
CPU time 1.17 seconds
Started Mar 07 02:39:36 PM PST 24
Finished Mar 07 02:39:38 PM PST 24
Peak memory 215804 kb
Host smart-a891b72c-140b-48bd-b26d-0627825e45a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458750659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.3458750659
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_smoke.3678024823
Short name T823
Test name
Test status
Simulation time 32001391 ps
CPU time 0.84 seconds
Started Mar 07 02:39:37 PM PST 24
Finished Mar 07 02:39:38 PM PST 24
Peak memory 214416 kb
Host smart-e0f0218e-91ad-4618-906a-9ca6306bf4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678024823 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3678024823
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.58199904
Short name T312
Test name
Test status
Simulation time 61205742 ps
CPU time 0.98 seconds
Started Mar 07 02:39:40 PM PST 24
Finished Mar 07 02:39:42 PM PST 24
Peak memory 214476 kb
Host smart-efacb459-40f4-4898-b641-a316621e876e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58199904 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.58199904
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.2209860759
Short name T193
Test name
Test status
Simulation time 70016287581 ps
CPU time 1560.07 seconds
Started Mar 07 02:39:40 PM PST 24
Finished Mar 07 03:05:41 PM PST 24
Peak memory 221776 kb
Host smart-31b7591b-09c3-453e-b540-1a0079b24926
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209860759 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.2209860759
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.edn_genbits.3680253423
Short name T175
Test name
Test status
Simulation time 584450109 ps
CPU time 5.1 seconds
Started Mar 07 02:42:08 PM PST 24
Finished Mar 07 02:42:14 PM PST 24
Peak memory 215960 kb
Host smart-0b3ba9d4-8269-416d-9e6e-fa202c6d7409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680253423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.3680253423
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/152.edn_genbits.331342188
Short name T460
Test name
Test status
Simulation time 42974818 ps
CPU time 1.54 seconds
Started Mar 07 02:42:08 PM PST 24
Finished Mar 07 02:42:10 PM PST 24
Peak memory 216840 kb
Host smart-3856d8bf-d5c7-4724-b5f5-99ddf6024af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331342188 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.331342188
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.2280940532
Short name T806
Test name
Test status
Simulation time 45920488 ps
CPU time 1.37 seconds
Started Mar 07 02:42:07 PM PST 24
Finished Mar 07 02:42:09 PM PST 24
Peak memory 217240 kb
Host smart-340f3ec4-4159-42e6-aad3-6dfdf7843aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280940532 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.2280940532
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.3557841925
Short name T334
Test name
Test status
Simulation time 95597749 ps
CPU time 1.2 seconds
Started Mar 07 02:42:09 PM PST 24
Finished Mar 07 02:42:10 PM PST 24
Peak memory 215784 kb
Host smart-10b6b3c7-bad4-4e25-9428-cc54a27cf953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557841925 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.3557841925
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.2602354474
Short name T534
Test name
Test status
Simulation time 67832327 ps
CPU time 1.18 seconds
Started Mar 07 02:42:06 PM PST 24
Finished Mar 07 02:42:07 PM PST 24
Peak memory 215748 kb
Host smart-528c21cd-33b9-4fdf-af00-b4d64cedb894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602354474 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.2602354474
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.3820851709
Short name T457
Test name
Test status
Simulation time 45112168 ps
CPU time 1.88 seconds
Started Mar 07 02:42:09 PM PST 24
Finished Mar 07 02:42:12 PM PST 24
Peak memory 217088 kb
Host smart-c5dcc0fd-faaf-44dd-a6be-93f5ea85f4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820851709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3820851709
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.476458738
Short name T19
Test name
Test status
Simulation time 78882136 ps
CPU time 1.33 seconds
Started Mar 07 02:42:08 PM PST 24
Finished Mar 07 02:42:10 PM PST 24
Peak memory 216924 kb
Host smart-d93eb942-c0ce-4aba-b6f2-3f925af536fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476458738 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.476458738
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.2874347378
Short name T523
Test name
Test status
Simulation time 82412373 ps
CPU time 1.3 seconds
Started Mar 07 02:42:05 PM PST 24
Finished Mar 07 02:42:06 PM PST 24
Peak memory 215628 kb
Host smart-1ef2e189-b9a1-451a-9e57-eed2ec2e9cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874347378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.2874347378
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.3215131537
Short name T649
Test name
Test status
Simulation time 37412541 ps
CPU time 1.39 seconds
Started Mar 07 02:42:11 PM PST 24
Finished Mar 07 02:42:13 PM PST 24
Peak memory 215496 kb
Host smart-e0c735c3-74c0-4b85-b278-2bf2e923a023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215131537 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.3215131537
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.3332587682
Short name T254
Test name
Test status
Simulation time 45611508 ps
CPU time 1.17 seconds
Started Mar 07 02:39:39 PM PST 24
Finished Mar 07 02:39:41 PM PST 24
Peak memory 214776 kb
Host smart-331f8d1b-dc63-499a-b5c1-74922cfc1057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332587682 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.3332587682
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.1579895461
Short name T730
Test name
Test status
Simulation time 17176080 ps
CPU time 0.98 seconds
Started Mar 07 02:39:38 PM PST 24
Finished Mar 07 02:39:40 PM PST 24
Peak memory 206088 kb
Host smart-1f028a40-e293-49f8-92fd-142967638eda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579895461 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.1579895461
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable_auto_req_mode.1161520072
Short name T484
Test name
Test status
Simulation time 87284505 ps
CPU time 1 seconds
Started Mar 07 02:39:37 PM PST 24
Finished Mar 07 02:39:38 PM PST 24
Peak memory 215608 kb
Host smart-3e090e83-5517-43c6-a91e-cfbd399b5a85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161520072 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_d
isable_auto_req_mode.1161520072
Directory /workspace/16.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/16.edn_err.932378761
Short name T45
Test name
Test status
Simulation time 74375696 ps
CPU time 1.01 seconds
Started Mar 07 02:39:40 PM PST 24
Finished Mar 07 02:39:42 PM PST 24
Peak memory 228784 kb
Host smart-b33cee0a-d7ff-4470-a13f-ac8b8bac22b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932378761 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.932378761
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_genbits.43457679
Short name T622
Test name
Test status
Simulation time 48278638 ps
CPU time 1.17 seconds
Started Mar 07 02:39:39 PM PST 24
Finished Mar 07 02:39:41 PM PST 24
Peak memory 217272 kb
Host smart-e60357c0-088e-4776-8aed-120a48c44fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43457679 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.43457679
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_intr.3086668622
Short name T43
Test name
Test status
Simulation time 20839158 ps
CPU time 1.23 seconds
Started Mar 07 02:39:38 PM PST 24
Finished Mar 07 02:39:40 PM PST 24
Peak memory 222388 kb
Host smart-71b14b3d-e91f-463b-bfdf-9cb545244aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086668622 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.3086668622
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.4106105656
Short name T811
Test name
Test status
Simulation time 36425742 ps
CPU time 0.89 seconds
Started Mar 07 02:39:38 PM PST 24
Finished Mar 07 02:39:40 PM PST 24
Peak memory 206224 kb
Host smart-f7e4fe8c-71e9-4c6b-8e22-1c45744614b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106105656 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.4106105656
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.1166268977
Short name T636
Test name
Test status
Simulation time 554739362 ps
CPU time 4.3 seconds
Started Mar 07 02:39:39 PM PST 24
Finished Mar 07 02:39:44 PM PST 24
Peak memory 215524 kb
Host smart-8fd2cb08-0068-4d76-b173-0cbfca485f8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166268977 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.1166268977
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3817731570
Short name T421
Test name
Test status
Simulation time 21685926548 ps
CPU time 513.99 seconds
Started Mar 07 02:39:38 PM PST 24
Finished Mar 07 02:48:12 PM PST 24
Peak memory 222732 kb
Host smart-8d939b7b-adb8-4208-8d5e-2f8c1506b2b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817731570 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3817731570
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.2674062355
Short name T359
Test name
Test status
Simulation time 64049096 ps
CPU time 1.17 seconds
Started Mar 07 02:42:06 PM PST 24
Finished Mar 07 02:42:08 PM PST 24
Peak memory 215620 kb
Host smart-355a2cc9-a981-4436-9d1e-995718cace50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674062355 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.2674062355
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.2353803572
Short name T32
Test name
Test status
Simulation time 54224164 ps
CPU time 1.14 seconds
Started Mar 07 02:42:06 PM PST 24
Finished Mar 07 02:42:07 PM PST 24
Peak memory 215784 kb
Host smart-05b4ec5f-7caf-47ee-aaae-b7b074850258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353803572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2353803572
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/162.edn_genbits.1391820062
Short name T9
Test name
Test status
Simulation time 90320932 ps
CPU time 2.23 seconds
Started Mar 07 02:42:04 PM PST 24
Finished Mar 07 02:42:07 PM PST 24
Peak memory 216816 kb
Host smart-0f964175-7446-4dab-80f6-910f077ae172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391820062 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1391820062
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.1614315720
Short name T815
Test name
Test status
Simulation time 33419796 ps
CPU time 1.29 seconds
Started Mar 07 02:42:09 PM PST 24
Finished Mar 07 02:42:11 PM PST 24
Peak memory 215688 kb
Host smart-a558b131-1d81-4ed7-b73e-24e7f72f9fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614315720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.1614315720
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.337164381
Short name T305
Test name
Test status
Simulation time 44566596 ps
CPU time 1.38 seconds
Started Mar 07 02:42:13 PM PST 24
Finished Mar 07 02:42:16 PM PST 24
Peak memory 216748 kb
Host smart-d295d32b-a61b-4b20-8473-81d3110ffe7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337164381 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.337164381
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/165.edn_genbits.2286674710
Short name T506
Test name
Test status
Simulation time 72107540 ps
CPU time 1.04 seconds
Started Mar 07 02:42:06 PM PST 24
Finished Mar 07 02:42:07 PM PST 24
Peak memory 215468 kb
Host smart-0f9e2df4-9daa-4843-a510-345d30ad596c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286674710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.2286674710
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.2797438370
Short name T532
Test name
Test status
Simulation time 93257175 ps
CPU time 1.44 seconds
Started Mar 07 02:42:13 PM PST 24
Finished Mar 07 02:42:16 PM PST 24
Peak memory 217096 kb
Host smart-17b34f3a-8a93-49e4-8d13-ced08c510d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797438370 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.2797438370
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.3253378185
Short name T698
Test name
Test status
Simulation time 46927143 ps
CPU time 1.66 seconds
Started Mar 07 02:42:05 PM PST 24
Finished Mar 07 02:42:07 PM PST 24
Peak memory 216792 kb
Host smart-6836009a-6d54-4355-a367-3f0d2d7b0329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253378185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3253378185
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.1095157122
Short name T330
Test name
Test status
Simulation time 22241388 ps
CPU time 1.13 seconds
Started Mar 07 02:42:13 PM PST 24
Finished Mar 07 02:42:15 PM PST 24
Peak memory 215544 kb
Host smart-2c9295a3-b197-4479-9bd0-0f8310ea10e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095157122 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.1095157122
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.564270805
Short name T756
Test name
Test status
Simulation time 43073927 ps
CPU time 1.39 seconds
Started Mar 07 02:42:11 PM PST 24
Finished Mar 07 02:42:13 PM PST 24
Peak memory 216832 kb
Host smart-32b8b5b1-5b09-49d8-9ec0-2a5cfe588fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564270805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.564270805
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.2993193030
Short name T688
Test name
Test status
Simulation time 25248331 ps
CPU time 1.2 seconds
Started Mar 07 02:39:47 PM PST 24
Finished Mar 07 02:39:49 PM PST 24
Peak memory 214868 kb
Host smart-854677f7-8c7a-4678-9d20-0a3b6e379142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993193030 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.2993193030
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.2202425866
Short name T368
Test name
Test status
Simulation time 15677740 ps
CPU time 0.95 seconds
Started Mar 07 02:39:49 PM PST 24
Finished Mar 07 02:39:51 PM PST 24
Peak memory 206068 kb
Host smart-53ed2865-0db2-4d2b-96a3-ddd8cd01d3c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202425866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.2202425866
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.3081394102
Short name T118
Test name
Test status
Simulation time 13810351 ps
CPU time 0.96 seconds
Started Mar 07 02:39:52 PM PST 24
Finished Mar 07 02:39:53 PM PST 24
Peak memory 215068 kb
Host smart-5498f3bd-3710-47a8-8d8f-f2cca327ae37
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081394102 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.3081394102
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_err.547893580
Short name T97
Test name
Test status
Simulation time 21581416 ps
CPU time 1.09 seconds
Started Mar 07 02:39:48 PM PST 24
Finished Mar 07 02:39:49 PM PST 24
Peak memory 230540 kb
Host smart-87e47c39-34fb-4191-a78c-8a1cdcfc4a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547893580 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.547893580
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2976306396
Short name T419
Test name
Test status
Simulation time 51284662 ps
CPU time 1.14 seconds
Started Mar 07 02:39:46 PM PST 24
Finished Mar 07 02:39:48 PM PST 24
Peak memory 216956 kb
Host smart-e6d7f924-6cf4-41bf-81e9-61e654ceb9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976306396 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2976306396
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.361808099
Short name T712
Test name
Test status
Simulation time 36213886 ps
CPU time 0.97 seconds
Started Mar 07 02:39:47 PM PST 24
Finished Mar 07 02:39:48 PM PST 24
Peak memory 223148 kb
Host smart-74f2976a-7364-4366-a4ae-0ae71a2e8370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361808099 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.361808099
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.3043642802
Short name T46
Test name
Test status
Simulation time 41460971 ps
CPU time 0.89 seconds
Started Mar 07 02:39:42 PM PST 24
Finished Mar 07 02:39:44 PM PST 24
Peak memory 214352 kb
Host smart-adaa106f-effa-4ae7-9f29-9c4ca1edc289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043642802 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.3043642802
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.103243426
Short name T733
Test name
Test status
Simulation time 77267726 ps
CPU time 1.98 seconds
Started Mar 07 02:39:48 PM PST 24
Finished Mar 07 02:39:50 PM PST 24
Peak memory 215548 kb
Host smart-7ffb6cf7-0e88-4bb2-958a-a58bd248fabb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103243426 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.103243426
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3012729890
Short name T23
Test name
Test status
Simulation time 61363756539 ps
CPU time 744.19 seconds
Started Mar 07 02:39:47 PM PST 24
Finished Mar 07 02:52:11 PM PST 24
Peak memory 218308 kb
Host smart-2c1ee551-a5d5-48f6-9b96-d707a59f7bec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012729890 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3012729890
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.753499785
Short name T383
Test name
Test status
Simulation time 90056643 ps
CPU time 2.57 seconds
Started Mar 07 02:42:06 PM PST 24
Finished Mar 07 02:42:09 PM PST 24
Peak memory 216924 kb
Host smart-5e0823a3-c2f6-4ebe-99ae-f9f4a9147e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753499785 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.753499785
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.2235012461
Short name T465
Test name
Test status
Simulation time 78695061 ps
CPU time 1.26 seconds
Started Mar 07 02:42:17 PM PST 24
Finished Mar 07 02:42:19 PM PST 24
Peak memory 217260 kb
Host smart-6b06e42b-0259-4c5b-b5aa-17370d17ac8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235012461 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.2235012461
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.3031619603
Short name T373
Test name
Test status
Simulation time 74111510 ps
CPU time 1.4 seconds
Started Mar 07 02:42:16 PM PST 24
Finished Mar 07 02:42:18 PM PST 24
Peak memory 217104 kb
Host smart-0eec0799-0bc3-475d-bfb2-86c7c0fd3ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031619603 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.3031619603
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.3064296768
Short name T445
Test name
Test status
Simulation time 77951820 ps
CPU time 1.21 seconds
Started Mar 07 02:42:20 PM PST 24
Finished Mar 07 02:42:21 PM PST 24
Peak memory 215520 kb
Host smart-a21da3e9-96c7-40eb-9ac8-c166d2c1c6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064296768 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.3064296768
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.247299658
Short name T783
Test name
Test status
Simulation time 30676071 ps
CPU time 1.22 seconds
Started Mar 07 02:42:19 PM PST 24
Finished Mar 07 02:42:20 PM PST 24
Peak memory 215464 kb
Host smart-c94de714-bd0f-4318-afe5-49afa1b2d723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247299658 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.247299658
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.2045920605
Short name T607
Test name
Test status
Simulation time 95048295 ps
CPU time 1.13 seconds
Started Mar 07 02:42:17 PM PST 24
Finished Mar 07 02:42:18 PM PST 24
Peak memory 215628 kb
Host smart-14e63b28-02dd-48af-8c20-3c4cd8a741b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045920605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.2045920605
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.2824291411
Short name T722
Test name
Test status
Simulation time 91322041 ps
CPU time 2.57 seconds
Started Mar 07 02:42:19 PM PST 24
Finished Mar 07 02:42:22 PM PST 24
Peak memory 218228 kb
Host smart-f6c92184-1deb-4a3e-bcc4-2a2887a04ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824291411 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.2824291411
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.3276634595
Short name T321
Test name
Test status
Simulation time 35758024 ps
CPU time 1.52 seconds
Started Mar 07 02:42:18 PM PST 24
Finished Mar 07 02:42:20 PM PST 24
Peak memory 216932 kb
Host smart-e9c036b1-2314-4f98-b9e0-b431dfecc3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276634595 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3276634595
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1545068060
Short name T13
Test name
Test status
Simulation time 29123692 ps
CPU time 1.17 seconds
Started Mar 07 02:39:47 PM PST 24
Finished Mar 07 02:39:49 PM PST 24
Peak memory 214752 kb
Host smart-c0fd956b-851d-43e1-a0ca-de87eca5d5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545068060 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1545068060
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.3887815380
Short name T719
Test name
Test status
Simulation time 29789834 ps
CPU time 0.97 seconds
Started Mar 07 02:39:47 PM PST 24
Finished Mar 07 02:39:49 PM PST 24
Peak memory 205728 kb
Host smart-99fb77a0-55f6-4f5c-8912-912703dfbb53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887815380 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.3887815380
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.2936101124
Short name T20
Test name
Test status
Simulation time 17957665 ps
CPU time 0.87 seconds
Started Mar 07 02:39:54 PM PST 24
Finished Mar 07 02:39:55 PM PST 24
Peak memory 214652 kb
Host smart-fc01c4fb-cf24-4579-a402-73187905a490
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936101124 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.2936101124
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.876397028
Short name T79
Test name
Test status
Simulation time 74913830 ps
CPU time 1.2 seconds
Started Mar 07 02:39:50 PM PST 24
Finished Mar 07 02:39:52 PM PST 24
Peak memory 215636 kb
Host smart-fbb78080-3ebf-4652-a5c9-d75fac18aaaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876397028 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_di
sable_auto_req_mode.876397028
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.228798511
Short name T105
Test name
Test status
Simulation time 18125508 ps
CPU time 1.12 seconds
Started Mar 07 02:39:54 PM PST 24
Finished Mar 07 02:39:56 PM PST 24
Peak memory 222344 kb
Host smart-062253b9-34b7-46c2-bfd0-33e917bc4be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228798511 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.228798511
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.691650720
Short name T398
Test name
Test status
Simulation time 52909083 ps
CPU time 1.59 seconds
Started Mar 07 02:39:49 PM PST 24
Finished Mar 07 02:39:51 PM PST 24
Peak memory 216752 kb
Host smart-01f10a07-23f9-4037-a2f7-0010a276dd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691650720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.691650720
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_smoke.191729355
Short name T336
Test name
Test status
Simulation time 44641760 ps
CPU time 0.87 seconds
Started Mar 07 02:39:46 PM PST 24
Finished Mar 07 02:39:47 PM PST 24
Peak memory 214368 kb
Host smart-a332c5ac-816b-4901-bbcd-78b1a742762f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191729355 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.191729355
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.3886964437
Short name T614
Test name
Test status
Simulation time 196784689 ps
CPU time 4.34 seconds
Started Mar 07 02:39:48 PM PST 24
Finished Mar 07 02:39:52 PM PST 24
Peak memory 214376 kb
Host smart-614ea7d2-b61f-4057-808d-7d115b16045d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886964437 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.3886964437
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.956906065
Short name T325
Test name
Test status
Simulation time 138448479508 ps
CPU time 997.75 seconds
Started Mar 07 02:39:52 PM PST 24
Finished Mar 07 02:56:30 PM PST 24
Peak memory 222844 kb
Host smart-dd9db83f-c844-41f9-a244-6395bd4e81d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956906065 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.956906065
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.2652546944
Short name T284
Test name
Test status
Simulation time 105062370 ps
CPU time 1.53 seconds
Started Mar 07 02:42:19 PM PST 24
Finished Mar 07 02:42:21 PM PST 24
Peak memory 217184 kb
Host smart-219f1e49-f934-4563-9ade-3374b6153994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652546944 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.2652546944
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.649595888
Short name T725
Test name
Test status
Simulation time 45859617 ps
CPU time 1.47 seconds
Started Mar 07 02:42:18 PM PST 24
Finished Mar 07 02:42:20 PM PST 24
Peak memory 216736 kb
Host smart-74a939f7-bed4-4809-b0d5-dd99f0de8346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649595888 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.649595888
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.2749012508
Short name T314
Test name
Test status
Simulation time 64731560 ps
CPU time 1.36 seconds
Started Mar 07 02:42:24 PM PST 24
Finished Mar 07 02:42:25 PM PST 24
Peak memory 217116 kb
Host smart-30689fbe-ea10-4e90-82be-220ebbc60ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749012508 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.2749012508
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.1018993968
Short name T199
Test name
Test status
Simulation time 73667912 ps
CPU time 1.19 seconds
Started Mar 07 02:42:17 PM PST 24
Finished Mar 07 02:42:19 PM PST 24
Peak memory 214424 kb
Host smart-37dd9ea7-dcf8-46d5-bce8-16fc20ad9216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018993968 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.1018993968
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.2837336202
Short name T677
Test name
Test status
Simulation time 48183217 ps
CPU time 1 seconds
Started Mar 07 02:42:16 PM PST 24
Finished Mar 07 02:42:17 PM PST 24
Peak memory 215764 kb
Host smart-36882728-dda7-4cef-8558-09055ad0394d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837336202 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.2837336202
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.203666544
Short name T486
Test name
Test status
Simulation time 43626050 ps
CPU time 1.66 seconds
Started Mar 07 02:42:19 PM PST 24
Finished Mar 07 02:42:21 PM PST 24
Peak memory 215868 kb
Host smart-03407070-f650-40fd-9a8c-201885c0aabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203666544 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.203666544
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.1446724134
Short name T728
Test name
Test status
Simulation time 39785439 ps
CPU time 1.05 seconds
Started Mar 07 02:42:19 PM PST 24
Finished Mar 07 02:42:20 PM PST 24
Peak memory 215572 kb
Host smart-b5472de3-2112-42e6-b4f0-cdd3a17a996e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446724134 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.1446724134
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.391052048
Short name T269
Test name
Test status
Simulation time 40006361 ps
CPU time 1.15 seconds
Started Mar 07 02:42:18 PM PST 24
Finished Mar 07 02:42:19 PM PST 24
Peak memory 216912 kb
Host smart-5288dc91-ca5a-4818-a113-24392b641efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391052048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.391052048
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.3146970409
Short name T774
Test name
Test status
Simulation time 49606643 ps
CPU time 1.24 seconds
Started Mar 07 02:42:20 PM PST 24
Finished Mar 07 02:42:21 PM PST 24
Peak memory 215708 kb
Host smart-b05856c4-0c6e-4c73-a860-bba2bdd23d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146970409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.3146970409
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.2411870199
Short name T397
Test name
Test status
Simulation time 46348751 ps
CPU time 1.23 seconds
Started Mar 07 02:42:19 PM PST 24
Finished Mar 07 02:42:20 PM PST 24
Peak memory 217744 kb
Host smart-b1d94863-1b07-4207-85b0-448aef9185dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411870199 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.2411870199
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.1024223710
Short name T745
Test name
Test status
Simulation time 98645273 ps
CPU time 1.08 seconds
Started Mar 07 02:39:52 PM PST 24
Finished Mar 07 02:39:53 PM PST 24
Peak memory 214832 kb
Host smart-ba24a21d-f95c-441b-be83-65f1a0976122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024223710 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.1024223710
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.2066789193
Short name T146
Test name
Test status
Simulation time 54972640 ps
CPU time 1.01 seconds
Started Mar 07 02:39:49 PM PST 24
Finished Mar 07 02:39:51 PM PST 24
Peak memory 205844 kb
Host smart-d90b83ee-bcac-4945-8a01-ea4bcc4cc555
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066789193 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.2066789193
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_err.3119842173
Short name T406
Test name
Test status
Simulation time 20652554 ps
CPU time 1.08 seconds
Started Mar 07 02:39:52 PM PST 24
Finished Mar 07 02:39:53 PM PST 24
Peak memory 222244 kb
Host smart-79104d67-5f3b-4551-965f-aa8ceccce89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119842173 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.3119842173
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3845189216
Short name T271
Test name
Test status
Simulation time 55261489 ps
CPU time 1.19 seconds
Started Mar 07 02:39:54 PM PST 24
Finished Mar 07 02:39:56 PM PST 24
Peak memory 216684 kb
Host smart-c378202c-c8c2-4c86-828b-e572c9589a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845189216 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3845189216
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3248350833
Short name T729
Test name
Test status
Simulation time 31951250 ps
CPU time 0.86 seconds
Started Mar 07 02:39:50 PM PST 24
Finished Mar 07 02:39:51 PM PST 24
Peak memory 214552 kb
Host smart-98884062-25ee-4179-b3a2-e11b8ccf3819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248350833 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3248350833
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.3370723763
Short name T339
Test name
Test status
Simulation time 24276371 ps
CPU time 0.91 seconds
Started Mar 07 02:39:48 PM PST 24
Finished Mar 07 02:39:49 PM PST 24
Peak memory 214440 kb
Host smart-d654f780-ac1c-4c33-a556-e854f30975ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370723763 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.3370723763
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.2642427531
Short name T529
Test name
Test status
Simulation time 432396477 ps
CPU time 2.73 seconds
Started Mar 07 02:39:51 PM PST 24
Finished Mar 07 02:39:54 PM PST 24
Peak memory 215608 kb
Host smart-7edcbe4e-4560-4de9-94c7-8519bbbeb1db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642427531 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.2642427531
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3505742157
Short name T318
Test name
Test status
Simulation time 310112876131 ps
CPU time 1928.33 seconds
Started Mar 07 02:39:49 PM PST 24
Finished Mar 07 03:11:58 PM PST 24
Peak memory 224668 kb
Host smart-f16e248a-5817-4c29-8136-964735f50189
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505742157 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3505742157
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.475658042
Short name T331
Test name
Test status
Simulation time 59901283 ps
CPU time 1.57 seconds
Started Mar 07 02:42:19 PM PST 24
Finished Mar 07 02:42:21 PM PST 24
Peak memory 216700 kb
Host smart-7d39e946-96cb-433b-9ae5-71dadd2862e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475658042 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.475658042
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.2838238549
Short name T290
Test name
Test status
Simulation time 30587720 ps
CPU time 1.3 seconds
Started Mar 07 02:42:18 PM PST 24
Finished Mar 07 02:42:20 PM PST 24
Peak memory 218104 kb
Host smart-93c69e0a-9816-490d-9278-023c173192b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838238549 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.2838238549
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3056175735
Short name T640
Test name
Test status
Simulation time 475176794 ps
CPU time 1.26 seconds
Started Mar 07 02:42:22 PM PST 24
Finished Mar 07 02:42:24 PM PST 24
Peak memory 215716 kb
Host smart-5d5a458b-2688-4de9-bdfa-4ea6f6b66654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056175735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3056175735
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.57194111
Short name T578
Test name
Test status
Simulation time 33144232 ps
CPU time 1 seconds
Started Mar 07 02:42:19 PM PST 24
Finished Mar 07 02:42:20 PM PST 24
Peak memory 215724 kb
Host smart-bd0c7bac-4411-4f65-b80f-fbfbc73547e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57194111 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.57194111
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.950920026
Short name T410
Test name
Test status
Simulation time 83304677 ps
CPU time 1.13 seconds
Started Mar 07 02:42:18 PM PST 24
Finished Mar 07 02:42:20 PM PST 24
Peak memory 215924 kb
Host smart-214a748c-2b14-4696-aa38-e273fe4be884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950920026 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.950920026
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.4171900261
Short name T489
Test name
Test status
Simulation time 59843599 ps
CPU time 1.27 seconds
Started Mar 07 02:42:19 PM PST 24
Finished Mar 07 02:42:21 PM PST 24
Peak memory 216772 kb
Host smart-ef538345-7446-4055-b729-d3d886a8563e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171900261 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.4171900261
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.2132581379
Short name T673
Test name
Test status
Simulation time 246146801 ps
CPU time 1.48 seconds
Started Mar 07 02:42:18 PM PST 24
Finished Mar 07 02:42:20 PM PST 24
Peak memory 215816 kb
Host smart-d9925546-b2a1-4204-82cd-043983c19a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132581379 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.2132581379
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.3967015380
Short name T435
Test name
Test status
Simulation time 61972400 ps
CPU time 1.32 seconds
Started Mar 07 02:42:18 PM PST 24
Finished Mar 07 02:42:19 PM PST 24
Peak memory 216848 kb
Host smart-d9816230-ef0f-4f61-85a6-d4e844a97ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967015380 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.3967015380
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.174134836
Short name T264
Test name
Test status
Simulation time 46766846 ps
CPU time 1.19 seconds
Started Mar 07 02:38:43 PM PST 24
Finished Mar 07 02:38:45 PM PST 24
Peak memory 214772 kb
Host smart-9dd1bc40-f1ca-40b9-ac40-c55759464130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174134836 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.174134836
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.778090373
Short name T812
Test name
Test status
Simulation time 22107506 ps
CPU time 0.84 seconds
Started Mar 07 02:38:43 PM PST 24
Finished Mar 07 02:38:44 PM PST 24
Peak memory 206024 kb
Host smart-81d1fe2b-afb8-4308-8b95-449b5da7ead9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778090373 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.778090373
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable.4260368293
Short name T28
Test name
Test status
Simulation time 38682262 ps
CPU time 0.87 seconds
Started Mar 07 02:38:44 PM PST 24
Finished Mar 07 02:38:45 PM PST 24
Peak memory 214536 kb
Host smart-e19463e9-5ff5-48ac-85ea-7f6a5866e6d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260368293 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.4260368293
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/2.edn_err.1894861736
Short name T76
Test name
Test status
Simulation time 78758050 ps
CPU time 0.89 seconds
Started Mar 07 02:38:46 PM PST 24
Finished Mar 07 02:38:47 PM PST 24
Peak memory 218228 kb
Host smart-a3bff2b6-6006-4f9d-9808-017d8b0747df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894861736 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1894861736
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.2462296849
Short name T583
Test name
Test status
Simulation time 47394831 ps
CPU time 1.17 seconds
Started Mar 07 02:38:41 PM PST 24
Finished Mar 07 02:38:43 PM PST 24
Peak memory 215916 kb
Host smart-ed5c2b4a-d786-4637-87e6-0fdec5f8dc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462296849 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2462296849
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.3821362909
Short name T653
Test name
Test status
Simulation time 31404550 ps
CPU time 0.92 seconds
Started Mar 07 02:38:44 PM PST 24
Finished Mar 07 02:38:45 PM PST 24
Peak memory 214516 kb
Host smart-42091f36-24a9-4b51-b970-2f5143c48744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821362909 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.3821362909
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.1437198184
Short name T252
Test name
Test status
Simulation time 51980210 ps
CPU time 0.93 seconds
Started Mar 07 02:38:41 PM PST 24
Finished Mar 07 02:38:43 PM PST 24
Peak memory 206220 kb
Host smart-c51ba4c4-5aba-4922-bc1f-4036512954a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437198184 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.1437198184
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.2393928836
Short name T49
Test name
Test status
Simulation time 185198469 ps
CPU time 3.34 seconds
Started Mar 07 02:38:42 PM PST 24
Finished Mar 07 02:38:46 PM PST 24
Peak memory 234908 kb
Host smart-6c1cbb13-97c4-44d6-9d5c-6afbac0c37b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393928836 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.2393928836
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.146441909
Short name T790
Test name
Test status
Simulation time 26497107 ps
CPU time 1.1 seconds
Started Mar 07 02:38:43 PM PST 24
Finished Mar 07 02:38:44 PM PST 24
Peak memory 214428 kb
Host smart-dcc77456-3335-44a1-9700-4897d29f254d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146441909 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.146441909
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.35552236
Short name T138
Test name
Test status
Simulation time 497530129 ps
CPU time 5.44 seconds
Started Mar 07 02:38:47 PM PST 24
Finished Mar 07 02:38:52 PM PST 24
Peak memory 219108 kb
Host smart-d528c1cc-db85-4d21-997e-e48c4d189fb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35552236 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.35552236
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.545312340
Short name T317
Test name
Test status
Simulation time 70924420547 ps
CPU time 1812.43 seconds
Started Mar 07 02:38:46 PM PST 24
Finished Mar 07 03:08:58 PM PST 24
Peak memory 225704 kb
Host smart-bc743fb6-ef56-4661-b7dc-e66b8c8476d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545312340 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.545312340
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.2082824880
Short name T123
Test name
Test status
Simulation time 40527806 ps
CPU time 1.21 seconds
Started Mar 07 02:39:51 PM PST 24
Finished Mar 07 02:39:53 PM PST 24
Peak memory 214744 kb
Host smart-31177be5-c83b-48b6-9849-a032f15a56ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082824880 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.2082824880
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.1398278445
Short name T347
Test name
Test status
Simulation time 16650131 ps
CPU time 0.91 seconds
Started Mar 07 02:39:51 PM PST 24
Finished Mar 07 02:39:52 PM PST 24
Peak memory 205700 kb
Host smart-62c0638a-4164-4236-ab83-95fb1d47da66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398278445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.1398278445
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.43106737
Short name T696
Test name
Test status
Simulation time 23410110 ps
CPU time 0.88 seconds
Started Mar 07 02:39:51 PM PST 24
Finished Mar 07 02:39:52 PM PST 24
Peak memory 214548 kb
Host smart-91b27da7-09f6-49de-8cf3-b48e42e6a99c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43106737 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.43106737
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.1313551132
Short name T235
Test name
Test status
Simulation time 18023987 ps
CPU time 1.03 seconds
Started Mar 07 02:39:54 PM PST 24
Finished Mar 07 02:39:56 PM PST 24
Peak memory 216912 kb
Host smart-be3ff549-20eb-47e7-a6c3-4eed2f4cc7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313551132 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1313551132
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.3621672227
Short name T282
Test name
Test status
Simulation time 44669781 ps
CPU time 1.53 seconds
Started Mar 07 02:39:50 PM PST 24
Finished Mar 07 02:39:53 PM PST 24
Peak memory 217032 kb
Host smart-a4880955-0900-47d7-b4f2-17dfb74c405c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621672227 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.3621672227
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_smoke.463894538
Short name T434
Test name
Test status
Simulation time 26684851 ps
CPU time 1.03 seconds
Started Mar 07 02:39:49 PM PST 24
Finished Mar 07 02:39:51 PM PST 24
Peak memory 214416 kb
Host smart-2c0f63d1-fb8a-46d8-87fd-610fbd8558fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463894538 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.463894538
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2396306869
Short name T735
Test name
Test status
Simulation time 131259215 ps
CPU time 2.85 seconds
Started Mar 07 02:39:51 PM PST 24
Finished Mar 07 02:39:54 PM PST 24
Peak memory 215516 kb
Host smart-46be113e-9b53-41d9-b2fc-d6d4071e45cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396306869 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2396306869
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.2339637333
Short name T666
Test name
Test status
Simulation time 48314026296 ps
CPU time 571.7 seconds
Started Mar 07 02:39:54 PM PST 24
Finished Mar 07 02:49:26 PM PST 24
Peak memory 217328 kb
Host smart-afaee6d9-1df7-40a2-bd02-6e6908891003
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339637333 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.2339637333
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/202.edn_genbits.249190992
Short name T804
Test name
Test status
Simulation time 41258937 ps
CPU time 1.46 seconds
Started Mar 07 02:42:19 PM PST 24
Finished Mar 07 02:42:21 PM PST 24
Peak memory 216924 kb
Host smart-f368d429-fa4d-4cbc-9119-419f2ba443a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249190992 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.249190992
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.404397061
Short name T679
Test name
Test status
Simulation time 56127714 ps
CPU time 0.96 seconds
Started Mar 07 02:42:20 PM PST 24
Finished Mar 07 02:42:21 PM PST 24
Peak memory 215700 kb
Host smart-4fc7eb51-e798-4439-9fcc-89ca5999f250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404397061 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.404397061
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.3004090710
Short name T511
Test name
Test status
Simulation time 39663670 ps
CPU time 1.38 seconds
Started Mar 07 02:42:21 PM PST 24
Finished Mar 07 02:42:22 PM PST 24
Peak memory 216620 kb
Host smart-8ad9d2d9-a79f-4d02-98cd-d78210994fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004090710 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.3004090710
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.4267456916
Short name T651
Test name
Test status
Simulation time 41741700 ps
CPU time 1.48 seconds
Started Mar 07 02:42:20 PM PST 24
Finished Mar 07 02:42:21 PM PST 24
Peak memory 216828 kb
Host smart-61729d30-9679-49a8-8d9d-f35ea7e5f6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267456916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.4267456916
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.2812599775
Short name T545
Test name
Test status
Simulation time 87637906 ps
CPU time 1.04 seconds
Started Mar 07 02:42:20 PM PST 24
Finished Mar 07 02:42:21 PM PST 24
Peak memory 215696 kb
Host smart-1b6a800b-1062-490c-b3ef-4f0e255e8e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812599775 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.2812599775
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.3534973728
Short name T746
Test name
Test status
Simulation time 83927767 ps
CPU time 1.2 seconds
Started Mar 07 02:42:20 PM PST 24
Finished Mar 07 02:42:21 PM PST 24
Peak memory 217080 kb
Host smart-a2aa1da6-501d-4ef8-8137-11e0749d1090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534973728 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.3534973728
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.2348512787
Short name T374
Test name
Test status
Simulation time 180239734 ps
CPU time 0.95 seconds
Started Mar 07 02:42:22 PM PST 24
Finished Mar 07 02:42:23 PM PST 24
Peak memory 215508 kb
Host smart-185426f2-d59b-4188-a7e5-83d8e5617a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348512787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.2348512787
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.3627171855
Short name T813
Test name
Test status
Simulation time 26856240 ps
CPU time 1.27 seconds
Started Mar 07 02:39:55 PM PST 24
Finished Mar 07 02:39:57 PM PST 24
Peak memory 214856 kb
Host smart-a8da75da-2d29-4f3f-968b-6e6dd0af0012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627171855 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.3627171855
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.3445898832
Short name T546
Test name
Test status
Simulation time 56057892 ps
CPU time 0.9 seconds
Started Mar 07 02:39:59 PM PST 24
Finished Mar 07 02:40:01 PM PST 24
Peak memory 206112 kb
Host smart-c695bc39-abf6-4fc4-9c88-f5300caf7325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445898832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.3445898832
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.1919034149
Short name T165
Test name
Test status
Simulation time 12416318 ps
CPU time 0.86 seconds
Started Mar 07 02:39:55 PM PST 24
Finished Mar 07 02:39:56 PM PST 24
Peak memory 214668 kb
Host smart-5a1c3b68-4adb-473a-ad30-3696eb396023
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919034149 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.1919034149
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.2008626347
Short name T157
Test name
Test status
Simulation time 25445985 ps
CPU time 1.08 seconds
Started Mar 07 02:39:56 PM PST 24
Finished Mar 07 02:39:58 PM PST 24
Peak memory 215764 kb
Host smart-0f9e496b-1cb2-4a7a-bfdb-f3b9b91c54a0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008626347 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_d
isable_auto_req_mode.2008626347
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.1208544575
Short name T751
Test name
Test status
Simulation time 25304577 ps
CPU time 0.87 seconds
Started Mar 07 02:39:54 PM PST 24
Finished Mar 07 02:39:55 PM PST 24
Peak memory 216988 kb
Host smart-338f5ffb-6681-404b-8957-5a842a64a156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208544575 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.1208544575
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.1340478860
Short name T634
Test name
Test status
Simulation time 47247494 ps
CPU time 1.62 seconds
Started Mar 07 02:39:54 PM PST 24
Finished Mar 07 02:39:56 PM PST 24
Peak memory 218436 kb
Host smart-9c6cbbe5-01e2-4a10-acb3-ca0ad3007f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340478860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1340478860
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.689337216
Short name T452
Test name
Test status
Simulation time 28423009 ps
CPU time 1.07 seconds
Started Mar 07 02:39:59 PM PST 24
Finished Mar 07 02:40:01 PM PST 24
Peak memory 222344 kb
Host smart-d6f46800-5738-477e-902d-1de36e7349d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689337216 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.689337216
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.794311490
Short name T299
Test name
Test status
Simulation time 15846609 ps
CPU time 0.95 seconds
Started Mar 07 02:39:56 PM PST 24
Finished Mar 07 02:39:57 PM PST 24
Peak memory 214376 kb
Host smart-4674fb6a-95ed-40c2-a624-8d1cff253b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794311490 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.794311490
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.3012502735
Short name T455
Test name
Test status
Simulation time 446236944 ps
CPU time 2.11 seconds
Started Mar 07 02:39:56 PM PST 24
Finished Mar 07 02:39:58 PM PST 24
Peak memory 215708 kb
Host smart-da2962c3-6d99-4def-b284-bbb04e5aed32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012502735 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.3012502735
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.858206060
Short name T596
Test name
Test status
Simulation time 57183785637 ps
CPU time 359.65 seconds
Started Mar 07 02:39:54 PM PST 24
Finished Mar 07 02:45:54 PM PST 24
Peak memory 217688 kb
Host smart-de26b208-1f1a-4a4a-a2fe-dbfcbc2aae17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858206060 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.858206060
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.1428930193
Short name T603
Test name
Test status
Simulation time 88597734 ps
CPU time 1.11 seconds
Started Mar 07 02:42:24 PM PST 24
Finished Mar 07 02:42:25 PM PST 24
Peak memory 216940 kb
Host smart-e7de362b-e424-459e-814d-30981c0837e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428930193 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.1428930193
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.292450512
Short name T303
Test name
Test status
Simulation time 61779412 ps
CPU time 1.32 seconds
Started Mar 07 02:42:20 PM PST 24
Finished Mar 07 02:42:21 PM PST 24
Peak memory 218276 kb
Host smart-95d0fa1f-9c05-4446-a403-ea5e786485d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292450512 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.292450512
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.3986189618
Short name T810
Test name
Test status
Simulation time 44465081 ps
CPU time 1.13 seconds
Started Mar 07 02:42:19 PM PST 24
Finished Mar 07 02:42:20 PM PST 24
Peak memory 216972 kb
Host smart-7ebbbc88-2321-4805-9f7f-5f66ebf02f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986189618 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.3986189618
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3241652724
Short name T469
Test name
Test status
Simulation time 51123236 ps
CPU time 1.21 seconds
Started Mar 07 02:42:28 PM PST 24
Finished Mar 07 02:42:29 PM PST 24
Peak memory 215716 kb
Host smart-1288cab5-6fde-4f74-a107-3723a2b3e06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241652724 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3241652724
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.3743908393
Short name T367
Test name
Test status
Simulation time 42837636 ps
CPU time 1.47 seconds
Started Mar 07 02:42:40 PM PST 24
Finished Mar 07 02:42:42 PM PST 24
Peak memory 216432 kb
Host smart-9a03815a-1af6-485d-b8a3-45f8cdf9c080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743908393 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.3743908393
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.1228582526
Short name T589
Test name
Test status
Simulation time 138407658 ps
CPU time 1.29 seconds
Started Mar 07 02:42:40 PM PST 24
Finished Mar 07 02:42:41 PM PST 24
Peak memory 217320 kb
Host smart-87e1af3e-20d6-43ec-a700-e436c1a40ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228582526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.1228582526
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2370093313
Short name T428
Test name
Test status
Simulation time 61193663 ps
CPU time 1.36 seconds
Started Mar 07 02:42:32 PM PST 24
Finished Mar 07 02:42:34 PM PST 24
Peak memory 218304 kb
Host smart-dfd3e4bd-6ad3-45f7-ba0d-8b3acb1c766c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370093313 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2370093313
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.2131134112
Short name T272
Test name
Test status
Simulation time 112381951 ps
CPU time 0.94 seconds
Started Mar 07 02:42:28 PM PST 24
Finished Mar 07 02:42:29 PM PST 24
Peak memory 214424 kb
Host smart-f22c89fd-1c5f-4572-bcc7-8160673c53ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131134112 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.2131134112
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.4073582445
Short name T342
Test name
Test status
Simulation time 84317719 ps
CPU time 1.27 seconds
Started Mar 07 02:42:29 PM PST 24
Finished Mar 07 02:42:30 PM PST 24
Peak memory 217404 kb
Host smart-7e6f70b9-9f5f-4f57-856b-c90034eca45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073582445 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.4073582445
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/219.edn_genbits.1686889021
Short name T731
Test name
Test status
Simulation time 48279786 ps
CPU time 1.16 seconds
Started Mar 07 02:42:29 PM PST 24
Finished Mar 07 02:42:31 PM PST 24
Peak memory 215612 kb
Host smart-cc31c068-0961-4ab5-bb28-6010782d3514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686889021 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.1686889021
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.698105915
Short name T678
Test name
Test status
Simulation time 67174709 ps
CPU time 1.13 seconds
Started Mar 07 02:39:55 PM PST 24
Finished Mar 07 02:39:56 PM PST 24
Peak memory 214768 kb
Host smart-cf8723f6-e6dc-4b4b-b1e2-9e351faba67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698105915 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.698105915
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.2655095671
Short name T652
Test name
Test status
Simulation time 21561946 ps
CPU time 1.02 seconds
Started Mar 07 02:40:03 PM PST 24
Finished Mar 07 02:40:04 PM PST 24
Peak memory 206108 kb
Host smart-45041169-45df-497c-a185-9ef01ccc1371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655095671 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.2655095671
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3672026555
Short name T121
Test name
Test status
Simulation time 10796205 ps
CPU time 0.88 seconds
Started Mar 07 02:40:07 PM PST 24
Finished Mar 07 02:40:09 PM PST 24
Peak memory 214932 kb
Host smart-e28d106b-26cc-41d1-b8f3-f0c338e4d826
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672026555 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3672026555
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.208587309
Short name T78
Test name
Test status
Simulation time 35465329 ps
CPU time 1.22 seconds
Started Mar 07 02:40:04 PM PST 24
Finished Mar 07 02:40:05 PM PST 24
Peak memory 216976 kb
Host smart-9960e8c0-1c00-4966-af8a-07d112e34a6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208587309 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_di
sable_auto_req_mode.208587309
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_err.3676888293
Short name T655
Test name
Test status
Simulation time 29909827 ps
CPU time 0.89 seconds
Started Mar 07 02:40:03 PM PST 24
Finished Mar 07 02:40:04 PM PST 24
Peak memory 216992 kb
Host smart-878ce059-6a82-45a6-a2a2-cd8ce6f5ce4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676888293 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3676888293
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/default/22.edn_genbits.1303981270
Short name T323
Test name
Test status
Simulation time 135474972 ps
CPU time 2.94 seconds
Started Mar 07 02:39:57 PM PST 24
Finished Mar 07 02:40:00 PM PST 24
Peak memory 215976 kb
Host smart-2e5ada38-6afe-45b3-9de1-0c8d019baf76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303981270 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1303981270
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_intr.15309002
Short name T466
Test name
Test status
Simulation time 31206059 ps
CPU time 0.84 seconds
Started Mar 07 02:39:56 PM PST 24
Finished Mar 07 02:39:57 PM PST 24
Peak memory 214756 kb
Host smart-22665463-c0e7-4688-b9bb-2fd5153dab2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15309002 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.15309002
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/22.edn_smoke.3076068053
Short name T189
Test name
Test status
Simulation time 15962264 ps
CPU time 0.99 seconds
Started Mar 07 02:39:55 PM PST 24
Finished Mar 07 02:39:56 PM PST 24
Peak memory 214448 kb
Host smart-6ed60931-2253-42e4-ad42-39a209abe3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076068053 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.3076068053
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.1582117265
Short name T483
Test name
Test status
Simulation time 55211701 ps
CPU time 1.61 seconds
Started Mar 07 02:39:59 PM PST 24
Finished Mar 07 02:40:02 PM PST 24
Peak memory 215548 kb
Host smart-49c3e11f-112c-411d-a307-c15b61a0e23d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582117265 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.1582117265
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.3302507929
Short name T447
Test name
Test status
Simulation time 54093351097 ps
CPU time 365.59 seconds
Started Mar 07 02:39:56 PM PST 24
Finished Mar 07 02:46:02 PM PST 24
Peak memory 216668 kb
Host smart-f7b7159e-9893-44df-a734-4313e83b949d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302507929 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.3302507929
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.3156688818
Short name T492
Test name
Test status
Simulation time 33920023 ps
CPU time 1.57 seconds
Started Mar 07 02:42:32 PM PST 24
Finished Mar 07 02:42:33 PM PST 24
Peak memory 216888 kb
Host smart-6082fef1-a629-45ce-84b7-f43d6b02d2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156688818 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.3156688818
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.1273437181
Short name T362
Test name
Test status
Simulation time 44252023 ps
CPU time 0.99 seconds
Started Mar 07 02:42:34 PM PST 24
Finished Mar 07 02:42:35 PM PST 24
Peak memory 215908 kb
Host smart-8529919a-99cd-41b5-8255-0e7f0d9dcebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273437181 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.1273437181
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.3345957382
Short name T585
Test name
Test status
Simulation time 70686216 ps
CPU time 1.28 seconds
Started Mar 07 02:42:34 PM PST 24
Finished Mar 07 02:42:36 PM PST 24
Peak memory 216772 kb
Host smart-392a5861-c5a4-4eca-bdec-733e0f8f5284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345957382 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.3345957382
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.4154393960
Short name T375
Test name
Test status
Simulation time 83298851 ps
CPU time 1.1 seconds
Started Mar 07 02:42:30 PM PST 24
Finished Mar 07 02:42:31 PM PST 24
Peak memory 215676 kb
Host smart-704c6cf0-595f-4dd0-bf9a-168d66c2b32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154393960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.4154393960
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.2466141970
Short name T502
Test name
Test status
Simulation time 28284253 ps
CPU time 1.29 seconds
Started Mar 07 02:42:29 PM PST 24
Finished Mar 07 02:42:30 PM PST 24
Peak memory 218468 kb
Host smart-6e25c00a-f6b0-403e-986b-8e8436ccfcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466141970 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.2466141970
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.376029094
Short name T787
Test name
Test status
Simulation time 181608774 ps
CPU time 2.26 seconds
Started Mar 07 02:42:29 PM PST 24
Finished Mar 07 02:42:31 PM PST 24
Peak memory 216136 kb
Host smart-d6a01a45-22d9-41a2-9fd3-446ca6d64be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376029094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.376029094
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.2944205207
Short name T686
Test name
Test status
Simulation time 51165799 ps
CPU time 1.16 seconds
Started Mar 07 02:42:34 PM PST 24
Finished Mar 07 02:42:36 PM PST 24
Peak memory 215684 kb
Host smart-2e52864f-fe96-46ee-b10c-a84a000764ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944205207 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.2944205207
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.642125869
Short name T448
Test name
Test status
Simulation time 84574878 ps
CPU time 2.92 seconds
Started Mar 07 02:42:32 PM PST 24
Finished Mar 07 02:42:35 PM PST 24
Peak memory 217000 kb
Host smart-a304ebf6-e5bb-4c0d-a5c4-f6ee1a6340a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642125869 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.642125869
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.3787159572
Short name T645
Test name
Test status
Simulation time 87544332 ps
CPU time 1.14 seconds
Started Mar 07 02:42:34 PM PST 24
Finished Mar 07 02:42:35 PM PST 24
Peak memory 216684 kb
Host smart-5fea3263-da56-4004-936d-5c819afa9ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787159572 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.3787159572
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.3108479208
Short name T423
Test name
Test status
Simulation time 57684951 ps
CPU time 1.16 seconds
Started Mar 07 02:42:29 PM PST 24
Finished Mar 07 02:42:30 PM PST 24
Peak memory 218456 kb
Host smart-4b005a6a-13e9-4aa1-b3c4-ad468b3fefb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108479208 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.3108479208
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.1997626547
Short name T64
Test name
Test status
Simulation time 75625594 ps
CPU time 1.18 seconds
Started Mar 07 02:40:03 PM PST 24
Finished Mar 07 02:40:04 PM PST 24
Peak memory 214776 kb
Host smart-b02e94b0-c2a8-4644-b9a0-aa25ec3c7c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997626547 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.1997626547
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.266391978
Short name T549
Test name
Test status
Simulation time 24297890 ps
CPU time 0.93 seconds
Started Mar 07 02:40:10 PM PST 24
Finished Mar 07 02:40:11 PM PST 24
Peak memory 205792 kb
Host smart-c4d2bd3d-4dc1-4280-8f6b-abc4ffffeb2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266391978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.266391978
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.3863856810
Short name T552
Test name
Test status
Simulation time 10791710 ps
CPU time 0.84 seconds
Started Mar 07 02:40:03 PM PST 24
Finished Mar 07 02:40:04 PM PST 24
Peak memory 215044 kb
Host smart-b17811b3-4580-4e4e-bb47-4b59d7b011d1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863856810 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.3863856810
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.4037772882
Short name T577
Test name
Test status
Simulation time 22534431 ps
CPU time 0.93 seconds
Started Mar 07 02:40:03 PM PST 24
Finished Mar 07 02:40:05 PM PST 24
Peak memory 217068 kb
Host smart-06452ae5-dcf3-4e23-a31d-e95900936f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037772882 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.4037772882
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.2465146515
Short name T345
Test name
Test status
Simulation time 84753624 ps
CPU time 1.48 seconds
Started Mar 07 02:40:04 PM PST 24
Finished Mar 07 02:40:06 PM PST 24
Peak memory 215820 kb
Host smart-f8862ef0-26f1-443d-b0e5-1b08f0df8f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465146515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.2465146515
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.1891727653
Short name T405
Test name
Test status
Simulation time 26874951 ps
CPU time 0.93 seconds
Started Mar 07 02:40:03 PM PST 24
Finished Mar 07 02:40:05 PM PST 24
Peak memory 214668 kb
Host smart-18cb49c2-ab13-47df-b41d-845708b67585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891727653 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.1891727653
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.648455532
Short name T620
Test name
Test status
Simulation time 25456129 ps
CPU time 0.93 seconds
Started Mar 07 02:40:07 PM PST 24
Finished Mar 07 02:40:08 PM PST 24
Peak memory 214440 kb
Host smart-d17ccc2b-9a4e-45a2-b88a-ebe00c481595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648455532 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.648455532
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.2084794368
Short name T573
Test name
Test status
Simulation time 369025391 ps
CPU time 6.96 seconds
Started Mar 07 02:40:03 PM PST 24
Finished Mar 07 02:40:10 PM PST 24
Peak memory 214420 kb
Host smart-6d5c88d7-a1fe-415e-9aaa-7b52454e643d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084794368 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.2084794368
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2648768911
Short name T801
Test name
Test status
Simulation time 8559911094 ps
CPU time 89.97 seconds
Started Mar 07 02:40:02 PM PST 24
Finished Mar 07 02:41:32 PM PST 24
Peak memory 216852 kb
Host smart-49d43d11-25ce-4739-bc65-4943bbb737aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648768911 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2648768911
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.346716669
Short name T378
Test name
Test status
Simulation time 114908123 ps
CPU time 3.02 seconds
Started Mar 07 02:42:32 PM PST 24
Finished Mar 07 02:42:35 PM PST 24
Peak memory 215848 kb
Host smart-e7aa6f1e-6836-4b30-9397-121366f333fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346716669 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.346716669
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.2632335729
Short name T26
Test name
Test status
Simulation time 56799711 ps
CPU time 1.26 seconds
Started Mar 07 02:42:28 PM PST 24
Finished Mar 07 02:42:30 PM PST 24
Peak memory 216828 kb
Host smart-2580c080-0d45-47ec-9cbd-f798a9bfe5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632335729 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.2632335729
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.3675273594
Short name T687
Test name
Test status
Simulation time 78075641 ps
CPU time 1.13 seconds
Started Mar 07 02:42:35 PM PST 24
Finished Mar 07 02:42:37 PM PST 24
Peak memory 214476 kb
Host smart-56bd6174-5b8c-4b1f-a0eb-398e5c0863f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675273594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.3675273594
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.853085017
Short name T838
Test name
Test status
Simulation time 204528779 ps
CPU time 1.1 seconds
Started Mar 07 02:42:37 PM PST 24
Finished Mar 07 02:42:38 PM PST 24
Peak memory 215812 kb
Host smart-4f48ec13-b408-422b-9850-a787c1dd5e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853085017 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.853085017
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.515131403
Short name T296
Test name
Test status
Simulation time 89169677 ps
CPU time 1.88 seconds
Started Mar 07 02:42:35 PM PST 24
Finished Mar 07 02:42:38 PM PST 24
Peak memory 218572 kb
Host smart-bb34eea9-ca8d-4b9b-99d7-2099722a3590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515131403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.515131403
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.1245410911
Short name T307
Test name
Test status
Simulation time 47340486 ps
CPU time 1.69 seconds
Started Mar 07 02:42:31 PM PST 24
Finished Mar 07 02:42:33 PM PST 24
Peak memory 216892 kb
Host smart-2dc393e0-981c-45d5-a6e2-9540e05ada4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245410911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.1245410911
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.1314648330
Short name T358
Test name
Test status
Simulation time 35932200 ps
CPU time 1.36 seconds
Started Mar 07 02:42:32 PM PST 24
Finished Mar 07 02:42:33 PM PST 24
Peak memory 217676 kb
Host smart-beed83fc-2609-474a-ab49-07848395decf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314648330 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.1314648330
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.762808073
Short name T266
Test name
Test status
Simulation time 54136066 ps
CPU time 1.49 seconds
Started Mar 07 02:42:36 PM PST 24
Finished Mar 07 02:42:37 PM PST 24
Peak memory 217132 kb
Host smart-cc1775b6-7995-4115-a686-5126d7995951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762808073 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.762808073
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2762549800
Short name T702
Test name
Test status
Simulation time 150349305 ps
CPU time 3.21 seconds
Started Mar 07 02:42:34 PM PST 24
Finished Mar 07 02:42:38 PM PST 24
Peak memory 215912 kb
Host smart-197c08bc-9afd-4c1d-8d90-b39f8f964ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762549800 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2762549800
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.549527124
Short name T451
Test name
Test status
Simulation time 36231203 ps
CPU time 1.26 seconds
Started Mar 07 02:42:32 PM PST 24
Finished Mar 07 02:42:33 PM PST 24
Peak memory 216888 kb
Host smart-3bf12000-36be-40d1-a9ca-6be40e6e614d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549527124 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.549527124
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.3419646504
Short name T616
Test name
Test status
Simulation time 144886055 ps
CPU time 1.18 seconds
Started Mar 07 02:40:03 PM PST 24
Finished Mar 07 02:40:05 PM PST 24
Peak memory 214780 kb
Host smart-4197035a-5da3-4ab5-abd7-160e565d010e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419646504 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.3419646504
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.2424560750
Short name T599
Test name
Test status
Simulation time 16457603 ps
CPU time 0.91 seconds
Started Mar 07 02:40:04 PM PST 24
Finished Mar 07 02:40:05 PM PST 24
Peak memory 205704 kb
Host smart-9680234b-93d6-464b-ab6d-07c98435d847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424560750 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.2424560750
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable.2791239896
Short name T716
Test name
Test status
Simulation time 23545268 ps
CPU time 0.89 seconds
Started Mar 07 02:40:04 PM PST 24
Finished Mar 07 02:40:05 PM PST 24
Peak memory 214952 kb
Host smart-7746302a-d996-474a-890f-c6f4fbc4ead1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791239896 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2791239896
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.4226483615
Short name T808
Test name
Test status
Simulation time 28693232 ps
CPU time 1.17 seconds
Started Mar 07 02:40:02 PM PST 24
Finished Mar 07 02:40:03 PM PST 24
Peak memory 215652 kb
Host smart-b39d2232-b7cc-4476-aaf3-d2022fc902cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226483615 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_d
isable_auto_req_mode.4226483615
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_err.3072492192
Short name T439
Test name
Test status
Simulation time 18109975 ps
CPU time 1.03 seconds
Started Mar 07 02:40:05 PM PST 24
Finished Mar 07 02:40:06 PM PST 24
Peak memory 217056 kb
Host smart-049e5b76-c822-4ccd-9123-0cb8c83a8e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072492192 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.3072492192
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/24.edn_genbits.4162988744
Short name T353
Test name
Test status
Simulation time 82580968 ps
CPU time 1.07 seconds
Started Mar 07 02:40:04 PM PST 24
Finished Mar 07 02:40:06 PM PST 24
Peak memory 215808 kb
Host smart-86952dcc-18a5-4dd6-bf04-63c0fe48dbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162988744 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.4162988744
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3303651463
Short name T693
Test name
Test status
Simulation time 20800826 ps
CPU time 1.18 seconds
Started Mar 07 02:40:05 PM PST 24
Finished Mar 07 02:40:06 PM PST 24
Peak memory 231760 kb
Host smart-ee215641-6cad-429b-9768-f11cc8a94e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303651463 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3303651463
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.2248531033
Short name T298
Test name
Test status
Simulation time 42371129 ps
CPU time 0.92 seconds
Started Mar 07 02:40:04 PM PST 24
Finished Mar 07 02:40:06 PM PST 24
Peak memory 214476 kb
Host smart-a9fbef30-5f3a-4772-928f-85be72ae2022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248531033 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.2248531033
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.485559721
Short name T369
Test name
Test status
Simulation time 270440342 ps
CPU time 5.61 seconds
Started Mar 07 02:40:04 PM PST 24
Finished Mar 07 02:40:10 PM PST 24
Peak memory 215548 kb
Host smart-14418943-8471-433c-bac0-f1e4f70ed0af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485559721 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.485559721
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.1342554005
Short name T635
Test name
Test status
Simulation time 184840375013 ps
CPU time 1362.23 seconds
Started Mar 07 02:40:07 PM PST 24
Finished Mar 07 03:02:49 PM PST 24
Peak memory 223476 kb
Host smart-9d853d5b-381b-4ef1-b62f-92df235ea2a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342554005 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.1342554005
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/241.edn_genbits.4174672321
Short name T234
Test name
Test status
Simulation time 62069082 ps
CPU time 1.26 seconds
Started Mar 07 02:42:33 PM PST 24
Finished Mar 07 02:42:34 PM PST 24
Peak memory 217028 kb
Host smart-5a182430-5ed0-44d9-9a22-91ab810ec97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174672321 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.4174672321
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.729859859
Short name T568
Test name
Test status
Simulation time 45189298 ps
CPU time 1.44 seconds
Started Mar 07 02:42:31 PM PST 24
Finished Mar 07 02:42:33 PM PST 24
Peak memory 217648 kb
Host smart-0605f589-ead3-4a02-b3e3-0b4376d17db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729859859 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.729859859
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.4150589470
Short name T591
Test name
Test status
Simulation time 49259078 ps
CPU time 1.71 seconds
Started Mar 07 02:42:31 PM PST 24
Finished Mar 07 02:42:33 PM PST 24
Peak memory 218340 kb
Host smart-89abacdb-7e95-47d5-ad82-1d95b0e910df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150589470 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.4150589470
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.2341631795
Short name T765
Test name
Test status
Simulation time 191846080 ps
CPU time 0.9 seconds
Started Mar 07 02:42:34 PM PST 24
Finished Mar 07 02:42:35 PM PST 24
Peak memory 215712 kb
Host smart-06d65b39-11dc-4238-813a-598920a59533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341631795 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.2341631795
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.4200054879
Short name T627
Test name
Test status
Simulation time 37596457 ps
CPU time 1.16 seconds
Started Mar 07 02:42:29 PM PST 24
Finished Mar 07 02:42:30 PM PST 24
Peak memory 216144 kb
Host smart-84cbf779-19ea-43f2-947c-d777f33718f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200054879 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.4200054879
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.373949907
Short name T297
Test name
Test status
Simulation time 62627960 ps
CPU time 1.02 seconds
Started Mar 07 02:42:30 PM PST 24
Finished Mar 07 02:42:31 PM PST 24
Peak memory 215808 kb
Host smart-0c2260a0-83ca-4f52-a40a-967d7592a912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373949907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.373949907
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.2592195419
Short name T313
Test name
Test status
Simulation time 116966109 ps
CPU time 1.24 seconds
Started Mar 07 02:42:40 PM PST 24
Finished Mar 07 02:42:41 PM PST 24
Peak memory 215800 kb
Host smart-c9b58351-7c07-46c7-9536-9292e5572ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592195419 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.2592195419
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.2087299251
Short name T818
Test name
Test status
Simulation time 59134742 ps
CPU time 1.01 seconds
Started Mar 07 02:42:28 PM PST 24
Finished Mar 07 02:42:29 PM PST 24
Peak memory 217436 kb
Host smart-c277117c-8c3d-4d39-b2cb-f25c59beca95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087299251 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.2087299251
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert_test.2862744344
Short name T413
Test name
Test status
Simulation time 26878548 ps
CPU time 0.8 seconds
Started Mar 07 02:40:18 PM PST 24
Finished Mar 07 02:40:21 PM PST 24
Peak memory 205000 kb
Host smart-9a3d0673-e0ca-47ce-b6d7-9ec86b5d45fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862744344 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.2862744344
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable.1117087134
Short name T112
Test name
Test status
Simulation time 18951331 ps
CPU time 0.86 seconds
Started Mar 07 02:40:18 PM PST 24
Finished Mar 07 02:40:21 PM PST 24
Peak memory 214896 kb
Host smart-e9ef5e82-473f-4b58-a777-b0d04bce1e11
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117087134 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.1117087134
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.1428882132
Short name T86
Test name
Test status
Simulation time 29764307 ps
CPU time 1.12 seconds
Started Mar 07 02:40:14 PM PST 24
Finished Mar 07 02:40:17 PM PST 24
Peak memory 215708 kb
Host smart-9aae3894-86e3-459b-9140-b22e65c46acf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428882132 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.1428882132
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.3065119405
Short name T61
Test name
Test status
Simulation time 31646928 ps
CPU time 1.12 seconds
Started Mar 07 02:40:13 PM PST 24
Finished Mar 07 02:40:16 PM PST 24
Peak memory 215840 kb
Host smart-a8977624-53b9-43c7-b9bf-08e733db13f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065119405 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.3065119405
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.142577914
Short name T820
Test name
Test status
Simulation time 61901875 ps
CPU time 1.71 seconds
Started Mar 07 02:40:05 PM PST 24
Finished Mar 07 02:40:07 PM PST 24
Peak memory 217032 kb
Host smart-633cb0ea-d788-4a03-822b-d39e4d7374c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142577914 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.142577914
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.3448595907
Short name T392
Test name
Test status
Simulation time 23451992 ps
CPU time 1.15 seconds
Started Mar 07 02:40:13 PM PST 24
Finished Mar 07 02:40:15 PM PST 24
Peak memory 222420 kb
Host smart-1eaaf787-b6ab-446b-9003-6926be9c430a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448595907 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.3448595907
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.2125561185
Short name T338
Test name
Test status
Simulation time 38681220 ps
CPU time 0.87 seconds
Started Mar 07 02:40:04 PM PST 24
Finished Mar 07 02:40:05 PM PST 24
Peak memory 214404 kb
Host smart-a4045eef-948b-4ad0-9599-157b871789bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125561185 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.2125561185
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.3200354586
Short name T561
Test name
Test status
Simulation time 663277048 ps
CPU time 2.25 seconds
Started Mar 07 02:40:13 PM PST 24
Finished Mar 07 02:40:17 PM PST 24
Peak memory 215548 kb
Host smart-b138f51f-572c-4614-afa5-4a5a0c25f4fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200354586 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.3200354586
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.4248984962
Short name T672
Test name
Test status
Simulation time 103265684106 ps
CPU time 668.69 seconds
Started Mar 07 02:40:12 PM PST 24
Finished Mar 07 02:51:21 PM PST 24
Peak memory 222856 kb
Host smart-35622d3a-11d4-4047-957f-4665616496c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248984962 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.4248984962
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.1590418645
Short name T391
Test name
Test status
Simulation time 94232105 ps
CPU time 1.12 seconds
Started Mar 07 02:42:40 PM PST 24
Finished Mar 07 02:42:41 PM PST 24
Peak memory 215336 kb
Host smart-79bc6a20-ebb8-4e23-8c21-8ab1a1ad4349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590418645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.1590418645
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.1852487
Short name T329
Test name
Test status
Simulation time 31401758 ps
CPU time 1.23 seconds
Started Mar 07 02:42:33 PM PST 24
Finished Mar 07 02:42:34 PM PST 24
Peak memory 215648 kb
Host smart-af867a3d-2483-4b05-a048-c5e54e98d64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.1852487
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.195339755
Short name T613
Test name
Test status
Simulation time 33444193 ps
CPU time 1.36 seconds
Started Mar 07 02:42:31 PM PST 24
Finished Mar 07 02:42:32 PM PST 24
Peak memory 218276 kb
Host smart-47e5972d-11a3-4bd0-b90e-4e118d3df8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195339755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.195339755
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.130540433
Short name T34
Test name
Test status
Simulation time 264819680 ps
CPU time 1.37 seconds
Started Mar 07 02:42:29 PM PST 24
Finished Mar 07 02:42:31 PM PST 24
Peak memory 215212 kb
Host smart-f4414e55-b29a-48e2-8404-488703f9edd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130540433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.130540433
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3269611903
Short name T662
Test name
Test status
Simulation time 46201642 ps
CPU time 1.59 seconds
Started Mar 07 02:42:34 PM PST 24
Finished Mar 07 02:42:36 PM PST 24
Peak memory 218180 kb
Host smart-734e6af9-3555-4fae-a93a-ea7bdbf7973f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269611903 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3269611903
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.2054597259
Short name T494
Test name
Test status
Simulation time 72068995 ps
CPU time 1.05 seconds
Started Mar 07 02:42:35 PM PST 24
Finished Mar 07 02:42:37 PM PST 24
Peak memory 215760 kb
Host smart-63dda1d4-989a-4e91-abc7-05008bc32176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054597259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.2054597259
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3313057485
Short name T480
Test name
Test status
Simulation time 53804080 ps
CPU time 1.31 seconds
Started Mar 07 02:42:31 PM PST 24
Finished Mar 07 02:42:32 PM PST 24
Peak memory 216840 kb
Host smart-900c44b7-47b6-4467-a1e8-9804be390ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313057485 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3313057485
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.3595681910
Short name T724
Test name
Test status
Simulation time 99782647 ps
CPU time 1.34 seconds
Started Mar 07 02:42:31 PM PST 24
Finished Mar 07 02:42:32 PM PST 24
Peak memory 217124 kb
Host smart-59aeaadb-ce48-4dae-aef1-da9fc94e5734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595681910 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.3595681910
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.2455389409
Short name T659
Test name
Test status
Simulation time 68688089 ps
CPU time 1.51 seconds
Started Mar 07 02:42:30 PM PST 24
Finished Mar 07 02:42:32 PM PST 24
Peak memory 217200 kb
Host smart-e2416705-ffb3-4dd8-a745-256bcf85ceb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455389409 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.2455389409
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.1237983046
Short name T704
Test name
Test status
Simulation time 44842168 ps
CPU time 1.4 seconds
Started Mar 07 02:42:28 PM PST 24
Finished Mar 07 02:42:30 PM PST 24
Peak memory 215960 kb
Host smart-83585fdd-d7ea-4854-9ab0-7290d759cc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237983046 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.1237983046
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.1908155982
Short name T107
Test name
Test status
Simulation time 24310858 ps
CPU time 1.1 seconds
Started Mar 07 02:40:12 PM PST 24
Finished Mar 07 02:40:15 PM PST 24
Peak memory 214736 kb
Host smart-b4c6b7c0-9f81-4375-a942-fe5d57247092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908155982 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.1908155982
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.2605889301
Short name T590
Test name
Test status
Simulation time 25436717 ps
CPU time 0.86 seconds
Started Mar 07 02:40:15 PM PST 24
Finished Mar 07 02:40:17 PM PST 24
Peak memory 205212 kb
Host smart-098f1393-fba8-44e8-8a8a-483b9756f7ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605889301 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.2605889301
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.2792066579
Short name T563
Test name
Test status
Simulation time 13129375 ps
CPU time 0.91 seconds
Started Mar 07 02:40:13 PM PST 24
Finished Mar 07 02:40:15 PM PST 24
Peak memory 215036 kb
Host smart-a54b1b09-351d-4d00-8538-509da98ba06c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792066579 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.2792066579
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_err.1521717822
Short name T608
Test name
Test status
Simulation time 24836193 ps
CPU time 0.95 seconds
Started Mar 07 02:40:13 PM PST 24
Finished Mar 07 02:40:15 PM PST 24
Peak memory 217256 kb
Host smart-9cd8709d-a31b-4031-8e5e-ec1c1fded7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521717822 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.1521717822
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.1982989286
Short name T288
Test name
Test status
Simulation time 103038893 ps
CPU time 1.6 seconds
Started Mar 07 02:40:14 PM PST 24
Finished Mar 07 02:40:17 PM PST 24
Peak memory 217292 kb
Host smart-ab1bb198-9012-4c34-9a22-4407a8c2ef47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982989286 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.1982989286
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.3487568118
Short name T833
Test name
Test status
Simulation time 34065259 ps
CPU time 0.87 seconds
Started Mar 07 02:40:14 PM PST 24
Finished Mar 07 02:40:16 PM PST 24
Peak memory 214724 kb
Host smart-00079b57-b550-4dee-8794-6f9885c2df7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487568118 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.3487568118
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.141193451
Short name T580
Test name
Test status
Simulation time 25130121 ps
CPU time 0.91 seconds
Started Mar 07 02:40:16 PM PST 24
Finished Mar 07 02:40:21 PM PST 24
Peak memory 214368 kb
Host smart-f22a096d-4808-4e6a-8783-de0382dd8bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141193451 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.141193451
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3393192420
Short name T337
Test name
Test status
Simulation time 857029176 ps
CPU time 4.62 seconds
Started Mar 07 02:40:16 PM PST 24
Finished Mar 07 02:40:24 PM PST 24
Peak memory 215644 kb
Host smart-30514b35-e716-4472-b1d1-ff84df9aa143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393192420 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3393192420
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.4015047986
Short name T316
Test name
Test status
Simulation time 68023444632 ps
CPU time 782.61 seconds
Started Mar 07 02:40:13 PM PST 24
Finished Mar 07 02:53:17 PM PST 24
Peak memory 222704 kb
Host smart-246d0307-1751-49bf-9cc4-41b478ab2f79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015047986 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.4015047986
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.2729955297
Short name T780
Test name
Test status
Simulation time 49319252 ps
CPU time 1.9 seconds
Started Mar 07 02:42:31 PM PST 24
Finished Mar 07 02:42:33 PM PST 24
Peak memory 216984 kb
Host smart-001dae99-b2a6-456e-b8ab-4fa0f70a29e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729955297 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.2729955297
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3102566229
Short name T588
Test name
Test status
Simulation time 134011724 ps
CPU time 1.54 seconds
Started Mar 07 02:42:35 PM PST 24
Finished Mar 07 02:42:37 PM PST 24
Peak memory 216956 kb
Host smart-a3863751-90a1-4567-a34f-924590b8f1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102566229 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3102566229
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.3203640467
Short name T629
Test name
Test status
Simulation time 90235942 ps
CPU time 1.54 seconds
Started Mar 07 02:42:36 PM PST 24
Finished Mar 07 02:42:38 PM PST 24
Peak memory 217220 kb
Host smart-1a84f990-8e5d-411f-96db-aba21544945d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203640467 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.3203640467
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.2504043215
Short name T295
Test name
Test status
Simulation time 59950778 ps
CPU time 1.6 seconds
Started Mar 07 02:42:29 PM PST 24
Finished Mar 07 02:42:31 PM PST 24
Peak memory 215308 kb
Host smart-1c2f230f-7a24-4099-82c9-5d85c7b0d355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504043215 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.2504043215
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2325924774
Short name T817
Test name
Test status
Simulation time 129035448 ps
CPU time 1.28 seconds
Started Mar 07 02:42:36 PM PST 24
Finished Mar 07 02:42:37 PM PST 24
Peak memory 216936 kb
Host smart-96aacbc8-d8f5-41d7-a23e-1fb21ba1416d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325924774 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2325924774
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.1965961916
Short name T29
Test name
Test status
Simulation time 85558642 ps
CPU time 1.33 seconds
Started Mar 07 02:42:38 PM PST 24
Finished Mar 07 02:42:39 PM PST 24
Peak memory 216920 kb
Host smart-83f63483-ec9f-4359-8c0c-bf7116eaf37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965961916 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.1965961916
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.2236501426
Short name T327
Test name
Test status
Simulation time 53594489 ps
CPU time 1.2 seconds
Started Mar 07 02:42:37 PM PST 24
Finished Mar 07 02:42:39 PM PST 24
Peak memory 215548 kb
Host smart-ada6a894-3e1f-4fb5-bd4e-8e316028bffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236501426 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.2236501426
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.1027785571
Short name T824
Test name
Test status
Simulation time 81831738 ps
CPU time 2.52 seconds
Started Mar 07 02:42:37 PM PST 24
Finished Mar 07 02:42:40 PM PST 24
Peak memory 218432 kb
Host smart-b6c2c482-bd15-40ac-9d37-a31d037614b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027785571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.1027785571
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.2757310191
Short name T606
Test name
Test status
Simulation time 274548037 ps
CPU time 1.16 seconds
Started Mar 07 02:42:39 PM PST 24
Finished Mar 07 02:42:40 PM PST 24
Peak memory 217164 kb
Host smart-7db2552d-1dff-424b-8968-1b90448d0810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757310191 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.2757310191
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.1653716604
Short name T773
Test name
Test status
Simulation time 23964109 ps
CPU time 1.14 seconds
Started Mar 07 02:40:13 PM PST 24
Finished Mar 07 02:40:15 PM PST 24
Peak memory 214728 kb
Host smart-48c3082b-6dd3-477d-ac1b-f7adc0c053aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653716604 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.1653716604
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.896440757
Short name T463
Test name
Test status
Simulation time 14599101 ps
CPU time 0.92 seconds
Started Mar 07 02:40:14 PM PST 24
Finished Mar 07 02:40:16 PM PST 24
Peak memory 205696 kb
Host smart-ca62bc40-826c-4a6b-8e1f-193b0a3adbae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896440757 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.896440757
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.1335597032
Short name T344
Test name
Test status
Simulation time 37083643 ps
CPU time 0.82 seconds
Started Mar 07 02:40:13 PM PST 24
Finished Mar 07 02:40:15 PM PST 24
Peak memory 214640 kb
Host smart-49e9868b-05c4-427c-8eb3-8b762c4144cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335597032 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.1335597032
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_disable_auto_req_mode.105758270
Short name T628
Test name
Test status
Simulation time 33886436 ps
CPU time 1.19 seconds
Started Mar 07 02:40:13 PM PST 24
Finished Mar 07 02:40:16 PM PST 24
Peak memory 215432 kb
Host smart-f59f83a5-cd2c-49cf-8931-5c047d3fab3f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105758270 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_di
sable_auto_req_mode.105758270
Directory /workspace/27.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/27.edn_err.1113606831
Short name T701
Test name
Test status
Simulation time 43232774 ps
CPU time 1.2 seconds
Started Mar 07 02:40:17 PM PST 24
Finished Mar 07 02:40:21 PM PST 24
Peak memory 218412 kb
Host smart-018fdf29-17ba-4d09-b6a7-f5b3713cb139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113606831 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.1113606831
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_genbits.4150236614
Short name T683
Test name
Test status
Simulation time 38796023 ps
CPU time 1.73 seconds
Started Mar 07 02:40:14 PM PST 24
Finished Mar 07 02:40:17 PM PST 24
Peak memory 215928 kb
Host smart-d1e4dcdc-d75d-4911-9633-4510c57b4ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150236614 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.4150236614
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_intr.705854198
Short name T605
Test name
Test status
Simulation time 22703915 ps
CPU time 0.93 seconds
Started Mar 07 02:40:16 PM PST 24
Finished Mar 07 02:40:21 PM PST 24
Peak memory 214700 kb
Host smart-be238707-0a47-48cc-b294-77a3ef7ed9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705854198 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.705854198
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.339679995
Short name T562
Test name
Test status
Simulation time 14992325 ps
CPU time 0.93 seconds
Started Mar 07 02:40:17 PM PST 24
Finished Mar 07 02:40:21 PM PST 24
Peak memory 214376 kb
Host smart-908addd6-2071-46fa-b636-8c1bf078ffc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339679995 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.339679995
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.13950399
Short name T139
Test name
Test status
Simulation time 362393332 ps
CPU time 4.13 seconds
Started Mar 07 02:40:14 PM PST 24
Finished Mar 07 02:40:19 PM PST 24
Peak memory 214428 kb
Host smart-7447d944-828c-441b-b991-3dedf81ba4e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13950399 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.13950399
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.1376650149
Short name T797
Test name
Test status
Simulation time 17874262990 ps
CPU time 453.82 seconds
Started Mar 07 02:40:18 PM PST 24
Finished Mar 07 02:47:54 PM PST 24
Peak memory 219408 kb
Host smart-84e013bc-b531-400f-b29b-d1d143b1ead8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376650149 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.1376650149
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.92501930
Short name T784
Test name
Test status
Simulation time 29595398 ps
CPU time 1.22 seconds
Started Mar 07 02:42:37 PM PST 24
Finished Mar 07 02:42:38 PM PST 24
Peak memory 217016 kb
Host smart-34d01eb3-5c77-46c5-8fc7-26ed5e79a474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92501930 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.92501930
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.2821456580
Short name T388
Test name
Test status
Simulation time 53917710 ps
CPU time 1.07 seconds
Started Mar 07 02:42:37 PM PST 24
Finished Mar 07 02:42:38 PM PST 24
Peak memory 217056 kb
Host smart-ac58a07c-30d5-4918-af8c-2709f9b8b7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821456580 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.2821456580
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.919942796
Short name T767
Test name
Test status
Simulation time 37857241 ps
CPU time 1.4 seconds
Started Mar 07 02:42:36 PM PST 24
Finished Mar 07 02:42:37 PM PST 24
Peak memory 216824 kb
Host smart-f90f107d-13cf-421c-a03e-f4206d961a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919942796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.919942796
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.1382694912
Short name T565
Test name
Test status
Simulation time 49238296 ps
CPU time 1.12 seconds
Started Mar 07 02:42:36 PM PST 24
Finished Mar 07 02:42:37 PM PST 24
Peak memory 215728 kb
Host smart-d3dfaa9d-7549-4928-bd60-7ed0b44e3737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382694912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.1382694912
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.3392483378
Short name T273
Test name
Test status
Simulation time 62951515 ps
CPU time 1.22 seconds
Started Mar 07 02:42:34 PM PST 24
Finished Mar 07 02:42:35 PM PST 24
Peak memory 215596 kb
Host smart-7df0b1cf-3dc2-4976-babf-e07acc527b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392483378 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.3392483378
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.2388162639
Short name T430
Test name
Test status
Simulation time 74992438 ps
CPU time 1.02 seconds
Started Mar 07 02:42:36 PM PST 24
Finished Mar 07 02:42:37 PM PST 24
Peak memory 215528 kb
Host smart-7bd84f85-54e8-41cb-a60c-38b12ad76cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388162639 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.2388162639
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.37749833
Short name T657
Test name
Test status
Simulation time 48636309 ps
CPU time 1.85 seconds
Started Mar 07 02:42:38 PM PST 24
Finished Mar 07 02:42:40 PM PST 24
Peak memory 216928 kb
Host smart-8fd4b0e6-6de3-4d0d-ad87-e6badef35353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37749833 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.37749833
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.2462783911
Short name T356
Test name
Test status
Simulation time 49060161 ps
CPU time 1.24 seconds
Started Mar 07 02:42:37 PM PST 24
Finished Mar 07 02:42:38 PM PST 24
Peak memory 216988 kb
Host smart-dc64155d-cbb1-45a9-8e08-3d92947fe500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462783911 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.2462783911
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.4137793857
Short name T795
Test name
Test status
Simulation time 40767253 ps
CPU time 1.06 seconds
Started Mar 07 02:42:42 PM PST 24
Finished Mar 07 02:42:43 PM PST 24
Peak memory 215768 kb
Host smart-0298d50e-5e6c-4de9-b3e3-b8b5ab5d182f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137793857 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.4137793857
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.65122662
Short name T675
Test name
Test status
Simulation time 200839304 ps
CPU time 1.83 seconds
Started Mar 07 02:42:41 PM PST 24
Finished Mar 07 02:42:43 PM PST 24
Peak memory 217052 kb
Host smart-0aff5cdb-9687-4bc9-a7b0-e8db458cccb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65122662 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.65122662
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.1166415982
Short name T253
Test name
Test status
Simulation time 120973868 ps
CPU time 1.17 seconds
Started Mar 07 02:40:24 PM PST 24
Finished Mar 07 02:40:28 PM PST 24
Peak memory 214784 kb
Host smart-6dcc6d37-f424-43a7-93c9-53817bbd5864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166415982 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.1166415982
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.1761561708
Short name T676
Test name
Test status
Simulation time 13572215 ps
CPU time 0.86 seconds
Started Mar 07 02:40:24 PM PST 24
Finished Mar 07 02:40:28 PM PST 24
Peak memory 205100 kb
Host smart-014c3721-bc91-4010-943f-7c11852c93c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761561708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.1761561708
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.2678712665
Short name T101
Test name
Test status
Simulation time 36148515 ps
CPU time 0.85 seconds
Started Mar 07 02:40:24 PM PST 24
Finished Mar 07 02:40:28 PM PST 24
Peak memory 214648 kb
Host smart-f8156d0f-354c-4734-84a2-147b22f3c44a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678712665 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.2678712665
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.3586391544
Short name T160
Test name
Test status
Simulation time 43149120 ps
CPU time 1.19 seconds
Started Mar 07 02:40:23 PM PST 24
Finished Mar 07 02:40:28 PM PST 24
Peak memory 231572 kb
Host smart-1f8b87f1-6053-4dd7-bb0c-853341ec0e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586391544 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.3586391544
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.2596150276
Short name T315
Test name
Test status
Simulation time 72450872 ps
CPU time 1.54 seconds
Started Mar 07 02:40:11 PM PST 24
Finished Mar 07 02:40:13 PM PST 24
Peak memory 216980 kb
Host smart-bb926683-9a9e-4a0d-a682-84db5fa61a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596150276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.2596150276
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.2783145688
Short name T781
Test name
Test status
Simulation time 21479465 ps
CPU time 1.07 seconds
Started Mar 07 02:40:13 PM PST 24
Finished Mar 07 02:40:15 PM PST 24
Peak memory 214536 kb
Host smart-42f181b1-4e82-4233-949c-80ddd1c426d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783145688 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.2783145688
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.1321406647
Short name T233
Test name
Test status
Simulation time 17362455 ps
CPU time 1.06 seconds
Started Mar 07 02:40:13 PM PST 24
Finished Mar 07 02:40:15 PM PST 24
Peak memory 214384 kb
Host smart-79aca55d-91e2-4f41-a58d-82edc067831c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321406647 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.1321406647
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.2660689190
Short name T306
Test name
Test status
Simulation time 195805692 ps
CPU time 3.6 seconds
Started Mar 07 02:40:15 PM PST 24
Finished Mar 07 02:40:20 PM PST 24
Peak memory 218280 kb
Host smart-0c64bb28-eb03-4513-b7d1-4788e58c9d93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660689190 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.2660689190
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2296628938
Short name T191
Test name
Test status
Simulation time 617598090892 ps
CPU time 726.18 seconds
Started Mar 07 02:40:13 PM PST 24
Finished Mar 07 02:52:21 PM PST 24
Peak memory 218044 kb
Host smart-18e9212e-1351-4077-a64a-9fe9b9a87485
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296628938 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2296628938
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.2009269913
Short name T133
Test name
Test status
Simulation time 63723241 ps
CPU time 1.69 seconds
Started Mar 07 02:42:38 PM PST 24
Finished Mar 07 02:42:39 PM PST 24
Peak memory 217392 kb
Host smart-75272beb-7b5b-4ca5-a55a-46b735ed7335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009269913 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.2009269913
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.1971243244
Short name T766
Test name
Test status
Simulation time 83268920 ps
CPU time 0.9 seconds
Started Mar 07 02:42:44 PM PST 24
Finished Mar 07 02:42:45 PM PST 24
Peak memory 215836 kb
Host smart-5861bda9-617b-4417-a97e-fef1dac04d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971243244 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.1971243244
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.3771883543
Short name T25
Test name
Test status
Simulation time 98375977 ps
CPU time 1.22 seconds
Started Mar 07 02:42:37 PM PST 24
Finished Mar 07 02:42:38 PM PST 24
Peak memory 215852 kb
Host smart-768e967f-eaae-47e7-b763-954e8a2c9632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771883543 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.3771883543
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.2017845936
Short name T584
Test name
Test status
Simulation time 79625002 ps
CPU time 1.06 seconds
Started Mar 07 02:42:36 PM PST 24
Finished Mar 07 02:42:37 PM PST 24
Peak memory 216868 kb
Host smart-e63e1ae0-1691-4c9c-a95a-cd45a22ae3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017845936 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.2017845936
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2574327260
Short name T443
Test name
Test status
Simulation time 92064944 ps
CPU time 1.49 seconds
Started Mar 07 02:42:36 PM PST 24
Finished Mar 07 02:42:38 PM PST 24
Peak memory 217036 kb
Host smart-4abd2038-80f6-4388-a64e-bf1a401f32fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574327260 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2574327260
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2559699095
Short name T597
Test name
Test status
Simulation time 97470622 ps
CPU time 1.34 seconds
Started Mar 07 02:42:37 PM PST 24
Finished Mar 07 02:42:39 PM PST 24
Peak memory 217140 kb
Host smart-7b4c8af5-80aa-4d23-9dc9-ef18626df27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559699095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2559699095
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.616907087
Short name T31
Test name
Test status
Simulation time 50547559 ps
CPU time 1.2 seconds
Started Mar 07 02:42:36 PM PST 24
Finished Mar 07 02:42:38 PM PST 24
Peak memory 216716 kb
Host smart-7e8bf257-2c06-4f0a-870d-ab9186ad287b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616907087 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.616907087
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.3896601605
Short name T354
Test name
Test status
Simulation time 73679448 ps
CPU time 1.54 seconds
Started Mar 07 02:42:39 PM PST 24
Finished Mar 07 02:42:41 PM PST 24
Peak memory 216768 kb
Host smart-69a0f0ae-514f-49f2-a29c-65286b8f291a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896601605 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.3896601605
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.1979730960
Short name T576
Test name
Test status
Simulation time 61702471 ps
CPU time 1.34 seconds
Started Mar 07 02:42:37 PM PST 24
Finished Mar 07 02:42:38 PM PST 24
Peak memory 217900 kb
Host smart-e39ea194-21b3-4b27-9439-f86ec134da88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979730960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1979730960
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3690206497
Short name T371
Test name
Test status
Simulation time 43311445 ps
CPU time 1.6 seconds
Started Mar 07 02:42:40 PM PST 24
Finished Mar 07 02:42:42 PM PST 24
Peak memory 216976 kb
Host smart-ef96772e-2e8d-4ea8-b2eb-efb386f74ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690206497 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3690206497
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.3759689550
Short name T259
Test name
Test status
Simulation time 27785907 ps
CPU time 1.32 seconds
Started Mar 07 02:40:24 PM PST 24
Finished Mar 07 02:40:28 PM PST 24
Peak memory 214816 kb
Host smart-fa5b3c38-8819-48be-aba9-de4538653ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759689550 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.3759689550
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.3388309894
Short name T446
Test name
Test status
Simulation time 18731277 ps
CPU time 0.97 seconds
Started Mar 07 02:40:25 PM PST 24
Finished Mar 07 02:40:28 PM PST 24
Peak memory 205736 kb
Host smart-7dad05a1-e4b2-40b9-b4bc-0be47bf88a53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388309894 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.3388309894
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable_auto_req_mode.1986815840
Short name T92
Test name
Test status
Simulation time 53229772 ps
CPU time 1.47 seconds
Started Mar 07 02:40:23 PM PST 24
Finished Mar 07 02:40:28 PM PST 24
Peak memory 215428 kb
Host smart-e20fdebf-0a88-4f1e-b9d0-7bee35e76517
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986815840 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_d
isable_auto_req_mode.1986815840
Directory /workspace/29.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/29.edn_err.3568377279
Short name T639
Test name
Test status
Simulation time 18507820 ps
CPU time 1.07 seconds
Started Mar 07 02:40:26 PM PST 24
Finished Mar 07 02:40:28 PM PST 24
Peak memory 217064 kb
Host smart-fb126833-ed10-4967-97ad-516dfe34c815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568377279 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.3568377279
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.2310875434
Short name T381
Test name
Test status
Simulation time 107922068 ps
CPU time 1.19 seconds
Started Mar 07 02:40:25 PM PST 24
Finished Mar 07 02:40:28 PM PST 24
Peak memory 215604 kb
Host smart-8980b1a6-f0e0-4c1e-8ac7-99794062ff8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310875434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.2310875434
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.2978336144
Short name T352
Test name
Test status
Simulation time 41654913 ps
CPU time 0.86 seconds
Started Mar 07 02:40:22 PM PST 24
Finished Mar 07 02:40:24 PM PST 24
Peak memory 214484 kb
Host smart-be5a58f8-5388-4e32-8a15-737da4e0f568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978336144 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.2978336144
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.4207777454
Short name T499
Test name
Test status
Simulation time 53710847 ps
CPU time 0.92 seconds
Started Mar 07 02:40:26 PM PST 24
Finished Mar 07 02:40:28 PM PST 24
Peak memory 214368 kb
Host smart-22fcd2ce-0b25-477a-baf1-4ca1995683fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207777454 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.4207777454
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.3480657390
Short name T786
Test name
Test status
Simulation time 248229607 ps
CPU time 1.85 seconds
Started Mar 07 02:40:23 PM PST 24
Finished Mar 07 02:40:28 PM PST 24
Peak memory 214428 kb
Host smart-826aa4b0-e37c-40c1-b555-eb874fa90954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480657390 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.3480657390
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.2341675311
Short name T582
Test name
Test status
Simulation time 110738315694 ps
CPU time 1446.48 seconds
Started Mar 07 02:40:24 PM PST 24
Finished Mar 07 03:04:34 PM PST 24
Peak memory 224860 kb
Host smart-6839ff81-5cbb-4cff-b086-302f6681d8ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341675311 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.2341675311
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.627451751
Short name T760
Test name
Test status
Simulation time 35957820 ps
CPU time 1.37 seconds
Started Mar 07 02:42:40 PM PST 24
Finished Mar 07 02:42:42 PM PST 24
Peak memory 216992 kb
Host smart-163d5493-4a4c-44f5-b545-d4ae3f5137a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627451751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.627451751
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.2877080065
Short name T377
Test name
Test status
Simulation time 61864282 ps
CPU time 1.24 seconds
Started Mar 07 02:42:41 PM PST 24
Finished Mar 07 02:42:42 PM PST 24
Peak memory 216740 kb
Host smart-0e181436-7f3c-46c5-a320-417ed282ee7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877080065 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.2877080065
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.4127909417
Short name T495
Test name
Test status
Simulation time 56225380 ps
CPU time 1.5 seconds
Started Mar 07 02:42:39 PM PST 24
Finished Mar 07 02:42:41 PM PST 24
Peak memory 216904 kb
Host smart-b4cc153a-b413-417f-b462-6c5bd5593c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127909417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.4127909417
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.2864708659
Short name T320
Test name
Test status
Simulation time 52681302 ps
CPU time 1.32 seconds
Started Mar 07 02:42:39 PM PST 24
Finished Mar 07 02:42:41 PM PST 24
Peak memory 215596 kb
Host smart-51a14c9f-c04f-4258-ad26-de3d4bc5524a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864708659 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.2864708659
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.1314942671
Short name T514
Test name
Test status
Simulation time 45611717 ps
CPU time 1.63 seconds
Started Mar 07 02:42:40 PM PST 24
Finished Mar 07 02:42:42 PM PST 24
Peak memory 217044 kb
Host smart-99ed0158-b121-4b89-b46f-e42200548e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314942671 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.1314942671
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.2368900182
Short name T535
Test name
Test status
Simulation time 62365989 ps
CPU time 1.22 seconds
Started Mar 07 02:42:41 PM PST 24
Finished Mar 07 02:42:42 PM PST 24
Peak memory 217348 kb
Host smart-fb567621-8335-45a7-9f5e-cd24f4d1bc90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368900182 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.2368900182
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.3250594000
Short name T279
Test name
Test status
Simulation time 67069939 ps
CPU time 1.45 seconds
Started Mar 07 02:42:41 PM PST 24
Finished Mar 07 02:42:42 PM PST 24
Peak memory 217640 kb
Host smart-48bf9593-c11d-40de-b7a3-dce36bb34b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250594000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.3250594000
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.1677656138
Short name T720
Test name
Test status
Simulation time 91116338 ps
CPU time 2.07 seconds
Started Mar 07 02:42:40 PM PST 24
Finished Mar 07 02:42:42 PM PST 24
Peak memory 216092 kb
Host smart-3c4471ee-4111-4228-8319-b9c49fdd3586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677656138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.1677656138
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.2824481556
Short name T828
Test name
Test status
Simulation time 25461839 ps
CPU time 1.19 seconds
Started Mar 07 02:42:41 PM PST 24
Finished Mar 07 02:42:42 PM PST 24
Peak memory 215468 kb
Host smart-e62bed00-879f-433a-ac4d-7be1bc2d9b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824481556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.2824481556
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.1421645606
Short name T365
Test name
Test status
Simulation time 53984643 ps
CPU time 1.44 seconds
Started Mar 07 02:42:44 PM PST 24
Finished Mar 07 02:42:45 PM PST 24
Peak memory 216816 kb
Host smart-739cd6df-8eae-40dd-98e3-e42ac35e8cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421645606 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.1421645606
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert_test.2682477774
Short name T424
Test name
Test status
Simulation time 25505422 ps
CPU time 0.93 seconds
Started Mar 07 02:38:52 PM PST 24
Finished Mar 07 02:38:53 PM PST 24
Peak memory 205204 kb
Host smart-32bce4f1-195e-4e8f-a7b7-39d0fb4c9cb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682477774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.2682477774
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable_auto_req_mode.994386742
Short name T88
Test name
Test status
Simulation time 49286645 ps
CPU time 1.47 seconds
Started Mar 07 02:38:53 PM PST 24
Finished Mar 07 02:38:54 PM PST 24
Peak memory 215524 kb
Host smart-52b94b9d-bbbb-4eea-9498-46ac0bf563aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994386742 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_dis
able_auto_req_mode.994386742
Directory /workspace/3.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/3.edn_err.1860283504
Short name T89
Test name
Test status
Simulation time 37268566 ps
CPU time 0.92 seconds
Started Mar 07 02:38:49 PM PST 24
Finished Mar 07 02:38:50 PM PST 24
Peak memory 215944 kb
Host smart-308aea59-21e5-4cf9-a9e3-3b926983c5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860283504 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.1860283504
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.1741347755
Short name T415
Test name
Test status
Simulation time 70478437 ps
CPU time 1.3 seconds
Started Mar 07 02:38:42 PM PST 24
Finished Mar 07 02:38:44 PM PST 24
Peak memory 217068 kb
Host smart-c39d6e6a-24d1-47b7-b555-886a190d0dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741347755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.1741347755
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.2929290304
Short name T544
Test name
Test status
Simulation time 40868873 ps
CPU time 0.82 seconds
Started Mar 07 02:38:52 PM PST 24
Finished Mar 07 02:38:53 PM PST 24
Peak memory 214672 kb
Host smart-f618f9a7-ff92-404c-8ab8-b6fc72e8ef7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929290304 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.2929290304
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_regwen.1252199888
Short name T126
Test name
Test status
Simulation time 27281195 ps
CPU time 0.93 seconds
Started Mar 07 02:38:44 PM PST 24
Finished Mar 07 02:38:45 PM PST 24
Peak memory 206168 kb
Host smart-f825a42e-ff7c-4b59-af6d-6773ebfd63bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252199888 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.1252199888
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/3.edn_sec_cm.424922050
Short name T16
Test name
Test status
Simulation time 2886905029 ps
CPU time 3.69 seconds
Started Mar 07 02:38:51 PM PST 24
Finished Mar 07 02:38:55 PM PST 24
Peak memory 233992 kb
Host smart-a80b5e11-98ed-4bf0-994c-88dc1a3ab38a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424922050 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.424922050
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.3142490615
Short name T48
Test name
Test status
Simulation time 16748573 ps
CPU time 1.02 seconds
Started Mar 07 02:38:47 PM PST 24
Finished Mar 07 02:38:48 PM PST 24
Peak memory 214444 kb
Host smart-874ee8e1-c0a0-4bec-800e-3c679dd14344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142490615 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.3142490615
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.1223404583
Short name T390
Test name
Test status
Simulation time 220029919 ps
CPU time 2.52 seconds
Started Mar 07 02:38:42 PM PST 24
Finished Mar 07 02:38:45 PM PST 24
Peak memory 215580 kb
Host smart-5799c68a-d2c7-4802-9632-a5fc0cfd873f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223404583 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.1223404583
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.3793523949
Short name T487
Test name
Test status
Simulation time 36447164070 ps
CPU time 454.48 seconds
Started Mar 07 02:38:52 PM PST 24
Finished Mar 07 02:46:27 PM PST 24
Peak memory 220628 kb
Host smart-c5c84e38-788d-4350-bdb7-eeb7dcd70850
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793523949 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.3793523949
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert_test.1058184261
Short name T349
Test name
Test status
Simulation time 11344250 ps
CPU time 0.85 seconds
Started Mar 07 02:40:29 PM PST 24
Finished Mar 07 02:40:30 PM PST 24
Peak memory 204944 kb
Host smart-99368119-4de0-4742-af60-0838948b3990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058184261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1058184261
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.907101368
Short name T53
Test name
Test status
Simulation time 43526983 ps
CPU time 1.4 seconds
Started Mar 07 02:40:26 PM PST 24
Finished Mar 07 02:40:29 PM PST 24
Peak memory 217700 kb
Host smart-f9ff3309-9902-4aba-8003-b18006fab3c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907101368 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_di
sable_auto_req_mode.907101368
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3757857201
Short name T449
Test name
Test status
Simulation time 64080856 ps
CPU time 0.88 seconds
Started Mar 07 02:40:26 PM PST 24
Finished Mar 07 02:40:28 PM PST 24
Peak memory 217288 kb
Host smart-a88dc1db-96e3-448c-8381-e828c87b4f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757857201 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3757857201
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.3891419187
Short name T510
Test name
Test status
Simulation time 58130045 ps
CPU time 1.64 seconds
Started Mar 07 02:40:23 PM PST 24
Finished Mar 07 02:40:29 PM PST 24
Peak memory 216700 kb
Host smart-52fdcfde-cf8a-4180-82ee-423441c189f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891419187 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.3891419187
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.93819395
Short name T202
Test name
Test status
Simulation time 28202592 ps
CPU time 1.07 seconds
Started Mar 07 02:40:29 PM PST 24
Finished Mar 07 02:40:30 PM PST 24
Peak memory 214844 kb
Host smart-94815634-6c1c-4882-9c89-cdcfcaaec809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93819395 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.93819395
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.2753652167
Short name T326
Test name
Test status
Simulation time 41152786 ps
CPU time 0.9 seconds
Started Mar 07 02:40:24 PM PST 24
Finished Mar 07 02:40:28 PM PST 24
Peak memory 214416 kb
Host smart-9a8dc19e-6067-47d4-900c-f61c0be47f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753652167 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.2753652167
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1031698442
Short name T526
Test name
Test status
Simulation time 222370104 ps
CPU time 4.22 seconds
Started Mar 07 02:40:24 PM PST 24
Finished Mar 07 02:40:31 PM PST 24
Peak memory 214472 kb
Host smart-57a55b27-7c20-46d3-af86-9025fd9be67b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031698442 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1031698442
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3520831303
Short name T626
Test name
Test status
Simulation time 172048960082 ps
CPU time 966.45 seconds
Started Mar 07 02:40:25 PM PST 24
Finished Mar 07 02:56:34 PM PST 24
Peak memory 220820 kb
Host smart-2da837e3-c4f5-4dae-b78e-2213ed8ed9a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520831303 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3520831303
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.1083015710
Short name T181
Test name
Test status
Simulation time 93141917 ps
CPU time 1.17 seconds
Started Mar 07 02:40:27 PM PST 24
Finished Mar 07 02:40:29 PM PST 24
Peak memory 214804 kb
Host smart-4adf7d37-8a55-4af5-baa6-0d1fbe7839b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083015710 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.1083015710
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.731598850
Short name T738
Test name
Test status
Simulation time 33270629 ps
CPU time 0.93 seconds
Started Mar 07 02:40:28 PM PST 24
Finished Mar 07 02:40:29 PM PST 24
Peak memory 206080 kb
Host smart-61e744d8-a7a9-4dec-aade-6526b9641ede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731598850 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.731598850
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.2436333517
Short name T837
Test name
Test status
Simulation time 77056035 ps
CPU time 0.88 seconds
Started Mar 07 02:40:28 PM PST 24
Finished Mar 07 02:40:29 PM PST 24
Peak memory 214556 kb
Host smart-807de7e4-9776-412b-a354-ca64964a8627
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436333517 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.2436333517
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_err.1647439340
Short name T124
Test name
Test status
Simulation time 19314135 ps
CPU time 1.04 seconds
Started Mar 07 02:40:28 PM PST 24
Finished Mar 07 02:40:30 PM PST 24
Peak memory 216896 kb
Host smart-62a9bf00-87bb-4528-b407-e8e9c2c86d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647439340 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.1647439340
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.618814654
Short name T602
Test name
Test status
Simulation time 51532480 ps
CPU time 1.83 seconds
Started Mar 07 02:40:29 PM PST 24
Finished Mar 07 02:40:31 PM PST 24
Peak memory 216832 kb
Host smart-6b4bada8-fc69-472f-b03e-61601ff05076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618814654 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.618814654
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.2095081358
Short name T420
Test name
Test status
Simulation time 52780387 ps
CPU time 0.83 seconds
Started Mar 07 02:40:26 PM PST 24
Finished Mar 07 02:40:28 PM PST 24
Peak memory 214616 kb
Host smart-24c7ce32-de51-40e2-9ac2-074f6e7ce2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095081358 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.2095081358
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.4065349867
Short name T475
Test name
Test status
Simulation time 16416995 ps
CPU time 0.99 seconds
Started Mar 07 02:40:25 PM PST 24
Finished Mar 07 02:40:28 PM PST 24
Peak memory 214380 kb
Host smart-d6b4eed0-3c5e-4063-b49c-41353baf6877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065349867 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.4065349867
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.4181305322
Short name T658
Test name
Test status
Simulation time 113209803 ps
CPU time 1.72 seconds
Started Mar 07 02:40:30 PM PST 24
Finished Mar 07 02:40:32 PM PST 24
Peak memory 214432 kb
Host smart-bd3929ff-aa7e-45ff-9681-012dfeed9c9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181305322 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.4181305322
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.4205801534
Short name T468
Test name
Test status
Simulation time 20003903150 ps
CPU time 135.4 seconds
Started Mar 07 02:40:24 PM PST 24
Finished Mar 07 02:42:42 PM PST 24
Peak memory 216956 kb
Host smart-569246a1-6f42-4f39-aa3b-8c29c15539eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205801534 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.4205801534
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert_test.4050583843
Short name T335
Test name
Test status
Simulation time 17356083 ps
CPU time 0.91 seconds
Started Mar 07 02:40:36 PM PST 24
Finished Mar 07 02:40:37 PM PST 24
Peak memory 205780 kb
Host smart-6cd2a0aa-8e7d-44ad-9dde-dee69a98c675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050583843 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.4050583843
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.2566628745
Short name T782
Test name
Test status
Simulation time 17263596 ps
CPU time 0.88 seconds
Started Mar 07 02:40:34 PM PST 24
Finished Mar 07 02:40:35 PM PST 24
Peak memory 214916 kb
Host smart-b9b3f579-a3a9-4a72-aeae-cc5776ce0cd0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566628745 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.2566628745
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_err.1992838055
Short name T558
Test name
Test status
Simulation time 57297911 ps
CPU time 0.93 seconds
Started Mar 07 02:40:34 PM PST 24
Finished Mar 07 02:40:35 PM PST 24
Peak memory 219392 kb
Host smart-50540330-ba36-4ef0-b43c-56f5548abe12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992838055 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.1992838055
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3158432971
Short name T267
Test name
Test status
Simulation time 74550136 ps
CPU time 1.25 seconds
Started Mar 07 02:40:36 PM PST 24
Finished Mar 07 02:40:37 PM PST 24
Peak memory 215764 kb
Host smart-46518a4f-4247-426c-92c1-989c1533ba44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158432971 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3158432971
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.105310561
Short name T41
Test name
Test status
Simulation time 33131422 ps
CPU time 0.98 seconds
Started Mar 07 02:40:34 PM PST 24
Finished Mar 07 02:40:35 PM PST 24
Peak memory 222404 kb
Host smart-5ac86adb-7ee3-4841-ad2c-33e0ad187f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105310561 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.105310561
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.773148214
Short name T630
Test name
Test status
Simulation time 15662882 ps
CPU time 0.98 seconds
Started Mar 07 02:40:25 PM PST 24
Finished Mar 07 02:40:28 PM PST 24
Peak memory 214436 kb
Host smart-5c50fda2-949b-4f1d-af83-b80a1447029f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773148214 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.773148214
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.897848756
Short name T376
Test name
Test status
Simulation time 613927875 ps
CPU time 2.84 seconds
Started Mar 07 02:40:37 PM PST 24
Finished Mar 07 02:40:40 PM PST 24
Peak memory 215260 kb
Host smart-31c27006-0121-4627-ab67-22a828670f35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897848756 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.897848756
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3608917224
Short name T431
Test name
Test status
Simulation time 46367553346 ps
CPU time 513.01 seconds
Started Mar 07 02:40:33 PM PST 24
Finished Mar 07 02:49:07 PM PST 24
Peak memory 217196 kb
Host smart-051ae87e-7f7a-473a-be2f-2c286ef1616b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608917224 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3608917224
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert.4077260003
Short name T144
Test name
Test status
Simulation time 31183507 ps
CPU time 1.3 seconds
Started Mar 07 02:40:33 PM PST 24
Finished Mar 07 02:40:35 PM PST 24
Peak memory 214804 kb
Host smart-43d837e7-469c-4778-a4e2-59635f874c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077260003 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.4077260003
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/33.edn_alert_test.2726028329
Short name T819
Test name
Test status
Simulation time 48585351 ps
CPU time 0.92 seconds
Started Mar 07 02:40:35 PM PST 24
Finished Mar 07 02:40:37 PM PST 24
Peak memory 205704 kb
Host smart-7011c86b-65ba-43db-ab60-5c4c04e967eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726028329 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.2726028329
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.1170190313
Short name T681
Test name
Test status
Simulation time 12918841 ps
CPU time 0.88 seconds
Started Mar 07 02:40:36 PM PST 24
Finished Mar 07 02:40:37 PM PST 24
Peak memory 214588 kb
Host smart-b82813de-287b-417d-aa8f-ee2db998790b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170190313 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.1170190313
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_err.437569678
Short name T166
Test name
Test status
Simulation time 24002257 ps
CPU time 0.93 seconds
Started Mar 07 02:40:37 PM PST 24
Finished Mar 07 02:40:38 PM PST 24
Peak memory 217220 kb
Host smart-28a5886d-7f5c-49c4-84f8-6fe987e1b83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437569678 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.437569678
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2842131656
Short name T51
Test name
Test status
Simulation time 149129725 ps
CPU time 2.84 seconds
Started Mar 07 02:40:36 PM PST 24
Finished Mar 07 02:40:39 PM PST 24
Peak memory 216964 kb
Host smart-8bf01e31-cd5b-43e3-9bbb-86cd7b56d964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842131656 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2842131656
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.589125747
Short name T759
Test name
Test status
Simulation time 45103360 ps
CPU time 0.87 seconds
Started Mar 07 02:40:39 PM PST 24
Finished Mar 07 02:40:40 PM PST 24
Peak memory 214212 kb
Host smart-b1dca969-fb4e-4219-ac4d-19427c867e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589125747 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.589125747
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.273239008
Short name T409
Test name
Test status
Simulation time 120773740 ps
CPU time 0.91 seconds
Started Mar 07 02:40:35 PM PST 24
Finished Mar 07 02:40:37 PM PST 24
Peak memory 214408 kb
Host smart-a402e2bd-23e5-4cb3-becd-0588b767c290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273239008 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.273239008
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.2715886853
Short name T482
Test name
Test status
Simulation time 538841563 ps
CPU time 3.38 seconds
Started Mar 07 02:40:35 PM PST 24
Finished Mar 07 02:40:39 PM PST 24
Peak memory 215744 kb
Host smart-031da534-5bb7-48ce-b860-d4754236159e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715886853 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.2715886853
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.594518629
Short name T798
Test name
Test status
Simulation time 44860932959 ps
CPU time 1175.56 seconds
Started Mar 07 02:40:34 PM PST 24
Finished Mar 07 03:00:10 PM PST 24
Peak memory 220808 kb
Host smart-14a5845c-9723-43af-b68b-2e7b5863189c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594518629 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.594518629
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert.2231973655
Short name T566
Test name
Test status
Simulation time 26065104 ps
CPU time 1.27 seconds
Started Mar 07 02:40:34 PM PST 24
Finished Mar 07 02:40:36 PM PST 24
Peak memory 214816 kb
Host smart-90c6a68f-8331-420e-8e9f-bb68b3b8923c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231973655 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.2231973655
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/34.edn_alert_test.1271246936
Short name T718
Test name
Test status
Simulation time 52980199 ps
CPU time 0.84 seconds
Started Mar 07 02:40:34 PM PST 24
Finished Mar 07 02:40:35 PM PST 24
Peak memory 206112 kb
Host smart-3668eb58-8b6b-4b27-b259-a3c886ea87e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271246936 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.1271246936
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1425511237
Short name T737
Test name
Test status
Simulation time 10428706 ps
CPU time 0.82 seconds
Started Mar 07 02:40:34 PM PST 24
Finished Mar 07 02:40:35 PM PST 24
Peak memory 214616 kb
Host smart-8c8aab12-e58c-4765-961f-189613859b41
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425511237 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1425511237
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.1364137011
Short name T522
Test name
Test status
Simulation time 43216506 ps
CPU time 1.04 seconds
Started Mar 07 02:40:34 PM PST 24
Finished Mar 07 02:40:35 PM PST 24
Peak memory 216632 kb
Host smart-7b1238cf-96cf-4953-a830-fba19cc0dbec
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364137011 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.1364137011
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.3867308261
Short name T747
Test name
Test status
Simulation time 24605144 ps
CPU time 0.95 seconds
Started Mar 07 02:40:37 PM PST 24
Finished Mar 07 02:40:39 PM PST 24
Peak memory 216932 kb
Host smart-81c62693-d1a7-4198-8fcd-822c11908035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867308261 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.3867308261
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.3200260799
Short name T247
Test name
Test status
Simulation time 37448303 ps
CPU time 1.2 seconds
Started Mar 07 02:40:37 PM PST 24
Finished Mar 07 02:40:39 PM PST 24
Peak memory 216948 kb
Host smart-3650954f-ebb7-4232-94dc-c767c81bc915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200260799 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.3200260799
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.373135509
Short name T508
Test name
Test status
Simulation time 34541446 ps
CPU time 0.85 seconds
Started Mar 07 02:40:32 PM PST 24
Finished Mar 07 02:40:32 PM PST 24
Peak memory 214712 kb
Host smart-e36e956f-6773-4f9f-8d6d-12cde130a46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373135509 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.373135509
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.3470011871
Short name T418
Test name
Test status
Simulation time 16977661 ps
CPU time 1 seconds
Started Mar 07 02:40:36 PM PST 24
Finished Mar 07 02:40:37 PM PST 24
Peak memory 214444 kb
Host smart-50f42666-c7ce-4942-942a-863f64631aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470011871 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.3470011871
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.2257942512
Short name T638
Test name
Test status
Simulation time 330824049 ps
CPU time 1.51 seconds
Started Mar 07 02:40:36 PM PST 24
Finished Mar 07 02:40:38 PM PST 24
Peak memory 215760 kb
Host smart-51fb5e0c-bdaf-4a6e-97a2-ad0bfc76bdc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257942512 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.2257942512
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.1431031041
Short name T632
Test name
Test status
Simulation time 210329513437 ps
CPU time 1182.59 seconds
Started Mar 07 02:40:39 PM PST 24
Finished Mar 07 03:00:22 PM PST 24
Peak memory 222748 kb
Host smart-893098eb-f7a1-4741-8d35-0fcec18b5bf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431031041 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.1431031041
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3442222242
Short name T102
Test name
Test status
Simulation time 79184656 ps
CPU time 1.14 seconds
Started Mar 07 02:40:35 PM PST 24
Finished Mar 07 02:40:37 PM PST 24
Peak memory 214772 kb
Host smart-f1a80570-7361-4381-bd3b-7d15ce694672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442222242 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3442222242
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.497142283
Short name T624
Test name
Test status
Simulation time 25717651 ps
CPU time 0.84 seconds
Started Mar 07 02:40:40 PM PST 24
Finished Mar 07 02:40:41 PM PST 24
Peak memory 205788 kb
Host smart-aab908e7-5e00-4015-b684-b03fe050aa76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497142283 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.497142283
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.3776817141
Short name T586
Test name
Test status
Simulation time 54213640 ps
CPU time 0.84 seconds
Started Mar 07 02:40:35 PM PST 24
Finished Mar 07 02:40:36 PM PST 24
Peak memory 214656 kb
Host smart-9f2c26c1-4f6b-4df7-8a3a-1693063f1a13
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776817141 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.3776817141
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_disable_auto_req_mode.812265920
Short name T762
Test name
Test status
Simulation time 71897929 ps
CPU time 0.98 seconds
Started Mar 07 02:40:35 PM PST 24
Finished Mar 07 02:40:36 PM PST 24
Peak memory 215688 kb
Host smart-4b0f1f13-8185-43e8-817e-580d5cfe5a88
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812265920 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_di
sable_auto_req_mode.812265920
Directory /workspace/35.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/35.edn_err.4133035533
Short name T791
Test name
Test status
Simulation time 76290337 ps
CPU time 1.01 seconds
Started Mar 07 02:40:36 PM PST 24
Finished Mar 07 02:40:37 PM PST 24
Peak memory 218308 kb
Host smart-f155ea94-31b2-416a-9684-b84da999534d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133035533 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.4133035533
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.535168172
Short name T665
Test name
Test status
Simulation time 184068404 ps
CPU time 1.34 seconds
Started Mar 07 02:40:35 PM PST 24
Finished Mar 07 02:40:36 PM PST 24
Peak memory 217532 kb
Host smart-fd0f4d92-1d02-4c0a-bd8c-246d9fc83609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535168172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.535168172
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.4209964681
Short name T778
Test name
Test status
Simulation time 32755769 ps
CPU time 0.85 seconds
Started Mar 07 02:40:37 PM PST 24
Finished Mar 07 02:40:38 PM PST 24
Peak memory 214568 kb
Host smart-a2520517-a4e6-4e7e-86ef-93b96cc4b39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209964681 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.4209964681
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.3791675930
Short name T324
Test name
Test status
Simulation time 22699531 ps
CPU time 0.91 seconds
Started Mar 07 02:40:40 PM PST 24
Finished Mar 07 02:40:41 PM PST 24
Peak memory 214460 kb
Host smart-cfd7f8cd-97f4-4c80-b0ad-fbc4941f61c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791675930 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.3791675930
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.2907055064
Short name T205
Test name
Test status
Simulation time 1040885452 ps
CPU time 3.14 seconds
Started Mar 07 02:40:37 PM PST 24
Finished Mar 07 02:40:40 PM PST 24
Peak memory 215316 kb
Host smart-bbb854a0-eb9f-48ba-a1fb-49faa83817ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907055064 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.2907055064
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2138484596
Short name T587
Test name
Test status
Simulation time 82442268062 ps
CPU time 1509.55 seconds
Started Mar 07 02:40:36 PM PST 24
Finished Mar 07 03:05:46 PM PST 24
Peak memory 222524 kb
Host smart-9ffbac8d-adfb-491c-a4ad-cbe251a54c5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138484596 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2138484596
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.2189597731
Short name T575
Test name
Test status
Simulation time 45232883 ps
CPU time 1.22 seconds
Started Mar 07 02:40:40 PM PST 24
Finished Mar 07 02:40:41 PM PST 24
Peak memory 214832 kb
Host smart-1ac18876-df49-49f8-9370-03ef7fab1004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189597731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.2189597731
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.684180231
Short name T556
Test name
Test status
Simulation time 26911749 ps
CPU time 0.93 seconds
Started Mar 07 02:40:45 PM PST 24
Finished Mar 07 02:40:46 PM PST 24
Peak memory 205740 kb
Host smart-6b97a3db-f037-4489-9a50-f83fbce07c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684180231 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.684180231
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.1343660145
Short name T789
Test name
Test status
Simulation time 89220331 ps
CPU time 0.83 seconds
Started Mar 07 02:40:35 PM PST 24
Finished Mar 07 02:40:36 PM PST 24
Peak memory 214728 kb
Host smart-facf5226-755d-45f0-9ef1-99b37a596a7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343660145 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.1343660145
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_err.1832642333
Short name T571
Test name
Test status
Simulation time 24177044 ps
CPU time 0.94 seconds
Started Mar 07 02:40:34 PM PST 24
Finished Mar 07 02:40:36 PM PST 24
Peak memory 216024 kb
Host smart-da17b9c1-8b2b-4b2b-9f38-41ba92128160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832642333 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1832642333
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.1853362377
Short name T341
Test name
Test status
Simulation time 114885688 ps
CPU time 1.41 seconds
Started Mar 07 02:40:36 PM PST 24
Finished Mar 07 02:40:37 PM PST 24
Peak memory 215600 kb
Host smart-e6cb5011-776b-463d-8a0c-d8cfbc67c3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853362377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.1853362377
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_smoke.1243527091
Short name T758
Test name
Test status
Simulation time 18195787 ps
CPU time 0.95 seconds
Started Mar 07 02:40:36 PM PST 24
Finished Mar 07 02:40:37 PM PST 24
Peak memory 214404 kb
Host smart-a2edeb17-25cc-4a9a-85bc-418cefa9e9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243527091 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.1243527091
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.2358721339
Short name T204
Test name
Test status
Simulation time 171191842 ps
CPU time 2.16 seconds
Started Mar 07 02:40:35 PM PST 24
Finished Mar 07 02:40:37 PM PST 24
Peak memory 215396 kb
Host smart-a51a441b-2b73-4e88-985c-48cec8d6680c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358721339 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.2358721339
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_alert.1596001153
Short name T667
Test name
Test status
Simulation time 120852619 ps
CPU time 1.14 seconds
Started Mar 07 02:40:55 PM PST 24
Finished Mar 07 02:40:56 PM PST 24
Peak memory 214816 kb
Host smart-278120b0-046b-4dea-966a-97bac09207db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596001153 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1596001153
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.4099463659
Short name T661
Test name
Test status
Simulation time 13929888 ps
CPU time 0.89 seconds
Started Mar 07 02:40:46 PM PST 24
Finished Mar 07 02:40:47 PM PST 24
Peak memory 205640 kb
Host smart-14d07b71-4faa-4b03-bc21-4bb131ba2c7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099463659 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.4099463659
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2807166433
Short name T116
Test name
Test status
Simulation time 27071231 ps
CPU time 0.84 seconds
Started Mar 07 02:40:55 PM PST 24
Finished Mar 07 02:40:57 PM PST 24
Peak memory 215040 kb
Host smart-b4b53bdf-25be-4632-9c6f-443fe92a47c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807166433 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2807166433
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_disable_auto_req_mode.1291923583
Short name T68
Test name
Test status
Simulation time 76932560 ps
CPU time 1.28 seconds
Started Mar 07 02:40:44 PM PST 24
Finished Mar 07 02:40:45 PM PST 24
Peak memory 215352 kb
Host smart-da74fdbb-9bd4-4090-8ad6-86d4172c4313
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291923583 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_d
isable_auto_req_mode.1291923583
Directory /workspace/37.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/37.edn_err.75094599
Short name T7
Test name
Test status
Simulation time 55620847 ps
CPU time 1.36 seconds
Started Mar 07 02:40:44 PM PST 24
Finished Mar 07 02:40:45 PM PST 24
Peak memory 232676 kb
Host smart-233555de-21fb-4ff2-bf3a-39c3f0a4aaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75094599 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.75094599
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.3089199721
Short name T601
Test name
Test status
Simulation time 203482258 ps
CPU time 1.02 seconds
Started Mar 07 02:40:47 PM PST 24
Finished Mar 07 02:40:49 PM PST 24
Peak memory 215680 kb
Host smart-4a5131d5-9484-48a1-b971-728d7f353e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089199721 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.3089199721
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.2980033174
Short name T669
Test name
Test status
Simulation time 26010972 ps
CPU time 0.84 seconds
Started Mar 07 02:40:45 PM PST 24
Finished Mar 07 02:40:46 PM PST 24
Peak memory 214612 kb
Host smart-276187d8-4b61-4c98-86c6-8c0210b1008c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980033174 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.2980033174
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.2147232796
Short name T450
Test name
Test status
Simulation time 16148446 ps
CPU time 1.01 seconds
Started Mar 07 02:40:45 PM PST 24
Finished Mar 07 02:40:46 PM PST 24
Peak memory 214444 kb
Host smart-3e7ecd46-d76d-4075-af8b-999c9f9fbdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147232796 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.2147232796
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.2201216186
Short name T559
Test name
Test status
Simulation time 581522181 ps
CPU time 6.22 seconds
Started Mar 07 02:40:45 PM PST 24
Finished Mar 07 02:40:51 PM PST 24
Peak memory 213832 kb
Host smart-7ee78289-c93b-4251-a7a0-967aeb1d0a1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201216186 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.2201216186
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.2943480225
Short name T581
Test name
Test status
Simulation time 61374408541 ps
CPU time 775.41 seconds
Started Mar 07 02:40:56 PM PST 24
Finished Mar 07 02:53:52 PM PST 24
Peak memory 222840 kb
Host smart-a1eab694-4485-42f4-95d8-0765099b3abd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943480225 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.2943480225
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.2885528917
Short name T243
Test name
Test status
Simulation time 301556896 ps
CPU time 1.48 seconds
Started Mar 07 02:40:45 PM PST 24
Finished Mar 07 02:40:47 PM PST 24
Peak memory 214788 kb
Host smart-8dca34db-a8c5-48a1-ac8d-2b1f30b0e8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885528917 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.2885528917
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.3625692720
Short name T706
Test name
Test status
Simulation time 58781564 ps
CPU time 0.83 seconds
Started Mar 07 02:40:56 PM PST 24
Finished Mar 07 02:40:57 PM PST 24
Peak memory 205016 kb
Host smart-f2dac854-6fa4-46a4-b98c-c4188f3dd9cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625692720 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.3625692720
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.712473239
Short name T177
Test name
Test status
Simulation time 71146566 ps
CPU time 0.86 seconds
Started Mar 07 02:40:48 PM PST 24
Finished Mar 07 02:40:49 PM PST 24
Peak memory 214656 kb
Host smart-0b95b557-3f86-4df9-862e-7c349663e0f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712473239 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.712473239
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.2169886400
Short name T67
Test name
Test status
Simulation time 58392735 ps
CPU time 1.19 seconds
Started Mar 07 02:40:45 PM PST 24
Finished Mar 07 02:40:46 PM PST 24
Peak memory 215376 kb
Host smart-ad49f0a2-710d-48f3-8826-7a6ebe0f07cc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169886400 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.2169886400
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.2659925071
Short name T807
Test name
Test status
Simulation time 18721290 ps
CPU time 1.02 seconds
Started Mar 07 02:40:44 PM PST 24
Finished Mar 07 02:40:45 PM PST 24
Peak memory 217176 kb
Host smart-1e490635-1373-4ca4-8aab-d30e2d67bf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659925071 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.2659925071
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.2277788211
Short name T301
Test name
Test status
Simulation time 67106803 ps
CPU time 1.24 seconds
Started Mar 07 02:40:47 PM PST 24
Finished Mar 07 02:40:49 PM PST 24
Peak memory 215808 kb
Host smart-750dae09-d5e2-4a77-8164-38fcc912ad6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277788211 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.2277788211
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.1757929652
Short name T476
Test name
Test status
Simulation time 22833945 ps
CPU time 1.03 seconds
Started Mar 07 02:40:47 PM PST 24
Finished Mar 07 02:40:48 PM PST 24
Peak memory 214796 kb
Host smart-633cd8dc-c67a-47ff-a0d0-ca990c4f1813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757929652 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.1757929652
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.696761961
Short name T799
Test name
Test status
Simulation time 22722285 ps
CPU time 0.92 seconds
Started Mar 07 02:40:45 PM PST 24
Finished Mar 07 02:40:46 PM PST 24
Peak memory 213716 kb
Host smart-6633e425-e158-4674-9203-f35885cd2b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696761961 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.696761961
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.1128229044
Short name T207
Test name
Test status
Simulation time 21375457 ps
CPU time 1.02 seconds
Started Mar 07 02:40:47 PM PST 24
Finished Mar 07 02:40:48 PM PST 24
Peak memory 205024 kb
Host smart-e78eaac7-fc8e-48c0-a6f7-b264ee27b01b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128229044 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.1128229044
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.937456204
Short name T140
Test name
Test status
Simulation time 818058758137 ps
CPU time 1913.2 seconds
Started Mar 07 02:40:44 PM PST 24
Finished Mar 07 03:12:38 PM PST 24
Peak memory 224168 kb
Host smart-ff5387cd-f17d-44f0-9c6b-8c37ebd39d3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937456204 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.937456204
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.2525437111
Short name T832
Test name
Test status
Simulation time 99210059 ps
CPU time 1.14 seconds
Started Mar 07 02:40:54 PM PST 24
Finished Mar 07 02:40:56 PM PST 24
Peak memory 214816 kb
Host smart-2d6286ff-2392-4e9d-9234-1db069570721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525437111 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.2525437111
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.1060238920
Short name T643
Test name
Test status
Simulation time 36709461 ps
CPU time 0.88 seconds
Started Mar 07 02:40:56 PM PST 24
Finished Mar 07 02:40:57 PM PST 24
Peak memory 205000 kb
Host smart-7e81ab27-8187-427b-aaa8-cd2d959a6ba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060238920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.1060238920
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable.2118639209
Short name T154
Test name
Test status
Simulation time 12057398 ps
CPU time 0.84 seconds
Started Mar 07 02:40:55 PM PST 24
Finished Mar 07 02:40:56 PM PST 24
Peak memory 214924 kb
Host smart-b41873c0-65b0-4419-9f70-c7b857b571c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118639209 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2118639209
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/39.edn_err.1196591217
Short name T113
Test name
Test status
Simulation time 24788642 ps
CPU time 0.97 seconds
Started Mar 07 02:40:45 PM PST 24
Finished Mar 07 02:40:46 PM PST 24
Peak memory 217184 kb
Host smart-7e67ed26-02a5-473d-807a-f5bba485fc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196591217 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1196591217
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.614415390
Short name T564
Test name
Test status
Simulation time 106701356 ps
CPU time 2.14 seconds
Started Mar 07 02:40:44 PM PST 24
Finished Mar 07 02:40:46 PM PST 24
Peak memory 214460 kb
Host smart-eaf23ed9-b9f5-4f31-ac0b-3867b9668407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614415390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.614415390
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.309626126
Short name T610
Test name
Test status
Simulation time 21145387 ps
CPU time 1.18 seconds
Started Mar 07 02:40:55 PM PST 24
Finished Mar 07 02:40:56 PM PST 24
Peak memory 231852 kb
Host smart-de766092-5193-4637-bf38-14e18bf9353c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309626126 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.309626126
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/default/39.edn_smoke.2667657472
Short name T625
Test name
Test status
Simulation time 43735628 ps
CPU time 0.9 seconds
Started Mar 07 02:40:44 PM PST 24
Finished Mar 07 02:40:45 PM PST 24
Peak memory 214360 kb
Host smart-18d65fd9-b547-4cfc-8d85-bd1fb6d2b972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667657472 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.2667657472
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.109163870
Short name T633
Test name
Test status
Simulation time 96262043 ps
CPU time 2.29 seconds
Started Mar 07 02:40:46 PM PST 24
Finished Mar 07 02:40:49 PM PST 24
Peak memory 214464 kb
Host smart-884ab3eb-379a-41c1-866c-27bd82e715c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109163870 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.109163870
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.779288220
Short name T350
Test name
Test status
Simulation time 177296571317 ps
CPU time 1786.39 seconds
Started Mar 07 02:40:46 PM PST 24
Finished Mar 07 03:10:33 PM PST 24
Peak memory 225836 kb
Host smart-61a491d1-cfde-4cc2-90eb-2586c1584a8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779288220 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.779288220
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.363990222
Short name T262
Test name
Test status
Simulation time 47309274 ps
CPU time 1.21 seconds
Started Mar 07 02:38:51 PM PST 24
Finished Mar 07 02:38:52 PM PST 24
Peak memory 214800 kb
Host smart-7cf14e11-2098-49aa-974b-33a3b59e08b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363990222 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.363990222
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.2529407107
Short name T372
Test name
Test status
Simulation time 33920503 ps
CPU time 0.98 seconds
Started Mar 07 02:38:53 PM PST 24
Finished Mar 07 02:38:55 PM PST 24
Peak memory 206164 kb
Host smart-e4f252e1-750e-4e18-93a7-46a93206945f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529407107 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.2529407107
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.3308557023
Short name T119
Test name
Test status
Simulation time 59432627 ps
CPU time 0.8 seconds
Started Mar 07 02:38:53 PM PST 24
Finished Mar 07 02:38:54 PM PST 24
Peak memory 214812 kb
Host smart-2f3f5a2f-102a-47d3-a14b-8fe1f8d50ac4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308557023 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.3308557023
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2881517648
Short name T164
Test name
Test status
Simulation time 140379320 ps
CPU time 1.49 seconds
Started Mar 07 02:38:53 PM PST 24
Finished Mar 07 02:38:54 PM PST 24
Peak memory 218276 kb
Host smart-20ebf2f0-0777-43ce-b81c-b7eb12cdb777
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881517648 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2881517648
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_err.3401633461
Short name T99
Test name
Test status
Simulation time 33985854 ps
CPU time 1 seconds
Started Mar 07 02:38:52 PM PST 24
Finished Mar 07 02:38:53 PM PST 24
Peak memory 230428 kb
Host smart-6f96dbc7-89fd-4710-a44d-03f5cf14b648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401633461 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.3401633461
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.2975235203
Short name T294
Test name
Test status
Simulation time 28652056 ps
CPU time 1.36 seconds
Started Mar 07 02:38:50 PM PST 24
Finished Mar 07 02:38:52 PM PST 24
Peak memory 216892 kb
Host smart-58ae5e09-481f-4dc9-b64e-9899866c78bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975235203 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.2975235203
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.255882463
Short name T40
Test name
Test status
Simulation time 31856248 ps
CPU time 0.88 seconds
Started Mar 07 02:38:49 PM PST 24
Finished Mar 07 02:38:50 PM PST 24
Peak memory 214604 kb
Host smart-8d3883f1-7839-4f9f-ba75-385ebf65dbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255882463 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.255882463
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.116613447
Short name T803
Test name
Test status
Simulation time 19091861 ps
CPU time 0.99 seconds
Started Mar 07 02:38:51 PM PST 24
Finished Mar 07 02:38:52 PM PST 24
Peak memory 206168 kb
Host smart-cbfa5648-c5df-4d8e-ad97-949b18f4a976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116613447 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.116613447
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.417828981
Short name T554
Test name
Test status
Simulation time 72883662 ps
CPU time 0.91 seconds
Started Mar 07 02:38:51 PM PST 24
Finished Mar 07 02:38:52 PM PST 24
Peak memory 214424 kb
Host smart-89a93980-fdf6-4269-bf23-c1cd5537fab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417828981 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.417828981
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.1212529952
Short name T478
Test name
Test status
Simulation time 422755432 ps
CPU time 2.59 seconds
Started Mar 07 02:38:51 PM PST 24
Finished Mar 07 02:38:53 PM PST 24
Peak memory 215764 kb
Host smart-e702bdae-29a3-4af4-a61f-73ab76f3d975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212529952 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.1212529952
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.2572101333
Short name T402
Test name
Test status
Simulation time 199090177805 ps
CPU time 1655.49 seconds
Started Mar 07 02:38:51 PM PST 24
Finished Mar 07 03:06:27 PM PST 24
Peak memory 226212 kb
Host smart-b709e4d2-9b2d-429a-9dc6-8899c401df98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572101333 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.2572101333
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.4098542833
Short name T14
Test name
Test status
Simulation time 24274977 ps
CPU time 1.1 seconds
Started Mar 07 02:41:01 PM PST 24
Finished Mar 07 02:41:02 PM PST 24
Peak memory 214868 kb
Host smart-0c3d1511-a50e-4459-9ae1-0014460876a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098542833 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.4098542833
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.2414442764
Short name T38
Test name
Test status
Simulation time 36144991 ps
CPU time 0.91 seconds
Started Mar 07 02:41:05 PM PST 24
Finished Mar 07 02:41:06 PM PST 24
Peak memory 205792 kb
Host smart-3bbc5636-4154-41da-8aef-97479bf013f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414442764 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.2414442764
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.204760898
Short name T200
Test name
Test status
Simulation time 12658978 ps
CPU time 0.87 seconds
Started Mar 07 02:40:53 PM PST 24
Finished Mar 07 02:40:54 PM PST 24
Peak memory 215048 kb
Host smart-3b616249-3d86-4e85-b0a3-fd87a6ef0fb5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204760898 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.204760898
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.874234490
Short name T595
Test name
Test status
Simulation time 53226554 ps
CPU time 1.08 seconds
Started Mar 07 02:40:54 PM PST 24
Finished Mar 07 02:40:55 PM PST 24
Peak memory 216864 kb
Host smart-c03f86c5-e39f-44dd-87e7-f7d1ee54e94c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874234490 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_di
sable_auto_req_mode.874234490
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/40.edn_err.3159295075
Short name T95
Test name
Test status
Simulation time 35410764 ps
CPU time 1.14 seconds
Started Mar 07 02:40:55 PM PST 24
Finished Mar 07 02:40:56 PM PST 24
Peak memory 218168 kb
Host smart-20882586-917e-446c-bef9-c62444f77ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159295075 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.3159295075
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2695793932
Short name T366
Test name
Test status
Simulation time 34119762 ps
CPU time 1.36 seconds
Started Mar 07 02:40:44 PM PST 24
Finished Mar 07 02:40:45 PM PST 24
Peak memory 216748 kb
Host smart-04e6fcaa-819b-4128-847e-3fdca82bf0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695793932 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2695793932
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.1551250683
Short name T56
Test name
Test status
Simulation time 62298356 ps
CPU time 0.86 seconds
Started Mar 07 02:40:53 PM PST 24
Finished Mar 07 02:40:54 PM PST 24
Peak memory 214640 kb
Host smart-702e2522-cd6d-4a10-918e-2a35e1feba84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551250683 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.1551250683
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.3917029572
Short name T394
Test name
Test status
Simulation time 48403257 ps
CPU time 0.91 seconds
Started Mar 07 02:40:43 PM PST 24
Finished Mar 07 02:40:44 PM PST 24
Peak memory 214404 kb
Host smart-3859709e-0dd2-46b8-a454-1653fd370ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917029572 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.3917029572
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.3326308151
Short name T275
Test name
Test status
Simulation time 159128959 ps
CPU time 3.53 seconds
Started Mar 07 02:40:55 PM PST 24
Finished Mar 07 02:40:58 PM PST 24
Peak memory 215504 kb
Host smart-d13bbc77-2f60-4249-8250-82cdda99cfb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326308151 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.3326308151
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.812670028
Short name T184
Test name
Test status
Simulation time 12667612083 ps
CPU time 277.12 seconds
Started Mar 07 02:40:55 PM PST 24
Finished Mar 07 02:45:32 PM PST 24
Peak memory 217112 kb
Host smart-44a4c5e6-3c82-4960-9617-03c0535a61cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812670028 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.812670028
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.2083406217
Short name T122
Test name
Test status
Simulation time 167180224 ps
CPU time 1.27 seconds
Started Mar 07 02:40:53 PM PST 24
Finished Mar 07 02:40:55 PM PST 24
Peak memory 214792 kb
Host smart-9356e5be-a3f3-4d61-8070-13c3eafb1ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083406217 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.2083406217
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.1765260644
Short name T467
Test name
Test status
Simulation time 37849687 ps
CPU time 0.83 seconds
Started Mar 07 02:40:54 PM PST 24
Finished Mar 07 02:40:55 PM PST 24
Peak memory 204980 kb
Host smart-604835eb-f485-4d5c-84ae-37b81215ee9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765260644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.1765260644
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.4097523657
Short name T547
Test name
Test status
Simulation time 215406359 ps
CPU time 1.07 seconds
Started Mar 07 02:40:54 PM PST 24
Finished Mar 07 02:40:55 PM PST 24
Peak memory 215388 kb
Host smart-9094f978-0b9c-446d-9751-74c9bc9e9f8a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097523657 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_d
isable_auto_req_mode.4097523657
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.2782342584
Short name T830
Test name
Test status
Simulation time 34939223 ps
CPU time 1.07 seconds
Started Mar 07 02:40:53 PM PST 24
Finished Mar 07 02:40:54 PM PST 24
Peak memory 219196 kb
Host smart-1c956d18-4670-480a-92e4-1a7236a27ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782342584 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.2782342584
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.1173025798
Short name T440
Test name
Test status
Simulation time 98303807 ps
CPU time 1.14 seconds
Started Mar 07 02:40:53 PM PST 24
Finished Mar 07 02:40:54 PM PST 24
Peak memory 215748 kb
Host smart-a49f491f-7111-461f-b61e-223ba0912a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173025798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.1173025798
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.1755440611
Short name T44
Test name
Test status
Simulation time 20914038 ps
CPU time 1.17 seconds
Started Mar 07 02:40:55 PM PST 24
Finished Mar 07 02:40:56 PM PST 24
Peak memory 222292 kb
Host smart-94aa4d22-14b8-4864-b06f-4da23e5a488c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755440611 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.1755440611
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.1964755927
Short name T663
Test name
Test status
Simulation time 22786411 ps
CPU time 0.88 seconds
Started Mar 07 02:40:56 PM PST 24
Finished Mar 07 02:40:57 PM PST 24
Peak memory 214400 kb
Host smart-7b6dc341-f5a8-45c6-9fab-ba9c7841e24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964755927 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.1964755927
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.1807965882
Short name T401
Test name
Test status
Simulation time 90947093 ps
CPU time 1.13 seconds
Started Mar 07 02:40:54 PM PST 24
Finished Mar 07 02:40:55 PM PST 24
Peak memory 214464 kb
Host smart-9ae0d022-04df-4e97-84a7-7b2947f3dd1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807965882 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.1807965882
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.639575316
Short name T194
Test name
Test status
Simulation time 410670046657 ps
CPU time 2459.7 seconds
Started Mar 07 02:40:54 PM PST 24
Finished Mar 07 03:21:54 PM PST 24
Peak memory 226100 kb
Host smart-ab2c301a-199c-4d98-b29a-5dc131625fa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639575316 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.639575316
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.2851304767
Short name T263
Test name
Test status
Simulation time 50446986 ps
CPU time 1.21 seconds
Started Mar 07 02:41:03 PM PST 24
Finished Mar 07 02:41:05 PM PST 24
Peak memory 214696 kb
Host smart-afef5d35-9098-4ba4-996d-2e25f062e7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851304767 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.2851304767
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.2094902065
Short name T426
Test name
Test status
Simulation time 24562051 ps
CPU time 0.9 seconds
Started Mar 07 02:41:05 PM PST 24
Finished Mar 07 02:41:06 PM PST 24
Peak memory 205708 kb
Host smart-5b5b3084-94ac-4c0c-994a-8548d70a61fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094902065 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.2094902065
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.3993629817
Short name T120
Test name
Test status
Simulation time 11628949 ps
CPU time 0.87 seconds
Started Mar 07 02:41:04 PM PST 24
Finished Mar 07 02:41:05 PM PST 24
Peak memory 214840 kb
Host smart-e97fb970-f59d-43ba-a559-2e315a278c4d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993629817 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.3993629817
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.2068791725
Short name T462
Test name
Test status
Simulation time 169994173 ps
CPU time 1.15 seconds
Started Mar 07 02:41:05 PM PST 24
Finished Mar 07 02:41:06 PM PST 24
Peak memory 215560 kb
Host smart-225c857e-9054-465e-a775-8647e1eb01f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068791725 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_d
isable_auto_req_mode.2068791725
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.4197786852
Short name T57
Test name
Test status
Simulation time 43397820 ps
CPU time 0.89 seconds
Started Mar 07 02:41:05 PM PST 24
Finished Mar 07 02:41:06 PM PST 24
Peak memory 217068 kb
Host smart-cc19dc40-0827-47ab-88f9-4ecd9a56800f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197786852 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.4197786852
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.3049898793
Short name T594
Test name
Test status
Simulation time 52145857 ps
CPU time 1.6 seconds
Started Mar 07 02:40:54 PM PST 24
Finished Mar 07 02:40:56 PM PST 24
Peak memory 216860 kb
Host smart-1363cd3e-5d66-4eff-b317-674472bfa835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049898793 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.3049898793
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3500675553
Short name T59
Test name
Test status
Simulation time 23223360 ps
CPU time 0.97 seconds
Started Mar 07 02:41:05 PM PST 24
Finished Mar 07 02:41:06 PM PST 24
Peak memory 214772 kb
Host smart-8833893f-1e8d-40cc-a8cc-5c6a49da777b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500675553 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3500675553
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.4202017682
Short name T739
Test name
Test status
Simulation time 157242300 ps
CPU time 0.94 seconds
Started Mar 07 02:41:03 PM PST 24
Finished Mar 07 02:41:05 PM PST 24
Peak memory 214348 kb
Host smart-783f64f7-4c21-4594-8b6e-04d7b2040d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202017682 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.4202017682
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.221157382
Short name T741
Test name
Test status
Simulation time 252286676 ps
CPU time 4.87 seconds
Started Mar 07 02:41:04 PM PST 24
Finished Mar 07 02:41:09 PM PST 24
Peak memory 215536 kb
Host smart-a0efc89c-f4b4-463d-a108-20961c9300fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221157382 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.221157382
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.145528626
Short name T379
Test name
Test status
Simulation time 41418069062 ps
CPU time 549.39 seconds
Started Mar 07 02:41:04 PM PST 24
Finished Mar 07 02:50:13 PM PST 24
Peak memory 216860 kb
Host smart-43240c2a-c760-47c4-b52d-97d0393df680
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145528626 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.145528626
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.2213312156
Short name T178
Test name
Test status
Simulation time 52782770 ps
CPU time 1.26 seconds
Started Mar 07 02:41:04 PM PST 24
Finished Mar 07 02:41:05 PM PST 24
Peak memory 214772 kb
Host smart-2eae0d36-ade0-410c-a111-1871fe597163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213312156 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.2213312156
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.255890147
Short name T39
Test name
Test status
Simulation time 40804431 ps
CPU time 0.82 seconds
Started Mar 07 02:41:03 PM PST 24
Finished Mar 07 02:41:04 PM PST 24
Peak memory 206040 kb
Host smart-fa33cabe-1377-4e5a-9efd-34ea9e5abcdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255890147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.255890147
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2171569386
Short name T536
Test name
Test status
Simulation time 36461621 ps
CPU time 0.85 seconds
Started Mar 07 02:41:05 PM PST 24
Finished Mar 07 02:41:06 PM PST 24
Peak memory 214880 kb
Host smart-13081ba6-99fc-40e3-afa3-893b871537db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171569386 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2171569386
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_err.3751324001
Short name T831
Test name
Test status
Simulation time 23296284 ps
CPU time 1.02 seconds
Started Mar 07 02:41:06 PM PST 24
Finished Mar 07 02:41:07 PM PST 24
Peak memory 230572 kb
Host smart-98226801-fdb2-448d-b741-3a88ef5fd976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751324001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.3751324001
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.3521127531
Short name T835
Test name
Test status
Simulation time 75033702 ps
CPU time 1.19 seconds
Started Mar 07 02:41:05 PM PST 24
Finished Mar 07 02:41:06 PM PST 24
Peak memory 218444 kb
Host smart-f24d6309-f49f-4e09-ae1f-77cd690a181e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521127531 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.3521127531
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3574637804
Short name T520
Test name
Test status
Simulation time 26317835 ps
CPU time 0.94 seconds
Started Mar 07 02:41:06 PM PST 24
Finished Mar 07 02:41:07 PM PST 24
Peak memory 214576 kb
Host smart-d8c25b99-2211-416f-833e-f486bd11bbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574637804 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3574637804
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1220390388
Short name T809
Test name
Test status
Simulation time 160133558 ps
CPU time 0.83 seconds
Started Mar 07 02:41:04 PM PST 24
Finished Mar 07 02:41:05 PM PST 24
Peak memory 214320 kb
Host smart-0685e89a-d9bb-445e-8c1d-977a9f03b6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220390388 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1220390388
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.3877744050
Short name T528
Test name
Test status
Simulation time 724977030 ps
CPU time 3.28 seconds
Started Mar 07 02:41:05 PM PST 24
Finished Mar 07 02:41:09 PM PST 24
Peak memory 215576 kb
Host smart-1371e8f2-3201-4e3e-8368-4dd8f0e4336d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877744050 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.3877744050
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.2836930575
Short name T192
Test name
Test status
Simulation time 116910574053 ps
CPU time 2336.07 seconds
Started Mar 07 02:41:03 PM PST 24
Finished Mar 07 03:19:59 PM PST 24
Peak memory 225868 kb
Host smart-58a46cfa-aaa2-4698-8f21-dd35a9b84ba9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836930575 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.2836930575
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2545043693
Short name T242
Test name
Test status
Simulation time 27224656 ps
CPU time 1.27 seconds
Started Mar 07 02:41:03 PM PST 24
Finished Mar 07 02:41:05 PM PST 24
Peak memory 214792 kb
Host smart-6da73ecc-3baa-4694-be37-b801dfad0658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545043693 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2545043693
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.1994053629
Short name T714
Test name
Test status
Simulation time 23971945 ps
CPU time 0.97 seconds
Started Mar 07 02:41:06 PM PST 24
Finished Mar 07 02:41:07 PM PST 24
Peak memory 206068 kb
Host smart-4ed3e3e2-2d74-4713-92c0-9c989066fca1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994053629 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.1994053629
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.2808562523
Short name T507
Test name
Test status
Simulation time 15886581 ps
CPU time 0.81 seconds
Started Mar 07 02:41:06 PM PST 24
Finished Mar 07 02:41:06 PM PST 24
Peak memory 214744 kb
Host smart-0478b26c-d596-4bd7-bcbc-d8019aa3340a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808562523 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.2808562523
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_err.299829524
Short name T73
Test name
Test status
Simulation time 41334315 ps
CPU time 1 seconds
Started Mar 07 02:41:05 PM PST 24
Finished Mar 07 02:41:06 PM PST 24
Peak memory 218344 kb
Host smart-c8ad486c-943f-49ab-9e66-6611d4975c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299829524 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.299829524
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.1854455268
Short name T742
Test name
Test status
Simulation time 86487593 ps
CPU time 1.18 seconds
Started Mar 07 02:41:04 PM PST 24
Finished Mar 07 02:41:06 PM PST 24
Peak memory 214308 kb
Host smart-fe344af8-89c1-4b8e-81ce-8fe99fedc980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854455268 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.1854455268
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.1616545280
Short name T129
Test name
Test status
Simulation time 33993695 ps
CPU time 0.89 seconds
Started Mar 07 02:41:04 PM PST 24
Finished Mar 07 02:41:05 PM PST 24
Peak memory 214672 kb
Host smart-fd08f567-1958-4ce2-b0d8-8becb1605488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616545280 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.1616545280
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.231168215
Short name T147
Test name
Test status
Simulation time 76447741 ps
CPU time 0.88 seconds
Started Mar 07 02:41:07 PM PST 24
Finished Mar 07 02:41:08 PM PST 24
Peak memory 214440 kb
Host smart-b6268bb6-2268-4c0d-950a-4f563309a502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231168215 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.231168215
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.1968094858
Short name T524
Test name
Test status
Simulation time 352404506 ps
CPU time 3.66 seconds
Started Mar 07 02:41:03 PM PST 24
Finished Mar 07 02:41:07 PM PST 24
Peak memory 215592 kb
Host smart-1279d34d-f3fa-4c5f-8dad-334da0fc59ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968094858 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.1968094858
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.597049900
Short name T684
Test name
Test status
Simulation time 98841092866 ps
CPU time 1377.67 seconds
Started Mar 07 02:41:04 PM PST 24
Finished Mar 07 03:04:02 PM PST 24
Peak memory 224108 kb
Host smart-ff8e0b5f-6a06-4da7-a3f1-b0b498323d32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597049900 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.597049900
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.49889928
Short name T174
Test name
Test status
Simulation time 84988763 ps
CPU time 1.26 seconds
Started Mar 07 02:41:16 PM PST 24
Finished Mar 07 02:41:17 PM PST 24
Peak memory 214836 kb
Host smart-0ee87407-98ba-4063-ac99-754dc70d180b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49889928 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.49889928
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.969500361
Short name T433
Test name
Test status
Simulation time 134226788 ps
CPU time 0.84 seconds
Started Mar 07 02:41:18 PM PST 24
Finished Mar 07 02:41:19 PM PST 24
Peak memory 205976 kb
Host smart-683162f6-67d1-4270-b797-460cb2a3be15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969500361 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.969500361
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.3094568067
Short name T93
Test name
Test status
Simulation time 37793714 ps
CPU time 1.03 seconds
Started Mar 07 02:41:19 PM PST 24
Finished Mar 07 02:41:20 PM PST 24
Peak memory 215644 kb
Host smart-7ce8d011-24c0-4e35-ae58-d204224d72aa
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094568067 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.3094568067
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_err.3195772811
Short name T114
Test name
Test status
Simulation time 97461388 ps
CPU time 0.8 seconds
Started Mar 07 02:41:17 PM PST 24
Finished Mar 07 02:41:18 PM PST 24
Peak memory 216916 kb
Host smart-1e8ef93b-c1a1-43fa-bcbc-4071fd2c94ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195772811 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.3195772811
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/45.edn_genbits.3497604304
Short name T12
Test name
Test status
Simulation time 80860154 ps
CPU time 1.19 seconds
Started Mar 07 02:41:03 PM PST 24
Finished Mar 07 02:41:04 PM PST 24
Peak memory 218084 kb
Host smart-7982ff2c-9662-4760-a314-68d7d61b3545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497604304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.3497604304
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3900666172
Short name T131
Test name
Test status
Simulation time 56955119 ps
CPU time 0.83 seconds
Started Mar 07 02:41:19 PM PST 24
Finished Mar 07 02:41:20 PM PST 24
Peak memory 214656 kb
Host smart-04635957-2445-4538-80f4-597e940eadfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900666172 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3900666172
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.1773441533
Short name T380
Test name
Test status
Simulation time 36653757 ps
CPU time 0.89 seconds
Started Mar 07 02:41:03 PM PST 24
Finished Mar 07 02:41:04 PM PST 24
Peak memory 206200 kb
Host smart-4c783979-e8c9-44dc-bfb3-012a7090076a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773441533 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.1773441533
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.1570432544
Short name T395
Test name
Test status
Simulation time 147208847 ps
CPU time 1.44 seconds
Started Mar 07 02:41:16 PM PST 24
Finished Mar 07 02:41:17 PM PST 24
Peak memory 215416 kb
Host smart-aeed6fd7-6f1a-4d61-9ec2-088923bd8a00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570432544 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.1570432544
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3107845950
Short name T24
Test name
Test status
Simulation time 131216425994 ps
CPU time 732.2 seconds
Started Mar 07 02:41:16 PM PST 24
Finished Mar 07 02:53:28 PM PST 24
Peak memory 222864 kb
Host smart-5a44394b-dc97-43c6-b4b9-20cb07e4cb63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107845950 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3107845950
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.1399984901
Short name T793
Test name
Test status
Simulation time 72939007 ps
CPU time 1.17 seconds
Started Mar 07 02:41:17 PM PST 24
Finished Mar 07 02:41:18 PM PST 24
Peak memory 214740 kb
Host smart-e2c01bae-f38c-4739-b514-96513f112a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399984901 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.1399984901
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.4203538774
Short name T382
Test name
Test status
Simulation time 18892608 ps
CPU time 0.93 seconds
Started Mar 07 02:41:16 PM PST 24
Finished Mar 07 02:41:17 PM PST 24
Peak memory 205768 kb
Host smart-bec37bc7-2219-48d6-955a-eecadf63db5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203538774 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.4203538774
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.1775240025
Short name T183
Test name
Test status
Simulation time 21359053 ps
CPU time 0.87 seconds
Started Mar 07 02:41:17 PM PST 24
Finished Mar 07 02:41:18 PM PST 24
Peak memory 214596 kb
Host smart-f1a7a176-cabd-43e9-8ada-1c2c1d09c73b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775240025 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.1775240025
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.3968734743
Short name T60
Test name
Test status
Simulation time 106953580 ps
CPU time 1.27 seconds
Started Mar 07 02:41:18 PM PST 24
Finished Mar 07 02:41:19 PM PST 24
Peak memory 215448 kb
Host smart-0586880e-6b1c-4ddb-b41b-6b9c5ee3bd87
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968734743 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.3968734743
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.4137761564
Short name T58
Test name
Test status
Simulation time 19030291 ps
CPU time 0.99 seconds
Started Mar 07 02:41:16 PM PST 24
Finished Mar 07 02:41:17 PM PST 24
Peak memory 216984 kb
Host smart-d03e6871-7fe4-4c54-8c9f-59ac415ae4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137761564 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.4137761564
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.399759010
Short name T150
Test name
Test status
Simulation time 302856899 ps
CPU time 1.95 seconds
Started Mar 07 02:41:17 PM PST 24
Finished Mar 07 02:41:19 PM PST 24
Peak memory 217072 kb
Host smart-12655ee5-6890-4dfe-82b0-36d79f957f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399759010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.399759010
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.828355162
Short name T128
Test name
Test status
Simulation time 23987299 ps
CPU time 0.92 seconds
Started Mar 07 02:41:19 PM PST 24
Finished Mar 07 02:41:20 PM PST 24
Peak memory 214720 kb
Host smart-fd54934e-670f-4e9c-aa98-ec26cf218901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828355162 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.828355162
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.3783576260
Short name T668
Test name
Test status
Simulation time 24614028 ps
CPU time 0.97 seconds
Started Mar 07 02:41:19 PM PST 24
Finished Mar 07 02:41:20 PM PST 24
Peak memory 214440 kb
Host smart-cd184c83-dc3e-4642-8846-c50995694c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783576260 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.3783576260
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.1100027495
Short name T481
Test name
Test status
Simulation time 312881469 ps
CPU time 1.38 seconds
Started Mar 07 02:41:18 PM PST 24
Finished Mar 07 02:41:19 PM PST 24
Peak memory 214356 kb
Host smart-c10d65a6-0082-4826-a0e8-e9ef7c1063ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100027495 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.1100027495
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1147635575
Short name T399
Test name
Test status
Simulation time 8944039828 ps
CPU time 215.07 seconds
Started Mar 07 02:41:17 PM PST 24
Finished Mar 07 02:44:52 PM PST 24
Peak memory 216444 kb
Host smart-a04a95be-701c-49c3-ad82-3733f0dbc462
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147635575 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1147635575
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.1403371714
Short name T255
Test name
Test status
Simulation time 25708644 ps
CPU time 1.22 seconds
Started Mar 07 02:41:17 PM PST 24
Finished Mar 07 02:41:19 PM PST 24
Peak memory 214688 kb
Host smart-0821c583-183e-4b1d-9761-da07bccc90cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403371714 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.1403371714
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.1214713612
Short name T612
Test name
Test status
Simulation time 53902414 ps
CPU time 0.91 seconds
Started Mar 07 02:41:20 PM PST 24
Finished Mar 07 02:41:21 PM PST 24
Peak memory 206068 kb
Host smart-386a70bd-4555-4bf8-8529-413b8e9b05ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214713612 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.1214713612
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable.47665515
Short name T723
Test name
Test status
Simulation time 22594443 ps
CPU time 0.92 seconds
Started Mar 07 02:41:19 PM PST 24
Finished Mar 07 02:41:20 PM PST 24
Peak memory 214724 kb
Host smart-bf5bf67c-63ed-4d65-8376-641da202ff27
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47665515 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.47665515
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/47.edn_err.2735479837
Short name T531
Test name
Test status
Simulation time 18047229 ps
CPU time 1.15 seconds
Started Mar 07 02:41:20 PM PST 24
Finished Mar 07 02:41:21 PM PST 24
Peak memory 216824 kb
Host smart-e159d6f8-ffa2-4197-b33d-ad68af632af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735479837 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.2735479837
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.886272577
Short name T530
Test name
Test status
Simulation time 33710923 ps
CPU time 1.16 seconds
Started Mar 07 02:41:15 PM PST 24
Finished Mar 07 02:41:16 PM PST 24
Peak memory 215724 kb
Host smart-7f205a6f-1e6c-4cff-afd4-5c6901ae7c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886272577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.886272577
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.3708364245
Short name T743
Test name
Test status
Simulation time 22742769 ps
CPU time 0.93 seconds
Started Mar 07 02:41:19 PM PST 24
Finished Mar 07 02:41:20 PM PST 24
Peak memory 214788 kb
Host smart-d3224b8e-0d8e-4bbe-9d97-49cd491b555c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708364245 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.3708364245
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1544596433
Short name T631
Test name
Test status
Simulation time 25082898 ps
CPU time 0.91 seconds
Started Mar 07 02:41:17 PM PST 24
Finished Mar 07 02:41:18 PM PST 24
Peak memory 214380 kb
Host smart-b974f16b-e3bb-42ae-8561-d85b7ac2b5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544596433 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1544596433
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.547095494
Short name T438
Test name
Test status
Simulation time 625518545 ps
CPU time 1.48 seconds
Started Mar 07 02:41:20 PM PST 24
Finished Mar 07 02:41:22 PM PST 24
Peak memory 214412 kb
Host smart-7602d839-aebd-4513-808c-9ed37fa2ffde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547095494 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.547095494
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.2006078851
Short name T195
Test name
Test status
Simulation time 51453239921 ps
CPU time 1170.18 seconds
Started Mar 07 02:41:20 PM PST 24
Finished Mar 07 03:00:50 PM PST 24
Peak memory 217992 kb
Host smart-b78a32c9-f1d5-42d5-9e0c-2b68335f2d1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006078851 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.2006078851
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.edn_alert.1023311720
Short name T180
Test name
Test status
Simulation time 196799301 ps
CPU time 1.21 seconds
Started Mar 07 02:41:20 PM PST 24
Finished Mar 07 02:41:22 PM PST 24
Peak memory 214752 kb
Host smart-b6691973-75cb-42be-a151-2accac575c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023311720 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.1023311720
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.4252612610
Short name T422
Test name
Test status
Simulation time 52479784 ps
CPU time 0.94 seconds
Started Mar 07 02:41:20 PM PST 24
Finished Mar 07 02:41:21 PM PST 24
Peak memory 206040 kb
Host smart-e66956ad-d5c3-4256-98a3-4a2956dcc072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252612610 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.4252612610
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2542193659
Short name T515
Test name
Test status
Simulation time 24082833 ps
CPU time 0.88 seconds
Started Mar 07 02:41:20 PM PST 24
Finished Mar 07 02:41:21 PM PST 24
Peak memory 214832 kb
Host smart-da9c20c2-6658-4fcc-ae63-afdb6f6e9c60
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542193659 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2542193659
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.347485974
Short name T615
Test name
Test status
Simulation time 49926437 ps
CPU time 1.34 seconds
Started Mar 07 02:41:21 PM PST 24
Finished Mar 07 02:41:22 PM PST 24
Peak memory 218028 kb
Host smart-a52c868a-5479-45aa-a75a-908e0c1137dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347485974 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_di
sable_auto_req_mode.347485974
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.2151068126
Short name T83
Test name
Test status
Simulation time 137403672 ps
CPU time 0.98 seconds
Started Mar 07 02:41:17 PM PST 24
Finished Mar 07 02:41:18 PM PST 24
Peak memory 218388 kb
Host smart-c01a0e72-d32b-4d7a-9d4f-78a9ebda7374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151068126 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.2151068126
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.160046889
Short name T340
Test name
Test status
Simulation time 51222129 ps
CPU time 0.97 seconds
Started Mar 07 02:41:18 PM PST 24
Finished Mar 07 02:41:20 PM PST 24
Peak memory 215500 kb
Host smart-3cd90eed-d61a-4191-80f1-6a5e83ac5fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160046889 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.160046889
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3132857151
Short name T504
Test name
Test status
Simulation time 33913261 ps
CPU time 0.84 seconds
Started Mar 07 02:41:17 PM PST 24
Finished Mar 07 02:41:18 PM PST 24
Peak memory 214732 kb
Host smart-16e6a2dc-8e15-4704-979d-f08aae0b910f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132857151 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3132857151
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.3683433775
Short name T149
Test name
Test status
Simulation time 15283986 ps
CPU time 0.94 seconds
Started Mar 07 02:41:17 PM PST 24
Finished Mar 07 02:41:18 PM PST 24
Peak memory 214396 kb
Host smart-051784b9-1137-494a-8822-0cf2d6b182fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683433775 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.3683433775
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.2074972149
Short name T485
Test name
Test status
Simulation time 356420985 ps
CPU time 2.42 seconds
Started Mar 07 02:41:17 PM PST 24
Finished Mar 07 02:41:20 PM PST 24
Peak memory 215524 kb
Host smart-c8d35269-a9b6-429a-942d-a0f5b2497a1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074972149 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.2074972149
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.2380536799
Short name T505
Test name
Test status
Simulation time 31893627113 ps
CPU time 580.52 seconds
Started Mar 07 02:41:18 PM PST 24
Finished Mar 07 02:50:59 PM PST 24
Peak memory 216836 kb
Host smart-53d4eb48-11a9-464e-839a-912962673edc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380536799 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.2380536799
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.770172062
Short name T560
Test name
Test status
Simulation time 50637112 ps
CPU time 1.18 seconds
Started Mar 07 02:41:20 PM PST 24
Finished Mar 07 02:41:21 PM PST 24
Peak memory 214748 kb
Host smart-26581e34-d149-4e95-a520-18a168d008ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770172062 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.770172062
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/49.edn_alert_test.1707610660
Short name T542
Test name
Test status
Simulation time 17589941 ps
CPU time 0.81 seconds
Started Mar 07 02:41:21 PM PST 24
Finished Mar 07 02:41:22 PM PST 24
Peak memory 204944 kb
Host smart-56e331aa-1f13-4a66-a67a-6c9111d4be52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707610660 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.1707610660
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2110341490
Short name T163
Test name
Test status
Simulation time 19987636 ps
CPU time 0.81 seconds
Started Mar 07 02:41:21 PM PST 24
Finished Mar 07 02:41:22 PM PST 24
Peak memory 214928 kb
Host smart-c942bdcc-ccda-4212-94c0-a00b8b98f6a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110341490 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2110341490
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_err.3530267784
Short name T538
Test name
Test status
Simulation time 40994194 ps
CPU time 1.04 seconds
Started Mar 07 02:41:18 PM PST 24
Finished Mar 07 02:41:19 PM PST 24
Peak memory 218516 kb
Host smart-3646fa20-434b-4580-9636-b08492948b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530267784 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.3530267784
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_genbits.993450044
Short name T518
Test name
Test status
Simulation time 54345513 ps
CPU time 1.82 seconds
Started Mar 07 02:41:19 PM PST 24
Finished Mar 07 02:41:21 PM PST 24
Peak memory 214464 kb
Host smart-30f00cab-0ab3-4a80-ad49-8a7929849770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993450044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.993450044
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/49.edn_intr.1552376161
Short name T708
Test name
Test status
Simulation time 34374592 ps
CPU time 1.01 seconds
Started Mar 07 02:41:20 PM PST 24
Finished Mar 07 02:41:22 PM PST 24
Peak memory 222168 kb
Host smart-db740f8a-fc83-4ae4-8356-dea0065bd6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552376161 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1552376161
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.566390014
Short name T709
Test name
Test status
Simulation time 35186492 ps
CPU time 0.91 seconds
Started Mar 07 02:41:21 PM PST 24
Finished Mar 07 02:41:22 PM PST 24
Peak memory 214380 kb
Host smart-b6c0153a-5ea2-4609-8cc2-b7837bcad247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566390014 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.566390014
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.4041656658
Short name T203
Test name
Test status
Simulation time 148975720 ps
CPU time 3.18 seconds
Started Mar 07 02:41:19 PM PST 24
Finished Mar 07 02:41:22 PM PST 24
Peak memory 217880 kb
Host smart-d007893a-0050-41ae-b7e5-ee1c2a95476a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041656658 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.4041656658
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.2317479701
Short name T322
Test name
Test status
Simulation time 35782660520 ps
CPU time 932.05 seconds
Started Mar 07 02:41:19 PM PST 24
Finished Mar 07 02:56:51 PM PST 24
Peak memory 218616 kb
Host smart-7d31c13d-cfb7-4052-a12f-ba45bc533fff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317479701 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.2317479701
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.1589159572
Short name T779
Test name
Test status
Simulation time 145814041 ps
CPU time 1.2 seconds
Started Mar 07 02:39:00 PM PST 24
Finished Mar 07 02:39:02 PM PST 24
Peak memory 214784 kb
Host smart-f71a65e1-185e-4665-8d3b-a77fb47b84a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589159572 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.1589159572
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3447197457
Short name T348
Test name
Test status
Simulation time 28323436 ps
CPU time 0.94 seconds
Started Mar 07 02:39:02 PM PST 24
Finished Mar 07 02:39:04 PM PST 24
Peak memory 206164 kb
Host smart-76933c40-c8fd-44b1-8baf-42b300cf3e3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447197457 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3447197457
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.687257563
Short name T156
Test name
Test status
Simulation time 11295311 ps
CPU time 0.86 seconds
Started Mar 07 02:39:01 PM PST 24
Finished Mar 07 02:39:02 PM PST 24
Peak memory 214780 kb
Host smart-c1f2abe8-f293-4164-adaa-a2bad3f72fd4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687257563 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.687257563
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.3972154645
Short name T308
Test name
Test status
Simulation time 57427466 ps
CPU time 1.08 seconds
Started Mar 07 02:39:02 PM PST 24
Finished Mar 07 02:39:04 PM PST 24
Peak memory 215584 kb
Host smart-9d13bdb2-6794-418f-9c13-b5eb8319b199
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972154645 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.3972154645
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.3770051270
Short name T158
Test name
Test status
Simulation time 31898046 ps
CPU time 0.86 seconds
Started Mar 07 02:39:01 PM PST 24
Finished Mar 07 02:39:02 PM PST 24
Peak memory 217220 kb
Host smart-eba8bf7f-11c1-4804-9adb-240e425e6d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770051270 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.3770051270
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.1393706761
Short name T500
Test name
Test status
Simulation time 51236540 ps
CPU time 1.13 seconds
Started Mar 07 02:39:01 PM PST 24
Finished Mar 07 02:39:02 PM PST 24
Peak memory 216592 kb
Host smart-c6e32680-ba5f-4120-84ba-09e97d3629f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393706761 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.1393706761
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.3136344175
Short name T503
Test name
Test status
Simulation time 24246024 ps
CPU time 0.98 seconds
Started Mar 07 02:39:03 PM PST 24
Finished Mar 07 02:39:04 PM PST 24
Peak memory 214712 kb
Host smart-3f57bd98-380d-4ac1-a47f-35af4747461a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136344175 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.3136344175
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_regwen.1804494878
Short name T744
Test name
Test status
Simulation time 17285350 ps
CPU time 1.02 seconds
Started Mar 07 02:38:52 PM PST 24
Finished Mar 07 02:38:53 PM PST 24
Peak memory 206280 kb
Host smart-3263a378-32df-4096-8cfd-507ca036e88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804494878 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1804494878
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/5.edn_smoke.775313652
Short name T497
Test name
Test status
Simulation time 17575871 ps
CPU time 0.99 seconds
Started Mar 07 02:38:53 PM PST 24
Finished Mar 07 02:38:54 PM PST 24
Peak memory 214400 kb
Host smart-a5f780e3-cdfb-4373-b706-3ec35cb9c777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775313652 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.775313652
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.2272493398
Short name T201
Test name
Test status
Simulation time 488753531 ps
CPU time 5.2 seconds
Started Mar 07 02:39:01 PM PST 24
Finished Mar 07 02:39:07 PM PST 24
Peak memory 214416 kb
Host smart-628083da-e0fe-47cc-b19b-c4b639eb1f7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272493398 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.2272493398
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.1909227783
Short name T444
Test name
Test status
Simulation time 249186280457 ps
CPU time 1046.06 seconds
Started Mar 07 02:39:01 PM PST 24
Finished Mar 07 02:56:27 PM PST 24
Peak memory 221232 kb
Host smart-b46dbf15-95d7-41ee-87a0-7497841a4ef9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909227783 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.1909227783
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.1706223197
Short name T470
Test name
Test status
Simulation time 28575186 ps
CPU time 0.87 seconds
Started Mar 07 02:41:21 PM PST 24
Finished Mar 07 02:41:22 PM PST 24
Peak memory 216884 kb
Host smart-0c56e852-2b8f-46d9-a37b-8e0ec0f4ff88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706223197 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1706223197
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.3677230835
Short name T141
Test name
Test status
Simulation time 126190012 ps
CPU time 1.18 seconds
Started Mar 07 02:41:18 PM PST 24
Finished Mar 07 02:41:19 PM PST 24
Peak memory 217084 kb
Host smart-80ff41b6-c144-4873-b8d4-29c10453a840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677230835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.3677230835
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.853192903
Short name T800
Test name
Test status
Simulation time 31595792 ps
CPU time 0.95 seconds
Started Mar 07 02:41:37 PM PST 24
Finished Mar 07 02:41:39 PM PST 24
Peak memory 222140 kb
Host smart-75a7550b-5f9a-411b-a020-c545a18c80a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853192903 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.853192903
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.4266202940
Short name T142
Test name
Test status
Simulation time 41420784 ps
CPU time 1.05 seconds
Started Mar 07 02:41:21 PM PST 24
Finished Mar 07 02:41:22 PM PST 24
Peak memory 215664 kb
Host smart-b42a808c-114d-4ba1-be55-a7ce766f323a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266202940 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.4266202940
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.2816894904
Short name T84
Test name
Test status
Simulation time 65294435 ps
CPU time 0.91 seconds
Started Mar 07 02:41:29 PM PST 24
Finished Mar 07 02:41:30 PM PST 24
Peak memory 218352 kb
Host smart-9633b778-3a66-4742-b254-72566902c8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816894904 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.2816894904
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.1154861239
Short name T403
Test name
Test status
Simulation time 44217003 ps
CPU time 1.46 seconds
Started Mar 07 02:41:32 PM PST 24
Finished Mar 07 02:41:34 PM PST 24
Peak memory 216624 kb
Host smart-fc2bee9e-0f4b-4b04-8820-47a212858098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154861239 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.1154861239
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.532508438
Short name T690
Test name
Test status
Simulation time 19097511 ps
CPU time 1.12 seconds
Started Mar 07 02:41:31 PM PST 24
Finished Mar 07 02:41:33 PM PST 24
Peak memory 217172 kb
Host smart-762a3865-80b1-462e-8182-6abfa0664658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532508438 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.532508438
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.4123011973
Short name T276
Test name
Test status
Simulation time 44605963 ps
CPU time 1.58 seconds
Started Mar 07 02:41:31 PM PST 24
Finished Mar 07 02:41:32 PM PST 24
Peak memory 215960 kb
Host smart-65a1678e-efbf-4eec-91c6-1a541fa8e389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123011973 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.4123011973
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.1578972951
Short name T98
Test name
Test status
Simulation time 19968181 ps
CPU time 0.99 seconds
Started Mar 07 02:41:31 PM PST 24
Finished Mar 07 02:41:32 PM PST 24
Peak memory 217200 kb
Host smart-3f263273-ca6c-4304-978d-6a7790751ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578972951 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1578972951
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.2484129523
Short name T836
Test name
Test status
Simulation time 77579168 ps
CPU time 2.53 seconds
Started Mar 07 02:41:30 PM PST 24
Finished Mar 07 02:41:33 PM PST 24
Peak memory 218616 kb
Host smart-ef82348a-a8df-4529-b8d0-ccc94d1e62df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484129523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.2484129523
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.2215349806
Short name T754
Test name
Test status
Simulation time 21296466 ps
CPU time 0.91 seconds
Started Mar 07 02:41:30 PM PST 24
Finished Mar 07 02:41:31 PM PST 24
Peak memory 217092 kb
Host smart-97b2a47e-cd80-4ecf-9293-22cada5348da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215349806 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.2215349806
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.1986586241
Short name T604
Test name
Test status
Simulation time 69168835 ps
CPU time 1.06 seconds
Started Mar 07 02:41:32 PM PST 24
Finished Mar 07 02:41:34 PM PST 24
Peak memory 215336 kb
Host smart-b047066d-4b70-43b8-8864-b40c4b337527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986586241 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.1986586241
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.509243430
Short name T710
Test name
Test status
Simulation time 40424389 ps
CPU time 1.11 seconds
Started Mar 07 02:41:30 PM PST 24
Finished Mar 07 02:41:31 PM PST 24
Peak memory 218296 kb
Host smart-d37002ee-4827-40dd-9290-50606308ed22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509243430 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.509243430
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.4168560980
Short name T521
Test name
Test status
Simulation time 83563479 ps
CPU time 1.13 seconds
Started Mar 07 02:41:29 PM PST 24
Finished Mar 07 02:41:31 PM PST 24
Peak memory 215568 kb
Host smart-7e37cdf9-551d-473d-a9d1-f29880b81eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168560980 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.4168560980
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.47458000
Short name T642
Test name
Test status
Simulation time 20671417 ps
CPU time 1.07 seconds
Started Mar 07 02:41:33 PM PST 24
Finished Mar 07 02:41:36 PM PST 24
Peak memory 218724 kb
Host smart-553e0220-37e0-4c32-a121-1955d40e8613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47458000 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.47458000
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.1762667926
Short name T404
Test name
Test status
Simulation time 311273819 ps
CPU time 1.38 seconds
Started Mar 07 02:41:29 PM PST 24
Finished Mar 07 02:41:31 PM PST 24
Peak memory 215972 kb
Host smart-3146149b-9fbd-40fe-b6ed-2ac7db2e4265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762667926 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.1762667926
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.3280905740
Short name T619
Test name
Test status
Simulation time 22873504 ps
CPU time 1.08 seconds
Started Mar 07 02:41:31 PM PST 24
Finished Mar 07 02:41:32 PM PST 24
Peak memory 218512 kb
Host smart-68fe5325-03b0-444f-82a9-7ce70b59647f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280905740 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3280905740
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.249864074
Short name T715
Test name
Test status
Simulation time 47269134 ps
CPU time 1.26 seconds
Started Mar 07 02:41:30 PM PST 24
Finished Mar 07 02:41:31 PM PST 24
Peak memory 215600 kb
Host smart-90e69fee-9747-413b-8542-7a99048f2da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249864074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.249864074
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.655978713
Short name T598
Test name
Test status
Simulation time 31594864 ps
CPU time 0.8 seconds
Started Mar 07 02:41:31 PM PST 24
Finished Mar 07 02:41:32 PM PST 24
Peak memory 216908 kb
Host smart-fe3973e3-f046-4a33-b181-b463ba1ee636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655978713 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.655978713
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.78928185
Short name T384
Test name
Test status
Simulation time 91797064 ps
CPU time 1.15 seconds
Started Mar 07 02:41:37 PM PST 24
Finished Mar 07 02:41:39 PM PST 24
Peak memory 215552 kb
Host smart-b961151d-b929-4b2e-aa3e-392adba4a0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78928185 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.78928185
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.2758722448
Short name T707
Test name
Test status
Simulation time 71773691 ps
CPU time 1.23 seconds
Started Mar 07 02:39:01 PM PST 24
Finished Mar 07 02:39:02 PM PST 24
Peak memory 214804 kb
Host smart-70e6bf09-24a4-4bf7-adce-726cbf92b099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758722448 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.2758722448
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.3997183300
Short name T472
Test name
Test status
Simulation time 58405081 ps
CPU time 1 seconds
Started Mar 07 02:39:02 PM PST 24
Finished Mar 07 02:39:04 PM PST 24
Peak memory 206028 kb
Host smart-b0bd7af3-646e-4cf3-ba4e-de4ed889e85e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997183300 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.3997183300
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.3665920594
Short name T685
Test name
Test status
Simulation time 11696195 ps
CPU time 0.84 seconds
Started Mar 07 02:39:00 PM PST 24
Finished Mar 07 02:39:00 PM PST 24
Peak memory 214612 kb
Host smart-a9aca66b-2f7f-4cc4-a15b-68372141a278
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665920594 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.3665920594
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_err.1583492077
Short name T96
Test name
Test status
Simulation time 87816442 ps
CPU time 1.19 seconds
Started Mar 07 02:39:02 PM PST 24
Finished Mar 07 02:39:05 PM PST 24
Peak memory 231480 kb
Host smart-89dda05d-0e9d-4c48-9e31-be9b170a6553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583492077 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.1583492077
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.1502032074
Short name T825
Test name
Test status
Simulation time 80947331 ps
CPU time 1.49 seconds
Started Mar 07 02:39:00 PM PST 24
Finished Mar 07 02:39:02 PM PST 24
Peak memory 216984 kb
Host smart-187f9cd6-3820-4cba-b294-8a6d87520b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502032074 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.1502032074
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.395814468
Short name T644
Test name
Test status
Simulation time 49999467 ps
CPU time 0.84 seconds
Started Mar 07 02:39:00 PM PST 24
Finished Mar 07 02:39:01 PM PST 24
Peak memory 214684 kb
Host smart-b725e341-814c-4380-a9aa-45a4ddb454c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395814468 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.395814468
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_smoke.2612979029
Short name T432
Test name
Test status
Simulation time 118845020 ps
CPU time 0.84 seconds
Started Mar 07 02:39:00 PM PST 24
Finished Mar 07 02:39:01 PM PST 24
Peak memory 214388 kb
Host smart-6361916b-fa75-4cd4-9af6-69554783b08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612979029 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.2612979029
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.3980979083
Short name T755
Test name
Test status
Simulation time 208204316 ps
CPU time 4.26 seconds
Started Mar 07 02:39:01 PM PST 24
Finished Mar 07 02:39:05 PM PST 24
Peak memory 215484 kb
Host smart-2f627ff4-3b56-4bdc-be27-a0d632cced23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980979083 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.3980979083
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.2150248316
Short name T186
Test name
Test status
Simulation time 694853589550 ps
CPU time 1536.15 seconds
Started Mar 07 02:39:00 PM PST 24
Finished Mar 07 03:04:37 PM PST 24
Peak memory 224336 kb
Host smart-bf7594c6-2824-472f-bdcc-5d22a8857f58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150248316 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.2150248316
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.931584077
Short name T70
Test name
Test status
Simulation time 47100084 ps
CPU time 1.02 seconds
Started Mar 07 02:41:37 PM PST 24
Finished Mar 07 02:41:39 PM PST 24
Peak memory 215840 kb
Host smart-6bd246b3-49ef-4bea-b109-708f0f80249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931584077 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.931584077
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.3238040867
Short name T3
Test name
Test status
Simulation time 38675713 ps
CPU time 1.16 seconds
Started Mar 07 02:41:29 PM PST 24
Finished Mar 07 02:41:30 PM PST 24
Peak memory 215840 kb
Host smart-63148f2b-98c9-45ef-8cdf-01f3cfb8d79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238040867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.3238040867
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.2173987910
Short name T115
Test name
Test status
Simulation time 36244100 ps
CPU time 0.85 seconds
Started Mar 07 02:41:31 PM PST 24
Finished Mar 07 02:41:32 PM PST 24
Peak memory 216804 kb
Host smart-748c9e08-e200-479d-91b3-47ef68604947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173987910 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.2173987910
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.2209085824
Short name T777
Test name
Test status
Simulation time 53930979 ps
CPU time 1.35 seconds
Started Mar 07 02:41:29 PM PST 24
Finished Mar 07 02:41:30 PM PST 24
Peak memory 216920 kb
Host smart-bd92d1c5-9bab-4da7-b345-45d5b21fad31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209085824 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.2209085824
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.2629688056
Short name T109
Test name
Test status
Simulation time 21161312 ps
CPU time 1.18 seconds
Started Mar 07 02:41:34 PM PST 24
Finished Mar 07 02:41:37 PM PST 24
Peak memory 230508 kb
Host smart-7d5dfd34-6367-4173-886e-d6d2eae8d565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629688056 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2629688056
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.550868038
Short name T425
Test name
Test status
Simulation time 47271056 ps
CPU time 1.71 seconds
Started Mar 07 02:41:33 PM PST 24
Finished Mar 07 02:41:38 PM PST 24
Peak memory 215508 kb
Host smart-a152ac33-52ab-4d8e-b3b7-2bd5cc819317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550868038 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.550868038
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.1277346433
Short name T408
Test name
Test status
Simulation time 29543428 ps
CPU time 0.87 seconds
Started Mar 07 02:41:35 PM PST 24
Finished Mar 07 02:41:37 PM PST 24
Peak memory 216816 kb
Host smart-6384eac9-f15b-4a7b-9e02-fd9587a4ce46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277346433 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.1277346433
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.1675910839
Short name T660
Test name
Test status
Simulation time 94757612 ps
CPU time 1.17 seconds
Started Mar 07 02:41:38 PM PST 24
Finished Mar 07 02:41:40 PM PST 24
Peak memory 216912 kb
Host smart-16c02efc-4bed-4a75-9ec8-8c35bacb0f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675910839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.1675910839
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.3253451434
Short name T752
Test name
Test status
Simulation time 18105592 ps
CPU time 1.02 seconds
Started Mar 07 02:41:29 PM PST 24
Finished Mar 07 02:41:30 PM PST 24
Peak memory 214716 kb
Host smart-926406fc-cd61-45e4-8fce-3f24c6628311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253451434 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.3253451434
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2148057114
Short name T11
Test name
Test status
Simulation time 95799976 ps
CPU time 1.2 seconds
Started Mar 07 02:41:34 PM PST 24
Finished Mar 07 02:41:38 PM PST 24
Peak memory 216896 kb
Host smart-ed6b025e-1a1e-453e-95d7-b6968945e87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148057114 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2148057114
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.4205500993
Short name T360
Test name
Test status
Simulation time 18587993 ps
CPU time 1.05 seconds
Started Mar 07 02:41:30 PM PST 24
Finished Mar 07 02:41:31 PM PST 24
Peak memory 216996 kb
Host smart-2f2d1ac6-9930-4313-bf71-8ec8e2fcdb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205500993 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.4205500993
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3261516612
Short name T637
Test name
Test status
Simulation time 111651787 ps
CPU time 1.4 seconds
Started Mar 07 02:41:29 PM PST 24
Finished Mar 07 02:41:31 PM PST 24
Peak memory 217052 kb
Host smart-42ca7eb0-1347-4aef-be0d-8e0af4c7ba0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261516612 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3261516612
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.2552336232
Short name T548
Test name
Test status
Simulation time 18233857 ps
CPU time 1.18 seconds
Started Mar 07 02:41:34 PM PST 24
Finished Mar 07 02:41:37 PM PST 24
Peak memory 222288 kb
Host smart-0383da0d-292e-4f79-9df4-568a96d238e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552336232 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.2552336232
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.1241380935
Short name T682
Test name
Test status
Simulation time 43055790 ps
CPU time 1.14 seconds
Started Mar 07 02:41:32 PM PST 24
Finished Mar 07 02:41:35 PM PST 24
Peak memory 218272 kb
Host smart-02dd4fab-3540-46e6-9131-823751905ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241380935 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.1241380935
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.41989932
Short name T81
Test name
Test status
Simulation time 97696674 ps
CPU time 1.07 seconds
Started Mar 07 02:41:31 PM PST 24
Finished Mar 07 02:41:33 PM PST 24
Peak memory 230612 kb
Host smart-03180b2f-8a4e-42a4-8356-270ecc2e1386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41989932 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.41989932
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.767080255
Short name T537
Test name
Test status
Simulation time 24508600 ps
CPU time 1.29 seconds
Started Mar 07 02:41:35 PM PST 24
Finished Mar 07 02:41:38 PM PST 24
Peak memory 216748 kb
Host smart-3f4a67f0-c8ec-420d-9d63-54bfdea032f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767080255 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.767080255
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.2799019292
Short name T90
Test name
Test status
Simulation time 55914283 ps
CPU time 1.08 seconds
Started Mar 07 02:41:29 PM PST 24
Finished Mar 07 02:41:30 PM PST 24
Peak memory 228988 kb
Host smart-f69de237-9bdc-42e3-87c2-409df0dd0556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799019292 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.2799019292
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.196145352
Short name T280
Test name
Test status
Simulation time 114574796 ps
CPU time 1.97 seconds
Started Mar 07 02:41:33 PM PST 24
Finished Mar 07 02:41:37 PM PST 24
Peak memory 215856 kb
Host smart-d9cc789c-a35a-44a4-9085-0322d4db9c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196145352 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.196145352
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.2059096285
Short name T162
Test name
Test status
Simulation time 21810018 ps
CPU time 0.9 seconds
Started Mar 07 02:41:32 PM PST 24
Finished Mar 07 02:41:33 PM PST 24
Peak memory 217240 kb
Host smart-6f80dfa6-54b2-4804-afde-0e39f01a2160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059096285 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2059096285
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.3289747179
Short name T496
Test name
Test status
Simulation time 67343766 ps
CPU time 1.1 seconds
Started Mar 07 02:41:30 PM PST 24
Finished Mar 07 02:41:32 PM PST 24
Peak memory 218188 kb
Host smart-e87414bf-dde4-4b52-83b8-e613d0680186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289747179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.3289747179
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert.1355651887
Short name T641
Test name
Test status
Simulation time 321136266 ps
CPU time 1.37 seconds
Started Mar 07 02:39:08 PM PST 24
Finished Mar 07 02:39:10 PM PST 24
Peak memory 214848 kb
Host smart-ebfbe95d-68a9-4e06-befe-c253f81b4808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355651887 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1355651887
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/7.edn_alert_test.857404424
Short name T464
Test name
Test status
Simulation time 35157049 ps
CPU time 0.98 seconds
Started Mar 07 02:39:11 PM PST 24
Finished Mar 07 02:39:13 PM PST 24
Peak memory 206132 kb
Host smart-4e459990-d74e-4e1d-bbbb-0e784ba35a78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857404424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.857404424
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1168570563
Short name T117
Test name
Test status
Simulation time 15772658 ps
CPU time 0.86 seconds
Started Mar 07 02:39:11 PM PST 24
Finished Mar 07 02:39:13 PM PST 24
Peak memory 214976 kb
Host smart-36350469-3a5d-464b-a8d6-f6fbcd81a94b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168570563 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1168570563
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_err.3959148975
Short name T172
Test name
Test status
Simulation time 19671227 ps
CPU time 1.02 seconds
Started Mar 07 02:39:10 PM PST 24
Finished Mar 07 02:39:11 PM PST 24
Peak memory 214608 kb
Host smart-2f43c2a3-81c1-451c-b487-121149184f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959148975 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.3959148975
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3572190135
Short name T287
Test name
Test status
Simulation time 44858318 ps
CPU time 1.81 seconds
Started Mar 07 02:39:11 PM PST 24
Finished Mar 07 02:39:13 PM PST 24
Peak memory 216992 kb
Host smart-0281bfd1-e00a-42ef-8d18-be315155236b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572190135 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3572190135
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.2178203397
Short name T805
Test name
Test status
Simulation time 21934263 ps
CPU time 1.07 seconds
Started Mar 07 02:39:07 PM PST 24
Finished Mar 07 02:39:09 PM PST 24
Peak memory 214528 kb
Host smart-e7aee44a-d9e3-42bc-b22b-e7dacd5e4419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178203397 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.2178203397
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3854674641
Short name T127
Test name
Test status
Simulation time 75419539 ps
CPU time 0.88 seconds
Started Mar 07 02:39:08 PM PST 24
Finished Mar 07 02:39:09 PM PST 24
Peak memory 206156 kb
Host smart-74e03db0-8ba7-45df-929f-d7f7b4eaecce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854674641 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3854674641
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.793235246
Short name T304
Test name
Test status
Simulation time 16434202 ps
CPU time 0.94 seconds
Started Mar 07 02:39:04 PM PST 24
Finished Mar 07 02:39:05 PM PST 24
Peak memory 214456 kb
Host smart-f29193bb-d846-454d-87fc-17be50e73208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793235246 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.793235246
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.4024396916
Short name T385
Test name
Test status
Simulation time 365497657 ps
CPU time 7 seconds
Started Mar 07 02:39:09 PM PST 24
Finished Mar 07 02:39:16 PM PST 24
Peak memory 214532 kb
Host smart-5585c25a-112b-40da-9829-30db708ea06f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024396916 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.4024396916
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.1737044131
Short name T54
Test name
Test status
Simulation time 1274026215751 ps
CPU time 1711.22 seconds
Started Mar 07 02:39:11 PM PST 24
Finished Mar 07 03:07:43 PM PST 24
Peak memory 225688 kb
Host smart-97d088ab-1b64-46a3-b609-e242da1bddec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737044131 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.1737044131
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.765712854
Short name T74
Test name
Test status
Simulation time 113118754 ps
CPU time 1.07 seconds
Started Mar 07 02:41:35 PM PST 24
Finished Mar 07 02:41:37 PM PST 24
Peak memory 219172 kb
Host smart-5391f7d7-9fe6-49c0-850b-e983368510b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765712854 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.765712854
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.1882718338
Short name T343
Test name
Test status
Simulation time 54503329 ps
CPU time 1.17 seconds
Started Mar 07 02:41:36 PM PST 24
Finished Mar 07 02:41:38 PM PST 24
Peak memory 215520 kb
Host smart-f340f1d9-55f0-4b61-bd17-c63a596eae62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882718338 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.1882718338
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.1143819212
Short name T567
Test name
Test status
Simulation time 48125777 ps
CPU time 0.78 seconds
Started Mar 07 02:41:29 PM PST 24
Finished Mar 07 02:41:30 PM PST 24
Peak memory 216848 kb
Host smart-a9bc3c71-7b10-4277-b5c7-535d54a57a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143819212 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1143819212
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.1284952010
Short name T750
Test name
Test status
Simulation time 32048115 ps
CPU time 1.28 seconds
Started Mar 07 02:41:32 PM PST 24
Finished Mar 07 02:41:35 PM PST 24
Peak memory 217948 kb
Host smart-92b1233f-57bd-407d-bb2f-a1cc92fcb82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284952010 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.1284952010
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.3992817343
Short name T519
Test name
Test status
Simulation time 57972310 ps
CPU time 1.03 seconds
Started Mar 07 02:41:30 PM PST 24
Finished Mar 07 02:41:32 PM PST 24
Peak memory 216000 kb
Host smart-4b0bdc18-41fa-4250-9dcf-a124223cf801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992817343 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.3992817343
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.2783048955
Short name T618
Test name
Test status
Simulation time 49644359 ps
CPU time 1.38 seconds
Started Mar 07 02:41:30 PM PST 24
Finished Mar 07 02:41:31 PM PST 24
Peak memory 216092 kb
Host smart-a0892fb6-92d4-479d-93fb-35ac05d99153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783048955 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.2783048955
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.1762458038
Short name T569
Test name
Test status
Simulation time 22997199 ps
CPU time 0.92 seconds
Started Mar 07 02:41:35 PM PST 24
Finished Mar 07 02:41:37 PM PST 24
Peak memory 217188 kb
Host smart-d7c8117b-a641-4819-92dc-e864061fa723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762458038 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.1762458038
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.1909762946
Short name T309
Test name
Test status
Simulation time 35028104 ps
CPU time 1.37 seconds
Started Mar 07 02:41:30 PM PST 24
Finished Mar 07 02:41:32 PM PST 24
Peak memory 218348 kb
Host smart-ba01a0af-5050-4402-92c1-a70594ec41fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909762946 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.1909762946
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.1809662413
Short name T66
Test name
Test status
Simulation time 35501254 ps
CPU time 0.95 seconds
Started Mar 07 02:41:30 PM PST 24
Finished Mar 07 02:41:31 PM PST 24
Peak memory 215768 kb
Host smart-2c0e7617-7e61-4de5-9a3e-d3ec6819fe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809662413 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.1809662413
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.1866650126
Short name T788
Test name
Test status
Simulation time 66604114 ps
CPU time 1.22 seconds
Started Mar 07 02:41:29 PM PST 24
Finished Mar 07 02:41:31 PM PST 24
Peak memory 217112 kb
Host smart-bc0599ac-7e5e-4271-b435-73c82c0495ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866650126 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.1866650126
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.844659265
Short name T52
Test name
Test status
Simulation time 40124651 ps
CPU time 0.86 seconds
Started Mar 07 02:41:30 PM PST 24
Finished Mar 07 02:41:31 PM PST 24
Peak memory 217140 kb
Host smart-a744fb5c-89bb-438a-b04e-1b1d0ed1a459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844659265 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.844659265
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.1150152233
Short name T772
Test name
Test status
Simulation time 148530406 ps
CPU time 1.96 seconds
Started Mar 07 02:41:33 PM PST 24
Finished Mar 07 02:41:37 PM PST 24
Peak memory 217744 kb
Host smart-bcd296c3-6e02-4010-b8fc-1be8851b171f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150152233 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.1150152233
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.1017911879
Short name T689
Test name
Test status
Simulation time 79224307 ps
CPU time 1.1 seconds
Started Mar 07 02:41:42 PM PST 24
Finished Mar 07 02:41:44 PM PST 24
Peak memory 218456 kb
Host smart-bb0f8649-abf7-4741-b4f1-6283cdef9e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017911879 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.1017911879
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/77.edn_err.3071428751
Short name T85
Test name
Test status
Simulation time 48636230 ps
CPU time 1.17 seconds
Started Mar 07 02:41:41 PM PST 24
Finished Mar 07 02:41:44 PM PST 24
Peak memory 215820 kb
Host smart-0608ceb2-c194-4923-b351-f2a4798883e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071428751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.3071428751
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3059900687
Short name T270
Test name
Test status
Simulation time 79884099 ps
CPU time 2.93 seconds
Started Mar 07 02:41:41 PM PST 24
Finished Mar 07 02:41:44 PM PST 24
Peak memory 216996 kb
Host smart-54df7764-470a-4432-93b6-a3966e8132fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059900687 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3059900687
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.1407266925
Short name T65
Test name
Test status
Simulation time 29384382 ps
CPU time 1.12 seconds
Started Mar 07 02:41:41 PM PST 24
Finished Mar 07 02:41:42 PM PST 24
Peak memory 219224 kb
Host smart-cb88a6d4-ce53-4e41-9f68-219ac317c471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407266925 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.1407266925
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.3354416623
Short name T656
Test name
Test status
Simulation time 38662307 ps
CPU time 1.36 seconds
Started Mar 07 02:41:43 PM PST 24
Finished Mar 07 02:41:45 PM PST 24
Peak memory 216876 kb
Host smart-9a82bfea-afd3-4e34-a838-c3b8b2cfa09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354416623 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.3354416623
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.3649994592
Short name T110
Test name
Test status
Simulation time 39002004 ps
CPU time 0.95 seconds
Started Mar 07 02:41:41 PM PST 24
Finished Mar 07 02:41:43 PM PST 24
Peak memory 222144 kb
Host smart-bd9b929d-771b-4a5b-841e-ab8f25f4814b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649994592 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.3649994592
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.3579928919
Short name T332
Test name
Test status
Simulation time 69980000 ps
CPU time 1.19 seconds
Started Mar 07 02:41:41 PM PST 24
Finished Mar 07 02:41:42 PM PST 24
Peak memory 217248 kb
Host smart-d1aeb14c-8157-4b66-9491-8f89da21a8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579928919 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.3579928919
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.795714182
Short name T572
Test name
Test status
Simulation time 67197649 ps
CPU time 1.16 seconds
Started Mar 07 02:39:10 PM PST 24
Finished Mar 07 02:39:11 PM PST 24
Peak memory 214800 kb
Host smart-bea5b214-d4cf-4fad-9480-02199a881a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795714182 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.795714182
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.3850151366
Short name T734
Test name
Test status
Simulation time 42622865 ps
CPU time 0.89 seconds
Started Mar 07 02:39:09 PM PST 24
Finished Mar 07 02:39:10 PM PST 24
Peak memory 206060 kb
Host smart-d72ebdde-ac75-48d7-94b8-ffe9cf8e7fd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850151366 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.3850151366
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.2038235119
Short name T170
Test name
Test status
Simulation time 23749347 ps
CPU time 0.82 seconds
Started Mar 07 02:39:09 PM PST 24
Finished Mar 07 02:39:09 PM PST 24
Peak memory 214848 kb
Host smart-3fad1934-9e11-4852-a1cc-3b4e0839e791
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038235119 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.2038235119
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1200465552
Short name T251
Test name
Test status
Simulation time 40241794 ps
CPU time 1.12 seconds
Started Mar 07 02:39:11 PM PST 24
Finished Mar 07 02:39:12 PM PST 24
Peak memory 216844 kb
Host smart-4703f5c3-7377-42d2-855a-e3d8ed876e9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200465552 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1200465552
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.2944449768
Short name T458
Test name
Test status
Simulation time 28680504 ps
CPU time 0.95 seconds
Started Mar 07 02:39:08 PM PST 24
Finished Mar 07 02:39:09 PM PST 24
Peak memory 222256 kb
Host smart-5fca9b9c-d7f7-415b-bb2d-943b27728c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944449768 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.2944449768
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.1844433693
Short name T386
Test name
Test status
Simulation time 54055262 ps
CPU time 1.77 seconds
Started Mar 07 02:39:09 PM PST 24
Finished Mar 07 02:39:11 PM PST 24
Peak memory 216892 kb
Host smart-832bea56-b5f8-4dd1-a5c0-cfc1f0d80839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844433693 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.1844433693
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.3299337715
Short name T130
Test name
Test status
Simulation time 22930961 ps
CPU time 0.93 seconds
Started Mar 07 02:39:10 PM PST 24
Finished Mar 07 02:39:11 PM PST 24
Peak memory 214632 kb
Host smart-ee0c3ab1-e88a-4ac5-9be1-260a6ef8f413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299337715 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.3299337715
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.840554018
Short name T621
Test name
Test status
Simulation time 17668826 ps
CPU time 0.98 seconds
Started Mar 07 02:39:10 PM PST 24
Finished Mar 07 02:39:11 PM PST 24
Peak memory 206164 kb
Host smart-7448e4de-5a0b-448c-9a34-d83ecb61dbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840554018 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.840554018
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.3406122345
Short name T611
Test name
Test status
Simulation time 18068460 ps
CPU time 0.98 seconds
Started Mar 07 02:39:08 PM PST 24
Finished Mar 07 02:39:09 PM PST 24
Peak memory 214428 kb
Host smart-6d27abad-f83e-4235-8622-ef20e6e81ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406122345 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.3406122345
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.2084990168
Short name T206
Test name
Test status
Simulation time 1791722536 ps
CPU time 4.04 seconds
Started Mar 07 02:39:11 PM PST 24
Finished Mar 07 02:39:15 PM PST 24
Peak memory 214364 kb
Host smart-3f5cb9d4-01ea-4a71-89b4-03e20af54179
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084990168 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.2084990168
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/80.edn_err.3823371213
Short name T108
Test name
Test status
Simulation time 22323969 ps
CPU time 0.96 seconds
Started Mar 07 02:41:40 PM PST 24
Finished Mar 07 02:41:42 PM PST 24
Peak memory 222288 kb
Host smart-8e393b7d-957a-4155-943a-7a1985b3d2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823371213 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.3823371213
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.2643889896
Short name T516
Test name
Test status
Simulation time 963800647 ps
CPU time 6.46 seconds
Started Mar 07 02:41:42 PM PST 24
Finished Mar 07 02:41:49 PM PST 24
Peak memory 217072 kb
Host smart-682fadf4-bfcd-46ce-afc3-11c3fca102fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643889896 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.2643889896
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.3945881593
Short name T748
Test name
Test status
Simulation time 35216637 ps
CPU time 0.91 seconds
Started Mar 07 02:41:40 PM PST 24
Finished Mar 07 02:41:42 PM PST 24
Peak memory 217248 kb
Host smart-66630327-feb2-403c-b9b9-ee9907bee7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945881593 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3945881593
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.100255802
Short name T517
Test name
Test status
Simulation time 49349896 ps
CPU time 1.51 seconds
Started Mar 07 02:41:41 PM PST 24
Finished Mar 07 02:41:43 PM PST 24
Peak memory 215652 kb
Host smart-ef0ee897-864e-40b6-a052-c4058692256d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100255802 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.100255802
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.1954003761
Short name T491
Test name
Test status
Simulation time 28528765 ps
CPU time 0.9 seconds
Started Mar 07 02:41:41 PM PST 24
Finished Mar 07 02:41:43 PM PST 24
Peak memory 216808 kb
Host smart-fa931b73-fed1-4401-ad7e-e11531bf031d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954003761 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1954003761
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.42504816
Short name T512
Test name
Test status
Simulation time 247746735 ps
CPU time 2.41 seconds
Started Mar 07 02:41:47 PM PST 24
Finished Mar 07 02:41:50 PM PST 24
Peak memory 216992 kb
Host smart-79eb1f30-533a-4500-9e74-9187bd559fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42504816 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.42504816
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.641076233
Short name T4
Test name
Test status
Simulation time 150653958 ps
CPU time 1.22 seconds
Started Mar 07 02:41:42 PM PST 24
Finished Mar 07 02:41:45 PM PST 24
Peak memory 232388 kb
Host smart-ecf70e26-5a6c-40a0-911c-e0abd9b3f9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641076233 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.641076233
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2566227210
Short name T293
Test name
Test status
Simulation time 65633692 ps
CPU time 1.21 seconds
Started Mar 07 02:41:42 PM PST 24
Finished Mar 07 02:41:45 PM PST 24
Peak memory 215528 kb
Host smart-44da5d15-e0be-419e-8a9f-ccfcaa96ac9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566227210 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2566227210
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.2787872559
Short name T459
Test name
Test status
Simulation time 21928909 ps
CPU time 1.09 seconds
Started Mar 07 02:41:41 PM PST 24
Finished Mar 07 02:41:43 PM PST 24
Peak memory 217096 kb
Host smart-a25f9b82-3977-4404-a14d-588786404319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787872559 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.2787872559
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.677895553
Short name T319
Test name
Test status
Simulation time 82877694 ps
CPU time 1.13 seconds
Started Mar 07 02:41:42 PM PST 24
Finished Mar 07 02:41:44 PM PST 24
Peak memory 218308 kb
Host smart-e7d49bc9-946d-45a7-8203-395c94f98bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677895553 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.677895553
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.1086335100
Short name T8
Test name
Test status
Simulation time 159756398 ps
CPU time 1.14 seconds
Started Mar 07 02:41:44 PM PST 24
Finished Mar 07 02:41:45 PM PST 24
Peak memory 218244 kb
Host smart-c35bfe65-0c3c-49da-81d1-dfe90d7bf500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086335100 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.1086335100
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.1066460921
Short name T771
Test name
Test status
Simulation time 27020199 ps
CPU time 1.47 seconds
Started Mar 07 02:41:42 PM PST 24
Finished Mar 07 02:41:44 PM PST 24
Peak memory 216992 kb
Host smart-c7493af2-4618-4fed-85f4-daf738192ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066460921 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.1066460921
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.2774446144
Short name T473
Test name
Test status
Simulation time 20845193 ps
CPU time 1.04 seconds
Started Mar 07 02:41:41 PM PST 24
Finished Mar 07 02:41:43 PM PST 24
Peak memory 222296 kb
Host smart-b7cc33cf-075e-47d1-b904-85df124b3055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774446144 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.2774446144
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3805270301
Short name T355
Test name
Test status
Simulation time 53614142 ps
CPU time 1.15 seconds
Started Mar 07 02:41:46 PM PST 24
Finished Mar 07 02:41:47 PM PST 24
Peak memory 217732 kb
Host smart-2b891df9-9ed9-4cc9-a2c4-e9b35bbeb5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805270301 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3805270301
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.1746200588
Short name T436
Test name
Test status
Simulation time 93185850 ps
CPU time 1.21 seconds
Started Mar 07 02:41:41 PM PST 24
Finished Mar 07 02:41:42 PM PST 24
Peak memory 218488 kb
Host smart-c2533048-65f7-4d4d-a178-7a1a32f9e3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746200588 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.1746200588
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.3273180670
Short name T574
Test name
Test status
Simulation time 36094030 ps
CPU time 1.05 seconds
Started Mar 07 02:41:43 PM PST 24
Finished Mar 07 02:41:45 PM PST 24
Peak memory 215720 kb
Host smart-12510fce-b768-4ca7-9ec9-baaf8f793011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273180670 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.3273180670
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.3191545198
Short name T768
Test name
Test status
Simulation time 70237276 ps
CPU time 1.09 seconds
Started Mar 07 02:41:41 PM PST 24
Finished Mar 07 02:41:43 PM PST 24
Peak memory 222292 kb
Host smart-2f9a3ca2-773b-4bfa-8101-c539e3673e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191545198 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.3191545198
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.1225117626
Short name T285
Test name
Test status
Simulation time 53421488 ps
CPU time 1.22 seconds
Started Mar 07 02:41:42 PM PST 24
Finished Mar 07 02:41:44 PM PST 24
Peak memory 217228 kb
Host smart-dce4e790-4857-495a-b5d1-4291e92fdd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225117626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.1225117626
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.1513936180
Short name T75
Test name
Test status
Simulation time 21627795 ps
CPU time 1.15 seconds
Started Mar 07 02:41:44 PM PST 24
Finished Mar 07 02:41:45 PM PST 24
Peak memory 228908 kb
Host smart-ceb695d6-f865-4a2d-81e7-6024e5f0c64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513936180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.1513936180
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/89.edn_genbits.4185367597
Short name T648
Test name
Test status
Simulation time 145652977 ps
CPU time 1.05 seconds
Started Mar 07 02:41:41 PM PST 24
Finished Mar 07 02:41:43 PM PST 24
Peak memory 215560 kb
Host smart-6e53856e-74c1-4d63-a21f-3ef23df1f7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185367597 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.4185367597
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_alert.1281412533
Short name T764
Test name
Test status
Simulation time 50393500 ps
CPU time 1.2 seconds
Started Mar 07 02:39:18 PM PST 24
Finished Mar 07 02:39:19 PM PST 24
Peak memory 214824 kb
Host smart-d691d472-bed2-4746-a2a6-de3640488745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281412533 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.1281412533
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.2724780496
Short name T427
Test name
Test status
Simulation time 56612476 ps
CPU time 0.95 seconds
Started Mar 07 02:39:19 PM PST 24
Finished Mar 07 02:39:20 PM PST 24
Peak memory 206128 kb
Host smart-3a8add31-4d69-43ae-a722-94502519c5fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724780496 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.2724780496
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.4027388792
Short name T533
Test name
Test status
Simulation time 25263776 ps
CPU time 0.8 seconds
Started Mar 07 02:39:18 PM PST 24
Finished Mar 07 02:39:19 PM PST 24
Peak memory 214812 kb
Host smart-e0015741-d53e-4eab-8b70-233b1723f5ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027388792 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.4027388792
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3917293885
Short name T168
Test name
Test status
Simulation time 49215914 ps
CPU time 1.08 seconds
Started Mar 07 02:39:21 PM PST 24
Finished Mar 07 02:39:22 PM PST 24
Peak memory 215712 kb
Host smart-ea88f58a-ec8e-4eb9-a6c0-c30ec1d582b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917293885 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3917293885
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3016309213
Short name T697
Test name
Test status
Simulation time 126461639 ps
CPU time 1.22 seconds
Started Mar 07 02:39:20 PM PST 24
Finished Mar 07 02:39:21 PM PST 24
Peak memory 218332 kb
Host smart-6718c236-1129-4479-a04b-816c1ccefe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016309213 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3016309213
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.1671380943
Short name T834
Test name
Test status
Simulation time 56350215 ps
CPU time 1.23 seconds
Started Mar 07 02:39:19 PM PST 24
Finished Mar 07 02:39:20 PM PST 24
Peak memory 215664 kb
Host smart-16dcc29d-8e81-44f8-9427-ba2d303ab11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671380943 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.1671380943
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.1255475851
Short name T785
Test name
Test status
Simulation time 107120237 ps
CPU time 0.85 seconds
Started Mar 07 02:39:19 PM PST 24
Finished Mar 07 02:39:20 PM PST 24
Peak memory 214620 kb
Host smart-33339599-fc3d-44c3-99f5-23e9e40df388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255475851 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.1255475851
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_smoke.84510904
Short name T414
Test name
Test status
Simulation time 17374027 ps
CPU time 1.01 seconds
Started Mar 07 02:39:08 PM PST 24
Finished Mar 07 02:39:09 PM PST 24
Peak memory 214416 kb
Host smart-5541c4a7-5f81-4c8e-8561-bfcc463de9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84510904 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.84510904
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.2519041464
Short name T749
Test name
Test status
Simulation time 365510865 ps
CPU time 4.07 seconds
Started Mar 07 02:39:19 PM PST 24
Finished Mar 07 02:39:23 PM PST 24
Peak memory 214432 kb
Host smart-1fa263a2-a0d7-4f4e-b03c-546399464d59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519041464 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.2519041464
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.1257695238
Short name T188
Test name
Test status
Simulation time 26618734082 ps
CPU time 328.66 seconds
Started Mar 07 02:39:19 PM PST 24
Finished Mar 07 02:44:48 PM PST 24
Peak memory 217712 kb
Host smart-2886a8ca-5510-4283-acb2-a269d210b86e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257695238 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.1257695238
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_genbits.3749254276
Short name T551
Test name
Test status
Simulation time 40821528 ps
CPU time 1.46 seconds
Started Mar 07 02:41:44 PM PST 24
Finished Mar 07 02:41:46 PM PST 24
Peak memory 215536 kb
Host smart-005789e2-3d9f-44f5-ae9b-f1eda9980877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749254276 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3749254276
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.117183494
Short name T691
Test name
Test status
Simulation time 37727854 ps
CPU time 1.06 seconds
Started Mar 07 02:41:42 PM PST 24
Finished Mar 07 02:41:44 PM PST 24
Peak memory 230592 kb
Host smart-11d3b07c-e515-4ba8-98f5-bc877dc59170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117183494 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.117183494
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.3070004836
Short name T361
Test name
Test status
Simulation time 91515048 ps
CPU time 1.31 seconds
Started Mar 07 02:41:41 PM PST 24
Finished Mar 07 02:41:43 PM PST 24
Peak memory 216712 kb
Host smart-43c2ad5a-187e-48a6-a71d-6085cab19a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070004836 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.3070004836
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.399860786
Short name T104
Test name
Test status
Simulation time 20491546 ps
CPU time 1.03 seconds
Started Mar 07 02:41:54 PM PST 24
Finished Mar 07 02:41:55 PM PST 24
Peak memory 217156 kb
Host smart-c208ca2a-9148-4dbd-8bbb-65aa6cb714b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399860786 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.399860786
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.944555491
Short name T763
Test name
Test status
Simulation time 49859938 ps
CPU time 1.58 seconds
Started Mar 07 02:41:42 PM PST 24
Finished Mar 07 02:41:45 PM PST 24
Peak memory 216936 kb
Host smart-88b220ed-8caa-4762-b16b-455d84b07182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944555491 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.944555491
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.1650095998
Short name T600
Test name
Test status
Simulation time 74750869 ps
CPU time 1.02 seconds
Started Mar 07 02:41:53 PM PST 24
Finished Mar 07 02:41:55 PM PST 24
Peak memory 218096 kb
Host smart-21270806-b08f-4343-bb27-aee2816962bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650095998 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.1650095998
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.2754484751
Short name T277
Test name
Test status
Simulation time 60915748 ps
CPU time 1.42 seconds
Started Mar 07 02:41:54 PM PST 24
Finished Mar 07 02:41:56 PM PST 24
Peak memory 216812 kb
Host smart-cdee9144-75c3-48c7-9aa4-60abf2df3945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754484751 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.2754484751
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.2950484115
Short name T173
Test name
Test status
Simulation time 73395974 ps
CPU time 1.05 seconds
Started Mar 07 02:41:56 PM PST 24
Finished Mar 07 02:41:57 PM PST 24
Peak memory 218352 kb
Host smart-27e62fab-c15f-4b82-8876-2dd86353ace0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950484115 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2950484115
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1346599895
Short name T477
Test name
Test status
Simulation time 52569473 ps
CPU time 1.24 seconds
Started Mar 07 02:41:54 PM PST 24
Finished Mar 07 02:41:55 PM PST 24
Peak memory 215852 kb
Host smart-5f4476bb-b5f8-4225-96c3-12e2bcfbdf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346599895 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1346599895
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.1970730001
Short name T159
Test name
Test status
Simulation time 26226218 ps
CPU time 0.92 seconds
Started Mar 07 02:41:54 PM PST 24
Finished Mar 07 02:41:55 PM PST 24
Peak memory 217152 kb
Host smart-d9114bfd-8592-471a-9245-84b0d41817f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970730001 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.1970730001
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.3700286279
Short name T10
Test name
Test status
Simulation time 38175602 ps
CPU time 1.39 seconds
Started Mar 07 02:41:56 PM PST 24
Finished Mar 07 02:41:58 PM PST 24
Peak memory 218176 kb
Host smart-24e3b70d-637a-49f2-b70f-423503aace9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700286279 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.3700286279
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.3028172814
Short name T393
Test name
Test status
Simulation time 64191969 ps
CPU time 0.92 seconds
Started Mar 07 02:41:56 PM PST 24
Finished Mar 07 02:41:58 PM PST 24
Peak memory 222156 kb
Host smart-a6493d20-fd12-448c-a013-d784514fc479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028172814 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.3028172814
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.2478167361
Short name T302
Test name
Test status
Simulation time 71701278 ps
CPU time 2.52 seconds
Started Mar 07 02:41:54 PM PST 24
Finished Mar 07 02:41:57 PM PST 24
Peak memory 218084 kb
Host smart-a23f50c4-e321-4da8-a7cf-e206b0a5020c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478167361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.2478167361
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.102637014
Short name T80
Test name
Test status
Simulation time 42190756 ps
CPU time 1.54 seconds
Started Mar 07 02:41:55 PM PST 24
Finished Mar 07 02:41:56 PM PST 24
Peak memory 231500 kb
Host smart-43687662-8bf2-432a-a879-0e52f810d3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102637014 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.102637014
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.3246697069
Short name T727
Test name
Test status
Simulation time 46267738 ps
CPU time 1.23 seconds
Started Mar 07 02:41:54 PM PST 24
Finished Mar 07 02:41:56 PM PST 24
Peak memory 216932 kb
Host smart-c4682f3d-b7c0-41e1-98ec-344ee0c0d6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246697069 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.3246697069
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.778943142
Short name T94
Test name
Test status
Simulation time 73619682 ps
CPU time 1.11 seconds
Started Mar 07 02:41:53 PM PST 24
Finished Mar 07 02:41:55 PM PST 24
Peak memory 218256 kb
Host smart-be658619-739f-4ea4-a299-ca67c3ed5ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778943142 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.778943142
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.2045236851
Short name T471
Test name
Test status
Simulation time 47320974 ps
CPU time 1.48 seconds
Started Mar 07 02:41:53 PM PST 24
Finished Mar 07 02:41:54 PM PST 24
Peak memory 216748 kb
Host smart-647dfa97-a76d-4e61-8438-09d7b63098f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045236851 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.2045236851
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.1584164572
Short name T699
Test name
Test status
Simulation time 67318221 ps
CPU time 1.04 seconds
Started Mar 07 02:41:55 PM PST 24
Finished Mar 07 02:41:56 PM PST 24
Peak memory 217324 kb
Host smart-0d5b5cdf-9b37-47f5-844f-4e92364545a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584164572 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.1584164572
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.1712221012
Short name T281
Test name
Test status
Simulation time 69631604 ps
CPU time 1.03 seconds
Started Mar 07 02:41:55 PM PST 24
Finished Mar 07 02:41:56 PM PST 24
Peak memory 215596 kb
Host smart-40448c1d-4176-4167-869c-34b8284e704c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712221012 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.1712221012
Directory /workspace/99.edn_genbits/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%