Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.93 98.27 93.56 96.79 82.08 96.87 96.58 93.35


Total test records in report: 969
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T89 /workspace/coverage/default/85.edn_err.806704286 Mar 12 02:45:49 PM PDT 24 Mar 12 02:45:51 PM PDT 24 20589097 ps
T788 /workspace/coverage/default/18.edn_disable.170567973 Mar 12 02:44:06 PM PDT 24 Mar 12 02:44:07 PM PDT 24 62113060 ps
T789 /workspace/coverage/default/23.edn_smoke.184183463 Mar 12 02:44:25 PM PDT 24 Mar 12 02:44:26 PM PDT 24 31337410 ps
T790 /workspace/coverage/default/31.edn_stress_all.1185716977 Mar 12 02:44:46 PM PDT 24 Mar 12 02:44:52 PM PDT 24 286528698 ps
T791 /workspace/coverage/default/35.edn_smoke.1695684604 Mar 12 02:44:57 PM PDT 24 Mar 12 02:44:58 PM PDT 24 72396537 ps
T792 /workspace/coverage/default/9.edn_stress_all_with_rand_reset.293168485 Mar 12 02:43:36 PM PDT 24 Mar 12 02:54:51 PM PDT 24 55957092529 ps
T793 /workspace/coverage/default/124.edn_genbits.3055841954 Mar 12 02:46:09 PM PDT 24 Mar 12 02:46:11 PM PDT 24 61323916 ps
T794 /workspace/coverage/default/78.edn_err.2381206883 Mar 12 02:45:52 PM PDT 24 Mar 12 02:45:53 PM PDT 24 18849403 ps
T795 /workspace/coverage/default/287.edn_genbits.2269331569 Mar 12 02:46:35 PM PDT 24 Mar 12 02:46:36 PM PDT 24 55418417 ps
T796 /workspace/coverage/default/142.edn_genbits.3542491924 Mar 12 02:46:06 PM PDT 24 Mar 12 02:46:07 PM PDT 24 66188105 ps
T797 /workspace/coverage/default/20.edn_stress_all.2811910375 Mar 12 02:44:15 PM PDT 24 Mar 12 02:44:18 PM PDT 24 313990981 ps
T798 /workspace/coverage/default/77.edn_genbits.3267967589 Mar 12 02:45:52 PM PDT 24 Mar 12 02:45:53 PM PDT 24 124933442 ps
T799 /workspace/coverage/default/23.edn_intr.3090083846 Mar 12 02:44:25 PM PDT 24 Mar 12 02:44:26 PM PDT 24 25885926 ps
T800 /workspace/coverage/default/148.edn_genbits.3926544387 Mar 12 02:46:08 PM PDT 24 Mar 12 02:46:09 PM PDT 24 54375164 ps
T76 /workspace/coverage/default/40.edn_disable_auto_req_mode.4093918641 Mar 12 02:45:10 PM PDT 24 Mar 12 02:45:11 PM PDT 24 39376450 ps
T801 /workspace/coverage/default/20.edn_alert.3172883928 Mar 12 02:44:15 PM PDT 24 Mar 12 02:44:17 PM PDT 24 167608474 ps
T802 /workspace/coverage/default/40.edn_alert_test.1412513644 Mar 12 02:45:10 PM PDT 24 Mar 12 02:45:12 PM PDT 24 15110789 ps
T803 /workspace/coverage/default/61.edn_err.1297897055 Mar 12 02:45:37 PM PDT 24 Mar 12 02:45:39 PM PDT 24 20221221 ps
T804 /workspace/coverage/default/9.edn_intr.4150122912 Mar 12 02:43:37 PM PDT 24 Mar 12 02:43:38 PM PDT 24 20925950 ps
T805 /workspace/coverage/default/5.edn_smoke.781650263 Mar 12 02:43:21 PM PDT 24 Mar 12 02:43:22 PM PDT 24 48482907 ps
T806 /workspace/coverage/default/127.edn_genbits.1852112037 Mar 12 02:46:08 PM PDT 24 Mar 12 02:46:09 PM PDT 24 51354925 ps
T807 /workspace/coverage/default/276.edn_genbits.4018047127 Mar 12 02:46:42 PM PDT 24 Mar 12 02:46:43 PM PDT 24 26665007 ps
T808 /workspace/coverage/default/12.edn_alert_test.1824473811 Mar 12 02:43:51 PM PDT 24 Mar 12 02:43:52 PM PDT 24 51440116 ps
T809 /workspace/coverage/default/40.edn_stress_all_with_rand_reset.978872973 Mar 12 02:45:10 PM PDT 24 Mar 12 03:05:47 PM PDT 24 216386841154 ps
T810 /workspace/coverage/default/1.edn_stress_all_with_rand_reset.4233065961 Mar 12 02:43:02 PM PDT 24 Mar 12 02:57:26 PM PDT 24 180006269545 ps
T77 /workspace/coverage/default/18.edn_disable_auto_req_mode.4187399044 Mar 12 02:44:06 PM PDT 24 Mar 12 02:44:07 PM PDT 24 74738122 ps
T811 /workspace/coverage/default/45.edn_disable.2287212876 Mar 12 02:45:26 PM PDT 24 Mar 12 02:45:27 PM PDT 24 34102029 ps
T812 /workspace/coverage/default/23.edn_disable.4141783459 Mar 12 02:44:26 PM PDT 24 Mar 12 02:44:27 PM PDT 24 22662515 ps
T813 /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1717448179 Mar 12 02:45:34 PM PDT 24 Mar 12 02:49:21 PM PDT 24 34902984805 ps
T814 /workspace/coverage/default/18.edn_stress_all_with_rand_reset.29022059 Mar 12 02:44:13 PM PDT 24 Mar 12 03:02:55 PM PDT 24 51996906123 ps
T815 /workspace/coverage/default/21.edn_err.3555980585 Mar 12 02:44:16 PM PDT 24 Mar 12 02:44:17 PM PDT 24 58304563 ps
T816 /workspace/coverage/default/1.edn_err.3810306281 Mar 12 02:45:04 PM PDT 24 Mar 12 02:45:05 PM PDT 24 26180859 ps
T817 /workspace/coverage/default/15.edn_genbits.2776462796 Mar 12 02:43:57 PM PDT 24 Mar 12 02:44:01 PM PDT 24 58664220 ps
T818 /workspace/coverage/default/31.edn_disable_auto_req_mode.717394417 Mar 12 02:44:47 PM PDT 24 Mar 12 02:44:48 PM PDT 24 223769100 ps
T819 /workspace/coverage/default/1.edn_alert.1403547998 Mar 12 02:46:08 PM PDT 24 Mar 12 02:46:09 PM PDT 24 50249617 ps
T820 /workspace/coverage/default/4.edn_err.4219072484 Mar 12 02:43:25 PM PDT 24 Mar 12 02:43:26 PM PDT 24 23019956 ps
T173 /workspace/coverage/default/25.edn_disable.3903794483 Mar 12 02:44:36 PM PDT 24 Mar 12 02:44:37 PM PDT 24 11346281 ps
T821 /workspace/coverage/default/40.edn_alert.1910101768 Mar 12 02:45:11 PM PDT 24 Mar 12 02:45:13 PM PDT 24 46293285 ps
T822 /workspace/coverage/default/48.edn_err.3397129970 Mar 12 02:45:30 PM PDT 24 Mar 12 02:45:31 PM PDT 24 27927638 ps
T823 /workspace/coverage/default/164.edn_genbits.4141460632 Mar 12 02:46:17 PM PDT 24 Mar 12 02:46:18 PM PDT 24 37883368 ps
T824 /workspace/coverage/default/125.edn_genbits.1008436577 Mar 12 02:46:05 PM PDT 24 Mar 12 02:46:07 PM PDT 24 81258527 ps
T825 /workspace/coverage/default/15.edn_disable.3265683690 Mar 12 02:43:57 PM PDT 24 Mar 12 02:44:00 PM PDT 24 23343508 ps
T54 /workspace/coverage/default/0.edn_sec_cm.2191099944 Mar 12 02:43:03 PM PDT 24 Mar 12 02:43:06 PM PDT 24 190777509 ps
T826 /workspace/coverage/default/13.edn_intr.792539970 Mar 12 02:43:51 PM PDT 24 Mar 12 02:43:52 PM PDT 24 20279207 ps
T827 /workspace/coverage/default/167.edn_genbits.3492721856 Mar 12 02:46:14 PM PDT 24 Mar 12 02:46:16 PM PDT 24 273347833 ps
T828 /workspace/coverage/default/112.edn_genbits.3294600000 Mar 12 02:45:57 PM PDT 24 Mar 12 02:45:58 PM PDT 24 88759255 ps
T829 /workspace/coverage/default/171.edn_genbits.1991093837 Mar 12 02:46:13 PM PDT 24 Mar 12 02:46:16 PM PDT 24 263643865 ps
T830 /workspace/coverage/default/45.edn_alert_test.2333891730 Mar 12 02:45:27 PM PDT 24 Mar 12 02:45:29 PM PDT 24 32120225 ps
T831 /workspace/coverage/default/41.edn_stress_all_with_rand_reset.4142354604 Mar 12 02:45:09 PM PDT 24 Mar 12 02:54:30 PM PDT 24 25318779118 ps
T832 /workspace/coverage/default/19.edn_alert.2873726712 Mar 12 02:44:14 PM PDT 24 Mar 12 02:44:15 PM PDT 24 39799419 ps
T833 /workspace/coverage/default/24.edn_alert_test.1943586849 Mar 12 02:44:25 PM PDT 24 Mar 12 02:44:26 PM PDT 24 49740183 ps
T834 /workspace/coverage/default/96.edn_err.2485268484 Mar 12 02:45:57 PM PDT 24 Mar 12 02:45:58 PM PDT 24 25014699 ps
T835 /workspace/coverage/default/290.edn_genbits.2301270655 Mar 12 02:46:38 PM PDT 24 Mar 12 02:46:39 PM PDT 24 27122118 ps
T836 /workspace/coverage/default/146.edn_genbits.810899388 Mar 12 02:46:04 PM PDT 24 Mar 12 02:46:05 PM PDT 24 184260116 ps
T837 /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3780849867 Mar 12 12:35:54 PM PDT 24 Mar 12 12:35:55 PM PDT 24 32501450 ps
T838 /workspace/coverage/cover_reg_top/12.edn_intr_test.1544163837 Mar 12 12:36:06 PM PDT 24 Mar 12 12:36:07 PM PDT 24 57958089 ps
T839 /workspace/coverage/cover_reg_top/41.edn_intr_test.953867129 Mar 12 12:36:16 PM PDT 24 Mar 12 12:36:17 PM PDT 24 14293776 ps
T840 /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3593565616 Mar 12 12:36:04 PM PDT 24 Mar 12 12:36:05 PM PDT 24 33662883 ps
T841 /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2488658672 Mar 12 12:35:47 PM PDT 24 Mar 12 12:35:49 PM PDT 24 17751796 ps
T226 /workspace/coverage/cover_reg_top/10.edn_csr_rw.2289121419 Mar 12 12:36:09 PM PDT 24 Mar 12 12:36:10 PM PDT 24 28983824 ps
T842 /workspace/coverage/cover_reg_top/6.edn_intr_test.559108857 Mar 12 12:36:00 PM PDT 24 Mar 12 12:36:01 PM PDT 24 24992059 ps
T843 /workspace/coverage/cover_reg_top/23.edn_intr_test.3188192533 Mar 12 12:36:12 PM PDT 24 Mar 12 12:36:14 PM PDT 24 44105123 ps
T844 /workspace/coverage/cover_reg_top/38.edn_intr_test.377127121 Mar 12 12:37:52 PM PDT 24 Mar 12 12:37:54 PM PDT 24 17554076 ps
T206 /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3521299744 Mar 12 12:35:44 PM PDT 24 Mar 12 12:35:45 PM PDT 24 27197237 ps
T230 /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3295340491 Mar 12 12:36:09 PM PDT 24 Mar 12 12:36:12 PM PDT 24 275111553 ps
T231 /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.433868120 Mar 12 12:36:08 PM PDT 24 Mar 12 12:36:09 PM PDT 24 57773055 ps
T845 /workspace/coverage/cover_reg_top/17.edn_tl_errors.3739942260 Mar 12 12:36:05 PM PDT 24 Mar 12 12:36:07 PM PDT 24 475911286 ps
T227 /workspace/coverage/cover_reg_top/12.edn_csr_rw.3877066615 Mar 12 12:36:10 PM PDT 24 Mar 12 12:36:11 PM PDT 24 52067620 ps
T207 /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2212228921 Mar 12 12:35:55 PM PDT 24 Mar 12 12:35:57 PM PDT 24 15177294 ps
T846 /workspace/coverage/cover_reg_top/11.edn_intr_test.2229785026 Mar 12 12:35:58 PM PDT 24 Mar 12 12:36:00 PM PDT 24 14156742 ps
T847 /workspace/coverage/cover_reg_top/29.edn_intr_test.3901987005 Mar 12 12:36:12 PM PDT 24 Mar 12 12:36:14 PM PDT 24 39139102 ps
T220 /workspace/coverage/cover_reg_top/9.edn_csr_rw.1150146760 Mar 12 12:35:54 PM PDT 24 Mar 12 12:35:56 PM PDT 24 31080520 ps
T848 /workspace/coverage/cover_reg_top/37.edn_intr_test.2743590322 Mar 12 12:36:17 PM PDT 24 Mar 12 12:36:18 PM PDT 24 27406404 ps
T228 /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2155698699 Mar 12 12:35:47 PM PDT 24 Mar 12 12:35:49 PM PDT 24 34279098 ps
T849 /workspace/coverage/cover_reg_top/2.edn_intr_test.3297915473 Mar 12 12:35:49 PM PDT 24 Mar 12 12:35:50 PM PDT 24 24862715 ps
T850 /workspace/coverage/cover_reg_top/1.edn_tl_errors.827248891 Mar 12 12:35:43 PM PDT 24 Mar 12 12:35:46 PM PDT 24 40595791 ps
T851 /workspace/coverage/cover_reg_top/3.edn_intr_test.2848474953 Mar 12 12:35:49 PM PDT 24 Mar 12 12:35:50 PM PDT 24 16110172 ps
T852 /workspace/coverage/cover_reg_top/7.edn_intr_test.1206674812 Mar 12 12:36:08 PM PDT 24 Mar 12 12:36:10 PM PDT 24 18014407 ps
T853 /workspace/coverage/cover_reg_top/15.edn_tl_errors.2354863439 Mar 12 12:36:05 PM PDT 24 Mar 12 12:36:07 PM PDT 24 165442642 ps
T854 /workspace/coverage/cover_reg_top/18.edn_tl_errors.3924444002 Mar 12 12:36:07 PM PDT 24 Mar 12 12:36:09 PM PDT 24 55879030 ps
T208 /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2561512124 Mar 12 12:35:56 PM PDT 24 Mar 12 12:35:57 PM PDT 24 21417911 ps
T221 /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1368968724 Mar 12 12:35:56 PM PDT 24 Mar 12 12:35:58 PM PDT 24 41046053 ps
T855 /workspace/coverage/cover_reg_top/8.edn_intr_test.3615689199 Mar 12 12:35:56 PM PDT 24 Mar 12 12:35:58 PM PDT 24 31329322 ps
T209 /workspace/coverage/cover_reg_top/14.edn_csr_rw.716801308 Mar 12 12:36:03 PM PDT 24 Mar 12 12:36:04 PM PDT 24 16412282 ps
T232 /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2513892418 Mar 12 12:35:54 PM PDT 24 Mar 12 12:35:56 PM PDT 24 188469178 ps
T856 /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1578011978 Mar 12 12:35:44 PM PDT 24 Mar 12 12:35:45 PM PDT 24 63771138 ps
T239 /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1655278984 Mar 12 12:35:58 PM PDT 24 Mar 12 12:36:01 PM PDT 24 50861940 ps
T857 /workspace/coverage/cover_reg_top/34.edn_intr_test.2776348284 Mar 12 12:36:08 PM PDT 24 Mar 12 12:36:10 PM PDT 24 25905059 ps
T858 /workspace/coverage/cover_reg_top/25.edn_intr_test.4267442876 Mar 12 12:36:04 PM PDT 24 Mar 12 12:36:05 PM PDT 24 34129920 ps
T859 /workspace/coverage/cover_reg_top/14.edn_intr_test.3114521545 Mar 12 12:36:07 PM PDT 24 Mar 12 12:36:08 PM PDT 24 14343280 ps
T229 /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.59774677 Mar 12 12:35:44 PM PDT 24 Mar 12 12:35:50 PM PDT 24 524104469 ps
T240 /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1207319963 Mar 12 12:35:53 PM PDT 24 Mar 12 12:35:56 PM PDT 24 1254132922 ps
T860 /workspace/coverage/cover_reg_top/5.edn_csr_rw.3131441234 Mar 12 12:36:09 PM PDT 24 Mar 12 12:36:10 PM PDT 24 16689535 ps
T861 /workspace/coverage/cover_reg_top/9.edn_intr_test.1468529614 Mar 12 12:35:56 PM PDT 24 Mar 12 12:35:58 PM PDT 24 42456036 ps
T862 /workspace/coverage/cover_reg_top/0.edn_intr_test.2010340013 Mar 12 12:35:46 PM PDT 24 Mar 12 12:35:49 PM PDT 24 16367870 ps
T863 /workspace/coverage/cover_reg_top/5.edn_intr_test.2925224289 Mar 12 12:35:57 PM PDT 24 Mar 12 12:35:59 PM PDT 24 52635863 ps
T864 /workspace/coverage/cover_reg_top/26.edn_intr_test.145726742 Mar 12 12:36:12 PM PDT 24 Mar 12 12:36:14 PM PDT 24 56272848 ps
T865 /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1387686858 Mar 12 12:36:05 PM PDT 24 Mar 12 12:36:07 PM PDT 24 35613999 ps
T866 /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1722916333 Mar 12 12:36:04 PM PDT 24 Mar 12 12:36:06 PM PDT 24 126961107 ps
T222 /workspace/coverage/cover_reg_top/3.edn_csr_rw.1405857424 Mar 12 12:35:45 PM PDT 24 Mar 12 12:35:46 PM PDT 24 10733190 ps
T867 /workspace/coverage/cover_reg_top/28.edn_intr_test.2605453563 Mar 12 12:36:12 PM PDT 24 Mar 12 12:36:14 PM PDT 24 25803498 ps
T868 /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1416050902 Mar 12 12:36:03 PM PDT 24 Mar 12 12:36:05 PM PDT 24 179926836 ps
T210 /workspace/coverage/cover_reg_top/0.edn_csr_rw.4094422280 Mar 12 12:35:45 PM PDT 24 Mar 12 12:35:46 PM PDT 24 30431167 ps
T869 /workspace/coverage/cover_reg_top/43.edn_intr_test.2664615876 Mar 12 12:36:16 PM PDT 24 Mar 12 12:36:17 PM PDT 24 13413798 ps
T870 /workspace/coverage/cover_reg_top/32.edn_intr_test.3226308673 Mar 12 12:36:05 PM PDT 24 Mar 12 12:36:06 PM PDT 24 12658173 ps
T211 /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2153137722 Mar 12 12:35:50 PM PDT 24 Mar 12 12:35:51 PM PDT 24 13890749 ps
T241 /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2654091732 Mar 12 12:35:46 PM PDT 24 Mar 12 12:35:50 PM PDT 24 77381342 ps
T212 /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1722408744 Mar 12 12:35:46 PM PDT 24 Mar 12 12:35:49 PM PDT 24 47388707 ps
T871 /workspace/coverage/cover_reg_top/2.edn_tl_errors.321497218 Mar 12 12:35:44 PM PDT 24 Mar 12 12:35:47 PM PDT 24 34905472 ps
T213 /workspace/coverage/cover_reg_top/6.edn_csr_rw.2215867947 Mar 12 12:35:56 PM PDT 24 Mar 12 12:35:56 PM PDT 24 74309353 ps
T214 /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2988393263 Mar 12 12:36:09 PM PDT 24 Mar 12 12:36:10 PM PDT 24 19561935 ps
T872 /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3478065267 Mar 12 12:35:46 PM PDT 24 Mar 12 12:35:49 PM PDT 24 126954091 ps
T215 /workspace/coverage/cover_reg_top/8.edn_csr_rw.4233064994 Mar 12 12:35:59 PM PDT 24 Mar 12 12:36:00 PM PDT 24 13432468 ps
T873 /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1097370953 Mar 12 12:35:47 PM PDT 24 Mar 12 12:35:49 PM PDT 24 37599152 ps
T874 /workspace/coverage/cover_reg_top/46.edn_intr_test.308353468 Mar 12 12:36:15 PM PDT 24 Mar 12 12:36:17 PM PDT 24 24335866 ps
T875 /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.225717400 Mar 12 12:35:43 PM PDT 24 Mar 12 12:35:48 PM PDT 24 176524107 ps
T876 /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2942105652 Mar 12 12:36:04 PM PDT 24 Mar 12 12:36:05 PM PDT 24 87938525 ps
T223 /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2467387320 Mar 12 12:35:45 PM PDT 24 Mar 12 12:35:46 PM PDT 24 41874440 ps
T224 /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3214822776 Mar 12 12:36:06 PM PDT 24 Mar 12 12:36:07 PM PDT 24 75744968 ps
T877 /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3055467315 Mar 12 12:35:47 PM PDT 24 Mar 12 12:35:49 PM PDT 24 330990250 ps
T878 /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1228226918 Mar 12 12:36:05 PM PDT 24 Mar 12 12:36:07 PM PDT 24 98934736 ps
T879 /workspace/coverage/cover_reg_top/20.edn_intr_test.798466198 Mar 12 12:36:05 PM PDT 24 Mar 12 12:36:06 PM PDT 24 15160815 ps
T225 /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1648977641 Mar 12 12:36:04 PM PDT 24 Mar 12 12:36:05 PM PDT 24 118847927 ps
T880 /workspace/coverage/cover_reg_top/16.edn_csr_rw.1973309360 Mar 12 12:36:06 PM PDT 24 Mar 12 12:36:07 PM PDT 24 61613822 ps
T881 /workspace/coverage/cover_reg_top/47.edn_intr_test.1045715724 Mar 12 12:36:18 PM PDT 24 Mar 12 12:36:19 PM PDT 24 41580504 ps
T882 /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2021321245 Mar 12 12:36:06 PM PDT 24 Mar 12 12:36:07 PM PDT 24 91845082 ps
T883 /workspace/coverage/cover_reg_top/36.edn_intr_test.1823784550 Mar 12 12:36:07 PM PDT 24 Mar 12 12:36:07 PM PDT 24 16258997 ps
T884 /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3783211532 Mar 12 12:35:53 PM PDT 24 Mar 12 12:35:55 PM PDT 24 89500789 ps
T885 /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3249675385 Mar 12 12:36:03 PM PDT 24 Mar 12 12:36:04 PM PDT 24 88420717 ps
T886 /workspace/coverage/cover_reg_top/4.edn_intr_test.2924654072 Mar 12 12:35:49 PM PDT 24 Mar 12 12:35:50 PM PDT 24 10453526 ps
T887 /workspace/coverage/cover_reg_top/16.edn_tl_errors.4288168817 Mar 12 12:36:07 PM PDT 24 Mar 12 12:36:10 PM PDT 24 186541378 ps
T888 /workspace/coverage/cover_reg_top/35.edn_intr_test.3651252907 Mar 12 12:36:05 PM PDT 24 Mar 12 12:36:06 PM PDT 24 56518014 ps
T889 /workspace/coverage/cover_reg_top/27.edn_intr_test.2190341002 Mar 12 12:36:10 PM PDT 24 Mar 12 12:36:11 PM PDT 24 70900593 ps
T890 /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3653056617 Mar 12 12:36:08 PM PDT 24 Mar 12 12:36:10 PM PDT 24 53660550 ps
T891 /workspace/coverage/cover_reg_top/4.edn_csr_rw.2785763868 Mar 12 12:35:45 PM PDT 24 Mar 12 12:35:46 PM PDT 24 12571035 ps
T892 /workspace/coverage/cover_reg_top/7.edn_tl_errors.3909197585 Mar 12 12:36:00 PM PDT 24 Mar 12 12:36:02 PM PDT 24 238710839 ps
T893 /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.290249215 Mar 12 12:36:07 PM PDT 24 Mar 12 12:36:08 PM PDT 24 59620743 ps
T894 /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2341914037 Mar 12 12:35:46 PM PDT 24 Mar 12 12:35:49 PM PDT 24 96969063 ps
T895 /workspace/coverage/cover_reg_top/22.edn_intr_test.51529263 Mar 12 12:36:08 PM PDT 24 Mar 12 12:36:10 PM PDT 24 43399772 ps
T896 /workspace/coverage/cover_reg_top/5.edn_tl_errors.1707843166 Mar 12 12:35:50 PM PDT 24 Mar 12 12:35:53 PM PDT 24 97932284 ps
T897 /workspace/coverage/cover_reg_top/4.edn_tl_errors.2796554384 Mar 12 12:35:52 PM PDT 24 Mar 12 12:35:56 PM PDT 24 225431390 ps
T898 /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1723701708 Mar 12 12:35:46 PM PDT 24 Mar 12 12:35:49 PM PDT 24 49731766 ps
T899 /workspace/coverage/cover_reg_top/19.edn_csr_rw.361678589 Mar 12 12:36:08 PM PDT 24 Mar 12 12:36:09 PM PDT 24 97111329 ps
T900 /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2169249743 Mar 12 12:36:04 PM PDT 24 Mar 12 12:36:06 PM PDT 24 67957280 ps
T901 /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.216945812 Mar 12 12:35:46 PM PDT 24 Mar 12 12:35:50 PM PDT 24 196296328 ps
T902 /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2185753827 Mar 12 12:35:47 PM PDT 24 Mar 12 12:35:51 PM PDT 24 58302299 ps
T903 /workspace/coverage/cover_reg_top/12.edn_tl_errors.4086724374 Mar 12 12:36:08 PM PDT 24 Mar 12 12:36:11 PM PDT 24 132171202 ps
T904 /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.4206974728 Mar 12 12:36:04 PM PDT 24 Mar 12 12:36:06 PM PDT 24 45345957 ps
T905 /workspace/coverage/cover_reg_top/8.edn_tl_errors.958558731 Mar 12 12:35:58 PM PDT 24 Mar 12 12:36:03 PM PDT 24 93229537 ps
T906 /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.744924946 Mar 12 12:35:55 PM PDT 24 Mar 12 12:35:56 PM PDT 24 133355786 ps
T907 /workspace/coverage/cover_reg_top/15.edn_csr_rw.2492475851 Mar 12 12:36:07 PM PDT 24 Mar 12 12:36:08 PM PDT 24 34821927 ps
T908 /workspace/coverage/cover_reg_top/17.edn_csr_rw.1861511509 Mar 12 12:36:05 PM PDT 24 Mar 12 12:36:06 PM PDT 24 18324273 ps
T909 /workspace/coverage/cover_reg_top/44.edn_intr_test.4145421875 Mar 12 12:36:14 PM PDT 24 Mar 12 12:36:15 PM PDT 24 72133689 ps
T910 /workspace/coverage/cover_reg_top/13.edn_intr_test.4271510702 Mar 12 12:36:05 PM PDT 24 Mar 12 12:36:06 PM PDT 24 19427510 ps
T911 /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2125162723 Mar 12 12:35:51 PM PDT 24 Mar 12 12:35:53 PM PDT 24 42427859 ps
T912 /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.124753096 Mar 12 12:36:05 PM PDT 24 Mar 12 12:36:06 PM PDT 24 43223891 ps
T913 /workspace/coverage/cover_reg_top/40.edn_intr_test.707998920 Mar 12 12:36:16 PM PDT 24 Mar 12 12:36:17 PM PDT 24 13277347 ps
T914 /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1015736685 Mar 12 12:35:45 PM PDT 24 Mar 12 12:35:46 PM PDT 24 20689652 ps
T915 /workspace/coverage/cover_reg_top/49.edn_intr_test.1562753976 Mar 12 12:36:15 PM PDT 24 Mar 12 12:36:17 PM PDT 24 109014255 ps
T916 /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.298840264 Mar 12 12:35:51 PM PDT 24 Mar 12 12:35:54 PM PDT 24 443420642 ps
T917 /workspace/coverage/cover_reg_top/19.edn_intr_test.4033016186 Mar 12 12:36:07 PM PDT 24 Mar 12 12:36:07 PM PDT 24 35624497 ps
T918 /workspace/coverage/cover_reg_top/14.edn_tl_errors.56857158 Mar 12 12:36:05 PM PDT 24 Mar 12 12:36:11 PM PDT 24 704590657 ps
T919 /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1828920607 Mar 12 12:36:06 PM PDT 24 Mar 12 12:36:08 PM PDT 24 68257293 ps
T920 /workspace/coverage/cover_reg_top/18.edn_intr_test.2435808312 Mar 12 12:36:07 PM PDT 24 Mar 12 12:36:07 PM PDT 24 31323171 ps
T921 /workspace/coverage/cover_reg_top/19.edn_tl_errors.1907065256 Mar 12 12:36:07 PM PDT 24 Mar 12 12:36:09 PM PDT 24 165037378 ps
T922 /workspace/coverage/cover_reg_top/3.edn_tl_errors.2038786164 Mar 12 12:35:46 PM PDT 24 Mar 12 12:35:50 PM PDT 24 75464183 ps
T923 /workspace/coverage/cover_reg_top/10.edn_intr_test.3220910564 Mar 12 12:36:00 PM PDT 24 Mar 12 12:36:01 PM PDT 24 35569645 ps
T924 /workspace/coverage/cover_reg_top/21.edn_intr_test.2198208280 Mar 12 12:36:06 PM PDT 24 Mar 12 12:36:07 PM PDT 24 17754055 ps
T925 /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.818321235 Mar 12 12:36:07 PM PDT 24 Mar 12 12:36:08 PM PDT 24 14577105 ps
T926 /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3194025903 Mar 12 12:35:55 PM PDT 24 Mar 12 12:35:57 PM PDT 24 18269685 ps
T927 /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1659093101 Mar 12 12:35:55 PM PDT 24 Mar 12 12:35:57 PM PDT 24 79245884 ps
T928 /workspace/coverage/cover_reg_top/24.edn_intr_test.1595662975 Mar 12 12:36:05 PM PDT 24 Mar 12 12:36:06 PM PDT 24 16079213 ps
T929 /workspace/coverage/cover_reg_top/17.edn_intr_test.878457463 Mar 12 12:36:09 PM PDT 24 Mar 12 12:36:10 PM PDT 24 15469998 ps
T930 /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3496799264 Mar 12 12:36:04 PM PDT 24 Mar 12 12:36:05 PM PDT 24 20524154 ps
T931 /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4231826117 Mar 12 12:35:44 PM PDT 24 Mar 12 12:35:46 PM PDT 24 111964485 ps
T932 /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2752752151 Mar 12 12:36:04 PM PDT 24 Mar 12 12:36:05 PM PDT 24 17446718 ps
T216 /workspace/coverage/cover_reg_top/13.edn_csr_rw.947922817 Mar 12 12:36:05 PM PDT 24 Mar 12 12:36:06 PM PDT 24 29632555 ps
T933 /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.618841204 Mar 12 12:35:53 PM PDT 24 Mar 12 12:35:55 PM PDT 24 22447195 ps
T934 /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3972549261 Mar 12 12:35:56 PM PDT 24 Mar 12 12:35:59 PM PDT 24 112120276 ps
T242 /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3944312640 Mar 12 12:35:47 PM PDT 24 Mar 12 12:35:50 PM PDT 24 248539837 ps
T935 /workspace/coverage/cover_reg_top/30.edn_intr_test.194821179 Mar 12 12:36:06 PM PDT 24 Mar 12 12:36:07 PM PDT 24 14502651 ps
T936 /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.565498782 Mar 12 12:35:47 PM PDT 24 Mar 12 12:35:49 PM PDT 24 39082200 ps
T937 /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2305890245 Mar 12 12:36:03 PM PDT 24 Mar 12 12:36:05 PM PDT 24 35161296 ps
T938 /workspace/coverage/cover_reg_top/11.edn_tl_errors.1255013622 Mar 12 12:35:52 PM PDT 24 Mar 12 12:35:55 PM PDT 24 64705500 ps
T939 /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.814736710 Mar 12 12:35:54 PM PDT 24 Mar 12 12:35:56 PM PDT 24 195588094 ps
T940 /workspace/coverage/cover_reg_top/0.edn_tl_errors.1859099492 Mar 12 12:35:44 PM PDT 24 Mar 12 12:35:46 PM PDT 24 110664483 ps
T941 /workspace/coverage/cover_reg_top/42.edn_intr_test.1459564996 Mar 12 12:36:15 PM PDT 24 Mar 12 12:36:17 PM PDT 24 54199118 ps
T942 /workspace/coverage/cover_reg_top/13.edn_tl_errors.3574250815 Mar 12 12:36:09 PM PDT 24 Mar 12 12:36:13 PM PDT 24 227131479 ps
T943 /workspace/coverage/cover_reg_top/39.edn_intr_test.3929805978 Mar 12 12:36:16 PM PDT 24 Mar 12 12:36:18 PM PDT 24 17619937 ps
T243 /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2603158688 Mar 12 12:36:03 PM PDT 24 Mar 12 12:36:05 PM PDT 24 52837076 ps
T944 /workspace/coverage/cover_reg_top/9.edn_tl_errors.3877387865 Mar 12 12:36:00 PM PDT 24 Mar 12 12:36:02 PM PDT 24 276098946 ps
T945 /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.811323892 Mar 12 12:35:55 PM PDT 24 Mar 12 12:35:56 PM PDT 24 23990035 ps
T946 /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.4195088175 Mar 12 12:35:51 PM PDT 24 Mar 12 12:35:52 PM PDT 24 24073909 ps
T947 /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2186260582 Mar 12 12:35:59 PM PDT 24 Mar 12 12:36:01 PM PDT 24 38381233 ps
T948 /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2981135072 Mar 12 12:35:55 PM PDT 24 Mar 12 12:35:57 PM PDT 24 34021019 ps
T949 /workspace/coverage/cover_reg_top/48.edn_intr_test.3276627700 Mar 12 12:36:17 PM PDT 24 Mar 12 12:36:18 PM PDT 24 105175264 ps
T950 /workspace/coverage/cover_reg_top/45.edn_intr_test.2895370181 Mar 12 12:36:15 PM PDT 24 Mar 12 12:36:17 PM PDT 24 64595557 ps
T217 /workspace/coverage/cover_reg_top/2.edn_csr_rw.1233931445 Mar 12 12:35:52 PM PDT 24 Mar 12 12:35:53 PM PDT 24 13566130 ps
T951 /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1408683125 Mar 12 12:35:45 PM PDT 24 Mar 12 12:35:46 PM PDT 24 26646467 ps
T952 /workspace/coverage/cover_reg_top/6.edn_tl_errors.2211817205 Mar 12 12:35:55 PM PDT 24 Mar 12 12:35:58 PM PDT 24 43546740 ps
T953 /workspace/coverage/cover_reg_top/7.edn_csr_rw.3885420502 Mar 12 12:35:57 PM PDT 24 Mar 12 12:35:58 PM PDT 24 13354679 ps
T954 /workspace/coverage/cover_reg_top/33.edn_intr_test.2829398173 Mar 12 12:36:07 PM PDT 24 Mar 12 12:36:08 PM PDT 24 13125953 ps
T955 /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2012463574 Mar 12 12:35:52 PM PDT 24 Mar 12 12:35:57 PM PDT 24 343399936 ps
T956 /workspace/coverage/cover_reg_top/15.edn_intr_test.3343403661 Mar 12 12:36:03 PM PDT 24 Mar 12 12:36:04 PM PDT 24 61230589 ps
T957 /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3241486286 Mar 12 12:35:56 PM PDT 24 Mar 12 12:35:58 PM PDT 24 52646749 ps
T958 /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1139635588 Mar 12 12:35:57 PM PDT 24 Mar 12 12:35:58 PM PDT 24 33991511 ps
T959 /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1495216683 Mar 12 12:35:46 PM PDT 24 Mar 12 12:35:49 PM PDT 24 34871184 ps
T960 /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.644664233 Mar 12 12:35:58 PM PDT 24 Mar 12 12:35:59 PM PDT 24 89685963 ps
T961 /workspace/coverage/cover_reg_top/10.edn_tl_errors.2638785431 Mar 12 12:35:57 PM PDT 24 Mar 12 12:36:01 PM PDT 24 471542484 ps
T962 /workspace/coverage/cover_reg_top/31.edn_intr_test.3626941938 Mar 12 12:36:05 PM PDT 24 Mar 12 12:36:06 PM PDT 24 14567936 ps
T963 /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1226088202 Mar 12 12:36:08 PM PDT 24 Mar 12 12:36:10 PM PDT 24 33443926 ps
T964 /workspace/coverage/cover_reg_top/16.edn_intr_test.3634723866 Mar 12 12:36:08 PM PDT 24 Mar 12 12:36:10 PM PDT 24 14986657 ps
T965 /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1308632586 Mar 12 12:36:08 PM PDT 24 Mar 12 12:36:11 PM PDT 24 753592398 ps
T218 /workspace/coverage/cover_reg_top/11.edn_csr_rw.2846054192 Mar 12 12:35:58 PM PDT 24 Mar 12 12:36:00 PM PDT 24 14467618 ps
T219 /workspace/coverage/cover_reg_top/18.edn_csr_rw.712495006 Mar 12 12:36:05 PM PDT 24 Mar 12 12:36:06 PM PDT 24 18038399 ps
T966 /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2405180910 Mar 12 12:35:55 PM PDT 24 Mar 12 12:35:56 PM PDT 24 26097636 ps
T967 /workspace/coverage/cover_reg_top/1.edn_csr_rw.4174626547 Mar 12 12:35:46 PM PDT 24 Mar 12 12:35:49 PM PDT 24 22513191 ps
T968 /workspace/coverage/cover_reg_top/1.edn_intr_test.3603259136 Mar 12 12:35:45 PM PDT 24 Mar 12 12:35:46 PM PDT 24 15330901 ps
T969 /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2737022281 Mar 12 12:35:52 PM PDT 24 Mar 12 12:35:54 PM PDT 24 53756649 ps

Test location /workspace/coverage/default/162.edn_genbits.1708041847
Short name T6
Test name
Test status
Simulation time 41607204 ps
CPU time 1.65 seconds
Started Mar 12 02:46:19 PM PDT 24
Finished Mar 12 02:46:21 PM PDT 24
Peak memory 215904 kb
Host smart-20d36019-505b-4a70-a6bf-566fb95a5856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708041847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.edn_genbits.1708041847
Directory /workspace/162.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_stress_all_with_rand_reset.3360706425
Short name T24
Test name
Test status
Simulation time 20098595201 ps
CPU time 435.96 seconds
Started Mar 12 02:45:26 PM PDT 24
Finished Mar 12 02:52:42 PM PDT 24
Peak memory 222768 kb
Host smart-04d17560-11fc-4e14-a8f2-1868685953d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360706425 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.edn_stress_all_with_rand_reset.3360706425
Directory /workspace/47.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.edn_disable_auto_req_mode.2888176805
Short name T10
Test name
Test status
Simulation time 41459891 ps
CPU time 1.41 seconds
Started Mar 12 02:43:44 PM PDT 24
Finished Mar 12 02:43:46 PM PDT 24
Peak memory 215668 kb
Host smart-4deb5b03-f606-49f2-afa5-5a70c0c5fc1d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888176805 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_d
isable_auto_req_mode.2888176805
Directory /workspace/11.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/4.edn_sec_cm.2447561535
Short name T20
Test name
Test status
Simulation time 1249900919 ps
CPU time 3.53 seconds
Started Mar 12 02:43:20 PM PDT 24
Finished Mar 12 02:43:23 PM PDT 24
Peak memory 233672 kb
Host smart-5f07fbaf-2ca2-4f3e-9b8a-2f57a3ee638c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447561535 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_sec_cm.2447561535
Directory /workspace/4.edn_sec_cm/latest

Test location /workspace/coverage/default/45.edn_err.2120282328
Short name T16
Test name
Test status
Simulation time 33740755 ps
CPU time 0.99 seconds
Started Mar 12 02:45:25 PM PDT 24
Finished Mar 12 02:45:27 PM PDT 24
Peak memory 222340 kb
Host smart-2ca8db00-c1ef-4dc0-81ff-dc6365d62c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120282328 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_err.2120282328
Directory /workspace/45.edn_err/latest

Test location /workspace/coverage/default/7.edn_alert.1347415383
Short name T18
Test name
Test status
Simulation time 23928232 ps
CPU time 1.23 seconds
Started Mar 12 02:43:29 PM PDT 24
Finished Mar 12 02:43:30 PM PDT 24
Peak memory 214840 kb
Host smart-0595e914-8f58-4fed-a4d3-77d8f6a69e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347415383 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert.1347415383
Directory /workspace/7.edn_alert/latest

Test location /workspace/coverage/default/242.edn_genbits.2400846750
Short name T27
Test name
Test status
Simulation time 126994171 ps
CPU time 1.57 seconds
Started Mar 12 02:46:28 PM PDT 24
Finished Mar 12 02:46:30 PM PDT 24
Peak memory 217580 kb
Host smart-7f7c2a9d-339c-4ff6-8e03-e44172f2f50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400846750 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.edn_genbits.2400846750
Directory /workspace/242.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_disable.2682252032
Short name T116
Test name
Test status
Simulation time 13453325 ps
CPU time 0.89 seconds
Started Mar 12 02:43:44 PM PDT 24
Finished Mar 12 02:43:45 PM PDT 24
Peak memory 215044 kb
Host smart-c131125d-9203-49cf-8def-7ed61541b2bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682252032 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_disable.2682252032
Directory /workspace/10.edn_disable/latest

Test location /workspace/coverage/default/16.edn_genbits.4137846103
Short name T13
Test name
Test status
Simulation time 49633393 ps
CPU time 1.19 seconds
Started Mar 12 02:43:56 PM PDT 24
Finished Mar 12 02:43:59 PM PDT 24
Peak memory 217032 kb
Host smart-0913c926-bfc0-43ed-bcde-8d3434e74aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137846103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_genbits.4137846103
Directory /workspace/16.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_intr.587923179
Short name T136
Test name
Test status
Simulation time 57303808 ps
CPU time 0.87 seconds
Started Mar 12 02:44:55 PM PDT 24
Finished Mar 12 02:44:56 PM PDT 24
Peak memory 214696 kb
Host smart-f6909f1d-f78f-4fba-8e6e-7d1b09e22069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587923179 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_intr.587923179
Directory /workspace/36.edn_intr/latest

Test location /workspace/coverage/default/14.edn_stress_all_with_rand_reset.2279082204
Short name T188
Test name
Test status
Simulation time 54221000877 ps
CPU time 1220.24 seconds
Started Mar 12 02:43:50 PM PDT 24
Finished Mar 12 03:04:11 PM PDT 24
Peak memory 219324 kb
Host smart-3656319d-d0dc-42ab-8162-d60f62fdf993
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279082204 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.edn_stress_all_with_rand_reset.2279082204
Directory /workspace/14.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert.1600146849
Short name T179
Test name
Test status
Simulation time 32504037 ps
CPU time 1.38 seconds
Started Mar 12 02:45:36 PM PDT 24
Finished Mar 12 02:45:39 PM PDT 24
Peak memory 214668 kb
Host smart-d7a4bf9a-8056-4f1f-b8a5-3c8393086606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600146849 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert.1600146849
Directory /workspace/49.edn_alert/latest

Test location /workspace/coverage/default/0.edn_regwen.2493310319
Short name T131
Test name
Test status
Simulation time 115605087 ps
CPU time 0.97 seconds
Started Mar 12 02:42:55 PM PDT 24
Finished Mar 12 02:42:56 PM PDT 24
Peak memory 206236 kb
Host smart-f5639540-48c5-4f6e-a9c3-bbe68f1ffb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493310319 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_regwen.2493310319
Directory /workspace/0.edn_regwen/latest

Test location /workspace/coverage/default/10.edn_alert.76732077
Short name T149
Test name
Test status
Simulation time 40719126 ps
CPU time 1.19 seconds
Started Mar 12 02:43:42 PM PDT 24
Finished Mar 12 02:43:44 PM PDT 24
Peak memory 214856 kb
Host smart-980f4d90-6717-4f7a-b303-7978a4aebe48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76732077 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert.76732077
Directory /workspace/10.edn_alert/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_intg_err.1207319963
Short name T240
Test name
Test status
Simulation time 1254132922 ps
CPU time 2.4 seconds
Started Mar 12 12:35:53 PM PDT 24
Finished Mar 12 12:35:56 PM PDT 24
Peak memory 206612 kb
Host smart-0b1ea40f-1397-41b8-a6d9-f52cbf302515
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207319963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_intg_err.1207319963
Directory /workspace/4.edn_tl_intg_err/latest

Test location /workspace/coverage/default/34.edn_alert.918322601
Short name T110
Test name
Test status
Simulation time 43582243 ps
CPU time 1.16 seconds
Started Mar 12 02:44:52 PM PDT 24
Finished Mar 12 02:44:53 PM PDT 24
Peak memory 214808 kb
Host smart-fd807ee5-c959-4e97-9978-2408ad48b3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918322601 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert.918322601
Directory /workspace/34.edn_alert/latest

Test location /workspace/coverage/default/24.edn_disable.2412818100
Short name T153
Test name
Test status
Simulation time 15428976 ps
CPU time 0.8 seconds
Started Mar 12 02:44:27 PM PDT 24
Finished Mar 12 02:44:28 PM PDT 24
Peak memory 215016 kb
Host smart-53a01eff-bb59-4d91-97b6-3b1bce2c0500
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412818100 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_disable.2412818100
Directory /workspace/24.edn_disable/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_rw.2215867947
Short name T213
Test name
Test status
Simulation time 74309353 ps
CPU time 0.81 seconds
Started Mar 12 12:35:56 PM PDT 24
Finished Mar 12 12:35:56 PM PDT 24
Peak memory 206640 kb
Host smart-6b10b288-12bc-46bb-9231-f95b70b1d87c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215867947 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_csr_rw.2215867947
Directory /workspace/6.edn_csr_rw/latest

Test location /workspace/coverage/default/22.edn_intr.2030041652
Short name T17
Test name
Test status
Simulation time 38197759 ps
CPU time 1.09 seconds
Started Mar 12 02:44:23 PM PDT 24
Finished Mar 12 02:44:24 PM PDT 24
Peak memory 223396 kb
Host smart-37d7f109-3558-45d9-a586-e3723d1599a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030041652 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_intr.2030041652
Directory /workspace/22.edn_intr/latest

Test location /workspace/coverage/default/19.edn_disable.3916796443
Short name T112
Test name
Test status
Simulation time 23904163 ps
CPU time 0.85 seconds
Started Mar 12 02:44:17 PM PDT 24
Finished Mar 12 02:44:19 PM PDT 24
Peak memory 214876 kb
Host smart-2b2c072e-507c-4f37-a420-62da4affb1cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916796443 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_disable.3916796443
Directory /workspace/19.edn_disable/latest

Test location /workspace/coverage/default/2.edn_disable.953487919
Short name T157
Test name
Test status
Simulation time 33593017 ps
CPU time 0.87 seconds
Started Mar 12 02:43:12 PM PDT 24
Finished Mar 12 02:43:13 PM PDT 24
Peak memory 214948 kb
Host smart-94d0575b-e8cb-4e08-a324-bdd2e757bd0b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953487919 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_disable.953487919
Directory /workspace/2.edn_disable/latest

Test location /workspace/coverage/default/40.edn_disable_auto_req_mode.4093918641
Short name T76
Test name
Test status
Simulation time 39376450 ps
CPU time 1.36 seconds
Started Mar 12 02:45:10 PM PDT 24
Finished Mar 12 02:45:11 PM PDT 24
Peak memory 215564 kb
Host smart-975137a3-d778-4941-9f1c-60c2cf2a5b4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093918641 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_d
isable_auto_req_mode.4093918641
Directory /workspace/40.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_intr.3270283113
Short name T135
Test name
Test status
Simulation time 20001759 ps
CPU time 1.06 seconds
Started Mar 12 02:44:06 PM PDT 24
Finished Mar 12 02:44:07 PM PDT 24
Peak memory 214836 kb
Host smart-03a4b1c0-f405-49bb-9357-264548545a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270283113 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_intr.3270283113
Directory /workspace/18.edn_intr/latest

Test location /workspace/coverage/default/129.edn_genbits.341841129
Short name T288
Test name
Test status
Simulation time 116217326 ps
CPU time 1.4 seconds
Started Mar 12 02:46:10 PM PDT 24
Finished Mar 12 02:46:12 PM PDT 24
Peak memory 217764 kb
Host smart-fe2b4487-014e-4299-8d68-f85d4c80bd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341841129 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.edn_genbits.341841129
Directory /workspace/129.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_alert.1949557233
Short name T105
Test name
Test status
Simulation time 22169922 ps
CPU time 1.14 seconds
Started Mar 12 02:44:58 PM PDT 24
Finished Mar 12 02:44:59 PM PDT 24
Peak memory 214852 kb
Host smart-3c15bd4d-b805-411b-9013-52724c55932a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949557233 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert.1949557233
Directory /workspace/33.edn_alert/latest

Test location /workspace/coverage/default/89.edn_genbits.2101000347
Short name T34
Test name
Test status
Simulation time 41540132 ps
CPU time 1.72 seconds
Started Mar 12 02:45:48 PM PDT 24
Finished Mar 12 02:45:51 PM PDT 24
Peak memory 215796 kb
Host smart-98b0ec2d-f50c-4fb5-adaf-87570afa9815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101000347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_genbits.2101000347
Directory /workspace/89.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_disable_auto_req_mode.2431488791
Short name T95
Test name
Test status
Simulation time 114412794 ps
CPU time 1.21 seconds
Started Mar 12 02:43:21 PM PDT 24
Finished Mar 12 02:43:23 PM PDT 24
Peak memory 215712 kb
Host smart-7e779b1e-9e35-4891-8e47-7d47d20246d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431488791 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_di
sable_auto_req_mode.2431488791
Directory /workspace/4.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_regwen.1678788768
Short name T769
Test name
Test status
Simulation time 27125900 ps
CPU time 0.94 seconds
Started Mar 12 02:43:18 PM PDT 24
Finished Mar 12 02:43:19 PM PDT 24
Peak memory 206240 kb
Host smart-b4074216-e559-4dac-90e9-7a5bb905f34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678788768 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_regwen.1678788768
Directory /workspace/5.edn_regwen/latest

Test location /workspace/coverage/default/23.edn_disable_auto_req_mode.2460295798
Short name T49
Test name
Test status
Simulation time 62571841 ps
CPU time 0.99 seconds
Started Mar 12 02:44:25 PM PDT 24
Finished Mar 12 02:44:27 PM PDT 24
Peak memory 216668 kb
Host smart-6cb56b78-b386-4c73-8c1b-454ced8391f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460295798 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_d
isable_auto_req_mode.2460295798
Directory /workspace/23.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_disable.3903794483
Short name T173
Test name
Test status
Simulation time 11346281 ps
CPU time 0.87 seconds
Started Mar 12 02:44:36 PM PDT 24
Finished Mar 12 02:44:37 PM PDT 24
Peak memory 215156 kb
Host smart-98b871a1-e05c-4afa-a237-623f6e11ca01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903794483 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_disable.3903794483
Directory /workspace/25.edn_disable/latest

Test location /workspace/coverage/default/39.edn_disable.2733400063
Short name T99
Test name
Test status
Simulation time 12805877 ps
CPU time 0.95 seconds
Started Mar 12 02:45:14 PM PDT 24
Finished Mar 12 02:45:15 PM PDT 24
Peak memory 214632 kb
Host smart-c096fd76-8d13-42f5-9bf0-689f2d45a1d3
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733400063 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_disable.2733400063
Directory /workspace/39.edn_disable/latest

Test location /workspace/coverage/default/47.edn_disable.1613066614
Short name T119
Test name
Test status
Simulation time 14409160 ps
CPU time 0.91 seconds
Started Mar 12 02:45:26 PM PDT 24
Finished Mar 12 02:45:27 PM PDT 24
Peak memory 214720 kb
Host smart-292b9c34-6224-408f-bf2e-40cd9340b46e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613066614 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_disable.1613066614
Directory /workspace/47.edn_disable/latest

Test location /workspace/coverage/default/11.edn_disable.320075301
Short name T172
Test name
Test status
Simulation time 12311118 ps
CPU time 0.91 seconds
Started Mar 12 02:43:41 PM PDT 24
Finished Mar 12 02:43:42 PM PDT 24
Peak memory 215092 kb
Host smart-3cc8e4f1-e495-469a-8c5a-5f1eb86c9c85
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320075301 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.320075301
Directory /workspace/11.edn_disable/latest

Test location /workspace/coverage/default/15.edn_disable_auto_req_mode.3668383121
Short name T81
Test name
Test status
Simulation time 234600830 ps
CPU time 1.3 seconds
Started Mar 12 02:43:57 PM PDT 24
Finished Mar 12 02:44:00 PM PDT 24
Peak memory 215408 kb
Host smart-b926991f-16ec-4705-843e-4ed67ece9c44
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668383121 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_d
isable_auto_req_mode.3668383121
Directory /workspace/15.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_disable.4086991473
Short name T165
Test name
Test status
Simulation time 39799281 ps
CPU time 0.86 seconds
Started Mar 12 02:44:51 PM PDT 24
Finished Mar 12 02:44:52 PM PDT 24
Peak memory 214876 kb
Host smart-50785122-55fb-40a8-9f65-ee9c88d78dc9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086991473 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_disable.4086991473
Directory /workspace/30.edn_disable/latest

Test location /workspace/coverage/default/15.edn_alert_test.3211280446
Short name T51
Test name
Test status
Simulation time 18895930 ps
CPU time 0.98 seconds
Started Mar 12 02:43:58 PM PDT 24
Finished Mar 12 02:44:00 PM PDT 24
Peak memory 206020 kb
Host smart-f7c32b38-d3fe-4902-a355-fab5ad0899a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211280446 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert_test.3211280446
Directory /workspace/15.edn_alert_test/latest

Test location /workspace/coverage/default/219.edn_genbits.2308570451
Short name T277
Test name
Test status
Simulation time 40908979 ps
CPU time 1.46 seconds
Started Mar 12 02:46:26 PM PDT 24
Finished Mar 12 02:46:27 PM PDT 24
Peak memory 217740 kb
Host smart-32e92860-def7-4a9b-9f6b-595af857a574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308570451 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.edn_genbits.2308570451
Directory /workspace/219.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_genbits.2672815860
Short name T284
Test name
Test status
Simulation time 59763769 ps
CPU time 1.18 seconds
Started Mar 12 02:44:33 PM PDT 24
Finished Mar 12 02:44:35 PM PDT 24
Peak memory 216792 kb
Host smart-7181203a-7965-4f5f-9b80-03ed8eed3cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672815860 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_genbits.2672815860
Directory /workspace/27.edn_genbits/latest

Test location /workspace/coverage/default/294.edn_genbits.274256053
Short name T256
Test name
Test status
Simulation time 176574682 ps
CPU time 1.05 seconds
Started Mar 12 02:46:35 PM PDT 24
Finished Mar 12 02:46:37 PM PDT 24
Peak memory 215700 kb
Host smart-7fecd92f-fccc-414e-ab20-1f282210b74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274256053 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.edn_genbits.274256053
Directory /workspace/294.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_err.2888424884
Short name T64
Test name
Test status
Simulation time 32359779 ps
CPU time 0.84 seconds
Started Mar 12 02:44:27 PM PDT 24
Finished Mar 12 02:44:28 PM PDT 24
Peak memory 217100 kb
Host smart-67d91663-51ac-49c4-aee6-2de41ff8d1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888424884 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_err.2888424884
Directory /workspace/24.edn_err/latest

Test location /workspace/coverage/default/30.edn_alert.2780938329
Short name T561
Test name
Test status
Simulation time 29660046 ps
CPU time 1.26 seconds
Started Mar 12 02:44:50 PM PDT 24
Finished Mar 12 02:44:52 PM PDT 24
Peak memory 214736 kb
Host smart-38e459cc-902f-41b8-ad3c-905b57830f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780938329 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert.2780938329
Directory /workspace/30.edn_alert/latest

Test location /workspace/coverage/default/49.edn_genbits.3464030582
Short name T291
Test name
Test status
Simulation time 312623588 ps
CPU time 3.57 seconds
Started Mar 12 02:45:35 PM PDT 24
Finished Mar 12 02:45:39 PM PDT 24
Peak memory 217108 kb
Host smart-7592fccc-e50a-465f-b0a9-d9b96999a26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464030582 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_genbits.3464030582
Directory /workspace/49.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_intr.65669670
Short name T141
Test name
Test status
Simulation time 20776183 ps
CPU time 1.03 seconds
Started Mar 12 02:45:08 PM PDT 24
Finished Mar 12 02:45:09 PM PDT 24
Peak memory 214768 kb
Host smart-29218c70-e9dd-43dd-b9fe-99a5cd7ee035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65669670 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_intr.65669670
Directory /workspace/39.edn_intr/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_aliasing.2155698699
Short name T228
Test name
Test status
Simulation time 34279098 ps
CPU time 0.96 seconds
Started Mar 12 12:35:47 PM PDT 24
Finished Mar 12 12:35:49 PM PDT 24
Peak memory 206596 kb
Host smart-fc62ab4e-a790-460f-8177-1159284903e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155698699 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_aliasing.2155698699
Directory /workspace/0.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_rw.712495006
Short name T219
Test name
Test status
Simulation time 18038399 ps
CPU time 0.85 seconds
Started Mar 12 12:36:05 PM PDT 24
Finished Mar 12 12:36:06 PM PDT 24
Peak memory 206536 kb
Host smart-9aef32d4-d2a2-427f-90d9-d628dc4cb2a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712495006 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_csr_rw.712495006
Directory /workspace/18.edn_csr_rw/latest

Test location /workspace/coverage/default/10.edn_err.2047531530
Short name T379
Test name
Test status
Simulation time 84041085 ps
CPU time 0.88 seconds
Started Mar 12 02:43:41 PM PDT 24
Finished Mar 12 02:43:42 PM PDT 24
Peak memory 217104 kb
Host smart-eddea405-a435-4e5a-8c7d-eaa082a48011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047531530 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_err.2047531530
Directory /workspace/10.edn_err/latest

Test location /workspace/coverage/default/1.edn_regwen.1760264723
Short name T129
Test name
Test status
Simulation time 227046963 ps
CPU time 0.98 seconds
Started Mar 12 02:47:19 PM PDT 24
Finished Mar 12 02:47:20 PM PDT 24
Peak memory 206196 kb
Host smart-6284e626-15a5-45a9-b14e-e1cddb758507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760264723 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_regwen.1760264723
Directory /workspace/1.edn_regwen/latest

Test location /workspace/coverage/default/102.edn_genbits.3260192752
Short name T281
Test name
Test status
Simulation time 58633966 ps
CPU time 2.35 seconds
Started Mar 12 02:45:57 PM PDT 24
Finished Mar 12 02:46:00 PM PDT 24
Peak memory 217144 kb
Host smart-1c698136-3bf0-4c3b-8cf4-65c8578bba8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260192752 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.edn_genbits.3260192752
Directory /workspace/102.edn_genbits/latest

Test location /workspace/coverage/default/109.edn_genbits.3122678660
Short name T485
Test name
Test status
Simulation time 97544081 ps
CPU time 1.18 seconds
Started Mar 12 02:46:00 PM PDT 24
Finished Mar 12 02:46:01 PM PDT 24
Peak memory 215800 kb
Host smart-a228c1bb-1070-4ccb-806c-e3993690da29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122678660 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.edn_genbits.3122678660
Directory /workspace/109.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert.2431826479
Short name T180
Test name
Test status
Simulation time 27628365 ps
CPU time 1.26 seconds
Started Mar 12 02:43:44 PM PDT 24
Finished Mar 12 02:43:46 PM PDT 24
Peak memory 214828 kb
Host smart-cd51a666-3344-46bb-a303-e6ce88f86b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431826479 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert.2431826479
Directory /workspace/11.edn_alert/latest

Test location /workspace/coverage/default/11.edn_genbits.249018858
Short name T268
Test name
Test status
Simulation time 53944644 ps
CPU time 1.06 seconds
Started Mar 12 02:43:40 PM PDT 24
Finished Mar 12 02:43:41 PM PDT 24
Peak memory 215808 kb
Host smart-f265a551-5ac5-4979-be53-bd2e5203a59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249018858 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_genbits.249018858
Directory /workspace/11.edn_genbits/latest

Test location /workspace/coverage/default/125.edn_genbits.1008436577
Short name T824
Test name
Test status
Simulation time 81258527 ps
CPU time 1.26 seconds
Started Mar 12 02:46:05 PM PDT 24
Finished Mar 12 02:46:07 PM PDT 24
Peak memory 215732 kb
Host smart-0732de87-93fe-40ce-98b9-b0c7cbb6bbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008436577 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.edn_genbits.1008436577
Directory /workspace/125.edn_genbits/latest

Test location /workspace/coverage/default/131.edn_genbits.1350043872
Short name T260
Test name
Test status
Simulation time 85848126 ps
CPU time 1.92 seconds
Started Mar 12 02:46:05 PM PDT 24
Finished Mar 12 02:46:07 PM PDT 24
Peak memory 216960 kb
Host smart-2a7fc7c7-e28f-4c32-85f9-dc963b2b06a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350043872 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.edn_genbits.1350043872
Directory /workspace/131.edn_genbits/latest

Test location /workspace/coverage/default/140.edn_genbits.2395242747
Short name T264
Test name
Test status
Simulation time 29469568 ps
CPU time 1.3 seconds
Started Mar 12 02:46:08 PM PDT 24
Finished Mar 12 02:46:09 PM PDT 24
Peak memory 216904 kb
Host smart-4fb49b58-d686-47c3-bdc8-bd553f36c631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395242747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.edn_genbits.2395242747
Directory /workspace/140.edn_genbits/latest

Test location /workspace/coverage/default/144.edn_genbits.711172569
Short name T283
Test name
Test status
Simulation time 44159182 ps
CPU time 1.35 seconds
Started Mar 12 02:46:07 PM PDT 24
Finished Mar 12 02:46:08 PM PDT 24
Peak memory 217844 kb
Host smart-306ac36f-181f-44d0-a5a7-d427dd41ff46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711172569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.edn_genbits.711172569
Directory /workspace/144.edn_genbits/latest

Test location /workspace/coverage/default/150.edn_genbits.132670883
Short name T2
Test name
Test status
Simulation time 73965578 ps
CPU time 1.11 seconds
Started Mar 12 02:46:06 PM PDT 24
Finished Mar 12 02:46:07 PM PDT 24
Peak memory 215716 kb
Host smart-615694e0-f7f6-4bf1-a783-66e851822472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132670883 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.edn_genbits.132670883
Directory /workspace/150.edn_genbits/latest

Test location /workspace/coverage/default/151.edn_genbits.400542404
Short name T266
Test name
Test status
Simulation time 34990312 ps
CPU time 1.44 seconds
Started Mar 12 02:46:07 PM PDT 24
Finished Mar 12 02:46:09 PM PDT 24
Peak memory 216712 kb
Host smart-b0756a76-048b-45fc-b8b5-8deefa46cbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400542404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.edn_genbits.400542404
Directory /workspace/151.edn_genbits/latest

Test location /workspace/coverage/default/248.edn_genbits.1025349540
Short name T273
Test name
Test status
Simulation time 966874706 ps
CPU time 7.37 seconds
Started Mar 12 02:46:35 PM PDT 24
Finished Mar 12 02:46:44 PM PDT 24
Peak memory 216996 kb
Host smart-101c5254-099d-47f8-9c10-d8f31fae34d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025349540 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.edn_genbits.1025349540
Directory /workspace/248.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_regwen.3636846543
Short name T245
Test name
Test status
Simulation time 14616661 ps
CPU time 0.95 seconds
Started Mar 12 02:43:11 PM PDT 24
Finished Mar 12 02:43:13 PM PDT 24
Peak memory 206236 kb
Host smart-027b7239-a483-45c8-ad1c-8d6e7e6c3c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636846543 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_regwen.3636846543
Directory /workspace/3.edn_regwen/latest

Test location /workspace/coverage/default/32.edn_alert.1980535991
Short name T255
Test name
Test status
Simulation time 119197525 ps
CPU time 1.28 seconds
Started Mar 12 02:44:45 PM PDT 24
Finished Mar 12 02:44:47 PM PDT 24
Peak memory 214844 kb
Host smart-d85a3a41-cbae-4803-b9bc-28d445aa8d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980535991 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert.1980535991
Directory /workspace/32.edn_alert/latest

Test location /workspace/coverage/default/13.edn_intr.792539970
Short name T826
Test name
Test status
Simulation time 20279207 ps
CPU time 1.07 seconds
Started Mar 12 02:43:51 PM PDT 24
Finished Mar 12 02:43:52 PM PDT 24
Peak memory 214820 kb
Host smart-373fa988-05a4-4a80-813a-51390bbc0a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792539970 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_intr.792539970
Directory /workspace/13.edn_intr/latest

Test location /workspace/coverage/default/165.edn_genbits.3503115011
Short name T365
Test name
Test status
Simulation time 120903002 ps
CPU time 1.43 seconds
Started Mar 12 02:46:18 PM PDT 24
Finished Mar 12 02:46:20 PM PDT 24
Peak memory 217080 kb
Host smart-d2f4c52f-03e8-452a-b2c0-3b3f60a6e04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503115011 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.edn_genbits.3503115011
Directory /workspace/165.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_err.3276052995
Short name T70
Test name
Test status
Simulation time 42372426 ps
CPU time 1.12 seconds
Started Mar 12 02:44:24 PM PDT 24
Finished Mar 12 02:44:26 PM PDT 24
Peak memory 214616 kb
Host smart-66d9cf58-4c81-4022-81a9-3ce31ce72c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276052995 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_err.3276052995
Directory /workspace/22.edn_err/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_bit_bash.225717400
Short name T875
Test name
Test status
Simulation time 176524107 ps
CPU time 4.9 seconds
Started Mar 12 12:35:43 PM PDT 24
Finished Mar 12 12:35:48 PM PDT 24
Peak memory 206656 kb
Host smart-a755d28c-5d22-4687-b772-6ca4d5231681
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225717400 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_bit_bash.225717400
Directory /workspace/0.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_hw_reset.1723701708
Short name T898
Test name
Test status
Simulation time 49731766 ps
CPU time 0.91 seconds
Started Mar 12 12:35:46 PM PDT 24
Finished Mar 12 12:35:49 PM PDT 24
Peak memory 206644 kb
Host smart-c141d4f8-26ae-4004-9c3e-fee4b88417a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723701708 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_hw_reset.1723701708
Directory /workspace/0.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_mem_rw_with_rand_reset.1578011978
Short name T856
Test name
Test status
Simulation time 63771138 ps
CPU time 1.49 seconds
Started Mar 12 12:35:44 PM PDT 24
Finished Mar 12 12:35:45 PM PDT 24
Peak memory 214916 kb
Host smart-b1a20c64-f620-41e6-81b6-70d3db036aca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578011978 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.edn_csr_mem_rw_with_rand_reset.1578011978
Directory /workspace/0.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.edn_csr_rw.4094422280
Short name T210
Test name
Test status
Simulation time 30431167 ps
CPU time 0.79 seconds
Started Mar 12 12:35:45 PM PDT 24
Finished Mar 12 12:35:46 PM PDT 24
Peak memory 206248 kb
Host smart-bd446d24-6fa2-4101-a93c-b7533acb7ac2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094422280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_csr_rw.4094422280
Directory /workspace/0.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.edn_intr_test.2010340013
Short name T862
Test name
Test status
Simulation time 16367870 ps
CPU time 0.88 seconds
Started Mar 12 12:35:46 PM PDT 24
Finished Mar 12 12:35:49 PM PDT 24
Peak memory 206584 kb
Host smart-88db3f6a-0258-4795-ab9b-c5cc7538bcb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010340013 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_intr_test.2010340013
Directory /workspace/0.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.edn_same_csr_outstanding.1015736685
Short name T914
Test name
Test status
Simulation time 20689652 ps
CPU time 1.06 seconds
Started Mar 12 12:35:45 PM PDT 24
Finished Mar 12 12:35:46 PM PDT 24
Peak memory 206420 kb
Host smart-027d9fc5-1fee-4d2b-a78d-b5977bdb9d20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015736685 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_ou
tstanding.1015736685
Directory /workspace/0.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_errors.1859099492
Short name T940
Test name
Test status
Simulation time 110664483 ps
CPU time 2 seconds
Started Mar 12 12:35:44 PM PDT 24
Finished Mar 12 12:35:46 PM PDT 24
Peak memory 214748 kb
Host smart-113026b2-86a4-40f8-81a4-2637d8074b7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859099492 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_errors.1859099492
Directory /workspace/0.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.edn_tl_intg_err.4231826117
Short name T931
Test name
Test status
Simulation time 111964485 ps
CPU time 1.56 seconds
Started Mar 12 12:35:44 PM PDT 24
Finished Mar 12 12:35:46 PM PDT 24
Peak memory 206684 kb
Host smart-9ef0a6fc-d0a3-4f46-9a9d-87065a88d190
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231826117 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_tl_intg_err.4231826117
Directory /workspace/0.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_aliasing.1722408744
Short name T212
Test name
Test status
Simulation time 47388707 ps
CPU time 0.95 seconds
Started Mar 12 12:35:46 PM PDT 24
Finished Mar 12 12:35:49 PM PDT 24
Peak memory 206656 kb
Host smart-941d5dcb-c74d-42d0-8db4-05e50a1d383b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722408744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_aliasing.1722408744
Directory /workspace/1.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_bit_bash.59774677
Short name T229
Test name
Test status
Simulation time 524104469 ps
CPU time 6.39 seconds
Started Mar 12 12:35:44 PM PDT 24
Finished Mar 12 12:35:50 PM PDT 24
Peak memory 206664 kb
Host smart-04141a19-b8f8-4205-aa96-ff080c0d7b3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59774677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_bit_bash.59774677
Directory /workspace/1.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_hw_reset.4195088175
Short name T946
Test name
Test status
Simulation time 24073909 ps
CPU time 0.87 seconds
Started Mar 12 12:35:51 PM PDT 24
Finished Mar 12 12:35:52 PM PDT 24
Peak memory 206460 kb
Host smart-64d69fe2-51ae-49fd-aed6-e1118ff36213
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195088175 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_hw_reset.4195088175
Directory /workspace/1.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_mem_rw_with_rand_reset.3055467315
Short name T877
Test name
Test status
Simulation time 330990250 ps
CPU time 1.17 seconds
Started Mar 12 12:35:47 PM PDT 24
Finished Mar 12 12:35:49 PM PDT 24
Peak memory 214828 kb
Host smart-aea61d37-19d0-4969-8fc9-1d43beec1893
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055467315 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.edn_csr_mem_rw_with_rand_reset.3055467315
Directory /workspace/1.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.edn_csr_rw.4174626547
Short name T967
Test name
Test status
Simulation time 22513191 ps
CPU time 0.85 seconds
Started Mar 12 12:35:46 PM PDT 24
Finished Mar 12 12:35:49 PM PDT 24
Peak memory 206488 kb
Host smart-009ec753-4b83-4044-aab6-8ac9b73b28c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174626547 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_csr_rw.4174626547
Directory /workspace/1.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.edn_intr_test.3603259136
Short name T968
Test name
Test status
Simulation time 15330901 ps
CPU time 0.81 seconds
Started Mar 12 12:35:45 PM PDT 24
Finished Mar 12 12:35:46 PM PDT 24
Peak memory 206552 kb
Host smart-82a81f42-b8ed-4681-a376-f8849c0f5668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603259136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_intr_test.3603259136
Directory /workspace/1.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.edn_same_csr_outstanding.2467387320
Short name T223
Test name
Test status
Simulation time 41874440 ps
CPU time 1.12 seconds
Started Mar 12 12:35:45 PM PDT 24
Finished Mar 12 12:35:46 PM PDT 24
Peak memory 206656 kb
Host smart-30c9d48d-34d4-4854-8ac2-b39f363adc5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467387320 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_same_csr_ou
tstanding.2467387320
Directory /workspace/1.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_errors.827248891
Short name T850
Test name
Test status
Simulation time 40595791 ps
CPU time 2.57 seconds
Started Mar 12 12:35:43 PM PDT 24
Finished Mar 12 12:35:46 PM PDT 24
Peak memory 218096 kb
Host smart-b810963d-d372-4174-aa5b-ad65bf785c45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827248891 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_errors.827248891
Directory /workspace/1.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.edn_tl_intg_err.2654091732
Short name T241
Test name
Test status
Simulation time 77381342 ps
CPU time 2.2 seconds
Started Mar 12 12:35:46 PM PDT 24
Finished Mar 12 12:35:50 PM PDT 24
Peak memory 206588 kb
Host smart-f162953f-cfc3-4ae2-b24a-9e8a4e41f6fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654091732 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.edn_tl_intg_err.2654091732
Directory /workspace/1.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_mem_rw_with_rand_reset.2981135072
Short name T948
Test name
Test status
Simulation time 34021019 ps
CPU time 1.12 seconds
Started Mar 12 12:35:55 PM PDT 24
Finished Mar 12 12:35:57 PM PDT 24
Peak memory 214832 kb
Host smart-067f2ec1-bc09-4f19-8002-f1d21be61ccf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981135072 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.edn_csr_mem_rw_with_rand_reset.2981135072
Directory /workspace/10.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.edn_csr_rw.2289121419
Short name T226
Test name
Test status
Simulation time 28983824 ps
CPU time 0.94 seconds
Started Mar 12 12:36:09 PM PDT 24
Finished Mar 12 12:36:10 PM PDT 24
Peak memory 206500 kb
Host smart-49405be5-ad32-49ae-9d4f-43cb567e97ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289121419 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_csr_rw.2289121419
Directory /workspace/10.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.edn_intr_test.3220910564
Short name T923
Test name
Test status
Simulation time 35569645 ps
CPU time 0.8 seconds
Started Mar 12 12:36:00 PM PDT 24
Finished Mar 12 12:36:01 PM PDT 24
Peak memory 206468 kb
Host smart-7e0b32c3-a8d1-48ca-a824-c8cec9247613
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220910564 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_intr_test.3220910564
Directory /workspace/10.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.edn_same_csr_outstanding.2405180910
Short name T966
Test name
Test status
Simulation time 26097636 ps
CPU time 1.14 seconds
Started Mar 12 12:35:55 PM PDT 24
Finished Mar 12 12:35:56 PM PDT 24
Peak memory 206480 kb
Host smart-418a9d75-181a-4c7b-9e4a-7b65afa04ad2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405180910 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_same_csr_o
utstanding.2405180910
Directory /workspace/10.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_errors.2638785431
Short name T961
Test name
Test status
Simulation time 471542484 ps
CPU time 3.17 seconds
Started Mar 12 12:35:57 PM PDT 24
Finished Mar 12 12:36:01 PM PDT 24
Peak memory 214772 kb
Host smart-318827b6-8a26-4f2a-af9b-ac1909cc7a5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638785431 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_errors.2638785431
Directory /workspace/10.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.edn_tl_intg_err.3972549261
Short name T934
Test name
Test status
Simulation time 112120276 ps
CPU time 2.73 seconds
Started Mar 12 12:35:56 PM PDT 24
Finished Mar 12 12:35:59 PM PDT 24
Peak memory 206560 kb
Host smart-4b259ae4-b3b5-4c94-95b0-abf11d006fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972549261 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.edn_tl_intg_err.3972549261
Directory /workspace/10.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_mem_rw_with_rand_reset.3653056617
Short name T890
Test name
Test status
Simulation time 53660550 ps
CPU time 1.22 seconds
Started Mar 12 12:36:08 PM PDT 24
Finished Mar 12 12:36:10 PM PDT 24
Peak memory 216352 kb
Host smart-0dc7ea16-c3a0-48d8-b402-226f46eb593d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653056617 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.edn_csr_mem_rw_with_rand_reset.3653056617
Directory /workspace/11.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.edn_csr_rw.2846054192
Short name T218
Test name
Test status
Simulation time 14467618 ps
CPU time 0.89 seconds
Started Mar 12 12:35:58 PM PDT 24
Finished Mar 12 12:36:00 PM PDT 24
Peak memory 206552 kb
Host smart-089859cb-27c3-45c8-9b65-51928112b91d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846054192 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_csr_rw.2846054192
Directory /workspace/11.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.edn_intr_test.2229785026
Short name T846
Test name
Test status
Simulation time 14156742 ps
CPU time 0.85 seconds
Started Mar 12 12:35:58 PM PDT 24
Finished Mar 12 12:36:00 PM PDT 24
Peak memory 206456 kb
Host smart-962a2925-d54c-499b-9439-3bcb0a6dbf66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229785026 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_intr_test.2229785026
Directory /workspace/11.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.edn_same_csr_outstanding.744924946
Short name T906
Test name
Test status
Simulation time 133355786 ps
CPU time 1.36 seconds
Started Mar 12 12:35:55 PM PDT 24
Finished Mar 12 12:35:56 PM PDT 24
Peak memory 206500 kb
Host smart-1cd106c3-083a-4202-af54-39cffe76c8ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744924946 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_same_csr_ou
tstanding.744924946
Directory /workspace/11.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_errors.1255013622
Short name T938
Test name
Test status
Simulation time 64705500 ps
CPU time 2.6 seconds
Started Mar 12 12:35:52 PM PDT 24
Finished Mar 12 12:35:55 PM PDT 24
Peak memory 214872 kb
Host smart-2d672262-8c9a-4a44-87f2-9b9103595325
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255013622 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_errors.1255013622
Directory /workspace/11.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.edn_tl_intg_err.1659093101
Short name T927
Test name
Test status
Simulation time 79245884 ps
CPU time 1.57 seconds
Started Mar 12 12:35:55 PM PDT 24
Finished Mar 12 12:35:57 PM PDT 24
Peak memory 206540 kb
Host smart-60ee2f74-fc55-4aa3-a50c-94e7bd11608f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659093101 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.edn_tl_intg_err.1659093101
Directory /workspace/11.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_mem_rw_with_rand_reset.3593565616
Short name T840
Test name
Test status
Simulation time 33662883 ps
CPU time 1.14 seconds
Started Mar 12 12:36:04 PM PDT 24
Finished Mar 12 12:36:05 PM PDT 24
Peak memory 214844 kb
Host smart-94f84a05-d958-4cf2-b51b-e4cb3083f467
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593565616 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.edn_csr_mem_rw_with_rand_reset.3593565616
Directory /workspace/12.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.edn_csr_rw.3877066615
Short name T227
Test name
Test status
Simulation time 52067620 ps
CPU time 0.92 seconds
Started Mar 12 12:36:10 PM PDT 24
Finished Mar 12 12:36:11 PM PDT 24
Peak memory 206548 kb
Host smart-92ed1aed-7140-4f33-a7be-f8c21088a49a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877066615 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_csr_rw.3877066615
Directory /workspace/12.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.edn_intr_test.1544163837
Short name T838
Test name
Test status
Simulation time 57958089 ps
CPU time 0.79 seconds
Started Mar 12 12:36:06 PM PDT 24
Finished Mar 12 12:36:07 PM PDT 24
Peak memory 206432 kb
Host smart-dc06f6e5-120e-48c0-a2c6-6aa9ab11b256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544163837 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_intr_test.1544163837
Directory /workspace/12.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.edn_same_csr_outstanding.1648977641
Short name T225
Test name
Test status
Simulation time 118847927 ps
CPU time 1.43 seconds
Started Mar 12 12:36:04 PM PDT 24
Finished Mar 12 12:36:05 PM PDT 24
Peak memory 206688 kb
Host smart-3b1ef131-8c07-4864-8f7d-70d05f509f37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648977641 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_same_csr_o
utstanding.1648977641
Directory /workspace/12.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_errors.4086724374
Short name T903
Test name
Test status
Simulation time 132171202 ps
CPU time 2.49 seconds
Started Mar 12 12:36:08 PM PDT 24
Finished Mar 12 12:36:11 PM PDT 24
Peak memory 214784 kb
Host smart-03a13ecb-3a80-43ee-a6ca-f93e6f5d1ac9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086724374 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_errors.4086724374
Directory /workspace/12.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.edn_tl_intg_err.3783211532
Short name T884
Test name
Test status
Simulation time 89500789 ps
CPU time 1.56 seconds
Started Mar 12 12:35:53 PM PDT 24
Finished Mar 12 12:35:55 PM PDT 24
Peak memory 206620 kb
Host smart-e82997ef-6454-43d8-acd0-680865059ddd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783211532 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.edn_tl_intg_err.3783211532
Directory /workspace/12.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_mem_rw_with_rand_reset.2021321245
Short name T882
Test name
Test status
Simulation time 91845082 ps
CPU time 1.24 seconds
Started Mar 12 12:36:06 PM PDT 24
Finished Mar 12 12:36:07 PM PDT 24
Peak memory 214848 kb
Host smart-33517769-c485-483e-8242-fe7705d01925
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021321245 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.edn_csr_mem_rw_with_rand_reset.2021321245
Directory /workspace/13.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.edn_csr_rw.947922817
Short name T216
Test name
Test status
Simulation time 29632555 ps
CPU time 0.93 seconds
Started Mar 12 12:36:05 PM PDT 24
Finished Mar 12 12:36:06 PM PDT 24
Peak memory 206544 kb
Host smart-2207f9a0-79a7-406d-8690-9f06045b3747
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947922817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_csr_rw.947922817
Directory /workspace/13.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.edn_intr_test.4271510702
Short name T910
Test name
Test status
Simulation time 19427510 ps
CPU time 0.91 seconds
Started Mar 12 12:36:05 PM PDT 24
Finished Mar 12 12:36:06 PM PDT 24
Peak memory 206468 kb
Host smart-1cc48704-be27-47b4-88a0-7131449f4b54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271510702 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_intr_test.4271510702
Directory /workspace/13.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.edn_same_csr_outstanding.3496799264
Short name T930
Test name
Test status
Simulation time 20524154 ps
CPU time 1.1 seconds
Started Mar 12 12:36:04 PM PDT 24
Finished Mar 12 12:36:05 PM PDT 24
Peak memory 206480 kb
Host smart-191f3943-c6ea-4d50-8228-b3cf22fc714f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496799264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_same_csr_o
utstanding.3496799264
Directory /workspace/13.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_errors.3574250815
Short name T942
Test name
Test status
Simulation time 227131479 ps
CPU time 3.99 seconds
Started Mar 12 12:36:09 PM PDT 24
Finished Mar 12 12:36:13 PM PDT 24
Peak memory 214892 kb
Host smart-15736d05-58c4-4b48-abac-77723fdb1e05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574250815 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_errors.3574250815
Directory /workspace/13.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.edn_tl_intg_err.1828920607
Short name T919
Test name
Test status
Simulation time 68257293 ps
CPU time 1.76 seconds
Started Mar 12 12:36:06 PM PDT 24
Finished Mar 12 12:36:08 PM PDT 24
Peak memory 206632 kb
Host smart-f4cfe69d-2d61-40c9-8e06-0b45884e1a5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828920607 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.edn_tl_intg_err.1828920607
Directory /workspace/13.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_mem_rw_with_rand_reset.3249675385
Short name T885
Test name
Test status
Simulation time 88420717 ps
CPU time 1.16 seconds
Started Mar 12 12:36:03 PM PDT 24
Finished Mar 12 12:36:04 PM PDT 24
Peak memory 214876 kb
Host smart-29352504-b793-4c6d-ad81-cae52b2da595
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249675385 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.edn_csr_mem_rw_with_rand_reset.3249675385
Directory /workspace/14.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.edn_csr_rw.716801308
Short name T209
Test name
Test status
Simulation time 16412282 ps
CPU time 0.93 seconds
Started Mar 12 12:36:03 PM PDT 24
Finished Mar 12 12:36:04 PM PDT 24
Peak memory 206476 kb
Host smart-54451d6d-2c17-47f9-8b2f-d5f750d4530f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716801308 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_csr_rw.716801308
Directory /workspace/14.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.edn_intr_test.3114521545
Short name T859
Test name
Test status
Simulation time 14343280 ps
CPU time 0.86 seconds
Started Mar 12 12:36:07 PM PDT 24
Finished Mar 12 12:36:08 PM PDT 24
Peak memory 206504 kb
Host smart-385602fd-c749-416b-8f27-7d43c205efc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114521545 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_intr_test.3114521545
Directory /workspace/14.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.edn_same_csr_outstanding.4206974728
Short name T904
Test name
Test status
Simulation time 45345957 ps
CPU time 1.33 seconds
Started Mar 12 12:36:04 PM PDT 24
Finished Mar 12 12:36:06 PM PDT 24
Peak memory 206540 kb
Host smart-45606a84-4004-4ebf-be48-0cf9783b118f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206974728 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_same_csr_o
utstanding.4206974728
Directory /workspace/14.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_errors.56857158
Short name T918
Test name
Test status
Simulation time 704590657 ps
CPU time 5.09 seconds
Started Mar 12 12:36:05 PM PDT 24
Finished Mar 12 12:36:11 PM PDT 24
Peak memory 214860 kb
Host smart-f579a158-73b9-47d1-bb36-34b49ad35565
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56857158 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_errors.56857158
Directory /workspace/14.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.edn_tl_intg_err.1416050902
Short name T868
Test name
Test status
Simulation time 179926836 ps
CPU time 1.54 seconds
Started Mar 12 12:36:03 PM PDT 24
Finished Mar 12 12:36:05 PM PDT 24
Peak memory 206612 kb
Host smart-a09e06cb-41b3-47ab-a36a-1e4a132eabb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416050902 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.edn_tl_intg_err.1416050902
Directory /workspace/14.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_mem_rw_with_rand_reset.1387686858
Short name T865
Test name
Test status
Simulation time 35613999 ps
CPU time 1.43 seconds
Started Mar 12 12:36:05 PM PDT 24
Finished Mar 12 12:36:07 PM PDT 24
Peak memory 214728 kb
Host smart-6eda4258-3aa0-4b0e-bb6f-c8b892f7b08c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387686858 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.edn_csr_mem_rw_with_rand_reset.1387686858
Directory /workspace/15.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.edn_csr_rw.2492475851
Short name T907
Test name
Test status
Simulation time 34821927 ps
CPU time 0.81 seconds
Started Mar 12 12:36:07 PM PDT 24
Finished Mar 12 12:36:08 PM PDT 24
Peak memory 206440 kb
Host smart-0ada8f5d-1ecf-4b08-9480-f9b336223ca3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492475851 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_csr_rw.2492475851
Directory /workspace/15.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.edn_intr_test.3343403661
Short name T956
Test name
Test status
Simulation time 61230589 ps
CPU time 0.83 seconds
Started Mar 12 12:36:03 PM PDT 24
Finished Mar 12 12:36:04 PM PDT 24
Peak memory 206440 kb
Host smart-b80c9326-3681-4992-aab3-a97932b2ccf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343403661 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_intr_test.3343403661
Directory /workspace/15.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.edn_same_csr_outstanding.818321235
Short name T925
Test name
Test status
Simulation time 14577105 ps
CPU time 0.97 seconds
Started Mar 12 12:36:07 PM PDT 24
Finished Mar 12 12:36:08 PM PDT 24
Peak memory 206612 kb
Host smart-21511e3a-9613-424c-b80a-4984138ab9df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818321235 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_same_csr_ou
tstanding.818321235
Directory /workspace/15.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_errors.2354863439
Short name T853
Test name
Test status
Simulation time 165442642 ps
CPU time 1.82 seconds
Started Mar 12 12:36:05 PM PDT 24
Finished Mar 12 12:36:07 PM PDT 24
Peak memory 214872 kb
Host smart-15cf12ef-3f01-4d2c-bfbf-32cf6427e52a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354863439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_errors.2354863439
Directory /workspace/15.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.edn_tl_intg_err.1722916333
Short name T866
Test name
Test status
Simulation time 126961107 ps
CPU time 2.1 seconds
Started Mar 12 12:36:04 PM PDT 24
Finished Mar 12 12:36:06 PM PDT 24
Peak memory 206524 kb
Host smart-d5bd2c2e-7f76-4b64-b4d5-78454d633a0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722916333 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.edn_tl_intg_err.1722916333
Directory /workspace/15.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_mem_rw_with_rand_reset.2752752151
Short name T932
Test name
Test status
Simulation time 17446718 ps
CPU time 0.98 seconds
Started Mar 12 12:36:04 PM PDT 24
Finished Mar 12 12:36:05 PM PDT 24
Peak memory 206644 kb
Host smart-87fba2ac-0794-4768-b35f-cef3fc199b89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752752151 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.edn_csr_mem_rw_with_rand_reset.2752752151
Directory /workspace/16.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.edn_csr_rw.1973309360
Short name T880
Test name
Test status
Simulation time 61613822 ps
CPU time 0.91 seconds
Started Mar 12 12:36:06 PM PDT 24
Finished Mar 12 12:36:07 PM PDT 24
Peak memory 206588 kb
Host smart-09706bda-a3e9-4fa7-ae02-9938504c1f2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973309360 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_csr_rw.1973309360
Directory /workspace/16.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.edn_intr_test.3634723866
Short name T964
Test name
Test status
Simulation time 14986657 ps
CPU time 0.87 seconds
Started Mar 12 12:36:08 PM PDT 24
Finished Mar 12 12:36:10 PM PDT 24
Peak memory 206516 kb
Host smart-befb16f1-4ecd-47a6-99eb-abe3d8646e41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634723866 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_intr_test.3634723866
Directory /workspace/16.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.edn_same_csr_outstanding.2988393263
Short name T214
Test name
Test status
Simulation time 19561935 ps
CPU time 0.86 seconds
Started Mar 12 12:36:09 PM PDT 24
Finished Mar 12 12:36:10 PM PDT 24
Peak memory 206540 kb
Host smart-c5073b3b-993a-4443-aaeb-5d9ad8ebdaaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988393263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_same_csr_o
utstanding.2988393263
Directory /workspace/16.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_errors.4288168817
Short name T887
Test name
Test status
Simulation time 186541378 ps
CPU time 2.45 seconds
Started Mar 12 12:36:07 PM PDT 24
Finished Mar 12 12:36:10 PM PDT 24
Peak memory 214764 kb
Host smart-a1dc9878-719b-466d-a450-75193b2662de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288168817 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_errors.4288168817
Directory /workspace/16.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.edn_tl_intg_err.2603158688
Short name T243
Test name
Test status
Simulation time 52837076 ps
CPU time 1.63 seconds
Started Mar 12 12:36:03 PM PDT 24
Finished Mar 12 12:36:05 PM PDT 24
Peak memory 206616 kb
Host smart-a9abe454-081f-470d-a04a-6c143137bbe4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603158688 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.edn_tl_intg_err.2603158688
Directory /workspace/16.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_mem_rw_with_rand_reset.1228226918
Short name T878
Test name
Test status
Simulation time 98934736 ps
CPU time 1.95 seconds
Started Mar 12 12:36:05 PM PDT 24
Finished Mar 12 12:36:07 PM PDT 24
Peak memory 214760 kb
Host smart-0af44543-3a24-40a4-bda1-ce0dbd65da3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228226918 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.edn_csr_mem_rw_with_rand_reset.1228226918
Directory /workspace/17.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.edn_csr_rw.1861511509
Short name T908
Test name
Test status
Simulation time 18324273 ps
CPU time 0.82 seconds
Started Mar 12 12:36:05 PM PDT 24
Finished Mar 12 12:36:06 PM PDT 24
Peak memory 206520 kb
Host smart-2e5eabe9-b070-4e1f-886d-66b7355140b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861511509 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_csr_rw.1861511509
Directory /workspace/17.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.edn_intr_test.878457463
Short name T929
Test name
Test status
Simulation time 15469998 ps
CPU time 0.82 seconds
Started Mar 12 12:36:09 PM PDT 24
Finished Mar 12 12:36:10 PM PDT 24
Peak memory 206632 kb
Host smart-f550291a-6533-409b-b887-d1615a04a733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878457463 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_intr_test.878457463
Directory /workspace/17.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.edn_same_csr_outstanding.3214822776
Short name T224
Test name
Test status
Simulation time 75744968 ps
CPU time 1.43 seconds
Started Mar 12 12:36:06 PM PDT 24
Finished Mar 12 12:36:07 PM PDT 24
Peak memory 206544 kb
Host smart-af4a8297-9224-43e5-b111-3398f94eef82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214822776 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_same_csr_o
utstanding.3214822776
Directory /workspace/17.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_errors.3739942260
Short name T845
Test name
Test status
Simulation time 475911286 ps
CPU time 2.5 seconds
Started Mar 12 12:36:05 PM PDT 24
Finished Mar 12 12:36:07 PM PDT 24
Peak memory 214820 kb
Host smart-7b2f4329-82df-4a7f-b6fb-d586c051f5a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739942260 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_errors.3739942260
Directory /workspace/17.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.edn_tl_intg_err.2942105652
Short name T876
Test name
Test status
Simulation time 87938525 ps
CPU time 1.55 seconds
Started Mar 12 12:36:04 PM PDT 24
Finished Mar 12 12:36:05 PM PDT 24
Peak memory 206592 kb
Host smart-ccbbd17c-b7c8-4778-bd8b-4960256440e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942105652 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.edn_tl_intg_err.2942105652
Directory /workspace/17.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.edn_csr_mem_rw_with_rand_reset.124753096
Short name T912
Test name
Test status
Simulation time 43223891 ps
CPU time 1.11 seconds
Started Mar 12 12:36:05 PM PDT 24
Finished Mar 12 12:36:06 PM PDT 24
Peak memory 214944 kb
Host smart-57d4c755-4706-46d1-a9a1-290ffd1c1dea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124753096 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.edn_csr_mem_rw_with_rand_reset.124753096
Directory /workspace/18.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.edn_intr_test.2435808312
Short name T920
Test name
Test status
Simulation time 31323171 ps
CPU time 0.79 seconds
Started Mar 12 12:36:07 PM PDT 24
Finished Mar 12 12:36:07 PM PDT 24
Peak memory 206400 kb
Host smart-28ebd21c-cbfe-4ab5-9bf4-a62a956d20ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435808312 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_intr_test.2435808312
Directory /workspace/18.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.edn_same_csr_outstanding.2305890245
Short name T937
Test name
Test status
Simulation time 35161296 ps
CPU time 1.41 seconds
Started Mar 12 12:36:03 PM PDT 24
Finished Mar 12 12:36:05 PM PDT 24
Peak memory 206608 kb
Host smart-46194a7f-4063-4686-a65d-d2384a2ae425
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305890245 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_same_csr_o
utstanding.2305890245
Directory /workspace/18.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_errors.3924444002
Short name T854
Test name
Test status
Simulation time 55879030 ps
CPU time 2.03 seconds
Started Mar 12 12:36:07 PM PDT 24
Finished Mar 12 12:36:09 PM PDT 24
Peak memory 214804 kb
Host smart-a227f3ed-c429-4704-8cbd-fa4df6acf590
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924444002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_errors.3924444002
Directory /workspace/18.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.edn_tl_intg_err.3295340491
Short name T230
Test name
Test status
Simulation time 275111553 ps
CPU time 2.19 seconds
Started Mar 12 12:36:09 PM PDT 24
Finished Mar 12 12:36:12 PM PDT 24
Peak memory 206620 kb
Host smart-bc0cd103-b06f-4b4a-ac03-e12751a5d26f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295340491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.edn_tl_intg_err.3295340491
Directory /workspace/18.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_mem_rw_with_rand_reset.2169249743
Short name T900
Test name
Test status
Simulation time 67957280 ps
CPU time 1.38 seconds
Started Mar 12 12:36:04 PM PDT 24
Finished Mar 12 12:36:06 PM PDT 24
Peak memory 214728 kb
Host smart-b6095956-a2a4-4dc1-ab77-62390746b325
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169249743 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.edn_csr_mem_rw_with_rand_reset.2169249743
Directory /workspace/19.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.edn_csr_rw.361678589
Short name T899
Test name
Test status
Simulation time 97111329 ps
CPU time 0.92 seconds
Started Mar 12 12:36:08 PM PDT 24
Finished Mar 12 12:36:09 PM PDT 24
Peak memory 206612 kb
Host smart-e1c064f9-1720-4ded-9022-77149f45c712
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361678589 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_csr_rw.361678589
Directory /workspace/19.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.edn_intr_test.4033016186
Short name T917
Test name
Test status
Simulation time 35624497 ps
CPU time 0.83 seconds
Started Mar 12 12:36:07 PM PDT 24
Finished Mar 12 12:36:07 PM PDT 24
Peak memory 206632 kb
Host smart-37f1accc-51bc-4b36-a953-b44e76162853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033016186 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_intr_test.4033016186
Directory /workspace/19.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.edn_same_csr_outstanding.290249215
Short name T893
Test name
Test status
Simulation time 59620743 ps
CPU time 1.02 seconds
Started Mar 12 12:36:07 PM PDT 24
Finished Mar 12 12:36:08 PM PDT 24
Peak memory 206608 kb
Host smart-de2a24a3-007c-44de-a946-87d07b4ef4be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290249215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_same_csr_ou
tstanding.290249215
Directory /workspace/19.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_errors.1907065256
Short name T921
Test name
Test status
Simulation time 165037378 ps
CPU time 2.64 seconds
Started Mar 12 12:36:07 PM PDT 24
Finished Mar 12 12:36:09 PM PDT 24
Peak memory 214844 kb
Host smart-20f20010-ef7c-4473-bdcc-28460da5b42c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907065256 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_errors.1907065256
Directory /workspace/19.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.edn_tl_intg_err.433868120
Short name T231
Test name
Test status
Simulation time 57773055 ps
CPU time 1.7 seconds
Started Mar 12 12:36:08 PM PDT 24
Finished Mar 12 12:36:09 PM PDT 24
Peak memory 206516 kb
Host smart-0f1f46fb-aaab-4594-9687-82368a830a31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433868120 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.edn_tl_intg_err.433868120
Directory /workspace/19.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_aliasing.1097370953
Short name T873
Test name
Test status
Simulation time 37599152 ps
CPU time 1.48 seconds
Started Mar 12 12:35:47 PM PDT 24
Finished Mar 12 12:35:49 PM PDT 24
Peak memory 206504 kb
Host smart-dec74964-715a-4b84-b88a-5790dc1b826c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097370953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_aliasing.1097370953
Directory /workspace/2.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_bit_bash.216945812
Short name T901
Test name
Test status
Simulation time 196296328 ps
CPU time 2.01 seconds
Started Mar 12 12:35:46 PM PDT 24
Finished Mar 12 12:35:50 PM PDT 24
Peak memory 206604 kb
Host smart-676b3cb1-1c2f-47f1-bb13-a399df2b4652
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216945812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_bit_bash.216945812
Directory /workspace/2.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_hw_reset.811323892
Short name T945
Test name
Test status
Simulation time 23990035 ps
CPU time 0.77 seconds
Started Mar 12 12:35:55 PM PDT 24
Finished Mar 12 12:35:56 PM PDT 24
Peak memory 206384 kb
Host smart-29c0c9c0-780c-434f-9e82-260222f938cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811323892 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_hw_reset.811323892
Directory /workspace/2.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_mem_rw_with_rand_reset.2488658672
Short name T841
Test name
Test status
Simulation time 17751796 ps
CPU time 1.12 seconds
Started Mar 12 12:35:47 PM PDT 24
Finished Mar 12 12:35:49 PM PDT 24
Peak memory 214788 kb
Host smart-7ad83cbb-78f2-4d74-865d-8241b18838fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488658672 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.edn_csr_mem_rw_with_rand_reset.2488658672
Directory /workspace/2.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.edn_csr_rw.1233931445
Short name T217
Test name
Test status
Simulation time 13566130 ps
CPU time 0.88 seconds
Started Mar 12 12:35:52 PM PDT 24
Finished Mar 12 12:35:53 PM PDT 24
Peak memory 206612 kb
Host smart-a7564be0-47a5-4315-8ca4-50386550bc35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233931445 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_csr_rw.1233931445
Directory /workspace/2.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.edn_intr_test.3297915473
Short name T849
Test name
Test status
Simulation time 24862715 ps
CPU time 0.86 seconds
Started Mar 12 12:35:49 PM PDT 24
Finished Mar 12 12:35:50 PM PDT 24
Peak memory 206552 kb
Host smart-474c34ca-d6df-40e3-b347-a9db8bd94ca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297915473 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_intr_test.3297915473
Directory /workspace/2.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.edn_same_csr_outstanding.1495216683
Short name T959
Test name
Test status
Simulation time 34871184 ps
CPU time 1.43 seconds
Started Mar 12 12:35:46 PM PDT 24
Finished Mar 12 12:35:49 PM PDT 24
Peak memory 206568 kb
Host smart-95922f0e-6fff-4d5e-8bb6-c9050f8adf0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495216683 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_same_csr_ou
tstanding.1495216683
Directory /workspace/2.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_errors.321497218
Short name T871
Test name
Test status
Simulation time 34905472 ps
CPU time 2.2 seconds
Started Mar 12 12:35:44 PM PDT 24
Finished Mar 12 12:35:47 PM PDT 24
Peak memory 217884 kb
Host smart-0744a713-cacd-4c59-ad8e-5e0e34619e1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321497218 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_errors.321497218
Directory /workspace/2.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.edn_tl_intg_err.3944312640
Short name T242
Test name
Test status
Simulation time 248539837 ps
CPU time 2 seconds
Started Mar 12 12:35:47 PM PDT 24
Finished Mar 12 12:35:50 PM PDT 24
Peak memory 206512 kb
Host smart-85800a3f-2064-4b66-841d-1bd04ab9ad9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944312640 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.edn_tl_intg_err.3944312640
Directory /workspace/2.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.edn_intr_test.798466198
Short name T879
Test name
Test status
Simulation time 15160815 ps
CPU time 0.89 seconds
Started Mar 12 12:36:05 PM PDT 24
Finished Mar 12 12:36:06 PM PDT 24
Peak memory 206620 kb
Host smart-60bca768-b7b2-40ff-b71c-290b4b288906
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798466198 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.edn_intr_test.798466198
Directory /workspace/20.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.edn_intr_test.2198208280
Short name T924
Test name
Test status
Simulation time 17754055 ps
CPU time 0.83 seconds
Started Mar 12 12:36:06 PM PDT 24
Finished Mar 12 12:36:07 PM PDT 24
Peak memory 206444 kb
Host smart-60c990b2-cf3c-49e9-b835-4cb523d6094e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198208280 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.edn_intr_test.2198208280
Directory /workspace/21.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.edn_intr_test.51529263
Short name T895
Test name
Test status
Simulation time 43399772 ps
CPU time 0.88 seconds
Started Mar 12 12:36:08 PM PDT 24
Finished Mar 12 12:36:10 PM PDT 24
Peak memory 206520 kb
Host smart-8eb5aa7c-e98b-4f2f-b89e-935aab3b024d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51529263 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.edn_intr_test.51529263
Directory /workspace/22.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.edn_intr_test.3188192533
Short name T843
Test name
Test status
Simulation time 44105123 ps
CPU time 0.79 seconds
Started Mar 12 12:36:12 PM PDT 24
Finished Mar 12 12:36:14 PM PDT 24
Peak memory 206392 kb
Host smart-178c243e-458e-4bb5-a662-1c7d0119804b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188192533 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.edn_intr_test.3188192533
Directory /workspace/23.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.edn_intr_test.1595662975
Short name T928
Test name
Test status
Simulation time 16079213 ps
CPU time 0.77 seconds
Started Mar 12 12:36:05 PM PDT 24
Finished Mar 12 12:36:06 PM PDT 24
Peak memory 206420 kb
Host smart-aa3c6138-8bd9-4785-89c3-347a002f3fe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595662975 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.edn_intr_test.1595662975
Directory /workspace/24.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.edn_intr_test.4267442876
Short name T858
Test name
Test status
Simulation time 34129920 ps
CPU time 0.87 seconds
Started Mar 12 12:36:04 PM PDT 24
Finished Mar 12 12:36:05 PM PDT 24
Peak memory 206496 kb
Host smart-f86517e4-3b27-40b2-94ea-3e6776257cbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267442876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.edn_intr_test.4267442876
Directory /workspace/25.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.edn_intr_test.145726742
Short name T864
Test name
Test status
Simulation time 56272848 ps
CPU time 0.83 seconds
Started Mar 12 12:36:12 PM PDT 24
Finished Mar 12 12:36:14 PM PDT 24
Peak memory 206448 kb
Host smart-44f3da8a-b452-4e4c-96eb-c7ff99b2e9d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145726742 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.edn_intr_test.145726742
Directory /workspace/26.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.edn_intr_test.2190341002
Short name T889
Test name
Test status
Simulation time 70900593 ps
CPU time 0.82 seconds
Started Mar 12 12:36:10 PM PDT 24
Finished Mar 12 12:36:11 PM PDT 24
Peak memory 206644 kb
Host smart-973e7a39-425b-4e10-a7db-08a051f2ac5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190341002 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.edn_intr_test.2190341002
Directory /workspace/27.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.edn_intr_test.2605453563
Short name T867
Test name
Test status
Simulation time 25803498 ps
CPU time 0.85 seconds
Started Mar 12 12:36:12 PM PDT 24
Finished Mar 12 12:36:14 PM PDT 24
Peak memory 206348 kb
Host smart-3920af63-5d82-4cca-8714-21fb379ac437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605453563 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.edn_intr_test.2605453563
Directory /workspace/28.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.edn_intr_test.3901987005
Short name T847
Test name
Test status
Simulation time 39139102 ps
CPU time 0.78 seconds
Started Mar 12 12:36:12 PM PDT 24
Finished Mar 12 12:36:14 PM PDT 24
Peak memory 206212 kb
Host smart-b2fd7387-56fa-482a-85fd-263475d71443
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901987005 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.edn_intr_test.3901987005
Directory /workspace/29.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_aliasing.565498782
Short name T936
Test name
Test status
Simulation time 39082200 ps
CPU time 1.13 seconds
Started Mar 12 12:35:47 PM PDT 24
Finished Mar 12 12:35:49 PM PDT 24
Peak memory 206532 kb
Host smart-199428a8-5d08-4bc2-a3ac-7d48564aab93
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565498782 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_aliasing.565498782
Directory /workspace/3.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_bit_bash.2185753827
Short name T902
Test name
Test status
Simulation time 58302299 ps
CPU time 3.21 seconds
Started Mar 12 12:35:47 PM PDT 24
Finished Mar 12 12:35:51 PM PDT 24
Peak memory 206680 kb
Host smart-e80ff57b-76da-4efe-a8eb-486d32670289
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185753827 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_bit_bash.2185753827
Directory /workspace/3.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_hw_reset.3521299744
Short name T206
Test name
Test status
Simulation time 27197237 ps
CPU time 0.88 seconds
Started Mar 12 12:35:44 PM PDT 24
Finished Mar 12 12:35:45 PM PDT 24
Peak memory 206484 kb
Host smart-18d32818-5e9c-4cd4-b235-0960a5f1549b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521299744 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_hw_reset.3521299744
Directory /workspace/3.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_mem_rw_with_rand_reset.3478065267
Short name T872
Test name
Test status
Simulation time 126954091 ps
CPU time 1.53 seconds
Started Mar 12 12:35:46 PM PDT 24
Finished Mar 12 12:35:49 PM PDT 24
Peak memory 214880 kb
Host smart-cf3e8f3b-3210-4fbd-812b-682567257308
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478065267 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.edn_csr_mem_rw_with_rand_reset.3478065267
Directory /workspace/3.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.edn_csr_rw.1405857424
Short name T222
Test name
Test status
Simulation time 10733190 ps
CPU time 0.85 seconds
Started Mar 12 12:35:45 PM PDT 24
Finished Mar 12 12:35:46 PM PDT 24
Peak memory 206568 kb
Host smart-bd75a8b8-6376-4c03-bf03-f12f358d4e04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405857424 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_csr_rw.1405857424
Directory /workspace/3.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.edn_intr_test.2848474953
Short name T851
Test name
Test status
Simulation time 16110172 ps
CPU time 0.91 seconds
Started Mar 12 12:35:49 PM PDT 24
Finished Mar 12 12:35:50 PM PDT 24
Peak memory 206600 kb
Host smart-f267a6ef-71d6-47ed-a1e6-571d31dc23ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848474953 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_intr_test.2848474953
Directory /workspace/3.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.edn_same_csr_outstanding.1408683125
Short name T951
Test name
Test status
Simulation time 26646467 ps
CPU time 1.08 seconds
Started Mar 12 12:35:45 PM PDT 24
Finished Mar 12 12:35:46 PM PDT 24
Peak memory 206636 kb
Host smart-e2794cfe-72b5-4ffb-8388-c0e2761ba1c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408683125 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_same_csr_ou
tstanding.1408683125
Directory /workspace/3.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_errors.2038786164
Short name T922
Test name
Test status
Simulation time 75464183 ps
CPU time 1.81 seconds
Started Mar 12 12:35:46 PM PDT 24
Finished Mar 12 12:35:50 PM PDT 24
Peak memory 214896 kb
Host smart-2b36c222-247f-453d-b1b6-32c722682e09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038786164 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_errors.2038786164
Directory /workspace/3.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.edn_tl_intg_err.298840264
Short name T916
Test name
Test status
Simulation time 443420642 ps
CPU time 2.56 seconds
Started Mar 12 12:35:51 PM PDT 24
Finished Mar 12 12:35:54 PM PDT 24
Peak memory 206464 kb
Host smart-c98e4786-db45-4b98-9659-e2b6bf9a4b41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298840264 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.edn_tl_intg_err.298840264
Directory /workspace/3.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.edn_intr_test.194821179
Short name T935
Test name
Test status
Simulation time 14502651 ps
CPU time 0.89 seconds
Started Mar 12 12:36:06 PM PDT 24
Finished Mar 12 12:36:07 PM PDT 24
Peak memory 206540 kb
Host smart-1a851531-1cd4-43db-81a8-f44653efc09d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194821179 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.edn_intr_test.194821179
Directory /workspace/30.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.edn_intr_test.3626941938
Short name T962
Test name
Test status
Simulation time 14567936 ps
CPU time 0.85 seconds
Started Mar 12 12:36:05 PM PDT 24
Finished Mar 12 12:36:06 PM PDT 24
Peak memory 206584 kb
Host smart-167d4b65-f38c-4ce0-b54d-7990cf2786aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626941938 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.edn_intr_test.3626941938
Directory /workspace/31.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.edn_intr_test.3226308673
Short name T870
Test name
Test status
Simulation time 12658173 ps
CPU time 0.84 seconds
Started Mar 12 12:36:05 PM PDT 24
Finished Mar 12 12:36:06 PM PDT 24
Peak memory 206468 kb
Host smart-e55de426-efb2-478b-ad54-711c58af3afc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226308673 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.edn_intr_test.3226308673
Directory /workspace/32.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.edn_intr_test.2829398173
Short name T954
Test name
Test status
Simulation time 13125953 ps
CPU time 0.87 seconds
Started Mar 12 12:36:07 PM PDT 24
Finished Mar 12 12:36:08 PM PDT 24
Peak memory 206588 kb
Host smart-d19461d4-c326-4bcf-8a1e-94026bf790ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829398173 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.edn_intr_test.2829398173
Directory /workspace/33.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.edn_intr_test.2776348284
Short name T857
Test name
Test status
Simulation time 25905059 ps
CPU time 0.86 seconds
Started Mar 12 12:36:08 PM PDT 24
Finished Mar 12 12:36:10 PM PDT 24
Peak memory 206520 kb
Host smart-94a3f7b3-c689-418a-af40-77eeef47aff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776348284 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.edn_intr_test.2776348284
Directory /workspace/34.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.edn_intr_test.3651252907
Short name T888
Test name
Test status
Simulation time 56518014 ps
CPU time 0.78 seconds
Started Mar 12 12:36:05 PM PDT 24
Finished Mar 12 12:36:06 PM PDT 24
Peak memory 206304 kb
Host smart-14718636-f091-464d-851e-3851e5c71c50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651252907 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.edn_intr_test.3651252907
Directory /workspace/35.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.edn_intr_test.1823784550
Short name T883
Test name
Test status
Simulation time 16258997 ps
CPU time 0.78 seconds
Started Mar 12 12:36:07 PM PDT 24
Finished Mar 12 12:36:07 PM PDT 24
Peak memory 206412 kb
Host smart-58d47a4a-f79a-4d8e-b800-13b19cc3d353
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823784550 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.edn_intr_test.1823784550
Directory /workspace/36.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.edn_intr_test.2743590322
Short name T848
Test name
Test status
Simulation time 27406404 ps
CPU time 0.88 seconds
Started Mar 12 12:36:17 PM PDT 24
Finished Mar 12 12:36:18 PM PDT 24
Peak memory 206588 kb
Host smart-b0447d3c-d24c-481b-af4a-dc1b1997ede2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743590322 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.edn_intr_test.2743590322
Directory /workspace/37.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.edn_intr_test.377127121
Short name T844
Test name
Test status
Simulation time 17554076 ps
CPU time 0.9 seconds
Started Mar 12 12:37:52 PM PDT 24
Finished Mar 12 12:37:54 PM PDT 24
Peak memory 205336 kb
Host smart-9206b6e5-5522-41da-ad66-769b469d3f24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377127121 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.edn_intr_test.377127121
Directory /workspace/38.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.edn_intr_test.3929805978
Short name T943
Test name
Test status
Simulation time 17619937 ps
CPU time 0.97 seconds
Started Mar 12 12:36:16 PM PDT 24
Finished Mar 12 12:36:18 PM PDT 24
Peak memory 206556 kb
Host smart-34f90550-5a57-425f-83ce-7d9cc985b56e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929805978 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.edn_intr_test.3929805978
Directory /workspace/39.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_aliasing.2341914037
Short name T894
Test name
Test status
Simulation time 96969063 ps
CPU time 1.16 seconds
Started Mar 12 12:35:46 PM PDT 24
Finished Mar 12 12:35:49 PM PDT 24
Peak memory 206592 kb
Host smart-b42b887b-e006-4515-a567-a9c3e7b7dedc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341914037 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_aliasing.2341914037
Directory /workspace/4.edn_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_bit_bash.2012463574
Short name T955
Test name
Test status
Simulation time 343399936 ps
CPU time 4.79 seconds
Started Mar 12 12:35:52 PM PDT 24
Finished Mar 12 12:35:57 PM PDT 24
Peak memory 206688 kb
Host smart-4dc58da5-cbc5-4a58-8dd8-b737d4ea1c4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012463574 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_bit_bash.2012463574
Directory /workspace/4.edn_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_hw_reset.2153137722
Short name T211
Test name
Test status
Simulation time 13890749 ps
CPU time 0.91 seconds
Started Mar 12 12:35:50 PM PDT 24
Finished Mar 12 12:35:51 PM PDT 24
Peak memory 206500 kb
Host smart-df81e634-84e3-491e-ba6f-3f06047c23f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153137722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_hw_reset.2153137722
Directory /workspace/4.edn_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_mem_rw_with_rand_reset.618841204
Short name T933
Test name
Test status
Simulation time 22447195 ps
CPU time 1.38 seconds
Started Mar 12 12:35:53 PM PDT 24
Finished Mar 12 12:35:55 PM PDT 24
Peak memory 214972 kb
Host smart-35f937c3-4e05-49c2-87e9-6ea57bdb86f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618841204 -assert nopostproc +UVM_TESTNAME=
edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.edn_csr_mem_rw_with_rand_reset.618841204
Directory /workspace/4.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.edn_csr_rw.2785763868
Short name T891
Test name
Test status
Simulation time 12571035 ps
CPU time 0.91 seconds
Started Mar 12 12:35:45 PM PDT 24
Finished Mar 12 12:35:46 PM PDT 24
Peak memory 206596 kb
Host smart-851330b4-4ddc-4cb3-b2fd-394239925a33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785763868 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_csr_rw.2785763868
Directory /workspace/4.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.edn_intr_test.2924654072
Short name T886
Test name
Test status
Simulation time 10453526 ps
CPU time 0.81 seconds
Started Mar 12 12:35:49 PM PDT 24
Finished Mar 12 12:35:50 PM PDT 24
Peak memory 206320 kb
Host smart-128d45f2-7164-41bf-aafd-d85b4bc7d2e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924654072 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_intr_test.2924654072
Directory /workspace/4.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.edn_same_csr_outstanding.2125162723
Short name T911
Test name
Test status
Simulation time 42427859 ps
CPU time 1.38 seconds
Started Mar 12 12:35:51 PM PDT 24
Finished Mar 12 12:35:53 PM PDT 24
Peak memory 206552 kb
Host smart-c20367eb-23d8-4f62-aefa-7978d00f8e70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125162723 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_same_csr_ou
tstanding.2125162723
Directory /workspace/4.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.edn_tl_errors.2796554384
Short name T897
Test name
Test status
Simulation time 225431390 ps
CPU time 3.79 seconds
Started Mar 12 12:35:52 PM PDT 24
Finished Mar 12 12:35:56 PM PDT 24
Peak memory 218400 kb
Host smart-1e1f4d33-6d40-4c2f-b293-1d1ef0a45dc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796554384 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.edn_tl_errors.2796554384
Directory /workspace/4.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.edn_intr_test.707998920
Short name T913
Test name
Test status
Simulation time 13277347 ps
CPU time 0.83 seconds
Started Mar 12 12:36:16 PM PDT 24
Finished Mar 12 12:36:17 PM PDT 24
Peak memory 206544 kb
Host smart-e9224390-f9a9-41fe-bfaf-a16cf96e1190
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707998920 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.edn_intr_test.707998920
Directory /workspace/40.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.edn_intr_test.953867129
Short name T839
Test name
Test status
Simulation time 14293776 ps
CPU time 0.84 seconds
Started Mar 12 12:36:16 PM PDT 24
Finished Mar 12 12:36:17 PM PDT 24
Peak memory 206468 kb
Host smart-9f5c5626-1059-4b5c-9fb3-dd636551e260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953867129 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.edn_intr_test.953867129
Directory /workspace/41.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.edn_intr_test.1459564996
Short name T941
Test name
Test status
Simulation time 54199118 ps
CPU time 0.87 seconds
Started Mar 12 12:36:15 PM PDT 24
Finished Mar 12 12:36:17 PM PDT 24
Peak memory 206620 kb
Host smart-97ce54a5-d121-4d2d-86ab-c57ed910b1a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459564996 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.edn_intr_test.1459564996
Directory /workspace/42.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.edn_intr_test.2664615876
Short name T869
Test name
Test status
Simulation time 13413798 ps
CPU time 0.89 seconds
Started Mar 12 12:36:16 PM PDT 24
Finished Mar 12 12:36:17 PM PDT 24
Peak memory 206576 kb
Host smart-b2a5c52c-e05a-4a30-90bb-3e3bb98cd1d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664615876 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.edn_intr_test.2664615876
Directory /workspace/43.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.edn_intr_test.4145421875
Short name T909
Test name
Test status
Simulation time 72133689 ps
CPU time 0.79 seconds
Started Mar 12 12:36:14 PM PDT 24
Finished Mar 12 12:36:15 PM PDT 24
Peak memory 206432 kb
Host smart-7a38c095-1b4b-4ec7-b104-563f9d3be000
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145421875 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.edn_intr_test.4145421875
Directory /workspace/44.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.edn_intr_test.2895370181
Short name T950
Test name
Test status
Simulation time 64595557 ps
CPU time 0.8 seconds
Started Mar 12 12:36:15 PM PDT 24
Finished Mar 12 12:36:17 PM PDT 24
Peak memory 206376 kb
Host smart-10990545-daa7-4659-aef4-1876cb846160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895370181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.edn_intr_test.2895370181
Directory /workspace/45.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.edn_intr_test.308353468
Short name T874
Test name
Test status
Simulation time 24335866 ps
CPU time 0.84 seconds
Started Mar 12 12:36:15 PM PDT 24
Finished Mar 12 12:36:17 PM PDT 24
Peak memory 206528 kb
Host smart-09e3dc92-8e46-42ea-b676-e8dcdd531817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308353468 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.edn_intr_test.308353468
Directory /workspace/46.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.edn_intr_test.1045715724
Short name T881
Test name
Test status
Simulation time 41580504 ps
CPU time 0.78 seconds
Started Mar 12 12:36:18 PM PDT 24
Finished Mar 12 12:36:19 PM PDT 24
Peak memory 206356 kb
Host smart-5bd02b6a-c745-44ec-a202-1493f4e862bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045715724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.edn_intr_test.1045715724
Directory /workspace/47.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.edn_intr_test.3276627700
Short name T949
Test name
Test status
Simulation time 105175264 ps
CPU time 0.84 seconds
Started Mar 12 12:36:17 PM PDT 24
Finished Mar 12 12:36:18 PM PDT 24
Peak memory 206468 kb
Host smart-d2fb5cb1-acf7-4deb-8720-82f908fa452b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276627700 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.edn_intr_test.3276627700
Directory /workspace/48.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.edn_intr_test.1562753976
Short name T915
Test name
Test status
Simulation time 109014255 ps
CPU time 0.82 seconds
Started Mar 12 12:36:15 PM PDT 24
Finished Mar 12 12:36:17 PM PDT 24
Peak memory 206416 kb
Host smart-d62a3b90-5c93-4b03-adda-99cb6f78d9d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562753976 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.edn_intr_test.1562753976
Directory /workspace/49.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_mem_rw_with_rand_reset.3780849867
Short name T837
Test name
Test status
Simulation time 32501450 ps
CPU time 0.96 seconds
Started Mar 12 12:35:54 PM PDT 24
Finished Mar 12 12:35:55 PM PDT 24
Peak memory 206760 kb
Host smart-acf657b4-eae0-468d-8776-255c347406a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780849867 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.edn_csr_mem_rw_with_rand_reset.3780849867
Directory /workspace/5.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.edn_csr_rw.3131441234
Short name T860
Test name
Test status
Simulation time 16689535 ps
CPU time 0.99 seconds
Started Mar 12 12:36:09 PM PDT 24
Finished Mar 12 12:36:10 PM PDT 24
Peak memory 206524 kb
Host smart-245aa8fe-41ec-44bd-bdfe-20a1dc284f6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131441234 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_csr_rw.3131441234
Directory /workspace/5.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.edn_intr_test.2925224289
Short name T863
Test name
Test status
Simulation time 52635863 ps
CPU time 0.88 seconds
Started Mar 12 12:35:57 PM PDT 24
Finished Mar 12 12:35:59 PM PDT 24
Peak memory 206584 kb
Host smart-c2e5b11e-bfdc-4d6f-9a34-8629eabdb246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925224289 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_intr_test.2925224289
Directory /workspace/5.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.edn_same_csr_outstanding.2212228921
Short name T207
Test name
Test status
Simulation time 15177294 ps
CPU time 0.99 seconds
Started Mar 12 12:35:55 PM PDT 24
Finished Mar 12 12:35:57 PM PDT 24
Peak memory 206540 kb
Host smart-f287db5f-6b97-403f-bce0-8f9da196d4e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212228921 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_ou
tstanding.2212228921
Directory /workspace/5.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_errors.1707843166
Short name T896
Test name
Test status
Simulation time 97932284 ps
CPU time 3.4 seconds
Started Mar 12 12:35:50 PM PDT 24
Finished Mar 12 12:35:53 PM PDT 24
Peak memory 214876 kb
Host smart-db1703c9-e0e1-4e84-954a-a7369897aa29
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707843166 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_errors.1707843166
Directory /workspace/5.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.edn_tl_intg_err.2737022281
Short name T969
Test name
Test status
Simulation time 53756649 ps
CPU time 1.67 seconds
Started Mar 12 12:35:52 PM PDT 24
Finished Mar 12 12:35:54 PM PDT 24
Peak memory 206624 kb
Host smart-2922721d-b9a3-454d-9a84-59bd0882f35f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737022281 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_tl_intg_err.2737022281
Directory /workspace/5.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.edn_csr_mem_rw_with_rand_reset.3194025903
Short name T926
Test name
Test status
Simulation time 18269685 ps
CPU time 1.08 seconds
Started Mar 12 12:35:55 PM PDT 24
Finished Mar 12 12:35:57 PM PDT 24
Peak memory 214880 kb
Host smart-93d3e6ed-1da2-4090-a8ad-cb1764041fca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194025903 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.edn_csr_mem_rw_with_rand_reset.3194025903
Directory /workspace/6.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.edn_intr_test.559108857
Short name T842
Test name
Test status
Simulation time 24992059 ps
CPU time 0.84 seconds
Started Mar 12 12:36:00 PM PDT 24
Finished Mar 12 12:36:01 PM PDT 24
Peak memory 206552 kb
Host smart-a1434f31-5c48-48d5-930f-6f3a49842cf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559108857 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_intr_test.559108857
Directory /workspace/6.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.edn_same_csr_outstanding.2561512124
Short name T208
Test name
Test status
Simulation time 21417911 ps
CPU time 1.15 seconds
Started Mar 12 12:35:56 PM PDT 24
Finished Mar 12 12:35:57 PM PDT 24
Peak memory 206556 kb
Host smart-84e7664d-41f4-4bfb-923a-1094b437763b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561512124 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_same_csr_ou
tstanding.2561512124
Directory /workspace/6.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_errors.2211817205
Short name T952
Test name
Test status
Simulation time 43546740 ps
CPU time 2.98 seconds
Started Mar 12 12:35:55 PM PDT 24
Finished Mar 12 12:35:58 PM PDT 24
Peak memory 214940 kb
Host smart-cc2e3974-92ff-47bd-bc7e-5b158bb2ef4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211817205 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_errors.2211817205
Directory /workspace/6.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.edn_tl_intg_err.2513892418
Short name T232
Test name
Test status
Simulation time 188469178 ps
CPU time 2.49 seconds
Started Mar 12 12:35:54 PM PDT 24
Finished Mar 12 12:35:56 PM PDT 24
Peak memory 206608 kb
Host smart-f1f7b80e-c0a0-4b98-90cb-c3ad3b61d61f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513892418 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.edn_tl_intg_err.2513892418
Directory /workspace/6.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_mem_rw_with_rand_reset.2186260582
Short name T947
Test name
Test status
Simulation time 38381233 ps
CPU time 1.12 seconds
Started Mar 12 12:35:59 PM PDT 24
Finished Mar 12 12:36:01 PM PDT 24
Peak memory 214940 kb
Host smart-0910dc8b-3edb-41bf-b5c2-89e6bc418293
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186260582 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.edn_csr_mem_rw_with_rand_reset.2186260582
Directory /workspace/7.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.edn_csr_rw.3885420502
Short name T953
Test name
Test status
Simulation time 13354679 ps
CPU time 0.83 seconds
Started Mar 12 12:35:57 PM PDT 24
Finished Mar 12 12:35:58 PM PDT 24
Peak memory 206556 kb
Host smart-7033ac47-0d4f-423f-b84d-bef3bccac8ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885420502 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_csr_rw.3885420502
Directory /workspace/7.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.edn_intr_test.1206674812
Short name T852
Test name
Test status
Simulation time 18014407 ps
CPU time 0.85 seconds
Started Mar 12 12:36:08 PM PDT 24
Finished Mar 12 12:36:10 PM PDT 24
Peak memory 206324 kb
Host smart-2cd8c7af-b2ba-44d0-ab05-4f524e3880ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206674812 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_intr_test.1206674812
Directory /workspace/7.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.edn_same_csr_outstanding.644664233
Short name T960
Test name
Test status
Simulation time 89685963 ps
CPU time 0.9 seconds
Started Mar 12 12:35:58 PM PDT 24
Finished Mar 12 12:35:59 PM PDT 24
Peak memory 206636 kb
Host smart-c93d4f29-6d77-4398-b564-b6cf70d6767e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644664233 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_same_csr_out
standing.644664233
Directory /workspace/7.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_errors.3909197585
Short name T892
Test name
Test status
Simulation time 238710839 ps
CPU time 2.41 seconds
Started Mar 12 12:36:00 PM PDT 24
Finished Mar 12 12:36:02 PM PDT 24
Peak memory 215176 kb
Host smart-2c4f269e-78ed-4deb-bc8f-a99431fe188f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909197585 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_errors.3909197585
Directory /workspace/7.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.edn_tl_intg_err.1655278984
Short name T239
Test name
Test status
Simulation time 50861940 ps
CPU time 1.73 seconds
Started Mar 12 12:35:58 PM PDT 24
Finished Mar 12 12:36:01 PM PDT 24
Peak memory 206536 kb
Host smart-cb4061cf-e131-4c77-8a1f-745e16c7b659
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655278984 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.edn_tl_intg_err.1655278984
Directory /workspace/7.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_mem_rw_with_rand_reset.1139635588
Short name T958
Test name
Test status
Simulation time 33991511 ps
CPU time 1.02 seconds
Started Mar 12 12:35:57 PM PDT 24
Finished Mar 12 12:35:58 PM PDT 24
Peak memory 206636 kb
Host smart-272ef0fe-29ed-4f9e-bfe2-45c9c777df26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139635588 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.edn_csr_mem_rw_with_rand_reset.1139635588
Directory /workspace/8.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.edn_csr_rw.4233064994
Short name T215
Test name
Test status
Simulation time 13432468 ps
CPU time 0.83 seconds
Started Mar 12 12:35:59 PM PDT 24
Finished Mar 12 12:36:00 PM PDT 24
Peak memory 206636 kb
Host smart-ed12332f-b91f-444e-9524-7ffb6fab9fdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233064994 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_csr_rw.4233064994
Directory /workspace/8.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.edn_intr_test.3615689199
Short name T855
Test name
Test status
Simulation time 31329322 ps
CPU time 0.77 seconds
Started Mar 12 12:35:56 PM PDT 24
Finished Mar 12 12:35:58 PM PDT 24
Peak memory 206424 kb
Host smart-442c1e34-9283-4967-a98c-bcfb2aa5c07a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615689199 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_intr_test.3615689199
Directory /workspace/8.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.edn_same_csr_outstanding.1368968724
Short name T221
Test name
Test status
Simulation time 41046053 ps
CPU time 1.04 seconds
Started Mar 12 12:35:56 PM PDT 24
Finished Mar 12 12:35:58 PM PDT 24
Peak memory 206584 kb
Host smart-28ed9008-ca6f-4bfa-abe6-8cc7bc8e7960
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368968724 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_same_csr_ou
tstanding.1368968724
Directory /workspace/8.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_errors.958558731
Short name T905
Test name
Test status
Simulation time 93229537 ps
CPU time 3.37 seconds
Started Mar 12 12:35:58 PM PDT 24
Finished Mar 12 12:36:03 PM PDT 24
Peak memory 214904 kb
Host smart-4f1d9c35-4f9f-4219-9c1e-8948cf7a6923
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958558731 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_errors.958558731
Directory /workspace/8.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.edn_tl_intg_err.1308632586
Short name T965
Test name
Test status
Simulation time 753592398 ps
CPU time 1.69 seconds
Started Mar 12 12:36:08 PM PDT 24
Finished Mar 12 12:36:11 PM PDT 24
Peak memory 206596 kb
Host smart-7d3697f9-8ace-4e34-8f3d-ddbd7a0d40fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308632586 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.edn_tl_intg_err.1308632586
Directory /workspace/8.edn_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_mem_rw_with_rand_reset.1226088202
Short name T963
Test name
Test status
Simulation time 33443926 ps
CPU time 1.47 seconds
Started Mar 12 12:36:08 PM PDT 24
Finished Mar 12 12:36:10 PM PDT 24
Peak memory 214832 kb
Host smart-46472537-4139-44d4-99b6-914825ee5ff1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226088202 -assert nopostproc +UVM_TESTNAME
=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.edn_csr_mem_rw_with_rand_reset.1226088202
Directory /workspace/9.edn_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.edn_csr_rw.1150146760
Short name T220
Test name
Test status
Simulation time 31080520 ps
CPU time 0.77 seconds
Started Mar 12 12:35:54 PM PDT 24
Finished Mar 12 12:35:56 PM PDT 24
Peak memory 206384 kb
Host smart-b25ab756-7629-4cee-ae22-a4cbeeda1c9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150146760 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_csr_rw.1150146760
Directory /workspace/9.edn_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.edn_intr_test.1468529614
Short name T861
Test name
Test status
Simulation time 42456036 ps
CPU time 0.86 seconds
Started Mar 12 12:35:56 PM PDT 24
Finished Mar 12 12:35:58 PM PDT 24
Peak memory 206384 kb
Host smart-ae39f986-115f-4ef8-9a7d-ae188a29f500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468529614 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_intr_test.1468529614
Directory /workspace/9.edn_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.edn_same_csr_outstanding.3241486286
Short name T957
Test name
Test status
Simulation time 52646749 ps
CPU time 1.08 seconds
Started Mar 12 12:35:56 PM PDT 24
Finished Mar 12 12:35:58 PM PDT 24
Peak memory 206528 kb
Host smart-333133e7-8cde-4398-810d-f8381985cbc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241486286 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_same_csr_ou
tstanding.3241486286
Directory /workspace/9.edn_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_errors.3877387865
Short name T944
Test name
Test status
Simulation time 276098946 ps
CPU time 1.82 seconds
Started Mar 12 12:36:00 PM PDT 24
Finished Mar 12 12:36:02 PM PDT 24
Peak memory 214924 kb
Host smart-52d46dda-fdf8-4b8f-a811-deae453e0287
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877387865 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_errors.3877387865
Directory /workspace/9.edn_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.edn_tl_intg_err.814736710
Short name T939
Test name
Test status
Simulation time 195588094 ps
CPU time 1.55 seconds
Started Mar 12 12:35:54 PM PDT 24
Finished Mar 12 12:35:56 PM PDT 24
Peak memory 206500 kb
Host smart-3e0114fe-c48c-46aa-952a-d2f4104b1092
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814736710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.edn_tl_intg_err.814736710
Directory /workspace/9.edn_tl_intg_err/latest

Test location /workspace/coverage/default/0.edn_alert.2252811770
Short name T248
Test name
Test status
Simulation time 78913643 ps
CPU time 1.24 seconds
Started Mar 12 02:43:03 PM PDT 24
Finished Mar 12 02:43:04 PM PDT 24
Peak memory 214684 kb
Host smart-9f96393b-08db-4c51-b47f-38046b27be83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252811770 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert.2252811770
Directory /workspace/0.edn_alert/latest

Test location /workspace/coverage/default/0.edn_alert_test.1973676181
Short name T464
Test name
Test status
Simulation time 51456465 ps
CPU time 0.92 seconds
Started Mar 12 02:43:03 PM PDT 24
Finished Mar 12 02:43:04 PM PDT 24
Peak memory 205948 kb
Host smart-96a26608-a477-43ad-ab17-a79004b4a75b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973676181 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_alert_test.1973676181
Directory /workspace/0.edn_alert_test/latest

Test location /workspace/coverage/default/0.edn_disable.944732020
Short name T317
Test name
Test status
Simulation time 66200901 ps
CPU time 0.86 seconds
Started Mar 12 02:43:01 PM PDT 24
Finished Mar 12 02:43:02 PM PDT 24
Peak memory 214644 kb
Host smart-5cdf664a-16cc-434f-970a-387c5beba9ed
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944732020 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_disable.944732020
Directory /workspace/0.edn_disable/latest

Test location /workspace/coverage/default/0.edn_disable_auto_req_mode.3797142359
Short name T451
Test name
Test status
Simulation time 22270868 ps
CPU time 0.98 seconds
Started Mar 12 02:43:02 PM PDT 24
Finished Mar 12 02:43:03 PM PDT 24
Peak memory 216516 kb
Host smart-185a7cee-e0ae-4aeb-aca0-f6a9244de157
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797142359 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_di
sable_auto_req_mode.3797142359
Directory /workspace/0.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/0.edn_err.927694475
Short name T540
Test name
Test status
Simulation time 30151468 ps
CPU time 1.05 seconds
Started Mar 12 02:43:02 PM PDT 24
Finished Mar 12 02:43:03 PM PDT 24
Peak memory 217352 kb
Host smart-56dbbf3d-d771-4b97-8bd7-1ac8290a1dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927694475 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_err.927694475
Directory /workspace/0.edn_err/latest

Test location /workspace/coverage/default/0.edn_genbits.746024308
Short name T439
Test name
Test status
Simulation time 91041650 ps
CPU time 1.05 seconds
Started Mar 12 02:42:55 PM PDT 24
Finished Mar 12 02:42:56 PM PDT 24
Peak memory 215720 kb
Host smart-6b663cb9-a169-45fc-859b-65a15b4894ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746024308 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_genbits.746024308
Directory /workspace/0.edn_genbits/latest

Test location /workspace/coverage/default/0.edn_intr.854129597
Short name T330
Test name
Test status
Simulation time 37092079 ps
CPU time 0.92 seconds
Started Mar 12 02:43:04 PM PDT 24
Finished Mar 12 02:43:05 PM PDT 24
Peak memory 214552 kb
Host smart-f101bfc7-3917-4a62-ac65-d836a74dde01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854129597 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.854129597
Directory /workspace/0.edn_intr/latest

Test location /workspace/coverage/default/0.edn_sec_cm.2191099944
Short name T54
Test name
Test status
Simulation time 190777509 ps
CPU time 3.49 seconds
Started Mar 12 02:43:03 PM PDT 24
Finished Mar 12 02:43:06 PM PDT 24
Peak memory 240156 kb
Host smart-a2dc125b-591d-4f37-9033-0578269d835d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191099944 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.2191099944
Directory /workspace/0.edn_sec_cm/latest

Test location /workspace/coverage/default/0.edn_smoke.2605971451
Short name T749
Test name
Test status
Simulation time 27114850 ps
CPU time 0.92 seconds
Started Mar 12 02:42:56 PM PDT 24
Finished Mar 12 02:42:57 PM PDT 24
Peak memory 206160 kb
Host smart-51400a07-c947-4e08-a093-cbb1801720eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605971451 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_smoke.2605971451
Directory /workspace/0.edn_smoke/latest

Test location /workspace/coverage/default/0.edn_stress_all.942623088
Short name T395
Test name
Test status
Simulation time 204355350 ps
CPU time 3.98 seconds
Started Mar 12 02:43:02 PM PDT 24
Finished Mar 12 02:43:06 PM PDT 24
Peak memory 216816 kb
Host smart-3c292286-5860-49fa-84f8-920aa867675a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942623088 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_stress_all.942623088
Directory /workspace/0.edn_stress_all/latest

Test location /workspace/coverage/default/0.edn_stress_all_with_rand_reset.3356427736
Short name T193
Test name
Test status
Simulation time 54445026252 ps
CPU time 661.62 seconds
Started Mar 12 02:43:01 PM PDT 24
Finished Mar 12 02:54:02 PM PDT 24
Peak memory 216500 kb
Host smart-21b61be8-1250-461d-88dd-a46e511e2486
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356427736 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.edn_stress_all_with_rand_reset.3356427736
Directory /workspace/0.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.edn_alert.1403547998
Short name T819
Test name
Test status
Simulation time 50249617 ps
CPU time 1.18 seconds
Started Mar 12 02:46:08 PM PDT 24
Finished Mar 12 02:46:09 PM PDT 24
Peak memory 214720 kb
Host smart-b07bb984-1243-4967-bfc5-51b997432b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403547998 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert.1403547998
Directory /workspace/1.edn_alert/latest

Test location /workspace/coverage/default/1.edn_alert_test.1656587367
Short name T416
Test name
Test status
Simulation time 17132432 ps
CPU time 0.99 seconds
Started Mar 12 02:46:37 PM PDT 24
Finished Mar 12 02:46:38 PM PDT 24
Peak memory 205996 kb
Host smart-24194628-dcd3-4a2e-a4dd-2b0a0c57caf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656587367 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_alert_test.1656587367
Directory /workspace/1.edn_alert_test/latest

Test location /workspace/coverage/default/1.edn_disable.3223760196
Short name T159
Test name
Test status
Simulation time 11085543 ps
CPU time 0.88 seconds
Started Mar 12 02:45:33 PM PDT 24
Finished Mar 12 02:45:35 PM PDT 24
Peak memory 214896 kb
Host smart-b8e6a802-af2f-46a3-b6b3-3302ae8e5c03
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223760196 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.3223760196
Directory /workspace/1.edn_disable/latest

Test location /workspace/coverage/default/1.edn_disable_auto_req_mode.708980897
Short name T463
Test name
Test status
Simulation time 119527489 ps
CPU time 1.11 seconds
Started Mar 12 02:43:01 PM PDT 24
Finished Mar 12 02:43:02 PM PDT 24
Peak memory 215624 kb
Host smart-0b064a7f-55c8-4947-924f-9063bdc40e05
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708980897 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_dis
able_auto_req_mode.708980897
Directory /workspace/1.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/1.edn_err.3810306281
Short name T816
Test name
Test status
Simulation time 26180859 ps
CPU time 1.3 seconds
Started Mar 12 02:45:04 PM PDT 24
Finished Mar 12 02:45:05 PM PDT 24
Peak memory 230612 kb
Host smart-39e864da-4c23-4a00-ac60-d4c5fae65f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810306281 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_err.3810306281
Directory /workspace/1.edn_err/latest

Test location /workspace/coverage/default/1.edn_genbits.2772080048
Short name T428
Test name
Test status
Simulation time 69502161 ps
CPU time 1.07 seconds
Started Mar 12 02:45:17 PM PDT 24
Finished Mar 12 02:45:19 PM PDT 24
Peak memory 215540 kb
Host smart-c7ba6c95-0156-4bdc-b6d3-bdd3adba71b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772080048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_genbits.2772080048
Directory /workspace/1.edn_genbits/latest

Test location /workspace/coverage/default/1.edn_intr.4250060641
Short name T132
Test name
Test status
Simulation time 26630412 ps
CPU time 0.86 seconds
Started Mar 12 02:46:07 PM PDT 24
Finished Mar 12 02:46:08 PM PDT 24
Peak memory 214832 kb
Host smart-40c2a5a8-fb0e-4e72-b322-9cd17c3e27a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250060641 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_intr.4250060641
Directory /workspace/1.edn_intr/latest

Test location /workspace/coverage/default/1.edn_sec_cm.1698815147
Short name T53
Test name
Test status
Simulation time 1537955582 ps
CPU time 6.19 seconds
Started Mar 12 02:46:34 PM PDT 24
Finished Mar 12 02:46:41 PM PDT 24
Peak memory 236316 kb
Host smart-757ef734-503e-4e12-886c-6ae668119e96
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698815147 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_sec_cm.1698815147
Directory /workspace/1.edn_sec_cm/latest

Test location /workspace/coverage/default/1.edn_smoke.4255502173
Short name T459
Test name
Test status
Simulation time 15895900 ps
CPU time 0.96 seconds
Started Mar 12 02:43:01 PM PDT 24
Finished Mar 12 02:43:03 PM PDT 24
Peak memory 214480 kb
Host smart-490ff03b-7671-4389-93d3-2cd9e56290c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255502173 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_smoke.4255502173
Directory /workspace/1.edn_smoke/latest

Test location /workspace/coverage/default/1.edn_stress_all.4263949085
Short name T204
Test name
Test status
Simulation time 262627071 ps
CPU time 2.4 seconds
Started Mar 12 02:43:03 PM PDT 24
Finished Mar 12 02:43:05 PM PDT 24
Peak memory 215632 kb
Host smart-f50466eb-2695-4a74-80d5-9b47eb6a1116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263949085 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.4263949085
Directory /workspace/1.edn_stress_all/latest

Test location /workspace/coverage/default/1.edn_stress_all_with_rand_reset.4233065961
Short name T810
Test name
Test status
Simulation time 180006269545 ps
CPU time 863.78 seconds
Started Mar 12 02:43:02 PM PDT 24
Finished Mar 12 02:57:26 PM PDT 24
Peak memory 218504 kb
Host smart-c7a14f43-40e2-4eac-b793-aa8ccf817317
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233065961 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.edn_stress_all_with_rand_reset.4233065961
Directory /workspace/1.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.edn_alert_test.2141160149
Short name T654
Test name
Test status
Simulation time 42921959 ps
CPU time 0.81 seconds
Started Mar 12 02:43:41 PM PDT 24
Finished Mar 12 02:43:42 PM PDT 24
Peak memory 204980 kb
Host smart-029490c0-8b67-4733-94fa-4abc3e59a42c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141160149 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_alert_test.2141160149
Directory /workspace/10.edn_alert_test/latest

Test location /workspace/coverage/default/10.edn_disable_auto_req_mode.2182712828
Short name T158
Test name
Test status
Simulation time 33802681 ps
CPU time 1.22 seconds
Started Mar 12 02:43:44 PM PDT 24
Finished Mar 12 02:43:46 PM PDT 24
Peak memory 216772 kb
Host smart-d0b93a2b-e31f-4c2f-9cbc-ae0c89e86649
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182712828 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_d
isable_auto_req_mode.2182712828
Directory /workspace/10.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/10.edn_genbits.4077709334
Short name T697
Test name
Test status
Simulation time 66085734 ps
CPU time 1.1 seconds
Started Mar 12 02:43:44 PM PDT 24
Finished Mar 12 02:43:46 PM PDT 24
Peak memory 217268 kb
Host smart-87f91b85-3c88-4219-b190-fb81d36c2c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077709334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_genbits.4077709334
Directory /workspace/10.edn_genbits/latest

Test location /workspace/coverage/default/10.edn_intr.3373665867
Short name T412
Test name
Test status
Simulation time 64700520 ps
CPU time 0.87 seconds
Started Mar 12 02:43:41 PM PDT 24
Finished Mar 12 02:43:42 PM PDT 24
Peak memory 214464 kb
Host smart-82358a77-866e-4add-b685-600840d4fa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373665867 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_intr.3373665867
Directory /workspace/10.edn_intr/latest

Test location /workspace/coverage/default/10.edn_smoke.700945718
Short name T364
Test name
Test status
Simulation time 15458780 ps
CPU time 0.9 seconds
Started Mar 12 02:43:36 PM PDT 24
Finished Mar 12 02:43:37 PM PDT 24
Peak memory 214484 kb
Host smart-a03ed758-c47a-4334-9ccc-5c0860aec54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700945718 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_smoke.700945718
Directory /workspace/10.edn_smoke/latest

Test location /workspace/coverage/default/10.edn_stress_all.4000895565
Short name T410
Test name
Test status
Simulation time 327824882 ps
CPU time 3.66 seconds
Started Mar 12 02:43:41 PM PDT 24
Finished Mar 12 02:43:45 PM PDT 24
Peak memory 215712 kb
Host smart-71ecfc49-4e50-4940-968d-aa1bee309730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000895565 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.edn_stress_all.4000895565
Directory /workspace/10.edn_stress_all/latest

Test location /workspace/coverage/default/10.edn_stress_all_with_rand_reset.1649286332
Short name T196
Test name
Test status
Simulation time 581031441331 ps
CPU time 1953.12 seconds
Started Mar 12 02:43:42 PM PDT 24
Finished Mar 12 03:16:15 PM PDT 24
Peak memory 224132 kb
Host smart-a0d10662-77b6-4c95-ae98-b6e937526583
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649286332 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 10.edn_stress_all_with_rand_reset.1649286332
Directory /workspace/10.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.edn_genbits.1473625709
Short name T574
Test name
Test status
Simulation time 215053459 ps
CPU time 2.92 seconds
Started Mar 12 02:45:57 PM PDT 24
Finished Mar 12 02:46:00 PM PDT 24
Peak memory 218528 kb
Host smart-d71e2576-5842-42f0-b72f-dab04427a835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473625709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.edn_genbits.1473625709
Directory /workspace/100.edn_genbits/latest

Test location /workspace/coverage/default/101.edn_genbits.3092587289
Short name T363
Test name
Test status
Simulation time 92088639 ps
CPU time 1.2 seconds
Started Mar 12 02:46:00 PM PDT 24
Finished Mar 12 02:46:02 PM PDT 24
Peak memory 218140 kb
Host smart-81cbe248-441d-4e07-b9d7-29431b496041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092587289 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.edn_genbits.3092587289
Directory /workspace/101.edn_genbits/latest

Test location /workspace/coverage/default/103.edn_genbits.3788911478
Short name T628
Test name
Test status
Simulation time 81993948 ps
CPU time 1.11 seconds
Started Mar 12 02:46:00 PM PDT 24
Finished Mar 12 02:46:01 PM PDT 24
Peak memory 215596 kb
Host smart-193a778b-2213-4224-9c7b-7ff6d9054d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788911478 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.edn_genbits.3788911478
Directory /workspace/103.edn_genbits/latest

Test location /workspace/coverage/default/104.edn_genbits.1812139995
Short name T406
Test name
Test status
Simulation time 114242707 ps
CPU time 1.32 seconds
Started Mar 12 02:46:02 PM PDT 24
Finished Mar 12 02:46:03 PM PDT 24
Peak memory 216960 kb
Host smart-87ee4466-b1bd-46f7-89fd-d48cb5872103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812139995 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.edn_genbits.1812139995
Directory /workspace/104.edn_genbits/latest

Test location /workspace/coverage/default/105.edn_genbits.1653487361
Short name T398
Test name
Test status
Simulation time 40533630 ps
CPU time 1.4 seconds
Started Mar 12 02:46:00 PM PDT 24
Finished Mar 12 02:46:01 PM PDT 24
Peak memory 217068 kb
Host smart-7eca12e5-f9af-40b9-b3ab-31ca47c7dddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653487361 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.edn_genbits.1653487361
Directory /workspace/105.edn_genbits/latest

Test location /workspace/coverage/default/106.edn_genbits.1764945567
Short name T725
Test name
Test status
Simulation time 31288605 ps
CPU time 1.32 seconds
Started Mar 12 02:45:59 PM PDT 24
Finished Mar 12 02:46:00 PM PDT 24
Peak memory 217916 kb
Host smart-8b8bfb1e-81d2-4f99-8809-eacd7a55bcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764945567 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.edn_genbits.1764945567
Directory /workspace/106.edn_genbits/latest

Test location /workspace/coverage/default/107.edn_genbits.4071797424
Short name T538
Test name
Test status
Simulation time 94256604 ps
CPU time 1.08 seconds
Started Mar 12 02:45:56 PM PDT 24
Finished Mar 12 02:45:57 PM PDT 24
Peak memory 215752 kb
Host smart-13092ad6-113d-4872-b0c7-00779973433a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071797424 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.edn_genbits.4071797424
Directory /workspace/107.edn_genbits/latest

Test location /workspace/coverage/default/108.edn_genbits.2108692526
Short name T678
Test name
Test status
Simulation time 341681627 ps
CPU time 1.57 seconds
Started Mar 12 02:46:03 PM PDT 24
Finished Mar 12 02:46:05 PM PDT 24
Peak memory 217588 kb
Host smart-9077db56-068e-4d0b-b3c4-5032c3691a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108692526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.edn_genbits.2108692526
Directory /workspace/108.edn_genbits/latest

Test location /workspace/coverage/default/11.edn_alert_test.3530441696
Short name T396
Test name
Test status
Simulation time 75409958 ps
CPU time 0.89 seconds
Started Mar 12 02:43:44 PM PDT 24
Finished Mar 12 02:43:46 PM PDT 24
Peak memory 206104 kb
Host smart-87f419b5-38d7-4812-b799-a0a6f4dcbba4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530441696 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_alert_test.3530441696
Directory /workspace/11.edn_alert_test/latest

Test location /workspace/coverage/default/11.edn_err.4028373407
Short name T662
Test name
Test status
Simulation time 122784038 ps
CPU time 1.16 seconds
Started Mar 12 02:43:41 PM PDT 24
Finished Mar 12 02:43:43 PM PDT 24
Peak memory 223504 kb
Host smart-e965bb82-4f2a-4c40-839e-257048320563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028373407 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_err.4028373407
Directory /workspace/11.edn_err/latest

Test location /workspace/coverage/default/11.edn_intr.1510324937
Short name T69
Test name
Test status
Simulation time 33773922 ps
CPU time 0.9 seconds
Started Mar 12 02:43:43 PM PDT 24
Finished Mar 12 02:43:44 PM PDT 24
Peak memory 214808 kb
Host smart-e9f4e722-28af-4c92-8432-d96eb669d8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510324937 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_intr.1510324937
Directory /workspace/11.edn_intr/latest

Test location /workspace/coverage/default/11.edn_smoke.2737336077
Short name T609
Test name
Test status
Simulation time 14593971 ps
CPU time 1.02 seconds
Started Mar 12 02:43:42 PM PDT 24
Finished Mar 12 02:43:44 PM PDT 24
Peak memory 214292 kb
Host smart-3b172102-3aab-4b4a-9909-3812da899264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737336077 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_smoke.2737336077
Directory /workspace/11.edn_smoke/latest

Test location /workspace/coverage/default/11.edn_stress_all.944971192
Short name T156
Test name
Test status
Simulation time 258818438 ps
CPU time 1.56 seconds
Started Mar 12 02:43:42 PM PDT 24
Finished Mar 12 02:43:44 PM PDT 24
Peak memory 214404 kb
Host smart-5e8cde83-18e0-4214-bf57-76f5b09a8911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944971192 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_stress_all.944971192
Directory /workspace/11.edn_stress_all/latest

Test location /workspace/coverage/default/11.edn_stress_all_with_rand_reset.725961757
Short name T192
Test name
Test status
Simulation time 93706411992 ps
CPU time 567.99 seconds
Started Mar 12 02:43:45 PM PDT 24
Finished Mar 12 02:53:13 PM PDT 24
Peak memory 217948 kb
Host smart-c141b561-e8fe-4027-9533-b4028b5d3ba2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725961757 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.edn_stress_all_with_rand_reset.725961757
Directory /workspace/11.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.edn_genbits.2833113040
Short name T28
Test name
Test status
Simulation time 46347450 ps
CPU time 1.35 seconds
Started Mar 12 02:46:01 PM PDT 24
Finished Mar 12 02:46:02 PM PDT 24
Peak memory 217200 kb
Host smart-720f177d-0b85-43e2-abe4-6c4bb4a2ffaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833113040 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.edn_genbits.2833113040
Directory /workspace/110.edn_genbits/latest

Test location /workspace/coverage/default/111.edn_genbits.1412411094
Short name T768
Test name
Test status
Simulation time 201155379 ps
CPU time 1.16 seconds
Started Mar 12 02:45:57 PM PDT 24
Finished Mar 12 02:45:58 PM PDT 24
Peak memory 215600 kb
Host smart-d3445030-5073-48cd-a1bd-76eb406caa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412411094 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.edn_genbits.1412411094
Directory /workspace/111.edn_genbits/latest

Test location /workspace/coverage/default/112.edn_genbits.3294600000
Short name T828
Test name
Test status
Simulation time 88759255 ps
CPU time 1.2 seconds
Started Mar 12 02:45:57 PM PDT 24
Finished Mar 12 02:45:58 PM PDT 24
Peak memory 216004 kb
Host smart-57de5b6a-0329-4938-96d4-ea45cc32b58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294600000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.edn_genbits.3294600000
Directory /workspace/112.edn_genbits/latest

Test location /workspace/coverage/default/113.edn_genbits.4181347509
Short name T754
Test name
Test status
Simulation time 59290043 ps
CPU time 1.28 seconds
Started Mar 12 02:46:00 PM PDT 24
Finished Mar 12 02:46:02 PM PDT 24
Peak memory 217068 kb
Host smart-a8609c18-e214-4bf2-86e7-8de298bb4d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181347509 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.edn_genbits.4181347509
Directory /workspace/113.edn_genbits/latest

Test location /workspace/coverage/default/114.edn_genbits.3280176000
Short name T47
Test name
Test status
Simulation time 56368589 ps
CPU time 1.33 seconds
Started Mar 12 02:45:59 PM PDT 24
Finished Mar 12 02:46:00 PM PDT 24
Peak memory 215560 kb
Host smart-b6ee85c2-fd65-40ca-8bf2-70ada5001c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280176000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.edn_genbits.3280176000
Directory /workspace/114.edn_genbits/latest

Test location /workspace/coverage/default/115.edn_genbits.2545294571
Short name T716
Test name
Test status
Simulation time 33469820 ps
CPU time 1.32 seconds
Started Mar 12 02:46:00 PM PDT 24
Finished Mar 12 02:46:01 PM PDT 24
Peak memory 214556 kb
Host smart-4dd44553-24ea-4128-988f-94f7a3acbfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545294571 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.edn_genbits.2545294571
Directory /workspace/115.edn_genbits/latest

Test location /workspace/coverage/default/116.edn_genbits.3599736981
Short name T767
Test name
Test status
Simulation time 81359762 ps
CPU time 1.1 seconds
Started Mar 12 02:46:00 PM PDT 24
Finished Mar 12 02:46:01 PM PDT 24
Peak memory 215680 kb
Host smart-ffb553d9-824f-4137-bbde-146fcdb72463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599736981 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.edn_genbits.3599736981
Directory /workspace/116.edn_genbits/latest

Test location /workspace/coverage/default/117.edn_genbits.3202237814
Short name T334
Test name
Test status
Simulation time 44361801 ps
CPU time 1.24 seconds
Started Mar 12 02:46:00 PM PDT 24
Finished Mar 12 02:46:01 PM PDT 24
Peak memory 216864 kb
Host smart-91d33047-73c6-4213-b951-d426035cdd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202237814 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.edn_genbits.3202237814
Directory /workspace/117.edn_genbits/latest

Test location /workspace/coverage/default/118.edn_genbits.3808377018
Short name T613
Test name
Test status
Simulation time 116912859 ps
CPU time 1.56 seconds
Started Mar 12 02:45:58 PM PDT 24
Finished Mar 12 02:46:00 PM PDT 24
Peak memory 217188 kb
Host smart-d1d54904-b9e5-414e-bda2-979cc67cebf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808377018 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.edn_genbits.3808377018
Directory /workspace/118.edn_genbits/latest

Test location /workspace/coverage/default/119.edn_genbits.3586063598
Short name T262
Test name
Test status
Simulation time 202693034 ps
CPU time 1.85 seconds
Started Mar 12 02:45:58 PM PDT 24
Finished Mar 12 02:46:00 PM PDT 24
Peak memory 217040 kb
Host smart-eae9c0a3-8e0f-4c88-a973-d520bc72d9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586063598 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.edn_genbits.3586063598
Directory /workspace/119.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_alert.4176726614
Short name T447
Test name
Test status
Simulation time 121442063 ps
CPU time 1.21 seconds
Started Mar 12 02:43:50 PM PDT 24
Finished Mar 12 02:43:52 PM PDT 24
Peak memory 214868 kb
Host smart-8f1f562b-af59-473a-9543-f96b822c3633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176726614 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert.4176726614
Directory /workspace/12.edn_alert/latest

Test location /workspace/coverage/default/12.edn_alert_test.1824473811
Short name T808
Test name
Test status
Simulation time 51440116 ps
CPU time 0.9 seconds
Started Mar 12 02:43:51 PM PDT 24
Finished Mar 12 02:43:52 PM PDT 24
Peak memory 205732 kb
Host smart-9b116a1c-06ee-401a-84bf-9be5309b5024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824473811 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_alert_test.1824473811
Directory /workspace/12.edn_alert_test/latest

Test location /workspace/coverage/default/12.edn_disable.1254828704
Short name T719
Test name
Test status
Simulation time 11839135 ps
CPU time 0.91 seconds
Started Mar 12 02:43:52 PM PDT 24
Finished Mar 12 02:43:54 PM PDT 24
Peak memory 214920 kb
Host smart-d5b87d7c-8e96-4200-9575-42020477503d
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254828704 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_disable.1254828704
Directory /workspace/12.edn_disable/latest

Test location /workspace/coverage/default/12.edn_disable_auto_req_mode.3741581013
Short name T533
Test name
Test status
Simulation time 199641144 ps
CPU time 0.95 seconds
Started Mar 12 02:43:51 PM PDT 24
Finished Mar 12 02:43:52 PM PDT 24
Peak memory 216644 kb
Host smart-d586a014-4f24-454f-addd-d9a8e71413e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741581013 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_d
isable_auto_req_mode.3741581013
Directory /workspace/12.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/12.edn_err.3492897828
Short name T101
Test name
Test status
Simulation time 32430076 ps
CPU time 0.96 seconds
Started Mar 12 02:43:49 PM PDT 24
Finished Mar 12 02:43:50 PM PDT 24
Peak memory 230484 kb
Host smart-4a882a2c-82e3-4a06-b5f6-dafe52f15c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492897828 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_err.3492897828
Directory /workspace/12.edn_err/latest

Test location /workspace/coverage/default/12.edn_genbits.512943161
Short name T677
Test name
Test status
Simulation time 70245300 ps
CPU time 1.22 seconds
Started Mar 12 02:43:45 PM PDT 24
Finished Mar 12 02:43:46 PM PDT 24
Peak memory 217156 kb
Host smart-79246191-3e9a-4a71-84d2-925c6b3d0112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512943161 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_genbits.512943161
Directory /workspace/12.edn_genbits/latest

Test location /workspace/coverage/default/12.edn_intr.660583257
Short name T465
Test name
Test status
Simulation time 22708072 ps
CPU time 0.9 seconds
Started Mar 12 02:43:52 PM PDT 24
Finished Mar 12 02:43:54 PM PDT 24
Peak memory 214788 kb
Host smart-5cf6b9fc-c1af-4857-8cbe-0e78a6c57c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660583257 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_intr.660583257
Directory /workspace/12.edn_intr/latest

Test location /workspace/coverage/default/12.edn_smoke.729424139
Short name T417
Test name
Test status
Simulation time 39795171 ps
CPU time 0.88 seconds
Started Mar 12 02:43:40 PM PDT 24
Finished Mar 12 02:43:42 PM PDT 24
Peak memory 214396 kb
Host smart-cb99f2f8-e939-4f5e-9381-1c4fd8ed3809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729424139 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_smoke.729424139
Directory /workspace/12.edn_smoke/latest

Test location /workspace/coverage/default/12.edn_stress_all.4290243261
Short name T313
Test name
Test status
Simulation time 894027429 ps
CPU time 3.32 seconds
Started Mar 12 02:43:43 PM PDT 24
Finished Mar 12 02:43:46 PM PDT 24
Peak memory 214476 kb
Host smart-4626f30b-4b45-4fb1-8f02-2141d2f91d00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290243261 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.edn_stress_all.4290243261
Directory /workspace/12.edn_stress_all/latest

Test location /workspace/coverage/default/12.edn_stress_all_with_rand_reset.4052358072
Short name T696
Test name
Test status
Simulation time 153928327938 ps
CPU time 924.99 seconds
Started Mar 12 02:43:44 PM PDT 24
Finished Mar 12 02:59:10 PM PDT 24
Peak memory 222852 kb
Host smart-3dbf034c-23b8-46ea-8b2c-7e434b44e85b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052358072 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.edn_stress_all_with_rand_reset.4052358072
Directory /workspace/12.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.edn_genbits.2284435032
Short name T651
Test name
Test status
Simulation time 31977338 ps
CPU time 1.23 seconds
Started Mar 12 02:45:58 PM PDT 24
Finished Mar 12 02:46:00 PM PDT 24
Peak memory 215616 kb
Host smart-d52b8a1f-f355-410f-9f33-7dd83fca4ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284435032 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.edn_genbits.2284435032
Directory /workspace/120.edn_genbits/latest

Test location /workspace/coverage/default/121.edn_genbits.1981913787
Short name T740
Test name
Test status
Simulation time 37310153 ps
CPU time 1.36 seconds
Started Mar 12 02:46:03 PM PDT 24
Finished Mar 12 02:46:05 PM PDT 24
Peak memory 217000 kb
Host smart-137276f4-263b-4f3e-b052-e6f1a7b0b2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981913787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.edn_genbits.1981913787
Directory /workspace/121.edn_genbits/latest

Test location /workspace/coverage/default/122.edn_genbits.160618389
Short name T695
Test name
Test status
Simulation time 316831525 ps
CPU time 3.86 seconds
Started Mar 12 02:46:06 PM PDT 24
Finished Mar 12 02:46:10 PM PDT 24
Peak memory 217088 kb
Host smart-4e38b558-8922-43c0-85d9-cf445a0120bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160618389 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.edn_genbits.160618389
Directory /workspace/122.edn_genbits/latest

Test location /workspace/coverage/default/123.edn_genbits.3461438179
Short name T186
Test name
Test status
Simulation time 60804204 ps
CPU time 1.35 seconds
Started Mar 12 02:46:09 PM PDT 24
Finished Mar 12 02:46:11 PM PDT 24
Peak memory 216952 kb
Host smart-e954339e-8d6e-413b-a2cc-2cd1f891dc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461438179 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.edn_genbits.3461438179
Directory /workspace/123.edn_genbits/latest

Test location /workspace/coverage/default/124.edn_genbits.3055841954
Short name T793
Test name
Test status
Simulation time 61323916 ps
CPU time 1.51 seconds
Started Mar 12 02:46:09 PM PDT 24
Finished Mar 12 02:46:11 PM PDT 24
Peak memory 215780 kb
Host smart-dccbc4e3-b7a1-49fa-be70-31aa3f232202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055841954 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.edn_genbits.3055841954
Directory /workspace/124.edn_genbits/latest

Test location /workspace/coverage/default/126.edn_genbits.1936052336
Short name T539
Test name
Test status
Simulation time 415561623 ps
CPU time 2.22 seconds
Started Mar 12 02:46:08 PM PDT 24
Finished Mar 12 02:46:10 PM PDT 24
Peak memory 217072 kb
Host smart-9e4037de-1093-4ef5-a0e3-76b64477efd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936052336 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.edn_genbits.1936052336
Directory /workspace/126.edn_genbits/latest

Test location /workspace/coverage/default/127.edn_genbits.1852112037
Short name T806
Test name
Test status
Simulation time 51354925 ps
CPU time 1.13 seconds
Started Mar 12 02:46:08 PM PDT 24
Finished Mar 12 02:46:09 PM PDT 24
Peak memory 216960 kb
Host smart-62950c7f-f561-46f1-85ae-cf200026c6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852112037 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.edn_genbits.1852112037
Directory /workspace/127.edn_genbits/latest

Test location /workspace/coverage/default/128.edn_genbits.973340404
Short name T739
Test name
Test status
Simulation time 35023223 ps
CPU time 1.05 seconds
Started Mar 12 02:46:06 PM PDT 24
Finished Mar 12 02:46:08 PM PDT 24
Peak memory 217244 kb
Host smart-118b8036-388a-437c-81f5-673240fa9c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973340404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.edn_genbits.973340404
Directory /workspace/128.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_alert.4069253169
Short name T12
Test name
Test status
Simulation time 26894834 ps
CPU time 1.21 seconds
Started Mar 12 02:43:49 PM PDT 24
Finished Mar 12 02:43:51 PM PDT 24
Peak memory 214860 kb
Host smart-e2c68bc3-f0fd-4dc9-b237-f61f811747b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069253169 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert.4069253169
Directory /workspace/13.edn_alert/latest

Test location /workspace/coverage/default/13.edn_alert_test.3368200980
Short name T433
Test name
Test status
Simulation time 13876122 ps
CPU time 0.88 seconds
Started Mar 12 02:43:49 PM PDT 24
Finished Mar 12 02:43:51 PM PDT 24
Peak memory 205636 kb
Host smart-f0a907d1-9fa8-4cd3-b12e-adfb5bef2c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368200980 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_alert_test.3368200980
Directory /workspace/13.edn_alert_test/latest

Test location /workspace/coverage/default/13.edn_disable.3525381869
Short name T505
Test name
Test status
Simulation time 14658082 ps
CPU time 0.91 seconds
Started Mar 12 02:43:50 PM PDT 24
Finished Mar 12 02:43:51 PM PDT 24
Peak memory 215040 kb
Host smart-d9748b88-5d4d-4573-917a-6844cef34a9f
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525381869 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_disable.3525381869
Directory /workspace/13.edn_disable/latest

Test location /workspace/coverage/default/13.edn_disable_auto_req_mode.3986947457
Short name T746
Test name
Test status
Simulation time 41722319 ps
CPU time 1.02 seconds
Started Mar 12 02:43:49 PM PDT 24
Finished Mar 12 02:43:51 PM PDT 24
Peak memory 216860 kb
Host smart-cb879606-1d25-4a3e-8c30-43dc4001eab9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986947457 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_d
isable_auto_req_mode.3986947457
Directory /workspace/13.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/13.edn_err.2536917951
Short name T770
Test name
Test status
Simulation time 29854293 ps
CPU time 0.9 seconds
Started Mar 12 02:43:53 PM PDT 24
Finished Mar 12 02:43:56 PM PDT 24
Peak memory 217240 kb
Host smart-d8efe5a1-6eea-45b2-a532-6f2ff5e16f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536917951 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_err.2536917951
Directory /workspace/13.edn_err/latest

Test location /workspace/coverage/default/13.edn_genbits.2807792534
Short name T514
Test name
Test status
Simulation time 69130643 ps
CPU time 1.15 seconds
Started Mar 12 02:43:52 PM PDT 24
Finished Mar 12 02:43:54 PM PDT 24
Peak memory 215648 kb
Host smart-23a63a1c-8a48-4f50-9fe5-0fadc88546d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807792534 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_genbits.2807792534
Directory /workspace/13.edn_genbits/latest

Test location /workspace/coverage/default/13.edn_smoke.1673297026
Short name T647
Test name
Test status
Simulation time 18201041 ps
CPU time 0.98 seconds
Started Mar 12 02:43:49 PM PDT 24
Finished Mar 12 02:43:50 PM PDT 24
Peak memory 214436 kb
Host smart-a4f8195f-ddd4-41a0-b472-c2b945a5a5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673297026 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_smoke.1673297026
Directory /workspace/13.edn_smoke/latest

Test location /workspace/coverage/default/13.edn_stress_all.1729388336
Short name T672
Test name
Test status
Simulation time 193019972 ps
CPU time 3.85 seconds
Started Mar 12 02:43:51 PM PDT 24
Finished Mar 12 02:43:55 PM PDT 24
Peak memory 215556 kb
Host smart-e7f9ac61-5abf-4298-808c-2123badd7e0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729388336 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.edn_stress_all.1729388336
Directory /workspace/13.edn_stress_all/latest

Test location /workspace/coverage/default/13.edn_stress_all_with_rand_reset.1920079219
Short name T778
Test name
Test status
Simulation time 19677940798 ps
CPU time 506.35 seconds
Started Mar 12 02:43:50 PM PDT 24
Finished Mar 12 02:52:17 PM PDT 24
Peak memory 216692 kb
Host smart-363322e0-7a13-4176-8a37-e96ad5442376
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920079219 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.edn_stress_all_with_rand_reset.1920079219
Directory /workspace/13.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.edn_genbits.2315305283
Short name T303
Test name
Test status
Simulation time 49716361 ps
CPU time 1.44 seconds
Started Mar 12 02:46:05 PM PDT 24
Finished Mar 12 02:46:07 PM PDT 24
Peak memory 217060 kb
Host smart-41a0083c-7e27-446c-a869-fe2390c22a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315305283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.edn_genbits.2315305283
Directory /workspace/130.edn_genbits/latest

Test location /workspace/coverage/default/132.edn_genbits.4261027334
Short name T422
Test name
Test status
Simulation time 35407549 ps
CPU time 1.42 seconds
Started Mar 12 02:46:07 PM PDT 24
Finished Mar 12 02:46:08 PM PDT 24
Peak memory 218392 kb
Host smart-ec54882f-c645-47b8-b830-0615d84ccb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261027334 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.edn_genbits.4261027334
Directory /workspace/132.edn_genbits/latest

Test location /workspace/coverage/default/133.edn_genbits.1182170626
Short name T741
Test name
Test status
Simulation time 47579672 ps
CPU time 1.33 seconds
Started Mar 12 02:46:08 PM PDT 24
Finished Mar 12 02:46:09 PM PDT 24
Peak memory 215568 kb
Host smart-b1d011c8-33ae-4965-9d2e-d4ce141f735a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182170626 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.edn_genbits.1182170626
Directory /workspace/133.edn_genbits/latest

Test location /workspace/coverage/default/134.edn_genbits.2843865481
Short name T689
Test name
Test status
Simulation time 56502943 ps
CPU time 1.49 seconds
Started Mar 12 02:46:06 PM PDT 24
Finished Mar 12 02:46:08 PM PDT 24
Peak memory 217136 kb
Host smart-0ce576bd-5714-43d5-837c-5be327171a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843865481 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.edn_genbits.2843865481
Directory /workspace/134.edn_genbits/latest

Test location /workspace/coverage/default/135.edn_genbits.1479189103
Short name T583
Test name
Test status
Simulation time 60811192 ps
CPU time 1.27 seconds
Started Mar 12 02:46:10 PM PDT 24
Finished Mar 12 02:46:12 PM PDT 24
Peak memory 217516 kb
Host smart-ee2dc3c3-5d88-47ff-ae82-401441895647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479189103 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.edn_genbits.1479189103
Directory /workspace/135.edn_genbits/latest

Test location /workspace/coverage/default/136.edn_genbits.3459224907
Short name T278
Test name
Test status
Simulation time 74543112 ps
CPU time 1.16 seconds
Started Mar 12 02:46:05 PM PDT 24
Finished Mar 12 02:46:07 PM PDT 24
Peak memory 215792 kb
Host smart-72ebcbe6-f001-4574-a0b1-26af1941e884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459224907 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.edn_genbits.3459224907
Directory /workspace/136.edn_genbits/latest

Test location /workspace/coverage/default/137.edn_genbits.1448263523
Short name T292
Test name
Test status
Simulation time 42100271 ps
CPU time 1.37 seconds
Started Mar 12 02:46:06 PM PDT 24
Finished Mar 12 02:46:08 PM PDT 24
Peak memory 218000 kb
Host smart-a50193c6-965b-4372-a7cb-80b9d0b19610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448263523 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.edn_genbits.1448263523
Directory /workspace/137.edn_genbits/latest

Test location /workspace/coverage/default/138.edn_genbits.1036485867
Short name T381
Test name
Test status
Simulation time 63613132 ps
CPU time 1.04 seconds
Started Mar 12 02:46:05 PM PDT 24
Finished Mar 12 02:46:06 PM PDT 24
Peak memory 215696 kb
Host smart-5b7036b5-fbab-4268-aff5-651d76a49f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036485867 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.edn_genbits.1036485867
Directory /workspace/138.edn_genbits/latest

Test location /workspace/coverage/default/139.edn_genbits.1226719024
Short name T536
Test name
Test status
Simulation time 40191309 ps
CPU time 1.63 seconds
Started Mar 12 02:46:05 PM PDT 24
Finished Mar 12 02:46:07 PM PDT 24
Peak memory 216888 kb
Host smart-6b06dc3d-c18b-43af-8dbd-d275834a0b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226719024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.edn_genbits.1226719024
Directory /workspace/139.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_alert.740312327
Short name T48
Test name
Test status
Simulation time 48969753 ps
CPU time 1.1 seconds
Started Mar 12 02:43:54 PM PDT 24
Finished Mar 12 02:43:57 PM PDT 24
Peak memory 214696 kb
Host smart-9f6e8d4c-c2ff-4b0f-a955-046ad9b83158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740312327 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert.740312327
Directory /workspace/14.edn_alert/latest

Test location /workspace/coverage/default/14.edn_alert_test.3698159439
Short name T373
Test name
Test status
Simulation time 161011154 ps
CPU time 0.98 seconds
Started Mar 12 02:43:57 PM PDT 24
Finished Mar 12 02:44:00 PM PDT 24
Peak memory 205676 kb
Host smart-b8c7cd74-2c96-49b8-929a-48828b5ce7d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698159439 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_alert_test.3698159439
Directory /workspace/14.edn_alert_test/latest

Test location /workspace/coverage/default/14.edn_disable.3154926465
Short name T181
Test name
Test status
Simulation time 22381271 ps
CPU time 0.9 seconds
Started Mar 12 02:43:57 PM PDT 24
Finished Mar 12 02:43:59 PM PDT 24
Peak memory 215084 kb
Host smart-386bfea1-f02a-4c94-9648-f8fa78a96e83
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154926465 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_disable.3154926465
Directory /workspace/14.edn_disable/latest

Test location /workspace/coverage/default/14.edn_disable_auto_req_mode.2465989898
Short name T773
Test name
Test status
Simulation time 22993940 ps
CPU time 0.93 seconds
Started Mar 12 02:43:57 PM PDT 24
Finished Mar 12 02:44:00 PM PDT 24
Peak memory 216544 kb
Host smart-d745da9c-3704-4bf1-a7ca-3b57cb0b5626
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465989898 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_d
isable_auto_req_mode.2465989898
Directory /workspace/14.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/14.edn_err.2471895789
Short name T115
Test name
Test status
Simulation time 18682369 ps
CPU time 1.19 seconds
Started Mar 12 02:43:58 PM PDT 24
Finished Mar 12 02:44:00 PM PDT 24
Peak memory 222412 kb
Host smart-fe55a03f-4c86-496a-ab8e-81daea4530ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471895789 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_err.2471895789
Directory /workspace/14.edn_err/latest

Test location /workspace/coverage/default/14.edn_genbits.3945509225
Short name T690
Test name
Test status
Simulation time 86446858 ps
CPU time 1.12 seconds
Started Mar 12 02:43:49 PM PDT 24
Finished Mar 12 02:43:50 PM PDT 24
Peak memory 215880 kb
Host smart-44bbced5-4ae4-48e4-88a9-888dbbe17980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945509225 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_genbits.3945509225
Directory /workspace/14.edn_genbits/latest

Test location /workspace/coverage/default/14.edn_intr.3386564901
Short name T432
Test name
Test status
Simulation time 21643259 ps
CPU time 1.06 seconds
Started Mar 12 02:43:49 PM PDT 24
Finished Mar 12 02:43:50 PM PDT 24
Peak memory 214836 kb
Host smart-77388b27-5c8e-471a-ae52-71592166a5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386564901 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_intr.3386564901
Directory /workspace/14.edn_intr/latest

Test location /workspace/coverage/default/14.edn_smoke.2821547086
Short name T655
Test name
Test status
Simulation time 33268764 ps
CPU time 0.88 seconds
Started Mar 12 02:43:49 PM PDT 24
Finished Mar 12 02:43:50 PM PDT 24
Peak memory 214436 kb
Host smart-a7442d36-d891-4cc6-9e83-2163996d2ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821547086 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_smoke.2821547086
Directory /workspace/14.edn_smoke/latest

Test location /workspace/coverage/default/14.edn_stress_all.1599883114
Short name T356
Test name
Test status
Simulation time 70757873 ps
CPU time 1.26 seconds
Started Mar 12 02:43:51 PM PDT 24
Finished Mar 12 02:43:54 PM PDT 24
Peak memory 214400 kb
Host smart-ca623840-3c49-40f3-8940-8fd323569772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599883114 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.edn_stress_all.1599883114
Directory /workspace/14.edn_stress_all/latest

Test location /workspace/coverage/default/141.edn_genbits.35183342
Short name T673
Test name
Test status
Simulation time 360089012 ps
CPU time 4.48 seconds
Started Mar 12 02:46:08 PM PDT 24
Finished Mar 12 02:46:13 PM PDT 24
Peak memory 217864 kb
Host smart-9bc545bb-e3e3-4787-b8a8-ff073f245bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35183342 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.edn_genbits.35183342
Directory /workspace/141.edn_genbits/latest

Test location /workspace/coverage/default/142.edn_genbits.3542491924
Short name T796
Test name
Test status
Simulation time 66188105 ps
CPU time 1.38 seconds
Started Mar 12 02:46:06 PM PDT 24
Finished Mar 12 02:46:07 PM PDT 24
Peak memory 217096 kb
Host smart-63badced-dbd8-43e8-9339-e1d82c476548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542491924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.edn_genbits.3542491924
Directory /workspace/142.edn_genbits/latest

Test location /workspace/coverage/default/143.edn_genbits.2777592902
Short name T521
Test name
Test status
Simulation time 34991674 ps
CPU time 1.37 seconds
Started Mar 12 02:46:06 PM PDT 24
Finished Mar 12 02:46:08 PM PDT 24
Peak memory 215708 kb
Host smart-6bb1a4d9-dca1-442a-955d-05bac285a994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777592902 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.edn_genbits.2777592902
Directory /workspace/143.edn_genbits/latest

Test location /workspace/coverage/default/145.edn_genbits.3700122691
Short name T435
Test name
Test status
Simulation time 37878536 ps
CPU time 1.42 seconds
Started Mar 12 02:46:06 PM PDT 24
Finished Mar 12 02:46:07 PM PDT 24
Peak memory 217036 kb
Host smart-1baad8db-0633-4b49-8d43-9d5f27af2c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700122691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.edn_genbits.3700122691
Directory /workspace/145.edn_genbits/latest

Test location /workspace/coverage/default/146.edn_genbits.810899388
Short name T836
Test name
Test status
Simulation time 184260116 ps
CPU time 1 seconds
Started Mar 12 02:46:04 PM PDT 24
Finished Mar 12 02:46:05 PM PDT 24
Peak memory 215796 kb
Host smart-f567575d-9f8e-41a6-a0d3-89039c52657f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810899388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.edn_genbits.810899388
Directory /workspace/146.edn_genbits/latest

Test location /workspace/coverage/default/147.edn_genbits.58304835
Short name T620
Test name
Test status
Simulation time 28331172 ps
CPU time 1.21 seconds
Started Mar 12 02:46:08 PM PDT 24
Finished Mar 12 02:46:10 PM PDT 24
Peak memory 215860 kb
Host smart-310a4f3b-98e6-4d2b-9827-f1cb0fb04d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58304835 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.edn_genbits.58304835
Directory /workspace/147.edn_genbits/latest

Test location /workspace/coverage/default/148.edn_genbits.3926544387
Short name T800
Test name
Test status
Simulation time 54375164 ps
CPU time 1.38 seconds
Started Mar 12 02:46:08 PM PDT 24
Finished Mar 12 02:46:09 PM PDT 24
Peak memory 216832 kb
Host smart-1b909a0a-3864-494a-a3a3-99e20b4da868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926544387 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.edn_genbits.3926544387
Directory /workspace/148.edn_genbits/latest

Test location /workspace/coverage/default/149.edn_genbits.829824844
Short name T282
Test name
Test status
Simulation time 80259568 ps
CPU time 2.94 seconds
Started Mar 12 02:46:08 PM PDT 24
Finished Mar 12 02:46:12 PM PDT 24
Peak memory 218480 kb
Host smart-05a6382a-5f2d-4801-97df-8a3f9497322a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829824844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.edn_genbits.829824844
Directory /workspace/149.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_alert.3583958538
Short name T649
Test name
Test status
Simulation time 29728334 ps
CPU time 1.22 seconds
Started Mar 12 02:43:56 PM PDT 24
Finished Mar 12 02:44:00 PM PDT 24
Peak memory 214848 kb
Host smart-50134736-4176-4b6d-b8b4-38b5823eec7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583958538 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_alert.3583958538
Directory /workspace/15.edn_alert/latest

Test location /workspace/coverage/default/15.edn_disable.3265683690
Short name T825
Test name
Test status
Simulation time 23343508 ps
CPU time 0.9 seconds
Started Mar 12 02:43:57 PM PDT 24
Finished Mar 12 02:44:00 PM PDT 24
Peak memory 214660 kb
Host smart-7ebc5399-5f3f-42bd-86bd-e88847883f58
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265683690 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_disable.3265683690
Directory /workspace/15.edn_disable/latest

Test location /workspace/coverage/default/15.edn_err.2956395101
Short name T79
Test name
Test status
Simulation time 34799674 ps
CPU time 1.05 seconds
Started Mar 12 02:43:59 PM PDT 24
Finished Mar 12 02:44:00 PM PDT 24
Peak memory 228916 kb
Host smart-924c160b-5c7c-4073-8383-d7b3697f9b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956395101 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_err.2956395101
Directory /workspace/15.edn_err/latest

Test location /workspace/coverage/default/15.edn_genbits.2776462796
Short name T817
Test name
Test status
Simulation time 58664220 ps
CPU time 2.21 seconds
Started Mar 12 02:43:57 PM PDT 24
Finished Mar 12 02:44:01 PM PDT 24
Peak memory 218620 kb
Host smart-915d7171-e55b-4d55-a1bd-4a2c4bb4d2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776462796 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_genbits.2776462796
Directory /workspace/15.edn_genbits/latest

Test location /workspace/coverage/default/15.edn_intr.752904002
Short name T429
Test name
Test status
Simulation time 25281898 ps
CPU time 0.94 seconds
Started Mar 12 02:43:57 PM PDT 24
Finished Mar 12 02:44:00 PM PDT 24
Peak memory 214496 kb
Host smart-1c5696c2-8cc4-41a2-a0b1-1f685642dd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752904002 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_intr.752904002
Directory /workspace/15.edn_intr/latest

Test location /workspace/coverage/default/15.edn_smoke.3427444719
Short name T327
Test name
Test status
Simulation time 36575711 ps
CPU time 0.86 seconds
Started Mar 12 02:43:55 PM PDT 24
Finished Mar 12 02:43:56 PM PDT 24
Peak memory 214468 kb
Host smart-6f6936b7-fdc6-4c68-a403-bf87945be320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427444719 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_smoke.3427444719
Directory /workspace/15.edn_smoke/latest

Test location /workspace/coverage/default/15.edn_stress_all.1058141208
Short name T644
Test name
Test status
Simulation time 85096373 ps
CPU time 1.5 seconds
Started Mar 12 02:43:55 PM PDT 24
Finished Mar 12 02:43:58 PM PDT 24
Peak memory 215720 kb
Host smart-87d1ca0b-64d2-4fee-be7a-a01a46a969bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058141208 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.edn_stress_all.1058141208
Directory /workspace/15.edn_stress_all/latest

Test location /workspace/coverage/default/15.edn_stress_all_with_rand_reset.1973325194
Short name T190
Test name
Test status
Simulation time 88408540444 ps
CPU time 1060.57 seconds
Started Mar 12 02:43:57 PM PDT 24
Finished Mar 12 03:01:39 PM PDT 24
Peak memory 221136 kb
Host smart-222c257d-a63a-4e34-a32a-62b1fc47d39c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973325194 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.edn_stress_all_with_rand_reset.1973325194
Directory /workspace/15.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/152.edn_genbits.2826121332
Short name T527
Test name
Test status
Simulation time 42521174 ps
CPU time 1.61 seconds
Started Mar 12 02:46:04 PM PDT 24
Finished Mar 12 02:46:06 PM PDT 24
Peak memory 216952 kb
Host smart-bfd9fad0-32f7-4d7e-b7a1-ca35f95ea44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826121332 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.edn_genbits.2826121332
Directory /workspace/152.edn_genbits/latest

Test location /workspace/coverage/default/153.edn_genbits.3211482385
Short name T755
Test name
Test status
Simulation time 78913699 ps
CPU time 2.52 seconds
Started Mar 12 02:46:08 PM PDT 24
Finished Mar 12 02:46:11 PM PDT 24
Peak memory 217888 kb
Host smart-bf500acb-ccdf-4bd9-b3ab-49490bd94bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211482385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.edn_genbits.3211482385
Directory /workspace/153.edn_genbits/latest

Test location /workspace/coverage/default/154.edn_genbits.375214238
Short name T452
Test name
Test status
Simulation time 81232529 ps
CPU time 2.9 seconds
Started Mar 12 02:46:06 PM PDT 24
Finished Mar 12 02:46:09 PM PDT 24
Peak memory 216892 kb
Host smart-9958b021-8746-4a7f-8501-17e05b3dccb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375214238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.edn_genbits.375214238
Directory /workspace/154.edn_genbits/latest

Test location /workspace/coverage/default/155.edn_genbits.3723896868
Short name T455
Test name
Test status
Simulation time 27064496 ps
CPU time 1.38 seconds
Started Mar 12 02:46:06 PM PDT 24
Finished Mar 12 02:46:08 PM PDT 24
Peak memory 217212 kb
Host smart-0aa92fdf-55aa-4935-b355-c48153d15bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723896868 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.edn_genbits.3723896868
Directory /workspace/155.edn_genbits/latest

Test location /workspace/coverage/default/156.edn_genbits.3793828640
Short name T466
Test name
Test status
Simulation time 32249242 ps
CPU time 1.28 seconds
Started Mar 12 02:46:07 PM PDT 24
Finished Mar 12 02:46:09 PM PDT 24
Peak memory 216812 kb
Host smart-e69dd8c2-8993-4b0e-8255-6c5fd0101fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793828640 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.edn_genbits.3793828640
Directory /workspace/156.edn_genbits/latest

Test location /workspace/coverage/default/157.edn_genbits.3746781213
Short name T274
Test name
Test status
Simulation time 42930602 ps
CPU time 1.49 seconds
Started Mar 12 02:46:10 PM PDT 24
Finished Mar 12 02:46:12 PM PDT 24
Peak memory 214396 kb
Host smart-33be6646-a7c8-4132-85a3-13e143b0d353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746781213 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.edn_genbits.3746781213
Directory /workspace/157.edn_genbits/latest

Test location /workspace/coverage/default/158.edn_genbits.3621708757
Short name T289
Test name
Test status
Simulation time 100907027 ps
CPU time 1.22 seconds
Started Mar 12 02:46:04 PM PDT 24
Finished Mar 12 02:46:06 PM PDT 24
Peak memory 215904 kb
Host smart-1c4bd854-795f-452e-9a26-391c8b1a81f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621708757 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.edn_genbits.3621708757
Directory /workspace/158.edn_genbits/latest

Test location /workspace/coverage/default/159.edn_genbits.2376583678
Short name T633
Test name
Test status
Simulation time 378427097 ps
CPU time 1.67 seconds
Started Mar 12 02:46:18 PM PDT 24
Finished Mar 12 02:46:20 PM PDT 24
Peak memory 215968 kb
Host smart-f14999de-e8d6-40da-ba92-e35c3f5360e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376583678 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.edn_genbits.2376583678
Directory /workspace/159.edn_genbits/latest

Test location /workspace/coverage/default/16.edn_alert.1490962778
Short name T498
Test name
Test status
Simulation time 87994572 ps
CPU time 1.17 seconds
Started Mar 12 02:43:57 PM PDT 24
Finished Mar 12 02:44:00 PM PDT 24
Peak memory 214776 kb
Host smart-4ddb24fa-5c57-4644-a48e-fc9c58398f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490962778 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert.1490962778
Directory /workspace/16.edn_alert/latest

Test location /workspace/coverage/default/16.edn_alert_test.119534763
Short name T558
Test name
Test status
Simulation time 13275267 ps
CPU time 0.9 seconds
Started Mar 12 02:44:09 PM PDT 24
Finished Mar 12 02:44:10 PM PDT 24
Peak memory 206072 kb
Host smart-a43f10bb-0b12-47af-818a-efb80f9f4720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119534763 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_alert_test.119534763
Directory /workspace/16.edn_alert_test/latest

Test location /workspace/coverage/default/16.edn_disable.3163359183
Short name T623
Test name
Test status
Simulation time 13570924 ps
CPU time 0.94 seconds
Started Mar 12 02:44:05 PM PDT 24
Finished Mar 12 02:44:06 PM PDT 24
Peak memory 215032 kb
Host smart-4dc66a15-e8bd-43e9-90da-5b138d2354d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163359183 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_disable.3163359183
Directory /workspace/16.edn_disable/latest

Test location /workspace/coverage/default/16.edn_err.1789798621
Short name T712
Test name
Test status
Simulation time 29097100 ps
CPU time 0.88 seconds
Started Mar 12 02:44:07 PM PDT 24
Finished Mar 12 02:44:08 PM PDT 24
Peak memory 216944 kb
Host smart-df28258a-137a-49d5-b54c-007188031679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789798621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_err.1789798621
Directory /workspace/16.edn_err/latest

Test location /workspace/coverage/default/16.edn_intr.2697213160
Short name T66
Test name
Test status
Simulation time 22796008 ps
CPU time 1.08 seconds
Started Mar 12 02:43:56 PM PDT 24
Finished Mar 12 02:44:00 PM PDT 24
Peak memory 214816 kb
Host smart-3938d9f5-c913-47e3-8e1b-5dd950560232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697213160 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_intr.2697213160
Directory /workspace/16.edn_intr/latest

Test location /workspace/coverage/default/16.edn_smoke.4274251610
Short name T563
Test name
Test status
Simulation time 30672938 ps
CPU time 0.9 seconds
Started Mar 12 02:43:57 PM PDT 24
Finished Mar 12 02:44:00 PM PDT 24
Peak memory 214484 kb
Host smart-75751d46-74d7-4a51-a01d-14fedb623c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274251610 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_smoke.4274251610
Directory /workspace/16.edn_smoke/latest

Test location /workspace/coverage/default/16.edn_stress_all.2063794645
Short name T626
Test name
Test status
Simulation time 359476324 ps
CPU time 2.54 seconds
Started Mar 12 02:43:56 PM PDT 24
Finished Mar 12 02:44:00 PM PDT 24
Peak memory 214488 kb
Host smart-6110a58c-1a8c-4dac-a759-0b0ee99a6a81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063794645 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.edn_stress_all.2063794645
Directory /workspace/16.edn_stress_all/latest

Test location /workspace/coverage/default/16.edn_stress_all_with_rand_reset.3900084321
Short name T759
Test name
Test status
Simulation time 1081405313557 ps
CPU time 2337.62 seconds
Started Mar 12 02:43:56 PM PDT 24
Finished Mar 12 03:22:57 PM PDT 24
Peak memory 228176 kb
Host smart-19f86ebb-160e-48c6-a485-a6942d60aff4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900084321 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 16.edn_stress_all_with_rand_reset.3900084321
Directory /workspace/16.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.edn_genbits.285689190
Short name T375
Test name
Test status
Simulation time 162140053 ps
CPU time 1.12 seconds
Started Mar 12 02:46:19 PM PDT 24
Finished Mar 12 02:46:20 PM PDT 24
Peak memory 215556 kb
Host smart-d3c729f9-d598-418f-bc67-e8d14a42c97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285689190 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.edn_genbits.285689190
Directory /workspace/160.edn_genbits/latest

Test location /workspace/coverage/default/161.edn_genbits.2899344736
Short name T347
Test name
Test status
Simulation time 270756083 ps
CPU time 1.35 seconds
Started Mar 12 02:46:15 PM PDT 24
Finished Mar 12 02:46:16 PM PDT 24
Peak memory 217160 kb
Host smart-bf840024-138b-4750-bfc7-c73e3170807c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899344736 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.edn_genbits.2899344736
Directory /workspace/161.edn_genbits/latest

Test location /workspace/coverage/default/163.edn_genbits.2509209672
Short name T305
Test name
Test status
Simulation time 47324332 ps
CPU time 1.69 seconds
Started Mar 12 02:46:17 PM PDT 24
Finished Mar 12 02:46:18 PM PDT 24
Peak memory 216700 kb
Host smart-d30d61aa-d8cd-41b3-83ef-40682d1be4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509209672 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.edn_genbits.2509209672
Directory /workspace/163.edn_genbits/latest

Test location /workspace/coverage/default/164.edn_genbits.4141460632
Short name T823
Test name
Test status
Simulation time 37883368 ps
CPU time 1.42 seconds
Started Mar 12 02:46:17 PM PDT 24
Finished Mar 12 02:46:18 PM PDT 24
Peak memory 216680 kb
Host smart-0a18b743-7d9b-431b-bf9f-b8007f62486a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141460632 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.edn_genbits.4141460632
Directory /workspace/164.edn_genbits/latest

Test location /workspace/coverage/default/166.edn_genbits.485852720
Short name T448
Test name
Test status
Simulation time 40052034 ps
CPU time 1.4 seconds
Started Mar 12 02:46:15 PM PDT 24
Finished Mar 12 02:46:16 PM PDT 24
Peak memory 214484 kb
Host smart-a47f9d14-aedc-40dd-933b-6a1c307db74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485852720 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.edn_genbits.485852720
Directory /workspace/166.edn_genbits/latest

Test location /workspace/coverage/default/167.edn_genbits.3492721856
Short name T827
Test name
Test status
Simulation time 273347833 ps
CPU time 2.11 seconds
Started Mar 12 02:46:14 PM PDT 24
Finished Mar 12 02:46:16 PM PDT 24
Peak memory 217320 kb
Host smart-a44bcf2c-968c-4bd9-a51c-e94677164b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492721856 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.edn_genbits.3492721856
Directory /workspace/167.edn_genbits/latest

Test location /workspace/coverage/default/168.edn_genbits.463612309
Short name T611
Test name
Test status
Simulation time 59701227 ps
CPU time 1.48 seconds
Started Mar 12 02:46:16 PM PDT 24
Finished Mar 12 02:46:18 PM PDT 24
Peak memory 216840 kb
Host smart-9f4b6b20-f579-45cf-a5ce-97eb93fbd526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463612309 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.edn_genbits.463612309
Directory /workspace/168.edn_genbits/latest

Test location /workspace/coverage/default/169.edn_genbits.536965390
Short name T322
Test name
Test status
Simulation time 36130650 ps
CPU time 1.66 seconds
Started Mar 12 02:46:16 PM PDT 24
Finished Mar 12 02:46:18 PM PDT 24
Peak memory 216792 kb
Host smart-130e73e7-cd17-4eb5-a555-80f65a80d005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536965390 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.edn_genbits.536965390
Directory /workspace/169.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_alert.3077190324
Short name T607
Test name
Test status
Simulation time 132242606 ps
CPU time 1.19 seconds
Started Mar 12 02:44:06 PM PDT 24
Finished Mar 12 02:44:07 PM PDT 24
Peak memory 214832 kb
Host smart-eee15010-3144-4249-85fe-a6fce8290058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077190324 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert.3077190324
Directory /workspace/17.edn_alert/latest

Test location /workspace/coverage/default/17.edn_alert_test.662169658
Short name T634
Test name
Test status
Simulation time 53656871 ps
CPU time 0.97 seconds
Started Mar 12 02:44:05 PM PDT 24
Finished Mar 12 02:44:06 PM PDT 24
Peak memory 206060 kb
Host smart-2ef5a320-6517-42ef-a4af-cc0494f29882
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662169658 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_alert_test.662169658
Directory /workspace/17.edn_alert_test/latest

Test location /workspace/coverage/default/17.edn_disable.666321627
Short name T692
Test name
Test status
Simulation time 25196954 ps
CPU time 0.96 seconds
Started Mar 12 02:44:04 PM PDT 24
Finished Mar 12 02:44:05 PM PDT 24
Peak memory 214896 kb
Host smart-8db85d24-76c8-4e95-bb93-e9afcf69c806
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666321627 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_disable.666321627
Directory /workspace/17.edn_disable/latest

Test location /workspace/coverage/default/17.edn_disable_auto_req_mode.27133236
Short name T629
Test name
Test status
Simulation time 33689184 ps
CPU time 1.07 seconds
Started Mar 12 02:44:03 PM PDT 24
Finished Mar 12 02:44:04 PM PDT 24
Peak memory 215336 kb
Host smart-4968d5eb-176f-4ca6-9ca6-bcd27493aea0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27133236 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_disa
ble_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_dis
able_auto_req_mode.27133236
Directory /workspace/17.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/17.edn_err.964116287
Short name T589
Test name
Test status
Simulation time 25152622 ps
CPU time 1.02 seconds
Started Mar 12 02:44:07 PM PDT 24
Finished Mar 12 02:44:08 PM PDT 24
Peak memory 222280 kb
Host smart-1176247a-0483-4d49-a219-f718a6237f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964116287 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_err.964116287
Directory /workspace/17.edn_err/latest

Test location /workspace/coverage/default/17.edn_genbits.2583638515
Short name T453
Test name
Test status
Simulation time 75807995 ps
CPU time 1.14 seconds
Started Mar 12 02:44:05 PM PDT 24
Finished Mar 12 02:44:06 PM PDT 24
Peak memory 215664 kb
Host smart-cfdec220-6cb0-4c38-85ca-37ced35345c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583638515 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_genbits.2583638515
Directory /workspace/17.edn_genbits/latest

Test location /workspace/coverage/default/17.edn_intr.1694390284
Short name T1
Test name
Test status
Simulation time 26871145 ps
CPU time 0.95 seconds
Started Mar 12 02:44:07 PM PDT 24
Finished Mar 12 02:44:09 PM PDT 24
Peak memory 214828 kb
Host smart-93c4777d-e9ad-4f3f-bf67-2feb5f710e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694390284 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_intr.1694390284
Directory /workspace/17.edn_intr/latest

Test location /workspace/coverage/default/17.edn_smoke.2176771225
Short name T722
Test name
Test status
Simulation time 16375288 ps
CPU time 1.02 seconds
Started Mar 12 02:44:07 PM PDT 24
Finished Mar 12 02:44:08 PM PDT 24
Peak memory 214460 kb
Host smart-31053f06-3933-4e72-bc64-6483e3151835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176771225 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_smoke.2176771225
Directory /workspace/17.edn_smoke/latest

Test location /workspace/coverage/default/17.edn_stress_all.3574302759
Short name T279
Test name
Test status
Simulation time 240421623 ps
CPU time 4.89 seconds
Started Mar 12 02:44:04 PM PDT 24
Finished Mar 12 02:44:09 PM PDT 24
Peak memory 216976 kb
Host smart-191172a4-a25a-42c9-9733-82ca968ec9d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574302759 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.edn_stress_all.3574302759
Directory /workspace/17.edn_stress_all/latest

Test location /workspace/coverage/default/17.edn_stress_all_with_rand_reset.3156287005
Short name T554
Test name
Test status
Simulation time 729271982923 ps
CPU time 1451.64 seconds
Started Mar 12 02:44:06 PM PDT 24
Finished Mar 12 03:08:18 PM PDT 24
Peak memory 224068 kb
Host smart-a72bbac3-2433-4d22-a461-c5362cd6b597
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156287005 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.edn_stress_all_with_rand_reset.3156287005
Directory /workspace/17.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.edn_genbits.1561055783
Short name T320
Test name
Test status
Simulation time 49394294 ps
CPU time 1.86 seconds
Started Mar 12 02:46:15 PM PDT 24
Finished Mar 12 02:46:17 PM PDT 24
Peak memory 217124 kb
Host smart-264503b8-1560-485b-bacf-fd5407ae5463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561055783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.edn_genbits.1561055783
Directory /workspace/170.edn_genbits/latest

Test location /workspace/coverage/default/171.edn_genbits.1991093837
Short name T829
Test name
Test status
Simulation time 263643865 ps
CPU time 3.07 seconds
Started Mar 12 02:46:13 PM PDT 24
Finished Mar 12 02:46:16 PM PDT 24
Peak memory 218980 kb
Host smart-e5a2ccc4-27c3-40dc-9491-ae605b3b0984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991093837 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.edn_genbits.1991093837
Directory /workspace/171.edn_genbits/latest

Test location /workspace/coverage/default/172.edn_genbits.3253973471
Short name T496
Test name
Test status
Simulation time 181287537 ps
CPU time 1.33 seconds
Started Mar 12 02:46:16 PM PDT 24
Finished Mar 12 02:46:18 PM PDT 24
Peak memory 215796 kb
Host smart-1a802715-c837-4095-b50f-74aa3d890cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253973471 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.edn_genbits.3253973471
Directory /workspace/172.edn_genbits/latest

Test location /workspace/coverage/default/173.edn_genbits.2786503530
Short name T376
Test name
Test status
Simulation time 36743053 ps
CPU time 1.24 seconds
Started Mar 12 02:46:19 PM PDT 24
Finished Mar 12 02:46:21 PM PDT 24
Peak memory 216956 kb
Host smart-07d6c4bb-86b8-41b7-aad5-c814a3bb77c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786503530 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.edn_genbits.2786503530
Directory /workspace/173.edn_genbits/latest

Test location /workspace/coverage/default/174.edn_genbits.2166362517
Short name T494
Test name
Test status
Simulation time 54525343 ps
CPU time 1.42 seconds
Started Mar 12 02:46:15 PM PDT 24
Finished Mar 12 02:46:16 PM PDT 24
Peak memory 217008 kb
Host smart-3054438f-2b1b-4a27-8d7e-e5af2c98afb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166362517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.edn_genbits.2166362517
Directory /workspace/174.edn_genbits/latest

Test location /workspace/coverage/default/175.edn_genbits.1400659839
Short name T631
Test name
Test status
Simulation time 123230324 ps
CPU time 1.3 seconds
Started Mar 12 02:46:16 PM PDT 24
Finished Mar 12 02:46:17 PM PDT 24
Peak memory 215604 kb
Host smart-30515ced-4a8a-451b-8be7-a17c8932b3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400659839 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.edn_genbits.1400659839
Directory /workspace/175.edn_genbits/latest

Test location /workspace/coverage/default/176.edn_genbits.1985569417
Short name T304
Test name
Test status
Simulation time 58165835 ps
CPU time 1.2 seconds
Started Mar 12 02:46:14 PM PDT 24
Finished Mar 12 02:46:16 PM PDT 24
Peak memory 215708 kb
Host smart-db98a20d-df5b-43bd-8255-7c12ccca15e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985569417 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.edn_genbits.1985569417
Directory /workspace/176.edn_genbits/latest

Test location /workspace/coverage/default/177.edn_genbits.702288905
Short name T595
Test name
Test status
Simulation time 47982529 ps
CPU time 1.73 seconds
Started Mar 12 02:46:14 PM PDT 24
Finished Mar 12 02:46:16 PM PDT 24
Peak memory 216788 kb
Host smart-41033272-16e3-46a0-a33e-ff2340986073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702288905 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.edn_genbits.702288905
Directory /workspace/177.edn_genbits/latest

Test location /workspace/coverage/default/178.edn_genbits.3641704759
Short name T332
Test name
Test status
Simulation time 51801149 ps
CPU time 1.17 seconds
Started Mar 12 02:46:12 PM PDT 24
Finished Mar 12 02:46:14 PM PDT 24
Peak memory 216924 kb
Host smart-f97f4f45-8f93-4941-a8c3-f2f9dd913fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641704759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.edn_genbits.3641704759
Directory /workspace/178.edn_genbits/latest

Test location /workspace/coverage/default/179.edn_genbits.2279403673
Short name T269
Test name
Test status
Simulation time 69990108 ps
CPU time 1.05 seconds
Started Mar 12 02:46:15 PM PDT 24
Finished Mar 12 02:46:16 PM PDT 24
Peak memory 214548 kb
Host smart-aac29714-a323-4b82-b189-1fd565917b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279403673 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.edn_genbits.2279403673
Directory /workspace/179.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_alert.1602337194
Short name T124
Test name
Test status
Simulation time 77075499 ps
CPU time 1.25 seconds
Started Mar 12 02:44:04 PM PDT 24
Finished Mar 12 02:44:05 PM PDT 24
Peak memory 214836 kb
Host smart-129506d4-9084-4ca0-9ff3-6e97650df32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602337194 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert.1602337194
Directory /workspace/18.edn_alert/latest

Test location /workspace/coverage/default/18.edn_alert_test.2059124229
Short name T766
Test name
Test status
Simulation time 13034862 ps
CPU time 0.92 seconds
Started Mar 12 02:44:08 PM PDT 24
Finished Mar 12 02:44:09 PM PDT 24
Peak memory 206028 kb
Host smart-e7d425d5-0720-47fa-8038-aefba983d7d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059124229 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_alert_test.2059124229
Directory /workspace/18.edn_alert_test/latest

Test location /workspace/coverage/default/18.edn_disable.170567973
Short name T788
Test name
Test status
Simulation time 62113060 ps
CPU time 0.81 seconds
Started Mar 12 02:44:06 PM PDT 24
Finished Mar 12 02:44:07 PM PDT 24
Peak memory 214652 kb
Host smart-d1d1439f-fbc8-474b-9f2e-969073c4c786
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170567973 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_disable.170567973
Directory /workspace/18.edn_disable/latest

Test location /workspace/coverage/default/18.edn_disable_auto_req_mode.4187399044
Short name T77
Test name
Test status
Simulation time 74738122 ps
CPU time 1.41 seconds
Started Mar 12 02:44:06 PM PDT 24
Finished Mar 12 02:44:07 PM PDT 24
Peak memory 215580 kb
Host smart-c82bb60c-3410-49ff-bc01-3eaf7afa65ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187399044 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_d
isable_auto_req_mode.4187399044
Directory /workspace/18.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/18.edn_err.859747219
Short name T169
Test name
Test status
Simulation time 64904850 ps
CPU time 0.83 seconds
Started Mar 12 02:44:06 PM PDT 24
Finished Mar 12 02:44:07 PM PDT 24
Peak memory 216984 kb
Host smart-d935d61e-b3aa-4b9d-b1c3-5db1bece6256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859747219 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_err.859747219
Directory /workspace/18.edn_err/latest

Test location /workspace/coverage/default/18.edn_genbits.3305390298
Short name T731
Test name
Test status
Simulation time 49671969 ps
CPU time 1.58 seconds
Started Mar 12 02:44:06 PM PDT 24
Finished Mar 12 02:44:07 PM PDT 24
Peak memory 217520 kb
Host smart-d7bd213b-cdfe-4e34-99cd-68b2b3c7def4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305390298 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_genbits.3305390298
Directory /workspace/18.edn_genbits/latest

Test location /workspace/coverage/default/18.edn_smoke.3369633977
Short name T337
Test name
Test status
Simulation time 72718640 ps
CPU time 0.97 seconds
Started Mar 12 02:44:09 PM PDT 24
Finished Mar 12 02:44:10 PM PDT 24
Peak memory 214448 kb
Host smart-bab55ef4-686b-40bd-8891-a8c171bec670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369633977 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_smoke.3369633977
Directory /workspace/18.edn_smoke/latest

Test location /workspace/coverage/default/18.edn_stress_all.2374719092
Short name T372
Test name
Test status
Simulation time 252147359 ps
CPU time 2.83 seconds
Started Mar 12 02:44:05 PM PDT 24
Finished Mar 12 02:44:08 PM PDT 24
Peak memory 206244 kb
Host smart-64e06e3e-213e-4221-b232-16abd2b0a5b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374719092 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.edn_stress_all.2374719092
Directory /workspace/18.edn_stress_all/latest

Test location /workspace/coverage/default/18.edn_stress_all_with_rand_reset.29022059
Short name T814
Test name
Test status
Simulation time 51996906123 ps
CPU time 1121.7 seconds
Started Mar 12 02:44:13 PM PDT 24
Finished Mar 12 03:02:55 PM PDT 24
Peak memory 218272 kb
Host smart-34be2e27-04bc-48be-bd8e-04c65837ca9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29022059 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 18.edn_stress_all_with_rand_reset.29022059
Directory /workspace/18.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.edn_genbits.116999004
Short name T572
Test name
Test status
Simulation time 51859553 ps
CPU time 1.74 seconds
Started Mar 12 02:46:17 PM PDT 24
Finished Mar 12 02:46:19 PM PDT 24
Peak memory 215828 kb
Host smart-0529a28c-8d06-4058-9698-456524ef4fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116999004 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.edn_genbits.116999004
Directory /workspace/180.edn_genbits/latest

Test location /workspace/coverage/default/181.edn_genbits.1328593574
Short name T694
Test name
Test status
Simulation time 57254452 ps
CPU time 1.74 seconds
Started Mar 12 02:46:13 PM PDT 24
Finished Mar 12 02:46:15 PM PDT 24
Peak memory 216740 kb
Host smart-342f247d-320d-4d71-b26f-b13f80d6c8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328593574 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.edn_genbits.1328593574
Directory /workspace/181.edn_genbits/latest

Test location /workspace/coverage/default/182.edn_genbits.263120564
Short name T576
Test name
Test status
Simulation time 108992243 ps
CPU time 1.15 seconds
Started Mar 12 02:46:15 PM PDT 24
Finished Mar 12 02:46:16 PM PDT 24
Peak memory 215880 kb
Host smart-a6a1eabf-c968-48c9-af8a-77242823e7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263120564 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.edn_genbits.263120564
Directory /workspace/182.edn_genbits/latest

Test location /workspace/coverage/default/183.edn_genbits.2001311969
Short name T409
Test name
Test status
Simulation time 48083262 ps
CPU time 1.27 seconds
Started Mar 12 02:46:18 PM PDT 24
Finished Mar 12 02:46:20 PM PDT 24
Peak memory 217932 kb
Host smart-2ef28f59-000d-42b0-8c1c-218794cb27ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001311969 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.edn_genbits.2001311969
Directory /workspace/183.edn_genbits/latest

Test location /workspace/coverage/default/184.edn_genbits.3865183035
Short name T442
Test name
Test status
Simulation time 57420937 ps
CPU time 1.3 seconds
Started Mar 12 02:46:13 PM PDT 24
Finished Mar 12 02:46:15 PM PDT 24
Peak memory 217140 kb
Host smart-123e02f9-ec64-4cf4-b6bd-ad07c9c3c460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865183035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.edn_genbits.3865183035
Directory /workspace/184.edn_genbits/latest

Test location /workspace/coverage/default/185.edn_genbits.42246620
Short name T285
Test name
Test status
Simulation time 67027164 ps
CPU time 1.09 seconds
Started Mar 12 02:46:13 PM PDT 24
Finished Mar 12 02:46:14 PM PDT 24
Peak memory 215768 kb
Host smart-b892bd06-b182-42af-9bb5-d02f7b26c127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42246620 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.edn_genbits.42246620
Directory /workspace/185.edn_genbits/latest

Test location /workspace/coverage/default/186.edn_genbits.223382383
Short name T33
Test name
Test status
Simulation time 55052111 ps
CPU time 1.12 seconds
Started Mar 12 02:46:15 PM PDT 24
Finished Mar 12 02:46:16 PM PDT 24
Peak memory 217208 kb
Host smart-f845f3b2-8ab2-4b95-8e27-fdf3da578b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223382383 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.edn_genbits.223382383
Directory /workspace/186.edn_genbits/latest

Test location /workspace/coverage/default/187.edn_genbits.259780432
Short name T368
Test name
Test status
Simulation time 39339152 ps
CPU time 1.5 seconds
Started Mar 12 02:46:15 PM PDT 24
Finished Mar 12 02:46:16 PM PDT 24
Peak memory 216944 kb
Host smart-2cb45975-4ccd-4149-b489-329b56169f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259780432 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.edn_genbits.259780432
Directory /workspace/187.edn_genbits/latest

Test location /workspace/coverage/default/188.edn_genbits.1872753952
Short name T475
Test name
Test status
Simulation time 23380146 ps
CPU time 1.12 seconds
Started Mar 12 02:46:14 PM PDT 24
Finished Mar 12 02:46:15 PM PDT 24
Peak memory 217056 kb
Host smart-5ab48f44-5cbf-47b3-9bf2-072572927bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872753952 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.edn_genbits.1872753952
Directory /workspace/188.edn_genbits/latest

Test location /workspace/coverage/default/189.edn_genbits.4280766404
Short name T776
Test name
Test status
Simulation time 30256862 ps
CPU time 1.15 seconds
Started Mar 12 02:46:19 PM PDT 24
Finished Mar 12 02:46:20 PM PDT 24
Peak memory 218280 kb
Host smart-fd53f03b-0f85-4d26-aa95-217abbdd3f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280766404 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.edn_genbits.4280766404
Directory /workspace/189.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_alert.2873726712
Short name T832
Test name
Test status
Simulation time 39799419 ps
CPU time 1.15 seconds
Started Mar 12 02:44:14 PM PDT 24
Finished Mar 12 02:44:15 PM PDT 24
Peak memory 214856 kb
Host smart-be4262ab-7fad-4567-bf4d-800e338ceb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873726712 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert.2873726712
Directory /workspace/19.edn_alert/latest

Test location /workspace/coverage/default/19.edn_alert_test.4116951637
Short name T342
Test name
Test status
Simulation time 38524631 ps
CPU time 0.88 seconds
Started Mar 12 02:44:15 PM PDT 24
Finished Mar 12 02:44:16 PM PDT 24
Peak memory 205200 kb
Host smart-c2a7fa74-9c91-4a1e-aef2-343354c532a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116951637 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_alert_test.4116951637
Directory /workspace/19.edn_alert_test/latest

Test location /workspace/coverage/default/19.edn_disable_auto_req_mode.781143165
Short name T185
Test name
Test status
Simulation time 133901125 ps
CPU time 1.08 seconds
Started Mar 12 02:44:15 PM PDT 24
Finished Mar 12 02:44:17 PM PDT 24
Peak memory 215628 kb
Host smart-c9b33439-3518-4e45-886b-20010fe559bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781143165 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_di
sable_auto_req_mode.781143165
Directory /workspace/19.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/19.edn_err.2699363508
Short name T657
Test name
Test status
Simulation time 117745590 ps
CPU time 1.12 seconds
Started Mar 12 02:44:14 PM PDT 24
Finished Mar 12 02:44:15 PM PDT 24
Peak memory 223564 kb
Host smart-db0beddc-f2db-44ec-97b4-cd3cccd920e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699363508 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_err.2699363508
Directory /workspace/19.edn_err/latest

Test location /workspace/coverage/default/19.edn_genbits.3838184024
Short name T581
Test name
Test status
Simulation time 48907657 ps
CPU time 1.1 seconds
Started Mar 12 02:44:14 PM PDT 24
Finished Mar 12 02:44:15 PM PDT 24
Peak memory 215724 kb
Host smart-e0e70646-a0d7-4e92-9296-087f4b15682c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838184024 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_genbits.3838184024
Directory /workspace/19.edn_genbits/latest

Test location /workspace/coverage/default/19.edn_intr.3994347562
Short name T393
Test name
Test status
Simulation time 27390520 ps
CPU time 0.97 seconds
Started Mar 12 02:44:15 PM PDT 24
Finished Mar 12 02:44:16 PM PDT 24
Peak memory 214644 kb
Host smart-dad6abae-e68c-4ea8-9a00-cb3f2812ee04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994347562 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_intr.3994347562
Directory /workspace/19.edn_intr/latest

Test location /workspace/coverage/default/19.edn_smoke.365951242
Short name T301
Test name
Test status
Simulation time 43571208 ps
CPU time 0.87 seconds
Started Mar 12 02:44:05 PM PDT 24
Finished Mar 12 02:44:06 PM PDT 24
Peak memory 214384 kb
Host smart-f2221938-9403-431f-9b06-edb40b18f22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365951242 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_smoke.365951242
Directory /workspace/19.edn_smoke/latest

Test location /workspace/coverage/default/19.edn_stress_all.1359985830
Short name T434
Test name
Test status
Simulation time 97772163 ps
CPU time 1.58 seconds
Started Mar 12 02:44:14 PM PDT 24
Finished Mar 12 02:44:15 PM PDT 24
Peak memory 215696 kb
Host smart-0c0428c4-b36e-4d5c-8788-f3996072e3bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359985830 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.edn_stress_all.1359985830
Directory /workspace/19.edn_stress_all/latest

Test location /workspace/coverage/default/19.edn_stress_all_with_rand_reset.3908320468
Short name T666
Test name
Test status
Simulation time 106692701765 ps
CPU time 1389.2 seconds
Started Mar 12 02:44:13 PM PDT 24
Finished Mar 12 03:07:23 PM PDT 24
Peak memory 224252 kb
Host smart-6db321b6-496f-45bd-b5b6-da041b5a0f92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908320468 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.edn_stress_all_with_rand_reset.3908320468
Directory /workspace/19.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.edn_genbits.1132305167
Short name T582
Test name
Test status
Simulation time 355526086 ps
CPU time 4.17 seconds
Started Mar 12 02:46:14 PM PDT 24
Finished Mar 12 02:46:18 PM PDT 24
Peak memory 217728 kb
Host smart-7f8f2635-6114-412a-a0e2-31a575f9983a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132305167 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.edn_genbits.1132305167
Directory /workspace/190.edn_genbits/latest

Test location /workspace/coverage/default/191.edn_genbits.1144379704
Short name T615
Test name
Test status
Simulation time 36146080 ps
CPU time 1.46 seconds
Started Mar 12 02:46:22 PM PDT 24
Finished Mar 12 02:46:24 PM PDT 24
Peak memory 215836 kb
Host smart-3d3b2bf1-79c2-4766-bc45-cec63784ffa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144379704 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.edn_genbits.1144379704
Directory /workspace/191.edn_genbits/latest

Test location /workspace/coverage/default/192.edn_genbits.2129958609
Short name T176
Test name
Test status
Simulation time 54511304 ps
CPU time 1.29 seconds
Started Mar 12 02:46:23 PM PDT 24
Finished Mar 12 02:46:24 PM PDT 24
Peak memory 215736 kb
Host smart-e3b655e4-498d-4768-b107-f104f05b070a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129958609 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.edn_genbits.2129958609
Directory /workspace/192.edn_genbits/latest

Test location /workspace/coverage/default/193.edn_genbits.3781829644
Short name T397
Test name
Test status
Simulation time 61712682 ps
CPU time 1.78 seconds
Started Mar 12 02:46:22 PM PDT 24
Finished Mar 12 02:46:24 PM PDT 24
Peak memory 216764 kb
Host smart-d06b01d9-3de7-437f-b1ba-9b335b841c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781829644 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.edn_genbits.3781829644
Directory /workspace/193.edn_genbits/latest

Test location /workspace/coverage/default/194.edn_genbits.4152493310
Short name T394
Test name
Test status
Simulation time 123772346 ps
CPU time 2.65 seconds
Started Mar 12 02:46:25 PM PDT 24
Finished Mar 12 02:46:28 PM PDT 24
Peak memory 218736 kb
Host smart-2de5f23e-6093-4814-a419-4f9e99736d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152493310 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.edn_genbits.4152493310
Directory /workspace/194.edn_genbits/latest

Test location /workspace/coverage/default/195.edn_genbits.1116377220
Short name T681
Test name
Test status
Simulation time 70880691 ps
CPU time 1.39 seconds
Started Mar 12 02:46:26 PM PDT 24
Finished Mar 12 02:46:28 PM PDT 24
Peak memory 215656 kb
Host smart-3f64b7f3-94f5-4cb7-a540-22468aaa1a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116377220 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.edn_genbits.1116377220
Directory /workspace/195.edn_genbits/latest

Test location /workspace/coverage/default/196.edn_genbits.1304236536
Short name T476
Test name
Test status
Simulation time 223691770 ps
CPU time 2.21 seconds
Started Mar 12 02:46:27 PM PDT 24
Finished Mar 12 02:46:30 PM PDT 24
Peak memory 215824 kb
Host smart-3b55f2e3-c96c-417c-8d6f-c20d75009046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304236536 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.edn_genbits.1304236536
Directory /workspace/196.edn_genbits/latest

Test location /workspace/coverage/default/197.edn_genbits.1167665677
Short name T462
Test name
Test status
Simulation time 29660127 ps
CPU time 1.4 seconds
Started Mar 12 02:46:27 PM PDT 24
Finished Mar 12 02:46:28 PM PDT 24
Peak memory 216856 kb
Host smart-304be5f8-939c-442a-a516-2571f007e318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167665677 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.edn_genbits.1167665677
Directory /workspace/197.edn_genbits/latest

Test location /workspace/coverage/default/198.edn_genbits.221223278
Short name T603
Test name
Test status
Simulation time 110226705 ps
CPU time 1.24 seconds
Started Mar 12 02:46:21 PM PDT 24
Finished Mar 12 02:46:23 PM PDT 24
Peak memory 218200 kb
Host smart-3b764b67-511d-4a34-9d2c-6ec0f0374b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221223278 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.edn_genbits.221223278
Directory /workspace/198.edn_genbits/latest

Test location /workspace/coverage/default/199.edn_genbits.1167947377
Short name T404
Test name
Test status
Simulation time 51284902 ps
CPU time 2.05 seconds
Started Mar 12 02:46:23 PM PDT 24
Finished Mar 12 02:46:26 PM PDT 24
Peak memory 216916 kb
Host smart-8bdfa8ba-1a9d-4fe3-9d4e-c019aa4e62ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167947377 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.edn_genbits.1167947377
Directory /workspace/199.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_alert.1426366785
Short name T122
Test name
Test status
Simulation time 44053263 ps
CPU time 1.14 seconds
Started Mar 12 02:43:09 PM PDT 24
Finished Mar 12 02:43:10 PM PDT 24
Peak memory 214836 kb
Host smart-f34a403b-a94a-4f03-be4d-af8885036fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426366785 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert.1426366785
Directory /workspace/2.edn_alert/latest

Test location /workspace/coverage/default/2.edn_alert_test.2150179491
Short name T128
Test name
Test status
Simulation time 47044442 ps
CPU time 0.98 seconds
Started Mar 12 02:43:10 PM PDT 24
Finished Mar 12 02:43:11 PM PDT 24
Peak memory 206104 kb
Host smart-03e20702-59c2-4f92-9dab-19cfed8695f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150179491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_alert_test.2150179491
Directory /workspace/2.edn_alert_test/latest

Test location /workspace/coverage/default/2.edn_disable_auto_req_mode.3101226906
Short name T700
Test name
Test status
Simulation time 20251017 ps
CPU time 1.02 seconds
Started Mar 12 02:43:11 PM PDT 24
Finished Mar 12 02:43:12 PM PDT 24
Peak memory 215456 kb
Host smart-794318d7-05d0-4ac3-b81b-fc18d20d6e01
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101226906 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_di
sable_auto_req_mode.3101226906
Directory /workspace/2.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/2.edn_err.1780979668
Short name T42
Test name
Test status
Simulation time 66860728 ps
CPU time 0.93 seconds
Started Mar 12 02:43:11 PM PDT 24
Finished Mar 12 02:43:13 PM PDT 24
Peak memory 222316 kb
Host smart-6c0cc360-9ef4-4601-809d-27dd83a82400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780979668 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_err.1780979668
Directory /workspace/2.edn_err/latest

Test location /workspace/coverage/default/2.edn_genbits.2383470974
Short name T145
Test name
Test status
Simulation time 100133069 ps
CPU time 1.12 seconds
Started Mar 12 02:43:04 PM PDT 24
Finished Mar 12 02:43:05 PM PDT 24
Peak memory 215764 kb
Host smart-4927f90b-9a1b-46b7-82a2-03e3e5673310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383470974 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_genbits.2383470974
Directory /workspace/2.edn_genbits/latest

Test location /workspace/coverage/default/2.edn_intr.4269332607
Short name T125
Test name
Test status
Simulation time 32878497 ps
CPU time 0.9 seconds
Started Mar 12 02:43:04 PM PDT 24
Finished Mar 12 02:43:05 PM PDT 24
Peak memory 214624 kb
Host smart-1e3ba73e-cfb2-4fca-9b2a-bc6b41a296f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269332607 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_intr.4269332607
Directory /workspace/2.edn_intr/latest

Test location /workspace/coverage/default/2.edn_regwen.3729257243
Short name T253
Test name
Test status
Simulation time 203528151 ps
CPU time 0.88 seconds
Started Mar 12 02:46:23 PM PDT 24
Finished Mar 12 02:46:24 PM PDT 24
Peak memory 206256 kb
Host smart-f934e6d6-c215-4713-b8fd-8102c0c50303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729257243 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_regwen.3729257243
Directory /workspace/2.edn_regwen/latest

Test location /workspace/coverage/default/2.edn_sec_cm.4027268122
Short name T21
Test name
Test status
Simulation time 180755631 ps
CPU time 3.52 seconds
Started Mar 12 02:43:11 PM PDT 24
Finished Mar 12 02:43:15 PM PDT 24
Peak memory 235128 kb
Host smart-b43322ba-23cf-4741-a20d-53cbc9dddea8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027268122 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_sec_cm.4027268122
Directory /workspace/2.edn_sec_cm/latest

Test location /workspace/coverage/default/2.edn_smoke.739844258
Short name T50
Test name
Test status
Simulation time 50963190 ps
CPU time 0.91 seconds
Started Mar 12 02:46:57 PM PDT 24
Finished Mar 12 02:46:58 PM PDT 24
Peak memory 206252 kb
Host smart-cf2d8bb6-a33f-4149-88a1-53543cf9789b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739844258 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_smoke.739844258
Directory /workspace/2.edn_smoke/latest

Test location /workspace/coverage/default/2.edn_stress_all.3877822801
Short name T383
Test name
Test status
Simulation time 69018493 ps
CPU time 1.87 seconds
Started Mar 12 02:43:01 PM PDT 24
Finished Mar 12 02:43:03 PM PDT 24
Peak memory 215540 kb
Host smart-80edd94d-68c6-4572-ba0a-174d84197b64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877822801 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.edn_stress_all.3877822801
Directory /workspace/2.edn_stress_all/latest

Test location /workspace/coverage/default/2.edn_stress_all_with_rand_reset.118248992
Short name T191
Test name
Test status
Simulation time 192568234594 ps
CPU time 580.1 seconds
Started Mar 12 02:43:03 PM PDT 24
Finished Mar 12 02:52:43 PM PDT 24
Peak memory 217708 kb
Host smart-526cd541-dabe-48dc-9616-931fcb988c30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118248992 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.edn_stress_all_with_rand_reset.118248992
Directory /workspace/2.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.edn_alert.3172883928
Short name T801
Test name
Test status
Simulation time 167608474 ps
CPU time 1.35 seconds
Started Mar 12 02:44:15 PM PDT 24
Finished Mar 12 02:44:17 PM PDT 24
Peak memory 214832 kb
Host smart-c136be9b-d4a6-45d2-a9c0-8095c71a36dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172883928 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert.3172883928
Directory /workspace/20.edn_alert/latest

Test location /workspace/coverage/default/20.edn_alert_test.3593244132
Short name T382
Test name
Test status
Simulation time 53183433 ps
CPU time 0.87 seconds
Started Mar 12 02:44:15 PM PDT 24
Finished Mar 12 02:44:16 PM PDT 24
Peak memory 206088 kb
Host smart-9f8f8120-752a-4d33-b276-10ea0d8c3d90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593244132 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_alert_test.3593244132
Directory /workspace/20.edn_alert_test/latest

Test location /workspace/coverage/default/20.edn_disable.721764574
Short name T488
Test name
Test status
Simulation time 16466198 ps
CPU time 0.88 seconds
Started Mar 12 02:44:19 PM PDT 24
Finished Mar 12 02:44:20 PM PDT 24
Peak memory 214900 kb
Host smart-a1492ecd-0592-4f4f-8e85-ae15bc746cd5
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721764574 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_disable.721764574
Directory /workspace/20.edn_disable/latest

Test location /workspace/coverage/default/20.edn_err.1579825567
Short name T106
Test name
Test status
Simulation time 21193368 ps
CPU time 0.91 seconds
Started Mar 12 02:44:14 PM PDT 24
Finished Mar 12 02:44:15 PM PDT 24
Peak memory 217188 kb
Host smart-7575dafb-8e58-4ced-bc5d-82e7880e380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579825567 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_err.1579825567
Directory /workspace/20.edn_err/latest

Test location /workspace/coverage/default/20.edn_genbits.667293131
Short name T302
Test name
Test status
Simulation time 51724507 ps
CPU time 1.5 seconds
Started Mar 12 02:44:19 PM PDT 24
Finished Mar 12 02:44:20 PM PDT 24
Peak memory 216836 kb
Host smart-14fd66c6-1d78-414a-be61-c24a86f26608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667293131 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_genbits.667293131
Directory /workspace/20.edn_genbits/latest

Test location /workspace/coverage/default/20.edn_intr.3605971675
Short name T133
Test name
Test status
Simulation time 20602828 ps
CPU time 1.1 seconds
Started Mar 12 02:44:16 PM PDT 24
Finished Mar 12 02:44:17 PM PDT 24
Peak memory 214720 kb
Host smart-80ffb320-e828-4480-ad8d-14dc3321d302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605971675 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_intr.3605971675
Directory /workspace/20.edn_intr/latest

Test location /workspace/coverage/default/20.edn_smoke.2224965333
Short name T413
Test name
Test status
Simulation time 56962347 ps
CPU time 0.93 seconds
Started Mar 12 02:44:16 PM PDT 24
Finished Mar 12 02:44:17 PM PDT 24
Peak memory 214456 kb
Host smart-3af1aaef-2ad5-484c-98f3-8831d49b677d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224965333 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_smoke.2224965333
Directory /workspace/20.edn_smoke/latest

Test location /workspace/coverage/default/20.edn_stress_all.2811910375
Short name T797
Test name
Test status
Simulation time 313990981 ps
CPU time 3.47 seconds
Started Mar 12 02:44:15 PM PDT 24
Finished Mar 12 02:44:18 PM PDT 24
Peak memory 214416 kb
Host smart-b97f05c1-4d67-4d16-bbb8-a39b96d25626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811910375 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.edn_stress_all.2811910375
Directory /workspace/20.edn_stress_all/latest

Test location /workspace/coverage/default/20.edn_stress_all_with_rand_reset.1698422415
Short name T26
Test name
Test status
Simulation time 109292655442 ps
CPU time 568.21 seconds
Started Mar 12 02:44:17 PM PDT 24
Finished Mar 12 02:53:46 PM PDT 24
Peak memory 220516 kb
Host smart-4d469eb3-ce2f-4796-a599-126fcfad9435
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698422415 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 20.edn_stress_all_with_rand_reset.1698422415
Directory /workspace/20.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/200.edn_genbits.645863304
Short name T377
Test name
Test status
Simulation time 151115914 ps
CPU time 0.97 seconds
Started Mar 12 02:46:22 PM PDT 24
Finished Mar 12 02:46:23 PM PDT 24
Peak memory 215536 kb
Host smart-6d39e909-ca10-45c8-832d-6a0be014966b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645863304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.edn_genbits.645863304
Directory /workspace/200.edn_genbits/latest

Test location /workspace/coverage/default/201.edn_genbits.2998454172
Short name T280
Test name
Test status
Simulation time 155112898 ps
CPU time 1.49 seconds
Started Mar 12 02:46:26 PM PDT 24
Finished Mar 12 02:46:28 PM PDT 24
Peak memory 217308 kb
Host smart-b8d93306-619f-48ee-990e-b7523684231c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998454172 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.edn_genbits.2998454172
Directory /workspace/201.edn_genbits/latest

Test location /workspace/coverage/default/202.edn_genbits.3644952783
Short name T482
Test name
Test status
Simulation time 262240810 ps
CPU time 1.09 seconds
Started Mar 12 02:46:20 PM PDT 24
Finished Mar 12 02:46:21 PM PDT 24
Peak memory 215660 kb
Host smart-a25e8dfb-f125-4849-8d83-ea80af1bc984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644952783 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.edn_genbits.3644952783
Directory /workspace/202.edn_genbits/latest

Test location /workspace/coverage/default/203.edn_genbits.2310583222
Short name T14
Test name
Test status
Simulation time 41495996 ps
CPU time 1.48 seconds
Started Mar 12 02:46:23 PM PDT 24
Finished Mar 12 02:46:24 PM PDT 24
Peak memory 218048 kb
Host smart-a30796f3-1bb9-4adb-aea8-3f108c65e88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310583222 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.edn_genbits.2310583222
Directory /workspace/203.edn_genbits/latest

Test location /workspace/coverage/default/204.edn_genbits.2690264976
Short name T508
Test name
Test status
Simulation time 127507558 ps
CPU time 1.01 seconds
Started Mar 12 02:46:20 PM PDT 24
Finished Mar 12 02:46:21 PM PDT 24
Peak memory 215820 kb
Host smart-9e5b6a0e-47de-4485-9f3e-712e0d848969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690264976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.edn_genbits.2690264976
Directory /workspace/204.edn_genbits/latest

Test location /workspace/coverage/default/205.edn_genbits.3078171759
Short name T343
Test name
Test status
Simulation time 96937043 ps
CPU time 1.36 seconds
Started Mar 12 02:46:23 PM PDT 24
Finished Mar 12 02:46:25 PM PDT 24
Peak memory 217276 kb
Host smart-cb5c3b28-4a7a-47bc-adc0-ffbfdb6e4ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078171759 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.edn_genbits.3078171759
Directory /workspace/205.edn_genbits/latest

Test location /workspace/coverage/default/206.edn_genbits.1306418596
Short name T200
Test name
Test status
Simulation time 75817579 ps
CPU time 1.1 seconds
Started Mar 12 02:46:28 PM PDT 24
Finished Mar 12 02:46:30 PM PDT 24
Peak memory 214408 kb
Host smart-88fe04b7-0ce2-4e0c-96fe-f5ec87f8880c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306418596 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.edn_genbits.1306418596
Directory /workspace/206.edn_genbits/latest

Test location /workspace/coverage/default/207.edn_genbits.50888141
Short name T545
Test name
Test status
Simulation time 56456190 ps
CPU time 1.19 seconds
Started Mar 12 02:46:24 PM PDT 24
Finished Mar 12 02:46:25 PM PDT 24
Peak memory 216968 kb
Host smart-0074d39a-11b0-4ca5-b90e-31ca2e049206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50888141 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.edn_genbits.50888141
Directory /workspace/207.edn_genbits/latest

Test location /workspace/coverage/default/208.edn_genbits.3522561259
Short name T339
Test name
Test status
Simulation time 38688252 ps
CPU time 1.35 seconds
Started Mar 12 02:46:23 PM PDT 24
Finished Mar 12 02:46:25 PM PDT 24
Peak memory 216720 kb
Host smart-bf5e520e-335a-40d2-b55c-ed0251e04f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522561259 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.edn_genbits.3522561259
Directory /workspace/208.edn_genbits/latest

Test location /workspace/coverage/default/209.edn_genbits.2206598769
Short name T328
Test name
Test status
Simulation time 87553040 ps
CPU time 1.46 seconds
Started Mar 12 02:46:26 PM PDT 24
Finished Mar 12 02:46:28 PM PDT 24
Peak memory 217160 kb
Host smart-ddf940ef-4554-4acb-b0dd-11059acef8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206598769 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.edn_genbits.2206598769
Directory /workspace/209.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_alert.1555728105
Short name T150
Test name
Test status
Simulation time 24307230 ps
CPU time 1.28 seconds
Started Mar 12 02:44:15 PM PDT 24
Finished Mar 12 02:44:16 PM PDT 24
Peak memory 214788 kb
Host smart-b8910e9e-8bca-4f2a-9ce9-d8729431f765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555728105 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert.1555728105
Directory /workspace/21.edn_alert/latest

Test location /workspace/coverage/default/21.edn_alert_test.2417052824
Short name T707
Test name
Test status
Simulation time 18919154 ps
CPU time 0.97 seconds
Started Mar 12 02:44:31 PM PDT 24
Finished Mar 12 02:44:32 PM PDT 24
Peak memory 206104 kb
Host smart-4964e16a-ae80-4bf7-9331-b26d105976f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417052824 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_alert_test.2417052824
Directory /workspace/21.edn_alert_test/latest

Test location /workspace/coverage/default/21.edn_disable.21399482
Short name T117
Test name
Test status
Simulation time 30385399 ps
CPU time 0.84 seconds
Started Mar 12 02:44:16 PM PDT 24
Finished Mar 12 02:44:17 PM PDT 24
Peak memory 214952 kb
Host smart-7feaf7e4-6e8c-4790-97f4-c27a22e174b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21399482 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_disable.21399482
Directory /workspace/21.edn_disable/latest

Test location /workspace/coverage/default/21.edn_disable_auto_req_mode.379576488
Short name T516
Test name
Test status
Simulation time 75104044 ps
CPU time 1.06 seconds
Started Mar 12 02:44:16 PM PDT 24
Finished Mar 12 02:44:18 PM PDT 24
Peak memory 216736 kb
Host smart-1ea00ab3-0136-48d2-8b81-cdf3fb492643
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379576488 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_di
sable_auto_req_mode.379576488
Directory /workspace/21.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/21.edn_err.3555980585
Short name T815
Test name
Test status
Simulation time 58304563 ps
CPU time 1 seconds
Started Mar 12 02:44:16 PM PDT 24
Finished Mar 12 02:44:17 PM PDT 24
Peak memory 216020 kb
Host smart-08971be4-9c19-4e82-a7fa-081143094371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555980585 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_err.3555980585
Directory /workspace/21.edn_err/latest

Test location /workspace/coverage/default/21.edn_genbits.1470863149
Short name T487
Test name
Test status
Simulation time 97069739 ps
CPU time 1.66 seconds
Started Mar 12 02:44:15 PM PDT 24
Finished Mar 12 02:44:17 PM PDT 24
Peak memory 218428 kb
Host smart-8acda3b3-eacf-40a6-89bf-766ea70b7a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470863149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_genbits.1470863149
Directory /workspace/21.edn_genbits/latest

Test location /workspace/coverage/default/21.edn_intr.2978410987
Short name T402
Test name
Test status
Simulation time 33258157 ps
CPU time 0.89 seconds
Started Mar 12 02:44:19 PM PDT 24
Finished Mar 12 02:44:20 PM PDT 24
Peak memory 214724 kb
Host smart-22727047-0b23-4b3f-88e1-6ff0ceb8796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978410987 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_intr.2978410987
Directory /workspace/21.edn_intr/latest

Test location /workspace/coverage/default/21.edn_smoke.3465029801
Short name T653
Test name
Test status
Simulation time 50381325 ps
CPU time 0.9 seconds
Started Mar 12 02:44:16 PM PDT 24
Finished Mar 12 02:44:17 PM PDT 24
Peak memory 214440 kb
Host smart-eaa3372a-412d-45d4-b929-d3ab4c4fbeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465029801 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_smoke.3465029801
Directory /workspace/21.edn_smoke/latest

Test location /workspace/coverage/default/21.edn_stress_all.972998841
Short name T353
Test name
Test status
Simulation time 592482230 ps
CPU time 4.74 seconds
Started Mar 12 02:44:13 PM PDT 24
Finished Mar 12 02:44:18 PM PDT 24
Peak memory 215584 kb
Host smart-32313f4e-0967-4ebc-ac8e-ff7cd7087c45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972998841 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.edn_stress_all.972998841
Directory /workspace/21.edn_stress_all/latest

Test location /workspace/coverage/default/21.edn_stress_all_with_rand_reset.3060242387
Short name T632
Test name
Test status
Simulation time 123045682589 ps
CPU time 442.64 seconds
Started Mar 12 02:44:24 PM PDT 24
Finished Mar 12 02:51:46 PM PDT 24
Peak memory 222780 kb
Host smart-eabbc419-df67-47a3-af8e-35a37103c0b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060242387 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.edn_stress_all_with_rand_reset.3060242387
Directory /workspace/21.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/210.edn_genbits.3144368894
Short name T622
Test name
Test status
Simulation time 37773602 ps
CPU time 1.06 seconds
Started Mar 12 02:46:23 PM PDT 24
Finished Mar 12 02:46:24 PM PDT 24
Peak memory 215472 kb
Host smart-bbc8377f-53ba-4248-9994-3c0345b87526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144368894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.edn_genbits.3144368894
Directory /workspace/210.edn_genbits/latest

Test location /workspace/coverage/default/211.edn_genbits.348130579
Short name T604
Test name
Test status
Simulation time 75972289 ps
CPU time 1.02 seconds
Started Mar 12 02:46:22 PM PDT 24
Finished Mar 12 02:46:23 PM PDT 24
Peak memory 215788 kb
Host smart-32fcd2f1-0fe7-4cf1-8afc-1f33aa508379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348130579 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.edn_genbits.348130579
Directory /workspace/211.edn_genbits/latest

Test location /workspace/coverage/default/212.edn_genbits.2482294844
Short name T423
Test name
Test status
Simulation time 93602683 ps
CPU time 1.64 seconds
Started Mar 12 02:46:19 PM PDT 24
Finished Mar 12 02:46:21 PM PDT 24
Peak memory 217340 kb
Host smart-9b391372-e473-4d38-9126-5fdcabd19985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482294844 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.edn_genbits.2482294844
Directory /workspace/212.edn_genbits/latest

Test location /workspace/coverage/default/213.edn_genbits.3220224291
Short name T630
Test name
Test status
Simulation time 57955015 ps
CPU time 1.65 seconds
Started Mar 12 02:46:25 PM PDT 24
Finished Mar 12 02:46:27 PM PDT 24
Peak memory 217052 kb
Host smart-97442f4f-d27d-478e-a2ef-619daefc023c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220224291 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.edn_genbits.3220224291
Directory /workspace/213.edn_genbits/latest

Test location /workspace/coverage/default/214.edn_genbits.95383594
Short name T780
Test name
Test status
Simulation time 62152830 ps
CPU time 1.54 seconds
Started Mar 12 02:46:28 PM PDT 24
Finished Mar 12 02:46:30 PM PDT 24
Peak memory 217180 kb
Host smart-0f43a571-be00-4b94-9976-29b243aed2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95383594 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.edn_genbits.95383594
Directory /workspace/214.edn_genbits/latest

Test location /workspace/coverage/default/215.edn_genbits.2410522206
Short name T420
Test name
Test status
Simulation time 50702593 ps
CPU time 1.33 seconds
Started Mar 12 02:46:23 PM PDT 24
Finished Mar 12 02:46:24 PM PDT 24
Peak memory 217432 kb
Host smart-05d49ae7-123f-492c-8dcb-9eca5aa967b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410522206 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.edn_genbits.2410522206
Directory /workspace/215.edn_genbits/latest

Test location /workspace/coverage/default/216.edn_genbits.2082007408
Short name T489
Test name
Test status
Simulation time 57290872 ps
CPU time 1.48 seconds
Started Mar 12 02:46:21 PM PDT 24
Finished Mar 12 02:46:23 PM PDT 24
Peak memory 216772 kb
Host smart-917d635e-1dd1-49bd-b6a2-f2963e726cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082007408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.edn_genbits.2082007408
Directory /workspace/216.edn_genbits/latest

Test location /workspace/coverage/default/217.edn_genbits.4030814341
Short name T351
Test name
Test status
Simulation time 151324990 ps
CPU time 1.16 seconds
Started Mar 12 02:46:26 PM PDT 24
Finished Mar 12 02:46:27 PM PDT 24
Peak memory 216176 kb
Host smart-3514a5cb-639f-4448-96bc-d7bc4b04e0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030814341 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.edn_genbits.4030814341
Directory /workspace/217.edn_genbits/latest

Test location /workspace/coverage/default/218.edn_genbits.2113634551
Short name T510
Test name
Test status
Simulation time 27382440 ps
CPU time 1.15 seconds
Started Mar 12 02:46:24 PM PDT 24
Finished Mar 12 02:46:25 PM PDT 24
Peak memory 215688 kb
Host smart-c7c8983c-3fe2-48d4-ad60-5f64ec30af5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113634551 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.edn_genbits.2113634551
Directory /workspace/218.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_alert.1470555731
Short name T108
Test name
Test status
Simulation time 116058130 ps
CPU time 1.14 seconds
Started Mar 12 02:44:24 PM PDT 24
Finished Mar 12 02:44:26 PM PDT 24
Peak memory 214900 kb
Host smart-4825ed50-0195-4530-8439-ba8461249c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470555731 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert.1470555731
Directory /workspace/22.edn_alert/latest

Test location /workspace/coverage/default/22.edn_alert_test.323790621
Short name T309
Test name
Test status
Simulation time 19946570 ps
CPU time 0.83 seconds
Started Mar 12 02:44:28 PM PDT 24
Finished Mar 12 02:44:29 PM PDT 24
Peak memory 205120 kb
Host smart-866bdd1e-e962-4d7a-9647-2af0bb84be1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323790621 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_alert_test.323790621
Directory /workspace/22.edn_alert_test/latest

Test location /workspace/coverage/default/22.edn_disable.3047620597
Short name T636
Test name
Test status
Simulation time 18705077 ps
CPU time 0.83 seconds
Started Mar 12 02:44:27 PM PDT 24
Finished Mar 12 02:44:28 PM PDT 24
Peak memory 214636 kb
Host smart-356e8b9f-2efc-4dd2-8d65-61cb4ad747a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047620597 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_disable.3047620597
Directory /workspace/22.edn_disable/latest

Test location /workspace/coverage/default/22.edn_disable_auto_req_mode.2424712264
Short name T421
Test name
Test status
Simulation time 66648554 ps
CPU time 0.96 seconds
Started Mar 12 02:44:26 PM PDT 24
Finished Mar 12 02:44:27 PM PDT 24
Peak memory 216804 kb
Host smart-1945c680-aa27-4b80-9a1e-181ee7117a08
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424712264 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_d
isable_auto_req_mode.2424712264
Directory /workspace/22.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/22.edn_genbits.1008453557
Short name T63
Test name
Test status
Simulation time 50397003 ps
CPU time 1.14 seconds
Started Mar 12 02:44:29 PM PDT 24
Finished Mar 12 02:44:31 PM PDT 24
Peak memory 217132 kb
Host smart-5b25fedc-c6c7-426a-9215-50523e02b2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008453557 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_genbits.1008453557
Directory /workspace/22.edn_genbits/latest

Test location /workspace/coverage/default/22.edn_smoke.2698941728
Short name T418
Test name
Test status
Simulation time 25697688 ps
CPU time 0.94 seconds
Started Mar 12 02:44:29 PM PDT 24
Finished Mar 12 02:44:30 PM PDT 24
Peak memory 214412 kb
Host smart-5d39a085-29b5-4c74-8bc8-ceadb1544222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698941728 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_smoke.2698941728
Directory /workspace/22.edn_smoke/latest

Test location /workspace/coverage/default/22.edn_stress_all.4047616068
Short name T590
Test name
Test status
Simulation time 198192759 ps
CPU time 2.5 seconds
Started Mar 12 02:44:26 PM PDT 24
Finished Mar 12 02:44:28 PM PDT 24
Peak memory 216964 kb
Host smart-b8d07e3e-f03f-4fbf-accf-8ed62b9ab99e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047616068 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.edn_stress_all.4047616068
Directory /workspace/22.edn_stress_all/latest

Test location /workspace/coverage/default/22.edn_stress_all_with_rand_reset.2648609123
Short name T486
Test name
Test status
Simulation time 342381147096 ps
CPU time 1061.29 seconds
Started Mar 12 02:44:27 PM PDT 24
Finished Mar 12 03:02:08 PM PDT 24
Peak memory 220528 kb
Host smart-69963d78-eee9-4349-b5a4-fcae3b2702fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648609123 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 22.edn_stress_all_with_rand_reset.2648609123
Directory /workspace/22.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/220.edn_genbits.337430049
Short name T639
Test name
Test status
Simulation time 50528328 ps
CPU time 1.23 seconds
Started Mar 12 02:46:26 PM PDT 24
Finished Mar 12 02:46:27 PM PDT 24
Peak memory 215916 kb
Host smart-5e01f866-b4fe-4077-8bc6-8e4f988d1f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337430049 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.edn_genbits.337430049
Directory /workspace/220.edn_genbits/latest

Test location /workspace/coverage/default/221.edn_genbits.739155924
Short name T571
Test name
Test status
Simulation time 53387199 ps
CPU time 1.16 seconds
Started Mar 12 02:46:20 PM PDT 24
Finished Mar 12 02:46:21 PM PDT 24
Peak memory 215616 kb
Host smart-b7f567ff-bc16-44fa-96f3-ccc41898afba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739155924 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.edn_genbits.739155924
Directory /workspace/221.edn_genbits/latest

Test location /workspace/coverage/default/222.edn_genbits.2023180156
Short name T295
Test name
Test status
Simulation time 40935400 ps
CPU time 1.16 seconds
Started Mar 12 02:46:27 PM PDT 24
Finished Mar 12 02:46:28 PM PDT 24
Peak memory 216872 kb
Host smart-67e49767-88c6-43b0-b6bc-bdb1ddde3858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023180156 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.edn_genbits.2023180156
Directory /workspace/222.edn_genbits/latest

Test location /workspace/coverage/default/223.edn_genbits.3793486987
Short name T276
Test name
Test status
Simulation time 30903991 ps
CPU time 1.33 seconds
Started Mar 12 02:46:22 PM PDT 24
Finished Mar 12 02:46:24 PM PDT 24
Peak memory 217028 kb
Host smart-7c592005-9614-4db3-8a7c-629c2433e9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793486987 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.edn_genbits.3793486987
Directory /workspace/223.edn_genbits/latest

Test location /workspace/coverage/default/224.edn_genbits.3864665447
Short name T338
Test name
Test status
Simulation time 54773816 ps
CPU time 1.18 seconds
Started Mar 12 02:46:26 PM PDT 24
Finished Mar 12 02:46:27 PM PDT 24
Peak memory 215788 kb
Host smart-8bf71ed0-2455-450b-8737-b16e2f997ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864665447 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.edn_genbits.3864665447
Directory /workspace/224.edn_genbits/latest

Test location /workspace/coverage/default/225.edn_genbits.2480153465
Short name T325
Test name
Test status
Simulation time 62208565 ps
CPU time 1.32 seconds
Started Mar 12 02:46:21 PM PDT 24
Finished Mar 12 02:46:22 PM PDT 24
Peak memory 215676 kb
Host smart-59616827-c139-4247-bf7b-dba6a072cd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480153465 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.edn_genbits.2480153465
Directory /workspace/225.edn_genbits/latest

Test location /workspace/coverage/default/226.edn_genbits.3340521933
Short name T617
Test name
Test status
Simulation time 62003170 ps
CPU time 1.08 seconds
Started Mar 12 02:46:26 PM PDT 24
Finished Mar 12 02:46:27 PM PDT 24
Peak memory 215604 kb
Host smart-7ded6e4c-265d-415d-9a95-091c64aadd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340521933 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.edn_genbits.3340521933
Directory /workspace/226.edn_genbits/latest

Test location /workspace/coverage/default/227.edn_genbits.1895825401
Short name T705
Test name
Test status
Simulation time 47637874 ps
CPU time 1.39 seconds
Started Mar 12 02:46:22 PM PDT 24
Finished Mar 12 02:46:24 PM PDT 24
Peak memory 215620 kb
Host smart-ecb0b5cb-d56f-421f-86a7-12eb107aac8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895825401 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.edn_genbits.1895825401
Directory /workspace/227.edn_genbits/latest

Test location /workspace/coverage/default/228.edn_genbits.326292186
Short name T31
Test name
Test status
Simulation time 57052377 ps
CPU time 1.97 seconds
Started Mar 12 02:46:23 PM PDT 24
Finished Mar 12 02:46:25 PM PDT 24
Peak memory 217052 kb
Host smart-abf6121f-cfb9-4552-ad8f-12c8db1201e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326292186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.edn_genbits.326292186
Directory /workspace/228.edn_genbits/latest

Test location /workspace/coverage/default/229.edn_genbits.4060497054
Short name T315
Test name
Test status
Simulation time 58656333 ps
CPU time 1.67 seconds
Started Mar 12 02:46:23 PM PDT 24
Finished Mar 12 02:46:25 PM PDT 24
Peak memory 217320 kb
Host smart-d33f1610-9a18-46c6-8e19-fea14aa1ccb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060497054 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.edn_genbits.4060497054
Directory /workspace/229.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_alert.514076940
Short name T72
Test name
Test status
Simulation time 43668509 ps
CPU time 1.19 seconds
Started Mar 12 02:44:29 PM PDT 24
Finished Mar 12 02:44:30 PM PDT 24
Peak memory 214844 kb
Host smart-58c9d84e-b36e-4bd3-8258-4fcbf850a7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514076940 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert.514076940
Directory /workspace/23.edn_alert/latest

Test location /workspace/coverage/default/23.edn_alert_test.2622983136
Short name T472
Test name
Test status
Simulation time 79116218 ps
CPU time 0.86 seconds
Started Mar 12 02:44:28 PM PDT 24
Finished Mar 12 02:44:29 PM PDT 24
Peak memory 206100 kb
Host smart-0ee7da11-6753-42c7-bf2d-7709dd570e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622983136 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_alert_test.2622983136
Directory /workspace/23.edn_alert_test/latest

Test location /workspace/coverage/default/23.edn_disable.4141783459
Short name T812
Test name
Test status
Simulation time 22662515 ps
CPU time 0.87 seconds
Started Mar 12 02:44:26 PM PDT 24
Finished Mar 12 02:44:27 PM PDT 24
Peak memory 214972 kb
Host smart-76fba1f3-d383-4e6b-82ee-45d1fb1c89e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141783459 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_disable.4141783459
Directory /workspace/23.edn_disable/latest

Test location /workspace/coverage/default/23.edn_err.1199188590
Short name T471
Test name
Test status
Simulation time 19882422 ps
CPU time 1.04 seconds
Started Mar 12 02:44:27 PM PDT 24
Finished Mar 12 02:44:28 PM PDT 24
Peak memory 217224 kb
Host smart-95bae5a4-299d-4408-86ed-f048126a140f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199188590 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_err.1199188590
Directory /workspace/23.edn_err/latest

Test location /workspace/coverage/default/23.edn_genbits.3591726505
Short name T671
Test name
Test status
Simulation time 97265868 ps
CPU time 1.51 seconds
Started Mar 12 02:44:23 PM PDT 24
Finished Mar 12 02:44:25 PM PDT 24
Peak memory 217324 kb
Host smart-54bfd3ae-bf89-4e51-a5be-54505c0ffb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591726505 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_genbits.3591726505
Directory /workspace/23.edn_genbits/latest

Test location /workspace/coverage/default/23.edn_intr.3090083846
Short name T799
Test name
Test status
Simulation time 25885926 ps
CPU time 1.22 seconds
Started Mar 12 02:44:25 PM PDT 24
Finished Mar 12 02:44:26 PM PDT 24
Peak memory 231832 kb
Host smart-1d81f40f-9c56-424c-846f-55d1ad985786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090083846 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_intr.3090083846
Directory /workspace/23.edn_intr/latest

Test location /workspace/coverage/default/23.edn_smoke.184183463
Short name T789
Test name
Test status
Simulation time 31337410 ps
CPU time 0.94 seconds
Started Mar 12 02:44:25 PM PDT 24
Finished Mar 12 02:44:26 PM PDT 24
Peak memory 214356 kb
Host smart-d6d90605-c851-4374-a2be-3405db18def0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184183463 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_smoke.184183463
Directory /workspace/23.edn_smoke/latest

Test location /workspace/coverage/default/23.edn_stress_all.357489105
Short name T60
Test name
Test status
Simulation time 405956233 ps
CPU time 2.36 seconds
Started Mar 12 02:44:31 PM PDT 24
Finished Mar 12 02:44:33 PM PDT 24
Peak memory 214428 kb
Host smart-358192ec-441d-4532-9244-750be6946ab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357489105 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.edn_stress_all.357489105
Directory /workspace/23.edn_stress_all/latest

Test location /workspace/coverage/default/23.edn_stress_all_with_rand_reset.2812529110
Short name T549
Test name
Test status
Simulation time 161246226885 ps
CPU time 1006.75 seconds
Started Mar 12 02:44:24 PM PDT 24
Finished Mar 12 03:01:11 PM PDT 24
Peak memory 222332 kb
Host smart-0bfa7688-fcae-470c-9a09-47f190fd85ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812529110 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 23.edn_stress_all_with_rand_reset.2812529110
Directory /workspace/23.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.edn_genbits.3402530976
Short name T518
Test name
Test status
Simulation time 61961732 ps
CPU time 1.61 seconds
Started Mar 12 02:46:23 PM PDT 24
Finished Mar 12 02:46:25 PM PDT 24
Peak memory 216972 kb
Host smart-be7fac3d-373b-4490-bf98-769f67c118d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402530976 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.edn_genbits.3402530976
Directory /workspace/230.edn_genbits/latest

Test location /workspace/coverage/default/231.edn_genbits.1256591977
Short name T544
Test name
Test status
Simulation time 42682935 ps
CPU time 1.28 seconds
Started Mar 12 02:46:27 PM PDT 24
Finished Mar 12 02:46:28 PM PDT 24
Peak memory 215640 kb
Host smart-6f450afc-b257-41d4-9acc-d906e86f3fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256591977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.edn_genbits.1256591977
Directory /workspace/231.edn_genbits/latest

Test location /workspace/coverage/default/232.edn_genbits.2158341442
Short name T477
Test name
Test status
Simulation time 28612040 ps
CPU time 1.24 seconds
Started Mar 12 02:46:23 PM PDT 24
Finished Mar 12 02:46:25 PM PDT 24
Peak memory 217084 kb
Host smart-221047e2-c666-4346-a7a9-8dde9bf447a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158341442 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.edn_genbits.2158341442
Directory /workspace/232.edn_genbits/latest

Test location /workspace/coverage/default/233.edn_genbits.1737080385
Short name T45
Test name
Test status
Simulation time 84722818 ps
CPU time 1.12 seconds
Started Mar 12 02:46:22 PM PDT 24
Finished Mar 12 02:46:24 PM PDT 24
Peak memory 215548 kb
Host smart-50691292-96db-4ac2-b1d2-9467fe382f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737080385 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.edn_genbits.1737080385
Directory /workspace/233.edn_genbits/latest

Test location /workspace/coverage/default/234.edn_genbits.1422174788
Short name T287
Test name
Test status
Simulation time 58869341 ps
CPU time 1.41 seconds
Started Mar 12 02:46:30 PM PDT 24
Finished Mar 12 02:46:32 PM PDT 24
Peak memory 217168 kb
Host smart-72d10661-7680-4463-b15b-db23df46b00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422174788 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.edn_genbits.1422174788
Directory /workspace/234.edn_genbits/latest

Test location /workspace/coverage/default/235.edn_genbits.2778758960
Short name T308
Test name
Test status
Simulation time 42841022 ps
CPU time 1.21 seconds
Started Mar 12 02:46:30 PM PDT 24
Finished Mar 12 02:46:31 PM PDT 24
Peak memory 216836 kb
Host smart-75fbb584-f75e-45f7-b3f1-219226cd37c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778758960 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.edn_genbits.2778758960
Directory /workspace/235.edn_genbits/latest

Test location /workspace/coverage/default/236.edn_genbits.3358905319
Short name T177
Test name
Test status
Simulation time 103211932 ps
CPU time 1.3 seconds
Started Mar 12 02:46:26 PM PDT 24
Finished Mar 12 02:46:28 PM PDT 24
Peak memory 215756 kb
Host smart-123284b9-1a29-4499-9747-9dd79c258770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358905319 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.edn_genbits.3358905319
Directory /workspace/236.edn_genbits/latest

Test location /workspace/coverage/default/237.edn_genbits.184233864
Short name T772
Test name
Test status
Simulation time 82123484 ps
CPU time 1.19 seconds
Started Mar 12 02:46:30 PM PDT 24
Finished Mar 12 02:46:31 PM PDT 24
Peak memory 215572 kb
Host smart-412a9541-07f7-4e1b-9d7a-d2733d736ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184233864 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.edn_genbits.184233864
Directory /workspace/237.edn_genbits/latest

Test location /workspace/coverage/default/238.edn_genbits.2062708790
Short name T350
Test name
Test status
Simulation time 117215168 ps
CPU time 1.16 seconds
Started Mar 12 02:46:32 PM PDT 24
Finished Mar 12 02:46:34 PM PDT 24
Peak memory 215544 kb
Host smart-acb65367-607b-4172-a1cd-a5144ee92916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062708790 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.edn_genbits.2062708790
Directory /workspace/238.edn_genbits/latest

Test location /workspace/coverage/default/239.edn_genbits.4087445254
Short name T387
Test name
Test status
Simulation time 57290155 ps
CPU time 1.38 seconds
Started Mar 12 02:46:30 PM PDT 24
Finished Mar 12 02:46:32 PM PDT 24
Peak memory 217156 kb
Host smart-ddecd02c-88d0-40cb-8057-c7dedc9446b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087445254 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.edn_genbits.4087445254
Directory /workspace/239.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_alert.4123225507
Short name T427
Test name
Test status
Simulation time 39018900 ps
CPU time 1.14 seconds
Started Mar 12 02:44:24 PM PDT 24
Finished Mar 12 02:44:26 PM PDT 24
Peak memory 214864 kb
Host smart-b934a598-e2e0-49d7-8e17-c7ef06d92c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123225507 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert.4123225507
Directory /workspace/24.edn_alert/latest

Test location /workspace/coverage/default/24.edn_alert_test.1943586849
Short name T833
Test name
Test status
Simulation time 49740183 ps
CPU time 0.89 seconds
Started Mar 12 02:44:25 PM PDT 24
Finished Mar 12 02:44:26 PM PDT 24
Peak memory 205700 kb
Host smart-6a5d1e9d-b002-42db-ba98-7d0cb5d541b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943586849 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_alert_test.1943586849
Directory /workspace/24.edn_alert_test/latest

Test location /workspace/coverage/default/24.edn_disable_auto_req_mode.493577550
Short name T757
Test name
Test status
Simulation time 106495363 ps
CPU time 1.16 seconds
Started Mar 12 02:44:26 PM PDT 24
Finished Mar 12 02:44:28 PM PDT 24
Peak memory 215560 kb
Host smart-b2616b8c-4f2d-419d-b85a-ee45f24fa11c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493577550 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_di
sable_auto_req_mode.493577550
Directory /workspace/24.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/24.edn_genbits.684372637
Short name T640
Test name
Test status
Simulation time 38129117 ps
CPU time 1.46 seconds
Started Mar 12 02:44:24 PM PDT 24
Finished Mar 12 02:44:25 PM PDT 24
Peak memory 217600 kb
Host smart-1efe1c31-d1e3-455a-840d-c71583ec93da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684372637 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_genbits.684372637
Directory /workspace/24.edn_genbits/latest

Test location /workspace/coverage/default/24.edn_intr.3954165941
Short name T126
Test name
Test status
Simulation time 23675154 ps
CPU time 0.95 seconds
Started Mar 12 02:44:27 PM PDT 24
Finished Mar 12 02:44:28 PM PDT 24
Peak memory 214592 kb
Host smart-7628270e-d9bd-4cf8-8fa1-7f0cb1728ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954165941 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_intr.3954165941
Directory /workspace/24.edn_intr/latest

Test location /workspace/coverage/default/24.edn_smoke.3917693388
Short name T683
Test name
Test status
Simulation time 26173118 ps
CPU time 0.92 seconds
Started Mar 12 02:44:26 PM PDT 24
Finished Mar 12 02:44:27 PM PDT 24
Peak memory 214388 kb
Host smart-b90ad8ec-54eb-43a3-81df-1010fb93c716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917693388 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_smoke.3917693388
Directory /workspace/24.edn_smoke/latest

Test location /workspace/coverage/default/24.edn_stress_all.2537175255
Short name T440
Test name
Test status
Simulation time 241924142 ps
CPU time 1.87 seconds
Started Mar 12 02:44:29 PM PDT 24
Finished Mar 12 02:44:31 PM PDT 24
Peak memory 214412 kb
Host smart-ffc54a88-6749-4dd1-965e-790be0f2e0f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537175255 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.edn_stress_all.2537175255
Directory /workspace/24.edn_stress_all/latest

Test location /workspace/coverage/default/24.edn_stress_all_with_rand_reset.3034265372
Short name T642
Test name
Test status
Simulation time 835456895013 ps
CPU time 2075.43 seconds
Started Mar 12 02:44:30 PM PDT 24
Finished Mar 12 03:19:05 PM PDT 24
Peak memory 224344 kb
Host smart-eea368b7-9edd-4190-a2f4-8a3a543a59d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034265372 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.edn_stress_all_with_rand_reset.3034265372
Directory /workspace/24.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/240.edn_genbits.2462063044
Short name T275
Test name
Test status
Simulation time 357157319 ps
CPU time 1.73 seconds
Started Mar 12 02:46:28 PM PDT 24
Finished Mar 12 02:46:30 PM PDT 24
Peak memory 217076 kb
Host smart-4a4cfa95-e2a6-4269-a2bc-ba3f2178b3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462063044 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.edn_genbits.2462063044
Directory /workspace/240.edn_genbits/latest

Test location /workspace/coverage/default/241.edn_genbits.3740486805
Short name T779
Test name
Test status
Simulation time 51862386 ps
CPU time 1.29 seconds
Started Mar 12 02:46:34 PM PDT 24
Finished Mar 12 02:46:36 PM PDT 24
Peak memory 217108 kb
Host smart-929100ad-8460-4d91-8499-9968f57f6fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740486805 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.edn_genbits.3740486805
Directory /workspace/241.edn_genbits/latest

Test location /workspace/coverage/default/243.edn_genbits.4256023663
Short name T265
Test name
Test status
Simulation time 77676094 ps
CPU time 1.34 seconds
Started Mar 12 02:46:28 PM PDT 24
Finished Mar 12 02:46:30 PM PDT 24
Peak memory 217408 kb
Host smart-3193064f-7426-4ea6-b094-d524b437b2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256023663 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.edn_genbits.4256023663
Directory /workspace/243.edn_genbits/latest

Test location /workspace/coverage/default/244.edn_genbits.4239462066
Short name T58
Test name
Test status
Simulation time 42536341 ps
CPU time 1.49 seconds
Started Mar 12 02:46:30 PM PDT 24
Finished Mar 12 02:46:32 PM PDT 24
Peak memory 215748 kb
Host smart-e38f906e-9a76-46be-bba0-b9b31f07c97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239462066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.edn_genbits.4239462066
Directory /workspace/244.edn_genbits/latest

Test location /workspace/coverage/default/245.edn_genbits.848944120
Short name T37
Test name
Test status
Simulation time 59067718 ps
CPU time 1.07 seconds
Started Mar 12 02:46:28 PM PDT 24
Finished Mar 12 02:46:29 PM PDT 24
Peak memory 215704 kb
Host smart-c34aa134-a7f7-46b9-9a94-7727b6f20774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848944120 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.edn_genbits.848944120
Directory /workspace/245.edn_genbits/latest

Test location /workspace/coverage/default/246.edn_genbits.1339780149
Short name T569
Test name
Test status
Simulation time 526821924 ps
CPU time 4.02 seconds
Started Mar 12 02:46:32 PM PDT 24
Finished Mar 12 02:46:37 PM PDT 24
Peak memory 218488 kb
Host smart-53338b33-0065-4a6b-9ebd-9154ab51369e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339780149 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.edn_genbits.1339780149
Directory /workspace/246.edn_genbits/latest

Test location /workspace/coverage/default/247.edn_genbits.2499421956
Short name T542
Test name
Test status
Simulation time 62677021 ps
CPU time 1.37 seconds
Started Mar 12 02:46:34 PM PDT 24
Finished Mar 12 02:46:36 PM PDT 24
Peak memory 215756 kb
Host smart-52979080-f58a-4a7a-8146-bffc15361d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499421956 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.edn_genbits.2499421956
Directory /workspace/247.edn_genbits/latest

Test location /workspace/coverage/default/249.edn_genbits.79978101
Short name T627
Test name
Test status
Simulation time 35443716 ps
CPU time 1.27 seconds
Started Mar 12 02:46:30 PM PDT 24
Finished Mar 12 02:46:31 PM PDT 24
Peak memory 218500 kb
Host smart-dfeb6393-388b-469b-8a3a-5b34f3b69e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79978101 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.edn_genbits.79978101
Directory /workspace/249.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_alert.1982724595
Short name T661
Test name
Test status
Simulation time 22961080 ps
CPU time 1.2 seconds
Started Mar 12 02:44:28 PM PDT 24
Finished Mar 12 02:44:29 PM PDT 24
Peak memory 214848 kb
Host smart-1ac0e8d2-ca79-4a6c-bb76-57a408eadaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982724595 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert.1982724595
Directory /workspace/25.edn_alert/latest

Test location /workspace/coverage/default/25.edn_alert_test.3797550392
Short name T378
Test name
Test status
Simulation time 26068805 ps
CPU time 0.93 seconds
Started Mar 12 02:44:34 PM PDT 24
Finished Mar 12 02:44:35 PM PDT 24
Peak memory 206108 kb
Host smart-a08c88df-02f1-4830-b9fb-b7e20cdf91e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797550392 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_alert_test.3797550392
Directory /workspace/25.edn_alert_test/latest

Test location /workspace/coverage/default/25.edn_disable_auto_req_mode.2115038702
Short name T91
Test name
Test status
Simulation time 83597063 ps
CPU time 1.14 seconds
Started Mar 12 02:44:36 PM PDT 24
Finished Mar 12 02:44:37 PM PDT 24
Peak memory 215400 kb
Host smart-0fdac927-78d3-4b29-b2f8-ff992c62f566
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115038702 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_d
isable_auto_req_mode.2115038702
Directory /workspace/25.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/25.edn_err.2642193099
Short name T735
Test name
Test status
Simulation time 99216807 ps
CPU time 1.08 seconds
Started Mar 12 02:44:34 PM PDT 24
Finished Mar 12 02:44:36 PM PDT 24
Peak memory 218380 kb
Host smart-20b0f737-677d-49ee-aeab-4f7f9bbae8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642193099 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_err.2642193099
Directory /workspace/25.edn_err/latest

Test location /workspace/coverage/default/25.edn_genbits.3264396408
Short name T481
Test name
Test status
Simulation time 81808760 ps
CPU time 1.14 seconds
Started Mar 12 02:44:29 PM PDT 24
Finished Mar 12 02:44:30 PM PDT 24
Peak memory 215908 kb
Host smart-67c6f99b-5287-4dff-a5f8-70df23839ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264396408 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_genbits.3264396408
Directory /workspace/25.edn_genbits/latest

Test location /workspace/coverage/default/25.edn_intr.1260432285
Short name T724
Test name
Test status
Simulation time 28143590 ps
CPU time 0.85 seconds
Started Mar 12 02:44:28 PM PDT 24
Finished Mar 12 02:44:29 PM PDT 24
Peak memory 214712 kb
Host smart-f99992cf-b531-4d0c-b623-b9480f1cc697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260432285 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_intr.1260432285
Directory /workspace/25.edn_intr/latest

Test location /workspace/coverage/default/25.edn_smoke.1358880540
Short name T619
Test name
Test status
Simulation time 19866810 ps
CPU time 0.98 seconds
Started Mar 12 02:44:27 PM PDT 24
Finished Mar 12 02:44:28 PM PDT 24
Peak memory 214452 kb
Host smart-c68824c5-0dd6-4bf8-843b-a5efa0b5a617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358880540 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_smoke.1358880540
Directory /workspace/25.edn_smoke/latest

Test location /workspace/coverage/default/25.edn_stress_all.360981893
Short name T493
Test name
Test status
Simulation time 298422609 ps
CPU time 3.5 seconds
Started Mar 12 02:44:26 PM PDT 24
Finished Mar 12 02:44:30 PM PDT 24
Peak memory 215612 kb
Host smart-fdb5c879-e2e0-4341-b7df-035553decee4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360981893 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.edn_stress_all.360981893
Directory /workspace/25.edn_stress_all/latest

Test location /workspace/coverage/default/25.edn_stress_all_with_rand_reset.2848604842
Short name T25
Test name
Test status
Simulation time 62937742685 ps
CPU time 1384.34 seconds
Started Mar 12 02:44:32 PM PDT 24
Finished Mar 12 03:07:37 PM PDT 24
Peak memory 221352 kb
Host smart-1cb8bc75-6665-4c35-9b5f-5a0db0583e8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848604842 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.edn_stress_all_with_rand_reset.2848604842
Directory /workspace/25.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/250.edn_genbits.3988673499
Short name T710
Test name
Test status
Simulation time 78019312 ps
CPU time 1.56 seconds
Started Mar 12 02:46:32 PM PDT 24
Finished Mar 12 02:46:35 PM PDT 24
Peak memory 216024 kb
Host smart-6148ebb7-1d70-4743-9864-44e4971ffbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988673499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.edn_genbits.3988673499
Directory /workspace/250.edn_genbits/latest

Test location /workspace/coverage/default/251.edn_genbits.97589351
Short name T259
Test name
Test status
Simulation time 38645645 ps
CPU time 1.33 seconds
Started Mar 12 02:46:31 PM PDT 24
Finished Mar 12 02:46:33 PM PDT 24
Peak memory 214380 kb
Host smart-c85c4a40-e59a-40b8-952d-6b57ddbc5105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97589351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.edn_genbits.97589351
Directory /workspace/251.edn_genbits/latest

Test location /workspace/coverage/default/252.edn_genbits.630231008
Short name T199
Test name
Test status
Simulation time 39369706 ps
CPU time 1.55 seconds
Started Mar 12 02:46:28 PM PDT 24
Finished Mar 12 02:46:30 PM PDT 24
Peak memory 216888 kb
Host smart-696ee2f5-1edb-4ae8-8277-8f5326bc77fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630231008 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.edn_genbits.630231008
Directory /workspace/252.edn_genbits/latest

Test location /workspace/coverage/default/253.edn_genbits.455766749
Short name T446
Test name
Test status
Simulation time 83146435 ps
CPU time 1.52 seconds
Started Mar 12 02:46:35 PM PDT 24
Finished Mar 12 02:46:37 PM PDT 24
Peak memory 217168 kb
Host smart-aae9e7c1-78dc-4a3f-aa2c-f8433e2586d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455766749 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.edn_genbits.455766749
Directory /workspace/253.edn_genbits/latest

Test location /workspace/coverage/default/254.edn_genbits.3601298066
Short name T473
Test name
Test status
Simulation time 93195956 ps
CPU time 1.23 seconds
Started Mar 12 02:46:30 PM PDT 24
Finished Mar 12 02:46:31 PM PDT 24
Peak memory 215656 kb
Host smart-46bb5c1f-613e-4eec-8ba8-55faf2c84b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601298066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.edn_genbits.3601298066
Directory /workspace/254.edn_genbits/latest

Test location /workspace/coverage/default/255.edn_genbits.1193000494
Short name T525
Test name
Test status
Simulation time 36244753 ps
CPU time 1.4 seconds
Started Mar 12 02:46:33 PM PDT 24
Finished Mar 12 02:46:35 PM PDT 24
Peak memory 216872 kb
Host smart-06ddd9de-0112-49ef-8b6c-eb004fb4290b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193000494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.edn_genbits.1193000494
Directory /workspace/255.edn_genbits/latest

Test location /workspace/coverage/default/256.edn_genbits.3044848407
Short name T781
Test name
Test status
Simulation time 252201921 ps
CPU time 3.2 seconds
Started Mar 12 02:46:32 PM PDT 24
Finished Mar 12 02:46:36 PM PDT 24
Peak memory 215968 kb
Host smart-65e1a5c1-8e7d-49b4-b641-dfe1ca3f6ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044848407 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.edn_genbits.3044848407
Directory /workspace/256.edn_genbits/latest

Test location /workspace/coverage/default/257.edn_genbits.1666599096
Short name T723
Test name
Test status
Simulation time 45008636 ps
CPU time 1.15 seconds
Started Mar 12 02:46:29 PM PDT 24
Finished Mar 12 02:46:30 PM PDT 24
Peak memory 215680 kb
Host smart-ea9b2511-f824-4a05-bbea-515a4f063fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666599096 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.edn_genbits.1666599096
Directory /workspace/257.edn_genbits/latest

Test location /workspace/coverage/default/258.edn_genbits.3973227349
Short name T500
Test name
Test status
Simulation time 48085602 ps
CPU time 1.09 seconds
Started Mar 12 02:46:32 PM PDT 24
Finished Mar 12 02:46:33 PM PDT 24
Peak memory 215644 kb
Host smart-6f85829f-b1f2-4b99-a13d-d4cd925b3f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973227349 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.edn_genbits.3973227349
Directory /workspace/258.edn_genbits/latest

Test location /workspace/coverage/default/259.edn_genbits.3866814247
Short name T344
Test name
Test status
Simulation time 80670936 ps
CPU time 1.15 seconds
Started Mar 12 02:46:28 PM PDT 24
Finished Mar 12 02:46:30 PM PDT 24
Peak memory 215852 kb
Host smart-22a72c6d-6c11-4059-821a-e0bcafb1c228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866814247 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.edn_genbits.3866814247
Directory /workspace/259.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_alert.233130492
Short name T764
Test name
Test status
Simulation time 30990455 ps
CPU time 1.21 seconds
Started Mar 12 02:44:36 PM PDT 24
Finished Mar 12 02:44:37 PM PDT 24
Peak memory 214832 kb
Host smart-1ddd7993-39bf-4df3-bd87-eaf16f05061a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233130492 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert.233130492
Directory /workspace/26.edn_alert/latest

Test location /workspace/coverage/default/26.edn_alert_test.1961091710
Short name T307
Test name
Test status
Simulation time 18603213 ps
CPU time 0.96 seconds
Started Mar 12 02:44:38 PM PDT 24
Finished Mar 12 02:44:39 PM PDT 24
Peak memory 206112 kb
Host smart-f531cf06-fd91-45db-9924-b9ee711dd715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961091710 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_alert_test.1961091710
Directory /workspace/26.edn_alert_test/latest

Test location /workspace/coverage/default/26.edn_disable.1228777549
Short name T436
Test name
Test status
Simulation time 14086531 ps
CPU time 0.91 seconds
Started Mar 12 02:44:39 PM PDT 24
Finished Mar 12 02:44:40 PM PDT 24
Peak memory 214756 kb
Host smart-04914d59-8c2c-405f-8a90-ae94694f7299
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228777549 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_disable.1228777549
Directory /workspace/26.edn_disable/latest

Test location /workspace/coverage/default/26.edn_disable_auto_req_mode.1585885809
Short name T691
Test name
Test status
Simulation time 45147140 ps
CPU time 1.2 seconds
Started Mar 12 02:44:35 PM PDT 24
Finished Mar 12 02:44:36 PM PDT 24
Peak memory 216784 kb
Host smart-a854bd52-e3ea-43b3-94db-f595f9da0afc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585885809 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_d
isable_auto_req_mode.1585885809
Directory /workspace/26.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/26.edn_err.2673492058
Short name T528
Test name
Test status
Simulation time 30176707 ps
CPU time 1.02 seconds
Started Mar 12 02:44:35 PM PDT 24
Finished Mar 12 02:44:36 PM PDT 24
Peak memory 217236 kb
Host smart-22014751-47d3-4954-ab1d-c0d8f7ef73c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673492058 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_err.2673492058
Directory /workspace/26.edn_err/latest

Test location /workspace/coverage/default/26.edn_genbits.2593700556
Short name T501
Test name
Test status
Simulation time 102350600 ps
CPU time 0.99 seconds
Started Mar 12 02:44:40 PM PDT 24
Finished Mar 12 02:44:41 PM PDT 24
Peak memory 215636 kb
Host smart-e6176782-6ac1-4807-afbf-5bad22e8911e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593700556 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_genbits.2593700556
Directory /workspace/26.edn_genbits/latest

Test location /workspace/coverage/default/26.edn_intr.2056482979
Short name T357
Test name
Test status
Simulation time 23966340 ps
CPU time 1.03 seconds
Started Mar 12 02:44:39 PM PDT 24
Finished Mar 12 02:44:40 PM PDT 24
Peak memory 214740 kb
Host smart-77f32347-abb3-4fca-96af-2aa9fb72b371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056482979 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_intr.2056482979
Directory /workspace/26.edn_intr/latest

Test location /workspace/coverage/default/26.edn_smoke.4050676826
Short name T688
Test name
Test status
Simulation time 149075238 ps
CPU time 0.91 seconds
Started Mar 12 02:44:36 PM PDT 24
Finished Mar 12 02:44:37 PM PDT 24
Peak memory 214456 kb
Host smart-e766487d-76ed-4f5b-8f1e-8e1404423d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050676826 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_smoke.4050676826
Directory /workspace/26.edn_smoke/latest

Test location /workspace/coverage/default/26.edn_stress_all.3753906071
Short name T597
Test name
Test status
Simulation time 632032411 ps
CPU time 4.23 seconds
Started Mar 12 02:44:36 PM PDT 24
Finished Mar 12 02:44:40 PM PDT 24
Peak memory 215556 kb
Host smart-b969a03b-6861-4ac7-98e3-3a2526d5616d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753906071 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.edn_stress_all.3753906071
Directory /workspace/26.edn_stress_all/latest

Test location /workspace/coverage/default/26.edn_stress_all_with_rand_reset.2887141409
Short name T197
Test name
Test status
Simulation time 862055301537 ps
CPU time 1255.2 seconds
Started Mar 12 02:44:38 PM PDT 24
Finished Mar 12 03:05:34 PM PDT 24
Peak memory 221424 kb
Host smart-d13af886-0b7a-4478-88f6-bd84339c41f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887141409 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 26.edn_stress_all_with_rand_reset.2887141409
Directory /workspace/26.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.edn_genbits.4256490351
Short name T515
Test name
Test status
Simulation time 82800754 ps
CPU time 1.31 seconds
Started Mar 12 02:46:29 PM PDT 24
Finished Mar 12 02:46:31 PM PDT 24
Peak memory 214476 kb
Host smart-3552cd37-b5c8-4564-b3b4-3f72549eed0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256490351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.edn_genbits.4256490351
Directory /workspace/260.edn_genbits/latest

Test location /workspace/coverage/default/261.edn_genbits.3896314160
Short name T588
Test name
Test status
Simulation time 51068795 ps
CPU time 2.01 seconds
Started Mar 12 02:46:30 PM PDT 24
Finished Mar 12 02:46:32 PM PDT 24
Peak memory 217204 kb
Host smart-178c8812-8a9b-45f8-8c9d-1616ad13de33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896314160 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.edn_genbits.3896314160
Directory /workspace/261.edn_genbits/latest

Test location /workspace/coverage/default/262.edn_genbits.908197517
Short name T786
Test name
Test status
Simulation time 84445380 ps
CPU time 1.18 seconds
Started Mar 12 02:46:27 PM PDT 24
Finished Mar 12 02:46:28 PM PDT 24
Peak memory 215908 kb
Host smart-5604198e-b995-4d4b-a84d-b13cf30d5ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908197517 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.edn_genbits.908197517
Directory /workspace/262.edn_genbits/latest

Test location /workspace/coverage/default/263.edn_genbits.1571644000
Short name T35
Test name
Test status
Simulation time 53196685 ps
CPU time 1.81 seconds
Started Mar 12 02:46:30 PM PDT 24
Finished Mar 12 02:46:32 PM PDT 24
Peak memory 216956 kb
Host smart-d9c39c4c-2de1-4edf-9069-6cdf94a46ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571644000 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.edn_genbits.1571644000
Directory /workspace/263.edn_genbits/latest

Test location /workspace/coverage/default/264.edn_genbits.2319759636
Short name T333
Test name
Test status
Simulation time 100407152 ps
CPU time 1.71 seconds
Started Mar 12 02:46:30 PM PDT 24
Finished Mar 12 02:46:32 PM PDT 24
Peak memory 217044 kb
Host smart-3a3ca56a-8e4b-4609-b814-aebf1a214394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319759636 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.edn_genbits.2319759636
Directory /workspace/264.edn_genbits/latest

Test location /workspace/coverage/default/265.edn_genbits.4120612351
Short name T326
Test name
Test status
Simulation time 67960657 ps
CPU time 1.32 seconds
Started Mar 12 02:46:26 PM PDT 24
Finished Mar 12 02:46:28 PM PDT 24
Peak memory 216976 kb
Host smart-8755cc35-c36b-4c94-bbe4-609e3c5b2df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120612351 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.edn_genbits.4120612351
Directory /workspace/265.edn_genbits/latest

Test location /workspace/coverage/default/266.edn_genbits.4008551584
Short name T726
Test name
Test status
Simulation time 45517992 ps
CPU time 1.45 seconds
Started Mar 12 02:46:30 PM PDT 24
Finished Mar 12 02:46:32 PM PDT 24
Peak memory 214452 kb
Host smart-123f7fd0-6f0e-48f9-915d-8be0fbb8c6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008551584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.edn_genbits.4008551584
Directory /workspace/266.edn_genbits/latest

Test location /workspace/coverage/default/267.edn_genbits.1710460777
Short name T401
Test name
Test status
Simulation time 150446082 ps
CPU time 2.88 seconds
Started Mar 12 02:46:35 PM PDT 24
Finished Mar 12 02:46:38 PM PDT 24
Peak memory 217048 kb
Host smart-95a3f41d-ec6a-421e-a1f7-d6c02049e1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710460777 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.edn_genbits.1710460777
Directory /workspace/267.edn_genbits/latest

Test location /workspace/coverage/default/268.edn_genbits.2311225487
Short name T669
Test name
Test status
Simulation time 207692798 ps
CPU time 3.2 seconds
Started Mar 12 02:46:30 PM PDT 24
Finished Mar 12 02:46:33 PM PDT 24
Peak memory 218432 kb
Host smart-3fee2f01-b3b0-44f4-baff-1d88d2e9d019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311225487 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.edn_genbits.2311225487
Directory /workspace/268.edn_genbits/latest

Test location /workspace/coverage/default/269.edn_genbits.562007416
Short name T286
Test name
Test status
Simulation time 47973079 ps
CPU time 1.73 seconds
Started Mar 12 02:46:30 PM PDT 24
Finished Mar 12 02:46:31 PM PDT 24
Peak memory 216956 kb
Host smart-9fdc6d39-866f-4e2f-966b-2b820972caaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562007416 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.edn_genbits.562007416
Directory /workspace/269.edn_genbits/latest

Test location /workspace/coverage/default/27.edn_alert.2703503997
Short name T249
Test name
Test status
Simulation time 47849654 ps
CPU time 1.21 seconds
Started Mar 12 02:44:38 PM PDT 24
Finished Mar 12 02:44:39 PM PDT 24
Peak memory 214808 kb
Host smart-781509e7-7e77-412d-b429-b0002e58fc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703503997 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert.2703503997
Directory /workspace/27.edn_alert/latest

Test location /workspace/coverage/default/27.edn_alert_test.725918268
Short name T573
Test name
Test status
Simulation time 23282264 ps
CPU time 0.97 seconds
Started Mar 12 02:44:38 PM PDT 24
Finished Mar 12 02:44:39 PM PDT 24
Peak memory 206100 kb
Host smart-c5b04b11-4ec8-4ef7-8fb4-b5a7a7a6c86b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725918268 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_alert_test.725918268
Directory /workspace/27.edn_alert_test/latest

Test location /workspace/coverage/default/27.edn_disable.3544536000
Short name T120
Test name
Test status
Simulation time 39660701 ps
CPU time 0.84 seconds
Started Mar 12 02:44:36 PM PDT 24
Finished Mar 12 02:44:37 PM PDT 24
Peak memory 214944 kb
Host smart-a5a69853-6bf5-445a-99fc-23e7822223cf
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544536000 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_disable.3544536000
Directory /workspace/27.edn_disable/latest

Test location /workspace/coverage/default/27.edn_err.2554249470
Short name T103
Test name
Test status
Simulation time 22876539 ps
CPU time 0.97 seconds
Started Mar 12 02:44:36 PM PDT 24
Finished Mar 12 02:44:37 PM PDT 24
Peak memory 217320 kb
Host smart-65f069b1-126c-48f4-82ee-c04cd6bd252d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554249470 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_err.2554249470
Directory /workspace/27.edn_err/latest

Test location /workspace/coverage/default/27.edn_intr.3854076915
Short name T625
Test name
Test status
Simulation time 23089649 ps
CPU time 1.15 seconds
Started Mar 12 02:44:39 PM PDT 24
Finished Mar 12 02:44:41 PM PDT 24
Peak memory 222412 kb
Host smart-539eff85-2537-4db2-9bcc-f491d53a1780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854076915 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_intr.3854076915
Directory /workspace/27.edn_intr/latest

Test location /workspace/coverage/default/27.edn_smoke.1382910229
Short name T346
Test name
Test status
Simulation time 50806157 ps
CPU time 0.94 seconds
Started Mar 12 02:44:36 PM PDT 24
Finished Mar 12 02:44:37 PM PDT 24
Peak memory 214452 kb
Host smart-fd736b54-b87f-4192-9a83-8406f8852bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382910229 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_smoke.1382910229
Directory /workspace/27.edn_smoke/latest

Test location /workspace/coverage/default/27.edn_stress_all.1178272896
Short name T450
Test name
Test status
Simulation time 244261025 ps
CPU time 4.84 seconds
Started Mar 12 02:44:37 PM PDT 24
Finished Mar 12 02:44:42 PM PDT 24
Peak memory 218376 kb
Host smart-e2a1c88a-ed6c-4c20-a91d-42ae7ca05126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178272896 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.edn_stress_all.1178272896
Directory /workspace/27.edn_stress_all/latest

Test location /workspace/coverage/default/27.edn_stress_all_with_rand_reset.930363439
Short name T663
Test name
Test status
Simulation time 320945384794 ps
CPU time 2170.09 seconds
Started Mar 12 02:44:36 PM PDT 24
Finished Mar 12 03:20:46 PM PDT 24
Peak memory 228392 kb
Host smart-f1d58819-3369-4a15-b21c-4e1e8decb9cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930363439 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.edn_stress_all_with_rand_reset.930363439
Directory /workspace/27.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.edn_genbits.421500002
Short name T519
Test name
Test status
Simulation time 25662728 ps
CPU time 1.24 seconds
Started Mar 12 02:46:27 PM PDT 24
Finished Mar 12 02:46:29 PM PDT 24
Peak memory 214452 kb
Host smart-e0735061-c749-4a54-95b8-baf97f2a8524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421500002 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.edn_genbits.421500002
Directory /workspace/270.edn_genbits/latest

Test location /workspace/coverage/default/271.edn_genbits.1648270787
Short name T349
Test name
Test status
Simulation time 39480446 ps
CPU time 1.53 seconds
Started Mar 12 02:46:35 PM PDT 24
Finished Mar 12 02:46:36 PM PDT 24
Peak memory 216976 kb
Host smart-b6e585f4-fd13-47ef-8dba-bbaff0ed39fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648270787 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.edn_genbits.1648270787
Directory /workspace/271.edn_genbits/latest

Test location /workspace/coverage/default/272.edn_genbits.2935272095
Short name T530
Test name
Test status
Simulation time 82137987 ps
CPU time 1.16 seconds
Started Mar 12 02:46:47 PM PDT 24
Finished Mar 12 02:46:48 PM PDT 24
Peak memory 215848 kb
Host smart-6dc5d92b-009b-41d6-83d9-0eb2695ce719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935272095 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.edn_genbits.2935272095
Directory /workspace/272.edn_genbits/latest

Test location /workspace/coverage/default/273.edn_genbits.2328133798
Short name T414
Test name
Test status
Simulation time 124335417 ps
CPU time 1.58 seconds
Started Mar 12 02:46:41 PM PDT 24
Finished Mar 12 02:46:43 PM PDT 24
Peak memory 217292 kb
Host smart-b95eca92-e46a-4bff-bc89-3346c72d579a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328133798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.edn_genbits.2328133798
Directory /workspace/273.edn_genbits/latest

Test location /workspace/coverage/default/274.edn_genbits.506307354
Short name T763
Test name
Test status
Simulation time 46893867 ps
CPU time 1.2 seconds
Started Mar 12 02:46:46 PM PDT 24
Finished Mar 12 02:46:48 PM PDT 24
Peak memory 215792 kb
Host smart-5c118b3a-029e-41f5-b53c-58e9bc762553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506307354 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.edn_genbits.506307354
Directory /workspace/274.edn_genbits/latest

Test location /workspace/coverage/default/275.edn_genbits.3608015735
Short name T391
Test name
Test status
Simulation time 45445897 ps
CPU time 1.07 seconds
Started Mar 12 02:46:38 PM PDT 24
Finished Mar 12 02:46:40 PM PDT 24
Peak memory 215896 kb
Host smart-222b2f74-97af-4a6b-a72e-74757750c359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608015735 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.edn_genbits.3608015735
Directory /workspace/275.edn_genbits/latest

Test location /workspace/coverage/default/276.edn_genbits.4018047127
Short name T807
Test name
Test status
Simulation time 26665007 ps
CPU time 1.14 seconds
Started Mar 12 02:46:42 PM PDT 24
Finished Mar 12 02:46:43 PM PDT 24
Peak memory 215544 kb
Host smart-08d0ff87-90c3-4f12-895d-fe9ffe654ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018047127 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.edn_genbits.4018047127
Directory /workspace/276.edn_genbits/latest

Test location /workspace/coverage/default/277.edn_genbits.998470500
Short name T15
Test name
Test status
Simulation time 56282325 ps
CPU time 1.32 seconds
Started Mar 12 02:46:35 PM PDT 24
Finished Mar 12 02:46:36 PM PDT 24
Peak memory 217936 kb
Host smart-6fc7c7c2-7f48-4817-b075-f99c6bfada40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998470500 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.edn_genbits.998470500
Directory /workspace/277.edn_genbits/latest

Test location /workspace/coverage/default/278.edn_genbits.745755645
Short name T598
Test name
Test status
Simulation time 113467081 ps
CPU time 0.91 seconds
Started Mar 12 02:46:35 PM PDT 24
Finished Mar 12 02:46:37 PM PDT 24
Peak memory 215712 kb
Host smart-8d2ce960-4229-48fc-ae3f-e87fdec04454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745755645 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.edn_genbits.745755645
Directory /workspace/278.edn_genbits/latest

Test location /workspace/coverage/default/279.edn_genbits.2198573304
Short name T148
Test name
Test status
Simulation time 87655394 ps
CPU time 1.13 seconds
Started Mar 12 02:46:37 PM PDT 24
Finished Mar 12 02:46:39 PM PDT 24
Peak memory 217132 kb
Host smart-6a0bf24c-66a1-4a2b-ba80-e02d9afa5f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198573304 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.edn_genbits.2198573304
Directory /workspace/279.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_alert.2410197015
Short name T541
Test name
Test status
Simulation time 25654114 ps
CPU time 1.16 seconds
Started Mar 12 02:44:37 PM PDT 24
Finished Mar 12 02:44:38 PM PDT 24
Peak memory 214860 kb
Host smart-0cad4265-226a-46dc-be61-4db3ea132e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410197015 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert.2410197015
Directory /workspace/28.edn_alert/latest

Test location /workspace/coverage/default/28.edn_alert_test.3959858626
Short name T355
Test name
Test status
Simulation time 17352872 ps
CPU time 0.96 seconds
Started Mar 12 02:44:48 PM PDT 24
Finished Mar 12 02:44:50 PM PDT 24
Peak memory 204868 kb
Host smart-e21a275b-096f-43b6-b44d-75deb55ec9c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959858626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_alert_test.3959858626
Directory /workspace/28.edn_alert_test/latest

Test location /workspace/coverage/default/28.edn_disable.1967889971
Short name T367
Test name
Test status
Simulation time 11322416 ps
CPU time 0.87 seconds
Started Mar 12 02:44:43 PM PDT 24
Finished Mar 12 02:44:44 PM PDT 24
Peak memory 214672 kb
Host smart-8b0781b1-6b75-4d36-95a8-3c2027ee59fe
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967889971 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_disable.1967889971
Directory /workspace/28.edn_disable/latest

Test location /workspace/coverage/default/28.edn_err.2742931833
Short name T782
Test name
Test status
Simulation time 20824550 ps
CPU time 1.05 seconds
Started Mar 12 02:44:39 PM PDT 24
Finished Mar 12 02:44:40 PM PDT 24
Peak memory 217004 kb
Host smart-8bdbcb65-a522-4a9d-88f8-cde27651e1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742931833 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_err.2742931833
Directory /workspace/28.edn_err/latest

Test location /workspace/coverage/default/28.edn_genbits.1682864436
Short name T648
Test name
Test status
Simulation time 38291959 ps
CPU time 1.61 seconds
Started Mar 12 02:44:39 PM PDT 24
Finished Mar 12 02:44:40 PM PDT 24
Peak memory 215956 kb
Host smart-670d45d4-9e12-4e8d-9b2c-0abf0a1a5b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682864436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_genbits.1682864436
Directory /workspace/28.edn_genbits/latest

Test location /workspace/coverage/default/28.edn_intr.4169080979
Short name T641
Test name
Test status
Simulation time 21027490 ps
CPU time 1.07 seconds
Started Mar 12 02:44:37 PM PDT 24
Finished Mar 12 02:44:38 PM PDT 24
Peak memory 214756 kb
Host smart-5ab057a7-ddd6-4c1c-a66e-5a51a1332101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169080979 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_intr.4169080979
Directory /workspace/28.edn_intr/latest

Test location /workspace/coverage/default/28.edn_smoke.3133736100
Short name T601
Test name
Test status
Simulation time 125892236 ps
CPU time 0.95 seconds
Started Mar 12 02:44:39 PM PDT 24
Finished Mar 12 02:44:40 PM PDT 24
Peak memory 214456 kb
Host smart-aacc7820-347c-45fd-a5e5-c1135bb536f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133736100 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_smoke.3133736100
Directory /workspace/28.edn_smoke/latest

Test location /workspace/coverage/default/28.edn_stress_all.479432001
Short name T143
Test name
Test status
Simulation time 650367302 ps
CPU time 3.92 seconds
Started Mar 12 02:44:38 PM PDT 24
Finished Mar 12 02:44:42 PM PDT 24
Peak memory 215568 kb
Host smart-186c3697-18b0-46b2-b42f-a79927db5d88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479432001 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.edn_stress_all.479432001
Directory /workspace/28.edn_stress_all/latest

Test location /workspace/coverage/default/28.edn_stress_all_with_rand_reset.2266608006
Short name T456
Test name
Test status
Simulation time 70107929338 ps
CPU time 1592.65 seconds
Started Mar 12 02:44:34 PM PDT 24
Finished Mar 12 03:11:07 PM PDT 24
Peak memory 224828 kb
Host smart-be2e954b-0bd4-464d-b82d-e3d5d23b52e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266608006 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.edn_stress_all_with_rand_reset.2266608006
Directory /workspace/28.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/280.edn_genbits.534770801
Short name T137
Test name
Test status
Simulation time 4569244833 ps
CPU time 92.61 seconds
Started Mar 12 02:46:39 PM PDT 24
Finished Mar 12 02:48:12 PM PDT 24
Peak memory 219132 kb
Host smart-dd7dc23c-f6d9-4532-8b7a-67575923e566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534770801 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.edn_genbits.534770801
Directory /workspace/280.edn_genbits/latest

Test location /workspace/coverage/default/281.edn_genbits.3288680423
Short name T787
Test name
Test status
Simulation time 68620499 ps
CPU time 1.35 seconds
Started Mar 12 02:46:37 PM PDT 24
Finished Mar 12 02:46:39 PM PDT 24
Peak memory 216904 kb
Host smart-f8ffbe65-2e11-45e5-a2e4-6010abf2417d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288680423 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.edn_genbits.3288680423
Directory /workspace/281.edn_genbits/latest

Test location /workspace/coverage/default/282.edn_genbits.1458944022
Short name T729
Test name
Test status
Simulation time 96863525 ps
CPU time 1.36 seconds
Started Mar 12 02:46:37 PM PDT 24
Finished Mar 12 02:46:39 PM PDT 24
Peak memory 214448 kb
Host smart-80025c4d-d259-4503-a3ea-8601f70ff5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458944022 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.edn_genbits.1458944022
Directory /workspace/282.edn_genbits/latest

Test location /workspace/coverage/default/283.edn_genbits.564168817
Short name T513
Test name
Test status
Simulation time 85047621 ps
CPU time 1.15 seconds
Started Mar 12 02:46:36 PM PDT 24
Finished Mar 12 02:46:38 PM PDT 24
Peak memory 218440 kb
Host smart-91ecefed-f22f-4d80-b856-a99fa0871dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564168817 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.edn_genbits.564168817
Directory /workspace/283.edn_genbits/latest

Test location /workspace/coverage/default/284.edn_genbits.2598233846
Short name T323
Test name
Test status
Simulation time 194259167 ps
CPU time 1.63 seconds
Started Mar 12 02:46:37 PM PDT 24
Finished Mar 12 02:46:40 PM PDT 24
Peak memory 217168 kb
Host smart-54442c86-3a83-437f-8114-cfd8dbc30421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598233846 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.edn_genbits.2598233846
Directory /workspace/284.edn_genbits/latest

Test location /workspace/coverage/default/285.edn_genbits.2293453542
Short name T46
Test name
Test status
Simulation time 77040110 ps
CPU time 1.26 seconds
Started Mar 12 02:46:47 PM PDT 24
Finished Mar 12 02:46:48 PM PDT 24
Peak memory 217832 kb
Host smart-62d0dfed-7416-41cd-96dc-104d2346812f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293453542 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.edn_genbits.2293453542
Directory /workspace/285.edn_genbits/latest

Test location /workspace/coverage/default/286.edn_genbits.2690496866
Short name T507
Test name
Test status
Simulation time 46452706 ps
CPU time 1.43 seconds
Started Mar 12 02:46:35 PM PDT 24
Finished Mar 12 02:46:38 PM PDT 24
Peak memory 215492 kb
Host smart-1680d256-93e6-4c02-8a1e-935140ccc12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690496866 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.edn_genbits.2690496866
Directory /workspace/286.edn_genbits/latest

Test location /workspace/coverage/default/287.edn_genbits.2269331569
Short name T795
Test name
Test status
Simulation time 55418417 ps
CPU time 1.33 seconds
Started Mar 12 02:46:35 PM PDT 24
Finished Mar 12 02:46:36 PM PDT 24
Peak memory 218608 kb
Host smart-9327ce27-fb17-40ab-b106-24720874a032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269331569 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.edn_genbits.2269331569
Directory /workspace/287.edn_genbits/latest

Test location /workspace/coverage/default/288.edn_genbits.1614459584
Short name T321
Test name
Test status
Simulation time 112672437 ps
CPU time 1.37 seconds
Started Mar 12 02:46:42 PM PDT 24
Finished Mar 12 02:46:44 PM PDT 24
Peak memory 217064 kb
Host smart-ed8f7892-3aa7-4df1-91bb-a7893cb480d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614459584 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.edn_genbits.1614459584
Directory /workspace/288.edn_genbits/latest

Test location /workspace/coverage/default/289.edn_genbits.3488948912
Short name T698
Test name
Test status
Simulation time 51515862 ps
CPU time 1.51 seconds
Started Mar 12 02:46:42 PM PDT 24
Finished Mar 12 02:46:44 PM PDT 24
Peak memory 216944 kb
Host smart-5ce96afa-49e4-41b9-b13a-260d1eb81b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488948912 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.edn_genbits.3488948912
Directory /workspace/289.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_alert.2290847599
Short name T235
Test name
Test status
Simulation time 30500227 ps
CPU time 1.16 seconds
Started Mar 12 02:44:51 PM PDT 24
Finished Mar 12 02:44:52 PM PDT 24
Peak memory 214740 kb
Host smart-92146a44-11a5-4b84-baaa-a9b75346fd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290847599 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert.2290847599
Directory /workspace/29.edn_alert/latest

Test location /workspace/coverage/default/29.edn_alert_test.1821418966
Short name T386
Test name
Test status
Simulation time 26065399 ps
CPU time 0.86 seconds
Started Mar 12 02:44:49 PM PDT 24
Finished Mar 12 02:44:50 PM PDT 24
Peak memory 206104 kb
Host smart-23331cde-8a0d-42fb-9d89-f288adad1010
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821418966 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_alert_test.1821418966
Directory /workspace/29.edn_alert_test/latest

Test location /workspace/coverage/default/29.edn_disable.2914201519
Short name T154
Test name
Test status
Simulation time 12705507 ps
CPU time 0.82 seconds
Started Mar 12 02:44:45 PM PDT 24
Finished Mar 12 02:44:46 PM PDT 24
Peak memory 214944 kb
Host smart-5f531e6c-9f7c-4aa9-b929-6bdc471ae2db
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914201519 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_disable.2914201519
Directory /workspace/29.edn_disable/latest

Test location /workspace/coverage/default/29.edn_err.299403819
Short name T584
Test name
Test status
Simulation time 25501435 ps
CPU time 1.3 seconds
Started Mar 12 02:44:45 PM PDT 24
Finished Mar 12 02:44:47 PM PDT 24
Peak memory 219312 kb
Host smart-8f7ba458-67c8-4b1c-9084-26ac12032f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299403819 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_err.299403819
Directory /workspace/29.edn_err/latest

Test location /workspace/coverage/default/29.edn_genbits.132602144
Short name T62
Test name
Test status
Simulation time 363063315 ps
CPU time 1.16 seconds
Started Mar 12 02:44:50 PM PDT 24
Finished Mar 12 02:44:51 PM PDT 24
Peak memory 215724 kb
Host smart-72912ad6-d7ec-4b89-b39d-1df378bd8728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132602144 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_genbits.132602144
Directory /workspace/29.edn_genbits/latest

Test location /workspace/coverage/default/29.edn_intr.941432641
Short name T744
Test name
Test status
Simulation time 38372078 ps
CPU time 0.88 seconds
Started Mar 12 02:44:46 PM PDT 24
Finished Mar 12 02:44:47 PM PDT 24
Peak memory 214608 kb
Host smart-67d7695a-fedf-4939-977d-2417b6e9bf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941432641 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_intr.941432641
Directory /workspace/29.edn_intr/latest

Test location /workspace/coverage/default/29.edn_smoke.1681778344
Short name T570
Test name
Test status
Simulation time 26398281 ps
CPU time 0.89 seconds
Started Mar 12 02:44:48 PM PDT 24
Finished Mar 12 02:44:49 PM PDT 24
Peak memory 205724 kb
Host smart-4d669956-83f6-4dc3-bc20-866a666de6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681778344 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_smoke.1681778344
Directory /workspace/29.edn_smoke/latest

Test location /workspace/coverage/default/29.edn_stress_all.784891686
Short name T300
Test name
Test status
Simulation time 45259713 ps
CPU time 1.04 seconds
Started Mar 12 02:44:44 PM PDT 24
Finished Mar 12 02:44:46 PM PDT 24
Peak memory 214460 kb
Host smart-b07ec968-513c-4062-a15b-6849c07578a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784891686 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.edn_stress_all.784891686
Directory /workspace/29.edn_stress_all/latest

Test location /workspace/coverage/default/29.edn_stress_all_with_rand_reset.1618033740
Short name T728
Test name
Test status
Simulation time 105336249055 ps
CPU time 1200.2 seconds
Started Mar 12 02:44:50 PM PDT 24
Finished Mar 12 03:04:51 PM PDT 24
Peak memory 220812 kb
Host smart-d5ea0e5f-cb2e-4be1-b90a-8599b2a75b52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618033740 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.edn_stress_all_with_rand_reset.1618033740
Directory /workspace/29.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/290.edn_genbits.2301270655
Short name T835
Test name
Test status
Simulation time 27122118 ps
CPU time 1.24 seconds
Started Mar 12 02:46:38 PM PDT 24
Finished Mar 12 02:46:39 PM PDT 24
Peak memory 214424 kb
Host smart-9c25a208-e40a-463a-9f38-a42cd030f3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301270655 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.edn_genbits.2301270655
Directory /workspace/290.edn_genbits/latest

Test location /workspace/coverage/default/291.edn_genbits.308489395
Short name T506
Test name
Test status
Simulation time 40615902 ps
CPU time 1.38 seconds
Started Mar 12 02:46:47 PM PDT 24
Finished Mar 12 02:46:48 PM PDT 24
Peak memory 215576 kb
Host smart-9b004eab-2101-4552-b335-75b95bb1a391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308489395 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.edn_genbits.308489395
Directory /workspace/291.edn_genbits/latest

Test location /workspace/coverage/default/292.edn_genbits.2536473429
Short name T293
Test name
Test status
Simulation time 33698377 ps
CPU time 1.36 seconds
Started Mar 12 02:46:34 PM PDT 24
Finished Mar 12 02:46:35 PM PDT 24
Peak memory 218416 kb
Host smart-ae7aa0a8-0cb3-4ca5-9841-593673430c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536473429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.edn_genbits.2536473429
Directory /workspace/292.edn_genbits/latest

Test location /workspace/coverage/default/293.edn_genbits.606097283
Short name T366
Test name
Test status
Simulation time 97384303 ps
CPU time 1.23 seconds
Started Mar 12 02:46:36 PM PDT 24
Finished Mar 12 02:46:39 PM PDT 24
Peak memory 217016 kb
Host smart-a1a8ab32-5ef2-483e-9724-1864aa897359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606097283 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.edn_genbits.606097283
Directory /workspace/293.edn_genbits/latest

Test location /workspace/coverage/default/295.edn_genbits.1762174847
Short name T709
Test name
Test status
Simulation time 31764416 ps
CPU time 1.25 seconds
Started Mar 12 02:46:35 PM PDT 24
Finished Mar 12 02:46:36 PM PDT 24
Peak memory 215528 kb
Host smart-ad78aa71-5abd-4701-8b53-aeb4b1963077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762174847 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.edn_genbits.1762174847
Directory /workspace/295.edn_genbits/latest

Test location /workspace/coverage/default/296.edn_genbits.1863207155
Short name T704
Test name
Test status
Simulation time 170996497 ps
CPU time 1.27 seconds
Started Mar 12 02:46:38 PM PDT 24
Finished Mar 12 02:46:39 PM PDT 24
Peak memory 217172 kb
Host smart-0dea0881-c538-47fc-b64c-859ccdbdb22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863207155 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.edn_genbits.1863207155
Directory /workspace/296.edn_genbits/latest

Test location /workspace/coverage/default/297.edn_genbits.553712113
Short name T272
Test name
Test status
Simulation time 278729616 ps
CPU time 3.95 seconds
Started Mar 12 02:46:36 PM PDT 24
Finished Mar 12 02:46:41 PM PDT 24
Peak memory 217840 kb
Host smart-9be8d887-359a-4aff-994a-c0ab8b401e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553712113 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.edn_genbits.553712113
Directory /workspace/297.edn_genbits/latest

Test location /workspace/coverage/default/298.edn_genbits.3762041138
Short name T547
Test name
Test status
Simulation time 179039654 ps
CPU time 1.35 seconds
Started Mar 12 02:46:36 PM PDT 24
Finished Mar 12 02:46:38 PM PDT 24
Peak memory 215812 kb
Host smart-79395579-4072-4f28-821b-d8cd5f2d028b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762041138 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.edn_genbits.3762041138
Directory /workspace/298.edn_genbits/latest

Test location /workspace/coverage/default/299.edn_genbits.3895875388
Short name T593
Test name
Test status
Simulation time 27108268 ps
CPU time 1.28 seconds
Started Mar 12 02:46:35 PM PDT 24
Finished Mar 12 02:46:37 PM PDT 24
Peak memory 215728 kb
Host smart-c8132c01-3739-4a5d-9871-539f954dccf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895875388 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.edn_genbits.3895875388
Directory /workspace/299.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_alert.4159469591
Short name T756
Test name
Test status
Simulation time 44057473 ps
CPU time 1.15 seconds
Started Mar 12 02:43:09 PM PDT 24
Finished Mar 12 02:43:10 PM PDT 24
Peak memory 214864 kb
Host smart-823e272e-5dda-4d36-808c-000596e038b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159469591 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert.4159469591
Directory /workspace/3.edn_alert/latest

Test location /workspace/coverage/default/3.edn_alert_test.3989330677
Short name T667
Test name
Test status
Simulation time 18847814 ps
CPU time 0.91 seconds
Started Mar 12 02:43:08 PM PDT 24
Finished Mar 12 02:43:09 PM PDT 24
Peak memory 206080 kb
Host smart-149bf7e8-65d0-431f-a73a-75cf485a4d28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989330677 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_alert_test.3989330677
Directory /workspace/3.edn_alert_test/latest

Test location /workspace/coverage/default/3.edn_disable.1314457787
Short name T551
Test name
Test status
Simulation time 13464511 ps
CPU time 0.9 seconds
Started Mar 12 02:43:12 PM PDT 24
Finished Mar 12 02:43:13 PM PDT 24
Peak memory 215036 kb
Host smart-6b621724-4f55-4ada-8692-518fc23f413a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314457787 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_disable.1314457787
Directory /workspace/3.edn_disable/latest

Test location /workspace/coverage/default/3.edn_err.4272133264
Short name T638
Test name
Test status
Simulation time 31640338 ps
CPU time 0.86 seconds
Started Mar 12 02:43:11 PM PDT 24
Finished Mar 12 02:43:13 PM PDT 24
Peak memory 216900 kb
Host smart-56dd2452-74ba-46c3-a66b-f91ec4d0b00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272133264 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_err.4272133264
Directory /workspace/3.edn_err/latest

Test location /workspace/coverage/default/3.edn_genbits.756044186
Short name T509
Test name
Test status
Simulation time 33629370 ps
CPU time 1.32 seconds
Started Mar 12 02:43:11 PM PDT 24
Finished Mar 12 02:43:12 PM PDT 24
Peak memory 216964 kb
Host smart-416c7b82-bfdd-4e86-af49-54dc04279812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756044186 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_genbits.756044186
Directory /workspace/3.edn_genbits/latest

Test location /workspace/coverage/default/3.edn_intr.3057579895
Short name T753
Test name
Test status
Simulation time 33206677 ps
CPU time 0.98 seconds
Started Mar 12 02:43:13 PM PDT 24
Finished Mar 12 02:43:15 PM PDT 24
Peak memory 214616 kb
Host smart-1257b9ba-e360-4934-9fff-adf2cd9dec53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057579895 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_intr.3057579895
Directory /workspace/3.edn_intr/latest

Test location /workspace/coverage/default/3.edn_sec_cm.766083411
Short name T22
Test name
Test status
Simulation time 1292195316 ps
CPU time 5.14 seconds
Started Mar 12 02:43:10 PM PDT 24
Finished Mar 12 02:43:16 PM PDT 24
Peak memory 234784 kb
Host smart-f29beea6-8d65-4f8f-a925-04ea1f1d786e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766083411 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.766083411
Directory /workspace/3.edn_sec_cm/latest

Test location /workspace/coverage/default/3.edn_smoke.2360189531
Short name T311
Test name
Test status
Simulation time 24029517 ps
CPU time 0.9 seconds
Started Mar 12 02:43:12 PM PDT 24
Finished Mar 12 02:43:14 PM PDT 24
Peak memory 214456 kb
Host smart-f08cd0c0-3779-4c60-bd39-86525e5c2364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360189531 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_smoke.2360189531
Directory /workspace/3.edn_smoke/latest

Test location /workspace/coverage/default/3.edn_stress_all.2156140711
Short name T612
Test name
Test status
Simulation time 592977854 ps
CPU time 5.89 seconds
Started Mar 12 02:43:12 PM PDT 24
Finished Mar 12 02:43:18 PM PDT 24
Peak memory 214484 kb
Host smart-6c30dffc-e470-4b61-87f2-e1a28be5dbc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156140711 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_stress_all.2156140711
Directory /workspace/3.edn_stress_all/latest

Test location /workspace/coverage/default/3.edn_stress_all_with_rand_reset.626833999
Short name T189
Test name
Test status
Simulation time 67025191305 ps
CPU time 1551.36 seconds
Started Mar 12 02:43:10 PM PDT 24
Finished Mar 12 03:09:02 PM PDT 24
Peak memory 221744 kb
Host smart-457114d9-5061-467d-91b0-94819281118a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626833999 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.edn_stress_all_with_rand_reset.626833999
Directory /workspace/3.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.edn_alert_test.1977193225
Short name T306
Test name
Test status
Simulation time 120592073 ps
CPU time 0.99 seconds
Started Mar 12 02:44:47 PM PDT 24
Finished Mar 12 02:44:48 PM PDT 24
Peak memory 206096 kb
Host smart-fcf56e9e-e1a2-48ca-8bd1-a487e8a9764f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977193225 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_alert_test.1977193225
Directory /workspace/30.edn_alert_test/latest

Test location /workspace/coverage/default/30.edn_disable_auto_req_mode.2827748908
Short name T577
Test name
Test status
Simulation time 50106924 ps
CPU time 1.13 seconds
Started Mar 12 02:44:46 PM PDT 24
Finished Mar 12 02:44:47 PM PDT 24
Peak memory 215504 kb
Host smart-5c114ae9-7412-438a-8196-7fb727dd699e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827748908 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_d
isable_auto_req_mode.2827748908
Directory /workspace/30.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/30.edn_err.3145490924
Short name T86
Test name
Test status
Simulation time 54996839 ps
CPU time 1.02 seconds
Started Mar 12 02:44:46 PM PDT 24
Finished Mar 12 02:44:47 PM PDT 24
Peak memory 217348 kb
Host smart-8fca1e91-a60c-4d6a-95bc-9965533b36c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145490924 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_err.3145490924
Directory /workspace/30.edn_err/latest

Test location /workspace/coverage/default/30.edn_genbits.1410551197
Short name T771
Test name
Test status
Simulation time 40656536 ps
CPU time 1.69 seconds
Started Mar 12 02:44:47 PM PDT 24
Finished Mar 12 02:44:49 PM PDT 24
Peak memory 216780 kb
Host smart-38de5f49-0377-4faf-8729-adad8e79b7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410551197 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_genbits.1410551197
Directory /workspace/30.edn_genbits/latest

Test location /workspace/coverage/default/30.edn_intr.365521075
Short name T354
Test name
Test status
Simulation time 21007391 ps
CPU time 1.17 seconds
Started Mar 12 02:44:46 PM PDT 24
Finished Mar 12 02:44:47 PM PDT 24
Peak memory 214768 kb
Host smart-1db37a59-34c8-44fc-a4de-f44fbe9b6853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365521075 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_intr.365521075
Directory /workspace/30.edn_intr/latest

Test location /workspace/coverage/default/30.edn_smoke.3935881684
Short name T443
Test name
Test status
Simulation time 27448294 ps
CPU time 0.94 seconds
Started Mar 12 02:44:46 PM PDT 24
Finished Mar 12 02:44:47 PM PDT 24
Peak memory 214468 kb
Host smart-79ed638e-8c34-45ae-97a8-316dcf2ab7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935881684 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_smoke.3935881684
Directory /workspace/30.edn_smoke/latest

Test location /workspace/coverage/default/30.edn_stress_all.1860491273
Short name T592
Test name
Test status
Simulation time 186140210 ps
CPU time 2.16 seconds
Started Mar 12 02:44:47 PM PDT 24
Finished Mar 12 02:44:49 PM PDT 24
Peak memory 214444 kb
Host smart-c512b473-dffe-4a4a-8660-9822f49d3225
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860491273 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.edn_stress_all.1860491273
Directory /workspace/30.edn_stress_all/latest

Test location /workspace/coverage/default/30.edn_stress_all_with_rand_reset.3749368147
Short name T194
Test name
Test status
Simulation time 37471222886 ps
CPU time 851.68 seconds
Started Mar 12 02:44:44 PM PDT 24
Finished Mar 12 02:58:56 PM PDT 24
Peak memory 216968 kb
Host smart-6c7f057b-a9ba-49aa-9870-82ea26937b43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749368147 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 30.edn_stress_all_with_rand_reset.3749368147
Directory /workspace/30.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.edn_alert.2878125345
Short name T178
Test name
Test status
Simulation time 154799287 ps
CPU time 1.41 seconds
Started Mar 12 02:44:48 PM PDT 24
Finished Mar 12 02:44:50 PM PDT 24
Peak memory 214780 kb
Host smart-9ccc0616-283e-480b-8fc9-0154f92575d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878125345 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert.2878125345
Directory /workspace/31.edn_alert/latest

Test location /workspace/coverage/default/31.edn_alert_test.3604028963
Short name T374
Test name
Test status
Simulation time 26552699 ps
CPU time 0.9 seconds
Started Mar 12 02:44:47 PM PDT 24
Finished Mar 12 02:44:48 PM PDT 24
Peak memory 206100 kb
Host smart-6230f3a1-9acb-4b72-8e0b-8453796073d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604028963 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_alert_test.3604028963
Directory /workspace/31.edn_alert_test/latest

Test location /workspace/coverage/default/31.edn_disable.108605409
Short name T479
Test name
Test status
Simulation time 22014628 ps
CPU time 0.82 seconds
Started Mar 12 02:44:45 PM PDT 24
Finished Mar 12 02:44:46 PM PDT 24
Peak memory 214924 kb
Host smart-d5285b6c-9204-4b45-80c1-56ec211ae4b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108605409 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_disable.108605409
Directory /workspace/31.edn_disable/latest

Test location /workspace/coverage/default/31.edn_disable_auto_req_mode.717394417
Short name T818
Test name
Test status
Simulation time 223769100 ps
CPU time 1.16 seconds
Started Mar 12 02:44:47 PM PDT 24
Finished Mar 12 02:44:48 PM PDT 24
Peak memory 215500 kb
Host smart-c067af50-837e-4560-a274-ebd830814a33
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717394417 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_di
sable_auto_req_mode.717394417
Directory /workspace/31.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/31.edn_err.2753081499
Short name T40
Test name
Test status
Simulation time 23525616 ps
CPU time 1.02 seconds
Started Mar 12 02:44:45 PM PDT 24
Finished Mar 12 02:44:46 PM PDT 24
Peak memory 222380 kb
Host smart-2b48b649-6597-4a75-b698-39424c9160c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753081499 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_err.2753081499
Directory /workspace/31.edn_err/latest

Test location /workspace/coverage/default/31.edn_genbits.1593279499
Short name T316
Test name
Test status
Simulation time 59992913 ps
CPU time 1.24 seconds
Started Mar 12 02:44:47 PM PDT 24
Finished Mar 12 02:44:48 PM PDT 24
Peak memory 217240 kb
Host smart-5a4ef64b-2bfd-42ef-870f-0d3371d74bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593279499 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_genbits.1593279499
Directory /workspace/31.edn_genbits/latest

Test location /workspace/coverage/default/31.edn_intr.3165349422
Short name T390
Test name
Test status
Simulation time 22557331 ps
CPU time 1.19 seconds
Started Mar 12 02:44:50 PM PDT 24
Finished Mar 12 02:44:52 PM PDT 24
Peak memory 222412 kb
Host smart-24ba696d-1d94-4073-9fc6-670bdfc7035c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165349422 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_intr.3165349422
Directory /workspace/31.edn_intr/latest

Test location /workspace/coverage/default/31.edn_smoke.1336300399
Short name T299
Test name
Test status
Simulation time 23076327 ps
CPU time 0.9 seconds
Started Mar 12 02:44:53 PM PDT 24
Finished Mar 12 02:44:54 PM PDT 24
Peak memory 214460 kb
Host smart-ec0356ee-aa77-48be-9505-894d24cb43b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336300399 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_smoke.1336300399
Directory /workspace/31.edn_smoke/latest

Test location /workspace/coverage/default/31.edn_stress_all.1185716977
Short name T790
Test name
Test status
Simulation time 286528698 ps
CPU time 5.93 seconds
Started Mar 12 02:44:46 PM PDT 24
Finished Mar 12 02:44:52 PM PDT 24
Peak memory 214456 kb
Host smart-489b25c7-91bc-46f6-93e9-b71df9e79bb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185716977 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.edn_stress_all.1185716977
Directory /workspace/31.edn_stress_all/latest

Test location /workspace/coverage/default/31.edn_stress_all_with_rand_reset.1198912814
Short name T511
Test name
Test status
Simulation time 32191656168 ps
CPU time 677.13 seconds
Started Mar 12 02:44:47 PM PDT 24
Finished Mar 12 02:56:05 PM PDT 24
Peak memory 222792 kb
Host smart-891ca7c8-201d-4522-9ec2-a388734fdaa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198912814 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 31.edn_stress_all_with_rand_reset.1198912814
Directory /workspace/31.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.edn_alert_test.589596491
Short name T348
Test name
Test status
Simulation time 14387927 ps
CPU time 0.91 seconds
Started Mar 12 02:44:47 PM PDT 24
Finished Mar 12 02:44:49 PM PDT 24
Peak memory 204996 kb
Host smart-e49e1013-1a2e-4693-8a81-5322d405ce7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589596491 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_alert_test.589596491
Directory /workspace/32.edn_alert_test/latest

Test location /workspace/coverage/default/32.edn_disable.1163465385
Short name T167
Test name
Test status
Simulation time 16326534 ps
CPU time 0.86 seconds
Started Mar 12 02:44:50 PM PDT 24
Finished Mar 12 02:44:51 PM PDT 24
Peak memory 214908 kb
Host smart-33c4390b-4720-4b20-9ffc-a3ce1f79b29a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163465385 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_disable.1163465385
Directory /workspace/32.edn_disable/latest

Test location /workspace/coverage/default/32.edn_err.3127907410
Short name T762
Test name
Test status
Simulation time 48648018 ps
CPU time 0.92 seconds
Started Mar 12 02:44:46 PM PDT 24
Finished Mar 12 02:44:47 PM PDT 24
Peak memory 215772 kb
Host smart-18046288-3f04-40c8-a6d5-50c678d9d18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127907410 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_err.3127907410
Directory /workspace/32.edn_err/latest

Test location /workspace/coverage/default/32.edn_genbits.3189904264
Short name T340
Test name
Test status
Simulation time 59630408 ps
CPU time 1.57 seconds
Started Mar 12 02:44:47 PM PDT 24
Finished Mar 12 02:44:48 PM PDT 24
Peak memory 216708 kb
Host smart-f4409fb5-5a49-4885-9c1b-1502ffff5d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189904264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_genbits.3189904264
Directory /workspace/32.edn_genbits/latest

Test location /workspace/coverage/default/32.edn_intr.3609520410
Short name T484
Test name
Test status
Simulation time 21572085 ps
CPU time 1.04 seconds
Started Mar 12 02:44:48 PM PDT 24
Finished Mar 12 02:44:50 PM PDT 24
Peak memory 214608 kb
Host smart-125ca338-b6d7-4788-8878-589df95fa155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609520410 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_intr.3609520410
Directory /workspace/32.edn_intr/latest

Test location /workspace/coverage/default/32.edn_smoke.2397451741
Short name T552
Test name
Test status
Simulation time 39395993 ps
CPU time 0.89 seconds
Started Mar 12 02:44:46 PM PDT 24
Finished Mar 12 02:44:47 PM PDT 24
Peak memory 214428 kb
Host smart-2f77c3f0-95d2-45f9-ba28-34f923fc98a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397451741 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_smoke.2397451741
Directory /workspace/32.edn_smoke/latest

Test location /workspace/coverage/default/32.edn_stress_all.3847711020
Short name T4
Test name
Test status
Simulation time 301709918 ps
CPU time 6.08 seconds
Started Mar 12 02:44:47 PM PDT 24
Finished Mar 12 02:44:53 PM PDT 24
Peak memory 218332 kb
Host smart-db19cd1f-74f0-41ff-964c-fd3fdc50b8c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847711020 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.edn_stress_all.3847711020
Directory /workspace/32.edn_stress_all/latest

Test location /workspace/coverage/default/32.edn_stress_all_with_rand_reset.3589802927
Short name T258
Test name
Test status
Simulation time 97291199461 ps
CPU time 337.14 seconds
Started Mar 12 02:44:51 PM PDT 24
Finished Mar 12 02:50:28 PM PDT 24
Peak memory 217280 kb
Host smart-970b441a-841e-46b3-853e-a64af9a9699a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589802927 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 32.edn_stress_all_with_rand_reset.3589802927
Directory /workspace/32.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.edn_alert_test.3192032337
Short name T445
Test name
Test status
Simulation time 25628969 ps
CPU time 0.86 seconds
Started Mar 12 02:44:51 PM PDT 24
Finished Mar 12 02:44:52 PM PDT 24
Peak memory 206112 kb
Host smart-879816d6-d68b-4421-9aea-81ae4a1d12ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192032337 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_alert_test.3192032337
Directory /workspace/33.edn_alert_test/latest

Test location /workspace/coverage/default/33.edn_disable.2246369973
Short name T111
Test name
Test status
Simulation time 21652105 ps
CPU time 0.87 seconds
Started Mar 12 02:44:54 PM PDT 24
Finished Mar 12 02:44:55 PM PDT 24
Peak memory 214912 kb
Host smart-b26a468c-2011-4f42-9657-86f3e186ed20
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246369973 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_disable.2246369973
Directory /workspace/33.edn_disable/latest

Test location /workspace/coverage/default/33.edn_disable_auto_req_mode.461247225
Short name T665
Test name
Test status
Simulation time 65298366 ps
CPU time 1.12 seconds
Started Mar 12 02:44:54 PM PDT 24
Finished Mar 12 02:44:56 PM PDT 24
Peak memory 215660 kb
Host smart-49626b5c-efb7-403b-a42f-2d98542d63d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461247225 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_di
sable_auto_req_mode.461247225
Directory /workspace/33.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/33.edn_err.1808328219
Short name T686
Test name
Test status
Simulation time 21142126 ps
CPU time 1.14 seconds
Started Mar 12 02:44:54 PM PDT 24
Finished Mar 12 02:44:56 PM PDT 24
Peak memory 215872 kb
Host smart-5af3284b-4ccf-4acd-952d-29916026b1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808328219 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_err.1808328219
Directory /workspace/33.edn_err/latest

Test location /workspace/coverage/default/33.edn_genbits.2643196243
Short name T733
Test name
Test status
Simulation time 33129259 ps
CPU time 1.44 seconds
Started Mar 12 02:44:47 PM PDT 24
Finished Mar 12 02:44:49 PM PDT 24
Peak memory 217028 kb
Host smart-4521b98f-6142-4382-bcdf-70627d844afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643196243 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_genbits.2643196243
Directory /workspace/33.edn_genbits/latest

Test location /workspace/coverage/default/33.edn_intr.4041256706
Short name T139
Test name
Test status
Simulation time 22081203 ps
CPU time 1.14 seconds
Started Mar 12 02:44:55 PM PDT 24
Finished Mar 12 02:44:56 PM PDT 24
Peak memory 214828 kb
Host smart-f870ec06-f153-43a6-bf87-58b285e722a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041256706 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_intr.4041256706
Directory /workspace/33.edn_intr/latest

Test location /workspace/coverage/default/33.edn_smoke.2109507665
Short name T407
Test name
Test status
Simulation time 16402739 ps
CPU time 0.92 seconds
Started Mar 12 02:44:48 PM PDT 24
Finished Mar 12 02:44:49 PM PDT 24
Peak memory 214400 kb
Host smart-529fe9e3-1a15-424f-9003-0ec06c3b4bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109507665 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_smoke.2109507665
Directory /workspace/33.edn_smoke/latest

Test location /workspace/coverage/default/33.edn_stress_all.1721778932
Short name T431
Test name
Test status
Simulation time 615082596 ps
CPU time 3.52 seconds
Started Mar 12 02:44:48 PM PDT 24
Finished Mar 12 02:44:51 PM PDT 24
Peak memory 215728 kb
Host smart-9c801e0e-9e8f-4b90-bc07-3120179c6c1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721778932 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.edn_stress_all.1721778932
Directory /workspace/33.edn_stress_all/latest

Test location /workspace/coverage/default/33.edn_stress_all_with_rand_reset.3645187021
Short name T195
Test name
Test status
Simulation time 38532923109 ps
CPU time 835.59 seconds
Started Mar 12 02:44:48 PM PDT 24
Finished Mar 12 02:58:44 PM PDT 24
Peak memory 222748 kb
Host smart-ed7cc4f5-a106-48b4-ab0a-ced71cfbb592
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645187021 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.edn_stress_all_with_rand_reset.3645187021
Directory /workspace/33.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.edn_alert_test.2945540788
Short name T469
Test name
Test status
Simulation time 23041452 ps
CPU time 0.83 seconds
Started Mar 12 02:44:54 PM PDT 24
Finished Mar 12 02:44:56 PM PDT 24
Peak memory 204976 kb
Host smart-0071dea7-8c12-46e3-8f6b-a4e26e0030c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945540788 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_alert_test.2945540788
Directory /workspace/34.edn_alert_test/latest

Test location /workspace/coverage/default/34.edn_disable.1610090772
Short name T55
Test name
Test status
Simulation time 25504295 ps
CPU time 0.81 seconds
Started Mar 12 02:44:54 PM PDT 24
Finished Mar 12 02:44:56 PM PDT 24
Peak memory 214972 kb
Host smart-dc5313f6-8c23-40d2-9a0f-b16fd8c678a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610090772 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_disable.1610090772
Directory /workspace/34.edn_disable/latest

Test location /workspace/coverage/default/34.edn_disable_auto_req_mode.2139126376
Short name T187
Test name
Test status
Simulation time 254919161 ps
CPU time 1.13 seconds
Started Mar 12 02:44:53 PM PDT 24
Finished Mar 12 02:44:54 PM PDT 24
Peak memory 215684 kb
Host smart-0715c1c2-45d2-4746-b587-9447c7b476f0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139126376 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_d
isable_auto_req_mode.2139126376
Directory /workspace/34.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/34.edn_err.572793180
Short name T82
Test name
Test status
Simulation time 26669423 ps
CPU time 1.13 seconds
Started Mar 12 02:44:57 PM PDT 24
Finished Mar 12 02:44:59 PM PDT 24
Peak memory 215916 kb
Host smart-67b88e4f-3a6c-4e0c-9944-63988d0b07ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572793180 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_err.572793180
Directory /workspace/34.edn_err/latest

Test location /workspace/coverage/default/34.edn_genbits.13676403
Short name T721
Test name
Test status
Simulation time 101566562 ps
CPU time 1.01 seconds
Started Mar 12 02:44:57 PM PDT 24
Finished Mar 12 02:44:59 PM PDT 24
Peak memory 215772 kb
Host smart-857e1d40-5a2a-4d04-a634-d9439e5631ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13676403 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_genbits.13676403
Directory /workspace/34.edn_genbits/latest

Test location /workspace/coverage/default/34.edn_intr.3951934716
Short name T138
Test name
Test status
Simulation time 24628056 ps
CPU time 0.93 seconds
Started Mar 12 02:44:52 PM PDT 24
Finished Mar 12 02:44:54 PM PDT 24
Peak memory 214804 kb
Host smart-9e5a1e48-a867-4421-9d4c-5b634f1c1277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951934716 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_intr.3951934716
Directory /workspace/34.edn_intr/latest

Test location /workspace/coverage/default/34.edn_smoke.431272727
Short name T714
Test name
Test status
Simulation time 19639395 ps
CPU time 0.98 seconds
Started Mar 12 02:44:54 PM PDT 24
Finished Mar 12 02:44:55 PM PDT 24
Peak memory 214496 kb
Host smart-d2fbe571-9dec-4ce4-aa5c-4bd143eab840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431272727 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_smoke.431272727
Directory /workspace/34.edn_smoke/latest

Test location /workspace/coverage/default/34.edn_stress_all.526290509
Short name T205
Test name
Test status
Simulation time 40386658 ps
CPU time 1.23 seconds
Started Mar 12 02:44:58 PM PDT 24
Finished Mar 12 02:44:59 PM PDT 24
Peak memory 206272 kb
Host smart-dfcd0125-9d23-460a-b88a-d51c8510ab9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526290509 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.edn_stress_all.526290509
Directory /workspace/34.edn_stress_all/latest

Test location /workspace/coverage/default/34.edn_stress_all_with_rand_reset.980968568
Short name T717
Test name
Test status
Simulation time 150084499642 ps
CPU time 1729.71 seconds
Started Mar 12 02:44:53 PM PDT 24
Finished Mar 12 03:13:44 PM PDT 24
Peak memory 223516 kb
Host smart-a6807ec1-e53b-4c5c-8d07-82e9d5925f83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980968568 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.edn_stress_all_with_rand_reset.980968568
Directory /workspace/34.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.edn_alert.3794675646
Short name T702
Test name
Test status
Simulation time 74832102 ps
CPU time 1.18 seconds
Started Mar 12 02:44:55 PM PDT 24
Finished Mar 12 02:44:56 PM PDT 24
Peak memory 214712 kb
Host smart-099f53fb-f64e-4f6d-a307-b0c384283ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794675646 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert.3794675646
Directory /workspace/35.edn_alert/latest

Test location /workspace/coverage/default/35.edn_alert_test.3291804626
Short name T502
Test name
Test status
Simulation time 25193186 ps
CPU time 1.01 seconds
Started Mar 12 02:44:57 PM PDT 24
Finished Mar 12 02:44:59 PM PDT 24
Peak memory 205636 kb
Host smart-c61701e0-ac85-460d-81d6-40455264a01e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291804626 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_alert_test.3291804626
Directory /workspace/35.edn_alert_test/latest

Test location /workspace/coverage/default/35.edn_disable.1636732421
Short name T121
Test name
Test status
Simulation time 39100419 ps
CPU time 0.84 seconds
Started Mar 12 02:44:53 PM PDT 24
Finished Mar 12 02:44:55 PM PDT 24
Peak memory 214956 kb
Host smart-0748097f-a394-420c-bddc-c871d05d4d49
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636732421 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_disable.1636732421
Directory /workspace/35.edn_disable/latest

Test location /workspace/coverage/default/35.edn_err.1593531883
Short name T74
Test name
Test status
Simulation time 28389322 ps
CPU time 1.33 seconds
Started Mar 12 02:44:56 PM PDT 24
Finished Mar 12 02:44:57 PM PDT 24
Peak memory 229092 kb
Host smart-21b0a15f-8c4f-4d4c-acb7-65c13a38b8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593531883 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_err.1593531883
Directory /workspace/35.edn_err/latest

Test location /workspace/coverage/default/35.edn_genbits.296458539
Short name T586
Test name
Test status
Simulation time 81094787 ps
CPU time 2.85 seconds
Started Mar 12 02:44:54 PM PDT 24
Finished Mar 12 02:44:57 PM PDT 24
Peak memory 217112 kb
Host smart-2b7bb4bd-0a09-4f7e-99fb-f2ee658e8c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296458539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_genbits.296458539
Directory /workspace/35.edn_genbits/latest

Test location /workspace/coverage/default/35.edn_intr.4136154813
Short name T610
Test name
Test status
Simulation time 22642457 ps
CPU time 1.03 seconds
Started Mar 12 02:44:55 PM PDT 24
Finished Mar 12 02:44:56 PM PDT 24
Peak memory 214780 kb
Host smart-953ddfbd-736c-48ec-b675-6c90d897b6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136154813 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_intr.4136154813
Directory /workspace/35.edn_intr/latest

Test location /workspace/coverage/default/35.edn_smoke.1695684604
Short name T791
Test name
Test status
Simulation time 72396537 ps
CPU time 0.87 seconds
Started Mar 12 02:44:57 PM PDT 24
Finished Mar 12 02:44:58 PM PDT 24
Peak memory 214460 kb
Host smart-d6805cce-5d23-4b54-8fe5-eb6d788f47a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695684604 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_smoke.1695684604
Directory /workspace/35.edn_smoke/latest

Test location /workspace/coverage/default/35.edn_stress_all.505868425
Short name T706
Test name
Test status
Simulation time 369115848 ps
CPU time 7.09 seconds
Started Mar 12 02:44:54 PM PDT 24
Finished Mar 12 02:45:01 PM PDT 24
Peak memory 214492 kb
Host smart-1731f2a5-fc8c-4ccb-970a-b0bf95ece70d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505868425 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.edn_stress_all.505868425
Directory /workspace/35.edn_stress_all/latest

Test location /workspace/coverage/default/35.edn_stress_all_with_rand_reset.2099976741
Short name T785
Test name
Test status
Simulation time 61026920127 ps
CPU time 1473.9 seconds
Started Mar 12 02:44:54 PM PDT 24
Finished Mar 12 03:09:29 PM PDT 24
Peak memory 223488 kb
Host smart-a40438a3-2164-4c2c-b8b2-e50c500849d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099976741 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 35.edn_stress_all_with_rand_reset.2099976741
Directory /workspace/35.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.edn_alert.988590536
Short name T254
Test name
Test status
Simulation time 45185966 ps
CPU time 1.15 seconds
Started Mar 12 02:44:53 PM PDT 24
Finished Mar 12 02:44:55 PM PDT 24
Peak memory 214804 kb
Host smart-4c812482-5519-4329-95d5-3e571a80dc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988590536 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert.988590536
Directory /workspace/36.edn_alert/latest

Test location /workspace/coverage/default/36.edn_alert_test.2605214704
Short name T557
Test name
Test status
Simulation time 104879526 ps
CPU time 1.1 seconds
Started Mar 12 02:45:02 PM PDT 24
Finished Mar 12 02:45:04 PM PDT 24
Peak memory 206040 kb
Host smart-3f02284c-82e8-4488-9f9c-da4481f81809
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605214704 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_alert_test.2605214704
Directory /workspace/36.edn_alert_test/latest

Test location /workspace/coverage/default/36.edn_disable.3886481297
Short name T480
Test name
Test status
Simulation time 29387102 ps
CPU time 0.89 seconds
Started Mar 12 02:45:04 PM PDT 24
Finished Mar 12 02:45:05 PM PDT 24
Peak memory 214964 kb
Host smart-372717ca-c1c2-4200-ad9a-b023eb18e130
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886481297 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_disable.3886481297
Directory /workspace/36.edn_disable/latest

Test location /workspace/coverage/default/36.edn_disable_auto_req_mode.3686529190
Short name T90
Test name
Test status
Simulation time 42188523 ps
CPU time 1.19 seconds
Started Mar 12 02:45:01 PM PDT 24
Finished Mar 12 02:45:03 PM PDT 24
Peak memory 215408 kb
Host smart-2b89e67e-f419-4d62-92f9-34a516a55481
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686529190 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_d
isable_auto_req_mode.3686529190
Directory /workspace/36.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/36.edn_err.1031831127
Short name T750
Test name
Test status
Simulation time 23202758 ps
CPU time 1.14 seconds
Started Mar 12 02:45:04 PM PDT 24
Finished Mar 12 02:45:06 PM PDT 24
Peak memory 215860 kb
Host smart-c2b56bb5-8fe2-4dab-bac8-157a48896b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031831127 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_err.1031831127
Directory /workspace/36.edn_err/latest

Test location /workspace/coverage/default/36.edn_genbits.641497433
Short name T30
Test name
Test status
Simulation time 42810314 ps
CPU time 1.08 seconds
Started Mar 12 02:44:57 PM PDT 24
Finished Mar 12 02:44:59 PM PDT 24
Peak memory 215696 kb
Host smart-4562f968-4f73-4dd2-b44d-bb76ff9c0c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641497433 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_genbits.641497433
Directory /workspace/36.edn_genbits/latest

Test location /workspace/coverage/default/36.edn_smoke.523665269
Short name T296
Test name
Test status
Simulation time 54310810 ps
CPU time 0.9 seconds
Started Mar 12 02:44:53 PM PDT 24
Finished Mar 12 02:44:54 PM PDT 24
Peak memory 214476 kb
Host smart-768fb93c-bd0b-4e25-bac2-0120903711fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523665269 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_smoke.523665269
Directory /workspace/36.edn_smoke/latest

Test location /workspace/coverage/default/36.edn_stress_all.3717599037
Short name T461
Test name
Test status
Simulation time 930965738 ps
CPU time 4.95 seconds
Started Mar 12 02:44:55 PM PDT 24
Finished Mar 12 02:45:00 PM PDT 24
Peak memory 214340 kb
Host smart-2075e37f-4269-459b-a392-e20b739654e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717599037 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.edn_stress_all.3717599037
Directory /workspace/36.edn_stress_all/latest

Test location /workspace/coverage/default/36.edn_stress_all_with_rand_reset.3514106181
Short name T495
Test name
Test status
Simulation time 149854826473 ps
CPU time 1905.45 seconds
Started Mar 12 02:44:52 PM PDT 24
Finished Mar 12 03:16:38 PM PDT 24
Peak memory 227200 kb
Host smart-78d81dcf-61f2-4c51-a62e-4d959753fd7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514106181 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 36.edn_stress_all_with_rand_reset.3514106181
Directory /workspace/36.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.edn_alert.1098793819
Short name T152
Test name
Test status
Simulation time 23968602 ps
CPU time 1.22 seconds
Started Mar 12 02:45:09 PM PDT 24
Finished Mar 12 02:45:10 PM PDT 24
Peak memory 214864 kb
Host smart-9d009960-a78f-46c4-be13-880120905855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098793819 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert.1098793819
Directory /workspace/37.edn_alert/latest

Test location /workspace/coverage/default/37.edn_alert_test.1039055855
Short name T491
Test name
Test status
Simulation time 33612525 ps
CPU time 0.92 seconds
Started Mar 12 02:45:05 PM PDT 24
Finished Mar 12 02:45:06 PM PDT 24
Peak memory 206060 kb
Host smart-65061518-50bc-48f6-9d47-9464c691eb31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039055855 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_alert_test.1039055855
Directory /workspace/37.edn_alert_test/latest

Test location /workspace/coverage/default/37.edn_disable.2043466055
Short name T335
Test name
Test status
Simulation time 20583595 ps
CPU time 0.82 seconds
Started Mar 12 02:45:03 PM PDT 24
Finished Mar 12 02:45:05 PM PDT 24
Peak memory 214648 kb
Host smart-7e550c33-1980-4282-ba84-896b35a887c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043466055 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_disable.2043466055
Directory /workspace/37.edn_disable/latest

Test location /workspace/coverage/default/37.edn_err.19928364
Short name T652
Test name
Test status
Simulation time 26532923 ps
CPU time 0.89 seconds
Started Mar 12 02:45:09 PM PDT 24
Finished Mar 12 02:45:10 PM PDT 24
Peak memory 222248 kb
Host smart-d66bc09d-36e4-418d-a351-f39ff7ab4957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19928364 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_err.19928364
Directory /workspace/37.edn_err/latest

Test location /workspace/coverage/default/37.edn_genbits.2503428892
Short name T708
Test name
Test status
Simulation time 100617881 ps
CPU time 1.48 seconds
Started Mar 12 02:45:00 PM PDT 24
Finished Mar 12 02:45:02 PM PDT 24
Peak memory 216968 kb
Host smart-501e27a6-cfb9-4a7a-9542-68bec0b92e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503428892 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_genbits.2503428892
Directory /workspace/37.edn_genbits/latest

Test location /workspace/coverage/default/37.edn_intr.3778387634
Short name T784
Test name
Test status
Simulation time 37424572 ps
CPU time 0.91 seconds
Started Mar 12 02:45:07 PM PDT 24
Finished Mar 12 02:45:08 PM PDT 24
Peak memory 214616 kb
Host smart-960d38b8-dc5e-4693-9b51-a687df6d3909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778387634 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_intr.3778387634
Directory /workspace/37.edn_intr/latest

Test location /workspace/coverage/default/37.edn_smoke.647022780
Short name T550
Test name
Test status
Simulation time 25438477 ps
CPU time 0.94 seconds
Started Mar 12 02:45:02 PM PDT 24
Finished Mar 12 02:45:04 PM PDT 24
Peak memory 214492 kb
Host smart-ab7efade-a406-4cb1-9953-7df908ca23fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647022780 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_smoke.647022780
Directory /workspace/37.edn_smoke/latest

Test location /workspace/coverage/default/37.edn_stress_all.268135706
Short name T233
Test name
Test status
Simulation time 563347149 ps
CPU time 3.43 seconds
Started Mar 12 02:45:02 PM PDT 24
Finished Mar 12 02:45:06 PM PDT 24
Peak memory 214436 kb
Host smart-c359cb07-b2a9-49e2-9195-dd6b5ec1a689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268135706 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.edn_stress_all.268135706
Directory /workspace/37.edn_stress_all/latest

Test location /workspace/coverage/default/37.edn_stress_all_with_rand_reset.489337968
Short name T587
Test name
Test status
Simulation time 96012730866 ps
CPU time 582.89 seconds
Started Mar 12 02:45:06 PM PDT 24
Finished Mar 12 02:54:49 PM PDT 24
Peak memory 218864 kb
Host smart-ef8f7c36-1b87-471d-8222-6b12ee921b3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489337968 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.edn_stress_all_with_rand_reset.489337968
Directory /workspace/37.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.edn_alert.108783780
Short name T109
Test name
Test status
Simulation time 67701789 ps
CPU time 1.07 seconds
Started Mar 12 02:45:09 PM PDT 24
Finished Mar 12 02:45:11 PM PDT 24
Peak memory 214860 kb
Host smart-47e0c8f0-647e-4235-8573-13ee883f4a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108783780 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert.108783780
Directory /workspace/38.edn_alert/latest

Test location /workspace/coverage/default/38.edn_alert_test.729385273
Short name T512
Test name
Test status
Simulation time 21826495 ps
CPU time 1.04 seconds
Started Mar 12 02:45:10 PM PDT 24
Finished Mar 12 02:45:11 PM PDT 24
Peak memory 205748 kb
Host smart-37cb5952-aca6-4614-8b14-3dd52a9516c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729385273 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_alert_test.729385273
Directory /workspace/38.edn_alert_test/latest

Test location /workspace/coverage/default/38.edn_disable.2822375637
Short name T104
Test name
Test status
Simulation time 13706337 ps
CPU time 0.92 seconds
Started Mar 12 02:45:10 PM PDT 24
Finished Mar 12 02:45:11 PM PDT 24
Peak memory 215008 kb
Host smart-02731786-48cd-4059-8d25-6f790c643f86
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822375637 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_disable.2822375637
Directory /workspace/38.edn_disable/latest

Test location /workspace/coverage/default/38.edn_disable_auto_req_mode.3268403398
Short name T155
Test name
Test status
Simulation time 102100185 ps
CPU time 1.14 seconds
Started Mar 12 02:45:10 PM PDT 24
Finished Mar 12 02:45:12 PM PDT 24
Peak memory 215480 kb
Host smart-d68d0cf6-2a39-4058-976a-60d5ea3dab88
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268403398 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_d
isable_auto_req_mode.3268403398
Directory /workspace/38.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/38.edn_err.1941401887
Short name T556
Test name
Test status
Simulation time 20999395 ps
CPU time 1.02 seconds
Started Mar 12 02:45:09 PM PDT 24
Finished Mar 12 02:45:10 PM PDT 24
Peak memory 222480 kb
Host smart-14ba6bdf-d3da-474c-8683-469cbbe862f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941401887 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_err.1941401887
Directory /workspace/38.edn_err/latest

Test location /workspace/coverage/default/38.edn_genbits.1498700525
Short name T424
Test name
Test status
Simulation time 30304295 ps
CPU time 1.31 seconds
Started Mar 12 02:45:03 PM PDT 24
Finished Mar 12 02:45:04 PM PDT 24
Peak memory 216972 kb
Host smart-0baec7a6-57ef-4890-aadf-e54d7fc7574a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498700525 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_genbits.1498700525
Directory /workspace/38.edn_genbits/latest

Test location /workspace/coverage/default/38.edn_intr.8332046
Short name T645
Test name
Test status
Simulation time 47459484 ps
CPU time 0.87 seconds
Started Mar 12 02:45:11 PM PDT 24
Finished Mar 12 02:45:13 PM PDT 24
Peak memory 214484 kb
Host smart-4bb165eb-fed5-49ab-b270-529448c16809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8332046 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_intr.8332046
Directory /workspace/38.edn_intr/latest

Test location /workspace/coverage/default/38.edn_smoke.2857496724
Short name T405
Test name
Test status
Simulation time 26437294 ps
CPU time 0.97 seconds
Started Mar 12 02:45:02 PM PDT 24
Finished Mar 12 02:45:03 PM PDT 24
Peak memory 214456 kb
Host smart-8840d3d8-56fb-4c88-bbc3-971c808cf058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857496724 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_smoke.2857496724
Directory /workspace/38.edn_smoke/latest

Test location /workspace/coverage/default/38.edn_stress_all.3932897690
Short name T520
Test name
Test status
Simulation time 688048395 ps
CPU time 3.74 seconds
Started Mar 12 02:45:08 PM PDT 24
Finished Mar 12 02:45:13 PM PDT 24
Peak memory 217028 kb
Host smart-cca69459-d067-44d5-8c0a-665b770572d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932897690 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.edn_stress_all.3932897690
Directory /workspace/38.edn_stress_all/latest

Test location /workspace/coverage/default/38.edn_stress_all_with_rand_reset.2483644918
Short name T523
Test name
Test status
Simulation time 10401283581 ps
CPU time 276.12 seconds
Started Mar 12 02:45:01 PM PDT 24
Finished Mar 12 02:49:38 PM PDT 24
Peak memory 215900 kb
Host smart-23048d74-a41a-4c93-9cec-7a2eb1f985ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483644918 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 38.edn_stress_all_with_rand_reset.2483644918
Directory /workspace/38.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.edn_alert.908795673
Short name T478
Test name
Test status
Simulation time 70869260 ps
CPU time 1.21 seconds
Started Mar 12 02:45:08 PM PDT 24
Finished Mar 12 02:45:10 PM PDT 24
Peak memory 214852 kb
Host smart-cf2034d1-bbbb-45f4-9833-89e97692f5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908795673 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert.908795673
Directory /workspace/39.edn_alert/latest

Test location /workspace/coverage/default/39.edn_alert_test.3561622800
Short name T660
Test name
Test status
Simulation time 30258725 ps
CPU time 1 seconds
Started Mar 12 02:45:10 PM PDT 24
Finished Mar 12 02:45:12 PM PDT 24
Peak memory 206104 kb
Host smart-0192a351-a4f8-47bf-8851-4a7b69b2c9ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561622800 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_alert_test.3561622800
Directory /workspace/39.edn_alert_test/latest

Test location /workspace/coverage/default/39.edn_disable_auto_req_mode.4006757456
Short name T384
Test name
Test status
Simulation time 32319690 ps
CPU time 1.18 seconds
Started Mar 12 02:45:14 PM PDT 24
Finished Mar 12 02:45:16 PM PDT 24
Peak memory 216696 kb
Host smart-f6a024bc-e2fd-4cac-a827-f78e386d6088
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006757456 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_d
isable_auto_req_mode.4006757456
Directory /workspace/39.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/39.edn_err.1648005616
Short name T426
Test name
Test status
Simulation time 27931463 ps
CPU time 0.93 seconds
Started Mar 12 02:45:08 PM PDT 24
Finished Mar 12 02:45:09 PM PDT 24
Peak memory 222384 kb
Host smart-0d986561-b6ae-4445-b00d-75c8f4ad22b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648005616 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_err.1648005616
Directory /workspace/39.edn_err/latest

Test location /workspace/coverage/default/39.edn_genbits.1848789035
Short name T568
Test name
Test status
Simulation time 136564462 ps
CPU time 1.39 seconds
Started Mar 12 02:45:11 PM PDT 24
Finished Mar 12 02:45:13 PM PDT 24
Peak memory 217252 kb
Host smart-97e91b92-7b0d-4e5c-84c9-4c144016584f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848789035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_genbits.1848789035
Directory /workspace/39.edn_genbits/latest

Test location /workspace/coverage/default/39.edn_smoke.1900869736
Short name T399
Test name
Test status
Simulation time 46846049 ps
CPU time 0.89 seconds
Started Mar 12 02:45:10 PM PDT 24
Finished Mar 12 02:45:11 PM PDT 24
Peak memory 214412 kb
Host smart-6da8aeeb-5f1b-40aa-83b1-6481bcd03b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900869736 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_smoke.1900869736
Directory /workspace/39.edn_smoke/latest

Test location /workspace/coverage/default/39.edn_stress_all.3246126177
Short name T362
Test name
Test status
Simulation time 344991575 ps
CPU time 6.6 seconds
Started Mar 12 02:45:11 PM PDT 24
Finished Mar 12 02:45:18 PM PDT 24
Peak memory 214520 kb
Host smart-b932551d-f771-4582-90df-07aa3e405dfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246126177 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.edn_stress_all.3246126177
Directory /workspace/39.edn_stress_all/latest

Test location /workspace/coverage/default/39.edn_stress_all_with_rand_reset.76241204
Short name T747
Test name
Test status
Simulation time 73656566876 ps
CPU time 1907.81 seconds
Started Mar 12 02:45:11 PM PDT 24
Finished Mar 12 03:17:00 PM PDT 24
Peak memory 225680 kb
Host smart-11f9b831-87f3-4a6c-abbc-2ed98777055d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76241204 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 39.edn_stress_all_with_rand_reset.76241204
Directory /workspace/39.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.edn_alert.3267084131
Short name T251
Test name
Test status
Simulation time 79736808 ps
CPU time 1.18 seconds
Started Mar 12 02:43:26 PM PDT 24
Finished Mar 12 02:43:27 PM PDT 24
Peak memory 214868 kb
Host smart-2441ab51-a37a-4824-b2bd-17b1fba3e271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267084131 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert.3267084131
Directory /workspace/4.edn_alert/latest

Test location /workspace/coverage/default/4.edn_alert_test.1448790049
Short name T680
Test name
Test status
Simulation time 32168640 ps
CPU time 0.8 seconds
Started Mar 12 02:43:18 PM PDT 24
Finished Mar 12 02:43:19 PM PDT 24
Peak memory 204952 kb
Host smart-5b8f1308-c5b4-40f5-b73b-2d8356688607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448790049 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_alert_test.1448790049
Directory /workspace/4.edn_alert_test/latest

Test location /workspace/coverage/default/4.edn_disable.1313114674
Short name T98
Test name
Test status
Simulation time 79035378 ps
CPU time 0.79 seconds
Started Mar 12 02:43:22 PM PDT 24
Finished Mar 12 02:43:24 PM PDT 24
Peak memory 214668 kb
Host smart-fdbccdbf-56a7-4a00-b254-6279e598039b
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313114674 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_disable.1313114674
Directory /workspace/4.edn_disable/latest

Test location /workspace/coverage/default/4.edn_err.4219072484
Short name T820
Test name
Test status
Simulation time 23019956 ps
CPU time 0.93 seconds
Started Mar 12 02:43:25 PM PDT 24
Finished Mar 12 02:43:26 PM PDT 24
Peak memory 217412 kb
Host smart-a8dc1882-c978-4b58-919b-0b7622d1ac91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219072484 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_err.4219072484
Directory /workspace/4.edn_err/latest

Test location /workspace/coverage/default/4.edn_genbits.4124483436
Short name T11
Test name
Test status
Simulation time 53677743 ps
CPU time 1.2 seconds
Started Mar 12 02:43:11 PM PDT 24
Finished Mar 12 02:43:12 PM PDT 24
Peak memory 218556 kb
Host smart-3104fe3c-a725-478e-a709-b3a549c734d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124483436 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_genbits.4124483436
Directory /workspace/4.edn_genbits/latest

Test location /workspace/coverage/default/4.edn_intr.4163889401
Short name T68
Test name
Test status
Simulation time 30634918 ps
CPU time 0.78 seconds
Started Mar 12 02:43:19 PM PDT 24
Finished Mar 12 02:43:20 PM PDT 24
Peak memory 214580 kb
Host smart-9102c4e1-13c3-4c0c-ac4d-bc1c2be3531f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163889401 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_intr.4163889401
Directory /workspace/4.edn_intr/latest

Test location /workspace/coverage/default/4.edn_regwen.4118456919
Short name T250
Test name
Test status
Simulation time 35583923 ps
CPU time 0.89 seconds
Started Mar 12 02:43:11 PM PDT 24
Finished Mar 12 02:43:13 PM PDT 24
Peak memory 206248 kb
Host smart-145f8fe4-6668-47a7-9599-2e8fe159db0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118456919 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_regwen.4118456919
Directory /workspace/4.edn_regwen/latest

Test location /workspace/coverage/default/4.edn_smoke.1584254855
Short name T358
Test name
Test status
Simulation time 47286317 ps
CPU time 0.86 seconds
Started Mar 12 02:43:10 PM PDT 24
Finished Mar 12 02:43:10 PM PDT 24
Peak memory 214388 kb
Host smart-44207630-62ff-4fb9-a405-33382a565cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584254855 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_smoke.1584254855
Directory /workspace/4.edn_smoke/latest

Test location /workspace/coverage/default/4.edn_stress_all.2016867173
Short name T555
Test name
Test status
Simulation time 96130950 ps
CPU time 1.49 seconds
Started Mar 12 02:43:10 PM PDT 24
Finished Mar 12 02:43:12 PM PDT 24
Peak memory 215528 kb
Host smart-8f63a075-3ec7-4d9f-a007-c26039f46334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016867173 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.edn_stress_all.2016867173
Directory /workspace/4.edn_stress_all/latest

Test location /workspace/coverage/default/4.edn_stress_all_with_rand_reset.529966006
Short name T685
Test name
Test status
Simulation time 143438944049 ps
CPU time 1933.17 seconds
Started Mar 12 02:43:20 PM PDT 24
Finished Mar 12 03:15:34 PM PDT 24
Peak memory 227212 kb
Host smart-74ff801d-31c1-4bf5-9184-d06b02ba0a40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529966006 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.edn_stress_all_with_rand_reset.529966006
Directory /workspace/4.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.edn_alert.1910101768
Short name T821
Test name
Test status
Simulation time 46293285 ps
CPU time 1.15 seconds
Started Mar 12 02:45:11 PM PDT 24
Finished Mar 12 02:45:13 PM PDT 24
Peak memory 214904 kb
Host smart-be95370c-b814-4c10-8bf0-459d7ef89fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910101768 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert.1910101768
Directory /workspace/40.edn_alert/latest

Test location /workspace/coverage/default/40.edn_alert_test.1412513644
Short name T802
Test name
Test status
Simulation time 15110789 ps
CPU time 0.92 seconds
Started Mar 12 02:45:10 PM PDT 24
Finished Mar 12 02:45:12 PM PDT 24
Peak memory 206088 kb
Host smart-1561ca4f-155d-435f-8073-e1946f38212a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412513644 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_alert_test.1412513644
Directory /workspace/40.edn_alert_test/latest

Test location /workspace/coverage/default/40.edn_disable.2974929115
Short name T107
Test name
Test status
Simulation time 11049266 ps
CPU time 0.88 seconds
Started Mar 12 02:45:11 PM PDT 24
Finished Mar 12 02:45:13 PM PDT 24
Peak memory 214944 kb
Host smart-80be4fdf-a396-46b5-94e2-1a0bc58bccbc
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974929115 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_disable.2974929115
Directory /workspace/40.edn_disable/latest

Test location /workspace/coverage/default/40.edn_err.2249134973
Short name T175
Test name
Test status
Simulation time 19209748 ps
CPU time 1.17 seconds
Started Mar 12 02:45:13 PM PDT 24
Finished Mar 12 02:45:14 PM PDT 24
Peak memory 230604 kb
Host smart-2549ccdd-d0a9-4d4c-b768-d737b25ce894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249134973 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_err.2249134973
Directory /workspace/40.edn_err/latest

Test location /workspace/coverage/default/40.edn_genbits.2307105293
Short name T559
Test name
Test status
Simulation time 95368539 ps
CPU time 1.19 seconds
Started Mar 12 02:45:14 PM PDT 24
Finished Mar 12 02:45:15 PM PDT 24
Peak memory 216892 kb
Host smart-3056a342-d358-46d0-9af8-7d2448702c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307105293 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_genbits.2307105293
Directory /workspace/40.edn_genbits/latest

Test location /workspace/coverage/default/40.edn_intr.88776413
Short name T546
Test name
Test status
Simulation time 65972081 ps
CPU time 0.85 seconds
Started Mar 12 02:45:21 PM PDT 24
Finished Mar 12 02:45:22 PM PDT 24
Peak memory 214404 kb
Host smart-823d4e92-1a48-4bc9-a0b6-ccafb69e67c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88776413 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_intr.88776413
Directory /workspace/40.edn_intr/latest

Test location /workspace/coverage/default/40.edn_smoke.1972943419
Short name T360
Test name
Test status
Simulation time 51058102 ps
CPU time 0.86 seconds
Started Mar 12 02:45:09 PM PDT 24
Finished Mar 12 02:45:10 PM PDT 24
Peak memory 214480 kb
Host smart-20c99b8e-18c4-4ccb-84a0-4e19f30d854e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972943419 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_smoke.1972943419
Directory /workspace/40.edn_smoke/latest

Test location /workspace/coverage/default/40.edn_stress_all.1261011124
Short name T591
Test name
Test status
Simulation time 288015680 ps
CPU time 2.02 seconds
Started Mar 12 02:45:11 PM PDT 24
Finished Mar 12 02:45:14 PM PDT 24
Peak memory 215668 kb
Host smart-b5af3592-bb52-427d-952b-0314b061062d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261011124 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.edn_stress_all.1261011124
Directory /workspace/40.edn_stress_all/latest

Test location /workspace/coverage/default/40.edn_stress_all_with_rand_reset.978872973
Short name T809
Test name
Test status
Simulation time 216386841154 ps
CPU time 1236.51 seconds
Started Mar 12 02:45:10 PM PDT 24
Finished Mar 12 03:05:47 PM PDT 24
Peak memory 220904 kb
Host smart-ffc30594-876f-4c65-9bbf-ff55a7b37e09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978872973 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.edn_stress_all_with_rand_reset.978872973
Directory /workspace/40.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.edn_alert.3679705044
Short name T236
Test name
Test status
Simulation time 71822063 ps
CPU time 1.1 seconds
Started Mar 12 02:45:08 PM PDT 24
Finished Mar 12 02:45:10 PM PDT 24
Peak memory 214808 kb
Host smart-0ff6730c-180f-46cd-b88e-f41f7ae06d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679705044 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert.3679705044
Directory /workspace/41.edn_alert/latest

Test location /workspace/coverage/default/41.edn_alert_test.662024893
Short name T400
Test name
Test status
Simulation time 32882861 ps
CPU time 1.02 seconds
Started Mar 12 02:45:18 PM PDT 24
Finished Mar 12 02:45:20 PM PDT 24
Peak memory 205760 kb
Host smart-54a0af79-bdcf-4907-b0a2-4c9d23869645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662024893 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_alert_test.662024893
Directory /workspace/41.edn_alert_test/latest

Test location /workspace/coverage/default/41.edn_disable.3275705552
Short name T670
Test name
Test status
Simulation time 39064705 ps
CPU time 0.81 seconds
Started Mar 12 02:45:13 PM PDT 24
Finished Mar 12 02:45:14 PM PDT 24
Peak memory 214960 kb
Host smart-68e9e142-ce39-4775-b3d7-06d0050cd893
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275705552 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_disable.3275705552
Directory /workspace/41.edn_disable/latest

Test location /workspace/coverage/default/41.edn_disable_auto_req_mode.371067596
Short name T75
Test name
Test status
Simulation time 85040203 ps
CPU time 1.09 seconds
Started Mar 12 02:45:09 PM PDT 24
Finished Mar 12 02:45:10 PM PDT 24
Peak memory 215508 kb
Host smart-a706af05-85a0-43cb-8ad7-d16952cf3f88
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371067596 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_di
sable_auto_req_mode.371067596
Directory /workspace/41.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/41.edn_err.4196685778
Short name T5
Test name
Test status
Simulation time 50515786 ps
CPU time 0.92 seconds
Started Mar 12 02:45:12 PM PDT 24
Finished Mar 12 02:45:13 PM PDT 24
Peak memory 217108 kb
Host smart-e75e0acc-0318-4362-9309-86df803c8e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196685778 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_err.4196685778
Directory /workspace/41.edn_err/latest

Test location /workspace/coverage/default/41.edn_genbits.276827615
Short name T32
Test name
Test status
Simulation time 33918075 ps
CPU time 1.31 seconds
Started Mar 12 02:45:09 PM PDT 24
Finished Mar 12 02:45:11 PM PDT 24
Peak memory 216840 kb
Host smart-1434d224-0f93-490d-a898-6a16dfc28bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276827615 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_genbits.276827615
Directory /workspace/41.edn_genbits/latest

Test location /workspace/coverage/default/41.edn_intr.3143658102
Short name T594
Test name
Test status
Simulation time 23707150 ps
CPU time 1.06 seconds
Started Mar 12 02:45:08 PM PDT 24
Finished Mar 12 02:45:10 PM PDT 24
Peak memory 223372 kb
Host smart-1f9c95ac-5ce2-4fdf-84db-7d5051120991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143658102 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_intr.3143658102
Directory /workspace/41.edn_intr/latest

Test location /workspace/coverage/default/41.edn_smoke.3459606225
Short name T553
Test name
Test status
Simulation time 17920961 ps
CPU time 1.01 seconds
Started Mar 12 02:45:11 PM PDT 24
Finished Mar 12 02:45:13 PM PDT 24
Peak memory 214444 kb
Host smart-0e16f2bd-fb10-4d40-bea1-2356e73345ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459606225 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_smoke.3459606225
Directory /workspace/41.edn_smoke/latest

Test location /workspace/coverage/default/41.edn_stress_all.2031016160
Short name T203
Test name
Test status
Simulation time 1128851439 ps
CPU time 6.81 seconds
Started Mar 12 02:45:11 PM PDT 24
Finished Mar 12 02:45:19 PM PDT 24
Peak memory 214428 kb
Host smart-7daa2393-a9bb-4171-b969-1dc1be432c38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031016160 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.edn_stress_all.2031016160
Directory /workspace/41.edn_stress_all/latest

Test location /workspace/coverage/default/41.edn_stress_all_with_rand_reset.4142354604
Short name T831
Test name
Test status
Simulation time 25318779118 ps
CPU time 559.58 seconds
Started Mar 12 02:45:09 PM PDT 24
Finished Mar 12 02:54:30 PM PDT 24
Peak memory 222856 kb
Host smart-0beb0442-d115-4ecb-846b-99cf027e2fc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142354604 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 41.edn_stress_all_with_rand_reset.4142354604
Directory /workspace/41.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.edn_alert.3856110432
Short name T637
Test name
Test status
Simulation time 52040987 ps
CPU time 1.19 seconds
Started Mar 12 02:45:16 PM PDT 24
Finished Mar 12 02:45:17 PM PDT 24
Peak memory 214848 kb
Host smart-82f680de-8972-48ac-9e2b-fcecfdf84738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856110432 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert.3856110432
Directory /workspace/42.edn_alert/latest

Test location /workspace/coverage/default/42.edn_alert_test.53254729
Short name T684
Test name
Test status
Simulation time 33005130 ps
CPU time 0.78 seconds
Started Mar 12 02:45:22 PM PDT 24
Finished Mar 12 02:45:22 PM PDT 24
Peak memory 204976 kb
Host smart-7ff78d4d-9314-4b12-8aef-22b4c36a2d56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53254729 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_alert_test.53254729
Directory /workspace/42.edn_alert_test/latest

Test location /workspace/coverage/default/42.edn_disable.1074979949
Short name T162
Test name
Test status
Simulation time 39436489 ps
CPU time 0.84 seconds
Started Mar 12 02:45:18 PM PDT 24
Finished Mar 12 02:45:19 PM PDT 24
Peak memory 215056 kb
Host smart-a007a3a3-3f4b-4348-9589-71fa9bdadc1e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074979949 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_disable.1074979949
Directory /workspace/42.edn_disable/latest

Test location /workspace/coverage/default/42.edn_disable_auto_req_mode.551626465
Short name T736
Test name
Test status
Simulation time 24322592 ps
CPU time 0.99 seconds
Started Mar 12 02:45:17 PM PDT 24
Finished Mar 12 02:45:18 PM PDT 24
Peak memory 216556 kb
Host smart-61639ff6-8cdf-49d4-838f-2416bdc0a15c
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551626465 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_di
sable_auto_req_mode.551626465
Directory /workspace/42.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/42.edn_err.883006240
Short name T329
Test name
Test status
Simulation time 27935173 ps
CPU time 0.79 seconds
Started Mar 12 02:45:16 PM PDT 24
Finished Mar 12 02:45:17 PM PDT 24
Peak memory 216788 kb
Host smart-34ed2326-58c3-438a-8a6e-18d63c42100e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883006240 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_err.883006240
Directory /workspace/42.edn_err/latest

Test location /workspace/coverage/default/42.edn_genbits.695656782
Short name T341
Test name
Test status
Simulation time 89141834 ps
CPU time 1.27 seconds
Started Mar 12 02:45:19 PM PDT 24
Finished Mar 12 02:45:21 PM PDT 24
Peak memory 216764 kb
Host smart-e7915189-dafa-4b8d-ab3d-4281f2f37370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695656782 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_genbits.695656782
Directory /workspace/42.edn_genbits/latest

Test location /workspace/coverage/default/42.edn_intr.3685783686
Short name T562
Test name
Test status
Simulation time 27479669 ps
CPU time 1.05 seconds
Started Mar 12 02:45:18 PM PDT 24
Finished Mar 12 02:45:20 PM PDT 24
Peak memory 222584 kb
Host smart-bc0031c3-3950-4024-88a0-146a11ee2872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685783686 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_intr.3685783686
Directory /workspace/42.edn_intr/latest

Test location /workspace/coverage/default/42.edn_smoke.2865444645
Short name T624
Test name
Test status
Simulation time 21498833 ps
CPU time 0.87 seconds
Started Mar 12 02:45:17 PM PDT 24
Finished Mar 12 02:45:18 PM PDT 24
Peak memory 214452 kb
Host smart-84f39b29-972d-4ed7-8c5b-042c1ff16f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865444645 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_smoke.2865444645
Directory /workspace/42.edn_smoke/latest

Test location /workspace/coverage/default/42.edn_stress_all.2874012554
Short name T504
Test name
Test status
Simulation time 652459951 ps
CPU time 5.03 seconds
Started Mar 12 02:45:17 PM PDT 24
Finished Mar 12 02:45:22 PM PDT 24
Peak memory 218488 kb
Host smart-924c0736-5137-4eee-99ff-bfe53cc453b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874012554 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.edn_stress_all.2874012554
Directory /workspace/42.edn_stress_all/latest

Test location /workspace/coverage/default/42.edn_stress_all_with_rand_reset.1158772644
Short name T59
Test name
Test status
Simulation time 172813878530 ps
CPU time 1004.17 seconds
Started Mar 12 02:45:19 PM PDT 24
Finished Mar 12 03:02:03 PM PDT 24
Peak memory 219500 kb
Host smart-a0618aab-0fc4-4b54-b72c-85027c505efb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158772644 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 42.edn_stress_all_with_rand_reset.1158772644
Directory /workspace/42.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.edn_alert.1337630853
Short name T467
Test name
Test status
Simulation time 126963412 ps
CPU time 1.03 seconds
Started Mar 12 02:45:17 PM PDT 24
Finished Mar 12 02:45:19 PM PDT 24
Peak memory 214872 kb
Host smart-926790cf-6050-4f96-b2dc-1a21c593ae33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337630853 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert.1337630853
Directory /workspace/43.edn_alert/latest

Test location /workspace/coverage/default/43.edn_alert_test.1782770019
Short name T656
Test name
Test status
Simulation time 22278979 ps
CPU time 0.85 seconds
Started Mar 12 02:45:16 PM PDT 24
Finished Mar 12 02:45:17 PM PDT 24
Peak memory 206120 kb
Host smart-cacd1d1c-29c8-4e4d-b7e0-0db5149d5d96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782770019 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_alert_test.1782770019
Directory /workspace/43.edn_alert_test/latest

Test location /workspace/coverage/default/43.edn_disable.2271325130
Short name T113
Test name
Test status
Simulation time 51601501 ps
CPU time 0.79 seconds
Started Mar 12 02:45:20 PM PDT 24
Finished Mar 12 02:45:21 PM PDT 24
Peak memory 214956 kb
Host smart-ace8c9e7-5db6-421c-a4b4-cd9e3b609767
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271325130 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_disable.2271325130
Directory /workspace/43.edn_disable/latest

Test location /workspace/coverage/default/43.edn_err.2654991374
Short name T43
Test name
Test status
Simulation time 27753464 ps
CPU time 1.06 seconds
Started Mar 12 02:45:18 PM PDT 24
Finished Mar 12 02:45:20 PM PDT 24
Peak memory 230532 kb
Host smart-99c604ed-340b-4c03-96d5-b4c8d1089c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654991374 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_err.2654991374
Directory /workspace/43.edn_err/latest

Test location /workspace/coverage/default/43.edn_genbits.1138346661
Short name T385
Test name
Test status
Simulation time 33977209 ps
CPU time 1.34 seconds
Started Mar 12 02:45:19 PM PDT 24
Finished Mar 12 02:45:21 PM PDT 24
Peak memory 217844 kb
Host smart-c10973cf-bda3-47fd-9536-81768f48e43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138346661 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_genbits.1138346661
Directory /workspace/43.edn_genbits/latest

Test location /workspace/coverage/default/43.edn_intr.3982723023
Short name T403
Test name
Test status
Simulation time 45391679 ps
CPU time 0.78 seconds
Started Mar 12 02:45:15 PM PDT 24
Finished Mar 12 02:45:16 PM PDT 24
Peak memory 214696 kb
Host smart-3cd76eae-1e94-462d-afd6-0c40df9a598d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982723023 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_intr.3982723023
Directory /workspace/43.edn_intr/latest

Test location /workspace/coverage/default/43.edn_smoke.1858500765
Short name T310
Test name
Test status
Simulation time 31376545 ps
CPU time 1.01 seconds
Started Mar 12 02:45:19 PM PDT 24
Finished Mar 12 02:45:20 PM PDT 24
Peak memory 214444 kb
Host smart-e51069bb-de70-4484-8d45-05c90b7150ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858500765 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_smoke.1858500765
Directory /workspace/43.edn_smoke/latest

Test location /workspace/coverage/default/43.edn_stress_all.2449599132
Short name T361
Test name
Test status
Simulation time 2414967742 ps
CPU time 4.45 seconds
Started Mar 12 02:45:21 PM PDT 24
Finished Mar 12 02:45:25 PM PDT 24
Peak memory 214524 kb
Host smart-77e8b39e-b1a6-41fa-a2ad-cb8b62e1d917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449599132 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.edn_stress_all.2449599132
Directory /workspace/43.edn_stress_all/latest

Test location /workspace/coverage/default/43.edn_stress_all_with_rand_reset.3624060917
Short name T567
Test name
Test status
Simulation time 313978953195 ps
CPU time 1837.74 seconds
Started Mar 12 02:45:16 PM PDT 24
Finished Mar 12 03:15:54 PM PDT 24
Peak memory 224176 kb
Host smart-f2113fb3-aec5-454f-9344-73cd5be63997
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624060917 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 43.edn_stress_all_with_rand_reset.3624060917
Directory /workspace/43.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.edn_alert.2341696253
Short name T244
Test name
Test status
Simulation time 71571805 ps
CPU time 1.14 seconds
Started Mar 12 02:45:19 PM PDT 24
Finished Mar 12 02:45:21 PM PDT 24
Peak memory 214800 kb
Host smart-839a6c4b-0e90-4374-8754-805ee8570b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341696253 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert.2341696253
Directory /workspace/44.edn_alert/latest

Test location /workspace/coverage/default/44.edn_alert_test.2790875014
Short name T732
Test name
Test status
Simulation time 58395082 ps
CPU time 0.94 seconds
Started Mar 12 02:45:17 PM PDT 24
Finished Mar 12 02:45:19 PM PDT 24
Peak memory 206092 kb
Host smart-02e2259e-9fcd-409e-950b-3b3263a1e8a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790875014 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_alert_test.2790875014
Directory /workspace/44.edn_alert_test/latest

Test location /workspace/coverage/default/44.edn_disable.52869053
Short name T602
Test name
Test status
Simulation time 11287684 ps
CPU time 0.87 seconds
Started Mar 12 02:45:19 PM PDT 24
Finished Mar 12 02:45:20 PM PDT 24
Peak memory 214960 kb
Host smart-a0d4f842-55b9-4e6f-a881-70d9a15ca7f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52869053 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_disable.52869053
Directory /workspace/44.edn_disable/latest

Test location /workspace/coverage/default/44.edn_disable_auto_req_mode.2612429465
Short name T659
Test name
Test status
Simulation time 203845041 ps
CPU time 1.07 seconds
Started Mar 12 02:45:19 PM PDT 24
Finished Mar 12 02:45:20 PM PDT 24
Peak memory 216724 kb
Host smart-7275ded9-f4f4-42b9-bfdc-e47ae9ee133e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612429465 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_d
isable_auto_req_mode.2612429465
Directory /workspace/44.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/44.edn_err.2021856449
Short name T701
Test name
Test status
Simulation time 21857128 ps
CPU time 1.02 seconds
Started Mar 12 02:45:17 PM PDT 24
Finished Mar 12 02:45:19 PM PDT 24
Peak memory 222380 kb
Host smart-688389dd-1832-4987-90a9-a255c009829b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021856449 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_err.2021856449
Directory /workspace/44.edn_err/latest

Test location /workspace/coverage/default/44.edn_genbits.3280243583
Short name T618
Test name
Test status
Simulation time 48992349 ps
CPU time 1.56 seconds
Started Mar 12 02:45:20 PM PDT 24
Finished Mar 12 02:45:21 PM PDT 24
Peak memory 217920 kb
Host smart-a89b5713-9ff0-4e6e-acb4-de18ee3d397c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280243583 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_genbits.3280243583
Directory /workspace/44.edn_genbits/latest

Test location /workspace/coverage/default/44.edn_intr.3765924476
Short name T134
Test name
Test status
Simulation time 22432574 ps
CPU time 0.94 seconds
Started Mar 12 02:45:21 PM PDT 24
Finished Mar 12 02:45:22 PM PDT 24
Peak memory 214664 kb
Host smart-423233be-9a53-47fa-be4a-cb71625c5e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765924476 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_intr.3765924476
Directory /workspace/44.edn_intr/latest

Test location /workspace/coverage/default/44.edn_smoke.3701850796
Short name T774
Test name
Test status
Simulation time 16127993 ps
CPU time 0.96 seconds
Started Mar 12 02:45:20 PM PDT 24
Finished Mar 12 02:45:21 PM PDT 24
Peak memory 214468 kb
Host smart-4f2e034d-8fe1-44d0-8e64-3baecc1a284b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701850796 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_smoke.3701850796
Directory /workspace/44.edn_smoke/latest

Test location /workspace/coverage/default/44.edn_stress_all.3708943485
Short name T147
Test name
Test status
Simulation time 669596268 ps
CPU time 6.64 seconds
Started Mar 12 02:45:19 PM PDT 24
Finished Mar 12 02:45:26 PM PDT 24
Peak memory 214368 kb
Host smart-7d09c92a-aee5-497a-ae48-1a94d9b35068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708943485 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.edn_stress_all.3708943485
Directory /workspace/44.edn_stress_all/latest

Test location /workspace/coverage/default/44.edn_stress_all_with_rand_reset.1174890112
Short name T529
Test name
Test status
Simulation time 316518688500 ps
CPU time 1125.05 seconds
Started Mar 12 02:45:15 PM PDT 24
Finished Mar 12 03:04:01 PM PDT 24
Peak memory 230580 kb
Host smart-c1d36472-6ae7-4989-a0c4-e73cc049b1d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174890112 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 44.edn_stress_all_with_rand_reset.1174890112
Directory /workspace/44.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.edn_alert.795181563
Short name T718
Test name
Test status
Simulation time 210777235 ps
CPU time 1.07 seconds
Started Mar 12 02:45:27 PM PDT 24
Finished Mar 12 02:45:28 PM PDT 24
Peak memory 214860 kb
Host smart-a1ac87da-fba9-4064-a55c-c0c82d892d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795181563 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert.795181563
Directory /workspace/45.edn_alert/latest

Test location /workspace/coverage/default/45.edn_alert_test.2333891730
Short name T830
Test name
Test status
Simulation time 32120225 ps
CPU time 0.89 seconds
Started Mar 12 02:45:27 PM PDT 24
Finished Mar 12 02:45:29 PM PDT 24
Peak memory 205692 kb
Host smart-1aa8ec72-e9ba-4d05-97f1-edc6c64f9eaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333891730 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_alert_test.2333891730
Directory /workspace/45.edn_alert_test/latest

Test location /workspace/coverage/default/45.edn_disable.2287212876
Short name T811
Test name
Test status
Simulation time 34102029 ps
CPU time 0.8 seconds
Started Mar 12 02:45:26 PM PDT 24
Finished Mar 12 02:45:27 PM PDT 24
Peak memory 215084 kb
Host smart-82456f6c-f360-4eb4-a939-7a75a39b5cb0
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287212876 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_disable.2287212876
Directory /workspace/45.edn_disable/latest

Test location /workspace/coverage/default/45.edn_disable_auto_req_mode.1228633658
Short name T543
Test name
Test status
Simulation time 63556273 ps
CPU time 1.19 seconds
Started Mar 12 02:45:28 PM PDT 24
Finished Mar 12 02:45:29 PM PDT 24
Peak memory 215608 kb
Host smart-f778a573-1cf7-4936-ada2-5764a0a9b386
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228633658 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_d
isable_auto_req_mode.1228633658
Directory /workspace/45.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/45.edn_genbits.2480208281
Short name T596
Test name
Test status
Simulation time 29139588 ps
CPU time 1.25 seconds
Started Mar 12 02:45:16 PM PDT 24
Finished Mar 12 02:45:17 PM PDT 24
Peak memory 216924 kb
Host smart-c4163f8d-1391-43ba-b813-54e4e668dfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480208281 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_genbits.2480208281
Directory /workspace/45.edn_genbits/latest

Test location /workspace/coverage/default/45.edn_intr.3991955849
Short name T674
Test name
Test status
Simulation time 44287717 ps
CPU time 0.8 seconds
Started Mar 12 02:45:26 PM PDT 24
Finished Mar 12 02:45:27 PM PDT 24
Peak memory 214680 kb
Host smart-2a1ad473-9181-4cf3-8750-0339beb42e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991955849 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_intr.3991955849
Directory /workspace/45.edn_intr/latest

Test location /workspace/coverage/default/45.edn_smoke.602654614
Short name T693
Test name
Test status
Simulation time 19659357 ps
CPU time 0.94 seconds
Started Mar 12 02:45:17 PM PDT 24
Finished Mar 12 02:45:18 PM PDT 24
Peak memory 214480 kb
Host smart-6e99f22a-54b8-4b9d-8df2-84942774e9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602654614 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_smoke.602654614
Directory /workspace/45.edn_smoke/latest

Test location /workspace/coverage/default/45.edn_stress_all.3931217053
Short name T743
Test name
Test status
Simulation time 156347828 ps
CPU time 1.34 seconds
Started Mar 12 02:45:27 PM PDT 24
Finished Mar 12 02:45:28 PM PDT 24
Peak memory 214460 kb
Host smart-9e34a25b-158b-40d2-a67c-b0b2dce9a443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931217053 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.edn_stress_all.3931217053
Directory /workspace/45.edn_stress_all/latest

Test location /workspace/coverage/default/45.edn_stress_all_with_rand_reset.3151026793
Short name T664
Test name
Test status
Simulation time 39168434642 ps
CPU time 166.83 seconds
Started Mar 12 02:45:26 PM PDT 24
Finished Mar 12 02:48:13 PM PDT 24
Peak memory 219024 kb
Host smart-aaf90a04-37cd-4cf7-9b78-27d5d2004d04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151026793 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.edn_stress_all_with_rand_reset.3151026793
Directory /workspace/45.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.edn_alert.303805254
Short name T252
Test name
Test status
Simulation time 30717067 ps
CPU time 1.25 seconds
Started Mar 12 02:45:25 PM PDT 24
Finished Mar 12 02:45:27 PM PDT 24
Peak memory 214824 kb
Host smart-988152e5-eb41-4fb9-9dbb-a451aed11220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303805254 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert.303805254
Directory /workspace/46.edn_alert/latest

Test location /workspace/coverage/default/46.edn_alert_test.2458159355
Short name T36
Test name
Test status
Simulation time 63574773 ps
CPU time 0.87 seconds
Started Mar 12 02:45:26 PM PDT 24
Finished Mar 12 02:45:27 PM PDT 24
Peak memory 206060 kb
Host smart-afd88058-6413-4788-afef-1471d3eeb22a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458159355 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_alert_test.2458159355
Directory /workspace/46.edn_alert_test/latest

Test location /workspace/coverage/default/46.edn_disable.256229554
Short name T444
Test name
Test status
Simulation time 11961488 ps
CPU time 0.84 seconds
Started Mar 12 02:45:30 PM PDT 24
Finished Mar 12 02:45:31 PM PDT 24
Peak memory 214804 kb
Host smart-d1b6d94f-b861-4d7b-b7d5-32ac17e4f9bb
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256229554 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_disable.256229554
Directory /workspace/46.edn_disable/latest

Test location /workspace/coverage/default/46.edn_disable_auto_req_mode.4102264756
Short name T711
Test name
Test status
Simulation time 34627447 ps
CPU time 0.97 seconds
Started Mar 12 02:45:27 PM PDT 24
Finished Mar 12 02:45:29 PM PDT 24
Peak memory 215400 kb
Host smart-49a31c65-b8c7-480f-8c9d-c77a220f905e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102264756 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_d
isable_auto_req_mode.4102264756
Directory /workspace/46.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/46.edn_err.3175968919
Short name T564
Test name
Test status
Simulation time 30507811 ps
CPU time 0.86 seconds
Started Mar 12 02:45:29 PM PDT 24
Finished Mar 12 02:45:30 PM PDT 24
Peak memory 217344 kb
Host smart-9b6ac976-1315-4800-9255-b1fafbb3df43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175968919 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_err.3175968919
Directory /workspace/46.edn_err/latest

Test location /workspace/coverage/default/46.edn_genbits.237714820
Short name T497
Test name
Test status
Simulation time 46015080 ps
CPU time 1.71 seconds
Started Mar 12 02:45:32 PM PDT 24
Finished Mar 12 02:45:34 PM PDT 24
Peak memory 215604 kb
Host smart-569c418c-6c23-4c10-a71e-4dae6ee9a3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237714820 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_genbits.237714820
Directory /workspace/46.edn_genbits/latest

Test location /workspace/coverage/default/46.edn_intr.2695964160
Short name T140
Test name
Test status
Simulation time 26101197 ps
CPU time 0.94 seconds
Started Mar 12 02:45:32 PM PDT 24
Finished Mar 12 02:45:33 PM PDT 24
Peak memory 214648 kb
Host smart-24347fec-1af4-451e-b3b4-6c94f7da77a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695964160 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_intr.2695964160
Directory /workspace/46.edn_intr/latest

Test location /workspace/coverage/default/46.edn_smoke.1006200723
Short name T408
Test name
Test status
Simulation time 17577453 ps
CPU time 0.88 seconds
Started Mar 12 02:45:26 PM PDT 24
Finished Mar 12 02:45:27 PM PDT 24
Peak memory 214440 kb
Host smart-7ccaab21-37a3-4c48-82ab-741e54dc3810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006200723 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_smoke.1006200723
Directory /workspace/46.edn_smoke/latest

Test location /workspace/coverage/default/46.edn_stress_all.2315679655
Short name T565
Test name
Test status
Simulation time 1215542579 ps
CPU time 1.9 seconds
Started Mar 12 02:45:27 PM PDT 24
Finished Mar 12 02:45:30 PM PDT 24
Peak memory 215540 kb
Host smart-2ef22532-7a4c-49ca-b598-616b6f1ca51a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315679655 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.edn_stress_all.2315679655
Directory /workspace/46.edn_stress_all/latest

Test location /workspace/coverage/default/46.edn_stress_all_with_rand_reset.1804331442
Short name T534
Test name
Test status
Simulation time 202058329650 ps
CPU time 2106.75 seconds
Started Mar 12 02:45:26 PM PDT 24
Finished Mar 12 03:20:34 PM PDT 24
Peak memory 229056 kb
Host smart-23bb9e9c-e302-4f4a-b83a-1dbde53ed973
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804331442 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 46.edn_stress_all_with_rand_reset.1804331442
Directory /workspace/46.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.edn_alert.2330403757
Short name T575
Test name
Test status
Simulation time 42957097 ps
CPU time 1.19 seconds
Started Mar 12 02:45:27 PM PDT 24
Finished Mar 12 02:45:29 PM PDT 24
Peak memory 214852 kb
Host smart-aa2c5af9-082b-4b0e-b4c9-3bbfbb7f9cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330403757 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert.2330403757
Directory /workspace/47.edn_alert/latest

Test location /workspace/coverage/default/47.edn_alert_test.2117718390
Short name T668
Test name
Test status
Simulation time 51122588 ps
CPU time 0.85 seconds
Started Mar 12 02:45:27 PM PDT 24
Finished Mar 12 02:45:28 PM PDT 24
Peak memory 206096 kb
Host smart-d9c30545-157b-4045-902a-ccba9bad380d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117718390 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_alert_test.2117718390
Directory /workspace/47.edn_alert_test/latest

Test location /workspace/coverage/default/47.edn_disable_auto_req_mode.1538357920
Short name T643
Test name
Test status
Simulation time 223007103 ps
CPU time 1.09 seconds
Started Mar 12 02:45:26 PM PDT 24
Finished Mar 12 02:45:27 PM PDT 24
Peak memory 215484 kb
Host smart-b9e0f260-3bc0-4dc1-96c9-d9dc8b74acb2
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538357920 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_d
isable_auto_req_mode.1538357920
Directory /workspace/47.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/47.edn_err.3980585529
Short name T87
Test name
Test status
Simulation time 19910540 ps
CPU time 1.07 seconds
Started Mar 12 02:45:26 PM PDT 24
Finished Mar 12 02:45:27 PM PDT 24
Peak memory 217016 kb
Host smart-2107c1bc-0523-4707-b56b-e8482c2b03ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980585529 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_err.3980585529
Directory /workspace/47.edn_err/latest

Test location /workspace/coverage/default/47.edn_genbits.3217851931
Short name T748
Test name
Test status
Simulation time 153980621 ps
CPU time 1.09 seconds
Started Mar 12 02:45:25 PM PDT 24
Finished Mar 12 02:45:27 PM PDT 24
Peak memory 215648 kb
Host smart-37441fbf-7a1a-4dee-8720-fcdb775305a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217851931 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_genbits.3217851931
Directory /workspace/47.edn_genbits/latest

Test location /workspace/coverage/default/47.edn_intr.535797995
Short name T441
Test name
Test status
Simulation time 29648662 ps
CPU time 0.93 seconds
Started Mar 12 02:45:26 PM PDT 24
Finished Mar 12 02:45:27 PM PDT 24
Peak memory 214648 kb
Host smart-06ee07b6-261d-4acb-9437-854ddff6da61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535797995 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_intr.535797995
Directory /workspace/47.edn_intr/latest

Test location /workspace/coverage/default/47.edn_smoke.1858809569
Short name T734
Test name
Test status
Simulation time 39496997 ps
CPU time 0.93 seconds
Started Mar 12 02:45:30 PM PDT 24
Finished Mar 12 02:45:32 PM PDT 24
Peak memory 214384 kb
Host smart-3b6e19f5-3721-48f4-8682-449d0995649d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858809569 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_smoke.1858809569
Directory /workspace/47.edn_smoke/latest

Test location /workspace/coverage/default/47.edn_stress_all.514203765
Short name T599
Test name
Test status
Simulation time 502921065 ps
CPU time 3.46 seconds
Started Mar 12 02:45:27 PM PDT 24
Finished Mar 12 02:45:32 PM PDT 24
Peak memory 215592 kb
Host smart-34165fd1-2650-4ded-9a31-e5c2ce716213
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514203765 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.edn_stress_all.514203765
Directory /workspace/47.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_alert.868886706
Short name T123
Test name
Test status
Simulation time 75699065 ps
CPU time 1.11 seconds
Started Mar 12 02:45:30 PM PDT 24
Finished Mar 12 02:45:32 PM PDT 24
Peak memory 214784 kb
Host smart-5c449707-b434-4d5c-8708-e2dfde558eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868886706 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert.868886706
Directory /workspace/48.edn_alert/latest

Test location /workspace/coverage/default/48.edn_alert_test.1483917442
Short name T522
Test name
Test status
Simulation time 27417708 ps
CPU time 0.94 seconds
Started Mar 12 02:45:36 PM PDT 24
Finished Mar 12 02:45:38 PM PDT 24
Peak memory 205592 kb
Host smart-21cadec3-75f1-4b96-9897-af7cf36eadb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483917442 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_alert_test.1483917442
Directory /workspace/48.edn_alert_test/latest

Test location /workspace/coverage/default/48.edn_disable.2473169436
Short name T166
Test name
Test status
Simulation time 14126788 ps
CPU time 0.87 seconds
Started Mar 12 02:45:36 PM PDT 24
Finished Mar 12 02:45:38 PM PDT 24
Peak memory 215052 kb
Host smart-fe4d146c-a2fb-4f94-ac6a-27c7fbe90988
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473169436 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_disable.2473169436
Directory /workspace/48.edn_disable/latest

Test location /workspace/coverage/default/48.edn_disable_auto_req_mode.3531089494
Short name T606
Test name
Test status
Simulation time 80520094 ps
CPU time 1.15 seconds
Started Mar 12 02:45:28 PM PDT 24
Finished Mar 12 02:45:29 PM PDT 24
Peak memory 216832 kb
Host smart-2c313cd8-111c-47ee-829a-43aa0f8b32bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531089494 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_d
isable_auto_req_mode.3531089494
Directory /workspace/48.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/48.edn_err.3397129970
Short name T822
Test name
Test status
Simulation time 27927638 ps
CPU time 1.05 seconds
Started Mar 12 02:45:30 PM PDT 24
Finished Mar 12 02:45:31 PM PDT 24
Peak memory 222228 kb
Host smart-914047bb-bafd-4993-be75-8e294e34011d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397129970 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_err.3397129970
Directory /workspace/48.edn_err/latest

Test location /workspace/coverage/default/48.edn_genbits.3781642347
Short name T312
Test name
Test status
Simulation time 70950234 ps
CPU time 0.94 seconds
Started Mar 12 02:45:28 PM PDT 24
Finished Mar 12 02:45:29 PM PDT 24
Peak memory 215472 kb
Host smart-0e509d25-d11b-4650-a449-0a7a9daf3d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781642347 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_genbits.3781642347
Directory /workspace/48.edn_genbits/latest

Test location /workspace/coverage/default/48.edn_intr.3939772923
Short name T142
Test name
Test status
Simulation time 25535101 ps
CPU time 0.94 seconds
Started Mar 12 02:45:26 PM PDT 24
Finished Mar 12 02:45:27 PM PDT 24
Peak memory 214756 kb
Host smart-3e25118c-1c7f-4603-abad-eb5768044e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939772923 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_intr.3939772923
Directory /workspace/48.edn_intr/latest

Test location /workspace/coverage/default/48.edn_smoke.1075664991
Short name T314
Test name
Test status
Simulation time 45810769 ps
CPU time 1.01 seconds
Started Mar 12 02:45:26 PM PDT 24
Finished Mar 12 02:45:27 PM PDT 24
Peak memory 214456 kb
Host smart-e4d8597a-939f-4ccf-8150-6fa1eacac29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075664991 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_smoke.1075664991
Directory /workspace/48.edn_smoke/latest

Test location /workspace/coverage/default/48.edn_stress_all.235624331
Short name T616
Test name
Test status
Simulation time 527989290 ps
CPU time 3.31 seconds
Started Mar 12 02:45:24 PM PDT 24
Finished Mar 12 02:45:28 PM PDT 24
Peak memory 215428 kb
Host smart-630d32e7-bf97-4ac7-8207-dafa9ab472c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235624331 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.edn_stress_all.235624331
Directory /workspace/48.edn_stress_all/latest

Test location /workspace/coverage/default/48.edn_stress_all_with_rand_reset.1851863670
Short name T392
Test name
Test status
Simulation time 66197853479 ps
CPU time 740.77 seconds
Started Mar 12 02:45:25 PM PDT 24
Finished Mar 12 02:57:46 PM PDT 24
Peak memory 222728 kb
Host smart-38b35d97-9ef2-4005-b6d1-86ba6cc484e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851863670 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.edn_stress_all_with_rand_reset.1851863670
Directory /workspace/48.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.edn_alert_test.2336706074
Short name T3
Test name
Test status
Simulation time 17172373 ps
CPU time 0.96 seconds
Started Mar 12 02:45:36 PM PDT 24
Finished Mar 12 02:45:38 PM PDT 24
Peak memory 205160 kb
Host smart-f336f306-189f-49e6-bc3b-c81919fad2e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336706074 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_alert_test.2336706074
Directory /workspace/49.edn_alert_test/latest

Test location /workspace/coverage/default/49.edn_disable.2852292845
Short name T171
Test name
Test status
Simulation time 28498767 ps
CPU time 0.79 seconds
Started Mar 12 02:45:34 PM PDT 24
Finished Mar 12 02:45:36 PM PDT 24
Peak memory 215064 kb
Host smart-472b4c3a-bd93-4ca3-ab64-93601580d3f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852292845 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_disable.2852292845
Directory /workspace/49.edn_disable/latest

Test location /workspace/coverage/default/49.edn_err.172336358
Short name T775
Test name
Test status
Simulation time 245881347 ps
CPU time 1.14 seconds
Started Mar 12 02:45:36 PM PDT 24
Finished Mar 12 02:45:37 PM PDT 24
Peak memory 223420 kb
Host smart-faea4391-e307-4205-b186-baa0418d1d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172336358 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_err.172336358
Directory /workspace/49.edn_err/latest

Test location /workspace/coverage/default/49.edn_intr.1255465830
Short name T369
Test name
Test status
Simulation time 27552973 ps
CPU time 0.92 seconds
Started Mar 12 02:45:39 PM PDT 24
Finished Mar 12 02:45:41 PM PDT 24
Peak memory 214712 kb
Host smart-44cfc17d-11f0-4f6d-8506-f7e63afd7405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255465830 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_intr.1255465830
Directory /workspace/49.edn_intr/latest

Test location /workspace/coverage/default/49.edn_smoke.2641028932
Short name T600
Test name
Test status
Simulation time 15313861 ps
CPU time 0.99 seconds
Started Mar 12 02:45:37 PM PDT 24
Finished Mar 12 02:45:39 PM PDT 24
Peak memory 214348 kb
Host smart-d5a53159-76df-437a-a4e3-343f2e046d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641028932 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_smoke.2641028932
Directory /workspace/49.edn_smoke/latest

Test location /workspace/coverage/default/49.edn_stress_all.924664643
Short name T713
Test name
Test status
Simulation time 156840121 ps
CPU time 3.48 seconds
Started Mar 12 02:45:34 PM PDT 24
Finished Mar 12 02:45:38 PM PDT 24
Peak memory 215728 kb
Host smart-a7e0f01f-d4c5-4c69-9bb9-f112007bec07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924664643 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.edn_stress_all.924664643
Directory /workspace/49.edn_stress_all/latest

Test location /workspace/coverage/default/49.edn_stress_all_with_rand_reset.1717448179
Short name T813
Test name
Test status
Simulation time 34902984805 ps
CPU time 225.86 seconds
Started Mar 12 02:45:34 PM PDT 24
Finished Mar 12 02:49:21 PM PDT 24
Peak memory 217504 kb
Host smart-1dddac4f-87a7-4170-b0cf-9b312faade57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717448179 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 49.edn_stress_all_with_rand_reset.1717448179
Directory /workspace/49.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.edn_alert.2385603598
Short name T783
Test name
Test status
Simulation time 41792151 ps
CPU time 1.27 seconds
Started Mar 12 02:43:20 PM PDT 24
Finished Mar 12 02:43:21 PM PDT 24
Peak memory 214736 kb
Host smart-fc50237e-fa73-4a21-9920-649a5f0eee14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385603598 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert.2385603598
Directory /workspace/5.edn_alert/latest

Test location /workspace/coverage/default/5.edn_alert_test.3290320619
Short name T687
Test name
Test status
Simulation time 18396245 ps
CPU time 0.92 seconds
Started Mar 12 02:43:24 PM PDT 24
Finished Mar 12 02:43:25 PM PDT 24
Peak memory 206132 kb
Host smart-71b23f82-83e9-46cf-b3ef-66c803f44589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290320619 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_alert_test.3290320619
Directory /workspace/5.edn_alert_test/latest

Test location /workspace/coverage/default/5.edn_disable.3100333801
Short name T118
Test name
Test status
Simulation time 32428270 ps
CPU time 0.78 seconds
Started Mar 12 02:43:21 PM PDT 24
Finished Mar 12 02:43:22 PM PDT 24
Peak memory 214864 kb
Host smart-43efe994-7b2f-4eb8-a9d3-37de43e9264e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100333801 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_disable.3100333801
Directory /workspace/5.edn_disable/latest

Test location /workspace/coverage/default/5.edn_disable_auto_req_mode.2432978199
Short name T566
Test name
Test status
Simulation time 64805418 ps
CPU time 1.12 seconds
Started Mar 12 02:43:23 PM PDT 24
Finished Mar 12 02:43:25 PM PDT 24
Peak memory 216956 kb
Host smart-3e8bdcf1-ddc3-4203-8de7-9699b13d434a
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432978199 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_di
sable_auto_req_mode.2432978199
Directory /workspace/5.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/5.edn_err.2808264532
Short name T92
Test name
Test status
Simulation time 37043888 ps
CPU time 0.88 seconds
Started Mar 12 02:43:18 PM PDT 24
Finished Mar 12 02:43:19 PM PDT 24
Peak memory 215964 kb
Host smart-2ac36a3d-aa39-4ba3-bcc5-1fa684ebaad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808264532 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_err.2808264532
Directory /workspace/5.edn_err/latest

Test location /workspace/coverage/default/5.edn_genbits.473025284
Short name T430
Test name
Test status
Simulation time 58535000 ps
CPU time 1.65 seconds
Started Mar 12 02:43:18 PM PDT 24
Finished Mar 12 02:43:20 PM PDT 24
Peak memory 216596 kb
Host smart-24f63d2c-f796-4d5a-a55d-ff07f254393c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473025284 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_genbits.473025284
Directory /workspace/5.edn_genbits/latest

Test location /workspace/coverage/default/5.edn_intr.816307964
Short name T560
Test name
Test status
Simulation time 31068663 ps
CPU time 0.95 seconds
Started Mar 12 02:43:19 PM PDT 24
Finished Mar 12 02:43:20 PM PDT 24
Peak memory 223268 kb
Host smart-156ef743-0d36-46b8-bb47-a3921410c6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816307964 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_intr.816307964
Directory /workspace/5.edn_intr/latest

Test location /workspace/coverage/default/5.edn_smoke.781650263
Short name T805
Test name
Test status
Simulation time 48482907 ps
CPU time 0.89 seconds
Started Mar 12 02:43:21 PM PDT 24
Finished Mar 12 02:43:22 PM PDT 24
Peak memory 214456 kb
Host smart-589d2c25-99c0-4489-8bcc-4dc7272d0bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781650263 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_smoke.781650263
Directory /workspace/5.edn_smoke/latest

Test location /workspace/coverage/default/5.edn_stress_all.722318761
Short name T578
Test name
Test status
Simulation time 25934297 ps
CPU time 1.11 seconds
Started Mar 12 02:43:21 PM PDT 24
Finished Mar 12 02:43:23 PM PDT 24
Peak memory 214436 kb
Host smart-37fe4069-ff71-4397-b585-d5f9bb205c6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722318761 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.edn_stress_all.722318761
Directory /workspace/5.edn_stress_all/latest

Test location /workspace/coverage/default/5.edn_stress_all_with_rand_reset.4078053137
Short name T458
Test name
Test status
Simulation time 38156229789 ps
CPU time 424.58 seconds
Started Mar 12 02:43:25 PM PDT 24
Finished Mar 12 02:50:30 PM PDT 24
Peak memory 217408 kb
Host smart-30df2035-1332-4678-9682-5a6d3d8f09bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078053137 -assert nopostpr
oc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 5.edn_stress_all_with_rand_reset.4078053137
Directory /workspace/5.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.edn_err.1123583224
Short name T761
Test name
Test status
Simulation time 22674091 ps
CPU time 1.04 seconds
Started Mar 12 02:45:36 PM PDT 24
Finished Mar 12 02:45:39 PM PDT 24
Peak memory 222236 kb
Host smart-e9bafb61-0e42-44f3-b14f-1a96ab0b59a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123583224 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_err.1123583224
Directory /workspace/50.edn_err/latest

Test location /workspace/coverage/default/50.edn_genbits.2011980539
Short name T237
Test name
Test status
Simulation time 34411994 ps
CPU time 1.3 seconds
Started Mar 12 02:45:32 PM PDT 24
Finished Mar 12 02:45:34 PM PDT 24
Peak memory 215696 kb
Host smart-8116e793-bf36-4e66-8225-22be0b3a0a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011980539 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.edn_genbits.2011980539
Directory /workspace/50.edn_genbits/latest

Test location /workspace/coverage/default/51.edn_err.871074412
Short name T97
Test name
Test status
Simulation time 25274948 ps
CPU time 0.94 seconds
Started Mar 12 02:45:36 PM PDT 24
Finished Mar 12 02:45:39 PM PDT 24
Peak memory 217144 kb
Host smart-b2dfa660-cc52-456f-92e0-01fb5704f64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871074412 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_err.871074412
Directory /workspace/51.edn_err/latest

Test location /workspace/coverage/default/51.edn_genbits.1475227429
Short name T608
Test name
Test status
Simulation time 91571029 ps
CPU time 1.18 seconds
Started Mar 12 02:45:39 PM PDT 24
Finished Mar 12 02:45:41 PM PDT 24
Peak memory 215844 kb
Host smart-e304761f-4317-4d98-ae02-cf5b7508082d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475227429 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.edn_genbits.1475227429
Directory /workspace/51.edn_genbits/latest

Test location /workspace/coverage/default/52.edn_err.1140702285
Short name T88
Test name
Test status
Simulation time 32755744 ps
CPU time 1.05 seconds
Started Mar 12 02:45:39 PM PDT 24
Finished Mar 12 02:45:41 PM PDT 24
Peak memory 218332 kb
Host smart-b566f530-3800-48a8-8bcd-4f286bca02df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140702285 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_err.1140702285
Directory /workspace/52.edn_err/latest

Test location /workspace/coverage/default/52.edn_genbits.3998607365
Short name T621
Test name
Test status
Simulation time 102525792 ps
CPU time 1.24 seconds
Started Mar 12 02:45:35 PM PDT 24
Finished Mar 12 02:45:37 PM PDT 24
Peak memory 215724 kb
Host smart-9742ec3b-a9ab-404a-a994-6af1064f877d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998607365 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.edn_genbits.3998607365
Directory /workspace/52.edn_genbits/latest

Test location /workspace/coverage/default/53.edn_err.1368897934
Short name T73
Test name
Test status
Simulation time 29514805 ps
CPU time 0.99 seconds
Started Mar 12 02:45:37 PM PDT 24
Finished Mar 12 02:45:39 PM PDT 24
Peak memory 218404 kb
Host smart-3ad5344a-f7f8-4661-b450-c03222f288d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368897934 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_err.1368897934
Directory /workspace/53.edn_err/latest

Test location /workspace/coverage/default/53.edn_genbits.1238920050
Short name T579
Test name
Test status
Simulation time 69297461 ps
CPU time 1.2 seconds
Started Mar 12 02:45:37 PM PDT 24
Finished Mar 12 02:45:39 PM PDT 24
Peak memory 215708 kb
Host smart-ebd50ff0-324b-4c71-99cd-20090b069706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238920050 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.edn_genbits.1238920050
Directory /workspace/53.edn_genbits/latest

Test location /workspace/coverage/default/54.edn_err.1151585931
Short name T202
Test name
Test status
Simulation time 19319893 ps
CPU time 1.05 seconds
Started Mar 12 02:45:36 PM PDT 24
Finished Mar 12 02:45:38 PM PDT 24
Peak memory 216788 kb
Host smart-6e551079-38f3-459d-a798-530cb2ca6c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151585931 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_err.1151585931
Directory /workspace/54.edn_err/latest

Test location /workspace/coverage/default/54.edn_genbits.999100359
Short name T438
Test name
Test status
Simulation time 33392401 ps
CPU time 1.32 seconds
Started Mar 12 02:45:36 PM PDT 24
Finished Mar 12 02:45:39 PM PDT 24
Peak memory 215724 kb
Host smart-4bc12c52-86ca-41ed-a8c0-5b3e14b91e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999100359 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.edn_genbits.999100359
Directory /workspace/54.edn_genbits/latest

Test location /workspace/coverage/default/55.edn_err.3384299134
Short name T164
Test name
Test status
Simulation time 71983711 ps
CPU time 1.1 seconds
Started Mar 12 02:45:34 PM PDT 24
Finished Mar 12 02:45:35 PM PDT 24
Peak memory 218540 kb
Host smart-20623685-9eec-4e43-9cbc-4744daa86ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384299134 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_err.3384299134
Directory /workspace/55.edn_err/latest

Test location /workspace/coverage/default/55.edn_genbits.3755615734
Short name T635
Test name
Test status
Simulation time 31378039 ps
CPU time 1.16 seconds
Started Mar 12 02:45:33 PM PDT 24
Finished Mar 12 02:45:35 PM PDT 24
Peak memory 215592 kb
Host smart-466e81f0-6b5c-4862-8e14-af7064152677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755615734 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.edn_genbits.3755615734
Directory /workspace/55.edn_genbits/latest

Test location /workspace/coverage/default/56.edn_err.1598530314
Short name T585
Test name
Test status
Simulation time 25813781 ps
CPU time 0.99 seconds
Started Mar 12 02:45:32 PM PDT 24
Finished Mar 12 02:45:34 PM PDT 24
Peak memory 218516 kb
Host smart-e20cef4a-b3f6-4de7-9c15-34313b824e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598530314 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_err.1598530314
Directory /workspace/56.edn_err/latest

Test location /workspace/coverage/default/56.edn_genbits.6976798
Short name T738
Test name
Test status
Simulation time 86791519 ps
CPU time 1.43 seconds
Started Mar 12 02:45:35 PM PDT 24
Finished Mar 12 02:45:37 PM PDT 24
Peak memory 217064 kb
Host smart-5306e7ef-c50d-4d8d-88fa-a08df818b17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6976798 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.edn_genbits.6976798
Directory /workspace/56.edn_genbits/latest

Test location /workspace/coverage/default/57.edn_err.3549336407
Short name T730
Test name
Test status
Simulation time 27057125 ps
CPU time 0.92 seconds
Started Mar 12 02:45:39 PM PDT 24
Finished Mar 12 02:45:41 PM PDT 24
Peak memory 217060 kb
Host smart-7b82d54d-478c-4654-b74b-3bdbb9a1d19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549336407 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_err.3549336407
Directory /workspace/57.edn_err/latest

Test location /workspace/coverage/default/57.edn_genbits.3980022152
Short name T526
Test name
Test status
Simulation time 50508331 ps
CPU time 1.24 seconds
Started Mar 12 02:45:36 PM PDT 24
Finished Mar 12 02:45:39 PM PDT 24
Peak memory 217000 kb
Host smart-d98c9aab-13cb-4a6d-a9ec-da47b4119978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980022152 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.edn_genbits.3980022152
Directory /workspace/57.edn_genbits/latest

Test location /workspace/coverage/default/58.edn_err.3907446229
Short name T524
Test name
Test status
Simulation time 29607866 ps
CPU time 1.25 seconds
Started Mar 12 02:45:36 PM PDT 24
Finished Mar 12 02:45:39 PM PDT 24
Peak memory 218188 kb
Host smart-fa774f15-ff9c-4370-9fbd-07f44e02f7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907446229 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_err.3907446229
Directory /workspace/58.edn_err/latest

Test location /workspace/coverage/default/58.edn_genbits.1134143747
Short name T676
Test name
Test status
Simulation time 89041755 ps
CPU time 1.19 seconds
Started Mar 12 02:45:35 PM PDT 24
Finished Mar 12 02:45:37 PM PDT 24
Peak memory 215644 kb
Host smart-6da3b54e-a291-4055-a885-86ee8619be46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134143747 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.edn_genbits.1134143747
Directory /workspace/58.edn_genbits/latest

Test location /workspace/coverage/default/59.edn_err.3322552000
Short name T44
Test name
Test status
Simulation time 18194542 ps
CPU time 1.1 seconds
Started Mar 12 02:45:33 PM PDT 24
Finished Mar 12 02:45:35 PM PDT 24
Peak memory 222432 kb
Host smart-043ae80b-5f45-40bd-bbd0-cefa28bfa9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322552000 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_err.3322552000
Directory /workspace/59.edn_err/latest

Test location /workspace/coverage/default/59.edn_genbits.4069066079
Short name T765
Test name
Test status
Simulation time 68525342 ps
CPU time 1.68 seconds
Started Mar 12 02:45:39 PM PDT 24
Finished Mar 12 02:45:41 PM PDT 24
Peak memory 216000 kb
Host smart-c807f6d8-27d8-453a-a0bd-b86ad2189d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069066079 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.edn_genbits.4069066079
Directory /workspace/59.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_alert.384293611
Short name T234
Test name
Test status
Simulation time 47888044 ps
CPU time 1.15 seconds
Started Mar 12 02:43:32 PM PDT 24
Finished Mar 12 02:43:33 PM PDT 24
Peak memory 214704 kb
Host smart-6265ef9d-76aa-45ec-b37f-594812aca55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384293611 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert.384293611
Directory /workspace/6.edn_alert/latest

Test location /workspace/coverage/default/6.edn_alert_test.1196972327
Short name T319
Test name
Test status
Simulation time 15129351 ps
CPU time 0.93 seconds
Started Mar 12 02:43:30 PM PDT 24
Finished Mar 12 02:43:31 PM PDT 24
Peak memory 206028 kb
Host smart-fb4d1b54-8741-4740-8710-d53f85e1fdfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196972327 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_alert_test.1196972327
Directory /workspace/6.edn_alert_test/latest

Test location /workspace/coverage/default/6.edn_disable.1794815233
Short name T777
Test name
Test status
Simulation time 18576357 ps
CPU time 0.82 seconds
Started Mar 12 02:43:27 PM PDT 24
Finished Mar 12 02:43:28 PM PDT 24
Peak memory 214960 kb
Host smart-c6a5edb9-f4cf-4faf-bccf-7ba051a9e991
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794815233 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_disable.1794815233
Directory /workspace/6.edn_disable/latest

Test location /workspace/coverage/default/6.edn_disable_auto_req_mode.2397508548
Short name T52
Test name
Test status
Simulation time 38104977 ps
CPU time 1.02 seconds
Started Mar 12 02:43:28 PM PDT 24
Finished Mar 12 02:43:29 PM PDT 24
Peak memory 215424 kb
Host smart-a541ed9f-db63-4fc7-8807-9f9a20beb3d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397508548 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_di
sable_auto_req_mode.2397508548
Directory /workspace/6.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/6.edn_err.3498880942
Short name T658
Test name
Test status
Simulation time 29968959 ps
CPU time 0.87 seconds
Started Mar 12 02:43:27 PM PDT 24
Finished Mar 12 02:43:28 PM PDT 24
Peak memory 217004 kb
Host smart-8bef31ba-32f1-4dfd-b393-9d4f0c4a2305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498880942 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_err.3498880942
Directory /workspace/6.edn_err/latest

Test location /workspace/coverage/default/6.edn_genbits.280504703
Short name T318
Test name
Test status
Simulation time 31793226 ps
CPU time 1.4 seconds
Started Mar 12 02:43:22 PM PDT 24
Finished Mar 12 02:43:24 PM PDT 24
Peak memory 215864 kb
Host smart-7d5d8c6e-175b-4683-a2f3-655b8a94cbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280504703 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_genbits.280504703
Directory /workspace/6.edn_genbits/latest

Test location /workspace/coverage/default/6.edn_intr.3974387915
Short name T380
Test name
Test status
Simulation time 25945521 ps
CPU time 0.97 seconds
Started Mar 12 02:43:29 PM PDT 24
Finished Mar 12 02:43:30 PM PDT 24
Peak memory 214788 kb
Host smart-fe1117fa-be7f-4eb2-8fb6-e6f543221cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974387915 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_intr.3974387915
Directory /workspace/6.edn_intr/latest

Test location /workspace/coverage/default/6.edn_regwen.4091529815
Short name T246
Test name
Test status
Simulation time 27961963 ps
CPU time 0.96 seconds
Started Mar 12 02:43:22 PM PDT 24
Finished Mar 12 02:43:24 PM PDT 24
Peak memory 206216 kb
Host smart-18f7c277-58b9-4de2-9314-5de6c534dfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091529815 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_regwen.4091529815
Directory /workspace/6.edn_regwen/latest

Test location /workspace/coverage/default/6.edn_smoke.3853258353
Short name T336
Test name
Test status
Simulation time 125486626 ps
CPU time 0.91 seconds
Started Mar 12 02:43:23 PM PDT 24
Finished Mar 12 02:43:25 PM PDT 24
Peak memory 214464 kb
Host smart-e877d7ff-7b54-4d14-92b2-a5101990b180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853258353 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_smoke.3853258353
Directory /workspace/6.edn_smoke/latest

Test location /workspace/coverage/default/6.edn_stress_all.1739115329
Short name T650
Test name
Test status
Simulation time 474625312 ps
CPU time 5.17 seconds
Started Mar 12 02:43:21 PM PDT 24
Finished Mar 12 02:43:27 PM PDT 24
Peak memory 214420 kb
Host smart-dd548c28-d83e-4f12-93b4-afc410429fec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739115329 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.1739115329
Directory /workspace/6.edn_stress_all/latest

Test location /workspace/coverage/default/6.edn_stress_all_with_rand_reset.121955553
Short name T198
Test name
Test status
Simulation time 78899893678 ps
CPU time 738.48 seconds
Started Mar 12 02:43:29 PM PDT 24
Finished Mar 12 02:55:48 PM PDT 24
Peak memory 217692 kb
Host smart-3cc43244-519d-4fd3-8020-7a31450cda9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121955553 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.edn_stress_all_with_rand_reset.121955553
Directory /workspace/6.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.edn_err.1327207432
Short name T160
Test name
Test status
Simulation time 65026475 ps
CPU time 0.79 seconds
Started Mar 12 02:45:32 PM PDT 24
Finished Mar 12 02:45:33 PM PDT 24
Peak memory 217288 kb
Host smart-91341e7b-fc51-42ff-9f2a-1207032559f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327207432 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_err.1327207432
Directory /workspace/60.edn_err/latest

Test location /workspace/coverage/default/60.edn_genbits.1551127884
Short name T737
Test name
Test status
Simulation time 41324113 ps
CPU time 1.45 seconds
Started Mar 12 02:45:36 PM PDT 24
Finished Mar 12 02:45:39 PM PDT 24
Peak memory 215768 kb
Host smart-602ca2f9-0da1-4a4a-ad4f-7f96cdf4acc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551127884 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.edn_genbits.1551127884
Directory /workspace/60.edn_genbits/latest

Test location /workspace/coverage/default/61.edn_err.1297897055
Short name T803
Test name
Test status
Simulation time 20221221 ps
CPU time 1.06 seconds
Started Mar 12 02:45:37 PM PDT 24
Finished Mar 12 02:45:39 PM PDT 24
Peak memory 214484 kb
Host smart-4c75218c-227b-4ca2-83ce-c6cc89ce3cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297897055 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_err.1297897055
Directory /workspace/61.edn_err/latest

Test location /workspace/coverage/default/61.edn_genbits.3768899506
Short name T267
Test name
Test status
Simulation time 105701710 ps
CPU time 2.22 seconds
Started Mar 12 02:45:36 PM PDT 24
Finished Mar 12 02:45:39 PM PDT 24
Peak memory 218140 kb
Host smart-d80102a6-03a3-44da-a980-19c961efb105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768899506 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.edn_genbits.3768899506
Directory /workspace/61.edn_genbits/latest

Test location /workspace/coverage/default/62.edn_err.2311061223
Short name T483
Test name
Test status
Simulation time 21277940 ps
CPU time 1.06 seconds
Started Mar 12 02:45:37 PM PDT 24
Finished Mar 12 02:45:39 PM PDT 24
Peak memory 217396 kb
Host smart-37128094-ea25-45f5-a4b3-a1ccbe14b065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311061223 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_err.2311061223
Directory /workspace/62.edn_err/latest

Test location /workspace/coverage/default/62.edn_genbits.1241372006
Short name T238
Test name
Test status
Simulation time 78182426 ps
CPU time 1.14 seconds
Started Mar 12 02:45:39 PM PDT 24
Finished Mar 12 02:45:41 PM PDT 24
Peak memory 215732 kb
Host smart-2f6f76e3-e50b-4f81-9d67-0efb27edf503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241372006 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.edn_genbits.1241372006
Directory /workspace/62.edn_genbits/latest

Test location /workspace/coverage/default/63.edn_err.2198133031
Short name T41
Test name
Test status
Simulation time 24965495 ps
CPU time 1.27 seconds
Started Mar 12 02:45:35 PM PDT 24
Finished Mar 12 02:45:37 PM PDT 24
Peak memory 229172 kb
Host smart-3ac26033-e8dd-460e-9fdd-97d0c7e4e7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198133031 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_err.2198133031
Directory /workspace/63.edn_err/latest

Test location /workspace/coverage/default/63.edn_genbits.977620709
Short name T257
Test name
Test status
Simulation time 98145747 ps
CPU time 1.3 seconds
Started Mar 12 02:45:39 PM PDT 24
Finished Mar 12 02:45:41 PM PDT 24
Peak memory 216992 kb
Host smart-f4400b36-507e-48d3-8975-6a003f061ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977620709 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.edn_genbits.977620709
Directory /workspace/63.edn_genbits/latest

Test location /workspace/coverage/default/64.edn_err.4093515998
Short name T8
Test name
Test status
Simulation time 51201821 ps
CPU time 1 seconds
Started Mar 12 02:45:35 PM PDT 24
Finished Mar 12 02:45:37 PM PDT 24
Peak memory 218528 kb
Host smart-cb7dc825-8f13-46e3-b4b2-d1d6e6235076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093515998 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_err.4093515998
Directory /workspace/64.edn_err/latest

Test location /workspace/coverage/default/64.edn_genbits.2656255562
Short name T517
Test name
Test status
Simulation time 50966670 ps
CPU time 1.92 seconds
Started Mar 12 02:45:35 PM PDT 24
Finished Mar 12 02:45:38 PM PDT 24
Peak memory 217132 kb
Host smart-defcfb1c-b9ec-4d4d-8434-6b2f36d106e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656255562 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.edn_genbits.2656255562
Directory /workspace/64.edn_genbits/latest

Test location /workspace/coverage/default/65.edn_err.954169890
Short name T168
Test name
Test status
Simulation time 43012395 ps
CPU time 1.11 seconds
Started Mar 12 02:45:32 PM PDT 24
Finished Mar 12 02:45:34 PM PDT 24
Peak memory 218324 kb
Host smart-6c8689c1-02f6-4320-b4f0-eb7cbd5b5c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954169890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_err.954169890
Directory /workspace/65.edn_err/latest

Test location /workspace/coverage/default/65.edn_genbits.3990211638
Short name T146
Test name
Test status
Simulation time 48496920 ps
CPU time 1.06 seconds
Started Mar 12 02:45:35 PM PDT 24
Finished Mar 12 02:45:37 PM PDT 24
Peak memory 215860 kb
Host smart-17d1f416-b5e9-48fa-88a1-ef47bf7a8848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990211638 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.edn_genbits.3990211638
Directory /workspace/65.edn_genbits/latest

Test location /workspace/coverage/default/66.edn_err.1453801107
Short name T102
Test name
Test status
Simulation time 22491797 ps
CPU time 0.97 seconds
Started Mar 12 02:45:40 PM PDT 24
Finished Mar 12 02:45:41 PM PDT 24
Peak memory 217324 kb
Host smart-72d8e6f8-556c-4917-81f8-b66977fe216f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453801107 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_err.1453801107
Directory /workspace/66.edn_err/latest

Test location /workspace/coverage/default/66.edn_genbits.3944538494
Short name T331
Test name
Test status
Simulation time 47091825 ps
CPU time 1.53 seconds
Started Mar 12 02:45:36 PM PDT 24
Finished Mar 12 02:45:38 PM PDT 24
Peak memory 214432 kb
Host smart-7003c056-4072-4e40-80a7-c508b3387f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944538494 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.edn_genbits.3944538494
Directory /workspace/66.edn_genbits/latest

Test location /workspace/coverage/default/67.edn_err.3023989404
Short name T38
Test name
Test status
Simulation time 18625255 ps
CPU time 1.15 seconds
Started Mar 12 02:45:43 PM PDT 24
Finished Mar 12 02:45:45 PM PDT 24
Peak memory 222348 kb
Host smart-1ed3a4c1-408a-4563-9223-3a6f12901eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023989404 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_err.3023989404
Directory /workspace/67.edn_err/latest

Test location /workspace/coverage/default/67.edn_genbits.2994073966
Short name T270
Test name
Test status
Simulation time 68454865 ps
CPU time 1.4 seconds
Started Mar 12 02:45:38 PM PDT 24
Finished Mar 12 02:45:40 PM PDT 24
Peak memory 217228 kb
Host smart-caacb2b3-da1e-477c-b330-6008357f7455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994073966 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.edn_genbits.2994073966
Directory /workspace/67.edn_genbits/latest

Test location /workspace/coverage/default/68.edn_err.3042713097
Short name T96
Test name
Test status
Simulation time 22146533 ps
CPU time 0.91 seconds
Started Mar 12 02:45:42 PM PDT 24
Finished Mar 12 02:45:43 PM PDT 24
Peak memory 217240 kb
Host smart-413ab73b-a294-48f3-86c6-761347ce5715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042713097 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_err.3042713097
Directory /workspace/68.edn_err/latest

Test location /workspace/coverage/default/68.edn_genbits.2544196337
Short name T359
Test name
Test status
Simulation time 98742206 ps
CPU time 1.48 seconds
Started Mar 12 02:45:43 PM PDT 24
Finished Mar 12 02:45:45 PM PDT 24
Peak memory 216128 kb
Host smart-a9ba1064-0736-469e-a2c2-08523cbdb730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544196337 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.edn_genbits.2544196337
Directory /workspace/68.edn_genbits/latest

Test location /workspace/coverage/default/69.edn_err.2485689600
Short name T100
Test name
Test status
Simulation time 23188481 ps
CPU time 0.98 seconds
Started Mar 12 02:45:42 PM PDT 24
Finished Mar 12 02:45:43 PM PDT 24
Peak memory 217212 kb
Host smart-38777e60-ec77-4107-b0d6-2d77190169ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485689600 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_err.2485689600
Directory /workspace/69.edn_err/latest

Test location /workspace/coverage/default/69.edn_genbits.2797246631
Short name T580
Test name
Test status
Simulation time 60137201 ps
CPU time 1.61 seconds
Started Mar 12 02:45:42 PM PDT 24
Finished Mar 12 02:45:44 PM PDT 24
Peak memory 217244 kb
Host smart-465cb7cd-3764-48fe-b070-53ea4d35c7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797246631 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.edn_genbits.2797246631
Directory /workspace/69.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_alert_test.535504834
Short name T324
Test name
Test status
Simulation time 37555287 ps
CPU time 0.86 seconds
Started Mar 12 02:43:28 PM PDT 24
Finished Mar 12 02:43:30 PM PDT 24
Peak memory 205732 kb
Host smart-d822026c-56f5-4b53-a923-9c549e0b976a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535504834 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_alert_test.535504834
Directory /workspace/7.edn_alert_test/latest

Test location /workspace/coverage/default/7.edn_disable.1131213294
Short name T174
Test name
Test status
Simulation time 116129087 ps
CPU time 0.83 seconds
Started Mar 12 02:43:36 PM PDT 24
Finished Mar 12 02:43:37 PM PDT 24
Peak memory 214952 kb
Host smart-c5add43c-0c55-42eb-90c6-2c9a96d51ec7
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131213294 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_disable.1131213294
Directory /workspace/7.edn_disable/latest

Test location /workspace/coverage/default/7.edn_disable_auto_req_mode.214453541
Short name T492
Test name
Test status
Simulation time 100075739 ps
CPU time 1.21 seconds
Started Mar 12 02:43:35 PM PDT 24
Finished Mar 12 02:43:37 PM PDT 24
Peak memory 217972 kb
Host smart-541bd290-298c-4587-973b-280ec36672d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214453541 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_dis
able_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_dis
able_auto_req_mode.214453541
Directory /workspace/7.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/7.edn_err.69078028
Short name T78
Test name
Test status
Simulation time 32943616 ps
CPU time 1.03 seconds
Started Mar 12 02:43:30 PM PDT 24
Finished Mar 12 02:43:31 PM PDT 24
Peak memory 218368 kb
Host smart-b12948e4-a058-470d-bd99-313e1ee5cc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69078028 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_err.69078028
Directory /workspace/7.edn_err/latest

Test location /workspace/coverage/default/7.edn_genbits.3953127466
Short name T758
Test name
Test status
Simulation time 62005716 ps
CPU time 2.48 seconds
Started Mar 12 02:43:29 PM PDT 24
Finished Mar 12 02:43:32 PM PDT 24
Peak memory 218780 kb
Host smart-821f3b28-71c6-4465-9d86-405887df54db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953127466 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_genbits.3953127466
Directory /workspace/7.edn_genbits/latest

Test location /workspace/coverage/default/7.edn_intr.1336097410
Short name T127
Test name
Test status
Simulation time 23640653 ps
CPU time 1.11 seconds
Started Mar 12 02:43:30 PM PDT 24
Finished Mar 12 02:43:31 PM PDT 24
Peak memory 214608 kb
Host smart-eb7415b2-db48-415f-8e37-4e73b1c416f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336097410 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.1336097410
Directory /workspace/7.edn_intr/latest

Test location /workspace/coverage/default/7.edn_regwen.3534962402
Short name T130
Test name
Test status
Simulation time 118148500 ps
CPU time 0.87 seconds
Started Mar 12 02:43:28 PM PDT 24
Finished Mar 12 02:43:29 PM PDT 24
Peak memory 206248 kb
Host smart-67aee3ed-74af-4cb0-890e-e43d13bf55af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534962402 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_regwen.3534962402
Directory /workspace/7.edn_regwen/latest

Test location /workspace/coverage/default/7.edn_smoke.1031242859
Short name T499
Test name
Test status
Simulation time 18710651 ps
CPU time 0.98 seconds
Started Mar 12 02:43:27 PM PDT 24
Finished Mar 12 02:43:29 PM PDT 24
Peak memory 214460 kb
Host smart-1ab42e9c-6b17-4720-a1d2-4ce498252582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031242859 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_smoke.1031242859
Directory /workspace/7.edn_smoke/latest

Test location /workspace/coverage/default/7.edn_stress_all.4077720509
Short name T548
Test name
Test status
Simulation time 345432547 ps
CPU time 6.57 seconds
Started Mar 12 02:43:27 PM PDT 24
Finished Mar 12 02:43:34 PM PDT 24
Peak memory 215368 kb
Host smart-cfec021a-cf3e-495e-b3c6-02860cb75a95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077720509 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_stress_all.4077720509
Directory /workspace/7.edn_stress_all/latest

Test location /workspace/coverage/default/7.edn_stress_all_with_rand_reset.76304963
Short name T388
Test name
Test status
Simulation time 63808514463 ps
CPU time 853 seconds
Started Mar 12 02:43:29 PM PDT 24
Finished Mar 12 02:57:42 PM PDT 24
Peak memory 222744 kb
Host smart-63ebe66d-86e7-4949-a475-284fcf4838ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76304963 -assert nopostproc
+UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 7.edn_stress_all_with_rand_reset.76304963
Directory /workspace/7.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.edn_err.366561123
Short name T532
Test name
Test status
Simulation time 25352344 ps
CPU time 1.17 seconds
Started Mar 12 02:45:43 PM PDT 24
Finished Mar 12 02:45:44 PM PDT 24
Peak memory 221720 kb
Host smart-3282193b-50f5-4ec3-8600-0f60488328b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366561123 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_err.366561123
Directory /workspace/70.edn_err/latest

Test location /workspace/coverage/default/70.edn_genbits.2625328242
Short name T271
Test name
Test status
Simulation time 37636180 ps
CPU time 1.62 seconds
Started Mar 12 02:45:40 PM PDT 24
Finished Mar 12 02:45:42 PM PDT 24
Peak memory 217016 kb
Host smart-0e7fff23-71c0-4f3c-9305-c64628602e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625328242 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.edn_genbits.2625328242
Directory /workspace/70.edn_genbits/latest

Test location /workspace/coverage/default/71.edn_err.1979772622
Short name T411
Test name
Test status
Simulation time 36510483 ps
CPU time 0.91 seconds
Started Mar 12 02:45:41 PM PDT 24
Finished Mar 12 02:45:42 PM PDT 24
Peak memory 217092 kb
Host smart-5ee34db8-324c-4c6f-ba1a-234e06b68c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979772622 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_err.1979772622
Directory /workspace/71.edn_err/latest

Test location /workspace/coverage/default/71.edn_genbits.2755429238
Short name T425
Test name
Test status
Simulation time 61996304 ps
CPU time 1.26 seconds
Started Mar 12 02:45:53 PM PDT 24
Finished Mar 12 02:45:55 PM PDT 24
Peak memory 216916 kb
Host smart-5da5ebdd-f743-4ea8-85a2-28c9de6cd0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755429238 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.edn_genbits.2755429238
Directory /workspace/71.edn_genbits/latest

Test location /workspace/coverage/default/72.edn_err.2175259533
Short name T682
Test name
Test status
Simulation time 93981599 ps
CPU time 1.09 seconds
Started Mar 12 02:45:42 PM PDT 24
Finished Mar 12 02:45:43 PM PDT 24
Peak memory 230684 kb
Host smart-71c04e02-9f83-4c63-8eeb-9c9da811441a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175259533 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_err.2175259533
Directory /workspace/72.edn_err/latest

Test location /workspace/coverage/default/72.edn_genbits.3996337755
Short name T437
Test name
Test status
Simulation time 47452751 ps
CPU time 1.31 seconds
Started Mar 12 02:45:45 PM PDT 24
Finished Mar 12 02:45:47 PM PDT 24
Peak memory 218240 kb
Host smart-5e667cc8-966e-4787-97e0-afa725c8674f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996337755 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.edn_genbits.3996337755
Directory /workspace/72.edn_genbits/latest

Test location /workspace/coverage/default/73.edn_err.176042155
Short name T370
Test name
Test status
Simulation time 25352460 ps
CPU time 1 seconds
Started Mar 12 02:45:43 PM PDT 24
Finished Mar 12 02:45:44 PM PDT 24
Peak memory 221728 kb
Host smart-906c9c9c-8764-402a-9c3c-c8645a2c3952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176042155 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_err.176042155
Directory /workspace/73.edn_err/latest

Test location /workspace/coverage/default/73.edn_genbits.309540622
Short name T415
Test name
Test status
Simulation time 105982411 ps
CPU time 1.51 seconds
Started Mar 12 02:45:40 PM PDT 24
Finished Mar 12 02:45:42 PM PDT 24
Peak memory 217252 kb
Host smart-ca842fc5-fa06-46cd-97ed-191197d5e4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309540622 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.edn_genbits.309540622
Directory /workspace/73.edn_genbits/latest

Test location /workspace/coverage/default/74.edn_err.2787040752
Short name T84
Test name
Test status
Simulation time 149874490 ps
CPU time 1.02 seconds
Started Mar 12 02:45:40 PM PDT 24
Finished Mar 12 02:45:41 PM PDT 24
Peak memory 219060 kb
Host smart-2ec69ed1-f8a6-4ce5-bc59-d92f9ea7d78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787040752 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_err.2787040752
Directory /workspace/74.edn_err/latest

Test location /workspace/coverage/default/74.edn_genbits.138247434
Short name T535
Test name
Test status
Simulation time 160590506 ps
CPU time 2.11 seconds
Started Mar 12 02:45:41 PM PDT 24
Finished Mar 12 02:45:43 PM PDT 24
Peak memory 218148 kb
Host smart-1ada9967-0ff9-4c20-b1d2-769b795d52c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138247434 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.edn_genbits.138247434
Directory /workspace/74.edn_genbits/latest

Test location /workspace/coverage/default/75.edn_err.45089890
Short name T161
Test name
Test status
Simulation time 24511321 ps
CPU time 1.07 seconds
Started Mar 12 02:45:39 PM PDT 24
Finished Mar 12 02:45:41 PM PDT 24
Peak memory 230700 kb
Host smart-4092c56d-f466-4185-838f-2bcd84ab4326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45089890 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_err.45089890
Directory /workspace/75.edn_err/latest

Test location /workspace/coverage/default/75.edn_genbits.3824151066
Short name T298
Test name
Test status
Simulation time 40597182 ps
CPU time 1.15 seconds
Started Mar 12 02:45:42 PM PDT 24
Finished Mar 12 02:45:43 PM PDT 24
Peak memory 216892 kb
Host smart-649d0d44-996f-49fb-a36f-4b6f208728fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824151066 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.edn_genbits.3824151066
Directory /workspace/75.edn_genbits/latest

Test location /workspace/coverage/default/76.edn_err.3704162629
Short name T170
Test name
Test status
Simulation time 21285214 ps
CPU time 1.24 seconds
Started Mar 12 02:45:50 PM PDT 24
Finished Mar 12 02:45:51 PM PDT 24
Peak memory 231884 kb
Host smart-adc18cfc-2c1d-4320-a9be-fc0cba9cc5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704162629 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_err.3704162629
Directory /workspace/76.edn_err/latest

Test location /workspace/coverage/default/76.edn_genbits.4119860786
Short name T183
Test name
Test status
Simulation time 41936176 ps
CPU time 1.54 seconds
Started Mar 12 02:45:49 PM PDT 24
Finished Mar 12 02:45:51 PM PDT 24
Peak memory 216812 kb
Host smart-862e5c17-6714-4bb5-aefb-3e3d7bfcd44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119860786 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.edn_genbits.4119860786
Directory /workspace/76.edn_genbits/latest

Test location /workspace/coverage/default/77.edn_err.2696713259
Short name T93
Test name
Test status
Simulation time 26805374 ps
CPU time 1.01 seconds
Started Mar 12 02:45:50 PM PDT 24
Finished Mar 12 02:45:52 PM PDT 24
Peak memory 218504 kb
Host smart-f1e04c60-8244-4cc0-b098-ea1e8de8aed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696713259 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_err.2696713259
Directory /workspace/77.edn_err/latest

Test location /workspace/coverage/default/77.edn_genbits.3267967589
Short name T798
Test name
Test status
Simulation time 124933442 ps
CPU time 1.47 seconds
Started Mar 12 02:45:52 PM PDT 24
Finished Mar 12 02:45:53 PM PDT 24
Peak memory 217084 kb
Host smart-4726885a-c287-4e6b-8e1d-aa2b46b4386c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267967589 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.edn_genbits.3267967589
Directory /workspace/77.edn_genbits/latest

Test location /workspace/coverage/default/78.edn_err.2381206883
Short name T794
Test name
Test status
Simulation time 18849403 ps
CPU time 1.03 seconds
Started Mar 12 02:45:52 PM PDT 24
Finished Mar 12 02:45:53 PM PDT 24
Peak memory 217216 kb
Host smart-ced02983-4878-43a2-95c7-c59ab2a0c7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381206883 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_err.2381206883
Directory /workspace/78.edn_err/latest

Test location /workspace/coverage/default/78.edn_genbits.607675894
Short name T184
Test name
Test status
Simulation time 45882966 ps
CPU time 1.16 seconds
Started Mar 12 02:45:50 PM PDT 24
Finished Mar 12 02:45:52 PM PDT 24
Peak memory 215848 kb
Host smart-cd8f465e-c8ef-4980-89c6-f214dbb975f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607675894 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.edn_genbits.607675894
Directory /workspace/78.edn_genbits/latest

Test location /workspace/coverage/default/79.edn_err.1805419701
Short name T760
Test name
Test status
Simulation time 20995520 ps
CPU time 0.91 seconds
Started Mar 12 02:45:49 PM PDT 24
Finished Mar 12 02:45:50 PM PDT 24
Peak memory 216980 kb
Host smart-c3f85037-e1e3-4c69-b5ad-4477e507a8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805419701 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_err.1805419701
Directory /workspace/79.edn_err/latest

Test location /workspace/coverage/default/79.edn_genbits.2599774691
Short name T675
Test name
Test status
Simulation time 81230007 ps
CPU time 1.14 seconds
Started Mar 12 02:45:52 PM PDT 24
Finished Mar 12 02:45:54 PM PDT 24
Peak memory 217208 kb
Host smart-a3043c30-2c22-4388-bb3f-4dd634a01235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599774691 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.edn_genbits.2599774691
Directory /workspace/79.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_alert.2165709091
Short name T151
Test name
Test status
Simulation time 74346234 ps
CPU time 1.21 seconds
Started Mar 12 02:43:36 PM PDT 24
Finished Mar 12 02:43:37 PM PDT 24
Peak memory 214808 kb
Host smart-8aa173f6-4781-4451-b75b-b6b7a92521de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165709091 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert.2165709091
Directory /workspace/8.edn_alert/latest

Test location /workspace/coverage/default/8.edn_alert_test.422828215
Short name T352
Test name
Test status
Simulation time 25244360 ps
CPU time 1.1 seconds
Started Mar 12 02:43:36 PM PDT 24
Finished Mar 12 02:43:37 PM PDT 24
Peak memory 205424 kb
Host smart-2730a7cb-ff28-4668-9ad3-72e3a3cb5685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422828215 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_alert_test.422828215
Directory /workspace/8.edn_alert_test/latest

Test location /workspace/coverage/default/8.edn_disable.1573347300
Short name T182
Test name
Test status
Simulation time 18409180 ps
CPU time 0.84 seconds
Started Mar 12 02:43:39 PM PDT 24
Finished Mar 12 02:43:40 PM PDT 24
Peak memory 214620 kb
Host smart-714113d0-9d02-436e-aa79-b94a0e7834ab
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573347300 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_disable.1573347300
Directory /workspace/8.edn_disable/latest

Test location /workspace/coverage/default/8.edn_disable_auto_req_mode.1563902905
Short name T727
Test name
Test status
Simulation time 35159174 ps
CPU time 1.2 seconds
Started Mar 12 02:43:36 PM PDT 24
Finished Mar 12 02:43:37 PM PDT 24
Peak memory 216700 kb
Host smart-5e79fea1-d0b6-4e31-9751-1593a1fd7df6
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563902905 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_di
sable_auto_req_mode.1563902905
Directory /workspace/8.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/8.edn_err.3798334971
Short name T9
Test name
Test status
Simulation time 34914202 ps
CPU time 0.93 seconds
Started Mar 12 02:43:35 PM PDT 24
Finished Mar 12 02:43:37 PM PDT 24
Peak memory 217300 kb
Host smart-e7083c22-e197-4d94-a573-5495e50b7dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798334971 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_err.3798334971
Directory /workspace/8.edn_err/latest

Test location /workspace/coverage/default/8.edn_genbits.2302557080
Short name T263
Test name
Test status
Simulation time 25532410 ps
CPU time 1.23 seconds
Started Mar 12 02:43:36 PM PDT 24
Finished Mar 12 02:43:37 PM PDT 24
Peak memory 216040 kb
Host smart-da952dbd-bdf0-414a-8861-c3d0a558bf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302557080 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_genbits.2302557080
Directory /workspace/8.edn_genbits/latest

Test location /workspace/coverage/default/8.edn_intr.2628131286
Short name T503
Test name
Test status
Simulation time 41104807 ps
CPU time 0.99 seconds
Started Mar 12 02:43:37 PM PDT 24
Finished Mar 12 02:43:39 PM PDT 24
Peak memory 222576 kb
Host smart-d146f439-89a4-494c-97d3-c5e3c95a0e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628131286 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_intr.2628131286
Directory /workspace/8.edn_intr/latest

Test location /workspace/coverage/default/8.edn_regwen.824857615
Short name T646
Test name
Test status
Simulation time 22260254 ps
CPU time 1 seconds
Started Mar 12 02:43:29 PM PDT 24
Finished Mar 12 02:43:30 PM PDT 24
Peak memory 206248 kb
Host smart-3df1aca3-8cf9-431c-813b-7d4326f4d12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824857615 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_regwen.824857615
Directory /workspace/8.edn_regwen/latest

Test location /workspace/coverage/default/8.edn_smoke.1748216663
Short name T144
Test name
Test status
Simulation time 44159095 ps
CPU time 0.87 seconds
Started Mar 12 02:43:29 PM PDT 24
Finished Mar 12 02:43:30 PM PDT 24
Peak memory 214516 kb
Host smart-3d7e5ed8-9049-4f2b-a3ec-55627cb69c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748216663 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_smoke.1748216663
Directory /workspace/8.edn_smoke/latest

Test location /workspace/coverage/default/8.edn_stress_all.1633454483
Short name T201
Test name
Test status
Simulation time 441009068 ps
CPU time 4.33 seconds
Started Mar 12 02:43:35 PM PDT 24
Finished Mar 12 02:43:40 PM PDT 24
Peak memory 215656 kb
Host smart-c2bc13f7-99ea-4d9e-af7d-6d10bc5d8ab9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633454483 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.edn_stress_all.1633454483
Directory /workspace/8.edn_stress_all/latest

Test location /workspace/coverage/default/8.edn_stress_all_with_rand_reset.931659747
Short name T474
Test name
Test status
Simulation time 109725261474 ps
CPU time 596.58 seconds
Started Mar 12 02:43:40 PM PDT 24
Finished Mar 12 02:53:37 PM PDT 24
Peak memory 222812 kb
Host smart-da3df0a0-9ec1-4b70-bff1-da2cff250d13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931659747 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.edn_stress_all_with_rand_reset.931659747
Directory /workspace/8.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.edn_err.716067145
Short name T56
Test name
Test status
Simulation time 18718813 ps
CPU time 1.15 seconds
Started Mar 12 02:45:54 PM PDT 24
Finished Mar 12 02:45:55 PM PDT 24
Peak memory 222376 kb
Host smart-d87c4de1-27af-4a6d-b09b-19d85a574624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716067145 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_err.716067145
Directory /workspace/80.edn_err/latest

Test location /workspace/coverage/default/80.edn_genbits.3101933906
Short name T531
Test name
Test status
Simulation time 25144901 ps
CPU time 1.29 seconds
Started Mar 12 02:45:48 PM PDT 24
Finished Mar 12 02:45:50 PM PDT 24
Peak memory 215872 kb
Host smart-70de15c0-c113-4870-9df6-8b430a46ed92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101933906 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.edn_genbits.3101933906
Directory /workspace/80.edn_genbits/latest

Test location /workspace/coverage/default/81.edn_err.3150779778
Short name T371
Test name
Test status
Simulation time 19817911 ps
CPU time 1.09 seconds
Started Mar 12 02:45:51 PM PDT 24
Finished Mar 12 02:45:53 PM PDT 24
Peak memory 222480 kb
Host smart-b8e3dd85-510d-488f-9ab0-956d198b7c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150779778 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_err.3150779778
Directory /workspace/81.edn_err/latest

Test location /workspace/coverage/default/81.edn_genbits.328986078
Short name T679
Test name
Test status
Simulation time 54750742 ps
CPU time 1.83 seconds
Started Mar 12 02:45:51 PM PDT 24
Finished Mar 12 02:45:53 PM PDT 24
Peak memory 216956 kb
Host smart-5b98bf04-9a50-4875-921e-e2b5e9942712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328986078 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.edn_genbits.328986078
Directory /workspace/81.edn_genbits/latest

Test location /workspace/coverage/default/82.edn_err.1758866403
Short name T470
Test name
Test status
Simulation time 18676153 ps
CPU time 1.03 seconds
Started Mar 12 02:45:46 PM PDT 24
Finished Mar 12 02:45:47 PM PDT 24
Peak memory 217088 kb
Host smart-99af12d6-4a6e-4a40-b73c-61bedbe74420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758866403 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_err.1758866403
Directory /workspace/82.edn_err/latest

Test location /workspace/coverage/default/82.edn_genbits.1551744942
Short name T457
Test name
Test status
Simulation time 92305387 ps
CPU time 1.17 seconds
Started Mar 12 02:45:53 PM PDT 24
Finished Mar 12 02:45:54 PM PDT 24
Peak memory 215704 kb
Host smart-9eb40691-d776-4b77-999f-e6b4a5b77cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551744942 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.edn_genbits.1551744942
Directory /workspace/82.edn_genbits/latest

Test location /workspace/coverage/default/83.edn_err.2999588299
Short name T752
Test name
Test status
Simulation time 56575065 ps
CPU time 1.05 seconds
Started Mar 12 02:45:52 PM PDT 24
Finished Mar 12 02:45:53 PM PDT 24
Peak memory 215992 kb
Host smart-90ba5f33-063b-44fc-bc16-6f541f9a99a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999588299 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_err.2999588299
Directory /workspace/83.edn_err/latest

Test location /workspace/coverage/default/83.edn_genbits.2479341109
Short name T468
Test name
Test status
Simulation time 42223185 ps
CPU time 1.71 seconds
Started Mar 12 02:45:49 PM PDT 24
Finished Mar 12 02:45:51 PM PDT 24
Peak memory 216892 kb
Host smart-8f0ba6bc-4962-4717-bd52-db8d4035a194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479341109 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.edn_genbits.2479341109
Directory /workspace/83.edn_genbits/latest

Test location /workspace/coverage/default/84.edn_err.1578177768
Short name T65
Test name
Test status
Simulation time 25760172 ps
CPU time 0.84 seconds
Started Mar 12 02:45:52 PM PDT 24
Finished Mar 12 02:45:53 PM PDT 24
Peak memory 216988 kb
Host smart-e1dc50df-83d6-4cb9-999d-b23cd46428f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578177768 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_err.1578177768
Directory /workspace/84.edn_err/latest

Test location /workspace/coverage/default/84.edn_genbits.1772274162
Short name T460
Test name
Test status
Simulation time 128764090 ps
CPU time 1.72 seconds
Started Mar 12 02:45:49 PM PDT 24
Finished Mar 12 02:45:51 PM PDT 24
Peak memory 217652 kb
Host smart-de15b1da-59cf-4156-9d2c-5849829ffb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772274162 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.edn_genbits.1772274162
Directory /workspace/84.edn_genbits/latest

Test location /workspace/coverage/default/85.edn_err.806704286
Short name T89
Test name
Test status
Simulation time 20589097 ps
CPU time 1.11 seconds
Started Mar 12 02:45:49 PM PDT 24
Finished Mar 12 02:45:51 PM PDT 24
Peak memory 218476 kb
Host smart-27a8c4eb-4467-4318-b042-abab6cff3f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806704286 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_err.806704286
Directory /workspace/85.edn_err/latest

Test location /workspace/coverage/default/85.edn_genbits.3349526256
Short name T261
Test name
Test status
Simulation time 40817731 ps
CPU time 1.45 seconds
Started Mar 12 02:45:51 PM PDT 24
Finished Mar 12 02:45:53 PM PDT 24
Peak memory 215516 kb
Host smart-312dad01-2c88-4e9e-b860-bbf0cfae82ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349526256 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.edn_genbits.3349526256
Directory /workspace/85.edn_genbits/latest

Test location /workspace/coverage/default/86.edn_err.241721030
Short name T7
Test name
Test status
Simulation time 57419762 ps
CPU time 1.07 seconds
Started Mar 12 02:45:52 PM PDT 24
Finished Mar 12 02:45:54 PM PDT 24
Peak memory 229040 kb
Host smart-e80829f0-be6a-483d-8370-4529ab7f5e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241721030 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_err.241721030
Directory /workspace/86.edn_err/latest

Test location /workspace/coverage/default/86.edn_genbits.3966580290
Short name T419
Test name
Test status
Simulation time 49806598 ps
CPU time 1.22 seconds
Started Mar 12 02:45:54 PM PDT 24
Finished Mar 12 02:45:55 PM PDT 24
Peak memory 215796 kb
Host smart-3c864712-6d86-486b-a67c-75384f07e798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966580290 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.edn_genbits.3966580290
Directory /workspace/86.edn_genbits/latest

Test location /workspace/coverage/default/87.edn_err.353003751
Short name T80
Test name
Test status
Simulation time 26532350 ps
CPU time 1.03 seconds
Started Mar 12 02:45:50 PM PDT 24
Finished Mar 12 02:45:51 PM PDT 24
Peak memory 218424 kb
Host smart-754939b0-211d-44cc-a31d-5741b6c8afa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353003751 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_err.353003751
Directory /workspace/87.edn_err/latest

Test location /workspace/coverage/default/87.edn_genbits.792221275
Short name T720
Test name
Test status
Simulation time 45662432 ps
CPU time 1.47 seconds
Started Mar 12 02:45:48 PM PDT 24
Finished Mar 12 02:45:50 PM PDT 24
Peak memory 216756 kb
Host smart-1f9c6010-de12-4c89-a75d-d790987486b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792221275 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.edn_genbits.792221275
Directory /workspace/87.edn_genbits/latest

Test location /workspace/coverage/default/88.edn_err.2583791738
Short name T67
Test name
Test status
Simulation time 20535531 ps
CPU time 1.08 seconds
Started Mar 12 02:45:50 PM PDT 24
Finished Mar 12 02:45:51 PM PDT 24
Peak memory 217372 kb
Host smart-86bce2e0-3524-484a-82f2-c11270250669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583791738 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_err.2583791738
Directory /workspace/88.edn_err/latest

Test location /workspace/coverage/default/88.edn_genbits.3216442237
Short name T29
Test name
Test status
Simulation time 37307960 ps
CPU time 1.55 seconds
Started Mar 12 02:45:53 PM PDT 24
Finished Mar 12 02:45:54 PM PDT 24
Peak memory 216916 kb
Host smart-51569683-b098-4cd2-8869-151d7cef44fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216442237 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.edn_genbits.3216442237
Directory /workspace/88.edn_genbits/latest

Test location /workspace/coverage/default/89.edn_err.2141582621
Short name T745
Test name
Test status
Simulation time 25859110 ps
CPU time 0.86 seconds
Started Mar 12 02:45:49 PM PDT 24
Finished Mar 12 02:45:50 PM PDT 24
Peak memory 216876 kb
Host smart-31036d61-0173-468a-93f2-55bf63d7e548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141582621 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.edn_err.2141582621
Directory /workspace/89.edn_err/latest

Test location /workspace/coverage/default/9.edn_alert.3945230988
Short name T19
Test name
Test status
Simulation time 27044326 ps
CPU time 1.18 seconds
Started Mar 12 02:43:40 PM PDT 24
Finished Mar 12 02:43:42 PM PDT 24
Peak memory 214852 kb
Host smart-f3cc727b-75a6-4d89-b1c4-34067fe8fcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945230988 -assert nopostproc +UVM_TESTNAME=edn_alert_test +UVM_TEST_SEQ=edn_alert_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert.3945230988
Directory /workspace/9.edn_alert/latest

Test location /workspace/coverage/default/9.edn_alert_test.49903001
Short name T345
Test name
Test status
Simulation time 25866912 ps
CPU time 0.87 seconds
Started Mar 12 02:43:40 PM PDT 24
Finished Mar 12 02:43:41 PM PDT 24
Peak memory 205228 kb
Host smart-580b792c-f4bc-4225-848d-b58acbc8912e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49903001 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_alert_test.49903001
Directory /workspace/9.edn_alert_test/latest

Test location /workspace/coverage/default/9.edn_disable.1529092261
Short name T751
Test name
Test status
Simulation time 128754419 ps
CPU time 0.84 seconds
Started Mar 12 02:43:37 PM PDT 24
Finished Mar 12 02:43:39 PM PDT 24
Peak memory 215040 kb
Host smart-520293c4-3da8-4ca7-8eb9-a7b891e6b342
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529092261 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_disable.1529092261
Directory /workspace/9.edn_disable/latest

Test location /workspace/coverage/default/9.edn_disable_auto_req_mode.3392973428
Short name T85
Test name
Test status
Simulation time 38999246 ps
CPU time 1.25 seconds
Started Mar 12 02:43:38 PM PDT 24
Finished Mar 12 02:43:40 PM PDT 24
Peak memory 216836 kb
Host smart-3aec538d-58fa-4d67-bbf6-28c33ff8534e
User root
Command /workspace/default/simv +test_timeout_ns=500_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392973428 -assert nopostproc +UVM_TESTNAME=edn_disable_auto_req_mode_test +UVM_TEST_SEQ=edn_di
sable_auto_req_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_di
sable_auto_req_mode.3392973428
Directory /workspace/9.edn_disable_auto_req_mode/latest

Test location /workspace/coverage/default/9.edn_err.3169809004
Short name T163
Test name
Test status
Simulation time 52828630 ps
CPU time 1.02 seconds
Started Mar 12 02:43:39 PM PDT 24
Finished Mar 12 02:43:40 PM PDT 24
Peak memory 218720 kb
Host smart-e1e3c21b-4673-43a8-afda-054b90200954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169809004 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_err.3169809004
Directory /workspace/9.edn_err/latest

Test location /workspace/coverage/default/9.edn_genbits.3401548977
Short name T294
Test name
Test status
Simulation time 29489630 ps
CPU time 1.22 seconds
Started Mar 12 02:43:36 PM PDT 24
Finished Mar 12 02:43:37 PM PDT 24
Peak memory 215796 kb
Host smart-ec012f07-c5db-4bf0-8678-51232b86207b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401548977 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_genbits.3401548977
Directory /workspace/9.edn_genbits/latest

Test location /workspace/coverage/default/9.edn_intr.4150122912
Short name T804
Test name
Test status
Simulation time 20925950 ps
CPU time 1.19 seconds
Started Mar 12 02:43:37 PM PDT 24
Finished Mar 12 02:43:38 PM PDT 24
Peak memory 222324 kb
Host smart-2b363120-494d-4e85-97e8-e5c1672f9eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150122912 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_intr.4150122912
Directory /workspace/9.edn_intr/latest

Test location /workspace/coverage/default/9.edn_regwen.1167999841
Short name T247
Test name
Test status
Simulation time 22188602 ps
CPU time 0.88 seconds
Started Mar 12 02:43:37 PM PDT 24
Finished Mar 12 02:43:38 PM PDT 24
Peak memory 206208 kb
Host smart-4c7d219b-dc1e-4831-b264-1541bcee29ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167999841 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_regwen.1167999841
Directory /workspace/9.edn_regwen/latest

Test location /workspace/coverage/default/9.edn_smoke.1966250699
Short name T449
Test name
Test status
Simulation time 16115505 ps
CPU time 0.98 seconds
Started Mar 12 02:43:34 PM PDT 24
Finished Mar 12 02:43:36 PM PDT 24
Peak memory 214396 kb
Host smart-53218058-4a6f-4323-83d3-12a7bf274a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966250699 -assert nopostproc +UVM_TESTNAME=edn_smoke_test +UVM_TEST_SEQ=edn_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_smoke.1966250699
Directory /workspace/9.edn_smoke/latest

Test location /workspace/coverage/default/9.edn_stress_all.3410376825
Short name T614
Test name
Test status
Simulation time 1862600225 ps
CPU time 3.57 seconds
Started Mar 12 02:43:37 PM PDT 24
Finished Mar 12 02:43:41 PM PDT 24
Peak memory 215688 kb
Host smart-4fc35c33-542a-47d4-97e5-315c0139e49c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410376825 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.edn_stress_all.3410376825
Directory /workspace/9.edn_stress_all/latest

Test location /workspace/coverage/default/9.edn_stress_all_with_rand_reset.293168485
Short name T792
Test name
Test status
Simulation time 55957092529 ps
CPU time 675.5 seconds
Started Mar 12 02:43:36 PM PDT 24
Finished Mar 12 02:54:51 PM PDT 24
Peak memory 216328 kb
Host smart-d2e4118d-d88d-4d27-a2d0-f5725314f36b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=edn_stress_all_vseq +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293168485 -assert nopostpro
c +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.edn_stress_all_with_rand_reset.293168485
Directory /workspace/9.edn_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.edn_err.543178796
Short name T114
Test name
Test status
Simulation time 21180240 ps
CPU time 0.94 seconds
Started Mar 12 02:45:52 PM PDT 24
Finished Mar 12 02:45:54 PM PDT 24
Peak memory 216960 kb
Host smart-15494e73-046c-4d0f-856b-139cac52cea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543178796 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_err.543178796
Directory /workspace/90.edn_err/latest

Test location /workspace/coverage/default/90.edn_genbits.3757309526
Short name T742
Test name
Test status
Simulation time 30399726 ps
CPU time 1.29 seconds
Started Mar 12 02:45:53 PM PDT 24
Finished Mar 12 02:45:55 PM PDT 24
Peak memory 215516 kb
Host smart-9dcf2817-9b97-4d15-a62f-26ec8b75a13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757309526 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.edn_genbits.3757309526
Directory /workspace/90.edn_genbits/latest

Test location /workspace/coverage/default/91.edn_err.3592408299
Short name T83
Test name
Test status
Simulation time 55165763 ps
CPU time 1.11 seconds
Started Mar 12 02:45:50 PM PDT 24
Finished Mar 12 02:45:51 PM PDT 24
Peak memory 229104 kb
Host smart-9c2b8d5e-f5a6-4ebc-9ee5-1e7450e57278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592408299 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_err.3592408299
Directory /workspace/91.edn_err/latest

Test location /workspace/coverage/default/91.edn_genbits.1292123828
Short name T703
Test name
Test status
Simulation time 56410556 ps
CPU time 1.28 seconds
Started Mar 12 02:45:50 PM PDT 24
Finished Mar 12 02:45:52 PM PDT 24
Peak memory 215724 kb
Host smart-41b9899a-be4b-4b37-8d0d-e63468ac2830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292123828 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.edn_genbits.1292123828
Directory /workspace/91.edn_genbits/latest

Test location /workspace/coverage/default/92.edn_err.3269038875
Short name T94
Test name
Test status
Simulation time 139333099 ps
CPU time 1.04 seconds
Started Mar 12 02:45:50 PM PDT 24
Finished Mar 12 02:45:52 PM PDT 24
Peak memory 228984 kb
Host smart-26bf4b8b-5265-4de7-9734-0c51659da84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269038875 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_err.3269038875
Directory /workspace/92.edn_err/latest

Test location /workspace/coverage/default/92.edn_genbits.709265831
Short name T61
Test name
Test status
Simulation time 38859359 ps
CPU time 1.59 seconds
Started Mar 12 02:45:50 PM PDT 24
Finished Mar 12 02:45:52 PM PDT 24
Peak memory 216980 kb
Host smart-f9603137-315b-4792-9f98-31af4f2bc011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709265831 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.edn_genbits.709265831
Directory /workspace/92.edn_genbits/latest

Test location /workspace/coverage/default/93.edn_err.2312249760
Short name T715
Test name
Test status
Simulation time 17769477 ps
CPU time 1.01 seconds
Started Mar 12 02:45:59 PM PDT 24
Finished Mar 12 02:46:00 PM PDT 24
Peak memory 217032 kb
Host smart-535135b2-584f-42c7-8399-8f223b8fe628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312249760 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_err.2312249760
Directory /workspace/93.edn_err/latest

Test location /workspace/coverage/default/93.edn_genbits.4016192264
Short name T605
Test name
Test status
Simulation time 179287031 ps
CPU time 1.12 seconds
Started Mar 12 02:46:00 PM PDT 24
Finished Mar 12 02:46:01 PM PDT 24
Peak memory 215636 kb
Host smart-0a5a90f8-63dc-4439-901a-97ab68ffbeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016192264 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.edn_genbits.4016192264
Directory /workspace/93.edn_genbits/latest

Test location /workspace/coverage/default/94.edn_err.2952237174
Short name T39
Test name
Test status
Simulation time 32648056 ps
CPU time 1.04 seconds
Started Mar 12 02:45:59 PM PDT 24
Finished Mar 12 02:46:01 PM PDT 24
Peak memory 222312 kb
Host smart-fecc3c97-4359-42f4-b18d-c66c9939d931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952237174 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_err.2952237174
Directory /workspace/94.edn_err/latest

Test location /workspace/coverage/default/94.edn_genbits.1106924098
Short name T454
Test name
Test status
Simulation time 35228870 ps
CPU time 1.4 seconds
Started Mar 12 02:45:59 PM PDT 24
Finished Mar 12 02:46:01 PM PDT 24
Peak memory 218204 kb
Host smart-80d829c9-9a84-45db-b567-dac3c5f52eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106924098 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.edn_genbits.1106924098
Directory /workspace/94.edn_genbits/latest

Test location /workspace/coverage/default/95.edn_err.3811582553
Short name T389
Test name
Test status
Simulation time 26478663 ps
CPU time 0.9 seconds
Started Mar 12 02:45:56 PM PDT 24
Finished Mar 12 02:45:57 PM PDT 24
Peak memory 217228 kb
Host smart-9efce5a7-9a58-4410-af7f-880d7c513c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811582553 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_err.3811582553
Directory /workspace/95.edn_err/latest

Test location /workspace/coverage/default/95.edn_genbits.2375810985
Short name T57
Test name
Test status
Simulation time 20279461 ps
CPU time 1.05 seconds
Started Mar 12 02:45:59 PM PDT 24
Finished Mar 12 02:46:00 PM PDT 24
Peak memory 215792 kb
Host smart-a67a79f3-de79-4cef-b254-ce46eb05a710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375810985 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.edn_genbits.2375810985
Directory /workspace/95.edn_genbits/latest

Test location /workspace/coverage/default/96.edn_err.2485268484
Short name T834
Test name
Test status
Simulation time 25014699 ps
CPU time 0.96 seconds
Started Mar 12 02:45:57 PM PDT 24
Finished Mar 12 02:45:58 PM PDT 24
Peak memory 215980 kb
Host smart-f1d769f9-14fe-4901-9349-161461dc317e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485268484 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_err.2485268484
Directory /workspace/96.edn_err/latest

Test location /workspace/coverage/default/96.edn_genbits.3059080937
Short name T290
Test name
Test status
Simulation time 244882132 ps
CPU time 2.16 seconds
Started Mar 12 02:45:58 PM PDT 24
Finished Mar 12 02:46:00 PM PDT 24
Peak memory 218492 kb
Host smart-0568f120-5c04-427b-b0f1-e137a50b4e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059080937 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.edn_genbits.3059080937
Directory /workspace/96.edn_genbits/latest

Test location /workspace/coverage/default/97.edn_err.3935637992
Short name T23
Test name
Test status
Simulation time 21872024 ps
CPU time 0.92 seconds
Started Mar 12 02:45:59 PM PDT 24
Finished Mar 12 02:46:00 PM PDT 24
Peak memory 217308 kb
Host smart-828728a5-9374-4483-abb1-45823d37d4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935637992 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_err.3935637992
Directory /workspace/97.edn_err/latest

Test location /workspace/coverage/default/97.edn_genbits.2133742329
Short name T537
Test name
Test status
Simulation time 38304592 ps
CPU time 1.37 seconds
Started Mar 12 02:45:58 PM PDT 24
Finished Mar 12 02:45:59 PM PDT 24
Peak memory 216904 kb
Host smart-4889abef-b690-4a00-944b-c12746f3fb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133742329 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.edn_genbits.2133742329
Directory /workspace/97.edn_genbits/latest

Test location /workspace/coverage/default/98.edn_err.585278367
Short name T71
Test name
Test status
Simulation time 26693376 ps
CPU time 1.04 seconds
Started Mar 12 02:45:59 PM PDT 24
Finished Mar 12 02:46:00 PM PDT 24
Peak memory 228960 kb
Host smart-e9332389-eaa9-46db-8344-08003dc59b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585278367 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_err.585278367
Directory /workspace/98.edn_err/latest

Test location /workspace/coverage/default/98.edn_genbits.583450035
Short name T297
Test name
Test status
Simulation time 57042483 ps
CPU time 1.56 seconds
Started Mar 12 02:46:00 PM PDT 24
Finished Mar 12 02:46:01 PM PDT 24
Peak memory 215820 kb
Host smart-2bc9a15c-8e36-4757-b392-c24dbe62e930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583450035 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.edn_genbits.583450035
Directory /workspace/98.edn_genbits/latest

Test location /workspace/coverage/default/99.edn_err.648376876
Short name T699
Test name
Test status
Simulation time 25254374 ps
CPU time 0.9 seconds
Started Mar 12 02:45:58 PM PDT 24
Finished Mar 12 02:45:59 PM PDT 24
Peak memory 217388 kb
Host smart-5da49f05-ea69-4efb-a2c5-173959187fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648376876 -assert nopostproc +UVM_TESTNAME=edn_err_test +UVM_TEST_SEQ=edn_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_err.648376876
Directory /workspace/99.edn_err/latest

Test location /workspace/coverage/default/99.edn_genbits.4167082048
Short name T490
Test name
Test status
Simulation time 230404187 ps
CPU time 1.68 seconds
Started Mar 12 02:45:59 PM PDT 24
Finished Mar 12 02:46:01 PM PDT 24
Peak memory 217148 kb
Host smart-a6262f76-db7a-46c5-a455-6e6be2df2adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167082048 -assert nopostproc +UVM_TESTNAME=edn_genbits_test +UVM_TEST_SEQ=edn_genbits_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.edn_genbits.4167082048
Directory /workspace/99.edn_genbits/latest
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